Display panel and manufacturing method therefor, and display device

Abstract

The present application relates to the technical field of display, and discloses a display panel and a manufacturing method therefor, and a display device. The display panel comprises a base substrate, and a plurality of driving circuits and a plurality of light-emitting units which are located on the base substrate. Moreover, the display panel further comprises a partition structure. A charge generation layer in an organic functional film layer can be partitioned by the partition structure, while a second electrode layer will not be partitioned by the partition structure. Therefore, the display function of the display panel can be ensured, and lateral leakage current can also be avoided, thereby ensuring the display effect.

Description

Display panel and manufacturing method thereof, and display device

[0001] This disclosure claims priority to Chinese patent application No. 202311246978.1 filed on September 25, 2023, entitled “Display panel, method for manufacturing the same, and display device.” The entire contents of the above case are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] Organic light emitting diode (OLED) display panels have been widely used due to their characteristics of self-luminescence, low driving voltage, and fast response.

[0004] Summary of the Invention

[0005] This application provides a display panel, a method for manufacturing the same, and a display device, which can solve the problem of poor display quality of the display panel due to lateral leakage current in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, comprising:

[0007] a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0008] a plurality of light-emitting units, the plurality of light-emitting units being located on one side of the base substrate and in the display area, the plurality of light-emitting units comprising: a first electrode layer, a pixel defining layer, an organic functional film layer, and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer comprising: a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate, the orthographic projection of the protective electrode layer on the base substrate covering the orthographic projection of the target electrode layer on the base substrate, and the organic functional film layer comprising at least a charge generation layer;

[0009] and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and configured to provide a driving signal to the corresponding light-emitting unit;

[0010] In which, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the protective electrode layer at least includes: a first protective pattern and a second protective pattern arranged at a first interval, the pixel defining layer at least includes: a first defining pattern and a second defining pattern arranged at a second interval, the first interval is greater than the second interval, the partition structure includes the first interval and the second interval, the charge generation layer is located in the partition structure and the light-emitting area of ​​the light-emitting unit. The portion of the second electrode layer located in the partition structure and the light-emitting area of ​​the light-emitting unit is disconnected, and the portion of the second electrode layer located in the partition structure and the light-emitting area of ​​the light-emitting unit is continuously arranged.

[0011] Optionally, the display panel further includes: an organic insulating layer and an inorganic protective layer located between the plurality of light-emitting units and the plurality of driving circuits and stacked in a direction away from the base substrate;

[0012] The target electrode layer is connected to the driving circuit through a first via hole in the inorganic protective layer and a second via hole in the organic insulating layer.

[0013] Optionally, the display panel further includes: an organic insulating layer located between the plurality of light-emitting units and the plurality of driving circuits; the first electrode layer further includes: a connecting electrode layer located on a side of the target electrode layer close to the base substrate, the connecting electrode layer being connected to the driving circuit through a second via hole in the organic insulating layer;

[0014] The connecting electrode layer and the protective electrode layer are formed by the same patterning process. The connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern spaced apart at a third interval. The partition structure also includes the third interval.

[0015] Optionally, the connecting electrode layer and the protective electrode layer are made of the same material, and the third interval is equal to the first interval; or,

[0016] The connection electrode layer and the protection electrode layer are made of different materials, and the third interval is not equal to the first interval.

[0017] In another aspect, a display panel is provided, comprising:

[0018] a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0019] a plurality of light-emitting units, the plurality of light-emitting units being located on one side of the base substrate and in the display area, the plurality of light-emitting units comprising: a first electrode layer, a pixel defining layer, an organic functional film layer, and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer comprising: a connecting electrode layer, a target electrode layer, and a protective electrode layer stacked in a direction away from the base substrate, the connecting electrode layer and the protective electrode layer being made of the same material and formed using the same patterning process, the orthographic projection of the protective electrode layer on the base substrate overlapping with the orthographic projection of the connecting electrode layer on the base substrate, and both covering the orthographic projection of the target electrode layer on the base substrate; the organic functional film layer comprising at least a charge generation layer;

[0020] and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and configured to provide a driving signal to the corresponding light-emitting unit;

[0021] In which, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the pixel defining layer includes a first defining layer, a second defining layer and a third defining layer stacked in a direction away from the base substrate, the first defining layer is continuously arranged, the second defining layer at least includes: a third defining pattern and a fourth defining pattern arranged at intervals in a first interval manner, the third defining layer at least includes: a fifth defining pattern and a sixth defining pattern arranged at intervals in a second interval manner, the first interval is larger than the second interval, the partition structure includes the first interval and the second interval, the charge generation layer is located in the portion of the partition structure and the portion located in the light-emitting area of ​​the light-emitting unit, and the second electrode layer is located in the portion of the partition structure and the portion located in the light-emitting area of ​​the light-emitting unit and is continuously arranged.

[0022] Optionally, the display panel further includes: an organic insulating layer located between the plurality of light-emitting units and the plurality of driving circuits;

[0023] The connection electrode layer is connected to the driving circuit through a second via hole in the organic insulating layer.

[0024] In another aspect, a display panel is provided, comprising:

[0025] a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0026] a plurality of light-emitting units, the plurality of light-emitting units being located on one side of the base substrate and in the display area, the plurality of light-emitting units comprising: a first electrode layer, a pixel defining layer, an organic functional film layer, and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer comprising: a connecting electrode layer, a target electrode layer, and a protective electrode layer stacked in a direction away from the base substrate, the orthographic projection of the protective electrode layer on the base substrate and the orthographic projection of the connecting electrode layer on the base substrate both covering the orthographic projection of the target electrode layer on the base substrate, and the organic functional film layer comprising at least a charge generation layer;

[0027] and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and configured to provide a driving signal to the corresponding light-emitting unit;

[0028] In which, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern arranged at a first interval, the protective electrode layer at least includes: a first protective pattern and a second protective pattern arranged at a second interval, the first interval is greater than the second interval, the partition structure includes the first interval and the second interval, the charge generation layer is located in the partition structure and the light-emitting area of ​​the light-emitting unit. The portion, which is disconnected, of the charge generation layer is located in the partition structure and the portion, which is located in the light-emitting area of ​​the light-emitting unit, and the portion, which is continuously arranged, of the second electrode layer is located in the partition structure and the portion, which is located in the light-emitting area of ​​the light-emitting unit.

[0029] Optionally, the connecting electrode layer and the protecting electrode layer are made of different materials, and the connecting electrode layer and the protecting electrode layer are formed by the same patterning process.

[0030] In another aspect, a display panel is provided, comprising:

[0031] a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0032] A plurality of light-emitting units, the plurality of light-emitting units being located on one side of the base substrate and in the display area, the plurality of light-emitting units comprising: a first electrode layer, an organic functional film layer, a pixel defining layer, and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer comprising: a connecting electrode layer, a target electrode layer, and a protective electrode layer stacked in a direction away from the base substrate; the organic functional film layer comprising at least a charge generating layer;

[0033] and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and configured to provide a driving signal to the corresponding light-emitting unit;

[0034] In which, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern arranged at a first interval, the target electrode layer at least includes: a first electrode pattern and a second electrode pattern arranged at a second interval, the first interval is greater than the second interval, the partition structure includes the first interval and the second interval, the protective electrode layer is located in a portion of the partition structure and a portion located in the light-emitting area of ​​the light-emitting unit and is disconnected, the charge generation layer is located in a portion of the partition structure and a portion located in the light-emitting area of ​​the light-emitting unit and is disconnected, and the second electrode layer is located in a portion of the partition structure and a portion located in the light-emitting area of ​​the light-emitting unit and is continuously arranged.

[0035] In another aspect, a display panel is provided, comprising:

[0036] a base substrate, the base substrate having a display area and a peripheral area surrounding the display area;

[0037] A plurality of light-emitting units, the plurality of light-emitting units being located on one side of the base substrate and in the display area, the plurality of light-emitting units comprising: a first electrode layer, an organic functional film layer, a pixel defining layer, and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer comprising: a connecting electrode layer, an inorganic partition layer, a target electrode layer, and a protective electrode layer stacked in a direction away from the base substrate; the organic functional film layer comprising at least a charge generation layer;

[0038] and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and configured to provide a driving signal to the corresponding light-emitting unit;

[0039] In which, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern arranged at a first interval, the inorganic partition layer at least includes: a first insulating pattern and a second insulating pattern arranged at a second interval, the first interval is larger than the second interval, the partition structure includes the first interval and the second interval, the charge generation layer is located in the partition structure and the light-emitting area of ​​the light-emitting unit. The portion, which is disconnected, of the charge generation layer is located in the partition structure and the portion, which is located in the light-emitting area of ​​the light-emitting unit, and the portion, which is continuously arranged, of the second electrode layer is located in the partition structure and the portion, which is located in the light-emitting area of ​​the light-emitting unit.

[0040] Optionally, the target electrode layer, the inorganic partition layer and the connecting electrode layer are formed by a same patterning process;

[0041] The orthographic projection of the target electrode layer on the base substrate overlaps with the orthographic projection of the inorganic partition layer on the base substrate.

[0042] Optionally, the protective electrode layer, the inorganic partition layer and the connecting electrode layer are formed by a same patterning process;

[0043] The protective electrode layer and the connecting electrode layer are made of the same material, and the orthographic projection of the protective electrode layer on the base substrate overlaps with the orthographic projection of the connecting electrode layer on the base substrate; or

[0044] The protective electrode layer and the connecting electrode layer are made of different materials. The protective electrode layer at least includes a first protective pattern and a second protective pattern spaced apart at a fourth interval. The fourth interval is smaller than the first interval and larger than the second interval.

[0045] In another aspect, a display panel is provided, comprising: a base substrate having a display area and a peripheral area surrounding the display area;

[0046] A plurality of light-emitting units, the plurality of light-emitting units being located on one side of the base substrate and in the display area, the plurality of light-emitting units comprising: a first electrode layer, an organic functional film layer, a pixel defining layer, and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer comprising: a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate, the target electrode layer being prepared using a wet etching process; the organic functional film layer comprising at least a charge generation layer;

[0047] and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and configured to provide a driving signal to the corresponding light-emitting unit;

[0048] In which, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the target electrode layer at least includes: a first electrode pattern and a second electrode pattern arranged at a first interval, the protective electrode layer at least includes: a first protective pattern and a second protective pattern arranged at a second interval, the first interval is greater than the second interval, the partition structure includes the first interval and the second interval, the charge generation layer is located in the partition structure and the light-emitting area of ​​the light-emitting unit. The portion of the second electrode layer located in the partition structure and the light-emitting area of ​​the light-emitting unit is disconnected, and the portion of the second electrode layer located in the partition structure and the light-emitting area of ​​the light-emitting unit is continuously arranged.

[0049] In another aspect, a method for preparing a display panel is provided, the method comprising:

[0050] Obtaining a base substrate, wherein the base substrate has a display area and a peripheral area surrounding the display area;

[0051] forming a plurality of driving circuits on one side of the base substrate;

[0052] A plurality of light-emitting units are formed on a side of the plurality of driving units away from the base substrate, the plurality of light-emitting units are located in the display area, the plurality of light-emitting units correspond to the plurality of driving units, and each of the driving circuits is connected to a corresponding light-emitting unit for providing a driving signal to the corresponding light-emitting unit;

[0053] The forming of a plurality of light-emitting units includes:

[0054] forming a connecting electrode film on a side of the plurality of driving circuits away from the base substrate;

[0055] forming a target electrode film on a side of the connecting electrode film away from the base substrate, and patterning the target electrode film to obtain a target electrode layer;

[0056] forming a protective electrode film on a side of the target electrode layer away from the base substrate;

[0057] The protective electrode film is processed using a first etching process to obtain a protective electrode layer, and the connecting electrode film is processed using a second etching process to obtain a connecting electrode layer, wherein the first etching process and the second etching process are performed in the same patterning process; wherein the connecting electrode layer includes at least: a first connecting pattern and a second connecting pattern arranged at a first interval, and the protective electrode layer includes at least: a first protective pattern and a second protective pattern arranged at a second interval, wherein the first interval is greater than the second interval, and the first interval and the second interval constitute a partition structure;

[0058] forming a pixel electrode layer on a side of the protective electrode layer away from the base substrate, wherein a portion of the pixel electrode layer located at the partition structure and a portion located at the light-emitting area of ​​the light-emitting unit are disconnected;

[0059] An organic functional film layer is formed on a side of the pixel electrode layer away from the base substrate, wherein the organic functional film layer includes at least a charge generation layer, and the charge generation layer is disconnected from a portion located in the partition structure and a portion located in the light-emitting area of ​​the light-emitting unit;

[0060] A second electrode layer is formed on a side of the organic functional film layer away from the base substrate, and the second electrode layer is continuously arranged at a portion located at the partition structure and a portion located at the light emitting area of ​​the light emitting unit.

[0061] In another aspect, a display device is provided, comprising: a power supply component and the display panel as described in the above aspect;

[0062] Wherein, the power supply component is used to supply power to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0064] FIG1 is a schematic diagram of the damage thickness of an organic insulating layer provided in an embodiment of the present application;

[0065] FIG2 is a structural flow chart of a conventional method for manufacturing a display panel according to an embodiment of the present application;

[0066] FIG3 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0067] FIG4 is a top view of a substrate provided in an embodiment of the present application;

[0068] FIG5 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0069] FIG6 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0070] FIG7 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0071] FIG8 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0072] FIG9 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0073] FIG10 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0074] FIG11 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0075] FIG12 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0076] FIG13 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0077] FIG14 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application;

[0078] FIG15 is a structural flow chart of some steps in a method for manufacturing a display panel provided in an embodiment of the present application;

[0079] FIG16 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0080] FIG17 is a structural flow chart of some steps in another method for manufacturing a display panel provided in an embodiment of the present application;

[0081] FIG18 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0082] FIG19 is a structural flow chart of some steps in another method for manufacturing a display panel provided in an embodiment of the present application;

[0083] FIG20 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0084] FIG21 is a structural flow chart of some steps in another method for manufacturing a display panel provided in an embodiment of the present application;

[0085] FIG22 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0086] FIG23 is a structural flow chart of some steps in another method for manufacturing a display panel provided in an embodiment of the present application;

[0087] FIG24 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0088] FIG25 is a structural flow chart of some steps in another method for manufacturing a display panel provided in an embodiment of the present application;

[0089] FIG26 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0090] FIG27 is a structural flow chart of some steps in another method for manufacturing a display panel provided in an embodiment of the present application;

[0091] FIG28 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application;

[0092] FIG29 is a structural flow chart of some steps in another method for manufacturing a display panel provided in an embodiment of the present application;

[0093] FIG30 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0094] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0095] In related art, an OLED display panel includes multiple OLED devices, each of which generally includes an anode, an organic functional film layer, and a cathode. The organic functional film layer is capable of emitting light when driven by the anode and cathode. Typically, to increase the brightness and reduce the power consumption of an OLED display panel, multiple OLED devices in the OLED display panel can be connected in series (tandem) via a connecting layer in the organic functional film layer, resulting in a highly efficient OLED device.

[0096] However, the charge-generation layer (CGL) in the connection layer has a high carrier mobility, which may generate a lateral leakage current, resulting in a poor display effect of the display panel.

[0097] In recent years, with the increase in the pixel density (producer price index, PPI) of display products such as virtual reality (VR) and augmented reality (AR), the area of ​​a single pixel unit has become smaller and smaller, which has placed increasingly higher requirements on layout design and process capabilities.

[0098] In the related art, the material of the anode (ANODE, AND) of the existing conventional OLED device is a triple stack of indium tin oxide (ITO), silver (Ag) and ITO (denoted as ITO / Ag / ITO). Among them, the anode pattern is usually formed by etching using a wet process, but because the etching solution of the anode pattern is relatively viscous, the distance between the anode patterns of different pixel units must be designed to be larger to avoid the problem of short-circuiting of the anode patterns of different pixel units due to material residue. In addition, since the wet etching process has a large etching deviation (CD bias) for ITO / Ag / ITO, this will lead to difficulties in the layout design of the anode on the one hand, and on the other hand, it will cause the size of the hollow area of ​​the pixel definition layer to become smaller. This will cause the aperture ratio of the OLED display panel to decrease, affecting the luminous efficiency, and thus increasing the power consumption of the OLED display panel.

[0099] Typically, tandem OLED technology is used to increase the PPI (Pulse Per Inch) brightness and reduce power consumption of OLED display panels. However, the CGL (including n-type and p-type CGL) in tandem OLED technology requires high carrier mobility, which can generate lateral leakage current and affect the luminous efficiency of the display panel.

[0100] Generally speaking, dry etching can reduce the distance between anode patterns and improve the PPI of OLED display panels compared to wet etching. Therefore, dry etching can be used to etch the anode film. However, dry etching of the anode film has the following problems:

[0101] 1. ITO / Ag / ITO is not easily etched by dry etching process, so ITO / Ag / ITO needs to be replaced with other metals such as ITO / Ti / Al / Ti. However, when etching ITO / Ti / Al / Ti, it is easy to cause etching damage to the organic insulating layer (PLN) below, and the damage thickness H1 exceeds 100nm (nanometers), refer to Figure 1. In this case, while isolating the charge generation layer, the cathode layer above the charge generation layer will also be isolated, causing display abnormalities. Therefore, it is necessary to deposit an inorganic protective layer (PVX) between the organic insulating layer and Ti / Al / Ti. In addition, it is necessary to add a patterning process to form vias in the inorganic protective layer to connect Ti / Al / Ti to the driving circuit below.

[0102] 2. Metal aluminum (Al) is easily corroded, and its sidewalls need to be protected by a protective layer. If the ITO / Ti / Al / Ti in the anode layer uses the same patterning process, the Al sidewalls will not be protected by the ITO and are easily corroded, causing display abnormalities. Therefore, it is necessary to use a two-step patterning process for ITO and Ti / Al / Ti. That is, the Ti / Al / Ti pattern is first formed through the first patterning process, and then the ITO pattern is formed through the second patterning process.

[0103] Based on the above analysis, referring to FIG2 , the conventional method requires five patterning processes, and the process is as follows:

[0104] 1. Forming vias in the inorganic protective layer (PVX): An inorganic protective film is formed on the side of the organic insulating layer (PLN) away from the substrate. This film is then patterned to form an inorganic protective layer. The inorganic protective layer has vias that connect the subsequently formed Ti / Al / Ti layers to the signal transmission portion of the driver circuit (located in the second source / drain layer SD2). This inorganic protective layer prevents damage to the organic insulating layer during subsequent dry etching of the Ti / Al / Ti layers.

[0105] 2. Forming a Ti / Al / Ti pattern (as an anode pattern): forming an anode film on the side of the inorganic protective layer away from the base substrate, and treating the anode film with a patterning process to obtain an anode pattern.

[0106] 3. Forming an ITO pattern (serving as a protective pattern for the anode pattern): A protective film is formed on the side of the anode pattern away from the substrate. This protective film is then patterned to form a protective pattern. This protective pattern covers the sidewalls of the anode pattern, preventing corrosion that could cause display anomalies.

[0107] 4. Forming the hollowed-out area of ​​the pixel definition layer: A pixel definition film is formed on the side of the protective pattern away from the substrate. The pixel definition film is processed using a patterning process to obtain the initial pixel definition layer. The pixel definition film comprises three layers of silicon oxide (SiO), silicon nitride (SiN), and silicon oxide (SiO).

[0108] 5. Forming a partition structure: The initial pixel defining layer is processed using a patterning process to obtain a pixel defining layer.

[0109] According to the above conventional process, it can be seen that the conventional process has the following problems:

[0110] 1. Five patterning processes are required, resulting in high manufacturing costs.

[0111] 2. By adjusting the etching conditions so that the etching rate of SiO is lower than that of SiN when etching SiO, an inscribed width w is formed. However, the size of the inscribed width w is difficult to control.

[0112] 3. The SiO in the upper layer of the pixel definition layer plays a role of partition. Since SiO is an inorganic material, it is easy to break when squeezed by the film forming of the organic functional film layer, thereby affecting the partition effect.

[0113] Figure 3 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Referring to Figure 3 , it can be seen that the display panel 10 includes: a base substrate 101, multiple light-emitting units 102, and multiple drive circuits 103. Figure 4 is a top view of a base substrate provided in an embodiment of the present application. Referring to Figure 4 , the base substrate 101 has a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0114] 3 and 4 , multiple light-emitting units 102 are located on one side of a base substrate 101 and in a display area 101a. The multiple light-emitting units 102 include: a first electrode layer 1021, a pixel defining layer 1022, an organic functional film layer (not shown), and a second electrode layer (not shown), stacked sequentially in a direction away from the base substrate 101.

[0115] The first electrode layer 1021 includes a target electrode layer 10211 and a protective electrode layer 10212, stacked in a direction away from the base substrate 101. The orthographic projection of the protective electrode layer 10212 on the base substrate 101 covers the orthographic projection of the target electrode layer 10211 on the base substrate 101, thereby preventing the target electrode layer 10211 from being affected during subsequent processing and ensuring the yield of the target electrode layer 10211. The organic functional film layer includes at least a charge generation layer.

[0116] The plurality of driving circuits 103 are located between the base substrate 101 and the plurality of light-emitting units 102 . Each driving circuit 103 is connected to a corresponding light-emitting unit 102 for providing a driving signal to the corresponding light-emitting unit 102 .

[0117] Referring to FIG. 3 , the display panel 10 further includes a partition structure 10a positioned between the light-emitting areas of any two adjacent light-emitting units 102. The protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced at a first interval h1. The pixel-defining layer 1022 includes at least a first delimiting pattern b1 and a second delimiting pattern b2 spaced at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0118] In the embodiment of the present application, because the second spacing h2 between the first defining pattern b1 and the second defining pattern b2 in the pixel defining layer 1022 is smaller than the first spacing h1 between the first protection pattern a1 and the second protection pattern a2 in the protection electrode layer 10212, the defining pattern of the pixel defining layer 1022 can cover the protection pattern in the protection electrode layer 10212, and the defining pattern has a portion that extends beyond the protection pattern. In other words, the protection electrode layer 10212 can be undercut relative to the pixel defining layer 1022.

[0119] Furthermore, the pixel defining layer 1022 is further away from the substrate 101 than the protective electrode layer 10212. Therefore, the portion of the film subsequently formed on the side of the pixel defining layer 1022 further away from the substrate 101 cannot be sequentially formed along the protective pattern and the pixel pattern, but is instead disconnected at the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the film layer, thereby ensuring luminous efficiency.

[0120] In the embodiment of the present application, under normal circumstances, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less isolated by the partition structure 10a as the distance from the pixel defining layer 1022 increases. Therefore, by adjusting the thickness of the protective electrode layer 10212 and the pixel electrode layer, the isolation effect of the partition structure 10a on the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted.

[0121] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the protective electrode layer 10212 and the pixel defining layer 1022, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0122] For example, the charge generation layer is located in the portion of the partition structure 10a and the portion of the light-emitting area of ​​the light-emitting unit 102 is disconnected, and the second electrode layer is located in the portion of the partition structure 10a and the portion of the light-emitting area of ​​the light-emitting unit 102 is connected.

[0123] Because the charge generation layer can be isolated by the partition structure 10a, even if the charge generation layer has high carrier mobility, no lateral leakage current will be generated between adjacent light-emitting units 102. Furthermore, the second electrode layer can serve as the cathode of the light-emitting unit 102 and is not isolated by the partition structure 10a, thereby ensuring normal display of the light-emitting unit 102.

[0124] In summary, embodiments of the present application provide a display panel comprising a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel further comprises a partition structure, wherein the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures that the display panel not only maintains its display function but also prevents the generation of lateral leakage current, thereby maintaining a good display quality.

[0125] 3 , it can be seen that the display panel 10 further includes an organic insulating layer 104 and an inorganic protective layer 105, which are located between the plurality of light-emitting units 102 and the plurality of driving circuits 103 and are stacked in a direction away from the base substrate 101. The target electrode layer 10211 is connected to the driving circuit 103 via a first via hole in the inorganic protective layer 105 and a second via hole in the organic insulating layer 104.

[0126] Optionally, the preparation process of the target electrode layer 10211 includes: first forming a target electrode film, and then performing a patterning process on the target electrode film to obtain the target electrode layer 10211. The patterning process includes: photoresist coating, exposure, development, etching, and removing the photoresist. The etching process can be a dry etching process.

[0127] Typically, the material of the organic insulating layer 104 is susceptible to dry etching, while the material of the inorganic protective layer 105 is not. Therefore, by providing the inorganic protective layer 105 on the side of the organic insulating layer 104 away from the base substrate 101, over-etching of the organic insulating layer 104 during formation of the target electrode layer 10211 can be avoided, thereby preventing the second electrode layer from being cut off due to the height of the partition structure 10a being too high. In Figure 3, the height of the partition structure 10a can be equal to the total thickness G1 of the protective electrode layer 10212 and the pixel defining layer 1022.

[0128] Figure 5 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to Figure 5 , the display panel further includes an organic insulating layer 104 positioned between the plurality of light-emitting units 102 and the plurality of drive circuits 103. The first electrode layer 1021 further includes a connecting electrode layer 10213 positioned on the side of the target electrode layer 10211 closest to the base substrate 101. The connecting electrode layer 10213 is connected to the drive circuits 103 via second vias in the organic insulating layer 104.

[0129] The connecting electrode layer 10213 and the protective electrode layer 10212 are formed using a single patterning process. The connecting electrode layer 10213 includes at least a first connecting pattern c1 and a second connecting pattern c2 spaced apart by a third interval h3, and the partition structure 10a also includes the third interval h3. In the embodiments of the present application, the single patterning process described below may include a complete set of steps including photoresist coating, exposure, development, etching, and photoresist removal. For the etching process within the same patterning process, different etching conditions may be used based on different film layers.

[0130] Generally, the material of the organic insulating layer 104 will not be affected by the wet etching process. Therefore, when the etching process in the patterning process used to connect the electrode layer 10213 and the protective electrode layer 10212 can be a wet etching process, there is no need to set an inorganic protective layer 105 on the side of the organic insulating layer 104 away from the base substrate 101.

[0131] Optionally, the connection electrode layer 10213 and the protection electrode layer 10212 may be made of the same material. In this case, referring to Figure 5 , the third interval h3 may be equal to the first interval h1. For example, the connection electrode layer 10213 and the protection electrode layer 10212 may both be made of indium tin oxide (ITO).

[0132] Alternatively, the materials of the connecting electrode layer 10213 and the protective electrode layer 10212 can be different. In this case, referring to FIG6 , the third interval h3 is not equal to the first interval h1. For example, the connecting electrode layer 10213 can be made of molybdenum (Mo), and the target electrode layer 10211 can be made of indium tin oxide (ITO). Because the wet etching process has a greater CD bias for molybdenum than for ITO, the connecting electrode layer 10213 can be undercut relative to the protective electrode layer 10212, i.e., the third interval h3 is greater than the first interval h1.

[0133] In the embodiment of the present application, the driving circuit 103 may include a plurality of thin film transistors and at least one storage capacitor. Optionally, the driving circuit 103 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 103 is a 7T1C driving circuit. Alternatively, the driving circuit 103 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 103 and the number of storage capacitors included.

[0134] Each thin film transistor includes a gate, a source, and a drain. The driving circuit 103 includes multiple thin film transistors that are interconnected to achieve the function of driving the light emitting unit 102 to emit light.

[0135] Optionally, the drain of one of the multiple thin-film transistors included in the driving circuit can be connected to the light-emitting unit 102. The driving circuit 103 in Figures 3, 5, and 6 can represent a signal transmission unit included in the driving circuit for transmitting signals. The signal transmission unit can be located in the second source and drain layer of the display panel.

[0136] In summary, embodiments of the present application provide a display panel comprising a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel further comprises a partition structure, wherein the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures that the display panel not only maintains its display function but also prevents the generation of lateral leakage current, thereby maintaining a good display quality.

[0137] FIG7 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG7 , the display panel 10 includes: a base substrate 101, a plurality of light-emitting units 102, and a plurality of driving circuits 103. Referring to FIG2 , the base substrate 101 has a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0138] In conjunction with Figures 1 and 2 , multiple light-emitting units 102 are located on one side of a base substrate 101 and within the display area 101a. The multiple light-emitting units 102 include: a first electrode layer 1021, a pixel-defining layer 1022, an organic functional film layer (not shown), and a second electrode layer (not shown), stacked sequentially away from the base substrate 101. The organic functional film layer includes at least a charge generation layer. The second electrode layer can serve as the cathode of the light-emitting unit 102.

[0139] The first electrode layer 1021 includes: a connecting electrode layer 10213, a target electrode layer 10211, and a protective electrode layer 10212, which are stacked in a direction away from the base substrate 101. The connecting electrode layer 10213 and the protective electrode layer 10212 are made of the same material. For example, the connecting electrode layer 10213 and the protective electrode layer 10212 can both be made of indium tin oxide (ITO). Furthermore, the connecting electrode layer 10213 and the protective electrode layer 10212 can be formed using the same patterning process. This allows the orthographic projection of the protective electrode layer 10212 on the base substrate 101 to overlap with the orthographic projection of the connecting electrode layer 10213 on the base substrate 101.

[0140] Furthermore, the orthographic projection of the protection electrode layer 10212 on the base substrate 101 and the orthographic projection of the connection electrode layer 10213 on the base substrate 101 both cover the orthographic projection of the target electrode layer 10211 on the base substrate 101. Thus, the target electrode layer 10211 can be prevented from being affected during subsequent processing, thereby ensuring the yield of the target electrode layer 10211.

[0141] The plurality of driving circuits 103 are located between the base substrate 101 and the plurality of light-emitting units 102 . Each driving circuit 103 is connected to a corresponding light-emitting unit 102 for providing a driving signal to the corresponding light-emitting unit 102 .

[0142] Referring to Figure 7, the display panel 10 also includes a partition structure 10a located between the light-emitting areas of any two adjacent light-emitting units 102. The pixel-defining layer 1022 includes a first defining layer 10221, a second defining layer 10222, and a third defining layer 10223, stacked in a direction away from the base substrate 101. The first defining layer 10221 is connected, the second defining layer 10222 includes at least a third defining pattern b3 and a fourth defining pattern b4 spaced apart at a first interval h1, and the third defining layer 10223 includes at least a fifth defining pattern b5 and a sixth defining pattern b6 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0143] In the embodiment of the present application, since the second interval h2 between the fifth defining pattern b5 and the sixth defining pattern b6 in the third defining layer 10223 is smaller than the first interval h1 between the third defining pattern b3 and the fourth defining pattern b4 in the second defining layer 10222, the defining pattern of the third defining layer 10223 can cover the defining pattern in the second defining layer 10222, and the defining pattern of the third defining layer 10223 has a portion that exceeds the defining pattern in the second defining layer 10222. In other words, the second defining layer 10222 can form an undercut relative to the third defining layer 10223.

[0144] Furthermore, the third defining layer 10223 is further away from the substrate 101 than the second defining layer 10222. Therefore, the portion of the film subsequently formed on the side of the pixel defining layer 1022 further away from the substrate 101 cannot be formed sequentially along the defining patterns in the third defining layer 10223 and the defining patterns in the second defining layer 10222. Instead, it is disconnected at the partition structure 10a. This prevents lateral leakage current generated by the high carrier mobility of the film layer, thereby ensuring luminous efficiency.

[0145] In the embodiment of the present application, under normal circumstances, the various film layers located on the side of the pixel defining layer 1022 away from the base substrate 101 in the display panel 10 will be less and less isolated by the partition structure 10a as the distance from the pixel defining layer 1022 increases. Therefore, by adjusting the thickness of the second defining layer 10222 and the third defining layer 10223 in the pixel defining layer 1022, the isolation effect of the partition structure 10a on the various film layers located on the side of the pixel defining layer 1022 away from the base substrate 101 in the display panel 10 can be adjusted.

[0146] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the partition structure 10a than the second electrode layer. Thus, by adjusting the thickness of the second defining layer 10222 and the third defining layer 10223, the charge generation layer can be blocked by the partition structure 10a, while the second electrode layer is not blocked by the partition structure 10a.

[0147] For example, the charge generation layer is located in the portion of the partition structure 10a and the portion of the light-emitting area of ​​the light-emitting unit 102 is disconnected, and the second electrode layer is located in the portion of the partition structure 10a and the portion of the light-emitting area of ​​the light-emitting unit 102 is connected.

[0148] Because the charge generation layer can be isolated by the partition structure 10a, even if the charge generation layer has high carrier mobility, no lateral leakage current will be generated between adjacent light-emitting units 102. Furthermore, the second electrode layer is not isolated by the partition structure 10a, thus ensuring normal display of the light-emitting unit 102.

[0149] In an embodiment of the present application, the partition structure 10a formed by the first spacer h1 and the second spacer h2 can be formed by the same patterning process, and only the etching conditions are changed in the middle of the etching process of the patterning process. Optionally, the material of the first defining layer 10221 and the third defining layer 10223 is silicon oxide (SiO), and the material of the second defining layer 10222 is silicon nitride (SiN). Among them, the etching conditions used for etching the third defining layer 10223 to obtain the fifth defining pattern b5 and the sixth defining pattern b6 include a mixed gas of trifluoromethane (CHF3), argon (Ar) and hydrogen (H2), and the etching conditions used for etching the second defining layer 10222 to obtain the third defining pattern b3 and the fourth defining pattern b4 include a mixed gas of sulfur hexafluoride (SF6), oxygen (O2) and helium (He).

[0150] 7 , the display panel 10 further includes an organic insulating layer 104 located between the plurality of light emitting units 102 and the plurality of driving circuits 103 . The connecting electrode layer 10213 is connected to the driving circuit 103 through a second via hole in the organic insulating layer 104 .

[0151] Typically, the material of the organic insulating layer 104 is not affected by the wet etching process. Therefore, if the etching process in the patterning process used for the connecting electrode layer 10213 and the protective electrode layer 10212 can be a wet etching process, there is no need to provide the inorganic protective layer 105 on the side of the organic insulating layer 104 away from the base substrate 101. This avoids the need for an additional patterning process due to the provision of the inorganic protective layer 105, thereby reducing the difficulty in manufacturing the display panel 10.

[0152] In the embodiment of the present application, the driving circuit 103 may include a plurality of thin film transistors and at least one storage capacitor. Optionally, the driving circuit 103 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 103 is a 7T1C driving circuit. Alternatively, the driving circuit 103 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 103 and the number of storage capacitors included.

[0153] Each thin film transistor includes a gate, a source, and a drain. The driving circuit 103 includes multiple thin film transistors that are interconnected to achieve the function of driving the light emitting unit 102 to emit light.

[0154] Optionally, the drain of one of the multiple thin film transistors included in the driving circuit can be connected to the light emitting unit 102. The driving circuit 103 in Figure 7 can represent a signal transmission unit included in the driving circuit for transmitting signals. The signal transmission unit can be located in the second source and drain layer of the display panel.

[0155] In summary, embodiments of the present application provide a display panel comprising a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel further comprises a partition structure, wherein the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures that the display panel not only maintains its display function but also prevents the generation of lateral leakage current, thereby maintaining a good display quality.

[0156] FIG8 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG8 , the display panel 10 includes: a base substrate 101, a plurality of light-emitting units 102, and a plurality of drive circuits 103. Referring to FIG2 , the base substrate 101 has a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0157] 8 and 4 , multiple light-emitting units 102 are located on one side of the base substrate 101 and in the display area 101a. The multiple light-emitting units 102 include: a first electrode layer 1021, a pixel defining layer 1022, an organic functional film layer (not shown), and a second electrode layer (not shown), stacked sequentially in a direction away from the base substrate 101.

[0158] The first electrode layer 1021 includes: a connecting electrode layer 10213, a target electrode layer 10211, and a protective electrode layer 10212, stacked in a direction away from the base substrate 101. The orthographic projection of the protective electrode layer 10212 on the base substrate 101 and the orthographic projection of the connecting electrode layer 10213 on the base substrate 101 both cover the orthographic projection of the target electrode layer 10211 on the base substrate 101, thereby preventing the target electrode layer 10211 from being affected during subsequent processing and ensuring the yield of the target electrode layer 10211. The organic functional film layer includes at least a charge generation layer.

[0159] The plurality of driving circuits 103 are located between the base substrate 101 and the plurality of light-emitting units 102 . Each driving circuit 103 is connected to a corresponding light-emitting unit 102 for providing a driving signal to the corresponding light-emitting unit 102 .

[0160] Referring to Figure 8 , the display panel 10 further includes a partition structure 10a positioned between the light-emitting regions of any two adjacent light-emitting units 102. The connecting electrode layer 10213 includes at least a first connecting pattern c1 and a second connecting pattern c2 spaced at a first interval h1. The protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0161] In the embodiment of the present application, because the second interval h2 between the first protection pattern a1 and the second protection pattern a2 in the protection electrode layer 10212 is smaller than the first interval h1 between the first connection pattern c1 and the second connection pattern c2 in the connection electrode layer 10213, the protection pattern of the protection electrode layer 10212 can cover the connection pattern in the connection electrode layer 10213, and the protection pattern has a portion that extends beyond the connection pattern. In other words, the connection electrode layer 10213 can be undercut relative to the protection electrode layer 10212.

[0162] Furthermore, the protective electrode layer 10212 is further away from the base substrate 101 than the connecting electrode layer 10213. Therefore, the portion of the film subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 cannot be sequentially formed along the protective pattern and the connecting pattern, but is instead disconnected at the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the film layer, thereby ensuring luminous efficiency.

[0163] In the embodiment of the present application, under normal circumstances, the film layers on the side of the pixel defining layer 1022 in the display panel 10 that is away from the base substrate 101 will be less and less isolated by the partition structure 10a as the distance from the pixel defining layer 1022 increases. Therefore, by adjusting the thickness of the protective electrode layer 10212 and the connecting electrode layer 10213, the isolation effect of the partition structure 10a on the film layers on the side of the pixel defining layer 1022 in the display panel 10 that is away from the base substrate 101 can be adjusted.

[0164] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the protective electrode layer 10212 and the connecting electrode layer 10213, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0165] For example, the charge generation layer is located in a portion of the partition structure 10a and is disconnected from the portion of the light-emitting region of the light-emitting unit 102, and the second electrode layer is located in a portion of the partition structure 10a and is connected to the portion of the light-emitting region of the light-emitting unit 102. The second electrode layer can be the cathode of the light-emitting unit 102.

[0166] Because the charge generation layer can be isolated by the partition structure 10a, even if the charge generation layer has high carrier mobility, no lateral leakage current will be generated between adjacent light-emitting units 102. Furthermore, the second electrode layer is not isolated by the partition structure 10a, thus ensuring normal display of the light-emitting unit 102.

[0167] In an embodiment of the present application, the materials of the connecting electrode layer 10213 and the protective electrode layer 10212 are different, and the connecting electrode layer 10213 and the protective electrode layer 10212 are formed using the same patterning process, and the etching conditions can be changed in the middle of the etching process of the patterning process.

[0168] Optionally, the material of the connecting electrode layer 10213 may be molybdenum (Mo), and the material of the protective electrode layer 10212 may be indium tin oxide (ITO). The etching process for the protective electrode layer 10212 and the etching process for the connecting electrode layer 10213 may be a wet etching process. The inset of the connecting electrode layer 10213 relative to the protective electrode layer 10212 is formed based on the fact that the etching deviation (CD bias) of the wet etching process for Mo is greater than the etching deviation of the wet etching process for ITO.

[0169] For example, the etching conditions used for etching the protective electrode layer 10212 to obtain the first protective pattern a1 and the second protective pattern a2 include sulfuric acid (H2SO4), and the etching conditions used for etching the connecting electrode layer 10213 to obtain the first connecting pattern c1 and the second connecting pattern c2 include a mixed solution of nitric acid (HNO3), phosphoric acid (H3PO4) and acetic acid (CH3COOH).

[0170] Moreover, since the material of the upper film layer (protective electrode layer 10212) of the partition structure 10a is metal material rather than inorganic material, the protective electrode layer 10212 is not easy to break and can better withstand the extrusion of the organic functional film layer, which can enable the partition structure 10a to play a better partitioning role.

[0171] 8 , the display panel 10 further includes an organic insulating layer 104 located between the plurality of light emitting units 102 and the plurality of driving circuits 103 . The connecting electrode layer 10213 is connected to the driving circuit 103 through a second via hole in the organic insulating layer 104 .

[0172] Typically, the material of the organic insulating layer 104 is not affected by the wet etching process. Therefore, if the etching process in the patterning process used for the connecting electrode layer 10213 can be a wet etching process, there is no need to provide the inorganic protective layer 105 on the side of the organic insulating layer 104 away from the base substrate 101. This avoids the need for an additional patterning process due to the provision of the inorganic protective layer 105, thereby reducing the difficulty in manufacturing the display panel 10.

[0173] Furthermore, since the material of the organic insulating layer 104 is not affected by the wet etching process, when the connecting electrode layer 10213 is formed by the wet etching process, the organic insulating layer 104 will not be over-etched, thereby ensuring that the height of the partition structure 10a is stable and controllable.

[0174] In the embodiment of the present application, the driving circuit 103 may include a plurality of thin film transistors and at least one storage capacitor. Optionally, the driving circuit 103 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 103 is a 7T1C driving circuit. Alternatively, the driving circuit 103 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 103 and the number of storage capacitors included.

[0175] Each thin film transistor includes a gate, a source, and a drain. The driving circuit 103 includes multiple thin film transistors that are interconnected to achieve the function of driving the light emitting unit 102 to emit light.

[0176] Optionally, the drain of one of the multiple thin film transistors included in the driving circuit can be connected to the light emitting unit 102. The driving circuit 103 in Figure 8 can represent a signal transmission unit included in the driving circuit for transmitting signals. The signal transmission unit can be located in the second source and drain layer of the display panel.

[0177] In summary, embodiments of the present application provide a display panel comprising a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel further comprises a partition structure, wherein the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures that the display panel not only maintains its display function but also prevents the generation of lateral leakage current, thereby maintaining a good display quality.

[0178] FIG9 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG9 , the display panel 10 includes: a base substrate 101, a plurality of light-emitting units 102, and a plurality of drive circuits 103. Referring to FIG4 , the base substrate 101 includes a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0179] 9 and 4 , multiple light-emitting units 102 are located on one side of the base substrate 101 and in the display area 101a. The multiple light-emitting units 102 include: a first electrode layer 1021, a pixel defining layer 1022, an organic functional film layer (not shown), and a second electrode layer (not shown), stacked sequentially in a direction away from the base substrate 101.

[0180] The first electrode layer 1021 includes: a connection electrode layer 10213, a target electrode layer 10211, and a protection electrode layer 10212 stacked in a direction away from the base substrate 101. The organic functional film layer includes at least a charge generation layer.

[0181] The plurality of driving circuits 103 are located between the base substrate 101 and the plurality of light-emitting units 102 . Each driving circuit 103 is connected to a corresponding light-emitting unit 102 for providing a driving signal to the corresponding light-emitting unit 102 .

[0182] Referring to Figure 9 , the display panel 10 further includes a partition structure 10a positioned between the light-emitting areas of any two adjacent light-emitting units 102. The connection electrode layer 10213 includes at least a first connection pattern c1 and a second connection pattern c2 spaced at a first interval h1. The target electrode layer 10211 includes at least a first electrode pattern d1 and a second electrode pattern d2 spaced at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0183] In the embodiment of the present application, because the second interval h2 between the first electrode pattern d1 and the second electrode pattern d2 in the target electrode layer 10211 is smaller than the first interval h1 between the first connection pattern c1 and the second connection pattern c2 in the connection electrode layer 10213, the electrode pattern of the target electrode layer 10211 can overlap the connection pattern in the connection electrode layer 10213, and the electrode pattern has a portion that extends beyond the connection pattern. In other words, the connection electrode layer 10213 can be undercut relative to the target electrode layer 10211.

[0184] Furthermore, the target electrode layer 10211 is further away from the base substrate 101 than the connection electrode layer 10213. Therefore, the portion of the film subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 cannot be sequentially formed along the protective pattern and the connection pattern, but is instead disconnected at the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the film layer, thereby ensuring luminous efficiency.

[0185] In the embodiment of the present application, under normal circumstances, the film layers located on the side of the pixel defining layer 1022 away from the base substrate 101 in the display panel 10 will be less and less isolated by the partition structure 10a as the distance from the pixel defining layer 1022 increases. Therefore, by adjusting the thickness of the target electrode layer 10211 and the connecting electrode layer 10213, the isolation effect of the partition structure 10a on the film layers located on the side of the pixel defining layer 1022 away from the base substrate 101 in the display panel 10 can be adjusted.

[0186] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the target electrode layer 10211 and the connecting electrode layer 10213, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0187] For example, the charge generation layer is located in the portion of the partition structure 10a and the portion of the light-emitting area of ​​the light-emitting unit 102 is disconnected, and the second electrode layer is located in the portion of the partition structure 10a and the portion of the light-emitting area of ​​the light-emitting unit 102 is connected.

[0188] Because the charge generation layer can be isolated by the isolation structure 10a, even if the charge generation layer has high carrier mobility, no lateral leakage current will be generated between adjacent light-emitting units 102. Furthermore, the second electrode layer is not isolated by the isolation structure 10a, thereby ensuring normal display of the light-emitting unit 102. The second electrode layer serves as the cathode of the light-emitting unit 102.

[0189] In addition, since the protective electrode layer 10212 is located on the side of the partition structure 10a away from the base substrate 101, the protective electrode layer 10212 is also isolated by the partition structure 10a. Optionally, the portion of the protective electrode layer 10212 located on the partition structure 10a and the portion located in the light-emitting area of ​​the light-emitting unit 102 are disconnected.

[0190] In an embodiment of the present application, the materials of the connecting electrode layer 10213 and the target electrode layer 10211 are different, and the connecting electrode layer 10213 and the protective electrode layer 10212 are formed using the same patterning process, and the etching conditions can be changed in the middle of the etching process of the patterning process.

[0191] Optionally, the material of the connecting electrode layer 10213 may be indium tin oxide (ITO), and the material of the target electrode layer 10211 may be a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (denoted as Ti / Al / Ti). The etching process performed on the target electrode layer 10211 may be a dry etching process, and the etching process performed on the connecting electrode layer 10213 may be a wet etching process. The indentation of the connecting electrode layer 10213 relative to the target electrode layer 10211 may be formed based on the fact that the etching deviation (CD bias) of the wet etching process for ITO is greater than the etching deviation of the dry etching process for Ti / Al / Ti.

[0192] For example, the etching conditions used for etching the target electrode layer 10211 to obtain the first electrode pattern d1 and the second electrode pattern d2 include chlorine (Cl2), and the etching conditions used for etching the connection electrode layer 10213 to obtain the first connection pattern c1 and the second connection pattern c2 include H2SO4.

[0193] Moreover, since the material of the upper film layer (protective electrode layer 10212) of the partition structure 10a is metal material rather than inorganic material, the protective electrode layer 10212 is not easy to break and can better withstand the extrusion of the organic functional film layer, which can enable the partition structure 10a to play a better partitioning role.

[0194] 9 , the display panel 10 further includes an organic insulating layer 104 located between the plurality of light emitting units 102 and the plurality of driving circuits 103 . The connecting electrode layer 10213 is connected to the driving circuit 103 through a second via hole in the organic insulating layer 104 .

[0195] Typically, the material of the organic insulating layer 104 is not affected by the wet etching process. Therefore, if the etching process in the patterning process used for the connecting electrode layer 10213 can be a wet etching process, there is no need to provide the inorganic protective layer 105 on the side of the organic insulating layer 104 away from the base substrate 101. This avoids the need for an additional patterning process due to the provision of the inorganic protective layer 105, thereby reducing the difficulty in manufacturing the display panel 10.

[0196] Furthermore, since the material of the organic insulating layer 104 is not affected by the wet etching process, when the connecting electrode layer 10213 is formed by the wet etching process, the organic insulating layer 104 will not be over-etched, thereby ensuring that the height of the partition structure 10a is stable and controllable.

[0197] In the embodiment of the present application, the driving circuit 103 may include a plurality of thin film transistors and at least one storage capacitor. Optionally, the driving circuit 103 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 103 is a 7T1C driving circuit. Alternatively, the driving circuit 103 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 103 and the number of storage capacitors included.

[0198] Each thin film transistor includes a gate, a source, and a drain. The driving circuit 103 includes multiple thin film transistors that are interconnected to achieve the function of driving the light emitting unit 102 to emit light.

[0199] Optionally, the drain of one of the multiple thin film transistors included in the driving circuit can be connected to the light emitting unit 102. The driving circuit 103 in Figure 9 can represent a signal transmission unit included in the driving circuit for transmitting signals. The signal transmission unit can be located in the second source and drain layer of the display panel.

[0200] In summary, embodiments of the present application provide a display panel comprising a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel further comprises a partition structure, wherein the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures that the display panel not only maintains its display function but also prevents the generation of lateral leakage current, thereby maintaining a good display quality.

[0201] FIG10 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG10 , the display panel 10 includes: a base substrate 101, a plurality of light-emitting units 102, and a plurality of drive circuits 103. Referring to FIG4 , the base substrate 101 includes a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0202] In conjunction with Figure 10 and Figure 4 , multiple light-emitting units 102 are located on one side of the base substrate 101 and in the display area 101a. The multiple light-emitting units 102 include: a first electrode layer 1021, a pixel defining layer 1022, an organic functional film layer (not shown), and a second electrode layer (not shown) stacked sequentially in a direction away from the base substrate 101.

[0203] The first electrode layer 1021 includes: a connecting electrode layer 10213, an inorganic barrier layer 10214, a target electrode layer 10211, and a protective electrode layer 10212 stacked in a direction away from the base substrate 101. The organic functional film layer includes at least a charge generation layer.

[0204] The plurality of driving circuits 103 are located between the base substrate 101 and the plurality of light-emitting units 102 . Each driving circuit 103 is connected to a corresponding light-emitting unit 102 for providing a driving signal to the corresponding light-emitting unit 102 .

[0205] Referring to Figure 10 , the display panel 10 further includes a partition structure 10a positioned between the light-emitting regions of any two adjacent light-emitting units 102. The connecting electrode layer 10213 includes at least a first connecting pattern c1 and a second connecting pattern c2 spaced at a first interval h1. The inorganic partition layer 10214 includes at least a first insulating pattern e1 and a second insulating pattern e2 spaced at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0206] In the embodiment of the present application, because the second spacing h2 between the first insulating pattern e1 and the second insulating pattern e2 in the inorganic barrier layer 10214 is smaller than the first spacing h1 between the first connecting pattern c1 and the second connecting pattern c2 in the connecting electrode layer 10213, the insulating pattern of the inorganic barrier layer 10214 can cover the connecting pattern in the connecting electrode layer 10213, and the insulating pattern has a portion that extends beyond the connecting pattern. In other words, the connecting electrode layer 10213 can be undercut relative to the inorganic barrier layer 10214.

[0207] Furthermore, the inorganic barrier layer 10214 is further away from the base substrate 101 than the connecting electrode layer 10213. Therefore, the portion of the film subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 cannot be sequentially formed along the protective pattern and the connecting pattern, but instead is disconnected at the barrier structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the film layer, thereby ensuring luminous efficiency.

[0208] In the embodiment of the present application, under normal circumstances, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less isolated by the partition structure 10a as the distance from the pixel defining layer 1022 increases. Therefore, by adjusting the thickness of the inorganic partition layer 10214 and the connecting electrode layer 10213, the partition structure 10a can be used to adjust the isolation effect of the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101.

[0209] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the partition structure 10a than the second electrode layer. Thus, by adjusting the thickness of the inorganic partition layer 10214 and the connecting electrode layer 10213, the charge generation layer can be blocked by the partition structure 10a, while the second electrode layer is not blocked by the partition structure 10a.

[0210] For example, the charge generation layer is located in the portion of the partition structure 10a and the portion of the light-emitting region of the light-emitting unit 102, and the second electrode layer is located in the portion of the partition structure 10a and the portion of the light-emitting region of the light-emitting unit 102, and is connected. The second electrode layer serves as the cathode of the light-emitting unit 102.

[0211] Because the charge generation layer can be isolated by the partition structure 10a, even if the charge generation layer has high carrier mobility, no lateral leakage current will be generated between adjacent light-emitting units 102. Furthermore, the second electrode layer is not isolated by the partition structure 10a, thus ensuring normal display of the light-emitting unit 102.

[0212] As a possible scenario, the protective electrode layer 10212, the inorganic barrier layer 10214, and the connecting electrode layer 10213 are formed by the same patterning process. In addition, the etching conditions can be changed in the middle of the etching process of the patterning process.

[0213] Optionally, the protective electrode layer 10212 and the connecting electrode layer 10213 may be made of the same material. For example, the protective electrode layer 10212 and the connecting electrode layer 10213 may be made of indium tin oxide (ITO). Furthermore, referring to FIG. 10 , the inorganic barrier layer 10214 may be made of silicon oxide (SiO) or silicon nitride (SiN). In this case, the orthographic projection of the protective electrode layer 10212 on the base substrate 101 overlaps with the orthographic projection of the connecting electrode layer 10213 on the base substrate 101.

[0214] The etching process for the target electrode layer 10211 can be a dry etching process or a wet etching process; the etching process for the inorganic barrier layer 10214 can be a dry etching process; and the etching process for the connection electrode layer 10213 can be a wet etching process. The undercutting of the connection electrode layer 10213 relative to the inorganic barrier layer 10214 can be achieved based on the fact that the etching bias (CD bias) of the wet etching process for ITO is greater than the etching bias of the dry etching process for SiO or SiN.

[0215] For example, the etching conditions used for etching the inorganic barrier layer 10214 to form the first insulating pattern e1 and the second insulating pattern e2 include a mixed gas of trifluoromethane (CHF3), argon (Ar), and hydrogen (H2). The etching conditions used for etching the connecting electrode layer 10213 to form the first connecting pattern c1 and the second connecting pattern c2 include H2SO4.

[0216] Alternatively, the materials of the protective electrode layer 10212 and the connecting electrode layer 10213 are different. For example, the material of the protective electrode layer 10212 is indium tin oxide (ITO), and the material of the connecting electrode layer 10213 is molybdenum (Mo). Alternatively, the material of the inorganic barrier layer 10214 may be silicon oxide (SiO). In this case, referring to FIG. 11 , the protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced apart at a fourth interval h4, where the fourth interval h4 is smaller than the first interval h1 and larger than the second interval h2.

[0217] Among them, the etching process performed on the target electrode layer 10211 can be a dry etching process or a wet etching process; the etching process performed on the inorganic barrier layer 10214 can be a dry etching process; and the etching process performed on the connecting electrode layer 10213 can be a wet etching process. The inner etching of the connecting electrode layer 10213 relative to the inorganic barrier layer 10214 can be formed based on the fact that the etching deviation (CD bias) of the wet etching process on Mo is greater than the etching deviation (CD bias) of the dry etching process on SiO or SiN. Moreover, the inner etching of the connecting electrode layer 10213 relative to the protective electrode layer 10212 can be formed based on the fact that the etching deviation (CD bias) of the wet etching process on Mo is greater than the etching deviation (CD bias) of the dry etching process (or wet etching process) on ITO.

[0218] For example, the etching conditions used to etch the inorganic barrier layer 10214 to obtain the first insulating pattern e1 and the second insulating pattern e2 include CHF3 / Ar / H2. The etching conditions used to etch the connecting electrode layer 10213 to obtain the first connecting pattern c1 and the second connecting pattern c2 include a mixed solution of HNO3, H3PO4 and CH3COOH.

[0219] As another possible scenario, the target electrode layer 10211, the inorganic partition layer 10214, and the connecting electrode layer 10213 are formed by the same patterning process. In addition, the etching conditions can be changed in the middle of the etching process of the patterning process.

[0220] Alternatively, the connecting electrode layer 10213 may be made of indium tin oxide (ITO), the inorganic barrier layer 10214 may be made of silicon oxide (SiO) or silicon nitride (SiN), and the target electrode layer 10211 may be made of a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (denoted as Ti / Al / Ti). In this case, referring to FIG. 12 , the orthographic projection of the target electrode layer 10211 on the base substrate 101 overlaps with the orthographic projection of the inorganic barrier layer 10214 on the base substrate 101.

[0221] The etching process for the target electrode layer 10211 and the inorganic barrier layer 10214 can be a dry etching process, and the etching process for the connection electrode layer 10213 can be a wet etching process. The undercutting of the connection electrode layer 10213 relative to the inorganic barrier layer 10214 and the target electrode layer 10211 can be formed based on the fact that the etching bias (CD bias) of the wet etching process for ITO is greater than the etching bias of the dry etching process for SiO or SiN and Ti / Al / Ti.

[0222] For example, the etching conditions used for etching the inorganic barrier layer 10214 to obtain the first insulating pattern e1 and the second insulating pattern e2 include CHF3 / Ar / H2, and the etching conditions used for etching the connecting electrode layer 10213 to obtain the first connecting pattern c1 and the second connecting pattern c2 include H2SO4.

[0223] In the embodiment of the present application, since the protective electrode layer 10212 is located on the side of the partition structure 10a away from the base substrate 101, the protective electrode layer 10212 is also isolated by the partition structure 10a. Optionally, the portion of the protective electrode layer 10212 located on the partition structure 10a and the portion located in the light-emitting area of ​​the light-emitting unit 102 are disconnected.

[0224] 10 to 12 , it can be seen that the display panel 10 further includes an organic insulating layer 104 located between the plurality of light-emitting units 102 and the plurality of driving circuits 103 . The connecting electrode layer 10213 is connected to the driving circuit 103 through a second via hole in the organic insulating layer 104 .

[0225] Typically, the material of the organic insulating layer 104 is not affected by the wet etching process. Therefore, if the etching process in the patterning process used for the connecting electrode layer 10213 can be a wet etching process, there is no need to provide the inorganic protective layer 105 on the side of the organic insulating layer 104 away from the base substrate 101. This avoids the need for an additional patterning process due to the provision of the inorganic protective layer 105, thereby reducing the difficulty in manufacturing the display panel 10.

[0226] Furthermore, since the material of the organic insulating layer 104 is not affected by the wet etching process, when the connecting electrode layer 10213 is formed by the wet etching process, the organic insulating layer 104 will not be over-etched, thereby ensuring that the height of the partition structure 10a is stable and controllable.

[0227] In the embodiment of the present application, the driving circuit 103 may include a plurality of thin film transistors and at least one storage capacitor. Optionally, the driving circuit 103 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 103 is a 7T1C driving circuit. Alternatively, the driving circuit 103 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 103 and the number of storage capacitors included.

[0228] Each thin film transistor includes a gate, a source, and a drain. The driving circuit 103 includes multiple thin film transistors that are interconnected to achieve the function of driving the light emitting unit 102 to emit light.

[0229] Optionally, the drain of one of the multiple thin-film transistors included in the driving circuit can be connected to the light-emitting unit 102. The driving circuit 103 in Figures 10 to 12 can represent a signal transmission unit included in the driving circuit for transmitting signals. The signal transmission unit can be located in the second source and drain layer of the display panel.

[0230] In summary, embodiments of the present application provide a display panel comprising a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel further comprises a partition structure, wherein the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures that the display panel not only maintains its display function but also prevents the generation of lateral leakage current, thereby maintaining a good display quality.

[0231] FIG13 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Referring to FIG13 , the display panel 10 includes: a base substrate 101, a plurality of light-emitting units 102, and a plurality of drive circuits 103. Referring to FIG4 , the base substrate 101 has a display area 101a and a peripheral area 101b surrounding the display area 101a.

[0232] 13 and 4 , multiple light-emitting units 102 are located on one side of a base substrate 101 and in a display area 101a. The multiple light-emitting units 102 include: a first electrode layer 1021, a pixel defining layer 1022, an organic functional film layer (not shown), and a second electrode layer (not shown), stacked sequentially in a direction away from the base substrate 101.

[0233] The first electrode layer 1021 includes a target electrode layer 10211 and a protective electrode layer 10212 stacked in a direction away from the base substrate 101. The target electrode layer 10211 can be prepared by a wet etching process. The organic functional film layer includes at least a charge generation layer.

[0234] The plurality of driving circuits 103 are located between the base substrate 101 and the plurality of light-emitting units 102 . Each driving circuit 103 is connected to a corresponding light-emitting unit 102 for providing a driving signal to the corresponding light-emitting unit 102 .

[0235] Referring to FIG. 13 , the display panel 10 further includes a partition structure 10a positioned between the light-emitting areas of any two adjacent light-emitting units 102. The target electrode layer 10211 includes at least a first electrode pattern d1 and a second electrode pattern d2 spaced apart at a first interval h1. The protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0236] In the embodiment of the present application, because the second gap h2 between the first protection pattern a1 and the second protection pattern a2 in the protection electrode layer 10212 is smaller than the first gap h1 between the first electrode pattern d1 and the second electrode pattern d2 in the target electrode layer 10211, the protection pattern of the protection electrode layer 10212 can cover the electrode pattern in the target electrode layer 10211, and the protection pattern has a portion that extends beyond the electrode pattern. In other words, the target electrode layer 10211 can be undercut relative to the protection electrode layer 10212.

[0237] Furthermore, the protective electrode layer 10212 is further away from the base substrate 101 than the target electrode layer 10211. Therefore, the portion of the film subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 cannot be sequentially formed along the protective pattern and the electrode pattern, but is instead disconnected at the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the film layer, thereby ensuring luminous efficiency.

[0238] In the embodiment of the present application, under normal circumstances, the various film layers located on the side of the pixel defining layer 1022 away from the base substrate 101 in the display panel 10 will be less and less isolated by the partition structure 10a as the distance from the pixel defining layer 1022 increases. Therefore, the thickness of the protective electrode layer 10212 and the target electrode layer 10211 can be adjusted to further adjust the isolation effect of the partition structure 10a on the various film layers located on the side of the pixel defining layer 1022 away from the base substrate 101 in the display panel 10.

[0239] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the target electrode layer 10211 and the protective electrode layer 10212, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0240] For example, the charge generation layer is located in the portion of the partition structure 10a and the portion of the light-emitting region of the light-emitting unit 102, and the second electrode layer is located in the portion of the partition structure 10a and the portion of the light-emitting region of the light-emitting unit 102, and is connected. The second electrode layer serves as the cathode of the light-emitting unit 102.

[0241] Because the charge generation layer can be isolated by the partition structure 10a, even if the charge generation layer has high carrier mobility, no lateral leakage current will be generated between adjacent light-emitting units 102. Furthermore, the second electrode layer is not isolated by the partition structure 10a, thus ensuring normal display of the light-emitting unit 102.

[0242] In an embodiment of the present application, the target electrode layer 10211 and the protective electrode layer 10212 are formed using the same patterning process, and the etching conditions can be changed in the middle of the etching process of the patterning process.

[0243] Optionally, the material of the target electrode layer 10211 may be a three-layer structure of molybdenum (Mo), aluminum (Al), and molybdenum (Mo) (denoted as Mo / Al / Mo), and the material of the protective electrode layer 10212 may be indium tin oxide (ITO). The etching process performed on the protective electrode layer 10212 may be a dry etching process or a wet etching process, and the etching process performed on the target electrode layer 10211 may be a wet etching process. The indentation of the target electrode layer 10211 relative to the protective electrode layer 10212 may be formed based on the fact that the etching deviation (CD bias) of the wet etching process for Mo / Al / Mo is greater than the etching deviation of the dry etching process (or wet etching process) for ITO.

[0244] For example, the etching conditions used to etch the protective electrode layer 10212 to obtain the first protective pattern a1 and the second protective pattern a2 include H2SO4, and the etching conditions used to etch the target electrode layer 10211 to obtain the first electrode pattern d1 and the second electrode pattern d2 include a mixed solution of HNO3, H3PO4 and CH3COOH.

[0245] Moreover, since the material of the upper film layer (protective electrode layer 10212) of the partition structure 10a is metal material rather than inorganic material, the protective electrode layer 10212 is not easy to break and can better withstand the extrusion of the organic functional film layer, which can enable the partition structure 10a to play a better partitioning role.

[0246] 13 , it can be seen that the display panel 10 further includes an organic insulating layer 104 located between the plurality of light emitting units 102 and the plurality of driving circuits 103 . The connecting electrode layer 10213 is connected to the driving circuit 103 through a second via hole in the organic insulating layer 104 .

[0247] Typically, the material of the organic insulating layer 104 is not affected by the wet etching process. Therefore, if the etching process in the patterning process used for the connecting electrode layer 10213 can be a wet etching process, there is no need to provide the inorganic protective layer 105 on the side of the organic insulating layer 104 away from the base substrate 101. This avoids the need for an additional patterning process due to the provision of the inorganic protective layer 105, thereby reducing the difficulty in manufacturing the display panel 10.

[0248] Furthermore, since the material of the organic insulating layer 104 is not affected by the wet etching process, when the target electrode layer 10211 is formed by the wet etching process, the organic insulating layer 104 will not be over-etched, thereby ensuring that the height of the partition structure 10a is stable and controllable.

[0249] In the embodiment of the present application, the driving circuit 103 may include a plurality of thin film transistors and at least one storage capacitor. Optionally, the driving circuit 103 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 103 is a 7T1C driving circuit. Alternatively, the driving circuit 103 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 103 and the number of storage capacitors included.

[0250] Each thin film transistor includes a gate, a source, and a drain. The driving circuit 103 includes multiple thin film transistors that are interconnected to achieve the function of driving the light emitting unit 102 to emit light.

[0251] Optionally, the drain of one of the multiple thin film transistors included in the driving circuit can be connected to the light emitting unit 102. The driving circuit 103 in Figure 13 can represent a signal transmission unit included in the driving circuit for transmitting signals. The signal transmission unit can be located in the second source and drain layer of the display panel.

[0252] In summary, embodiments of the present application provide a display panel comprising a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel further comprises a partition structure, wherein the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures that the display panel not only maintains its display function but also prevents the generation of lateral leakage current, thereby maintaining a good display quality.

[0253] FIG14 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present application. Referring to FIG14 , the method includes:

[0254] Step S101: Obtain a base substrate.

[0255] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0256] Step S102 : forming a plurality of driving circuits on one side of the base substrate.

[0257] In the embodiment of the present application, the driving circuit 103 may include a plurality of thin film transistors and at least one storage capacitor. Optionally, the driving circuit 103 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 103 is a 7T1C driving circuit. Alternatively, the driving circuit 103 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 103 and the number of storage capacitors included.

[0258] The film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0259] Step S103 : forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0260] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0261] Optionally, the organic insulating layer 104 includes a second via hole, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via hole to achieve transmission of the driving signal.

[0262] Step S104 : forming an inorganic protective layer on a side of the organic insulating layer away from the base substrate.

[0263] In the embodiment of the present application, the process of forming the inorganic protective layer 105 may include: forming an inorganic protective film on the side of the organic insulating layer 104 away from the base substrate 101; and treating the inorganic protective film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0264] 15 , the inorganic protective layer 105 includes a first via K1, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the first via K1 to achieve transmission of driving signals.

[0265] Step S105 : forming a plurality of light-emitting units on a side of the inorganic protective layer away from the base substrate.

[0266] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0267] 14 , the process of forming a plurality of light emitting units 102 includes:

[0268] Step S1051 : forming a target electrode thin film on a side of the inorganic protective layer away from the base substrate, and processing the target electrode thin film using a patterning process to obtain a target electrode layer.

[0269] In the embodiment of the present application, the material of the target electrode film can be a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (represented as Ti / Al / Ti). The etching process in the patterning process can be a dry etching process, and the dry etching process can use Cl2.

[0270] 15 , the target electrode layer 10211 includes a plurality of electrode patterns, each of which can be used to form an anode of a light-emitting unit 102. Furthermore, each electrode pattern can be connected to the driving circuit 103 via a first via K1 and a second via K2 to receive a driving signal provided by the driving circuit 103.

[0271] Step S1052 : forming a protective electrode film and a pixel defining film on a side of the target electrode layer away from the base substrate, and processing the pixel defining film using a patterning process to obtain an initial pixel defining layer.

[0272] In the embodiment of the present application, the initial pixel defining layer 1022a includes a plurality of hollow regions, each of which is used to expose an electrode pattern so as to facilitate contact between the subsequently formed organic functional film layer and the electrode pattern, thereby realizing a display function.

[0273] Optionally, the material of the protective electrode film may be indium tin oxide (ITO). The pixel defining film may include a first thin film layer, a second thin film layer, and a third thin film layer stacked in sequence. The materials of the first thin film layer and the third thin film layer may be silicon oxide (SiO), and the material of the second thin film layer may be silicon nitride (SiN). Alternatively, the pixel defining film may include a thin film layer whose material is silicon oxide (SiO), or a thin film layer whose material is silicon nitride (SiN). The embodiments of the present application do not limit the specific structure and material of the pixel defining film.

[0274] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0275] Step S1053 : Processing the initial pixel definition layer and the protective electrode film using a patterning process to obtain a pixel definition layer and a protective electrode layer.

[0276] In the embodiment of the present application, the initial pixel defining layer 1022 a and the protective electrode film are processed using the same patterning process, and the etching conditions can be changed in the middle of the etching process of the patterning process.

[0277] Optionally, a mixture of CHF3, Ar, and H2 can be used to etch the initial pixel defining layer 1022a, and H2SO4 can be used to etch the protective electrode film. Because the etching bias (CD bias) of the protective electrode film (ITO) is greater than the etching bias of the initial pixel defining layer 1022a (SiO / SiN / SiO), the resulting protective electrode layer 10212 is undercut relative to the pixel defining layer 1022.

[0278] Referring to FIG. 15 , the protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced apart at a first interval h1. The pixel defining layer 1022 includes at least a first defining pattern b1 and a second defining pattern b2 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the first and second intervals h1 and h2 may form a partition structure 10a.

[0279] Step S1054 : forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0280] In the embodiment of the present application, the organic functional film layer includes at least a charge generation layer. The charge generation layer has a high carrier mobility, so the charge generation layer needs to be isolated.

[0281] Because the pixel defining layer 1022 is further away from the substrate 101 than the protective electrode layer 10212, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 further away from the substrate 101 cannot be sequentially formed along the protective pattern and the pixel pattern. Instead, it is disconnected at the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0282] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the partition structure 10a. Therefore, by adjusting the thickness of the protective electrode layer 10212 and the pixel defining layer 1022, the isolation effect of the partition structure 10a on the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted.

[0283] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the protective electrode layer 10212 and the pixel defining layer 1022, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0284] It should be noted that the patterning process employed for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each fabrication method. To represent different fabrication methods, this embodiment uses the number of patterning processes from step S104 to step S1053 to measure the complexity of the fabrication process.

[0285] According to the above step description, it can be seen that the patterning process from step S104 to step S1053 includes: 1. Step S104: Processing the inorganic protective film to obtain the inorganic protective layer 105 (referred to as mask 1); 2. Step S1051: Processing the target electrode film to obtain the target electrode layer 10211 (referred to as mask 2); 3. Step S1052: Processing the pixel defining film to obtain the initial pixel defining layer 1022a (referred to as mask 3); 4. Step S1053: Processing the initial pixel defining layer 1022a and the protective electrode film to obtain the pixel defining layer 1022 and the protective electrode layer 10212 (referred to as mask 4). In other words, the preparation method provided in the embodiment of the present application can be a preparation method for 4 masks.

[0286] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0287] FIG16 is a flow chart of another method for manufacturing a display panel according to an embodiment of the present application. Referring to FIG16 , the method includes:

[0288] Step S201: Obtain a base substrate.

[0289] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0290] Step S202: forming a plurality of driving circuits on one side of the base substrate.

[0291] In the embodiment of the present application, the film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0292] Step S203 : forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0293] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0294] Optionally, the organic insulating layer 104 includes a second via hole, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via hole to achieve transmission of the driving signal.

[0295] Step S204 : forming a plurality of light-emitting units 102 on a side of the organic insulating layer 104 away from the base substrate 101 .

[0296] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0297] 16 , the process of forming a plurality of light emitting units 102 includes:

[0298] Step S2041 : forming a connecting electrode film and a target electrode film on a side of the organic insulating layer away from the base substrate, and processing the target electrode film using a patterning process to obtain a target electrode layer.

[0299] In the embodiment of the present application, at least a portion of the connecting electrode film can be located within the second via K2 and connected to the signal output portion of the driving circuit 103 exposed through the second via. Optionally, the connecting electrode film can be made of indium tin oxide (ITO). The target electrode film can be made of a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (referred to as Ti / Al / Ti).

[0300] The connecting electrode layer 10213 and the target electrode layer 10211 can be patterned in the same process, and the etching conditions can be adjusted during the etching process of the patterning process. Optionally, after forming the connecting electrode film and the target electrode film, the target electrode film can be processed by dry etching, and then the connecting electrode film can be processed by wet etching.

[0301] Since the etching bias (CD bias) of the wet etching process for ITO is greater than the etching bias of the dry etching process for Ti / Al / Ti, the connecting electrode layer 10213 can be undercut relative to the target electrode layer 10211 to form the partition structure 10a.

[0302] 17 , the target electrode layer 10211 includes a plurality of electrode patterns, each of which can be used to form the anode of a light-emitting unit 102. Furthermore, each electrode pattern can be connected to the driving circuit 103 via a connecting electrode film located in the second via K2 to receive a driving signal provided by the driving circuit 103.

[0303] Step S2042 : forming a protective electrode film and a pixel defining film on a side of the target electrode layer away from the base substrate, and processing the pixel defining film using a patterning process to obtain an initial pixel defining layer.

[0304] In the embodiment of the present application, the initial pixel defining layer 1022a includes a plurality of hollow regions, each of which is used to expose an electrode pattern so that the subsequently formed organic functional film layer can contact the electrode pattern, thereby realizing a display function.

[0305] Optionally, the protective electrode film may be made of indium tin oxide (ITO). The pixel defining film may include a first film layer, a second film layer, and a third film layer stacked in sequence. The first and third film layers may be made of silicon oxide (SiO), and the second film layer may be made of silicon nitride (SiN).

[0306] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0307] Step S2043 : Processing the initial pixel defining layer, the protective electrode film, and the connecting electrode film using a patterning process to obtain a pixel defining layer, a protective electrode layer, and a connecting electrode layer.

[0308] In the embodiment of the present application, the initial pixel defining layer 1022a, the protective electrode film and the connecting electrode film are processed using the same patterning process, and the etching conditions can be changed in the middle of the etching process of the patterning process.

[0309] Optionally, a mixture of CHF3, Ar, and H2 can be used to etch the initial pixel defining layer 1022a, and H2SO4 can be used to etch the protective electrode film. Because the etching bias (CD bias) of the protective electrode film (ITO) is greater than the etching bias of the initial pixel defining layer 1022a (SiO / SiN / SiO), the resulting protective electrode layer 10212 is undercut relative to the pixel defining layer 1022.

[0310] Referring to FIG. 17 , the protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced apart at a first interval h1. The pixel defining layer 1022 includes at least a first defining pattern b1 and a second defining pattern b2 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the first and second intervals h1 and h2 may form a partition structure 10a.

[0311] 17 , to avoid connecting the electrode patterns of adjacent light emitting units 102 in series, the connecting electrode layer 10213 includes at least a first connecting pattern c1 and a second connecting pattern c2 spaced apart at a third interval h3. The partition structure 10a further includes a third interval h3.

[0312] When the materials of the connecting electrode film and the protective electrode film are both ITO, the connecting electrode film can also be etched when the protective electrode film is etched. In this case, the third interval h3 can be equal to the first interval h1.

[0313] When the connecting electrode film is made of Mo, after the initial delimiting layer is etched, the etching conditions need to be changed. For example, a mixed solution of HNO3, H3PO4, and CH3COOH can be used to etch the connecting electrode film. Because the etching bias (CD bias) of the connecting electrode film (Mo) is greater than that of the protective electrode layer 10212 (ITO), the resulting connecting electrode layer 10213 has an undercut relative to the protective electrode layer 10212.

[0314] Step S2044 : forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0315] In the embodiment of the present application, the organic functional film layer includes at least a charge generation layer. Because the pixel defining layer 1022 is further away from the substrate 101 than the protective electrode layer 10212, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 further away from the substrate 101 cannot be formed sequentially along the defining pattern and the protective pattern. Instead, it is disconnected at the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0316] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the isolation structure 10a. Therefore, by adjusting the thickness of the protective electrode layer 10212 and the pixel electrode layer, the isolation effect of the isolation structure 10a on the various film layers in the display panel located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted.

[0317] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the protective electrode layer 10212 and the pixel electrode layer, the charge generation layer can be blocked by the blocking structure 10a while the second electrode layer is not blocked by the blocking structure 10a.

[0318] It should be noted that the patterning process used for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each manufacturing method. To represent different manufacturing methods, the embodiment of the present application uses the number of patterning processes from step S2041 to step S2043 to measure the complexity of the manufacturing process.

[0319] According to the above step description, the patterning process from step S2041 to step S2043 includes: 1. Step S2041: Processing the target electrode film to obtain the target electrode layer 10211 (referred to as mask 1); 2. Step S2042: Processing the pixel defining film to obtain the initial pixel defining layer 1022a (referred to as mask 2); 3. Step S2043: Processing the initial pixel defining layer 1022a, the protective electrode film, and the connecting electrode film to obtain the pixel defining layer 1022, the protective electrode layer 10212, and the connecting electrode layer 10213 (referred to as mask 3). In other words, the preparation method provided in the embodiment of the present application can be a preparation method for 3 masks.

[0320] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0321] FIG18 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG18 , the method includes:

[0322] Step S301: Obtain a base substrate.

[0323] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0324] Step S302: forming a plurality of driving circuits on one side of the base substrate.

[0325] In the embodiment of the present application, the film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0326] Step S303 : forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0327] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0328] Optionally, the organic insulating layer 104 includes a second via K2, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via K2 to achieve transmission of driving signals.

[0329] Step S304 : forming a plurality of light-emitting units on a side of the organic insulating layer away from the base substrate.

[0330] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0331] 18 , the process of forming a plurality of light emitting units 102 includes:

[0332] Step S3041: forming a connecting electrode film and a target electrode layer on a side of the organic insulating layer away from the base substrate.

[0333] In the embodiment of the present application, at least a portion of the connecting electrode film may be located within the second via hole K2 and connected to the signal output portion of the driving circuit 103 exposed through the second via hole K2. Optionally, the connecting electrode film may be made of indium tin oxide (ITO).

[0334] Furthermore, the process of forming the target electrode layer 10211 includes forming a target electrode film on a side of the connecting electrode film away from the base substrate 101, and patterning the target electrode film to obtain the target electrode layer 10211. Referring to FIG. 19 , when the target electrode film is etched, the underlying connecting electrode film is not etched, i.e., the connecting electrode film remains intact.

[0335] Optionally, the target electrode film may be made of a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (referred to as Ti / Al / Ti). The etching process in the patterning process may be a dry etching process, and the dry etching process may use Cl2.

[0336] 19 , the target electrode layer 10211 includes a plurality of electrode patterns, each of which can be used to form the anode of a light-emitting unit 102. Furthermore, each electrode pattern can be connected to the driving circuit 103 via a connecting electrode film located in the second via hole to receive a driving signal provided by the driving circuit 103.

[0337] Step S3042: forming a protective electrode film on a side of the target electrode layer away from the base substrate, and processing the protective electrode film and the connecting electrode film using a patterning process to obtain a protective electrode layer and a connecting electrode layer.

[0338] In an embodiment of the present application, the material of the protective electrode film can be indium tin oxide (ITO). After the protective electrode film is formed, the protective electrode film and the connecting electrode film are processed using the same patterning process. The orthographic projection of the resulting protective electrode layer 10212 on the base substrate 101 can cover the orthographic projection of the target electrode layer 10211 on the base substrate 101. Therefore, in the subsequent process, the protective electrode layer 10212 can protect the target electrode layer 10211, preventing the aluminum layer in the target electrode layer 10211 from being corroded during the subsequent process, thereby preventing display abnormalities.

[0339] Step S3043 : forming a pixel defining film on a side of the protective electrode layer away from the base substrate, and processing the pixel defining film using a patterning process to obtain an initial pixel defining layer.

[0340] In the embodiment of the present application, the pixel defining film may include a first film layer, a second film layer, and a third film layer stacked in sequence. The first and third film layers may be made of silicon oxide (SiO), and the second film layer may be made of silicon nitride (SiN). Furthermore, the initial pixel defining layer 1022a includes multiple hollow regions, each of which is used to expose an electrode pattern to facilitate contact between the subsequently formed organic functional film layer and the electrode pattern, thereby achieving display functionality.

[0341] Optionally, the pixel defining film may include a first film layer, a second film layer, and a third film layer stacked in sequence, wherein the first film layer and the third film layer may be made of silicon oxide (SiO), and the second film layer may be made of silicon nitride (SiN).

[0342] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0343] Step S3044: Process the initial pixel definition layer using a patterning process to obtain a pixel definition layer.

[0344] In the embodiment of the present application, referring to FIG. 19 , the first defining layer 10221 of the pixel defining layer 1022 is a continuous film layer. The second defining layer 10222 includes at least a third defining pattern b3 and a fourth defining pattern b4 spaced apart at a first interval h1. The third defining layer 10223 includes at least a fifth defining pattern b5 and a sixth defining pattern b6 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the first and second intervals h1 and h2 can form a partition structure 10a.

[0345] To form the partition structure 10a, the initial pixel definition layer 1022a is etched in two steps during the patterning process. In the first step, the third thin film layer is etched using a mixture of CHF3, Ar, and H2. By controlling the etching time, the CHF3, Ar, and H2 mixture is stopped after the second thin film layer (SiN) is etched. In the second step, the second thin film layer is etched using a mixture of SF6, O2, and He.

[0346] Among them, SF6 / O2 / H e Compared with the mixed gas of CHF3, Ar and H2, the etching rate of SiN is not much different, but the etching rate of SiO is very different. That is, the etching rate of SF6 / O2 / He on SiO is very small, and the etching rate of the mixed gas of CHF3, Ar and H2 on SiO is faster. Therefore, the second thin film layer in the middle can be etched away by SF6 / O2 / He, and by increasing the etching time, the second thin film layer can be retracted to form an undercut, thereby obtaining the partition structure 10a. Moreover, even if the etching time is increased, since the etching rate of SF6 / O2 / He on the first thin film layer (SiO) is very small, it will not cause significant etching damage to the first thin film layer, that is, the lower SiO layer is retained. The reason for retaining the lower SiO layer at the partition structure 10a is to avoid the high height of the partition structure 10a, which causes the second electrode layer to be punctured or the second electrode layer to be isolated.

[0347] In the embodiment of the present application, the reason why steps S3043 and S3044 must use two patterning processes is that the hollow area of ​​the pixel definition layer 1022 is etched by using a mixed gas of CHF3, Ar and H2 to etch SiO / SiN / SiO in one step, and the middle SiN cannot be retracted to form an undercut, so as to avoid puncturing or cutting off the light-emitting material or the second electrode layer in the organic functional film layer in the hollow area, and the lower SiO layer in the hollow area must be completely etched away. Secondly, the partition structure 10a needs to be etched in two steps, and the SiN layer needs to be undercut to play a partition role, and the lower SiO layer cannot be etched away, so as to avoid the height of the partition structure 10a being too high, resulting in puncture or cutting off the second electrode layer at the partition structure 10a.

[0348] Step S3045 : forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0349] In the embodiment of the present application, the organic functional film layer includes at least a charge generation layer. Because the third defining layer 10223 of the pixel defining layer 1022 is further away from the base substrate 101 than the second defining layer 10222, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 further away from the base substrate 101 cannot be formed sequentially along the defining patterns of the third defining layer 10223 and the second defining layer 10222. Instead, it is disconnected at the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0350] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the partition structure 10a. Therefore, the thickness of the second defining layer 10222 and the third defining layer 10223 can be adjusted to further adjust the isolation effect of the partition structure 10a on the various film layers in the display panel located on the side of the pixel defining layer 1022 away from the base substrate 101.

[0351] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the protective electrode layer 10212 and the pixel electrode layer, the charge generation layer can be blocked by the blocking structure 10a while the second electrode layer is not blocked by the blocking structure 10a.

[0352] It should be noted that the patterning process used for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each manufacturing method. To represent different manufacturing methods, the embodiment of the present application uses the number of patterning processes from step S3041 to step S3044 to measure the complexity of the manufacturing process.

[0353] According to the above step description, the patterning process from step S3041 to step S3044 includes: 1. Step S3041: Processing the target electrode film to obtain the target electrode layer 10211 (referred to as mask 1); 2. Step S3042: Processing the protective electrode film and the connecting electrode film to obtain the protective electrode layer 10212 and the connecting electrode layer 10213 (referred to as mask 2); 3. Step S3043: Processing the pixel defining film to obtain the initial pixel defining layer 1022a (referred to as mask 3); 4. Step S3044: Processing the initial pixel defining layer 1022a to obtain the pixel defining layer 1022 (mask 4). In other words, the preparation method provided in the embodiment of the present application can be a preparation method for 4 masks.

[0354] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0355] FIG20 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG20 , the method includes:

[0356] Step S401: Obtain a base substrate.

[0357] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0358] Step S402: forming a plurality of driving circuits on one side of the base substrate.

[0359] In the embodiment of the present application, the film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0360] Step S403: forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0361] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0362] Optionally, the organic insulating layer 104 includes a second via K2, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via K2 to achieve transmission of driving signals.

[0363] Step S404 : forming a plurality of light-emitting units on a side of the organic insulating layer away from the base substrate.

[0364] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0365] 20 , the process of forming a plurality of light emitting units 102 includes:

[0366] Step S4041 : forming a connecting electrode film and a target electrode layer on a side of the organic insulating layer away from the base substrate.

[0367] In the embodiment of the present application, at least a portion of the connecting electrode film may be located in the second via hole K2 and connected to the signal output portion of the driving circuit 103 exposed through the second via hole. Optionally, the connecting electrode film may be made of molybdenum (Mo).

[0368] Furthermore, the process of forming the target electrode layer 10211 includes forming a target electrode film on a side of the connecting electrode film away from the base substrate 101, and patterning the target electrode film to obtain the target electrode layer 10211. Referring to FIG. 21 , when the target electrode film is etched, the underlying connecting electrode film is not etched, meaning that the connecting electrode film remains intact.

[0369] Optionally, the target electrode film may be made of a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (referred to as Ti / Al / Ti). The etching process in the patterning process may be a dry etching process, and the dry etching process may use Cl2.

[0370] 21 , the target electrode layer 10211 includes a plurality of electrode patterns, each of which can be used to form the anode of a light-emitting unit 102. Furthermore, each electrode pattern can be connected to the driving circuit 103 via a connecting electrode film located in a second via hole to receive a driving signal provided by the driving circuit 103.

[0371] Step S4042: forming a protective electrode film on a side of the target electrode layer away from the base substrate, and processing the protective electrode film and the connecting electrode film using a patterning process to obtain a protective electrode layer and a connecting electrode layer.

[0372] In an embodiment of the present application, the material of the protective electrode film can be indium tin oxide (ITO). After the protective electrode film is formed, the protective electrode film and the connecting electrode film are processed using the same patterning process. The orthographic projection of the resulting protective electrode layer 10212 on the base substrate 101 can cover the orthographic projection of the target electrode layer 10211 on the base substrate 101. Therefore, in the subsequent process, the protective electrode layer 10212 can protect the target electrode layer 10211, preventing the aluminum layer in the target electrode layer 10211 from being corroded during the subsequent process, thereby preventing display abnormalities.

[0373] Referring to FIG. 21 , the connection electrode layer 10213 includes at least a first connection pattern c1 and a second connection pattern c2 spaced at a first interval h1. The protection electrode layer 10212 includes at least a first protection pattern a1 and a second protection pattern a2 spaced at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0374] Optionally, during the etching process for patterning the protective electrode film and the connecting electrode film, the protective electrode film (ITO) may be first etched using a wet etching process or a dry etching process, and then the connecting electrode film (Mo) may be etched using a wet etching process. The protective electrode film may be etched using H2SO4, and the connecting electrode film may be etched using a mixed solution of HNO3, H3PO4, and CH3COOH.

[0375] Since the wet etching process has a larger CD bias on molybdenum than the wet etching process on indium tin oxide, the connection electrode layer 10213 can be undercut relative to the protection electrode layer 10212, thereby forming a partition structure 10a.

[0376] In the embodiment of the present application, since the material of the organic insulating layer 104 will not be affected by the wet etching process, when the wet etching process is used to form the connecting electrode layer 10213, the organic insulating layer 104 will not be over-etched, which can ensure that the height of the partition structure 10a is stable and controllable.

[0377] Optionally, the inscribed width of the partition structure 10a can be less than 0.5 μm (micrometer), i.e., w < 0.5 μm, and the height of the partition structure 10a can be less than 200 nm (nanometer), i.e., G < 200 nm. By stably and controllably controlling the inscribed width and height of the partition structure 10a, the charge generation layer is ensured to be isolated by the partition structure 10a, while the second electrode layer is not isolated by the partition structure 10a.

[0378] Step S4043 : forming a pixel defining film on a side of the protective electrode layer away from the base substrate, and performing a patterning process on the pixel defining film to obtain a pixel defining layer.

[0379] In the embodiment of the present application, referring to FIG21 , due to the presence of the partition structure 10a, the formed pixel-defining thin film is disconnected by the partition structure 10a. A single patterning process forms hollow regions in the pixel-defining layer 1022. Each hollow region exposes an electrode pattern, facilitating contact between the subsequently formed organic functional film layer and the electrode pattern, thereby achieving display functionality.

[0380] Optionally, the pixel defining film may include a first thin film layer, a second thin film layer, and a third thin film layer stacked in sequence. The materials of the first thin film layer and the third thin film layer may be silicon oxide (SiO), and the material of the second thin film layer may be silicon nitride (SiN). Alternatively, the pixel defining film may include a thin film layer made of silicon oxide (SiO), or a thin film layer made of silicon nitride (SiN). The embodiments of the present application do not limit the specific structure and materials of the pixel defining film.

[0381] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0382] Step S4044 : forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0383] In the embodiment of the present application, the organic functional film layer includes at least a charge generation layer. The charge generation layer has a high carrier mobility, so it is necessary to isolate the charge generation layer. Due to the presence of the isolation structure 10a, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 is disconnected at the isolation structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0384] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the isolation structure 10a. Therefore, by adjusting the thickness of the connecting electrode layer 10213 and the protective electrode layer 10212, the isolation effect of the isolation structure 10a on the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted.

[0385] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the connecting electrode layer 10213 and the protective electrode layer 10212, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0386] It should be noted that the patterning process used for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each manufacturing method. To represent different manufacturing methods, the embodiment of the present application uses the number of patterning processes from step S4041 to step S4043 to measure the complexity of the manufacturing process.

[0387] According to the above step description, the patterning process from step S4041 to step S4043 includes: 1. Step S4041: Processing the target electrode film to obtain the target electrode layer 10211 (referred to as mask 1); 2. Step S4042: Processing the protective electrode film and the connecting electrode film to obtain the protective electrode layer 10212 and the connecting electrode layer 10213 (referred to as mask 2); 3. Step S4043: Processing the pixel defining film to obtain the pixel defining layer 1022 (referred to as mask 3). In other words, the preparation method provided in this embodiment of the application can be a preparation method for three masks.

[0388] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0389] FIG22 is a flow chart of another method for manufacturing a display panel according to an embodiment of the present application. Referring to FIG23 , the method includes:

[0390] Step S501: Obtain a base substrate.

[0391] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0392] Step S502: forming a plurality of driving circuits on one side of the base substrate.

[0393] In the embodiment of the present application, the film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0394] Step S503 : forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0395] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0396] Optionally, the organic insulating layer 104 includes a second via hole K2, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via hole K2 to achieve transmission of driving signals.

[0397] Step S504 : forming a plurality of light-emitting units on a side of the organic insulating layer away from the base substrate.

[0398] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0399] 22 , the process of forming a plurality of light emitting units 102 includes:

[0400] Step S5041 : forming a connecting electrode film and a target electrode layer on a side of the organic insulating layer away from the base substrate.

[0401] In the embodiment of the present application, at least a portion of the connecting electrode film may be located in the second via hole K2 and connected to the signal output portion of the driving circuit 103 exposed by the second via hole. Optionally, the connecting electrode film may be made of indium tin oxide (ITO) or molybdenum (Mo).

[0402] Furthermore, the process of forming the target electrode layer 10211 includes forming a target electrode film on a side of the connecting electrode film away from the base substrate 101, and patterning the target electrode film to obtain the target electrode layer 10211. Referring to FIG. 23 , when the target electrode film is etched, the underlying connecting electrode film is not etched, meaning that the connecting electrode film remains intact.

[0403] Optionally, the target electrode film may be made of a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (referred to as Ti / Al / Ti). The etching process in the patterning process may be a dry etching process, and the dry etching process may use Cl2.

[0404] Referring to Figure 23, the connection electrode layer 10213 includes at least a first connection pattern c1 and a second connection pattern c2 spaced apart at a first interval h1. The target electrode layer 10211 includes at least a first electrode pattern d1 and a second electrode pattern d2 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2. Each electrode pattern included in the target electrode layer 10211 can be used to form the anode of a light-emitting unit 102. Furthermore, each electrode pattern can be connected to the drive circuit 103 via a connection pattern located within the second via K2, thereby receiving a drive signal provided by the drive circuit 103.

[0405] Step S5042 : forming a protective electrode layer and a pixel defining film on a side of the target electrode layer away from the base substrate, and processing the pixel defining film using a patterning process to obtain a pixel defining layer.

[0406] In the embodiment of the present application, referring to FIG23 , due to the presence of the partition structure 10 a , the formed protection electrode layer 10212 is directly disconnected by the partition structure 10 a . That is, the portion of the protection electrode layer 10212 located on the partition structure 10 a and the portion located above the target electrode layer 10211 are disconnected.

[0407] Furthermore, due to the presence of the partition structure 10a, the formed pixel defining film is directly disconnected by the partition structure 10a. That is, the portion of the pixel defining film located at the partition structure 10a and the portion located above the target electrode are disconnected.

[0408] Thus, a single patterning process is used to form hollow regions in the pixel defining layer 1022. Each hollow region is used to expose an electrode pattern, so that the subsequently formed organic functional film layer can contact the electrode pattern, thereby realizing the display function.

[0409] Optionally, the pixel defining film may include a first thin film layer, a second thin film layer, and a third thin film layer stacked in sequence. The materials of the first thin film layer and the third thin film layer may be silicon oxide (SiO), and the material of the second thin film layer may be silicon nitride (SiN). Alternatively, the pixel defining film may include a thin film layer made of silicon oxide (SiO), or a thin film layer made of silicon nitride (SiN). The embodiments of the present application do not limit the specific structure and materials of the pixel defining film.

[0410] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0411] Step S5043 : forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0412] In the embodiment of the present application, the organic functional film layer includes at least a charge generation layer. Due to the presence of the partition structure 10a, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 is disconnected from the partition structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0413] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the isolation structure 10a. Therefore, the isolation effect of the isolation structure 10a on the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted by adjusting the thickness of the connecting electrode layer 10213 and the target electrode layer 10211.

[0414] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thickness of the connecting electrode layer 10213 and the target electrode layer 10211, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0415] It should be noted that the patterning process used for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each manufacturing method. To represent different manufacturing methods, the embodiment of the present application uses the number of patterning processes from step S5041 to step S5042 to measure the complexity of the manufacturing process.

[0416] According to the above step description, the patterning process from step S5041 to step S5042 includes: 1. Step S5041: Processing the target electrode film and the connecting electrode film to obtain the target electrode layer 10211 and the connecting electrode layer 10213 (referred to as mask 1); 2. Step S5042: Processing the pixel defining film to obtain the pixel defining layer 1022 (referred to as mask 2). In other words, the preparation method provided in this embodiment of the application can be a two-mask preparation method.

[0417] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0418] FIG24 is a flow chart of another method for manufacturing a display panel according to an embodiment of the present application. Referring to FIG24 , the method includes:

[0419] Step S601: Obtain a base substrate.

[0420] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0421] Step S602: forming a plurality of driving circuits on one side of the base substrate.

[0422] In the embodiment of the present application, the film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0423] Step S603 : forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0424] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0425] Optionally, the organic insulating layer 104 includes a second via K2, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via K2 to achieve transmission of driving signals.

[0426] Step S604 : forming a plurality of light-emitting units on a side of the organic insulating layer away from the base substrate.

[0427] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0428] 24 , the process of forming a plurality of light emitting units 102 includes:

[0429] Step S6041: forming a connection electrode film and an inorganic partition film on a side of the organic insulating layer away from the base substrate, and processing the inorganic partition film using a patterning process to obtain an initial partition layer.

[0430] In the embodiment of the present application, at least a portion of the connecting electrode film can be located within the second via hole and connected to the signal output portion of the driving circuit 103 exposed through the second via hole. Optionally, the connecting electrode film can be made of indium tin oxide (ITO) or molybdenum (Mo). The inorganic insulating film can be made of silicon oxide (SiO).

[0431] After forming the inorganic partition film, the inorganic partition film needs to be processed to ensure that the electrode pattern of the subsequent target electrode layer 10211 can contact the connecting electrode film. The resulting initial partition layer has a via hole that exposes the connecting electrode film, and the orthographic projection of this via hole on the base substrate 101 can be located within the orthographic projection of the second via hole K2 of the organic insulating layer 104 on the base substrate 101. In other words, referring to Figure 25, the portion of the connecting electrode film exposed in the initial partition layer is the portion of the connecting electrode film located within the second via hole K2.

[0432] Step S6042: forming a target electrode thin film on a side of the initial isolation layer away from the base substrate, and processing the target electrode thin film using a patterning process to obtain a target electrode layer.

[0433] In the embodiment of the present application, the material of the target electrode film can be a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (represented as Ti / Al / Ti). The etching process in the patterning process can be a dry etching process, and the dry etching process can use Cl2.

[0434] 25 , the target electrode layer 10211 includes a plurality of electrode patterns, each of which can be used to form the anode of a light-emitting unit 102. Furthermore, each electrode pattern can be connected to the driving circuit 103 via a connecting electrode film located within the second via K2 to receive a driving signal provided by the driving circuit 103.

[0435] Step S6043: forming a protective electrode film on the side of the target electrode layer away from the base substrate, and processing the protective electrode film, the initial isolation layer and the connecting electrode film using a patterning process to obtain a protective electrode layer, an inorganic isolation layer and a connecting electrode layer.

[0436] In the embodiment of the present application, the material of the protective electrode film can be indium tin oxide (ITO). After the protective electrode film is formed, the protective electrode film, the initial isolation layer and the connecting electrode film are processed using the same patterning process.

[0437] Referring to Figure 25 , the connection electrode layer 10213 includes at least a first connection pattern c1 and a second connection pattern c2 spaced apart at a first interval h1. The inorganic partition layer 10214 includes at least a first insulation pattern e1 and a second insulation pattern e2 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0438] If both the protective electrode film and the connecting electrode film are made of indium tin oxide (ITO), then, with reference to FIG25 , the orthographic projection of the protective electrode layer 10212 on the base substrate 101 overlaps the orthographic projection of the connecting electrode layer 10213 on the base substrate 101. If the protective electrode film is made of ITO and the connecting electrode film is made of Mo, then, with reference to FIG25 , the protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced apart at a fourth interval h4, where the fourth interval h4 is smaller than the first interval h1 and larger than the second interval h2.

[0439] Optionally, during the etching process for patterning the protective electrode film, the initial insulating layer, and the connecting electrode film, the protective electrode film (ITO) can be etched first using a wet etching process or a dry etching process, followed by etching the initial insulating layer using a dry etching process, and finally etching the connecting electrode film (ITO or Mo) using a wet etching process. The protective electrode film is etched using H2SO4, the initial insulating layer is etched using a mixed gas of CHF3, Ar, and H2, and the connecting electrode film is etched using a mixed solution of HNO3, H3PO4, and CH3COOH.

[0440] Because the wet etching process has a greater CD bias for ITO or Mo than the dry etching process for SiO, the connecting electrode layer 10213 can be undercut relative to the inorganic partition layer 10214, thereby forming the partition structure 10a. Furthermore, when the protective electrode film is made of ITO and the connecting electrode film is made of Mo, because the wet etching process has a greater CD bias for Mo than the wet or dry etching process for ITO, the fourth spacing h4 of the protective pattern of the protective electrode layer 10212 can be made smaller than the first spacing h1 of the connecting pattern of the connecting electrode layer 10213.

[0441] Step S6044: forming a pixel defining film on a side of the protective electrode layer away from the base substrate, and processing the pixel defining film using a patterning process to obtain a pixel defining layer.

[0442] In the embodiment of the present application, referring to FIG25 , due to the presence of the partition structure 10a, the formed pixel-defining thin film is disconnected by the partition structure 10a. A single patterning process forms hollow regions in the pixel-defining layer 1022. Each hollow region exposes an electrode pattern, facilitating contact between the subsequently formed organic functional film layer and the electrode pattern, thereby achieving display functionality.

[0443] Optionally, the pixel defining film may include a first thin film layer, a second thin film layer, and a third thin film layer stacked in sequence. The materials of the first thin film layer and the third thin film layer may be silicon oxide (SiO), and the material of the second thin film layer may be silicon nitride (SiN). Alternatively, the pixel defining film may include a thin film layer made of silicon oxide (SiO), or a thin film layer made of silicon nitride (SiN). The embodiments of the present application do not limit the specific structure and materials of the pixel defining film.

[0444] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0445] Step S6045 : forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0446] In the embodiment of the present application, the organic functional film layer includes at least a charge generation layer. The charge generation layer has a high carrier mobility, so it is necessary to isolate the charge generation layer. Due to the presence of the isolation structure 10a, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 is disconnected at the isolation structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0447] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the partition structure 10a. Therefore, by adjusting the thickness of the connecting electrode layer 10213 and the inorganic partition layer 10214, the isolation effect of the partition structure 10a on the various film layers in the display panel located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted.

[0448] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the partition structure 10a than the second electrode layer. Thus, by adjusting the thickness of the connecting electrode layer 10213 and the inorganic partition layer 10214, the charge generation layer can be blocked by the partition structure 10a, while the second electrode layer is not blocked by the partition structure 10a.

[0449] It should be noted that the patterning process used for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each manufacturing method. To represent different manufacturing methods, the embodiment of the present application uses the number of patterning processes from step S6041 to step S6044 to measure the complexity of the manufacturing process.

[0450] According to the above step description, it can be seen that the patterning process from step S6041 to step S6044 includes: 1. Step S6041: Processing the inorganic partition film to obtain an initial partition layer (referred to as mask 1); 2. Step S6042: Processing the target electrode film to obtain a target electrode layer 10211 (referred to as mask 2); 3. Step S6043: Processing the protective electrode film, the initial partition layer, and the connecting electrode film to obtain a protective electrode layer 10212, an inorganic partition layer 10214, and a connecting electrode layer 10213 (referred to as mask 3); 4. Step S6044: Processing the pixel defining film to obtain a pixel defining layer 1022 (referred to as mask 4). In other words, the preparation method provided in the embodiment of the present application can be a preparation method for 4 masks.

[0451] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0452] FIG26 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present application. Referring to FIG26 , the method includes:

[0453] Step S701: Obtain a base substrate.

[0454] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0455] Step S702: forming a plurality of driving circuits on one side of the base substrate.

[0456] In the embodiment of the present application, the film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0457] Step S703 : forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0458] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0459] Optionally, the organic insulating layer 104 includes a second via K2, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via K2 to achieve transmission of driving signals.

[0460] Step S704 : forming a plurality of light-emitting units on a side of the organic insulating layer away from the base substrate.

[0461] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0462] 26 , the process of forming a plurality of light emitting units 102 includes:

[0463] Step S7041: forming a connection electrode film and an inorganic partition film on a side of the organic insulating layer away from the base substrate, and processing the inorganic partition film using a patterning process to obtain an initial partition layer.

[0464] In this embodiment of the present application, at least a portion of the connecting electrode film can be located within the second via K2 and connected to the signal output portion of the driving circuit 103 exposed through the second via. Optionally, the connecting electrode film can be made of indium tin oxide (ITO) or molybdenum (Mo). The inorganic barrier film can be made of silicon oxide (SiO).

[0465] After forming the inorganic partition film, the inorganic partition film needs to be processed to ensure that the electrode pattern of the subsequent target electrode layer 10211 can contact the connecting electrode film. The resulting initial partition layer has a via hole that exposes the connecting electrode film, and the orthographic projection of this via hole on the base substrate 101 can be located within the orthographic projection of the second via hole K2 of the organic insulating layer 104 on the base substrate 101. In other words, referring to Figure 27, the portion of the connecting electrode film exposed in the initial insulating layer is the portion of the connecting electrode film located within the second via hole K2.

[0466] Step S7042: forming a target electrode film on the side of the initial isolation layer away from the base substrate, and processing the target electrode film, the initial isolation layer and the connecting electrode film using a patterning process to obtain a target electrode layer, an inorganic isolation layer and a connecting electrode layer.

[0467] In an embodiment of the present application, the target electrode film may be formed of a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (referred to as Ti / Al / Ti). After the target electrode film is formed, the target electrode film, the initial insulating layer, and the connecting electrode film are processed using the same patterning process.

[0468] Referring to Figure 27 , the connecting electrode layer 10213 includes at least a first connecting pattern c1 and a second connecting pattern c2 spaced at a first interval h1. The inorganic partition layer 10214 includes at least a first insulating pattern e1 and a second insulating pattern e2 spaced at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2. Furthermore, the orthographic projection of the target electrode layer 10211 on the base substrate 101 overlaps with the orthographic projection of the inorganic partition layer 10214 on the base substrate 101.

[0469] Optionally, during the etching process for patterning the target electrode film, the initial insulating layer, and the connecting electrode film, the protective electrode film (Ti / Al / Ti) can be etched first using a dry etching process, then the initial insulating layer can be etched using a dry etching process, and finally the connecting electrode film (ITO or Mo) can be etched using a wet etching process. The target electrode film is etched using Cl2, the initial insulating layer is etched using a mixed gas of CHF3, Ar, and H2, and the connecting electrode film is etched using H2SO4.

[0470] Since the etching bias (CD bias) of the wet etching process for ITO is greater than the etching bias of the dry etching process for SiO and Ti / Al / Ti, the connecting electrode layer 10213 can be undercut relative to the inorganic partition layer 10214 and the target electrode layer 10211, thereby forming a partition structure 10a.

[0471] Step S7043: forming a protective electrode layer and a pixel defining film on a side of the target electrode layer away from the base substrate, and processing the pixel defining film using a patterning process to obtain a pixel defining layer.

[0472] In the embodiment of the present application, referring to FIG27 , due to the presence of the partition structure 10a, the formed protection electrode layer 10212 is disconnected by the partition structure 10a. That is, the portion of the protection electrode layer 10212 located on the partition structure 10a and the portion located above the target electrode layer 10211 are disconnected.

[0473] Furthermore, due to the presence of the partition structure 10a, the formed pixel defining film is directly disconnected by the partition structure 10a. That is, the portion of the pixel defining film located at the partition structure 10a and the portion located above the target electrode are disconnected.

[0474] Thus, a single patterning process is used to form hollow regions in the pixel defining layer 1022. Each hollow region is used to expose an electrode pattern, so that the subsequently formed organic functional film layer can contact the electrode pattern, thereby realizing the display function.

[0475] Optionally, the pixel defining film may include a first thin film layer, a second thin film layer, and a third thin film layer stacked in sequence. The materials of the first thin film layer and the third thin film layer may be silicon oxide (SiO), and the material of the second thin film layer may be silicon nitride (SiN). Alternatively, the pixel defining film may include a thin film layer made of silicon oxide (SiO), or a thin film layer made of silicon nitride (SiN). The embodiments of the present application do not limit the specific structure and materials of the pixel defining film.

[0476] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0477] Step S7044: forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0478] In the embodiments of the present application, the organic functional film layer includes at least a charge generation layer. This charge generation layer has high carrier mobility, so it is necessary to isolate the charge generation layer. Due to the presence of the isolation structure 10a, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 is disconnected by the isolation structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0479] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the partition structure 10a. Therefore, by adjusting the thickness of the connecting electrode layer 10213, the inorganic partition layer 10214, and the target electrode layer 10211, the isolation effect of the partition structure 10a on the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted.

[0480] Optionally, because the second electrode layer is further away from the pixel defining layer 1022 than the charge generation layer, the charge generation layer is more easily blocked by the blocking structure 10a than the second electrode layer. Thus, by adjusting the thicknesses of the connecting electrode layer 10213, the inorganic blocking layer 10214, and the target electrode layer 10211, the charge generation layer can be blocked by the blocking structure 10a, while the second electrode layer is not blocked by the blocking structure 10a.

[0481] It should be noted that the patterning process used for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each manufacturing method. To represent different manufacturing methods, the embodiment of the present application uses the number of patterning processes from step S7041 to step S7043 to measure the complexity of the manufacturing process.

[0482] According to the above step description, the patterning process from step S7041 to step S7043 includes: 1. Step S7041: Processing the inorganic partition film to obtain an initial insulating layer (referred to as mask 1); 2. Step S7042: Processing the target electrode film, the initial partition layer, and the connecting electrode film to obtain the target electrode layer 10211, the inorganic partition layer 10214, and the connecting electrode layer 10213 (referred to as mask 2); 3. Step S7043: Processing the pixel defining film to obtain the pixel defining layer 1022 (referred to as mask 3). In other words, the preparation method provided in the embodiment of the present application can be a preparation method for 3 masks.

[0483] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0484] FIG28 is a flow chart of another method for manufacturing a display panel according to an embodiment of the present application. Referring to FIG28 , the method includes:

[0485] Step S801: Obtain a base substrate.

[0486] In the embodiment of the present application, the base substrate 101 has a display area 101 a and a peripheral area 101 b surrounding the display area 101 a .

[0487] Step S802: forming a plurality of driving circuits on one side of the base substrate.

[0488] In the embodiment of the present application, the film layers of the thin film transistors and storage capacitors in the plurality of driving circuits 103 may be formed on one side of the base substrate 101 first.

[0489] Step S803 : forming an organic insulating layer on a side of the plurality of driving circuits away from the base substrate.

[0490] In the embodiment of the present application, the process of forming the organic insulating layer 104 may include: forming an organic insulating film on a side of the plurality of driving circuits 103 away from the base substrate 101; and processing the organic insulating film using a patterning process. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0491] Optionally, the organic insulating layer 104 includes a second via K2, which can expose the signal output portion of the driving circuit 103. Thus, other film layers formed subsequently can be connected to the driving circuit 103 through the second via K2 to achieve transmission of driving signals.

[0492] Step S804 : forming a plurality of light-emitting units on a side of the organic insulating layer away from the base substrate.

[0493] In the embodiment of the present application, multiple light-emitting units 102 are located in the display area 101a, and the multiple light-emitting units 102 correspond to multiple driving circuits 103, and each driving circuit 103 is connected to the corresponding light-emitting unit 102 to provide a driving signal for the corresponding light-emitting unit 102.

[0494] 28 , the process of forming a plurality of light emitting units 102 includes:

[0495] Step S8041: forming a target electrode film and a protective electrode film on a side of the organic insulating layer away from the base substrate, and processing the protective electrode film and the target electrode film using a patterning process to obtain a target electrode layer and a protective electrode layer.

[0496] In an embodiment of the present application, at least a portion of the target electrode film can be located within the second via and connected to the signal output portion of the drive circuit 103 exposed through the second via. Optionally, the target electrode film can be made of molybdenum (Mo), aluminum (Al), or a Mo / Al / Mo triple layer. The protective electrode film can be made of indium tin oxide (ITO).

[0497] After the target electrode film and the protective electrode film are formed, the target electrode film and the protective electrode film are processed using the same patterning process.

[0498] Referring to FIG. 29 , the target electrode layer 10211 includes at least a first electrode pattern d1 and a second electrode pattern d2 spaced apart at a first interval h1. The protective electrode layer 10212 includes at least a first protective pattern a1 and a second protective pattern a2 spaced apart at a second interval h2. The first interval h1 is greater than the second interval h2, and the partition structure 10a includes the first interval h1 and the second interval h2.

[0499] Optionally, during the etching process for patterning the protective electrode film and the target electrode film, the protective electrode film (ITO) may be first etched using a wet etching process or a dry etching process, and then the target electrode film (Mo, Al, or Mo / Al / Mo) may be etched using a wet etching process. The protective electrode film may be etched using H2SO4, and the target electrode film may be etched using a mixed solution of HNO3, H3PO4, and CH3COOH.

[0500] Since the etching bias (CD bias) of the wet etching process or the dry etching process on ITO is greater than the etching bias of the wet etching process on Mo or Al or Mo / Al / Mo, the target electrode layer 10211 can be undercut relative to the protective electrode layer 10212, thereby forming a partition structure 10a.

[0501] If the material of the target electrode layer 10211 is Mo, even if the protection electrode layer 10212 does not cover the sidewall of the target electrode layer 10211, the target electrode layer 10211 will not be corroded due to subsequent processes.

[0502] If the target electrode layer 10211 is made of Al or Mo / Al / Mo, there may be a risk of corrosion because the protective electrode layer 10212 does not cover the sidewalls of the target electrode layer 10211, but the risk is relatively small. This is because the protective electrode layer 10212 directly above the sidewalls of the target electrode layer 10211 can reduce the risk of corrosion on the sidewalls of the target electrode layer 10211 caused by plasma during the subsequent formation of the pixel definition layer.

[0503] Step S8042 : forming a pixel defining film on a side of the protective electrode layer away from the base substrate, and processing the pixel defining film using a patterning process to obtain a pixel defining layer.

[0504] In the embodiment of the present application, referring to FIG29 , due to the presence of the partition structure 10 a , the formed pixel defining film is directly disconnected by the partition structure 10 a . That is, the portion of the pixel defining film located at the partition structure 10 a and the portion located above the target electrode are disconnected.

[0505] Thus, a single patterning process is used to form hollow regions in the pixel defining layer 1022. Each hollow region is used to expose an electrode pattern, so that the subsequently formed organic functional film layer can contact the electrode pattern, thereby realizing the display function.

[0506] Optionally, the pixel defining film may include a first thin film layer, a second thin film layer, and a third thin film layer stacked in sequence. The materials of the first thin film layer and the third thin film layer may be silicon oxide (SiO), and the material of the second thin film layer may be silicon nitride (SiN). Alternatively, the pixel defining film may include a thin film layer made of silicon oxide (SiO), or a thin film layer made of silicon nitride (SiN). The embodiments of the present application do not limit the specific structure and materials of the pixel defining film.

[0507] When the pixel defining film includes three thin film layers of SiO, SiN, and SiO (denoted as SiO / SiN / SiO), when a patterning process is used to process the pixel defining film to obtain the initial pixel defining layer 1022a, the etching process in the patterning process can use a mixed gas of CHF3, Ar, and H2 to etch the SiO / SiN / SiO. In other words, both SiO and SiN are etched using a mixed gas of CHF3, Ar, and H2, and all three layers of SiO / SiN / SiO need to be etched away to obtain the hollowed-out area.

[0508] Step S8043 : forming an organic functional film layer and a second electrode layer on a side of the pixel defining layer away from the base substrate.

[0509] In the embodiment of the present application, the organic functional film layer includes at least a charge generation layer. The charge generation layer has a high carrier mobility, so it is necessary to isolate the charge generation layer. Due to the presence of the isolation structure 10a, the charge generation layer subsequently formed on the side of the pixel defining layer 1022 away from the base substrate 101 is disconnected at the isolation structure 10a. This prevents lateral leakage current caused by the high carrier mobility of the charge generation layer, thereby ensuring luminous efficiency.

[0510] Typically, as the distance from the pixel defining layer 1022 increases, the various film layers in the display panel 10 located on the side of the pixel defining layer 1022 away from the base substrate 101 will be less and less likely to be isolated by the isolation structure 10a. Therefore, by adjusting the thickness of the target electrode layer 10211 and the protective electrode layer 10212, the isolation effect of the isolation structure 10a on the various film layers in the display panel located on the side of the pixel defining layer 1022 away from the base substrate 101 can be adjusted.

[0511] Optionally, since the second electrode layer is farther away from the pixel defining layer 1022 than the charge generating layer, the charge generating layer is more easily isolated by the partition structure 10a than the second electrode layer. Therefore, the thickness of the target electrode layer 10211 and the protective electrode layer 10212 can be adjusted so that the charge generating layer is isolated by the partition structure 10a, and the second electrode layer 10211 is further away from the pixel defining layer 1022. It should be noted that the patterning process used for the film layer formed before the organic insulating layer 104 and the film layer formed after the pixel defining layer 1022 is required for each preparation method. In order to represent different preparation methods, the embodiment of the present application uses the number of patterning processes from step S8041 to step S8042 to measure the complexity of the preparation process.

[0512] According to the above step description, the patterning process from step S8041 to step S8042 includes: 1. Step S8041: Processing the target electrode film and the protective electrode film to obtain the target electrode layer 10211 and the protective electrode layer 10212 (referred to as mask 1); 2. Step S8042: Processing the pixel definition film to obtain the pixel definition layer 1022 (referred to as mask 2). In other words, the preparation method provided in this embodiment of the application can be a two-mask preparation method.

[0513] In summary, embodiments of the present application provide a method for fabricating a display panel. The display panel fabricated by this method includes a base substrate, a plurality of drive circuits, and a plurality of light-emitting units located on the base substrate. Furthermore, the display panel includes a partition structure, and the charge generation layer in the organic functional film layer can be isolated by the partition structure, while the second electrode layer is not isolated by the partition structure. This ensures not only the display function of the display panel but also avoids the generation of lateral leakage current, thereby ensuring a good display effect.

[0514] In an embodiment of the present application, the material of the inorganic isolation layer 10214 in the above scheme can be a single layer of silicon oxide (SiO), or a single layer of silicon nitride (SiN), or a double layer of SiO / SiN, or a triple layer of SiO / SiN / SiO.

[0515] In addition, the materials of the connecting electrode layer, the target electrode layer, and the protective electrode layer may be replaced by other metals, such as indium zinc oxide (IZO), copper (Cu), and molybdenum-niobium alloy.

[0516] Moreover, the solution of the embodiment of the present application can adjust the isolation effect of the isolation structure on the charge generation layer by appropriately adjusting the etching parameters to isolate the inner etching width w and the isolation height G of the isolation structure, while ensuring that other functional layers such as the second electrode layer are not affected.

[0517] In the embodiments of the present application, the process steps adopted in the above eight preparation methods are relatively simple, and compared with the conventional scheme of Figure 2, fewer patterning processes are used, which can improve preparation efficiency and reduce manufacturing costs.

[0518] Moreover, among the above eight preparation methods, except for method three (the method of steps S301 to S304), the other seven preparation methods are all based on the undercut formed by different film layers using different etching conditions, and are not based on the difference in etching rates of different materials under the same etching conditions. Therefore, the undercut width is easy to control.

[0519] Furthermore, in method four (the method from step S401 to step S404), method five (the method from step S501 to step 504) and method eight (the method from step S801 to step 804) among the above eight preparation methods, the metal material plays a partitioning role, so it is less likely to break when subjected to film-forming extrusion of the organic functional film layer, thereby ensuring the partitioning effect.

[0520] For the eight preparation methods mentioned above, Method 1 (the method of steps S101 to S105), Method 2 (the method of steps S201 to S204), Method 3 (the method of steps S301 to S304), Method 6 (the method of steps S601 to S604), and Method 7 (the method of steps S701 to S704), although the inorganic material plays a partitioning role, the risk of inorganic material fracture can be controlled by controlling the inscribed width w < 0.1 μm and the height G of the partition structure < 0.1 μm. In addition, the direction of inorganic material fracture can be reduced by optimizing the process of the film layer formed after the pixel definition layer.

[0521] FIG30 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Referring to FIG30 , a power supply component 20 and a display panel 10 provided in the above embodiment are shown. The power supply component 20 is used to supply power to the display panel 10.

[0522] Optionally, the display device may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QD) display device. The display device may be any suitable display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation systems, e-books, and any other product or component with a display function.

[0523] Since the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0524] The terms used in the embodiments of this application are only used to explain the embodiments of this application and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the common meaning understood by people with ordinary skills in the field to which this application belongs.

[0525] The terms used in the embodiments of this application are intended solely to illustrate the embodiments of this application and are not intended to limit this application. Unless otherwise defined, technical or scientific terms used in the embodiments of this application should have the same ordinary meaning as those understood by persons of ordinary skill in the art to which this application belongs. The terms "first," "second," "third," and similar terms used in this patent specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish between different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather denote the presence of at least one. Terms such as "include" or "comprising" and similar terms mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used solely to indicate relative positions. When the absolute position of the described objects changes, the relative positions may also change accordingly.

[0526] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: A base substrate, the base substrate having a display area and a peripheral area surrounding the display area; A plurality of light-emitting units, the plurality of light-emitting units are located on one side of the base substrate and in the display area, the plurality of light-emitting units include: a first electrode layer, a pixel defining layer, an organic functional film layer and a second electrode layer sequentially stacked in a direction away from the base substrate, the first electrode layer includes: a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate, the orthographic projection of the protective electrode layer on the base substrate covers the orthographic projection of the target electrode layer on the base substrate, and the organic functional film layer includes at least a charge generation layer; and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and being used to provide a driving signal for the corresponding light-emitting unit; Among them, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the protective electrode layer at least includes: a first protective pattern and a second protective pattern arranged at a first interval, the pixel defining layer at least includes: a first defining pattern and a second defining pattern arranged at a second interval, the first interval is larger than the second interval, the partition structure includes the first interval and the second interval, the charge generating layer is located at a portion of the partition structure and a portion located at the light-emitting area of ​​the light-emitting unit, and the second electrode layer is located at a portion of the partition structure and a portion located at the light-emitting area of ​​the light-emitting unit. Continuous arrangement.

2. The display panel according to claim 1, characterized in that: The display panel further includes: an organic insulating layer and an inorganic protective layer located between the plurality of light emitting units and the plurality of driving circuits and stacked in a direction away from the base substrate; Wherein, the target electrode layer is connected to the driving circuit through a first via hole in the inorganic protective layer and a second via hole in the organic insulating layer.

3. The display panel according to claim 1, characterized in that: The display panel further includes: an organic insulating layer located between the plurality of light-emitting units and the plurality of driving circuits; the first electrode layer further includes: a connecting electrode layer located on a side of the target electrode layer close to the base substrate, the connecting electrode layer being connected to the driving circuit through a second via hole in the organic insulating layer; The connecting electrode layer and the protecting electrode layer are formed by the same patterning process. The connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern spaced apart at a third interval. The partition structure also includes the third interval.

4. The display panel according to claim 3, characterized in that: The connecting electrode layer and the protective electrode layer are made of the same material, and the third interval is equal to the first interval; or, The connection electrode layer and the protection electrode layer are made of different materials, and the third interval is not equal to the first interval.

5. A display panel, characterized in that: The display panel comprises: A base substrate, the base substrate having a display area and a peripheral area surrounding the display area; A plurality of light-emitting units, the plurality of light-emitting units are located on one side of the base substrate and in the display area, the plurality of light-emitting units include: a first electrode layer, a pixel defining layer, an organic functional film layer and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer includes: a connecting electrode layer, a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate, the connecting electrode layer and the protective electrode layer are made of the same material and are formed by the same patterning process, the orthographic projection of the protective electrode layer on the base substrate overlaps with the orthographic projection of the connecting electrode layer on the base substrate, and both cover the orthographic projection of the target electrode layer on the base substrate; the organic functional film layer includes at least a charge generating layer; and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and being used to provide a driving signal for the corresponding light-emitting unit; Wherein, the display panel further includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the pixel defining layer includes a first defining layer, a second defining layer and a third defining layer stacked in a direction away from the base substrate, the first defining layer is continuously arranged, the second defining layer at least includes: a third defining pattern and a fourth defining pattern arranged at intervals in a first interval manner, the third defining layer at least includes: a fifth defining pattern and a sixth defining pattern arranged at intervals in a second interval manner, the first interval is greater than the second interval, the partition structure includes the first interval and the second interval, the charge generation layer is located in the portion of the partition structure and in the portion of the light-emitting unit The portion of the second electrode layer located at the partition structure and the portion located at the light emitting area of ​​the light emitting unit are disconnected and arranged continuously.

6. The display panel according to claim 5, characterized in that: The display panel further includes: an organic insulating layer located between the plurality of light emitting units and the plurality of driving circuits; The connection electrode layer is connected to the driving circuit through a second via hole in the organic insulating layer.

7. A display panel, characterized in that: The display panel comprises: A base substrate, the base substrate having a display area and a peripheral area surrounding the display area; A plurality of light-emitting units, the plurality of light-emitting units are located on one side of the base substrate and in the display area, the plurality of light-emitting units include: a first electrode layer, a pixel defining layer, an organic functional film layer and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer includes: a connecting electrode layer, a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate, the orthographic projection of the protective electrode layer on the base substrate and the orthographic projection of the connecting electrode layer on the base substrate both cover the orthographic projection of the target electrode layer on the base substrate, and the organic functional film layer includes at least a charge generating layer; and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and being used to provide a driving signal for the corresponding light-emitting unit; Among them, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern arranged at a first interval, the protective electrode layer at least includes: a first protective pattern and a second protective pattern arranged at a second interval, the first interval is larger than the second interval, the partition structure includes the first interval and the second interval, the charge generating layer is located at a portion of the partition structure and a portion located at the light-emitting area of ​​the light-emitting unit, and the second electrode layer is located at a portion of the partition structure and a portion located at the light-emitting area of ​​the light-emitting unit. Continuous arrangement.

8. The display panel according to claim 7, characterized in that: The connecting electrode layer and the protecting electrode layer are made of different materials, and the connecting electrode layer and the protecting electrode layer are formed by a same patterning process.

9. A display panel, characterized in that: The display panel comprises: A base substrate, the base substrate having a display area and a peripheral area surrounding the display area; A plurality of light-emitting units, the plurality of light-emitting units are located on one side of the base substrate and in the display area, the plurality of light-emitting units include: a first electrode layer, an organic functional film layer, a pixel defining layer and a second electrode layer sequentially stacked in a direction away from the base substrate, the first electrode layer includes: a connecting electrode layer, a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate; the organic functional film layer includes at least a charge generating layer; and a plurality of driving circuits corresponding to the plurality of light-emitting units, the plurality of driving circuits being located between the substrate and the plurality of light-emitting units, each of the driving circuits being connected to a corresponding light-emitting unit and being used to provide a driving signal for the corresponding light-emitting unit; Wherein, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern arranged at a first interval, the target electrode layer at least includes: a first electrode pattern and a second electrode pattern arranged at a second interval, the first interval is greater than the second interval, the partition structure includes the first interval and the second interval, the protective electrode layer is located at a portion of the partition structure and a portion located in the light-emitting area of ​​the light-emitting unit and is disconnected, the charge generating layer is located at a portion of the partition structure and a portion located in the light-emitting area of ​​the light-emitting unit and is disconnected, and the second electrode layer is located at a portion of the partition structure and a portion located in the light-emitting area of ​​the light-emitting unit and is continuously arranged.

10. A display panel, characterized in that: The display panel comprises: A base substrate, the base substrate having a display area and a peripheral area surrounding the display area; A plurality of light-emitting units, the plurality of light-emitting units are located on one side of the base substrate and in the display area, the plurality of light-emitting units include: a first electrode layer, an organic functional film layer, a pixel defining layer and a second electrode layer stacked in sequence in a direction away from the base substrate, the first electrode layer includes: a connecting electrode layer, an inorganic partition layer, a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate; the organic functional film layer includes at least a charge generating layer; and a plurality of driving circuits corresponding to the plurality of light-emitting units, wherein the plurality of driving circuits are located between the substrate and the plurality of light-emitting units, and each of the driving circuits and the corresponding light-emitting unit connected to provide a driving signal for the corresponding light-emitting unit; Among them, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern arranged at a first interval, the inorganic partition layer at least includes: a first insulating pattern and a second insulating pattern arranged at a second interval, the first interval is larger than the second interval, the partition structure includes the first interval and the second interval, the charge generating layer is located at the partition structure and the light-emitting area of ​​the light-emitting unit, and the second electrode layer is located at the partition structure and the light-emitting area of ​​the light-emitting unit. The portion is continuously arranged.

11. The display panel according to claim 10, characterized in that: The target electrode layer, the inorganic partition layer and the connecting electrode layer are formed by a same patterning process; The orthographic projection of the target electrode layer on the base substrate overlaps with the orthographic projection of the inorganic partition layer on the base substrate.

12. The display panel according to claim 10, characterized in that: The protective electrode layer, the inorganic partition layer and the connecting electrode layer are formed by the same patterning process; The protective electrode layer and the connecting electrode layer are made of the same material, and the orthographic projection of the protective electrode layer on the base substrate overlaps with the orthographic projection of the connecting electrode layer on the base substrate; or, The protective electrode layer and the connecting electrode layer are made of different materials. The protective electrode layer at least includes: a first protective pattern and a second protective pattern spaced apart at a fourth interval. The fourth interval is smaller than the first interval and larger than the second interval.

13. A display panel, characterized in that: The display panel comprises: a base substrate, the base substrate having a display area and a peripheral area surrounding the display area; A plurality of light-emitting units, the plurality of light-emitting units are located on one side of the base substrate and in the display area, the plurality of light-emitting units include: a first electrode layer, an organic functional film layer, a pixel defining layer and a second electrode layer sequentially stacked in a direction away from the base substrate, the first electrode layer includes: a target electrode layer and a protective electrode layer stacked in a direction away from the base substrate, the target electrode layer is prepared by a wet etching process; the organic functional film layer includes at least a charge generating layer; and a plurality of driving circuits corresponding to the plurality of light emitting units, the plurality of driving circuits being located Between the base substrate and the plurality of light-emitting units, each of the driving circuits is connected to a corresponding light-emitting unit, and is used to provide a driving signal for the corresponding light-emitting unit; Wherein, the display panel also includes: a partition structure located between the light-emitting areas of any two adjacent light-emitting units, the target electrode layer at least includes: a first electrode pattern and a second electrode pattern arranged at a first interval, the protective electrode layer at least includes: a first protective pattern and a second protective pattern arranged at a second interval, the first interval is greater than the second interval, the partition structure includes the first interval and the second interval, the charge generation layer is located at a portion of the partition structure and a portion of the light-emitting area of ​​the light-emitting unit is disconnected, and the second electrode layer is located at a portion of the partition structure and a portion of the light-emitting area of ​​the light-emitting unit is continuously arranged.

14. A method for preparing a display panel, characterized in that: The method comprises: Obtaining a substrate, wherein the substrate has a display area and a peripheral area surrounding the display area; forming a plurality of driving circuits on one side of the base substrate; A plurality of light-emitting units are formed on a side of the plurality of driving units away from the base substrate, the plurality of light-emitting units are located in the display area, the plurality of light-emitting units correspond to the plurality of driving units, and each of the driving circuits is connected to a corresponding light-emitting unit for providing a driving signal to the corresponding light-emitting unit; Wherein, the forming of a plurality of light-emitting units comprises: forming a connection electrode film on a side of the plurality of driving circuits away from the base substrate; forming a target electrode film on a side of the connecting electrode film away from the base substrate, and patterning the target electrode film to obtain a target electrode layer; forming a protective electrode film on a side of the target electrode layer away from the base substrate; The protective electrode film is processed by a first etching process to obtain a protective electrode layer, and the connecting electrode film is processed by a second etching process to obtain a connecting electrode layer, wherein the first etching process and the second etching process are the same patterning process; wherein the connecting electrode layer at least includes: a first connecting pattern and a second connecting pattern arranged at a first interval, and the protective electrode layer at least includes: a first protective pattern and a second protective pattern arranged at a second interval, wherein the first interval is larger than the second interval, and the first interval and the second interval constitute a partition structure; A pixel electrode layer is formed on a side of the protective electrode layer away from the base substrate. The portion of the polar layer located at the partition structure and the portion located at the light emitting area of ​​the light emitting unit are disconnected; An organic functional film layer is formed on a side of the pixel electrode layer away from the base substrate, wherein the organic functional film layer at least comprises a charge generating layer, and the charge generating layer is disconnected from a portion located at the partition structure and a portion located at the light emitting area of ​​the light emitting unit; A second electrode layer is formed on a side of the organic functional film layer away from the base substrate, and the second electrode layer is continuously arranged at a portion located at the partition structure and a portion located at a light emitting area of ​​the light emitting unit.

15. A display device, characterized in that: The display device comprises: a power supply component and a display panel according to any one of claims 1 to 13; Wherein, the power supply component is used to supply power to the display panel.

Images