Three-dimensional memory and manufacturing method therefor, and electronic device

Abstract

The embodiments of the present application relate to a three-dimensional memory and a manufacturing method therefor, and an electronic device. The three-dimensional memory comprises a plurality of layers of storage units stacked at intervals in a third direction, wherein each layer of storage units comprises a plurality of storage units arranged at intervals in a second direction, each storage unit comprises a transistor, and a first direction and the second direction intersect and are both perpendicular to the third direction; and the transistor comprises a gate (60) and a semiconductor layer (50) extending in the first direction, and the gate (60) is arranged around the circumferential side wall of the semiconductor layer (50); a plurality of bit lines (90) extending in the third direction, wherein each bit line (90) is connected to the transistors in a column of storage units arranged in the third direction; and a plurality of word lines (70) extending in the second direction, the gates (60) of the transistors in a column of storage units arranged in the second direction being connected to form a word line (70).

Description

Three-dimensional memory, manufacturing method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed on September 28, 2023, with application number 202311285473.6 and invention name “Three-dimensional memory, manufacturing method thereof, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present application relate to, but are not limited to, the field of semiconductor technology, and in particular to a three-dimensional memory, a manufacturing method thereof, and an electronic device. Background Art

[0003] With the advancement of semiconductor technology, more and more types of memory devices have been manufactured using this technology. These memories include arrays of memory cells for storing data. As the demand for integration and storage capacity continues to increase across various electronic devices, three-dimensional (3D) memory devices have emerged. 3D stacked memory devices can be created by stacking multiple memory cell arrays for storing data, thereby increasing the memory's storage capacity.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] In one aspect, an exemplary embodiment of the present application provides a three-dimensional memory device, comprising a plurality of memory cells stacked at intervals along a third direction, each layer of memory cells comprising a plurality of memory cells arranged at intervals along a second direction, the memory cells comprising transistors, the transistors comprising gates and semiconductor layers extending along a first direction, the gates being disposed around circumferential sidewalls of the semiconductor layers, the first direction intersecting the second direction and both being perpendicular to the third direction;

[0007] a plurality of bit lines extending along a third direction, each of the bit lines being connected to the transistors in a column of the memory cells arranged along the third direction;

[0008] A plurality of word lines extend along a second direction, and the gates of the transistors in a column of the memory cells arranged along the second direction are connected to form one word line.

[0009] In an exemplary embodiment, each of the word lines has a plurality of through holes arranged at intervals along the second direction, and each of the through holes is located between two adjacent memory cells along the second direction, and each of the through holes is filled with a dielectric material.

[0010] In an exemplary embodiment, an insulating layer is provided between two adjacent word lines in the third direction.

[0011] In an exemplary embodiment, two memory cells adjacent to each other in the first direction share a bit line and are symmetrical with respect to the bit line.

[0012] In an exemplary embodiment, a region of the semiconductor layer of the transistor surrounded by the gate is a channel region, a material of the channel region includes single crystal silicon, and an end of the semiconductor layer close to the bit line has a metal silicide contact terminal.

[0013] In an exemplary embodiment, the memory cell further includes a capacitor located along the first direction at one end of the transistor away from the bit line, and the transistor further includes a first electrode and a second electrode located on both sides of the semiconductor layer in the first direction and connected to the semiconductor layer, the first electrode being connected to a first capacitance electrode of the capacitor, and the second electrode being connected to the bit line.

[0014] In an exemplary embodiment, the transistor further includes a gate insulating layer located between the semiconductor layer and the gate.

[0015] In an exemplary embodiment, a first isolation layer is further included, which surrounds one end of the semiconductor layer close to the bit line and is used to separate the word line and the bit line in a first direction.

[0016] In an exemplary embodiment, the device further includes a second isolation layer extending in the first direction and spaced apart between adjacent bit lines along the second direction.

[0017] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a three-dimensional memory, comprising:

[0018] Alternatingly forming sacrificial layers and initial semiconductor layers along a third direction to form a stacked structure;

[0019] Patterning the stacked structure to form a common bit line region and memory cell regions located on both sides of the common bit line region;

[0020] forming a transverse groove extending along a second direction and a through hole extending along a third direction at one end of the memory cell region close to the common bit line region, so as to expose at least a portion of a circumferential sidewall of the initial semiconductor layer;

[0021] By means of the transverse groove and the through hole, a gate surrounding a portion of the circumferential sidewall of the initial semiconductor layer and a word line extending along the second direction are formed;

[0022] A bit line extending along a third direction is formed in the common bit line region.

[0023] In an exemplary embodiment, forming the transverse grooves and the through holes includes:

[0024] forming a groove penetrating the stacked structure and extending along the second direction;

[0025] forming a plurality of through holes penetrating the stacked structure and arranged at intervals along a second direction on both sides of the groove along the first direction;

[0026] The sacrificial layer is laterally etched by means of the trench to form a lateral groove extending along a second direction, wherein the extending direction of the lateral groove is perpendicular to and intersects with the extending direction of the through hole to expose at least a portion of the circumferential sidewall of the initial semiconductor layer.

[0027] In an exemplary embodiment, forming a word line includes:

[0028] Depositing a dielectric material film and a conductive material film in sequence on the exposed surface of the initial semiconductor layer by means of the trenches, the transverse recesses and the through holes;

[0029] Filling the trench, the transverse groove and the through hole with insulating material to cover the conductive material film;

[0030] Re-vertically etching the insulating material at the position of the trench to remove the insulating material, dielectric material film and conductive material film in the trench;

[0031] removing a portion of the conductive material film in the transverse groove along a first direction by etching to form a first isolation trench in the transverse groove;

[0032] filling the exposed first isolation trench with an insulating material to form a first isolation layer;

[0033] The stacked structure is etched downward on a side of the lateral groove away from the common bit line region to expose the sidewall of the sacrificial layer, the sacrificial layer is removed by lateral etching along a first direction, and a portion of the dielectric material film and the conductive material film within the lateral groove is continuously etched away. The etching is stopped when the insulating material within the lateral groove is reached, so that adjacent conductive material films in the third direction within the lateral groove are disconnected, thereby forming a word line.

[0034] In an exemplary embodiment, forming a bit line includes:

[0035] filling the exposed groove with insulating material;

[0036] vertically etching the insulating material in the trench corresponding to a region between two adjacent through holes in the first direction to form a second isolation trench extending along the first direction;

[0037] Laterally etching away the material of the initial semiconductor layer until the gate insulating layers of two adjacent memory cell regions in the first direction are exposed, thereby forming an enlarged second isolation trench;

[0038] filling the second isolation trench with an insulating material to form a second isolation layer;

[0039] vertically etching the insulating material in the trench corresponding to a region between two adjacent transistors in the first direction to form a bit line trench;

[0040] A metal conductive material is deposited in the bit line groove to form a bit line extending along a third direction.

[0041] In an exemplary embodiment, the initial semiconductor layer includes a single crystal silicon layer, and the manufacturing method further includes:

[0042] After forming the bit line trench, metal is deposited on a sidewall of the initial semiconductor layer near one end of the bit line trench, so that a metal silicide contact terminal is formed in a region of the initial semiconductor layer near the bit line trench.

[0043] In yet another aspect, an exemplary embodiment of the present application provides an electronic device including the three-dimensional memory.

[0044] Other features and advantages of the present application will be described in the following description, and in part will become more apparent from the description, or understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0045] Summary of the Figures

[0046] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0047] FIG1A is a schematic diagram of a three-dimensional structure of a three-dimensional memory provided in an exemplary embodiment of the present application;

[0048] FIG1B is a partial schematic plan view of the structure shown in FIG1A ;

[0049] FIG1C is a schematic plan view of a word line in the structure shown in FIG1A ;

[0050] FIG1D is a partial plan view of the structure shown in FIG1A ;

[0051] FIG2 is a schematic vertical cross-sectional view taken along a plane perpendicular to a substrate after forming a stacked structure including a sacrificial layer and an initial semiconductor layer, according to an exemplary embodiment of the present application;

[0052] FIG3A is a perspective schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0053] 3B is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line VV′ in FIG. 3C ;

[0054] 3C is a horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line HH' in FIG. 3B ;

[0055] 4A is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line VV′ in FIG. 4B ;

[0056] 4B is a horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line HH' in FIG. 4A ;

[0057] 5A is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line VV′ in FIG. 5B ;

[0058] 5B is a horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along the cross-sectional line HH' in FIG. 5A ;

[0059] 6A is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line VV′ in FIG. 6B ;

[0060] 6B is a horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line HH′ in FIG. 6A ;

[0061] 7 is a vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application, taken along a plane parallel to the first direction (passing through a bit line).

[0062] Details

[0063] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0064] The embodiments herein can be implemented in a variety of different forms. A person skilled in the art can easily understand that the implementation and content can be transformed into various forms without departing from the purpose and scope of this application. Therefore, this application should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other in any manner.

[0065] The scales of the figures in this application are intended to serve as a reference for actual processes, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing between them can be adjusted according to actual needs. The figures described in this application are merely schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the figures.

[0066] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the words and phrases are not limited to those described in the specification and may be appropriately replaced according to the circumstances.

[0067] In this specification, unless otherwise specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application.

[0068] In the description of this application, ordinal numbers such as "first" and "second" are provided to avoid confusion of constituent elements, rather than to limit the quantity.

[0069] In this specification, the terms "film" and "layer" may be interchanged. For example, "insulating layer" may be replaced with "insulating film".

[0070] In the description of this application, a transistor refers to a component comprising at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the area through which the current mainly flows. In this application, the terms "metal oxide semiconductor channel," "channel," and "semiconductor layer" are interchangeable.

[0071] As used in the embodiments of this application, the term "first direction" X is defined as the direction in which transistors and capacitors are arranged; the term "second direction" Y is defined as a direction intersecting the "first direction" X and parallel to the direction in which the word lines extend; the term "third direction" Z is defined as a direction perpendicular to the plane of the substrate, for example, a direction parallel to the direction in which the bit lines extend; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be shown in Figures 1A, 1B, 1C, and 3A, etc.

[0072] As used in this application, the term "integrated structure" may refer to a microstructural separation between A and B, such as the absence of distinct interfaces such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integral. For example, A and B may be formed from the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0073] The applicant has found that in existing three-dimensional devices made of multi-layer horizontal gate-all-around silicon transistors, the word lines are vertical and the bit lines are horizontal, and the channel lengths of the manufactured gate-all-around transistors are uneven, which affects the current switching ratio.

[0074] The present application provides a three-dimensional memory, comprising:

[0075] A plurality of memory cells stacked at intervals along a third direction, each layer of memory cells comprising a plurality of memory cells arranged at intervals along a second direction, the memory cells comprising transistors, the transistors comprising gates and semiconductor layers extending along a first direction, the gates being disposed around circumferential sidewalls of the semiconductor layers, the first direction intersecting the second direction and both being perpendicular to the third direction;

[0076] a plurality of bit lines extending along a third direction, each of the bit lines being connected to the transistors in a column of the memory cells arranged along the third direction;

[0077] A plurality of word lines extend along a second direction, and the gates of the transistors in a column of the memory cells arranged along the second direction are connected to form one word line.

[0078] Figure 1A is a schematic diagram of a three-dimensional structure of a three-dimensional memory provided in an exemplary embodiment of the present application; Figure 1B is a schematic diagram of a partial plan view of the structure shown in Figure 1A; Figure 1C is a schematic diagram of a word line in the structure shown in Figure 1A; and Figure 1D is another schematic diagram of a partial plan view of the structure shown in Figure 1A. As shown in Figures 1A and 1B, the three-dimensional memory may include:

[0079] A plurality of memory cells are stacked along a third direction Z, each layer of memory cells including a plurality of memory cells arranged along a second direction Y. The memory cells include transistors, each transistor including a gate 60 and a semiconductor layer 50 extending along the first direction, the gate 60 being disposed around a circumferential sidewall of the semiconductor layer 50.

[0080] a plurality of bit lines 90 extending along a third direction Z, each of the bit lines 90 being connected to the transistors in a column of the memory cells arranged along the third direction Z;

[0081] A plurality of word lines 70 extend along the second direction Y, and the gates 60 of the transistors in a column of memory cells arranged along the second direction Y are connected to form one word line 70 .

[0082] The three-dimensional memory of the present application uses horizontal word lines and vertical bit lines, thereby reducing the coupling capacitance between the bit lines, increasing the sense margin, making it easier and more accurate to identify signals, and enhancing device performance.

[0083] The surrounding gate of the three-dimensional memory of the present application is uniformly surrounded, and the length of the effective channel can be accurately and easily defined by the size of the through hole. As shown in Figure 1A, the gate 60 can have a first surface 61 and a second surface 62 opposite to each other in the second direction Y, and a third surface 63 and a fourth surface 64 opposite to each other in the third direction Z. As shown in Figure 3A, the semiconductor layer 50 can have a first side surface 21 and a second side surface 22 opposite to each other in the second direction, and a third side surface 23 and a fourth side surface 24 opposite to each other in the third direction. The gate 60 arranged around the circumferential sidewall of the semiconductor layer 50 can be regarded as the first surface 61, the second surface 62, the third surface 63 and the fourth surface 64 of the gate 60 successively surrounding the first side surface 21, the second side surface 22, the third side surface 23 and the fourth side surface 24 of the semiconductor layer 50, thereby forming a surrounding gate 60 that surrounds the semiconductor layer 50 in the circumferential direction, that is, the gate 60 can be annular.

[0084] 1A and 1B also show that each word line 70 has a plurality of through holes K arranged at intervals along the second direction Y. Each through hole K is located between two adjacent memory cells along the second direction Y. Each through hole is filled with a dielectric material. The formed through holes can be used to form a surrounding gate.

[0085] FIG. 1A shows that two memory cells adjacent to each other in a first direction X share a bit line 90 and are symmetrical with respect to the bit line 90 .

[0086] In an exemplary embodiment, the region of the semiconductor layer of the transistor surrounded by the gate 60 is a channel region, the material of the channel region includes single crystal silicon, and the end of the semiconductor layer 50 close to the bit line 90 may have a metal silicide contact terminal 80 (as shown in Figure 6B).

[0087] Figures 1A and 1B also show that the memory cell may further include a capacitor located along the first direction X at one end of the transistor away from the bit line 90, and the transistor further includes a first electrode 81 and a second electrode 82 located on both sides of the semiconductor layer 50 in the first direction X and connected to the semiconductor layer 50, the first electrode 81 is connected to the first capacitor electrode 83 of the capacitor, and the second electrode 82 is connected to the bit line 90.

[0088] Although the terms "first electrode" and "second electrode" are used herein to refer to two separate and distinct electrodes, it is not intended that the electrodes referred to as "first" and / or "second" electrodes have a unique meaning. It is intended that only one of the electrodes be connected to a bit line, and the other be connected to a first capacitive electrode (e.g., an inner electrode) of a capacitor. For example, the first electrode can be the drain of the transistor and the second electrode can be the source of the transistor; or alternatively, the first electrode can be the source of the transistor and the second electrode can be the drain of the transistor.

[0089] In an exemplary embodiment, the first electrode 81 and the second electrode 82 are independent of each other.

[0090] In an exemplary embodiment, the transistor further includes a gate insulating layer 40 , wherein the gate insulating layer 40 is located between the semiconductor layer 50 and the gate 60 .

[0091] In an exemplary embodiment, the memory may further include a first isolation layer 31 surrounding a side of the semiconductor layer 50 close to the bit line 90 and used to separate the word line 70 from the bit line 90 in the first direction X.

[0092] In an exemplary embodiment, the memory may further include a second isolation layer 32 extending in the first direction X and spaced apart between adjacent bit lines 90 along the second direction Y.

[0093] As shown in FIG1C , a word line 70 may include two vertical portions 71 extending along the second direction and spaced apart in the first direction (illustrated by dashed lines II' and II-II' in FIG1C ), and a plurality of horizontal portions 72 spaced apart along the second direction. Thus, the word lines in the memory provided by the exemplary embodiments of the present application may extend horizontally along the second direction Y and may be ladder-shaped. This word line configuration of the present application may significantly reduce parasitic capacitance and enhance signal strength, thereby enhancing memory performance.

[0094] In this application, the semiconductor layer can be understood as a semiconductor material, and its shape and structure are not emphasized here, only its function is emphasized.

[0095] In an exemplary embodiment, the material of the semiconductor layer may be silicon or polysilicon with a band gap smaller than 1.65 eV, or a wide band gap material, such as a metal oxide material with a band gap larger than 1.65 eV.

[0096] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0097] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. Materials such as the above can be used as long as the leakage current of the transistor can meet the requirements. The specific adjustment can be made according to the actual situation.

[0098] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0099] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0100] In an exemplary embodiment, the electrode material of the gate may be any one or more of the following different types of materials:

[0101] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it may be a metal alloy containing the aforementioned metals;

[0102] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0103] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0104] In an exemplary embodiment, the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The following will exemplarily illustrate the characteristics of the gate insulating layer of the present application.

[0105] Low-K materials, such as silicon oxide.

[0106] High-K materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, they may include oxides of one or more of hafnium, aluminum, lanthanum, and zirconium. For example, they may include, but are not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), and zirconium oxide (ZrO2).

[0107] The technical solution of this application will be further illustrated below using the manufacturing process of a three-dimensional memory device according to an exemplary embodiment of this application. The "patterning process" referred to in this exemplary embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this exemplary embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this exemplary embodiment, it should be understood that a "thin film" refers to a thin film of a certain material deposited on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning or photolithography process contains at least one "pattern."

[0108] In an exemplary embodiment, a three-dimensional DRAM is taken as an example to describe the manufacturing method of the three-dimensional memory of the present application.

[0109] In an exemplary embodiment, a process for manufacturing a three-dimensional DRAM may include:

[0110] S100: forming a laminated structure.

[0111] An exemplary step may include providing a substrate (not shown), and alternately depositing a plurality of sacrificial layer films and a plurality of semiconductor material films on the substrate along a third direction Z to form a stacked structure 1 including a plurality of sacrificial layers 10 and a plurality of initial semiconductor layers 20, as shown in FIG2 . FIG2 is a schematic vertical cross-sectional view of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along a plane perpendicular to the substrate after forming a stacked structure including sacrificial layers and initial semiconductor layers.

[0112] In an exemplary embodiment, the sacrificial layer thin film and the semiconductor material thin film may be grown using an epitaxial growth method.

[0113] In an exemplary embodiment, the substrate may be a single crystal silicon substrate.

[0114] In an exemplary embodiment, the sacrificial layer 10 may be made of SiGe, such as single crystal SiGe.

[0115] In an exemplary embodiment, the initial semiconductor layer 20 may be made of a semiconductor material such as silicon, including single crystal silicon.

[0116] In an exemplary embodiment of the present application, a single crystal stacked structure may be formed by epitaxially growing a plurality of single crystal SiGe layers and a plurality of single crystal silicon layers on a single crystal silicon substrate.

[0117] 2 may include five sacrificial layers 10 and four initial semiconductor layers 20. In other exemplary embodiments, the stacked structure may further include more or fewer sacrificial layers 10 and initial semiconductor layers 20 that are alternately arranged.

[0118] In addition, a hard mask layer may be provided on top of the stacked structure 1 for use in subsequent patterning processes and will be removed after patterning.

[0119] S200: Patterning the stacked structure.

[0120] Exemplary steps may include: providing a common bit line region 100, transistor regions 200 located on both sides of the common bit line region 100, and a capacitor region 300 located on a side of the transistor region 200 away from the common bit line region 100 in the stacked structure (the transistor region and the capacitor region may constitute a memory cell region); forming a trench T1 in the stacked structure by etching, which penetrates the stacked structure and terminates at the upper surface of the substrate and extends along the second direction Y, wherein the trench T1 exposes sidewalls of the sacrificial layer 10 and the initial semiconductor layer 20 along the third direction Z. The region of the trench T1 may correspond to the common bit line region 100, that is, the trench T1 formed here may serve as the common bit line region 100;

[0121] A plurality of through holes K are formed in the stacked structure on both sides of the trench T1, penetrating the stacked structure and terminating at the upper surface of the substrate. The through holes K are arranged at intervals along the second direction Y and extend along the third direction Z. The initial semiconductor layer 20 between two adjacent through holes K in the second direction Y is subsequently used to form the semiconductor layer of each transistor. Each through hole K exposes two opposite sides of the initial semiconductor layer 20 in the second direction Y, namely, a first side surface 21 and an opposite second side surface 22. In the trench T1, each sacrificial layer 10 is laterally etched along the first direction X to form a lateral groove T2 in the sacrificial layer 10. The lateral groove T2 exposes two opposite sides of the initial semiconductor layer 20 in the third direction Z, namely, a third side surface 23 and an opposite fourth side surface 24. The region of the lateral groove T2 may correspond to the transistor region 200. The extension direction of the lateral groove T2 is perpendicular to and intersects with the extension direction of the through hole K. For example, the lateral groove T2 may extend along the first direction and the second direction, as shown in Figures 3A, 3B and 3C. Figure 3A is a three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Figure 3B is a vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along the cross-sectional line VV' in Figure 3C; Figure 3C is a horizontal cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along the cross-sectional line HH' in Figure 3B.

[0122] As shown in Figures 3A and 3C, multiple through holes K (for example, 4 through holes K in Figures A and 3C) formed on each side of the groove T1 can be arranged at equal intervals along the second direction Y, and each through hole K has a dimension M in the first direction X; the lateral groove T2 has a dimension L in the first direction X.

[0123] Figures 3B and 3C also show that the dimension L of the transverse groove T2 in the first direction X is greater than the dimension M of the through hole K in the first direction X. The dimension L of the transverse groove T2 in the first direction X (i.e., the dimension of the transistor region 200 along the first direction X) can be equal to the sum of the dimension M of the through hole K in the first direction X and the dimension N of the areas on both sides of the through hole K along the first direction (i.e., L = M + N + N). This design allows the word lines to extend horizontally along the second direction.

[0124] In an exemplary embodiment, the orthographic projection of each through hole K on a plane parallel to the substrate may be in the shape of a square, rectangle, or other quadrilateral. FIG3C shows that the orthographic projection of the through hole K on the substrate is a square.

[0125] In other exemplary embodiments, the transverse groove T2 may be formed first, and then the through hole K may be formed.

[0126] S300: forming a predetermined gate insulating layer.

[0127] An exemplary step may include: depositing a dielectric material film and a conductive material film in sequence along the inner wall of the trench T1 to cover the sidewalls of each initial semiconductor layer 20 along the third direction Z; depositing a dielectric material film and a conductive material film along the inner wall of the transverse groove T2; depositing a dielectric material film and a conductive material film in sequence along the inner sidewall of the through hole K; the dielectric material film deposited on the inner wall of the transverse groove T2 and extending along the second direction Y intersects with the dielectric material film deposited on the inner sidewall of the through hole K and extending along the third direction Z, forming a dielectric film surrounding the initial semiconductor layer 20. The first and second side surfaces 21 and 22 in the second direction Y and the third and fourth side surfaces 23 and 24 in the third direction Z of the semiconductor layer 10 are provided with a predetermined gate insulating layer 40'; the conductive material film deposited on the inner wall of the transverse groove T2 and extending in the second direction Y intersects with the conductive material film deposited on the inner sidewall of the through hole K and extending in the third direction Z, forming a predetermined gate 60' surrounding the first and second side surfaces 21 and 22 in the second direction Y and the third and fourth side surfaces 23 and 24 in the third direction Z of the semiconductor layer 10, as shown in Figures 4A and 4B. Figure 4A is a vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along the cross-sectional line VV' in Figure 4B; Figure 4B is a horizontal cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along the cross-sectional line HH' in Figure 4A.

[0128] Exemplarily, step S300 can simultaneously deposit a dielectric material film on the inner wall of the trench T1, the inner wall of the lateral groove T2 and the inner side wall of the through hole K through a one-time process, and simultaneously deposit a conductive material film on the inner wall of the trench T1, the inner wall of the lateral groove T2 and the inner side wall of the through hole K through a one-time process.

[0129] As can be seen from Figures 3A, 3B and Figures 4A, 4B, since the dimension L of the lateral groove T2 in the first direction X is greater than the dimension M of the through hole K in the first direction X, the conductive material film deposited on the inner wall of the lateral groove T2 extends along the second direction Y and continues to extend around the through hole K, thereby forming a horizontally extended preset word line.

[0130] In an exemplary embodiment, the dielectric material film and the conductive material film may be deposited by atomic layer deposition (ALD).

[0131] In an exemplary embodiment, the dielectric material may be a material with K≥3.9, including but not limited to silicon oxide, aluminum oxide (Al 2 O 3 ), and hafnium oxide.

[0132] S400: forming a first isolation trench.

[0133] Exemplary steps may include: depositing an insulating material (dielectric material) into the through hole K; depositing an insulating material into the trench T1 and the transverse recess T2 to cover the predetermined word line; then etching away the insulating material, conductive material, and dielectric material within the trench T1, leaving the insulating material within the transverse recess T2, to form an insulating layer 30 within the transverse recess T2; and removing a portion of the conductive material within the transverse recess T2 along a first direction X by wet etching, leaving the dielectric material within the transverse recess T2, thereby forming a first isolation trench T3 between the insulating layer 30 and the predetermined gate insulating layer 40' in each sacrificial layer 10. The first isolation trench T3 has a dimension S in the first direction X, as shown in Figures 5A and 5B. Figure 5A is a vertical cross-sectional view of an intermediate product obtained from an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line VV' in Figure 5B; and Figure 5B is a horizontal cross-sectional view of an intermediate product obtained from an intermediate step of a method for manufacturing a three-dimensional memory device according to an exemplary embodiment of the present application, taken along the cross-sectional line HH' in Figure 5A.

[0134] S500: forming a bit line.

[0135] Exemplary steps may include: depositing an insulating material into the first isolation trench T3 to form a first isolation layer 31, the first isolation layer 31 may be used to prevent a subsequently formed word line from being electrically connected to a bit line, i.e., electrically insulating; depositing an insulating material into the trench T1 again and filling the trench T1; at a position between two through holes K arranged along the first direction (i.e., position A1), vertically etching along a third direction to completely remove the insulating material to form a second isolation trench T4; at each initial semiconductor layer 20, laterally etching the initial semiconductor layer 20 along the first direction X until reaching the position of the preset gate insulating layer 40', exposing the preset gate insulating layers 40' of the two adjacent transistors, so as to form a gate insulating layer 40' extending into the initial semiconductor layer 20 at each initial semiconductor layer 20. An expanded second isolation trench T4 is provided; an insulating layer material is deposited into the second isolation trench T4 to form a second isolation layer 32, so that the size of the second isolation layer 32 located at the initial semiconductor layer 20 along the first direction X is larger than the size of the second isolation layer 32 located at the sacrificial layer 10 along the first direction X. This structural design can separate the initial semiconductor layer 20 in the second direction Y; at a position between adjacent second isolation layers 32 in the second direction Y (i.e., position B1), i.e., in the bit line to be formed area, the insulating material in the bit line to be formed area B1 is etched vertically downward along the third direction Z to form a bit line trench T5; a bit line material, such as a metal material, is deposited into the bit line trench T5 to form a bit line 90 extending along the third direction Z, as shown in Figures 6A and 6B. Figure 6A is a vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along the cross-sectional line VV' in Figure 6B; Figure 6B is a horizontal cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along the cross-sectional line HH' in Figure 6A.

[0136] As shown in FIG. 6B , at each preliminary semiconductor layer 20 , a dimension of the second isolation trench T4 along the first direction X is greater than a dimension of the bit line trench T5 along the first direction X.

[0137] In other exemplary embodiments, after forming the bit line trench T5, metal may be deposited on the sidewalls of each initial semiconductor layer 20 to form a metal silicide contact terminal 80 in the region of the initial semiconductor layer 20 adjacent to the bit line trench T5. Finally, a bit line material, such as a metal material, may be filled into the bit line trench T5 to form a bit line 90. This structural design allows the metal silicide region to form an ohmic contact with the bit line, thereby reducing the contact resistance between the semiconductor layer and the bit line.

[0138] S600: forming word lines.

[0139] Exemplary steps may include: forming two trenches (not shown) penetrating the stacked structure in the capacitor region 300 of the stacked structure; laterally etching the sacrificial layer along a first direction X, and continuing to etch away the material of the predetermined gate insulating layer and the predetermined gate until the etching reaches the insulating layer 30 and stops, thereby disconnecting the predetermined gate insulating layer in a third direction, thereby forming a gate insulating layer 40, and disconnecting the predetermined word line in the third direction, thereby forming a word line 70, as shown in FIG7 . FIG7 is a schematic vertical cross-sectional view of an intermediate product obtained by an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application, taken along a plane parallel to the first direction (through the bit line).

[0140] Subsequent steps may include forming a first capacitor electrode (e.g., an inner electrode) surrounding the initial semiconductor layer 20 in the capacitor region 300, and depositing a dielectric material film and a conductive material film around the inner electrode to form a dielectric layer of the capacitor and a second capacitor electrode (e.g., an outer electrode) to form a capacitor and complete the manufacture of a three-dimensional memory.

[0141] The exemplary embodiment of the present application further provides a method for manufacturing a three-dimensional memory, which may include:

[0142] S1000: alternately forming sacrificial layers and initial semiconductor layers along a third direction to form a stacked structure;

[0143] S1100: patterning the stacked structure to form a common bit line region and memory cell regions located on both sides of the common bit line region;

[0144] S1200: forming a transverse groove extending along a second direction and a through hole extending along a third direction on a side of the memory cell region close to the common bit line region, so as to expose at least a portion of a circumferential sidewall of the initial semiconductor layer;

[0145] S1300: forming a gate surrounding a portion of the circumferential sidewall of the initial semiconductor layer and a word line extending along the second direction by means of the lateral groove and the through hole; and

[0146] S1400 : forming a bit line extending along a third direction in the common bit line region.

[0147] The three-dimensional memory of the embodiment of the present application can be obtained by manufacturing as described above.

[0148] In an exemplary embodiment, the step ( S1200 ) of forming the transverse groove and the through hole may include:

[0149] forming a groove penetrating the stacked structure and extending along the second direction;

[0150] forming a plurality of through holes penetrating the stacked structure and arranged at intervals along a second direction on both sides of the groove along the first direction;

[0151] The sacrificial layer is laterally etched by means of the trench to form a lateral groove extending along a second direction, wherein the extending direction of the lateral groove is perpendicular to and intersects with the extending direction of the through hole to expose at least a portion of the circumferential sidewall of the initial semiconductor layer.

[0152] In an exemplary embodiment, the step S1300 of forming a word line may include:

[0153] Depositing a dielectric material film and a conductive material film in sequence on the exposed surface of the initial semiconductor layer by means of the trenches, the transverse recesses and the through holes;

[0154] Filling the trench, the transverse groove and the through hole with insulating material to cover the conductive material film;

[0155] Re-vertically etching the insulating material at the position of the trench to remove the insulating material, dielectric material film and conductive material film in the trench;

[0156] removing a portion of the conductive material film in the transverse groove along a first direction by etching to form a first isolation trench in the transverse groove;

[0157] filling the exposed first isolation trench with an insulating material to form a first isolation layer;

[0158] The stacked structure is etched downward on a side of the lateral groove away from the common bit line region to expose the sidewall of the sacrificial layer, the sacrificial layer is removed by lateral etching along a first direction, and a portion of the dielectric material film and the conductive material film within the lateral groove is continuously etched away. The etching is stopped when the insulating material within the lateral groove is reached, so that adjacent conductive material films in the third direction within the lateral groove are disconnected, thereby forming a word line.

[0159] In an exemplary embodiment, the step S1400 of forming a bit line may include:

[0160] filling the exposed groove with insulating material;

[0161] vertically etching the insulating material in the trench corresponding to a region between two adjacent through holes in the first direction to form a second isolation trench extending along the first direction;

[0162] Laterally etching away the material of the initial semiconductor layer until the gate insulating layers of two adjacent memory cell regions in the first direction are exposed, thereby forming an enlarged second isolation trench;

[0163] filling the second isolation trench with an insulating material to form a second isolation layer;

[0164] vertically etching the insulating material in the trench corresponding to a region between two adjacent transistors in the first direction to form a bit line trench;

[0165] A metal conductive material is deposited in the bit line groove to form a bit line extending along a third direction.

[0166] In an exemplary embodiment, the initial semiconductor layer includes a single crystal silicon layer, and the manufacturing method further includes:

[0167] After forming the bit line trench, metal is deposited on a sidewall of the initial semiconductor layer near one end of the bit line trench, so that a metal silicide contact terminal is formed in a region of the initial semiconductor layer near the bit line trench.

[0168] The exemplary embodiments of the present application further provide an electronic device, comprising the three-dimensional memory provided by the exemplary embodiments of the present application above.

[0169] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0170] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A three-dimensional memory, comprising: A plurality of memory cells stacked at intervals along a third direction, each layer of memory cells comprising a plurality of memory cells arranged at intervals along a second direction, the memory cells comprising transistors, the transistors comprising gates and a semiconductor layer extending along a first direction, the gates surrounding a circumferential side wall of the semiconductor layer, the first direction intersecting with the second direction and both being perpendicular to the third direction; a plurality of bit lines extending along the third direction, each of the bit lines being connected to the transistors in a column of the memory cells arranged along the third direction; A plurality of word lines extend along a second direction, and gates of the transistors in a column of the memory cells arranged along the second direction are connected to form one word line.

2. The three-dimensional memory according to claim 1, wherein along the second direction, each of the word lines has a plurality of through holes arranged at intervals, and each of the through holes is located between two adjacent memory cells along the second direction, and each of the through holes is filled with a dielectric material. 3 . The three-dimensional memory according to claim 1 , further comprising an insulating layer between two of the word lines adjacent to each other in the third direction. 4 . The three-dimensional memory according to claim 1 , wherein two memory cells adjacent to each other in the first direction share a bit line and are symmetrical with respect to the bit line. 5 . The three-dimensional memory according to claim 1 , wherein a region of the semiconductor layer of the transistor surrounded by the gate is a channel region, a material of the channel region comprises single crystal silicon, and an end of the semiconductor layer close to the bit line has a metal silicide contact terminal.

6. According to the three-dimensional memory according to claim 1, the storage unit also includes a capacitor located along the first direction at one end of the transistor away from the bit line, and the transistor also includes a first electrode and a second electrode located on both sides of the semiconductor layer in the first direction and connected to the semiconductor layer, the first electrode is connected to the first capacitor electrode of the capacitor, and the second electrode is connected to the bit line. 7 . The three-dimensional memory according to claim 1 , wherein the transistor further comprises a gate insulating layer, wherein the gate insulating layer is located between the semiconductor layer and the gate. 8 . The three-dimensional memory according to claim 1 , further comprising a first isolation layer surrounding a side of the semiconductor layer close to the bit line and used to separate the word line from the bit line in a first direction. 9 . The three-dimensional memory according to claim 1 , further comprising a second isolation layer extending in the first direction and arranged between adjacent bit lines at intervals along the second direction.

10. A method for manufacturing a three-dimensional memory, comprising: Alternatingly forming sacrificial layers and initial semiconductor layers along a third direction to form a stacked structure; Patterning the stacked structure to form a common bit line region and storage cell regions located on both sides of the common bit line region; On a side of the memory cell region close to the common bit line region, a lateral groove extending along the second direction and a through hole extending along the third direction are formed to expose at least a portion of the circumferential sidewall of the initial semiconductor layer; By means of the lateral groove and the through hole, a gate surrounding a portion of the circumferential side wall of the initial semiconductor layer and a word line extending along the second direction are formed; A bit line extending along a third direction is formed in the common bit line region.

11. The manufacturing method according to claim 10, forming the lateral groove and the through hole comprises: forming a groove penetrating the stacked structure and extending along the second direction; A plurality of through holes are formed on both sides of the groove along the first direction, penetrating the stacked structure and arranged at intervals along the second direction; The sacrificial layer is laterally etched by means of the groove to form a lateral groove extending along the second direction, wherein the extending direction of the lateral groove is perpendicular to and intersects with the extending direction of the through hole to expose at least part of the circumferential side wall of the initial semiconductor layer.

12. The manufacturing method according to claim 11, forming the word line comprises: Depositing a dielectric material film and a conductive material film in sequence on the exposed surface of the initial semiconductor layer by means of the trench, the lateral groove and the through hole; Filling the trench, the lateral groove and the through hole with insulating material to cover the conductive material film; Re-etching the insulating material vertically at the position of the groove to remove the insulating material, dielectric material film and conductive material film in the groove; Removing a portion of the conductive material film in the transverse groove along a first direction by etching to form a first isolation groove in the transverse groove; Filling the exposed first isolation groove with insulating material to form a first isolation layer; The stacked structure is etched downward on a side of the lateral groove away from the common bit line area to expose the side wall of the sacrificial layer, the sacrificial layer is removed by lateral etching along a first direction, and a portion of the dielectric material film and the conductive material film in the lateral groove is continued to be etched away, and the etching is stopped when the insulating material in the lateral groove is reached, so that the conductive material films adjacent to each other in the third direction in the lateral groove are disconnected, thereby forming a word line.

13. The manufacturing method according to claim 12, forming the bit line comprises: Filling the exposed groove with insulating material; Vertically etching the insulating material in the trench corresponding to a region between two adjacent through holes in the first direction to form a second isolation trench extending along the first direction; Laterally etching and removing the material of the initial semiconductor layer until the gate insulating layers of two adjacent memory cell regions in the first direction are exposed to form an enlarged second isolation trench; filling the expanded second isolation trench with an insulating material to form a second isolation layer; Vertically etching the insulating material in the trench corresponding to a region between two adjacent memory cell regions in a first direction to form a bit line trench; A metal conductive material is deposited in the bit line groove to form a bit line extending along a third direction.

14. The manufacturing method according to claim 13, wherein the initial semiconductor layer comprises a single crystal silicon layer, and the manufacturing method further comprises: After forming the bit line groove, metal is deposited on the side wall of the initial semiconductor layer near one end of the bit line groove, so that a metal silicide contact terminal is formed in the region of the initial semiconductor layer near the bit line groove.

15. An electronic device comprising the three-dimensional memory according to any one of claims 1 to 9.

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