Method for manufacturing semiconductor apparatus

Abstract

The present disclosure provides a method for manufacturing a semiconductor apparatus. The semiconductor apparatus comprises a first region in which multiple flash memory cells are formed, and a second region in which a metal oxide semiconductor (MOS) transistor is formed; each flash memory cell comprises two storage transistors, and a gate transistor disposed between the two storage transistors. The method for manufacturing a semiconductor apparatus according to the present disclosure comprises: providing a semiconductor substrate and forming an isolation structure therein; forming a storage transistor storage gate dielectric stack and first gate electrode layer; forming a storage transistor gate structure by means of patterning the storage gate dielectric stack and the first gate electrode layer; concurrently forming a gate dielectric layer and a second gate electrode layer of gating transistors and MOS transistors; and concurrently forming a MOS transistor gate structure and a gating transistor gate structure. According to the method for manufacturing a semiconductor device of the present disclosure, a non-volatile memory (NVM) transistor can be integrated into a manufacturing process for a MOS transistor.

Description

Method for manufacturing a semiconductor device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device including an integrally formed non-volatile memory (NVM) transistor and a metal oxide semiconductor (MOS) transistor. Background Art

[0002] Flash memory, also known as flash memory, is a type of non-volatile memory (NVM). This means that stored data remains intact even when the power is disconnected, making it particularly suitable for applications such as mobile communications and computer storage. Some flash memory also has high-density storage capabilities, making it suitable for use as large-capacity mobile storage media.

[0003] Traditional flash memory uses a floating gate cell structure or a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) cell structure. However, both existing floating gate and SONOS flash memory suffer from limitations in process scaling, large cell area, high write power consumption, and high array area overhead, hindering high-density integration exceeding gigabit (Gb) capacity.

[0004] Furthermore, for many applications such as system-on-chips, it is desirable to integrate metal oxide semiconductor (MOS) transistors and NVM transistors on a single chip or substrate. However, such integration severely impacts the manufacturing processes of the MOS and NVM transistors.

[0005] MOS transistors are typically manufactured using a benchmark complementary metal oxide semiconductor (CMOS) process flow, which involves the formation and patterning of conductor, semiconductor, and dielectric materials. The combination of these materials, the combination and concentration of processing reagents, and the temperature used in the CMOS process flow are strictly controlled for each process step to ensure that the resulting MOS transistor operates properly.

[0006] In addition, the NVM transistor includes a gate dielectric stack, which typically includes two oxide layers and a nitride layer or an oxynitride layer sandwiched between them. The materials and processes for manufacturing these two oxide layers are typically different from those of the baseline CMOS process flow, and therefore may adversely affect the manufacture of the MOS transistor or be affected by the manufacture of the MOS transistor.

[0007] Therefore, the integration of NVM transistors and MOS transistors can severely impact the baseline CMOS process flow and typically requires a large number of mask setups and processing steps, which increases manufacturing costs and reduces production efficiency.

[0008] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art.

[0009] Summary of the Invention

[0010] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel method for manufacturing a semiconductor device including an integrally formed non-volatile memory (NVM) transistor and a metal oxide semiconductor (MOS) transistor.

[0011] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The semiconductor device includes a first region in which a plurality of flash memory cells are formed and a second region in which metal oxide semiconductor (MOS) transistors are formed, and each flash memory cell includes two storage transistors and a gate transistor disposed between the two storage transistors. The method for manufacturing a semiconductor device according to the present disclosure includes: providing a semiconductor substrate and forming an isolation structure therein; forming a storage gate dielectric stack and a first gate electrode layer of the storage transistor; forming a gate structure of the storage transistor by patterning the storage gate dielectric stack and the first gate electrode layer; concurrently forming a gate dielectric layer and a second gate electrode layer of the gate transistor and the MOS transistor; and concurrently forming a gate structure of the MOS transistor and a gate structure of the gate transistor.

[0012] According to an embodiment of the present disclosure, the method for manufacturing a semiconductor device may further include replacing the gate structure of the MOS transistor and / or the gate transistor with a high-K gate dielectric layer and a metal gate.

[0013] According to the method for manufacturing a semiconductor device of the present disclosure, a non-volatile memory (NVM) transistor can be integrated into a manufacturing process of a MOS transistor.

[0014] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0016] FIG. 1 is a cross-sectional view illustrating a flash memory cell according to an embodiment of the present disclosure.

[0017] FIG. 2 is an equivalent circuit diagram illustrating a flash memory cell according to an embodiment of the present disclosure.

[0018] 3 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 4A to 4N are cross-sectional views illustrating a semiconductor device in respective steps of the method for manufacturing a semiconductor device shown in FIG.

[0019] FIG. 5 is a cross-sectional view illustrating a flash memory cell according to an alternative embodiment of the present disclosure.

[0020] FIG. 6 is a flowchart illustrating a method for manufacturing a semiconductor device according to an alternative embodiment of the present disclosure.

[0021] 7A to 7O are cross-sectional views illustrating the semiconductor device in respective steps of the method for manufacturing the semiconductor device shown in FIG. 6 . DETAILED DESCRIPTION

[0022] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the present invention, the specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0023] For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Although terms such as "first," "second," and the like may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0024] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "a" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise" and / or "comprising" mean that there are stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to account for the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0026] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout, the same reference numerals represent the same elements. Furthermore, in the accompanying drawings, for clarity of illustration, the various components are not necessarily drawn to ratio, and the ratios and sizes of the various components may be exaggerated.

[0027] Embodiments of a method for manufacturing a semiconductor device by integrating a non-volatile memory (NVM) transistor into a complementary metal oxide semiconductor (CMOS) manufacturing process or process flow including a metal oxide semiconductor (MOS) transistor are described herein with reference to the accompanying drawings. However, a particular embodiment may not use one or more of these specific details, or may be implemented in combination with other known methods, materials, and devices. In the following description, many specific details such as specific materials, dimensions, and process parameters are set forth to provide a thorough understanding of the present invention. In the embodiments, well-known semiconductor design and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the present invention. References to "embodiments" throughout the specification mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrase "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment of the present disclosure. In addition, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] The embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings.

[0029] Fig. 1 shows a cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure. Fig. 2 shows an equivalent circuit diagram of the flash memory cell MC 100 according to an embodiment of the present disclosure.

[0030] As shown in FIG. 1 , a flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a memory well region CPW 102 of a first doping type disposed on the deep well region DNW 103 .

[0031] Although the first doping type is defined as P type and the second doping type is defined as N type as an example herein, the present disclosure is not limited thereto. In an alternative embodiment of the present disclosure, the first doping type may also be N type, in which case the second doping type may be P type.

[0032] According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

[0033] 1 and 2 , flash memory cell MC100 includes a first memory transistor MS110, a gate transistor MG120, and a second memory transistor MD130, which are sequentially connected in series. The first memory transistor MS110 may be disposed on a memory well region CPW102 and store first data DATA1. The second memory transistor MD130 may be disposed on the memory well region CPW102 and store second data DATA2. The gate transistor MG120 is disposed between the first memory transistor MS110 and the second memory transistor MD130 along a horizontal direction DR1 on the memory well region CPW102 to isolate the first memory transistor MS110 and the second memory transistor MD130 and perform a gate operation on the first memory transistor MS110 and the second memory transistor MD130.

[0034] According to an embodiment of the present disclosure, the flash memory cell MC100 includes two storage transistors MS110 and MD130, so the flash memory cell MC100 can implement a two-bit storage function, that is, simultaneously store the first data DATA1 and the second data DATA2.

[0035] In addition, as shown in Figure 1, the source region of the first storage transistor MS110 is connected to the first electrode S of the flash memory cell MC100, which can also be referred to as the source S of the flash memory cell MC100, and the drain region of the second storage transistor MD130 is connected to the second electrode D of the flash memory cell MC100, which can also be referred to as the drain D of the flash memory cell MC100.

[0036] Those skilled in the art should recognize that the source and drain of a flash memory cell are defined herein for ease of description; however, the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" can be used interchangeably under different operating conditions.

[0037] 1 , the first storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask stopper 117, which are sequentially arranged along a vertical direction DR2. The gate dielectric stack 112 includes a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115, which are sequentially stacked along the vertical direction. Furthermore, the second storage transistor MD130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask stopper 137, which are sequentially arranged along the vertical direction DR2. The gate dielectric stack 132 includes a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135, which are sequentially stacked along the vertical direction.

[0038] According to an embodiment of the present disclosure, as shown in FIG1 , a flash memory cell MC100 for two-bit storage may be composed of three closely arranged transistors, namely, a gate transistor MG120 located in the middle of the flash memory cell MC100, a first storage transistor MS110 located at a first end of the flash memory cell MC100, and a second storage transistor MD130 located at a second end of the flash memory cell MC100.

[0039] As shown in FIG1 , flash memory cell MC100 may be formed on a memory well region CPW 102 within a semiconductor substrate 101. Furthermore, to isolate memory well region CPW 102 from substrate 101 and facilitate application of a voltage to memory well region CPW 102 under certain operating conditions, memory well region CPW 102 may be formed within a deep well region DNW 103, as shown in FIG1 .

[0040] As shown in FIG1 , a source region 140 formed by N-type doping is provided at a first end of flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at a second end of flash memory cell MC 100. Source region 140 is connected to an overlying metal source electrode 142, i.e., a first electrode S, via a contact hole 141, and drain region 150 is connected to an overlying metal drain electrode 152, i.e., a second electrode D, via a contact hole 151.

[0041] According to an embodiment of the present disclosure, the first electrode S and the second electrode D may include metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of metal, they may include at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0042] As described above, as shown in FIG1 , the gate structure of the first storage transistor MS110 may include, from bottom to top, a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask stopper 117 for sidewall self-alignment. According to embodiments of the present disclosure, the gate electrode 116 may comprise, for example, polysilicon, a metal gate, a metal silicide, or a combination thereof. According to embodiments of the present disclosure, the hard mask stopper 117 may comprise, for example, silicon oxide, silicon nitride, silicon glass, amorphous silicon, or a combination thereof.

[0043] 1 , the gate dielectric stack 112 includes a first oxide layer (tunneling oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115, which are stacked in sequence along a vertical direction. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide.

[0044] According to embodiments of the present disclosure, the storage medium layer 114 may include one or more layers of storage medium. Furthermore, according to embodiments of the present disclosure, the storage medium forming the storage medium layer 114 may include: a monovalent or polyvalent oxide, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium aluminum oxide; a monovalent or polyvalent nitride, such as silicon nitride; a monovalent or polyvalent oxynitride, such as silicon oxynitride; polycrystalline silicon or nanocrystals; or a combination of the foregoing materials.

[0045] According to an embodiment of the present disclosure, when the storage dielectric layer 114 is formed of, for example, silicon nitride, the first oxide layer 113, the storage dielectric layer 114, and the second oxide layer 115 may form a gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage dielectric. In this case, the first storage transistor MS110 may be a SONOS-type storage transistor.

[0046] In addition, according to an embodiment of the present disclosure, the first storage transistor MS110 can be another trapped charge capture type storage transistor having an operating mechanism similar to that of a traditional SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type storage transistor. This type of storage transistor uses a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc., instead of silicon nitride in the SONOS memory as the storage dielectric layer 114.

[0047] In addition, according to an embodiment of the present disclosure, the first storage transistor MS110 may also be a floating gate type storage transistor. This type of storage transistor uses polysilicon instead of silicon nitride in a SONOS memory to form a floating gate for storing charges as the storage dielectric layer 114 .

[0048] In addition, according to an embodiment of the present disclosure, the first storage transistor MS110 may also be a nano-crystal memory transistor. This type of memory transistor uses nanocrystals with quantum dots instead of silicon nitride in a SONOS memory as the storage medium layer 114 .

[0049] According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first storage transistor MS110 can be defined by the length of the hard mask stopper 117 disposed on the gate electrode 116 through a self-aligned process. Those skilled in the art should note that the "length" mentioned herein refers to the size of the stated object in the horizontal direction DR1, and the "thickness" mentioned herein refers to the size of the stated object in the vertical direction DR2.

[0050] According to an embodiment of the present disclosure, the second storage transistor MD130 has the same structure as the first storage transistor MS110 except that it is disposed on the opposite side of the selection transistor MG120 and can be manufactured by the same process as the first storage transistor MS110. Therefore, for the sake of brevity, a detailed description of the structure of the second storage transistor MD130 will be omitted here.

[0051] The gate structure of the gate transistor MG 120 may include, from bottom to top, a channel region 121, a gate dielectric layer 122, a gate electrode 123, and a metal silicide 126. According to an embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to the word line, and the length of the gate electrode 123 is determined by the process size of the photolithography process. According to an embodiment of the present disclosure, the gate dielectric layer 122 may include, for example, silicon oxide, silicon oxynitride, hafnium oxide, or a combination of the above materials. In addition, according to an embodiment of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the above materials. It should be noted that the gate structure of the gate transistor MG 120 includes the metal silicide 126 disposed above the gate electrode 123 only when the gate electrode 123 is formed of polysilicon.

[0052] According to an embodiment of the present disclosure, the channel regions 111, 131, and 121 of the first storage transistor MS110, the second storage transistor MD130, and the selection transistor MG120 may all have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may be lower than the doping concentration of the channel region 121 of the selection transistor MG120.

[0053] Furthermore, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second storage transistors MS110 and MD130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

[0054] For example, as shown in FIG1 , when the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 are lower than the doping concentration of the P-type channel 121 of the gate transistor MG120. In addition, according to an embodiment of the present disclosure, the channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

[0055] According to an embodiment of the present disclosure, the flash memory cell MC100 further includes: a first isolation portion 124, which is arranged between the first storage transistor MS110 and the selection transistor MG120 along the horizontal direction DR1, and is used to isolate the gate electrode 116 of the first storage transistor MS110 and the gate electrode 123 of the selection transistor MG120; and a second isolation portion 125, which is arranged between the selection transistor MG120 and the second storage transistor MD130 along the horizontal direction DR1, and is used to isolate the gate electrode 123 of the selection transistor MG120 and the gate electrode 136 of the second storage transistor MD130.

[0056] Specifically, as shown in FIG1 , a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls are provided on both sides of the gate electrode 123 of the gate transistor MG 120. These isolation portions are respectively used to electrically isolate the gate electrode 116 of the first memory transistor MS 110 and the gate electrode 136 of the second memory transistor MD 130 at specific isolation gap lengths. According to an embodiment of the present disclosure, the first isolation portion 124 and the second isolation portion 125 may comprise the same material as the gate dielectric layer 122.

[0057] 2 , the flash memory cell MC100 includes a first memory transistor MS110, a gate transistor MG120, and a second memory transistor MD130 sequentially connected in series. The gate transistor MG120 can isolate the first memory transistor MS110 and the second memory transistor MD130 and perform a gating operation on the first memory transistor MS110 and the second memory transistor MD130.

[0058] The flash memory cell according to the embodiment of the present disclosure can implement two storage transistors in one flash memory cell, thereby greatly reducing the equivalent area of ​​each storage bit, thereby achieving lower cost and higher integration density.

[0059] In addition, the storage transistor in the flash memory cell according to the embodiment of the present disclosure can use a simple SONOS device structure, which has the advantages of simple process, low gate electrode operating voltage, and good data retention reliability.

[0060] In addition, in the flash memory cell according to the embodiment of the present disclosure, the mutual influence of the two storage bits is isolated by the selection transistor, and the distribution width and lateral diffusion of the storage charge are suppressed, so that a higher storage charge density can be obtained in the silicon nitride storage layer, significantly improving the storage window and data reliability.

[0061] In particular, the equivalent channel length of the flash memory cell according to an embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the gate transistor, and the second storage transistor.

[0062] Furthermore, in a flash memory array comprised of flash memory cells according to embodiments of the present disclosure, for flash memory cells not selected for operation, the gate electrodes of the selection transistor and the first and second storage transistors are all grounded, thereby completely shutting off the entire series channel of the flash memory cell and increasing the equivalent channel length. This prevents source-drain punchthrough of the flash memory cell under high operating voltage conditions at smaller process feature sizes, thereby overcoming the problem that the gate electrode length of existing flash memory cells cannot be reduced as the process feature sizes are reduced. Therefore, the flash memory cell according to embodiments of the present disclosure has better process scaling capabilities, thereby enabling a smaller cell area and manufacturing cost to be achieved by reducing the process feature sizes.

[0063] Furthermore, in the flash memory cell according to the embodiments of the present disclosure, by reducing the doping concentration of the P-type channel regions of the first and second storage transistors or designing them as N-type doped channel regions, the threshold voltage of the storage transistors and the gate electrode operating voltage during erase and read operations can be reduced, thereby improving the reliability of the storage transistors. Simultaneously, by increasing the doping concentration of the P-type channel region of the select transistor, the punch-through voltage of the flash memory cell can be increased, reducing the leakage current between the source and drain regions of the unselected flash memory cells.

[0064] Next, a method for manufacturing a semiconductor device according to an embodiment of the present disclosure will be described with reference to FIG3 and FIG4A to FIG4N. FIG3 shows a flowchart of a method 300 for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG4A to FIG4N show cross-sectional views of a semiconductor device at various steps of the method 300 for manufacturing a semiconductor device shown in FIG3.

[0065] 3 , in step S301, as shown in FIG4A , a wafer serving as a substrate 401 is provided. According to an embodiment of the present disclosure, the wafer may be a wafer of a first doping type serving as a semiconductor substrate, such as a silicon substrate. According to an embodiment of the present disclosure, the first doping type may be defined as P-type, and the second doping type may be defined as N-type. However, those skilled in the art will recognize that the present disclosure is not limited thereto, and that the first doping type may also be N-type, in which case the second doping type may be P-type.

[0066] As shown in FIG4A , the wafer may be pre-processed, for example, by sequentially providing a liner layer 402 formed of, for example, silicon oxide and a cap layer 403 formed of, for example, silicon nitride on a substrate 401, wherein the liner layer 402 may be used to reduce the stress of the cap layer 403. According to an embodiment of the present disclosure, the liner layer 402 may be formed by, for example, thermal oxidation, in-situ water vapor oxidation (ISSG) or a deposition process, and its thickness is typically 10 nm to 100 nm. In addition, according to an embodiment of the present disclosure, the cap layer 403 may be formed by a deposition process, such as a commonly used low-pressure chemical vapor deposition process (LPCVD), and its thickness is typically 20 nm to 200 nm.

[0067] 3 , in step S302, as shown in FIG4B , according to an embodiment of the present disclosure, a plurality of isolation structures 404 defining active regions may be formed in the substrate 401 by active region patterning. According to an embodiment of the present disclosure, the isolation structures 404 may divide the substrate 401 into a first region NVMR in which the flash memory cells are disposed and a second region MOSR adjacent to the first region NVMR in which metal oxide semiconductor (MOS) transistors are disposed.

[0068] According to an embodiment of the present disclosure, the flash memory cell set in the first region NVMR can correspond to, for example, the flash memory cell MC100 described above with reference to Figures 1 and 2, that is, it includes two storage transistors, for example, the first storage transistor MS110 and the second storage transistor MD130 described above with reference to Figures 1 and 2, and a selection transistor, for example, the selection transistor MG120 described above with reference to Figures 1 and 2.

[0069] According to an embodiment of the present disclosure, a flash memory array composed of a plurality of flash memory cells similar to the flash memory cells MC100 described above with reference to FIG. 1 and FIG. 2 may be provided in the first NVMR region of the semiconductor device. Furthermore, although not shown in the figures, according to an embodiment of the present disclosure, each column of flash memory cells in the flash memory array provided in the first NVMR region may also be isolated from adjacent columns of flash memory cells by an isolation structure 404.

[0070] According to an embodiment of the present disclosure, the MOS transistors disposed in the second region MOSR may be one or more of a low-voltage LV-MOS transistor, an interface IO-MOS transistor, or a high-voltage HV-MOS transistor. According to an embodiment of the present disclosure, the MOS transistors in the second region MOSR may constitute a peripheral circuit for the flash memory cell array in the first region NVMR.

[0071] In addition, according to an embodiment of the present disclosure, the MOS transistor disposed in the second region MOSR may also be isolated from adjacent MOS transistors by the isolation structure 404 .

[0072] According to an embodiment of the present disclosure, the active area patterning of the first NVMR region and the second MOSR region can be simultaneously achieved through a single photolithography process using the same active area mask layer. Alternatively, the active area patterning of the first NVMR region and the second MOSR region can also be achieved through two photolithography processes using different active area mask layers.

[0073] Although as shown in FIG4B , according to an embodiment of the present disclosure, the isolation structure 404 can be implemented by a shallow trench isolation (STI) process, the present disclosure is not limited thereto. Those skilled in the art will recognize that the isolation structure can also be implemented by any isolation process commonly used in integrated circuit processes, such as a local oxidation isolation (LOCOS) process.

[0074] For example, according to an embodiment of the present disclosure, the isolation structure 404 can be formed by an STI process. Specifically, the STI process may include: sequentially removing a portion of the cap layer 403 and a portion of the liner layer 402 by an etching process to form a shallow trench structure having a specific depth in the substrate 401; filling the substrate surface with an isolation dielectric layer or a multi-layer composite isolation dielectric layer such as silicon oxide, silicon nitride, and / or polysilicon by a thermal oxidation or low-pressure deposition process; and removing the isolation dielectric layer, the cap layer 403, and the liner layer 402 by a chemical mechanical polishing (CMP) process and / or an etching process to obtain a flat surface of the substrate 401.

[0075] According to an embodiment of the present disclosure, the isolation structures 404 in the first NVMR region and the second MOSR region can be implemented through a single isolation process. Alternatively, the isolation structures 404 in the first NVMR region and the second MOSR region can be implemented through two isolation processes, respectively, to form isolation structures 404 having different widths or depths in the first NVMR region and the second MOSR region, respectively.

[0076] Subsequently, referring to FIG3 , in step S303 , as shown in FIG4C , according to an embodiment of the present disclosure, a well region of a flash memory cell, such as a deep well region DNW and a storage well region CPW, may be formed in the first region NVMR through a first implantation process. According to an embodiment of the present disclosure, the deep well region DNW of the flash memory cell may correspond to, for example, the deep well region DNW 103 of the second doping type described above with reference to FIG1 , and the storage well region CPW of the flash memory cell may correspond to, for example, the storage well region CPW 102 of the first doping type described above with reference to FIG1 . Furthermore, according to an embodiment of the present disclosure, the MOS transistor of the second region MOSR may also be disposed in the deep well region DNW.

[0077] 4C , according to an embodiment of the present disclosure, a first channel layer 405 of a flash memory cell may be formed in the first region NVMR by a first implantation process. According to an embodiment of the present disclosure, the first channel layer 405 of the flash memory cell may be used to subsequently form, for example, the channel region 111 of the first storage transistor MS110, the channel region 121 of the gate transistor MG120, and the channel region 131 of the second storage transistor MD130 described above with reference to FIG. 1 .

[0078] According to an embodiment of the present disclosure, the first implantation process may include at least one of the following process steps: first well region implantation, first anti-punch-through implantation, and first turn-on implantation. According to an embodiment of the present disclosure, the first well region implantation, the first anti-punch-through implantation, and the first turn-on implantation may all be implemented as ion implantation. Ion implantation refers to implanting appropriate ion species to an appropriate concentration with appropriate energy. According to an embodiment of the present disclosure, the ion species, dosage, and energy used in each process step of the first well region implantation, the first anti-punch-through implantation, and the first turn-on implantation may be the same or different.

[0079] For example, for the N-type flash memory cell according to this embodiment, the first well region can be implanted using a first doping type, i.e., P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type well region, such as a storage well region CPW, at a suitable depth inside the substrate of the first region NVMR.

[0080] According to an embodiment of the present disclosure, the first anti-punch-through injection can use P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type first punch-through barrier (not shown) at a suitable depth in the subsurface of the substrate of the first region NVMR, so that the junction electric field of the source-drain junction can be reduced and the voltage resistance of the device can be improved.

[0081] According to an embodiment of the present disclosure, the first turn-on injection can use P-type impurity ions, such as boron ions, boron difluoride ions or indium ions, to form a P-type first channel layer 405 at the substrate surface of the first region NVMR, and adjust the initial threshold voltage of the storage transistor (such as the first storage transistor MS110 and the second storage transistor MD 130 described above with reference to Figure 1) to 0V or greater.

[0082] Alternatively, according to an embodiment of the present disclosure, the first turn-on injection can also use a second doping type, i.e., N-type impurity ions, such as phosphorus ions or arsenic ions, to form an N-type first channel layer 405 at the substrate surface of the first region NVMR, and adjust the initial threshold voltage of the storage transistor to 0V or less.

[0083] Alternatively, according to an embodiment of the present disclosure, the first turn-on implantation may be omitted to define the substrate surface of the first NVMR region in an intrinsic or low-concentration doping state, thereby adjusting the initial threshold voltage of the memory transistor to an intrinsic state close to 0V.

[0084] According to an embodiment of the present disclosure, by adjusting the initial threshold voltage of the storage transistor (for example, the first storage transistor MS110 and the second storage transistor MD 130 described above with reference to FIG1 ) to be less than 0V or close to 0V, the gate operating voltage of the storage transistor can be reduced, thereby improving the read and write operation performance.

[0085] Subsequently, referring to FIG3 , in step S304 , as shown in FIG4D , according to an embodiment of the present disclosure, a well region of a MOS transistor can be formed in the second region MOSR by a second implantation process. As described above, according to an embodiment of the present disclosure, the MOS transistor in the second region MOSR can be one or more of a low-voltage LV-MOS transistor, an interface IO-MOS transistor (not shown), and a high-voltage HV-MOS transistor. For example, as shown in FIG4D , well regions PW and NW (not shown) of a low-voltage LV-MOS transistor and well regions HVPW and HVNW (not shown) of a high-voltage HV-MOS transistor can be formed in the second region MOSR by a second implantation process.

[0086] 4D , according to an embodiment of the present disclosure, a second channel layer 406 of the MOS transistor may be formed in the second region MOSR through a second implantation process. As shown in FIG4D , according to an embodiment of the present disclosure, the second channel layer 406 may include a channel region of a low-voltage LV-MOS transistor and a channel region of a high-voltage HV-MOS transistor.

[0087] Similar to the first implantation process described above, according to embodiments of the present disclosure, the second implantation process may include at least one of the following process steps: a second well implantation, a second anti-punchthrough implantation, and a second turn-on implantation. According to embodiments of the present disclosure, the second well implantation, the second anti-punchthrough implantation, and the second turn-on implantation may all be implemented as ion implantations. Furthermore, the ion species, dosage, and energy used in each of the second well implantation, the second anti-punchthrough implantation, and the second turn-on implantation may be the same or different.

[0088] According to an embodiment of the present disclosure, in the second region MOSR, the order of the second implantation process for the low-voltage LV-MOS transistor, the second implantation process for the interface IO-MOS transistor, and the second implantation process for the high-voltage HV-MOS transistor can be arbitrarily combined. For example, the second implantation process for the low-voltage LV-MOS transistor can be performed first, followed by the second implantation process for the interface IO-MOS transistor, and finally the second implantation process for the high-voltage HV-MOS transistor.

[0089] Furthermore, according to embodiments of the present disclosure, the order of the first implantation process for the first region NVMR and the second implantation process for the second region MOSR may be arbitrarily combined. For example, although in this embodiment the first implantation process for the first region NVMR is performed first and the second implantation process for the second region MOSR is performed subsequently, the present disclosure is not limited thereto. Alternatively, the second implantation process for the second region MOSR may be performed first and the first implantation process for the first region NVMR may be performed subsequently.

[0090] In addition, according to an embodiment of the present disclosure, the order of the first injection process for the first region NVMR, the second injection process for the low-voltage LV-MOS transistor in the second region MOSR, the second injection process for the interface IO-MOS transistor in the second region MOSR, and the second injection process for the high-voltage HV-MOS transistor in the second region MOSR can be arbitrarily combined.

[0091] Subsequently, referring to Figure 3, in step S305, as shown in Figure 4E, according to an embodiment of the present disclosure, the surface of the substrate 401 can be cleaned or pre-cleaned, and then a stacked structure 411 including a storage gate dielectric stack 407, a first gate electrode layer 408 and a hard mask barrier layer 409 is sequentially formed on the surface of the substrate 401 through oxidation, deposition or sputtering processes.

[0092] For example, according to an embodiment of the present disclosure, the storage gate dielectric stack 407 may be used to subsequently form, for example, the gate dielectric stack 112 of the first storage transistor MS 110 and the gate dielectric stack 132 of the second storage transistor MS 130 of the flash memory cell MC 100 described above with reference to FIG1 . Therefore, according to an embodiment of the present disclosure, the storage gate dielectric stack 407 may include, in a vertical direction from bottom to top, a first oxide layer (tunneling oxide layer) 407a, a storage dielectric layer (charge storage layer) 407b, and a second oxide layer (blocking oxide layer) 407c stacked in sequence.

[0093] According to an embodiment of the present disclosure, the first oxide layer 407a and the second oxide layer 407c may include, for example, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, or a combination thereof. For example, when the first oxide layer 407a and the second oxide layer 407c include silicon oxide, the first oxide layer 407a and the second oxide layer 407c may be formed using processes such as thermal oxidation, high-temperature thermal oxidation (HTO), low-pressure chemical vapor deposition, in-situ water vapor oxidation, and atomic layer deposition (ALD), and the thickness thereof is typically 1 nm to 20 nm.

[0094] According to an embodiment of the present disclosure, the storage medium layer 407b may include one or more storage medium sublayers. In addition, as described above, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 407b may include: a monovalent or polyvalent oxide, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; a monovalent or polyvalent nitride, such as silicon nitride; a monovalent or polyvalent oxynitride, such as silicon oxynitride; polycrystalline silicon or nanocrystals; or a combination of the above materials. For example, in the case where the storage medium layer 407b includes silicon nitride, the storage medium layer 407b may be formed using processes such as low-pressure chemical vapor deposition or atomic layer deposition, and its thickness is typically 2nm to 20nm.

[0095] For example, according to an embodiment of the present disclosure, when the storage dielectric layer 407b includes silicon nitride, a suitable reaction gas flow ratio can be used during its preparation to form a stack of multiple storage dielectric sublayers as the storage dielectric layer 407b. For example, as shown in FIG4E , according to an embodiment of the present disclosure, the storage dielectric layer 407b can include a first storage dielectric sublayer 407b1, a second storage dielectric sublayer 407b2, and a third storage dielectric sublayer 407b3, formed sequentially from bottom to top above the first oxide layer 407a. The second storage dielectric sublayer 407b2 has a higher silicon content than the first storage dielectric sublayer 407b1 and the third storage dielectric sublayer 407b3, and can therefore be referred to as "silicon-rich silicon nitride." Furthermore, according to an embodiment of the present disclosure, the thickness of the first storage dielectric sublayer 407b1 is 1 nm to 3 nm, and the thickness of the second storage dielectric sublayer 407b2 and the third storage dielectric sublayer 407b3 are both 2 nm to 10 nm.

[0096] Preferably, as shown in FIG. 4E , according to an embodiment of the present disclosure, storage medium layer 407b may further include a fourth storage medium sublayer 407b4 disposed on third storage medium sublayer 407b3. Fourth storage medium sublayer 407b4 has a higher silicon content than third storage medium sublayer 407b3 and may therefore be referred to as "silicon-rich silicon nitride." Furthermore, according to an embodiment of the present disclosure, the thickness of fourth storage medium sublayer 407b4 may also be 2 nm to 10 nm.

[0097] According to an embodiment of the present disclosure, the storage gate dielectric stack 407 can be subjected to a high-temperature annealing process using one or more gases selected from nitrogen (or argon), hydrogen (and / or oxygen), and nitrous oxide (or nitric oxide) in a suitable combination of ratios to convert the silicon-rich silicon nitride of the fourth storage dielectric sublayer 407b4 below the second oxide layer 407c into silicon oxynitride, while simultaneously densifying the second oxide layer 407c to improve the leakage characteristics of the second oxide layer (blocking oxide layer) 407c. According to an embodiment of the present disclosure, the annealing temperature is 800°C to 950°C, and the annealing time is 10 minutes to one hour.

[0098] Those skilled in the art will appreciate that although the embodiments of the present disclosure are described above with reference to an example in which the storage medium layer 407b includes four storage medium sublayers 407b1 to 407b4, the present disclosure is not limited thereto. For example, the storage medium layer 407b may also include more or fewer than four storage medium sublayers.

[0099] It should be noted that the silicon content described herein refers to the relative proportion of each chemical element in the storage medium sublayer measured in atomic relative quantity. For example, the relative Si / N ratio in the second storage medium sublayer 407b2 is higher than the relative Si / N ratio in the first storage medium sublayer 407b1. Therefore, the second storage medium sublayer 407b2 has properties closer to those of silicon, such as a higher refractive index and a higher trap density than Si3N4, while the first storage medium sublayer 407b1 and the third storage medium sublayer 407b3 have properties closer to those of Si3N4.

[0100] According to an embodiment of the present disclosure, the first gate electrode layer 408 can be used to subsequently form, for example, the gate electrode 116 of the first storage transistor MS110 and the gate electrode 136 of the second storage transistor MS130 of the flash memory cell MC100 described above with reference to FIG. Therefore, as described above, according to an embodiment of the present disclosure, the first gate electrode layer 408 can include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the foregoing materials. According to an embodiment of the present disclosure, the first gate electrode layer 408 can be formed, for example, by a deposition or sputtering process. For example, if the first gate electrode layer 408 includes polysilicon, a low-pressure chemical vapor deposition process can be used to form the first gate electrode layer 408 to a thickness of 10 nm to 200 nm.

[0101] According to an embodiment of the present disclosure, when the first gate electrode layer 408 includes polysilicon, a method such as in-situ doping or ion implantation may be used to add N-type impurities such as phosphorus or arsenic into the first gate electrode layer 408. Alternatively, according to an embodiment of the present disclosure, when the first gate electrode layer 408 includes polysilicon, P-type impurities such as boron or indium may be added into the first gate electrode layer 408 to reduce the Fermi potential of the first gate electrode layer 408, thereby increasing the electron barrier height between the first gate electrode layer 408 and the second oxide layer (blocking oxide layer) 407 c thereunder to improve the erase characteristics and reliability of the storage transistor in the flash memory cell.

[0102] Alternatively, although not shown in the figures, according to an embodiment of the present disclosure, when the first gate electrode layer 408 includes polysilicon, a high work function metal interface layer can be formed between the second oxide layer (blocking oxide layer) 407c and the first gate electrode layer 408. Alternatively, according to an embodiment of the present disclosure, a high work function metal material can be directly used to form the first gate electrode layer 408. According to an embodiment of the present disclosure, the metal interface layer or metal material, such as titanium or titanium nitride, has a larger work function than polysilicon, which can increase the electron barrier height between the first gate electrode layer 408 and the second oxide layer (blocking oxide layer) 407c thereunder to improve the erase characteristics and reliability of the storage transistor in the flash memory cell.

[0103] According to an embodiment of the present disclosure, the hard mask barrier layer 409 may include, for example, silicon oxide, silicon nitride, silicon glass, amorphous silicon, or a combination thereof. According to an embodiment of the present disclosure, the hard mask barrier layer 409 may be formed by a process such as oxidation, high-temperature thermal oxidation, deposition, or sputtering. For example, a hard mask barrier layer 409 including silicon oxide may be sequentially formed on the first gate electrode layer 408 by a low-pressure chemical vapor deposition process to a thickness of approximately 10 nm to 50 nm.

[0104] Subsequently, referring to FIG. 3 , in step S306, as shown in FIG. 4F , according to an embodiment of the present disclosure, the stacked structure 411 in regions other than the gate regions of the memory transistors of the flash memory cell (e.g., the first memory transistor MS110 and the second memory transistor MS130 of the flash memory cell MC100 described above with reference to FIG. 1 ) can be patterned and removed. Specifically, the hard mask barrier layer 409, the first gate electrode layer 408, and the memory gate dielectric stack 407 are sequentially removed, exposing the surface of the substrate 401 in regions other than the gate regions of the memory transistors of the flash memory cell. Consequently, as shown in FIG. 4F , a first trench 412 a and a second trench 412 b can be formed in the first region NVMR. The gate structure of the gate transistor of the flash memory cell (e.g., the gate transistor MG120 of the flash memory cell MC100 described above with reference to FIG. 1 ) can subsequently be formed in the first trench 412 a. Furthermore, as further described below, the remaining stacked structure 411 in the first region NVMR can form the gate structure of the memory transistor of the flash memory cell.

[0105] Subsequently, as shown in FIG4F , according to an embodiment of the present disclosure, an isolation layer 413 may be formed on the exposed surface of the substrate 401 and the sidewalls and / or over the remaining stacked structure 411 by, for example, thermal oxidation, high-temperature thermal oxidation, or low-pressure chemical vapor deposition. According to an embodiment of the present disclosure, the isolation layer 413 may include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, and may have a thickness of approximately 5 nm to 30 nm.

[0106] Subsequently, as shown in Figure 4F, according to an embodiment of the present disclosure, the isolation layer 413 above the substrate 401 and / or the stacked structure 411 can be removed by anisotropic and / or isotropic etching, while retaining the isolation layer 413 on the sidewalls of the stacked structure 411 to form isolation between the gate structure of the storage transistor and the gate structure of the selection transistor of the flash memory cell, wherein the isolation layer 413 formed on the sidewalls of the first trench 412a can correspond to, for example, the first isolation portion 124 and the second isolation portion 125 of the flash memory cell MC 100 described above with reference to Figure 1.

[0107] Subsequently, referring to FIG3 , in step S307, as shown in FIG4G , according to an embodiment of the present disclosure, a third implantation process can be performed in the patterned first trench 412a to form a channel region 414 of a gate transistor of the flash memory cell (e.g., the gate transistor MG120 of the flash memory cell MC100 described above with reference to FIG1 ). This channel region 414 can correspond to, for example, the channel region 121 of the gate transistor MG120 of the flash memory cell MC100 described above with reference to FIG1 . According to an embodiment of the present disclosure, the third implantation process can include at least one of the following process steps: a third anti-punchthrough implantation and a third turn-on implantation. According to an embodiment of the present disclosure, both the third anti-punchthrough implantation and the third turn-on implantation can be implemented as ion implantation, wherein the ion species, dose, and energy used in the third anti-punchthrough implantation and the third turn-on implantation can be the same or different.

[0108] For example, for an N-type flash memory cell (or NVM transistor) according to this embodiment, the third anti-punchthrough implantation may use P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type second punchthrough barrier (not shown) at a suitable depth below the substrate subsurface of the flash memory cell's gate transistor (e.g., the gate transistor MG120 of the flash memory cell MC100 described above with reference to FIG1 ), thereby suppressing leakage current and increasing the source-drain punchthrough voltage. According to embodiments of the present disclosure, the P-type impurity concentration of the second punchthrough barrier may be higher than the P-type impurity concentration of the first punchthrough barrier.

[0109] Furthermore, according to an embodiment of the present disclosure, the third turn-on implantation may use P-type impurity ions, such as boron ions, boron difluoride ions, or indium ions, to form a P-type channel region 414 of the gate transistor of the flash memory cell at the substrate surface below the first trench 412 a, thereby adjusting the threshold voltage of the gate transistor to be greater than 0 V and less than 1 V. As described above, according to an embodiment of the present disclosure, the P-type impurity concentration in the channel region 414 of the gate transistor of the flash memory cell may be higher than the P-type impurity concentration in the channel region of the storage transistor of the flash memory cell.

[0110] According to an embodiment of the present disclosure, the first modulation-on injection process step in the first injection process and the third modulation-on injection process step in the subsequent third injection process can respectively adjust and control the doping concentration of the channel region of the memory transistor (e.g., the first memory transistor MS110 and the second memory transistor MD130 of the flash memory cell MC100 described above with reference to FIG1 ) and the gate transistor (e.g., the gate transistor MG120 of the flash memory cell MC100 described above with reference to FIG1 ) of the flash memory cell by controlling the doping concentration. For example, as described above, the doping concentration of the channel region of the memory transistor is lower than the doping concentration of the channel region of the gate transistor. Furthermore, the threshold voltages of the memory transistor and the gate transistor of the flash memory cell can be adjusted and controlled, thereby achieving better cell read / write performance and off-state performance.

[0111] According to an embodiment of the present disclosure, the second injection process in step S304 of Figure 3 described above with reference to Figure 4D may also be performed after step S306 described with reference to Figure 4F , that is, after the gate structure of the storage transistor is formed by patterning the stacked structure 411 including the hard mask barrier layer 409, the first gate electrode layer 408 and the storage gate dielectric stack 407, so as to avoid the high temperature in the preparation process of the storage gate dielectric stack 407 of the storage transistor from adversely affecting the performance of the MOS transistor in the second region MOSR.

[0112] Subsequently, referring to FIG3 , in step S308 , as shown in FIG4H , according to an embodiment of the present disclosure, after pre-cleaning the wafer, a gate dielectric layer 415 for the gate transistor of the flash memory cell in the first NVMR region (which may correspond to, for example, the gate dielectric layer 122 of the gate transistor MG120 of the flash memory cell MC100 described above with reference to FIG1 ) and gate dielectric layers for the MOS transistors in the second MOSR region (such as, for example, the gate dielectric layer 416 of the low-voltage LV-MOS transistor and the gate dielectric layer 417 of the high-voltage HV-MOS transistor shown in FIG4H ) are simultaneously or sequentially formed on the surface of the exposed substrate 401 through one or more gate oxide processes. It should be noted that, as shown in FIG4H , a gate dielectric layer 415 is also concurrently formed at the bottom of the second trench 412 b in the first NVMR region. This gate dielectric layer 415 can be removed simultaneously with the removal of the second gate electrode layer 418 in the second trench 412 b in step S311 of FIG3 , which will be described later in conjunction with FIG4K .

[0113] According to an embodiment of the present disclosure, the gate dielectric layers 415, 416, and 417 may include silicon oxide, silicon oxynitride, hafnium oxide, or a combination thereof. Furthermore, according to an embodiment of the present disclosure, the gate oxide process used to form the gate dielectric layers 415, 416, and 417 may be a commonly used gate oxide process in a standard CMOS process. For example, when silicon oxide is used to form the gate dielectric layer, the gate oxide process may be thermal oxidation, high-temperature thermal oxidation, low-pressure chemical vapor deposition, in-situ water vapor oxidation, atomic layer deposition, or the like, and the thickness of the formed gate dielectric layer is typically 1 nm to 20 nm.

[0114] According to an embodiment of the present disclosure, depending on the configuration requirements of the MOS transistor in the second region MOSR, one, two or more gate oxide processes can be combined to form a gate dielectric layer 416 of a low-voltage LV-MOS transistor and / or a gate dielectric layer (not shown) of an interface IO-MOS transistor and / or a gate dielectric layer 417 of a high-voltage HV-MOS transistor having different thicknesses.

[0115] In addition, according to an embodiment of the present disclosure, the gate dielectric layer 415 can be formed simultaneously in the same gate oxide process as any one of the gate dielectric layer 416 of the low-voltage LV-CMOS transistor, the gate dielectric layer of the interface IO-CMOS transistor (not shown), and the gate dielectric layer 417 of the high-voltage HV-CMOS transistor, so that the thickness of the gate dielectric layer 415 of the selection transistor can be the same as the thickness of any one of the gate dielectric layer 416 of the low-voltage LV-MOS transistor, the gate dielectric layer of the interface IO-MOS transistor (not shown), and the gate dielectric layer 417 of the high-voltage HV-MOS transistor.

[0116] For example, in some embodiments, it is necessary to form a low-voltage LV-MOS transistor and a high-voltage HV-MOS transistor (and / or an interface IO-MOS transistor) in the second region MOSR, so a "dual-gate oxide process" can be performed to form a gate dielectric layer of the low-voltage LV-MOS transistor and a gate dielectric layer of the high-voltage HV-MOS transistor (and / or an interface IO-MOS transistor).

[0117] Specifically, as shown in FIG4H , in one embodiment, a first gate dielectric layer can be grown on the surface of the substrate 401 in the second region MOSR and on the surface of the channel region 414 of the gate transistor in the first region NVMR by a first gate oxide process. Subsequently, a patterned mask layer can be formed on the surface of the entire semiconductor device by patterning. The patterned mask layer can be a patterned photoresist layer formed using a standard photolithography process and includes an opening corresponding to the channel region of the low-voltage LV-MOS transistor in the second region MOSR. Subsequently, a dry or wet etching process can be used to remove the first gate dielectric layer on the surface of the channel region of the low-voltage LV-MOS transistor in the second region MOSR exposed by the above-mentioned opening and remove the patterned mask layer. Subsequently, a second gate dielectric layer can be grown on the surface of the exposed channel region of the low-voltage LV-MOS transistor by a second gate oxide process. In this way, the gate dielectric layer of the low-voltage LV-MOS transistor can have a different thickness from the gate dielectric layer of the gate transistor of the flash memory unit and the high-voltage HV-MOS transistor (and / or the interface IO-MOS transistor), and the gate dielectric layer of the gate transistor of the flash memory unit can have the same thickness as the gate dielectric layer of the high-voltage HV-MOS transistor (and / or the interface IO-MOS transistor).

[0118] In another embodiment, a first gate dielectric layer can be grown on the surface of the substrate 401 in the second MOSR region and on the surface of the channel region 414 of the gate transistor in the first NVMR region through a first gate oxide process. Subsequently, a patterned mask layer can be formed on the surface of the entire semiconductor device through patterning, the patterned mask layer including openings corresponding to the low-voltage LV-MOS transistor in the second MOSR region and the channel region 414 of the gate transistor of the flash memory cell in the first NVMR region. Subsequently, the first gate dielectric layer can be removed from the surface of the channel region of the low-voltage LV-MOS transistor in the second MOSR region and the surface of the channel region 414 of the gate transistor of the flash memory cell in the first NVMR region exposed by the aforementioned openings using a dry or wet etching process, and the patterned mask layer can be removed. Subsequently, a second gate dielectric layer can be grown on the surface of the exposed channel region of the low-voltage LV-MOS transistor and the surface of the channel region 414 of the gate transistor of the flash memory cell through a second gate oxide process. In this way, the gate dielectric layer of the low-voltage LV-MOS transistor can have a different thickness from the gate dielectric layer of the high-voltage HV-MOS transistor (and / or the interface IO-MOS transistor), and the gate dielectric layer of the select transistor of the flash memory cell can have the same thickness as the gate dielectric layer of the low-voltage LV-MOS transistor.

[0119] Similarly, in other embodiments, a triple-gate oxide process can be used to form gate dielectric layers with different thicknesses for the low-voltage LV-MOS transistor, the interface IO-MOS transistor, and the high-voltage HV-MOS transistor, and the gate dielectric layer of the select transistor of the flash memory cell can be formed to have the same thickness as the gate dielectric layer of any one of the low-voltage LV-MOS transistor, the interface IO-MOS transistor, and the high-voltage HV-MOS transistor.

[0120] Subsequently, referring to FIG3 , in step S309, as shown in FIG4I , according to an embodiment of the present disclosure, a second gate electrode layer 418 and an etching hard mask layer 419 may be sequentially formed on the surface of the entire substrate 401, particularly over the gate dielectric layers 415, 416, and 417 and the stacked structure 411 (including the isolation layers 413 on both sides thereof). According to an embodiment of the present disclosure, the etching hard mask layer 419 may be used to optimize the etching process of the second gate electrode layer 418 in subsequent steps, and therefore may be omitted in some simplified process flows.

[0121] According to an embodiment of the present disclosure, the second gate electrode layer 418 can be used to subsequently form, for example, the gate electrode 123 of the gate transistor MG 120 of the flash memory cell MC 100 described above with reference to FIG1 . In addition, the second gate electrode layer 418 can be used to subsequently form the gate electrodes of the various MOS transistors in the second region MOSR. According to an embodiment of the present disclosure, the second gate electrode layer 418 can be formed by, for example, a deposition or sputtering process. According to an embodiment of the present disclosure, the second gate electrode layer 418 can include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the foregoing materials. According to an embodiment of the present disclosure, in the case where the second gate electrode layer 418 includes polysilicon, a low-pressure chemical vapor deposition process can be used to form the second gate electrode layer 418, and its thickness is 50 nm to 500 nm. It should be noted that according to an embodiment of the present disclosure, the thickness of the second gate electrode layer 418 needs to be large enough to fill the first trench 412 a and the second trench 412 b, thereby having a flat upper surface in the first NVMR region and a higher upper surface of the second gate electrode layer 418 in the first NVMR region than in the second MOSR region. In addition, according to an embodiment of the present disclosure, the upper surface of the second gate electrode layer 418 is higher than the upper surface of the first gate electrode layer 408.

[0122] According to an embodiment of the present disclosure, the etching hard mask layer 419 may include, for example, silicon oxide, silicon nitride, silicon glass, or a combination thereof. According to an embodiment of the present disclosure, the etching hard mask layer 419 may be formed by, for example, oxidation, high-temperature thermal oxidation, deposition, or sputtering. For example, the etching hard mask layer 419 of silicon oxide may be formed on the second gate electrode layer 418 by a low-pressure chemical vapor deposition process, with a thickness of 20 nm to 100 nm.

[0123] Subsequently, referring to FIG3 , in step S310, as shown in FIG4J , according to an embodiment of the present disclosure, the etching hard mask layer 419, the second gate electrode layer 418, and the gate dielectric layers 416 and 417 in the portion outside the gate region of the MOS transistor in the second region MOSR can be removed by, for example, patterning and selective etching processes. In this way, the gate structure of the MOS transistor in the second region MOSR can be formed. In addition, as shown in FIG4J , according to an embodiment of the present disclosure, the etching hard mask layer 419 and a portion of the second gate electrode layer 418 in the first region NVMR can be removed concurrently until the upper surface of the stacked structure 411, that is, the upper surface of the hard mask barrier layer 409 is exposed, and at the same time, the second gate electrode layer 418 is filled in the first trench 412 a and the second trench 412 b. 4J , the second gate electrode layer 418 filled in the first trench 412 a in the first region NVMR may correspond to, for example, the gate electrode 123 of the gate transistor MG120 of the flash memory cell MC100 described above with reference to FIG1 , while the remaining second gate electrode layer 418 in the second region MOSR may form a gate electrode of a MOS transistor.

[0124] Subsequently, referring to FIG. 3 , in step S311, as shown in FIG. 4K , according to an embodiment of the present disclosure, a patterned mask layer can be formed in the first NVMR region by, for example, patterning. This patterned mask layer can be a patterned photoresist layer formed using a standard photolithography process and includes an opening corresponding to the second trench 412 b. Subsequently, the second gate electrode layer 418 and the gate dielectric layer 415 thereunder, exposed by the opening and not covered by the photoresist layer, can be removed by an anisotropic etching process. Specifically, the second gate electrode layer 418 and gate dielectric layer 415 in the second trench 412 b are removed, while the second gate electrode layer 418 and gate dielectric layer 415 in the first trench 412 a remain, thereby forming the gate structure of the memory transistor. Thus, the hard mask barrier layer 409 can correspond to, for example, the hard mask barrier portion 117 of the first memory transistor MS110 and the hard mask barrier portion 137 of the second memory transistor MD130 of the flash memory cell MC100 described above with reference to FIG. 1 .

[0125] Subsequently, referring to FIG. 3 , in step S312 , as shown in FIG. 4L , according to an embodiment of the present disclosure, lightly doped source / drain regions 420 of flash memory cells of the first region NVMR and transistors of the second region MOSR may be formed by patterning one or more lightly doped source / drain (LDD) regions.

[0126] According to an embodiment of the present disclosure, the lightly doped source and drain regions 420 can be formed by, for example, an ion implantation process. In addition, according to an embodiment of the present disclosure, the ion implantation process for forming the lightly doped source and drain regions 420 of the flash memory cell in the first region NVMR and the ion implantation process for forming the lightly doped source and drain regions 420 of the MOS transistor in the second region MOSR can use the same or different ion species, doses, and energies. In addition, according to an embodiment of the present disclosure, the ion implantation process for forming the lightly doped source and drain regions 420 of the flash memory cell in the first region NVMR can be the same as the ion implantation process for forming the lightly doped source and drain regions 420 of at least one transistor (e.g., a low-voltage LV-MOS transistor, an interface IO-MOS transistor, or a high-voltage HV-MOS transistor) in the second region MOSR, for example, using the same ion species, doses, and / or energies.

[0127] For example, for an N-type flash memory cell (or NVM transistor) according to this embodiment, the ion implantation process for forming its lightly doped source and drain regions 420 may use N-type impurity ions, such as phosphorus ions or arsenic ions, to form N-type lightly doped source and drain regions 420 on the surface of the source and drain regions of the flash memory cell.

[0128] Alternatively, according to an embodiment of the present disclosure, before performing the ion implantation process for forming the lightly doped source and drain regions 420 of the flash memory cell, P-type impurity ions, such as boron ions or boron difluoride ions, may be additionally implanted to form a P-type wrapping region (P-Halo) (not shown) outside the lightly doped source and drain regions 420 of the flash memory cell to improve the punch-through characteristics and storage characteristics of the flash memory cell.

[0129] Subsequently, referring to FIG3 , in step S313 , as shown in FIG4M , according to an embodiment of the present disclosure, sidewalls (spacers) 421 can be concurrently formed on both sides of the gate structure of the flash memory cell in the first region NVMR and the MOS transistor in the second region MOSR using a sidewall process commonly used in integrated circuit processes. For example, the sidewall process can first deposit one or more isolation dielectric layers on the surface of the substrate structure, and then use an anisotropic etching process to remove the isolation dielectric layers above the substrate structure, thereby forming the sidewalls 421.

[0130] Subsequently, as shown in FIG. 4M , according to an embodiment of the present disclosure, heavily doped source and drain regions 422 of the flash memory cells in the first region NVMR and the transistors in the second region MOSR may be formed by a heavily doped source and drain implantation process.

[0131] As shown in FIG. 4M , the lightly doped source and drain regions 420 and the heavily doped source and drain regions 422 of the flash memory cells in the first region NVM may together correspond to, for example, the source region 140 and the drain region 150 of the flash memory cell MC100 described above with reference to FIG. 1 .

[0132] Subsequently, referring to FIG3 , in step S314 , as shown in FIG4N , according to an embodiment of the present disclosure, the etching hard mask layer 419 above the gate structure of the MOS transistor in the second region MOSR can be removed by an etching cleaning process, and the second gate electrode layer 418 in the gate structure of the gate transistor of the flash memory cell in the first region NVMR can be overetched to form a recess. Subsequently, as shown in FIG4N , a metal layer, such as nickel, titanium, tungsten, molybdenum, cobalt, manganese, tantalum, platinum or palladium, can be formed on the surface of the substrate structure by a deposition or sputtering process, and a metal silicide layer (silicide) 424 can be formed on the surface of the source and drain regions of the flash memory cell in the first region NVMR and the gate electrode of the gate transistor and the source and drain regions of the MOS transistor in the second region MOSR and the gate electrode (second gate electrode layer 418) by an annealing process, thereby reducing the contact resistance of the source and drain regions and the on-resistance of the gate electrode.

[0133] Alternatively, according to an embodiment of the present disclosure, although not shown, all or a portion of the hard mask barrier layer 409 above the gate electrode (first gate electrode layer 408) of the storage transistor of the flash memory cell in the first region NVMR can be further removed by an etching and cleaning process to expose all or a portion of the surface of the gate electrode of the storage transistor (i.e., the first gate electrode layer 408), and a metal silicide layer can be concurrently formed on the exposed gate electrode surface of the storage transistor of the flash memory cell.

[0134] Thus, according to the embodiment of the present disclosure, the front-end manufacturing process of the integration process of the flash memory cells in the first region NVMR and the MOS transistors in the second region MOSR is completed.

[0135] Finally, according to the embodiments of the present disclosure, one or more metal connection layers and corresponding contact holes and through-holes can be formed through the back-end manufacturing process commonly used in integrated circuit processes, thereby forming electrical connections between the flash memory cells in the first region NVMR and the transistors in the second region MOSR.

[0136] FIG5 is a cross-sectional view illustrating a flash memory cell MC100′ according to an alternative embodiment of the present disclosure. Flash memory cell MC100′ according to an alternative embodiment of the present disclosure has the same equivalent circuit as that shown in FIG2 . Components of flash memory cell MC100′ shown in FIG5 that are identical to those of flash memory cell MC100 shown in FIG1 are denoted by the same reference numerals, and for the sake of brevity, a repeated description is omitted.

[0137] Referring to FIG. 5 in conjunction with FIG. 1 , the only difference between flash memory cell MC 100 ′ shown in FIG. 5 and flash memory cell MC 100 shown in FIG. 1 is the structure of gate transistor MG 120. As shown in FIG. 5 , unlike FIG. 1 , according to an alternative embodiment of the present disclosure, gate dielectric layer 122 of gate transistor MG 120 may be formed of a high-k material. The high-k material may have a dielectric constant of approximately 4 to 20 or greater. The high-k material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide. According to an alternative embodiment of the present disclosure, gate dielectric layer 122 may be formed of a composite layer including two or more layers of the aforementioned high-k materials. According to an alternative embodiment of the present disclosure, when the gate dielectric layer 122 is formed of a high-K material, the gate electrode 123 may be a metal gate, such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, molybdenum, molybdenum oxide, a titanium nitride / tungsten stack, or a tungsten nitride / tungsten stack. In this case, the gate structure of the gate transistor MG 120 is a high-K metal gate (HKMG) structure. In this case, as shown in FIG5 , the metal silicide 126 shown in FIG1 is not present on the gate electrode 123.

[0138] Next, a method for manufacturing a semiconductor device according to an alternative embodiment of the present disclosure will be described with reference to FIG6 and FIG7A to FIG7O. FIG6 shows a flowchart of a method 600 for manufacturing a semiconductor device according to an alternative embodiment of the present disclosure. FIG7A to FIG7O show cross-sectional views of a semiconductor device at various steps of the method 600 for manufacturing a semiconductor device shown in FIG6.

[0139] 6 , in step S601, as shown in FIG7A , a wafer serving as a substrate 701 is provided. According to an embodiment of the present disclosure, the wafer may be a wafer of a first doping type serving as a semiconductor substrate, such as a silicon substrate. According to an embodiment of the present disclosure, the first doping type may be defined as P-type, and the second doping type may be defined as N-type. However, those skilled in the art will recognize that the present disclosure is not limited thereto, and that the first doping type may also be N-type, in which case the second doping type may be P-type.

[0140] As shown in FIG7A , the wafer may be pre-processed, for example, by sequentially providing a liner layer 702 formed of, for example, silicon oxide and a cap layer 703 formed of, for example, silicon nitride on a substrate 701, wherein the liner layer 702 may be used to reduce the stress of the cap layer 703. According to an embodiment of the present disclosure, the liner layer 702 may be formed by, for example, thermal oxidation, in-situ water vapor oxidation (ISSG) or a deposition process, and its thickness is typically 10 nm to 100 nm. In addition, according to an embodiment of the present disclosure, the cap layer 703 may be formed by a deposition process, such as a commonly used low-pressure chemical vapor deposition process (LPCVD), and its thickness is typically 20 nm to 200 nm.

[0141] Subsequently, referring to FIG6 , in step S602, as shown in FIG7B , according to an embodiment of the present disclosure, a plurality of isolation structures 704 defining active regions may be formed in the substrate 701 by active region patterning. According to an embodiment of the present disclosure, the isolation structures 704 may divide the substrate 701 into a first region NVMR in which the flash memory cells are disposed and a second region MOSR adjacent to the first region NVMR in which metal oxide semiconductor (MOS) transistors are disposed.

[0142] According to an embodiment of the present disclosure, the flash memory cell set in the first region NVMR may correspond to, for example, the flash memory cell MC100' described above with reference to Figures 5 and 2, that is, it includes two storage transistors, for example, the first storage transistor MS110 and the second storage transistor MD130 described above with reference to Figures 5 and 2, and a selection transistor, for example, the selection transistor MG120 described above with reference to Figures 5 and 2.

[0143] According to an embodiment of the present disclosure, a flash memory array composed of a plurality of flash memory cells similar to the flash memory cells MC 100′ described above with reference to FIG. 5 and FIG. 2 may be provided in the first NVMR region of the semiconductor device. Furthermore, although not shown in the figures, according to an embodiment of the present disclosure, each column of flash memory cells in the flash memory array provided in the first NVMR region may also be isolated from adjacent columns of flash memory cells by an isolation structure 704.

[0144] According to an embodiment of the present disclosure, the MOS transistors disposed in the second region MOSR may be one or more of a low-voltage LV-MOS transistor, an interface IO-MOS transistor, or a high-voltage HV-MOS transistor. According to an embodiment of the present disclosure, the MOS transistors in the second region MOSR may constitute a peripheral circuit for the flash memory cell array in the first region NVMR.

[0145] In addition, according to an embodiment of the present disclosure, the MOS transistor disposed in the second region MOSR may also be isolated from adjacent MOS transistors by the isolation structure 704 .

[0146] According to an embodiment of the present disclosure, the active area patterning of the first NVMR region and the second MOSR region can be simultaneously achieved through a single photolithography process using the same active area mask layer. Alternatively, the active area patterning of the first NVMR region and the second MOSR region can also be achieved through two photolithography processes using different active area mask layers.

[0147] Although as shown in FIG7B , according to an embodiment of the present disclosure, the isolation structure 704 can be implemented by a shallow trench isolation (STI) process, the present disclosure is not limited thereto. Those skilled in the art will recognize that the isolation structure can also be implemented by any isolation process commonly used in integrated circuit processes, such as a local oxidation isolation (LOCOS) process.

[0148] For example, according to an embodiment of the present disclosure, the isolation structure 704 can be formed by an STI process. Specifically, the STI process may include: sequentially removing a portion of the cap layer 703 and a portion of the liner layer 702 by an etching process to form a shallow trench structure having a specific depth in the substrate 701; filling the substrate surface with an isolation dielectric layer or a multi-layer composite isolation dielectric layer such as silicon oxide, silicon nitride, and / or polysilicon by a thermal oxidation or low-pressure deposition process; and removing the isolation dielectric layer, the cap layer 703, and the liner layer 702 by a chemical mechanical polishing (CMP) process and / or an etching process to obtain a flat surface of the substrate 701.

[0149] According to an embodiment of the present disclosure, the isolation structures 704 in the first NVMR region and the second MOSR region can be implemented through a single isolation process. Alternatively, the isolation structures 704 in the first NVMR region and the second MOSR region can be implemented through two isolation processes, respectively, to form isolation structures 704 having different widths or depths in the first NVMR region and the second MOSR region, respectively.

[0150] Subsequently, referring to FIG6 , in step S603, as shown in FIG7C , according to an embodiment of the present disclosure, a well region of a flash memory cell, such as a deep well region DNW and a storage well region CPW, may be formed in the first region NVMR through a first implantation process. According to an embodiment of the present disclosure, the deep well region DNW of the flash memory cell may correspond to, for example, the deep well region DNW 103 of the second doping type described above with reference to FIG5 , and the storage well region CPW of the flash memory cell may correspond to, for example, the storage well region CPW 102 of the first doping type described above with reference to FIG5 . Furthermore, according to an embodiment of the present disclosure, the MOS transistor of the second region MOSR may also be disposed in the deep well region DNW.

[0151] 7C , according to an embodiment of the present disclosure, a first channel layer 705 of the flash memory cell may be formed in the first region NVMR by a first implantation process. According to an embodiment of the present disclosure, the first channel layer 705 of the flash memory cell may be used to subsequently form, for example, the channel region 111 of the first storage transistor MS110, the channel region 121 of the gate transistor MG120, and the channel region 131 of the second storage transistor MD130 described above with reference to FIG5 .

[0152] According to an embodiment of the present disclosure, the first implantation process may include at least one of the following process steps: first well region implantation, first anti-punch-through implantation, and first turn-on implantation. According to an embodiment of the present disclosure, the first well region implantation, the first anti-punch-through implantation, and the first turn-on implantation may all be implemented as ion implantation. Ion implantation refers to implanting appropriate ion species to an appropriate concentration with appropriate energy. According to an embodiment of the present disclosure, the ion species, dosage, and energy used in each process step of the first well region implantation, the first anti-punch-through implantation, and the first turn-on implantation may be the same or different.

[0153] For example, for the N-type flash memory cell according to this embodiment, the first well region can be implanted using a first doping type, i.e., P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type well region, such as a storage well region CPW, at a suitable depth inside the substrate of the first region NVMR.

[0154] According to an embodiment of the present disclosure, the first anti-punch-through injection can use P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type first punch-through barrier (not shown) at a suitable depth in the subsurface of the substrate of the first region NVMR, so that the junction electric field of the source-drain junction can be reduced and the voltage resistance of the device can be improved.

[0155] According to an embodiment of the present disclosure, the first turn-on injection can use P-type impurity ions, such as boron ions, boron difluoride ions or indium ions, to form a P-type first channel layer 705 at the substrate surface of the first region NVMR, and adjust the initial threshold voltage of the storage transistor (such as the first storage transistor MS110 and the second storage transistor MD 130 described above with reference to Figure 5) to 0V or greater.

[0156] Alternatively, according to an embodiment of the present disclosure, the first turn-on injection can also use a second doping type, i.e., N-type impurity ions, such as phosphorus ions or arsenic ions, to form an N-type first channel layer 705 at the substrate surface of the first region NVMR, and adjust the initial threshold voltage of the storage transistor to 0V or less.

[0157] Alternatively, according to an embodiment of the present disclosure, the first turn-on implantation may be omitted to define the substrate surface of the first NVMR region in an intrinsic or low-concentration doping state, thereby adjusting the initial threshold voltage of the memory transistor to an intrinsic state close to 0V.

[0158] According to an embodiment of the present disclosure, by adjusting the initial threshold voltage of the storage transistor (for example, the first storage transistor MS110 and the second storage transistor MD 130 described above with reference to Figure 5) to less than 0V or close to 0V, the gate operating voltage of the storage transistor can be reduced, thereby improving the read and write operation performance.

[0159] Subsequently, referring to Figure 6, in step S604, as shown in Figure 7D, according to an embodiment of the present disclosure, the surface of the substrate 701 can be cleaned or pre-cleaned, and then a stacked structure 711 including a storage gate dielectric stack 707, a first gate electrode layer 708 and a hard mask barrier layer 709 is sequentially formed on the surface of the substrate 701 through oxidation, deposition or sputtering processes.

[0160] For example, according to an embodiment of the present disclosure, the storage gate dielectric stack 707 may be used to subsequently form, for example, the gate dielectric stack 112 of the first storage transistor MS 110 and the gate dielectric stack 132 of the second storage transistor MS 130 of the flash memory cell MC 100′ described above with reference to FIG5 . Therefore, according to an embodiment of the present disclosure, the storage gate dielectric stack 707 may include, in a vertical direction from bottom to top, a first oxide layer (tunneling oxide layer) 707a, a storage dielectric layer (charge storage layer) 707b, and a second oxide layer (blocking oxide layer) 707c stacked in sequence.

[0161] According to an embodiment of the present disclosure, the first oxide layer 707a and the second oxide layer 707c may include, for example, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, or a combination thereof. For example, when the first oxide layer 707a and the second oxide layer 707c include silicon oxide, the first oxide layer 707a and the second oxide layer 707c may be formed using processes such as thermal oxidation, high-temperature thermal oxidation (HTO), low-pressure chemical vapor deposition, in-situ water vapor oxidation, and atomic layer deposition (ALD), and the thickness thereof is typically 1 nm to 20 nm.

[0162] According to an embodiment of the present disclosure, the storage medium layer 707b may include one or more storage medium sublayers. In addition, as described above, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 707b may include: a monovalent or polyvalent oxide, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; a monovalent or polyvalent nitride, such as silicon nitride; a monovalent or polyvalent oxynitride, such as silicon oxynitride; polycrystalline silicon or nanocrystals; or a combination of the above materials. For example, in the case where the storage medium layer 707b includes silicon nitride, the storage medium layer 707b may be formed using processes such as low-pressure chemical vapor deposition or atomic layer deposition, and its thickness is typically 2nm to 20nm.

[0163] For example, according to an embodiment of the present disclosure, when the storage dielectric layer 707b includes silicon nitride, a suitable reaction gas flow ratio can be used during its preparation to form a stack of multiple storage dielectric sublayers as the storage dielectric layer 707b. For example, as shown in FIG7D , according to an embodiment of the present disclosure, the storage dielectric layer 707b can include a first storage dielectric sublayer 707b1, a second storage dielectric sublayer 707b2, and a third storage dielectric sublayer 707b3, formed sequentially from bottom to top above the first oxide layer 707a. The second storage dielectric sublayer 707b2 has a higher silicon content than the first storage dielectric sublayer 707b1 and the third storage dielectric sublayer 707b3, and can therefore be referred to as "silicon-rich silicon nitride." In addition, according to an embodiment of the present disclosure, the thickness of the first storage dielectric sublayer 707b1 is 1 nm to 3 nm, and the thickness of the second storage dielectric sublayer 707b2 and the third storage dielectric sublayer 707b3 are both 2 nm to 10 nm.

[0164] Preferably, as shown in FIG. 7D , according to an embodiment of the present disclosure, the storage dielectric layer 707b may further include a fourth storage dielectric sublayer 707b4 disposed on the third storage dielectric sublayer 707b3. The fourth storage dielectric sublayer 707b4 has a higher silicon content than the third storage dielectric sublayer 707b3 and may therefore be referred to as "silicon-rich silicon nitride." Furthermore, according to an embodiment of the present disclosure, the thickness of the fourth storage dielectric sublayer 707b4 may also be 2 nm to 10 nm.

[0165] According to an embodiment of the present disclosure, the storage gate dielectric stack 707 can be subjected to a high-temperature annealing process using one or more gases selected from nitrogen (or argon), hydrogen (and / or oxygen), and nitrous oxide (or nitric oxide) in a suitable combination of ratios to convert the silicon-rich silicon nitride of the fourth storage dielectric sublayer 707b4 below the second oxide layer 707c into silicon oxynitride, while simultaneously densifying the second oxide layer 707c to improve the leakage characteristics of the second oxide layer (blocking oxide layer) 707c. According to an embodiment of the present disclosure, the annealing temperature is 800° C. to 950° C., and the annealing time is 10 minutes to one hour.

[0166] Those skilled in the art will appreciate that although the embodiments of the present disclosure are described above with reference to an example in which the storage medium layer 707b includes four storage medium sublayers 707b1 to 707b4, the present disclosure is not limited thereto. For example, the storage medium layer 707b may also include more or fewer than four storage medium sublayers.

[0167] It should be noted that the silicon content described herein refers to the relative proportion of each chemical element in the storage medium sublayer measured in atomic relative amounts. For example, the relative Si / N ratio in the second storage medium sublayer 707b2 is higher than the relative Si / N ratio in the first storage medium sublayer 707b1. Therefore, the second storage medium sublayer 707b2 has properties closer to those of silicon, such as a higher refractive index and a higher trap density than Si3N4, while the first storage medium sublayer 707b1 and the third storage medium sublayer 707b3 have properties closer to those of Si3N4.

[0168] According to an embodiment of the present disclosure, the first gate electrode layer 708 can be used to subsequently form, for example, the gate electrode 116 of the first storage transistor MS110 and the gate electrode 136 of the second storage transistor MS130 of the flash memory cell MC100' described above with reference to FIG5. Therefore, as described above, according to an embodiment of the present disclosure, the first gate electrode layer 708 can include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the foregoing materials. According to an embodiment of the present disclosure, the first gate electrode layer 708 can be formed, for example, by a deposition or sputtering process. For example, if the first gate electrode layer 708 includes polysilicon, a low-pressure chemical vapor deposition process can be used to form the first gate electrode layer 708 to a thickness of 10 nm to 200 nm.

[0169] According to an embodiment of the present disclosure, when the first gate electrode layer 708 includes polysilicon, a method such as in-situ doping or ion implantation may be used to add N-type impurities such as phosphorus or arsenic into the first gate electrode layer 708. Alternatively, according to an embodiment of the present disclosure, when the first gate electrode layer 708 includes polysilicon, P-type impurities such as boron or indium may be added into the first gate electrode layer 708 to reduce the Fermi potential of the first gate electrode layer 708, thereby increasing the electron barrier height between the first gate electrode layer 708 and the second oxide layer (blocking oxide layer) 707c thereunder to improve the erase characteristics and reliability of the storage transistor in the flash memory cell.

[0170] Alternatively, although not shown in the figures, according to an embodiment of the present disclosure, when the first gate electrode layer 708 includes polysilicon, a high work function metal interface layer can be formed between the second oxide layer (blocking oxide layer) 707c and the first gate electrode layer 708. Alternatively, according to an embodiment of the present disclosure, a high work function metal material can be directly used to form the first gate electrode layer 708. According to an embodiment of the present disclosure, the metal interface layer or metal material, such as titanium or titanium nitride, has a larger work function than polysilicon, which can increase the electron barrier height between the first gate electrode layer 708 and the second oxide layer (blocking oxide layer) 707c thereunder to improve the erase characteristics and reliability of the storage transistor in the flash memory cell.

[0171] According to an embodiment of the present disclosure, the hard mask barrier layer 709 may include, for example, silicon oxide, silicon nitride, silicon glass, amorphous silicon, or a combination thereof. According to an embodiment of the present disclosure, the hard mask barrier layer 709 may be formed by a process such as oxidation, high-temperature thermal oxidation, deposition, or sputtering. For example, a hard mask barrier layer 709 including silicon oxide may be sequentially formed on the first gate electrode layer 708 by a low-pressure chemical vapor deposition process to a thickness of approximately 10 nm to 50 nm.

[0172] Subsequently, referring to FIG. 6 , in step S605, as shown in FIG. 7E , according to an embodiment of the present disclosure, the stacked structure 711 in regions other than the gate regions of the memory transistors of the flash memory cell (e.g., the first memory transistor MS110 and the second memory transistor MS130 of the flash memory cell MC100′ described above with reference to FIG. 5 ) can be patterned and removed. Specifically, the hard mask barrier layer 709, the first gate electrode layer 708, and the memory gate dielectric stack 707 are sequentially removed, exposing the surface of the substrate 701 in regions other than the gate regions of the memory transistors of the flash memory cell. Consequently, as shown in FIG. 7E , a first trench 712 a and a second trench 712 b can be formed in the first NVMR region. The gate structure of the gate transistor of the flash memory cell (e.g., the gate transistor MG120 of the flash memory cell MC100′ described above with reference to FIG. 5 ) can subsequently be formed in the first trench 712 a. Furthermore, as further described below, the remaining stacked structure 711 in the first NVMR region can form the gate structure of the memory transistor of the flash memory cell.

[0173] 7E , according to an embodiment of the present disclosure, an isolation layer 713 may be formed on the exposed surface of the substrate 701 and the sidewalls and / or over the remaining stacked structure 711 by, for example, thermal oxidation, high-temperature thermal oxidation, or low-pressure chemical vapor deposition. According to an embodiment of the present disclosure, the isolation layer 713 may include silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof, and may have a thickness of approximately 5 nm to 30 nm.

[0174] Subsequently, as shown in Figure 7E, according to an embodiment of the present disclosure, the isolation layer 713 above the substrate 701 and / or the stacked structure 711 can be removed by anisotropic and / or isotropic etching, while retaining the isolation layer 713 on the sidewalls of the stacked structure 711 to form isolation between the gate structure of the storage transistor and the gate structure of the selection transistor of the flash memory cell, wherein the isolation layer 713 formed on the sidewalls of the first trench 712a can correspond to, for example, the first isolation portion 124 and the second isolation portion 125 of the flash memory cell MC 100' described above with reference to Figure 5.

[0175] Subsequently, referring to FIG6 , in step S606 , as shown in FIG7F , according to an embodiment of the present disclosure, a well region of a MOS transistor can be formed in the second region MOSR by a second implantation process. As described above, according to an embodiment of the present disclosure, the MOS transistor in the second region MOSR can be one or more of a low-voltage LV-MOS transistor, an interface IO-MOS transistor (not shown), and a high-voltage HV-MOS transistor. For example, as shown in FIG7F , well regions PW and NW (not shown) of a low-voltage LV-MOS transistor and well regions HVPW and HVNW (not shown) of a high-voltage HV-MOS transistor can be formed in the second region MOSR by a second implantation process.

[0176] 7F , according to an embodiment of the present disclosure, a second channel layer 706 of the MOS transistor may be formed in the second region MOSR through a second implantation process. As shown in FIG7F , according to an embodiment of the present disclosure, the second channel layer 706 may include a channel region of a low-voltage LV-MOS transistor and a channel region of a high-voltage HV-MOS transistor.

[0177] Similar to the first implantation process described above with reference to FIG. 7C , according to embodiments of the present disclosure, the second implantation process may include at least one of the following process steps: a second well implantation, a second anti-punchthrough implantation, and a second turn-on implantation. According to embodiments of the present disclosure, the second well implantation, the second anti-punchthrough implantation, and the second turn-on implantation may all be implemented as ion implantations. Furthermore, the ion species, dosage, and energy used in each of the second well implantation, the second anti-punchthrough implantation, and the second turn-on implantation may be the same or different.

[0178] According to an embodiment of the present disclosure, in the second region MOSR, the order of the second implantation process for the low-voltage LV-MOS transistor, the second implantation process for the interface IO-MOS transistor, and the second implantation process for the high-voltage HV-MOS transistor can be arbitrarily combined. For example, the second implantation process for the low-voltage LV-MOS transistor can be performed first, followed by the second implantation process for the interface IO-MOS transistor, and finally the second implantation process for the high-voltage HV-MOS transistor.

[0179] Subsequently, referring to FIG. 6 , in step S607, as shown in FIG. 7G , according to an embodiment of the present disclosure, a third implantation process can be performed in the patterned first trench 712 a to form a channel region 714 of a gate transistor of the flash memory cell (e.g., gate transistor MG120 of flash memory cell MC100′ described above with reference to FIG. 5 ). This channel region 714 can correspond to, for example, channel region 121 of gate transistor MG120 of flash memory cell MC100′ described above with reference to FIG. 5 . According to an embodiment of the present disclosure, the third implantation process can include at least one of the following process steps: a third anti-punchthrough implantation and a third turn-on implantation. According to an embodiment of the present disclosure, both the third anti-punchthrough implantation and the third turn-on implantation can be implemented as ion implantation, wherein the ion species, dose, and energy used in the third anti-punchthrough implantation and the third turn-on implantation can be the same or different.

[0180] For example, for an N-type flash memory cell (or NVM transistor) according to this embodiment, the third anti-punchthrough implantation may use P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type second punchthrough barrier (not shown) at a suitable depth below the substrate subsurface of the flash memory cell's gate transistor (e.g., the gate transistor MG120 of the flash memory cell MC100' described above with reference to FIG5 ), thereby suppressing leakage current and increasing the source-drain punchthrough voltage. According to an embodiment of the present disclosure, the P-type impurity concentration of the second punchthrough barrier may be higher than the P-type impurity concentration of the first punchthrough barrier.

[0181] Furthermore, according to an embodiment of the present disclosure, the third turn-on implantation may use P-type impurity ions, such as boron ions, boron difluoride ions, or indium ions, to form a P-type channel region 714 of the gate transistor of the flash memory cell at the substrate surface below the first trench 712 a, thereby adjusting the threshold voltage of the gate transistor to be greater than 0 V and less than 1 V. As described above, according to an embodiment of the present disclosure, the P-type impurity concentration in the channel region 714 of the gate transistor of the flash memory cell may be higher than the P-type impurity concentration in the channel region of the storage transistor of the flash memory cell.

[0182] According to an embodiment of the present disclosure, the first modulation-on injection process step in the first injection process and the third modulation-on injection process step in the subsequent third injection process can respectively adjust and control the doping concentration of the channel region of the memory transistor (e.g., the first memory transistor MS110 and the second memory transistor MD130 of the flash memory cell MC100' described above with reference to FIG5 ) and the gate transistor (e.g., the gate transistor MG120 of the flash memory cell MC100' described above with reference to FIG5 ) of the flash memory cell by controlling the doping concentration. For example, as described above, the doping concentration of the channel region of the memory transistor is lower than the doping concentration of the channel region of the gate transistor. Furthermore, the threshold voltages of the memory transistor and the gate transistor of the flash memory cell can be adjusted and controlled, thereby achieving better cell read / write performance and off-state performance.

[0183] Subsequently, referring to FIG6 , in step S608, as shown in FIG7H , according to an embodiment of the present disclosure, after pre-cleaning the wafer, a gate dielectric layer 715 for the gate transistor of the flash memory cell in the first NVMR region and the MOS transistor in the second MOSR region, such as the gate dielectric layer 715 of the low-voltage LV-MOS transistor and the high-voltage HV-MOS transistor shown in FIG7H , can be formed on the surface of the exposed substrate 701 through a gate oxide process. It should be noted that, as shown in FIG7H , a gate dielectric layer 715 is also concurrently formed at the bottom of the second trench 712 b in the first NVMR region, which can be removed simultaneously with the removal of the second gate electrode layer 718 in the second trench 712 b in step S611 of FIG6 described later in conjunction with FIG7K .

[0184] According to an embodiment of the present disclosure, the gate dielectric layer 715 may include silicon oxide, silicon oxynitride, hafnium oxide, or a combination of the foregoing materials. In addition, according to an embodiment of the present disclosure, the gate oxide process used to form the gate dielectric layer 715 may be a commonly used gate oxide process in a standard CMOS process. For example, when silicon oxide is used to form the gate dielectric layer, the gate oxide process may be thermal oxidation, high-temperature thermal oxidation, low-pressure chemical vapor deposition, in-situ water vapor oxidation, atomic layer deposition, etc., and the thickness of the formed gate dielectric layer is generally 1 nm to 20 nm.

[0185] According to an embodiment of the present disclosure, depending on the configuration requirements of the MOS transistor in the second region MOSR, multiple gate oxide processes can be combined so that the gate dielectric layer (not shown) of the low-voltage LV-MOS transistor, the interface IO-MOS transistor, and the gate dielectric layer 715 of the high-voltage HV-MOS transistor have different thicknesses from each other, and the gate dielectric layer 715 of the selection transistor of the flash memory unit can be formed to have the same thickness as the gate dielectric layer 715 of any one of the low-voltage LV-MOS transistor, the interface IO-MOS transistor, and the high-voltage HV-MOS transistor.

[0186] Subsequently, referring to FIG6 , in step S609, as shown in FIG7I , according to an embodiment of the present disclosure, a second gate electrode layer 718 and an etching hard mask layer 719 may be sequentially formed on the surface of the entire substrate 701, particularly above the gate dielectric layer 715 and the stacked structure 711 (including the isolation layers 713 on both sides thereof). According to an embodiment of the present disclosure, the etching hard mask layer 719 may be used to optimize the etching process of the second gate electrode layer 718 in subsequent steps, and therefore may be omitted in some simplified process flows.

[0187] According to an embodiment of the present disclosure, the second gate electrode layer 718 can be used to subsequently form, for example, the gate electrode 123 of the gate transistor MG 120 of the flash memory cell MC 100' described above with reference to Figure 5. In addition, the second gate electrode layer 718 can be used to subsequently form the gate electrodes of each MOS transistor in the second region MOSR. According to an embodiment of the present disclosure, the second gate electrode layer 718 can be formed by, for example, a deposition or sputtering process. According to an embodiment of the present disclosure, the second gate electrode layer 718 can include, for example, polysilicon, metal silicide, or a combination of the above materials. According to an embodiment of the present disclosure, when the second gate electrode layer 718 includes polysilicon, a low-pressure chemical vapor deposition process can be used to form the second gate electrode layer 718, and its thickness is 50nm to 500nm. It should be noted that according to an embodiment of the present disclosure, the thickness of the second gate electrode layer 718 needs to be large enough to fill the first trench 712a and the second trench 712b, so that the second gate electrode layer 718 has a flat upper surface in the first region NVMR, and the upper surface of the second gate electrode layer 718 in the first region NVMR is higher than the upper surface of the second gate electrode layer 718 in the second region MOSR. In addition, according to an embodiment of the present disclosure, the upper surface of the second gate electrode layer 718 is higher than the upper surface of the first gate electrode layer 708.

[0188] According to an embodiment of the present disclosure, the etching hard mask layer 719 may include, for example, silicon oxide, silicon nitride, silicon glass, or a combination thereof. According to an embodiment of the present disclosure, the etching hard mask layer 719 may be formed by, for example, oxidation, high-temperature thermal oxidation, deposition, or sputtering. For example, the etching hard mask layer 719 of silicon oxide may be formed on the second gate electrode layer 718 by a low-pressure chemical vapor deposition process, with a thickness of 20 nm to 100 nm.

[0189] Subsequently, referring to FIG6 , in step S610, as shown in FIG7J , according to an embodiment of the present disclosure, the etching hard mask layer 719, the second gate electrode layer 718, and the gate dielectric layer 715 in the portion outside the gate region of the MOS transistor in the second region MOSR can be removed by, for example, patterning and selective etching processes. In this way, the gate structure of the MOS transistor in the second region MOSR can be formed. In addition, as shown in FIG7J , according to an embodiment of the present disclosure, the etching hard mask layer 719 and a portion of the second gate electrode layer 718 in the first region NVMR can be removed concurrently until the upper surface of the stacked structure 711, that is, the upper surface of the hard mask barrier layer 709, is exposed, and at the same time, the second gate electrode layer 718 is filled in the first trench 712 a and the second trench 712 b. 7J , the second gate electrode layer 718 filled in the first trench 712 a in the first region NVMR may correspond to, for example, the gate electrode 123 of the gate transistor MG 120 of the flash memory cell MC 100 ′ described above with reference to FIG. 5 , while the remaining second gate electrode layer 718 in the second region MOSR may form a gate electrode of a MOS transistor.

[0190] Subsequently, referring to FIG. 6 , in step S611, as shown in FIG. 7K , according to an embodiment of the present disclosure, a patterned mask layer can be formed in the first NVMR region by, for example, patterning. This patterned mask layer can be a patterned photoresist layer formed using a standard photolithography process and includes an opening corresponding to the second trench 712 b. Subsequently, the second gate electrode layer 718 and the gate dielectric layer 715 thereunder, exposed by the opening and not covered by the photoresist layer, can be removed by an anisotropic etching process. Specifically, the second gate electrode layer 718 and gate dielectric layer 715 in the second trench 712 b are removed, while the second gate electrode layer 718 and gate dielectric layer 715 in the first trench 712 a remain, thereby forming the gate structure of the memory transistor. Thus, the hard mask barrier layer 709 can correspond to, for example, the hard mask barrier portion 117 of the first memory transistor MS110 and the hard mask barrier portion 137 of the second memory transistor MD130 of the flash memory cell MC100 ′ described above with reference to FIG. 5 .

[0191] Subsequently, referring to FIG. 6 , in step S612 , as shown in FIG. 7L , according to an embodiment of the present disclosure, lightly doped source / drain regions 720 of flash memory cells of the first region NVMR and transistors of the second region MOSR may be formed by patterning one or more lightly doped source / drain (LDD) regions.

[0192] According to an embodiment of the present disclosure, the lightly doped source and drain regions 720 can be formed by, for example, an ion implantation process. In addition, according to an embodiment of the present disclosure, the ion implantation process for forming the lightly doped source and drain regions 720 of the flash memory cell in the first region NVMR and the ion implantation process for forming the lightly doped source and drain regions 720 of the MOS transistor in the second region MOSR may use the same or different ion species, doses, and energies. In addition, according to an embodiment of the present disclosure, the ion implantation process for forming the lightly doped source and drain regions 720 of the flash memory cell in the first region NVMR may be the same as the ion implantation process for forming the lightly doped source and drain regions 720 of at least one transistor (e.g., a low-voltage LV-MOS transistor, an interface IO-MOS transistor, or a high-voltage HV-MOS transistor) in the second region MOSR, for example, using the same ion species, doses, and / or energies.

[0193] For example, for an N-type flash memory cell (or NVM transistor) according to this embodiment, the ion implantation process for forming its lightly doped source and drain regions 720 may use N-type impurity ions, such as phosphorus ions or arsenic ions, to form N-type lightly doped source and drain regions 720 on the surface of the source and drain regions of the flash memory cell.

[0194] Alternatively, according to an embodiment of the present disclosure, before performing the ion implantation process for forming the lightly doped source and drain regions 720 of the flash memory cell, P-type impurity ions, such as boron ions or boron difluoride ions, may be additionally implanted to form a P-type wrapping region (P-Halo) (not shown) outside the lightly doped source and drain regions 720 of the flash memory cell to improve the punch-through characteristics and storage characteristics of the flash memory cell.

[0195] Subsequently, referring to FIG6 , in step S613, as shown in FIG7M , according to an embodiment of the present disclosure, sidewalls (spacers) 721 can be concurrently formed on both sides of the gate structure of the flash memory cell in the first region NVMR and the MOS transistor in the second region MOSR using a sidewall process commonly used in integrated circuit processes. For example, the sidewall process can first deposit one or more isolation dielectric layers on the surface of the substrate structure, and then use an anisotropic etching process to remove the isolation dielectric layers above the substrate structure, thereby forming the sidewalls 721.

[0196] Subsequently, as shown in FIG. 7M , according to an embodiment of the present disclosure, heavily doped source and drain regions 722 of the flash memory cells in the first region NVMR and the transistors in the second region MOSR may be formed by a heavily doped source and drain implantation process.

[0197] As shown in FIG. 7M , the lightly doped source and drain regions 720 and the heavily doped source and drain regions 722 of the flash memory cells in the first region NVM may together correspond to, for example, the source region 140 and the drain region 150 of the flash memory cell MC 100 ′ described above with reference to FIG. 5 .

[0198] 6 , in step S614, as shown in FIG7N , according to an embodiment of the present disclosure, an inter-polysilicon dielectric layer 723 may be deposited on the surface of the entire semiconductor device by, for example, a deposition process. According to an embodiment of the present disclosure, the inter-polysilicon dielectric layer 723 may include, for example, silicon oxide, silicon nitride, silicon glass, or a combination thereof.

[0199] Subsequently, as shown in Figure 7N, according to an embodiment of the present disclosure, the upper surface of the semiconductor device can be planarized by, for example, a CMP process and the upper surface of the gate structure of the low-voltage LV-MOS transistor in the second region, that is, the upper surface of the etched hard mask layer 719 in its gate region, and the upper surface of the gate structure of the selection transistor in the first region NVMR, that is, the upper surface of the second gate electrode layer 718 in its gate region, are exposed.

[0200] Subsequently, as shown in Figure 7N, according to an embodiment of the present disclosure, the gate structure of the low-voltage LV-MOS transistor in the second region can be removed by an etching process, that is, the etching hard mask layer 719, the second gate electrode layer 718 and the gate dielectric layer 715 are removed in sequence, and the gate structure of the selection transistor in the first region NVMR can also be optionally removed, that is, the second gate electrode layer 718 and the gate dielectric layer 715 in the first trench 712a are removed in sequence, so that the upper surface of the substrate 701 is exposed in the gate region of the low-voltage LV-MOS transistor and the optional selection transistor.

[0201] Subsequently, referring to FIG. 6 , in step S615 , as shown in FIG. 7O , according to an embodiment of the present disclosure, a gate structure including a high-K gate dielectric layer 716 made of a high-K material and a metal gate 717 can be formed in the gate region of the low-voltage LV-MOS transistor and the gate transistor by, for example, deposition, etching, and CMP processes. According to an embodiment of the present disclosure, the high-K material can have a dielectric constant of approximately 4 to 20 or greater. The high-K material can include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide. According to an embodiment of the present disclosure, the high-K gate dielectric layer 716 can be formed from a composite layer including two or more layers of the aforementioned high-K materials. According to an embodiment of the present disclosure, the metal gate 717 can include, for example, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, molybdenum, molybdenum oxide, a titanium nitride / tungsten stack, or a tungsten nitride / tungsten stack.

[0202] In fact, steps S614 and S615 described above with reference to Figures 7N and 7O can be a standard HKMG metal replacement gate process (or last gate process) for replacing the gate structure of the low-voltage LV-MOS transistor in the second region and optionally the gate transistor in the first region NVMR with an HKMG gate structure.

[0203] Those skilled in the art will recognize that although the gate structures of the low-voltage LV-MOS transistor in the second MOSR region and the gate transistor in the first NVMR region are replaced with HKMG gate structures in the embodiments shown in Figures 6 and 7A to 7O, the present disclosure is not limited thereto. According to the concepts of the present disclosure, among the low-voltage LV-MOS transistor, interface IO-MOS transistor, and high-voltage HV-MOS transistor in the second MOSR region, and the gate transistor in the first NVMR region, at least the gate structure of the low-voltage LV-MOS transistor in the second MOSR region should be replaced with the HKMG gate structure. According to alternative embodiments of the present disclosure, only the gate structure of the low-voltage LV-MOS transistor in the second MOSR region may be replaced with the HKMG gate structure, while the interface IO-MOS transistor and high-voltage HV-MOS transistor in the second MOSR region, and the gate transistor in the first NVMR region, still retain the original gate structure including the gate dielectric layer 715 and the second gate electrode layer 718. According to another alternative embodiment of the present disclosure, in addition to replacing the gate structures of the low-voltage LV-MOS transistor in the second MOSR region and the gate transistor in the first NVMR region with the HKMG gate structure, the gate structures of the interface IO-MOS transistor and / or the high-voltage HV-MOS transistor in the second MOSR region may also be replaced with the HKMG gate structure. All of these alternative embodiments are intended to be within the scope of the present disclosure.

[0204] In addition, according to an embodiment of the present disclosure, the materials of the high-K gate dielectric layer 716 and the metal gate 717 in the HKMG gate structure of the low-voltage LV-MOS transistor and / or the interface IO-MOS transistor and / or the high-voltage HV-MOS transistor in the second region MOSR and the HKMG gate structure of the pass transistor in the first region NVMR may be the same or different.

[0205] Although not shown, according to an embodiment of the present disclosure, a buffer layer may be further formed between the high-K gate dielectric layer 716 and the metal gate 717. According to an embodiment of the present disclosure, the buffer layer may include a work function-controlled metal material such as titanium nitride, tantalum, or titanium aluminum. In addition, according to an embodiment of the present disclosure, the materials of the buffer layers in the HKMG gate structure of the NMOS transistor (and PMOS transistor) in the MOS transistor in the second region MOSR and the gate transistor in the first region NVMR may be the same or different, so as to obtain different threshold voltages by controlling the work function.

[0206] Thus, according to the embodiment of the present disclosure, the front-end manufacturing process of the integration process of the flash memory cells in the first region NVMR and the MOS transistors in the second region MOSR is completed.

[0207] Finally, according to the embodiments of the present disclosure, one or more metal connection layers and corresponding contact holes and through-holes can be formed through the back-end manufacturing process commonly used in integrated circuit processes, thereby forming electrical connections between the flash memory cells in the first region NVMR and the transistors in the second region MOSR.

[0208] Thus, embodiments of methods for fabricating semiconductor devices including integrally formed non-volatile memory (NVM) transistors and metal oxide semiconductor (MOS) transistors according to the present disclosure have been described. For illustrative purposes, a limited number of possible embodiments of the present disclosure have been presented above. Although the present disclosure has been described with reference to the embodiments thereof, those skilled in the art will appreciate that various modifications and variations may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0209] Although this document contains many details, these details should not be construed as limitations on the scope of the present disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated as such, in some cases one or more features in a combination may be deleted from the claimed combination, and the claimed combination may involve subcombinations or variations of subcombinations.

Claims

1. A method for manufacturing a semiconductor device, in, The semiconductor device includes a first region in which a plurality of flash memory cells are formed and a second region in which metal oxide semiconductor (MOS) transistors are formed, and wherein each flash memory cell includes two storage transistors and a gate transistor disposed between the two storage transistors. The method comprises: providing a semiconductor substrate and forming an isolation structure therein; forming a storage gate dielectric stack and a first gate electrode layer of the storage transistor; Forming a gate structure of the storage transistor by patterning the storage gate dielectric stack and the first gate electrode layer; Concurrently forming a gate dielectric layer and a second gate electrode layer of the gate transistor and the MOS transistor; and The gate structure of the MOS transistor and the gate structure of the gate transistor are formed concurrently.

2. The method according to claim 1, further comprising: The gate structure of the MOS transistor is replaced by a high-K gate dielectric layer and a metal gate.

3. The method according to claim 1 or 2, further comprising: The gate structure of the gate transistor is replaced by a high-K gate dielectric layer and a metal gate.

4. The method according to claim 1, wherein: The gate structure of the storage transistor includes a channel region, the storage gate dielectric stack, the first gate electrode layer and a hard mask blocking portion from bottom to top along the vertical direction. Wherein, the gate structure of the gate transistor includes a channel region, the gate dielectric layer and the second gate electrode layer which are sequentially arranged along a vertical direction.

5. The method according to claim 1, wherein: An upper surface of the second gate electrode layer is higher than an upper surface of the first gate electrode layer.

6. The method according to claim 1, wherein: The MOS transistor disposed in the second region includes one or more of a low voltage MOS transistor, an interface MOS transistor, or a high voltage MOS transistor.

7. The method according to claim 6, wherein: The thickness of the gate dielectric layer of the gate transistor is the same as the thickness of the gate dielectric layer of any one of the low-voltage MOS transistor, the interface MOS transistor and the high-voltage MOS transistor.

8. The method according to claim 6, further comprising: At least the gate structure of the low voltage MOS transistor is replaced by a high-K gate dielectric layer and a metal gate.

9. The method according to claim 1, wherein: The flash memory cells in the first region are isolated by a first isolation structure, the MOS transistors in the second region are isolated by a second isolation structure, and the first region and the second region are isolated by the first isolation structure and / or the second isolation structure, and The first isolation structure is the same as or different from the second isolation structure.

10. The method according to claim 1, further comprising: Performing a first implantation process for forming a well region of the flash memory cell and a channel region of the storage transistor, and for adjusting a threshold voltage of the storage transistor; Performing a second implantation process for forming a well region and a channel region of the MOS transistor and for adjusting a threshold voltage of the MOS transistor; as well as performing a third implantation process for forming a channel region of the gate transistor and for adjusting a threshold voltage of the gate transistor, The ion type, dosage and / or energy of the first implantation process and the third implantation process are the same or different.

11. The method according to claim 10, wherein: The second implantation process is performed before forming a storage gate dielectric stack and a first gate electrode layer of the storage transistor, or after forming a gate structure of the storage transistor by patterning the storage gate dielectric stack and the first gate electrode layer.

12. The method according to claim 10, wherein: The second implantation process is performed after forming a gate structure of the storage transistor by patterning the storage gate dielectric stack and the first gate electrode layer.

13. The method according to claim 10, wherein: The first implantation process and the third implantation process are performed so that the doping concentration of the channel region of the memory transistor is lower than the doping concentration of the channel region of the gate transistor.

14. The method according to claim 1, wherein: The storage gate dielectric stack includes a first oxide layer, a storage dielectric layer and a second oxide layer from bottom to top along the vertical direction. The storage medium layer includes first to third storage medium sub-layers formed of silicon nitride from bottom to top along the vertical direction, and The second storage medium sublayer has a higher silicon content than the first storage medium sublayer and the third storage medium sublayer.

15. The method according to claim 14, wherein: The storage medium layer further includes a fourth storage medium sublayer above the third storage medium sublayer, and The fourth storage medium sublayer has a higher silicon content than the third storage medium sublayer.

16. The method according to claim 1, further comprising: A high work function metal interface layer is formed between the storage gate dielectric stack and the first gate electrode layer.

17. The method according to claim 1, further comprising: An isolation layer for isolating the gate transistor and the memory transistor is formed.

18. The method of claim 1, further comprising: Metal silicide is formed on surfaces of the gate electrodes of the gate transistor and the MOS transistor.

19. The method according to claim 18, further comprising: A metal silicide is formed on the entire or partial surface of the gate electrode of the memory transistor.

20. The method according to claim 2, further comprising: A buffer layer is formed between the high-K gate dielectric layer and the metal gate.

21. The method according to claim 3, further comprising: A buffer layer is formed between the high-K gate dielectric layer and the metal gate.

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