Pixel circuit with memory circuit and image sensor for event detection

Abstract

A pixel circuit includes a capacitive element that receives a pixel voltage VPR at a first electrode. An event detection circuit outputs a comparator result signal VC, wherein the comparator result signal VC changes to an active level when a resettable floating voltage VF at a floating second electrode of the capacitive element passes a predefined threshold voltage VT. A multi-mode memory circuit outputs an event signal EV, wherein in a first mode the event signal EV follows the comparator result signal VC and in a second mode the event signal EV changes to an active level in response to receiving an active comparator result signal VC and changes to an inactive level in response to receiving an active memory reset signal RESL.

Description

PIXEL CIRCUIT WITH MEMORY CIRCUIT AND IMAGE SENSOR FOR EVENT DETECTIONThe present disclosure relates to pixel circuit including a memory circuit and to an image sensor for event detection . More particularly, the present disclosure relates to the field of event detection sensors that respond to predefined changes in light intensity, such as dynamic vision sensors ( DVS ) and event-based vision sensors ( EVS ) .BACKGROUNDEvent detection image sensors like DVS and EVS deliver information about the position of predefined changes in the imaged scene . Unlike image sensors that transfer large amounts of image information in frames , transfer of information about pixels that do not change can be omitted, resulting in a sort of in-pixel data compression . The in-pixel data compression removes data redundancy and combines high temporal resolution with low latency, low power consumption, high dynamic range , and little motion blur .Pixel circuits for DVS and EVS detect ON events indicating an increase in radiation intensity from an initial value by at least a predefined step-up value and OFF events indicating a decrease in radiation intensity from the initial value by at least the predefined step-down value . EVS pixel circuits with a single comparator sequentially compare a differential voltage derived from the current radiation intensity and a previous radiation intensity to a first threshold voltage to check for ON events and to a second threshold to check for OFF events . EVS pixel circuits with a capacitive amplifier typically use two parallel comparators that can simultaneously test for ON events and for OFF events .An EVS pixel circuit that detects an ON event or an OFF event stores the event until the pixel circuit is read out again . Once a pixel circuit is read out , the event is cleared . Clearing the event typically includes an automatic zeroing process ("autozero process" , "autozeroing" ) that resets the differential voltage to an initial value .SUMMARYIn EVS image sensors , an active comparator result signal indicating that the pixel circuit has detected an event triggers a readout request toan arbiter circuit . The arbiter circuit receives and prioritizes the current readout requests . The arbiter circuit outputs an acknowledgement signal to the pixel circuit selected for the next readout . In response to receiving the acknowledgement signal , the pixel circuit outputs an event signal indicating the type of detected event on a data bus and starts the autozero process .During a waiting time that begins with the detection of an event and ends with the start of outputting the detected event , the radiation intensity may change again in direction of the initial value such the differential voltage does not longer exceed the predefined step-up value or fall below the predefined step-down value . The comparator result signals return to inactive voltage levels . When the pixel circuit outputs the event signal on the basis of the instantaneous comparator result signal , the event data signal does not indicate any event . In this way, short light pulses and short dark periods ending before the pixel circuit outputs the event data, can be missed . The waiting time for which the effect occurs depends on the instantaneous activity of the pixel circuits of the image sensor .The present technology has been made in view of this situation and aims to improve the detection of events in pixel circuits for event detection .In this regard, the present disclosure relates to a pixel circuit that includes a capacitive element configured to receive a pixel voltage VPR at a first electrode . An event detection circuit outputs a comparator result signal VC, wherein the comparator result signal VC changes to an active level when a resettable floating voltage VF at a floating second electrode of the capacitive element passes a predefined threshold voltage VT . A multi-mode memory circuit outputs an event signal EV, wherein in a first mode the event signal EV follows the comparator result signal VC and in a second mode the event signal EV changes to an active level in response to receiving an active comparator result signal VC and changes to an inactive level in response to receiving an active memory reset signal RESL .The first mode is oriented towards the human visual sense and performs adaptive data compression at pixel level . The more movements and changes determine a scene , the more events , especially transient events , are filtered out at pixel level . The second mode enables the reliable detection of short light events typical for technical processes , e . g . detection of artificial radiation sources in the imaged scene and / ordetection of radiation emitted by a radiation source for range measurement , e . g . by using structured light and / or time-of-f light approaches . TheThe described embodiments , together with further advantages , will be best understood by reference to the following detailed description taken in conj unction with the accompanying drawings .BRIEF DESCRIPTION OF THE DRAWINGSFIG . 1 is a schematic diagram illustrating a configuration example of an imaging apparatus including a solid-state imaging device with pixel circuits according to the embodiments .FIG . 2 is a simplified block diagram illustrating a configuration example of a solid-state imaging device in accordance with an embodiment with pixel circuits with multi-mode memory circuit integrated in an image sensor for synchronous readout .FIG . 3 is a simplified block diagram illustrating a configuration example of a solid-state imaging device in accordance with an embodiment with pixel circuits for continuous detection integrated in an image sensor for asynchronous readout .FIG . 4 is a schematic diagram illustrating an embodiment in which a solid-state imaging device has a two-layer structure in a stacked CIS configuration .FIG . 5 is a simplified circuit diagram illustrating a configuration example of a pixel circuit with multi-mode memory circuit in accordance with an embodiment .FIG . 6 is a simplified circuit diagram illustrating a configuration example of a pixel circuit with a multi-mode memory circuit based on two latch circuits in accordance with an embodiment .FIG . 7 is a simplified circuit diagram illustrating a configuration example of a pixel circuit with a multi-mode memory circuit based on two latch circuits with enable inputs in accordance with another embodiment .FIG . 8 is a time diagram for illustrating a method of operating an image sensor with pixel circuits as illustrated in FIG . 7 in accordance with an embodiment .FIG . 9 is a block diagram depicting an example of a schematic configuration of a vehicle control system .FIG . 10 is a diagram of assistance in explaining an example of installation positions of an outside-vehicle information detecting section and an imaging section of the vehicle control system of FIG . 9 .DETAILED DESCRIPTIONEmbodiments for implementing techniques of the present disclosure will be described below in detail using the drawings . The techniques of the present disclosure are not limited to the described embodiments , and various numerical values and the like in the embodiments are illustrative only . The same elements and elements with the same functions are denoted by the same reference signs . Duplicate descriptions are omitted .Connected electronic elements may be electrically connected through a direct and permanent low-resistive connection, e . g . , through a conductive line . The terms "connected" , "electrically connected" and "signal-connected" may also include a connection through other electronic elements provided and suitable for permanent and / or temporary signal transmission and / or transmission of energy . For example , electronic elements may be electrically connected or signal-connected through resistors , capacitors , and electronic switches such as transistors or transistor circuits , e . g . , MOSFETs , transmission gates , and others .The load path of a transistor is the controlled current path through a transistor . For example , a voltage applied to the gate of a field effect transistor ( FET ) controls the current flow through the load path ( controlled path) between source and drain of the FET by field effect .A digital signal alternates between at least one active level and at least one passive level . A digital signal having an active level is active . A digital signal having an inactive level is inactive . For each signal separately, the active level can be a digital high level and the inactive level a digital low level , or the active level can be a digital low level and the inactive level a digital high level .In FIG . 1 , an imaging apparatus 1 includes an optical system 91 , a solid- state imaging device 90 , a storage unit 92 , and a control unit 93 . The optical system 91 includes one or more lenses and various mechanisms such as an autofocus mechanism and a diaphragm mechanism and guides light from an obj ect to a light receiving surface of the solid-state imaging device 90 .The solid-state imaging device 90 includes an image sensor having a plurality of pixel circuits . Each pixel circuit includes a photoelectric conversion element that converts incident radiation into electric signals by photoelectric conversion, and outputs the electric signals . The solid-state imaging device 90 further includes a signal processing unit that performs predetermined signal processing on the electric signals output from the pixel circuits and outputs image data based on the electric signals .The storage unit 92 stores the image data output from the solid-state imaging device 90 in a storage medium. The storage medium may include a volatile storage medium and / or non-volatile storage medium . The nonvolatile storage medium may be or include a flash memory or a hard disk drive . The non-volatile storage medium may be or include a dynamic random access memory ( DRAM) .The control unit 93 controls the solid-state imaging device 90 , such that the solid-state imaging device 90 performs an imaging operation . The imaging operation includes capturing an image of an obj ect or a scene and outputting image data including image information about changes in the appearance of the obj ect or in the scene .FIG . 2 and FIG . 3 are block diagrams illustrating configuration examples of a solid-state imaging device 90 with an image sensor 80 that includes pixel circuits 100 applicable to the embodiments . The solid-state imaging device 90 includes the image sensor 80 and a signal processing unit 60 . In both figures , the image sensor 80 includes a pixel array 10 , a signal buffer circuit 20 , a row arbiter 30 , and a sensor control circuit 50 .In the pixel array 10 , a plurality of pixel circuits 100 is arrayed in a two-dimensional matrix in pixel rows and pixel columns . For simplicity, pixel circuits 100 belonging to the same pixel row are arranged along a horizontal line in FIG . 2 and FIG . 3 , and pixel circuits 100 belongingto the same pixel column are arranged along a vertical line in FIG . 2 and FIG . 3 .Each pixel circuit 100 includes a radiation sensitive circuit that outputs a pixel voltage with a voltage level corresponding to the intensity of received radiation .The pixel circuit 100 further includes a capacitive element that receives a pixel voltage at a first electrode . An event detection circuit outputs a comparator result signal , wherein the comparator result signal changes to an active level when a resettable floating voltage at a floating second electrode of the capacitive element passes a predefined threshold voltage . A multi-mode memory circuit outputting an event signal is capable of at least two modes of operating . In a first mode the event signal follows the comparator result signal . In a second mode the event signal changes to an active level in response to receiving an active comparator result signal and changes to an inactive level in response to receiving an active memory reset signal .The event detection circuit detects events based on a magnitude of changes in a pixel voltage received from the radiation sensitive circuit . Each event detection circuit is resettable to an initial state by temporarily turning on an autozero switch that resets the resettable voltage during autozeroing . A pixel logic controls the output of event data from the pixel circuit 100 and the autozeroing of the event detection circuits .The event data may indicate that the intensity of incident radiation has decreased by more than a step-down value compared to the previous event readout ("OFF event" ) . Alternatively, the event data may indicate that the intensity of incident radiation has increased by more than a step- up value compared to the magnitude at the previous event readout ("ON event" ) .The signal buffer circuit 20 passes one or more threshold voltages and a memory mode signal to groups of pixel circuits 100 through a control bus 21 . Each group of pixel circuits 100 can include some or all pixel circuits 100 of a pixel row, the pixel circuits 100 of more than one pixel row, or all pixel circuits 100 of the pixel array 10 .FIG . 2 concerns an image sensor 80 for synchronous readout . Group control buses 31 connect the pixel circuits 100 with the row arbiter 30 . Eachgroup control bus 31 connects the pixel circuits 100 of one group with the row arbiter 30 . Each group control bus 31 includes a group request line for transmitting request signals from the pixel circuits 100 of the pixel group to the row arbiter 30 , and a group acknowledgement line for transmitting a group acknowledgement signal from the row arbiter 30 to the pixel circuits 100 of a group of pixel circuits 100 to be selected .For each pixel circuit 100 detecting an event , a pixel logic of the concerned pixel circuit 100 outputs an active request to the row arbiter 30 on the group request line . For transmitting the request , a request signal transmitted on the group request line has an active level .The row arbiter 30 performs arbitration among the pending active requests output from the pixel circuits 100 of the pixel array 10 . The row arbiter 30 selects a request received from a specific group of pixel circuits 100 , acknowledges the selected request by outputting a confirmation on the group control bus 31 , and transmits the corresponding group address ( e . g . the row number ) to a column readout circuit 40 . For transmitting the confirmation, the row arbiter 30 outputs an active group acknowledgement signal on the group acknowledgement line . The active group acknowledgement signal selects a group of pixel circuits 100 .In response to the confirmation, all selected pixel circuits 100 in which an event has been detected, apply the event data on the respective event data bus 41 . Each event data bus 41 may be connected to some or all pixel circuits 100 of a same pixel column, or to all pixel circuits 100 of more than one pixel column .The event data bus 41 may include a common data line for transmitting the ON events and the OFF events by different signal levels or in a time multiplex scheme . In the illustrated embodiment , the event data bus 41 includes a first data line 42 for transmitting the ON events and a second data line 43 for transmitting the OFF events . For transmitting an ON event , an on-event data signal transmitted on the first data line 42 has an active level . For transmitting an OFF event , an off-event data signal transmitted on the second data line 43 has an active level .The column readout circuit 40 receives the event data from all pixel circuits 100 of the selected pixel group via the event data bus 41 , and the group address ( es ) of the selected pixel group from which the received event data originates from the row arbiter 30 . From the group address and identifiers of the event data buses 41 transmitting event data , thecolumn readout circuit 40 compiles a digital address event representation AER for each event . The AER includes the group address , a column address derived from the identifiers of the event data busses transmitting events , the event data , and, if applicable , a time stamp . The column readout circuit 40 outputs the AERs to the signal processing unit 60 .The solid stage imaging device 90 in FIG . 3 is configured for asynchronous event-triggered readout . Each pixel circuit 100 that detects an event indicates the event by outputting a group request signal on a group request line of a group control bus 31 to the row arbiter 30 and a column request signal on a column interface bus 46 to a column arbiter 45 . In the row arbiter 30 and the column arbiter 45 , the request signals trigger the compilation of event information . The event information includes a pixel address identifying the position of the pixel circuit 100 in the pixel array 10 , the sign of the change in light intensity, and a time stamp . The row arbiter 30 and the column arbiter 45 output the event information to the signal processing unit 60 and confirm to the pixel circuit 100 reception of the event . Upon receiving the confirmation, the event in the pixel circuit 100 is cleared and the pixel circuit 100 is reset .The sensor control circuits 50 of FIG . 2 and FIG . 3 may control a timing of changing analog voltage signals in the signal buffer circuit 20 , a selection of voltage levels output by the signal buffer circuit 20 according to internal states and / or user settings , the memory mode signal , and / or a communication between the column readout circuit 40 and the signal processing unit 60 of FIG . 2 or between the row arbiter 30 , the column arbiter 45 and the signal processing unit 60 of FIG . 3 as indicated by the dashed line .The signal processing unit 60 receives the AERs . The signal processing unit 60 may execute signal processing such as image recognition processing based on the received AERs . The signal processing unit 60 may output processed image data to the storage unit 92 of FIG . 1 and / or through a wired or wireless electronic interface .Solid-state imaging devices 90 as described with reference to FIG . 2 and FIG . 3 can be provided as , for example , stacked contact image sensors ( CIS ) formed by stacking a plurality of semiconductor chips . As an example , the solid-state imaging device 90 can be formed by a two-layer structure in which semiconductor chips are stacked in two layers .FIG . 4 is a diagram illustrating an example in which the solid-state imaging device 90 of FIG . 2 or FIG . 3 is formed by a stacked CIS having a two-layer structure with a radiation receiving chip 910 and a processing chip 920 . The radiation receiving chip 910 includes at least the photoelectric conversion element . For example , the radiation receiving chip 910 may include only the photoelectric conversion element , or a part of the radiation sensitive circuit including the photoelectric conversion element and one or more transistors , or the complete radiation sensitive circuit , or the complete radiation sensitive circuit and further elements of the pixel circuits . The processing chip 920 includes the further elements of the pixel circuits 100 , e . g . , the event detection circuit and the pixel logic . The right side of FIG . 4 shows a solid- state imaging device 90 formed by j oining the radiation receiving chip 910 and the processing chip 920 , wherein contact pads on the radiation receiving chip 910 and corresponding contact pads on the processing chip 920 are bonded together to form electric contacts between the radiation receiving chip 910 and the processing chip 920 .FIG . 5 shows a block diagram of a pixel circuit 100 for a synchronous image sensor 80 as illustrated in FIG . 2 or an asynchronous image sensor 80 as illustrated in FIG . 3 .The pixel circuit 100 includes a capacitive element 121 that receives a pixel voltage VPR at a first electrode . An event detection circuit 140 outputs a comparator result signal VC, wherein the comparator result signal VC changes to an active level when a resettable floating voltage VF at a floating second electrode of the capacitive element 121 passes a predefined threshold voltage VT . A multi-mode memory circuit 200 outputs an event signal EV, wherein in a first mode the event signal EV follows the comparator result signal VC and in a second mode the event signal EV changes to an active level in response to receiving an active comparator result signal VC and changes to an inactive level in response to receiving an active memory reset signal RESL .A voltage level of the pixel voltage VPR increases with increasing intensity of radiation detected by the pixel circuit 100 .The capacitive element 121 receives the pixel voltage VPR at the first electrode . The second electrode of the capacitive element 121 forms a differentiation node 122 . The differentiation node 122 is forced to a predefined reference voltage in an autozero period . Directly after the autozero period, a capacitor voltage VPT across the capacitive element121 is defined by a voltage difference between the pixel voltage VPR directly after reset and the reference voltage VR .In a detection period following the autozero period, the differentiation node 122 floats . When the first differentiation node 122 floats , the capacitor voltage VP remains at least approximately constant and the floating voltage VF follows changes of the pixel voltage VPR . Changes in the pixel voltage VPR with respect to the pixel voltage VPR at the end of resetting are converted into voltage changes with respect to the reference voltage VR .In the detection period, the pixel circuit 100 is in a detection mode and an instantaneous value of the floating voltage VF is a function of the difference between the instantaneous voltage level of the pixel voltage VPR and the voltage level of the pixel voltage VPR directly after resetting . The floating voltage VF at the differentiation node 122 is a function of a change in detected radiation intensity . The change in radiation intensity concerns the difference in radiation intensity between the current time and immediately before the end of resetting .The event detection circuit 140 outputs an active comparator result signal VC when the floating voltage VF at the differentiation node 122 passes a predefined threshold voltage VT . For example , the event detection circuit 140 outputs an active comparator result signal VC as long as the floating voltage VF at the differentiation node 122 exceeds a predefined upper threshold voltage or as long as the floating voltage VF at the differentiation node 122 is below a predefined lower threshold voltage .The multi-mode memory circuit 200 operates in at least two different modes :In a first mode , the event signal EV output from the multi-mode memory circuit 200 follows the comparator result signal VC , wherein the event signal EV is active only when the comparator result signal VC is active , and the event signal EV is inactive only when the comparator result signal VC is inactive . Changes of the event signal EV between active and inactive can be delayed with respect to corresponding changes of the comparator result signal by some nanoseconds .In the second mode ( latch mode ) , the multi-mode memory circuit 200 latches transitions of the comparator result signal VC from inactive toactive and outputs the latched active comparator result signal VC until an active memory reset signal RESL resets the multi-mode memory circuit 200 .In the first mode of the multi-mode memory circuit , the pixel circuit performs adaptive data compression at pixel level by suppressing fast changes in the illumination of pixels . The second mode enables the reliable detection of short light events from artificial radiation sources like pulsed radiation sources in the imaged scene and / or detection of reflected radiation from radiation emitters for structured light and / or time of flight applications .The multi-mode memory circuit 200 is in the first mode when a memory mode signal MODL is inactive and in the second mode when the memory mode signal MODL is active .The same memory mode signal MODL may be applied to all pixel circuits 100 of the pixel array . Alternatively, a first memory mode signal MODL may be applied to a first group of pixel circuits and a second memory mode signal MODL may be applied to a second group of pixel circuits 100 . The second memory mode signal may be the inverted first memory mode signal . The first and second groups of pixel circuits 100 may complement each other to the pixel array . The first group of pixel circuits 100 may include one or more complete pixel columns , one or more complete pixel rows , or pixel sub-arrays with pixel circuits 100 from neighboring pixels columns and neighboring pixel rows .In a configuration for range measurements like ToF and patterned light approaches , changes of the memory mode signal may be synchronized with emitting radiation from a radiation source .The concept of the memory mode signal MODL prevents causing excessive sensitivity to fast changing signals or noise coupling , and facilitates an adj ustable trade-off between depth mapping performance and 2D-imaging performance of an image sensor .The functionalities of the event detection circuit 140 and the multimode memory circuit 200 can be combined in a latched comparator or in a serial combination of comparator circuits and latches , e . g . modified RS flip flops .FIG . 6 shows an example of a pixel circuit 100 with the event detection circuit 140 including two comparator circuits 131 , 132 operating in parallel .The illustrated pixel circuit 100 includes a radiation sensitive circuit 110 that converts incident radiation into the pixel voltage VPR, wherein the pixel voltage VPR increases with increasing radiation intensity .The radiation sensitive circuit 110 includes a photoelectric conversion element 111 and a photoreceptor circuit 112 . The photoelectric conversion element 111 may include or consist of a photodiode which by means of the photoelectric effect converts electromagnetic radiation incident on a detection surface of the pixel circuit 100 into a photodetector current . The electromagnetic radiation may include visible light , infrared radiation and / or ultraviolet radiation . The amplitude of the photodetector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the photodetector current may increase approximately linearly with increasing intensity of the detected electromagnetic radiation .The photoreceptor circuit 112 converts the photodetector current into the pixel voltage VPR . The voltage level of the pixel voltage VPR is a function of the photodetector current , wherein in the voltage range of interest the voltage amplitude of the pixel voltage VPR continuously increases with continuously increasing photodetector current .The photoreceptor circuit 112 includes , for example , a logarithmic amplifier that logarithmically converts the photodetector current into a voltage signal and a buffer circuit that outputs the amplified and buffered voltage as the pixel voltage VPR . The pixel voltage VPR increases logarithmically with the photodetector current .A first electrode of a capacitive element 121 is electrically connected to an output of the photoreceptor circuit 112 and receives the pixel voltage VPR at a first electrode . A second electrode of the capacitive element 121 floats in a detection period . A floating voltage VF at the second electrode of the capacitive element 121 changes in response to a change of the pixel voltage VPR .The event detection circuit 140 of the pixel circuit 100 includes a capacitive amplifier circuit 120 that receives the floating voltage VFat an amplifier input and outputs an amplified voltage signal VA at an amplifier output .The capacitive amplifier circuit 120 includes a switched capacitor amplifier including an inverting amplifier circuit 123 and a feedback capacitor 125 . An input of the inverting amplifier circuit 123 is electrically connected to the second electrode of the capacitive element 121 . The inverting amplifier circuit 123 outputs the amplified voltage signal VA at an output of the capacitive amplifier circuit 120 , wherein the amplified voltage signal VA represents an amplified voltage difference between a previously evaluated pixel voltage VPR and the present pixel voltage VPR . The feedback capacitor 125 is electrically connected in parallel between the input of the inverting amplifier circuit 123 and the output of the inverting amplifier circuit 123 .The event detection circuit 140 includes a first comparator circuit 131 configured to output a first comparator result signal VC1 . The first comparator result signal VC1 is active when the amplified signal exceeds a first threshold voltage VT1 .The first comparator result signal VC1 is inactive when the amplified signal does not exceed the first threshold voltage VT1 . The first comparator circuit 131 receives the amplified voltage signal VA from the output of the capacitive amplifier circuit 120 at a first comparator input and compares the amplified voltage signal VA with the first threshold voltage VT1 applied to a second comparator input . The multimode memory circuit 200 receives the first comparator result signal VC1 at a first memory input I / S .The multi-mode memory circuit 200 outputs an on-event signal EVI at a first memory output O / Q . In the first mode , the on-event signal EVI follows the first comparator result signal VC1 . In the second mode , the on-event signal EVI changes to an active level in response to receiving an active first comparator result signal VC1 and changes to an inactive level in response to receiving the active memory reset signal RESL .A second comparator circuit 132 is configured to output a second comparator result signal VC2 . The second comparator result signal VC2 is active when the amplified signal falls below a second threshold voltage VT2 .The second comparator result signal VC2 is inactive when the amplified signal does not fall below the second threshold voltage VT2 . The second comparator circuit 132 receives the amplified voltage signal VA from the output of the capacitive amplifier circuit 120 at a second comparator input and compares the amplified voltage signal VA with the second threshold voltage VT2 applied to a second comparator input . The multimode memory circuit 200 receives the second comparator result signal VC2 at a second memory input I / S .The multi-mode memory circuit 200 outputs an off-event signal EV2 at a second memory output O / Q . In the first mode , the off-event signal EV2 follows the second comparator result signal VC2 . In the second mode , the off-event signal EV2 changes to an active level in response to receiving an active second comparator result signal VC2 and changes to an inactive level in response to receiving the active memory reset signal RESL .The first and second comparator circuits 131 , 132 simultaneously compare the amplified voltage signal VA output from the capacitive amplifier circuit 120 with the first voltage threshold VT1 and the second voltage threshold VT2 .The multi-mode memory circuit 200 includes a first latch circuit 210 and a second latch circuit 220 . The first latch circuit 210 and the second latch circuit 220 have the same electrical functionality . The first latch circuit 210 receives the first comparator result signal VC1 at the first memory input I / S and outputs the on-event signal EVI at the first memory output O / Q . The second latch circuit 220 receives the second comparator result signal VC2 at the second memory input I / S and outputs the off- event signal EV2 at the second memory output O / Q .The first latch circuit 210 and the second latch circuit 220 receive the same memory mode signal MODL at mode inputs MD and the same memory reset signal RESL at reset inputs R .The pixel logic 150 receives the on-event signal EVI at a first input I l and the off-event signal EV2 at a second input 12 .The pixel logic 150 of the pixel circuit 100 includes an arbiter interface circuit 155 that outputs an active request signal REQ in response to receiving an active event signal EV from the multi-mode memory circuit 200 .The active event signal EV can be the active on-event signal EVI received at the first input I I or the active off-event signal EV2 received at the second input 12 . A group control bus 31 connects the pixel circuits 100 of one pixel group with the row arbiter 30 . The group control bus 31 includes a group request line 32 that electrically connects request outputs RQ of the arbiter interface circuits 155 with an input of the row arbiter 30 of FIG . 2 or FIG" 3 . The request outputs RQ may be of the open-collector type , by way of example .The row arbiter 20 as illustrated in FIG . 2 or FIG . 3 receives active request signals REQ from various pixel groups and selects one of the requesting pixel groups for readout by transmitting an active acknowledgement signal ACK selectively for the selected pixel group . To this purpose , the group control bus 31 includes a group acknowledgement line 33 for transmitting an acknowledgement signal ACK from the row arbiter 30 to acknowledgement inputs AK of the pixel circuits 100 of the selected pixel group .A pixel logic 150 of the pixel circuit 100 includes an event output circuit 151 that outputs an event data signal ON / OFF on an event data bus 41 in response to receiving an active acknowledgement signal ACK .More particularly, in response to receiving the active acknowledgement signal ACK at the acknowledgement input AK, the event output circuit 151 outputs an on-event data signal ON through a first data output DOI to the first data line 42 and an off-event data signal OFF through a second data output DO2 to the second data line 43 for a synchronous readout , wherein the on-event data signal ON is active only when the on-event signal EVI is active , and the off-event data signal OFF is active only when the off-event signal EV2 is active .The pixel logic 150 of the pixel circuit 100 further includes a reset output circuit 154 that outputs the active memory reset signal RESL in response to receiving an active acknowledgement signal ACK .The reset output circuit 154 outputs the memory reset signal RESL at a reset output ORes . A change of the memory reset signal RESL to the active level is delayed with respect to a change of the acknowledgement signal ACK to the active level by some nanoseconds , or is not delayed . The memory reset signal RESL and the active one of the on-event data signal ON and the off-event data signal OFF may simultaneously change to the active level or the change to the active level of one of the on-eventdata signal ON and the off-event data signal OFF and the memory reset signal RESL may be slightly delayed with respect to each other by at least some nanoseconds . A change of the memory reset signal RESL to the inactive level may have a fixed temporal relationship with the autozero period of the pixel circuit 100 .The event detection circuit 140 further includes an autozero switch circuit m that resets the resettable floating voltage VF in response to receiving an active autozero switch signal AZSW in an autozero period .The autozero switch circuit 126 includes a switched path between the input of the inverting amplifier circuit 123 and the output of the inverting amplifier circuit 123 . The autozero switch circuit 126 may include a single field effect transistor ( FET ) of the enhancement mode or an n channel FET and a p channel FET with the switched paths electrically connected in parallel .In the autozero period, the pixel circuit 100 is in an autozero mode that resets the floating voltages VF at the differentiation node 122 to a predefined reset voltage . Outside the autozero period, the autozero switch circuit 126 disconnects the second electrode of the capacitive element 121 from the output of the inverting amplifier circuit 123 . The autozero switch circuit 126 allows to reset the potential at the differentiation node 122 to the reset voltage . In a detection period following the autozero period, the floating voltage VF follows a change of the pixel voltage VPR .The pixel logic 150 further includes an autozero control circuit 159 that outputs the active autozero switch signal AZSW in response to receiving an active acknowledgement signal ACK .The autozero control circuit 159 outputs the autozero switch signal AZSW at an autozero switch output OAz . The autozero switch signal AZSW changes between an active level and an inactive level . An active autozero switch signal AZSW turns on the autozero switch circuit 126 for the autozero period . An inactive autozero switch signal AZSW turns off the autozero switch circuit 126 at least outside the autozero period, e . g . , for the detection period .If the autozero switch circuit 126 includes an n channel FET ( nFET ) , the active level of the autozero switch signal AZSW is the digital high level . If the autozero switch circuit 126 includes a p channel FET(pFET ) , the active level of the autozero switch signal AZSW is the digital low level .If the autozero switch circuit 126 includes a pFET and an nFET with the load paths electrically connected in parallel , the autozero switch signal AZSW is applied to the gate of the nFET and a complementary autozero switch signal xAZSW is applied to the gate of the pFET , wherein the autozero switch signal AZSW and the complementary autozero switch signal xAZSW have complementary active signal levels . The autozero switch signal AZSW and the complementary autozero switch signal xAZSW simultaneously change from the inactive level to the active level and simultaneously change from the active level to the inactive level .In the pixel circuit 100 of FIG . 7 , the multi-mode memory circuit 200 is insensitive to the comparator result signal VC when an input enable signal ENL in inactive and is sensitive to the active comparator result signal VC when the input enable signal ENL is active .When the multi-mode memory circuit 200 includes a first latch circuit 210 and a functionally identical second latch circuit 220 , the first latch circuit 210 receives the input enable signal ENL at a first enable input EN, and the second latch circuit 220 receives the input enable signal ENL at a second enable input EN .When the input enable signal ENL is active , the first and second latch circuits 210 , 220 are sensitive to the first and second comparator result signals VC1 , VC2 . When the first and second latch circuits 210 , 220 are sensitive to the first and second comparator result signals VC1 , VC2 , the first and second latch circuits 210 , 220 operate in the operation mode selected by the memory mode signal MODL . When the input enable signal ENL is inactive , the first and second latch circuits 210 , 220 are not sensitive ( opaque ) to the first and second comparator result signals VC1 , VC2 and the logic level of the on-event signal ON and the off-event signal OFF do not change in response to a change of the first and / or second comparator result signals VC1 , VC2 .The input enable signal ENL may be controlled by the sensor controller 50 of FIG . 2 or FIG . 3 and transmitted to the pixel circuits via enable lines of the control bus 21 . For example , the sensor controller 50 may set the input enable signal ENL to the inactive level for a preset time when event activity of the image sensor exceeds a predefined threshold .In the illustrated embodiment , the pixel logic 150 includes an enable control circuit 158 configured to change the enable signal ENL from active to inactive and from inactive to active in response to a change of an internal condition of the pixel logic 150FIG . 8 shows a time diagram for some of the signals of the pixel circuit100 in FIG . 7 . For each illustrated signal , the active level is the high level .At the beginning, the input enable signal ENL and the memory mode signal MODL are active . The pixel circuit 100 is in the second mode ( latch mode ) . The autozero switch signal AZSW is inactive . The pixel circuit 100 is in the detection period .When the intensity of radiation incident on a radiation-sensitive region of the photoelectric conversion element 111 increases to an extent that the amplified voltage signal VA exceeds the first threshold voltage VT1 , the first comparator result signal VC1 changes to the active level at t=tO and sets the first latch circuit 210 , wherein the on-event signal EVI changes to the active level .Shortly after, at t=tl , the pixel logic 150 outputs an active request signal REQ to the row arbiter . When the row arbiter selects the pixel group including the requesting pixel circuit 100 for the next readout , the row arbiter sends an active acknowledgement signal ACK to the pixel group including the requesting pixel circuit 100 .The pixel circuit 100 receives the active acknowledgement signal ACK at t=t3 . In response to receiving the active acknowledgement signal ACK, the pixel circuit 100 may proceed with outputting the event data , e . g . , by outputting the on-event data signal ON to a data signal line or by outputting a column request signal to a column arbiter .At t=t4 , an autozero period starts with the pixel logic 150 outputting an active autozero switch signal AZSW with active high level , and an active memory reset signal RESL . The active autozero switch signal AZSW turns on the autozero switch circuit 126 . The active memory reset signal RESL resets the first latch circuit 210 , wherein the on-event signal EVI changes to the inactive level .At t=t5 the autozero switch signal AZSW begins to fall and turns off the autozero switch circuit 126 sufficiently slowly . At t=t 6 the autozeroswitch signal AZSW reaches the signal low level . The slow ramp of the autozero switch signal AZSW prevents alterations of the floating voltage VF, when the autozero switch circuit 126 turns off . At t=t7 , the pixel logic 150 switches the memory reset signal RESL to the inactive level .The length of the time period between tl and t3 depends on the number of events detected per time unit ( event activity) . At high event activity, the time period can be long enough such that the comparator result signal VC1 returns to the inactive level within this time period, wherein the event would be lost . The latching operation prevents the loss of such events . For example , the input enable signal ENL may be low when the active acknowledgement signal ACK is high : this may prevent the latch to store new events and trigger a new request during read-out and while the current REQ-ACK cycle is not finished .FIG . 9 is a block diagram depicting an example of schematic configuration of a vehicle control system as an example of a system to which the technology according to an embodiment of the present disclosure can be applied .The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001 . In the example depicted in FIG . 9 , the vehicle control system 12000 includes a driving system control unit 12010 , a body system control unit 12020 , an outside-vehicle information detecting unit 12030 , an in- vehicle information detecting unit 12040 , and an integrated control unit 12050 . In addition, a microcomputer 12051 , a sound / image output section 12052 , and a vehicle-mounted network interface 12053 are illustrated as a functional configuration of the integrated control unit 12050 .The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs . For example , the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle , such as an internal combustion engine , a driving motor, or the like , a driving force transmitting mechanism for transmitting the driving force to wheels , a steering mechanism for adj usting the steering angle of the vehicle , a braking device for generating the braking force of the vehicle , and the like .The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs . For example , the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device , or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal , a fog lamp, or the like . In this case , radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020 . The body system control unit 12020 receives these input radio waves or signals , and controls a door lock device , the power window device , the lamps , or the like of the vehicle .The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000 . The outside-vehicle information detecting unit 12030 can be connected with an imaging section 12031 . The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle and receives the imaged image . Based on the received image , the outside-vehicle information detecting unit 12030 may perform processing of detecting an obj ect such as a human, a vehicle , an obstacle , a sign, a character on a road surface , or the like , or processing of detecting a distance thereto .The imaging section 12031 may be or may include an image sensor or a solid-state imaging device with an image sensor including pixel circuits according to the embodiments of the present disclosure . The light received by the imaging section 12031 may be visible light or may be invisible light such as infrared rays or the like .The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include an image sensor or a solid-state imaging device with an image sensor according to the embodiments of the present disclosure . The in-vehicle information detecting unit 12040 is , for example , connected with a driver state detecting section 12041 that detects the state of a driver . The driver state detecting section 12041 , for example , includes a camera that includes the solid-stage imaging device and that is focused on the driver . Based on detection information input from the driver state detecting section 12041 , the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree ofconcentration of the driver or may determine whether the driver is dozing .The microcomputer 12051 can calculate a control target value for the driving force generating device , the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040 and output a control command to the driving system control unit 12010 . For example , the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS ) which functions include collision avoidance or shock mitigation for the vehicle , following driving based on a following distance , vehicle speed maintaining driving, a warning of collision of the vehicle , a warning of deviation of the vehicle from a lane , or the like .In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like , by controlling the driving force generating device , the steering mechanism, the braking device , or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040 .In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 . For example , the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example , in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030 .The sound / image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle . In the example of FIG . 9 , an audio speaker 12061 , a display section 12062 , and an instrument panel 12063 are illustratedas the output device . The display section 12062 may, for example , include at least one of an on-board display or a head-up display .FIG . 10 is a diagram depicting an example of the installation position of the imaging section 12031 , wherein the imaging section 12031 may include imaging sections 12101 , 12102 , 12103 , 12104 , and 12105 .The imaging sections 12101 , 12102 , 12103 , 12104 , and 12105 are , for example , disposed at positions on a front nose , side-view mirrors , a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle . The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100 . The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100 . The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100 . The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle , a pedestrian, an obstacle , a signal , a traffic sign, a lane , or the like .Incidentally, FIG . 10 depicts an example of photographing ranges of the imaging sections 12101 to 12104 . An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose . Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the side view mirrors . An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door . A bird ' s-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104 , for example .At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information . For example , at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements , imaging element having pixels for phase difference detection or may include a ToF module including an image sensor or a solid-state imaging device with an image sensor including pixel circuits according to the embodiments of the present disclosure .For example , the microcomputer 12051 can determine a distance to each three-dimensional obj ect within the imaging ranges 12111 to 12114 and a temporal change in the distance ( relative speed with respect to the vehicle 12100 on the basis of the distance information obtained from the imaging sections 12101 to 12104 , and thereby extract , as a preceding vehicle , a nearest three-dimensional obj ect in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed ( for example , equal to or more than 0 km / hour ) . Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance and perform automatic brake control ( including following stop control ) , automatic acceleration control ( including following start control ) , or the like . It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like .For example , the microcomputer 12051 can classify three-dimensional obj ect data on three-dimensional obj ects into three-dimensional obj ect data of a two-wheeled vehicle , a standard-sized vehicle , a large-sized vehicle , a pedestrian, a utility pole , and other three-dimensional obj ects on the basis of the distance information obtained from the imaging sections 12101 to 12104 , extract the classified three- dimensional obj ect data, and use the extracted three-dimensional obj ect data for automatic avoidance of an obstacle . For example , the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually . Then, the microcomputer 12051 determines a collision ris k indicating a risk of collision with each obstacle . In a situation in which the collision ris k is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062 and performs forced deceleration or avoidance steering via the driving system control unit 12010 . The microcomputer 12051 can thereby assist in driving to avoid collision .At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays . The microcomputer 12051 can, for example , recognize a pedestrian by determining whether there is a pedestrian in imaged images of the imaging sections 12101 to 12104 . Such recognition of a pedestrian is , for example , performed by a procedureof extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the obj ect . When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104 , and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian . The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position .The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above . By applying an image sensor or a solid-state imaging device with an image sensor including pixel circuits according to the embodiments of the present disclosure , high temporal resolution can be combined with low contrast sensitivity non-uniformity .Additionally, embodiments of the present technology are not limited to the above-described embodiments , but various changes can be made within the scope of the present technology without departing from the gist of the present technology .The image sensor with pixel circuits according to the present disclosure may be any device used for analyzing and / or processing radiation such as visible light , infrared light , ultraviolet light , and X-rays . For example , a solid-state imaging device including an image sensor with pixel circuits according to the embodiments may be any electronic device in the field of traffic, the field of home appliances , the field of medical and healthcare , the field of security, the field of beauty, the field of sports , the field of agriculture , the field of image reproduction or the like .Specifically, in the field of image reproduction, the solid-state imaging device including an image sensor with pixel circuits according to the embodiments may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone , or a mobile phone device having a camera function . In the field of traffic, for example , the solid-state imaging device including an image sensor with pixel circuits according to the embodiments may be integrated in an in-vehiclesensor that captures the front , rear, peripheries , an interior of the vehicle , etc . for safe driving such as automatic stop, recognition of a state of a driver , or the like , in a monitoring camera that monitors traveling vehicles and roads , or in a distance measuring sensor that measures a distance between vehicles or the like .In the field of home appliances , the image sensor with pixel circuits according to the embodiments may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers , refrigerators , and air conditioners to capture gestures of users and perform device operations according to the gestures . Accordingly, the image sensor with pixel circuits according to the embodiments may be integrated in home appliances such as TV receivers , refrigerators , and air conditioners and / or in devices controlling the home appliances . Furthermore , in the field of medical and healthcare , the image sensor with pixel circuits according to the embodiments may be integrated in any type of sensor , e . g . , a solid-state image device , provided for use in medical and healthcare , such as an endoscope or a device that performs angiography by receiving infrared light .In the field of security, the image sensor with pixel circuits according to the embodiments can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use . Furthermore , in the field of beauty, an image sensor with pixel circuits according to the embodiments can be used in a device provided for use in beauty, such as a skin measuring instrument that captures s kin or a microscope that captures a probe . In the field of sports , an image sensor with pixel circuits according to the embodiments can be integrated in a device provided for use in sports , such as an action camera or a wearable camera for sport use or the like . Furthermore , in the field of agriculture , the image sensor with pixel circuits can be used in a device provided for use in agriculture , such as a camera for monitoring the condition of fields and crops .The present technology can also be configured as described below :

[0001] A pixel circuit , comprising : a capacitive element ( 121 ) configured to receive a pixel voltage VPR at a first electrode ; an event detection circuit ( 140 ) configured to output a comparator result signal VC , wherein the comparator result signal VC changes to an active level when a resettable floating voltageVF at a floating second electrode of the capacitive element (121) passes a predefined threshold voltage VT; and a multi-mode memory circuit (200) configured to output an event signal EV, wherein in a first mode the event signal EV follows the comparator result signal VC and in a second mode the event signal EV changes to an active level in response to receiving an active comparator result signal VC and changes to an inactive level in response to receiving an active memory reset signal ef .[2] The pixel circuit according to [1] , wherein the multi-mode memory circuit (200) is configured to be in the first mode when a memory mode signal MODL is inactive and in the second mode when the memory mode signal MODL is active.[3] The pixel circuit according to [1] or [2] , further comprising: a radiation sensitive circuit (110) configured to convert incident radiation into the pixel voltage VPR, wherein the pixel voltage VPR increases with increasing radiation intensity.[4] The pixel circuit according to any of [1] to [3] , wherein the event detection circuit (140) comprises a capacitive amplifier circuit (120) configured to receive the floating voltage VF at an amplifier input and output an amplified voltage signal VA at an amplifier output.[5] The pixel circuit according to [4] , wherein the event detection circuit (140) comprises a first comparator circuit (131) configured to output a first comparator result signal VC1, wherein the first comparator result signal VC2 is active when the amplified signal exceeds a first threshold voltage VT1, and wherein the multi-mode memory circuit (200) is configured to output an on-event signal EVI, wherein in the first mode the on-event signal EVI follows the first comparator result signal VC1 and in the second mode the on-event signal EVI changes to an active level in response to receiving an active first comparator result signal VC1 and changes to an inactive level in response to receiving the active memory reset signal RESL.[6] The pixel circuit according to [4] or [5] ,wherein the event detection circuit (140) comprises a second comparator circuit (132) configured to output a second comparator result signal VC2 , wherein the second comparator result signal VC2 is active when the amplified signal falls below a second threshold voltage VT2, and. wherein the multi-mode memory circuit (200) is configured to output an off-event signal EV2, wherein in the first mode the off- event signal EV2 follows the second comparator result signal VC2 and in the second mode the off-event signal E2 changes to an active level in response to receiving an active second comparator result signal VC2 and changes to an inactive level in response to receiving the active memory reset signal RESL.[7] The pixel circuit according to any of [1] to [6] , further comprising: an arbiter interface circuit (155) configured to output an active request signal REQ in response to receiving an active event signal EV from the multi-mode memory circuit (200) .[8] The pixel circuit according to any of [1] to [7] , further comprising: an event output circuit (151) configured to output an event data signal ON / OFF on an event data bus (41) in response to receiving an active acknowledgement signal ACK.[9] The pixel circuit according to any of [1] to [8] , further comprising: a reset output circuit (154) configured to output the active memory reset signal RESL in response to receiving an active acknowledgement signal ACK.

[0010] The pixel circuit according to any of [1] to [9] , further comprising : an autozero switch circuit (135) configured to reset the resettable floating voltage VF in response to receiving an active autozero switch signal AZSW in an autozero period.

[0011] The pixel circuit according to

[0010] , further comprising: an autozero control circuit (157) configured to output the active autozero switch signal AZSW in response to receiving an active acknowledgement signal ACK.

[0012] The pixel circuit according to any of [1] to

[0011] , wherein the multi-mode memory circuit (200) is configured to be insensitive to the comparator result signal VC when an inputenable signal ENL in inactive and sensitive to the active comparator result signal VC when the input enable signal ENL is active .

[0013] The pixel circuit according to

[0012] , further comprising: an enable control circuit (158) configured to output an active enable signal ENL in response to a change of an internal condition.

[0014] An image sensor comprising pixel circuits, wherein each pixel circuit (100) comprises: a capacitive element (121) configured to receive a pixel voltage VPR at a first electrode; an event detection circuit (140) configured to output a comparator result signal VC, wherein the comparator result signal VC changes to an active level when a resettable floating voltage VF at a floating second electrode of the capacitive element (121) passes a predefined threshold voltage VT; and a multi-mode memory circuit (200) configured to output an event signal EV, wherein in a first mode the event signal EV follows the comparator result signal VC and in a second mode the event signal EV changes to an active level in response to receiving an active comparator result signal VC and changes to an inactive level in response to receiving an active memory reset signal RESL.

Claims

CLAIMS1 . A pixel circuit , comprising : a capacitive element configured to receive a pixel voltage VPR at a first electrode ; an event detection circuit configured to output a comparator result signal VC , wherein the comparator result signal VC changes to an active level when a resettable floating voltage VF at a floating second electrode of the capacitive element passes a predefined threshold voltage VT ; and a multi-mode memory circuit configured to output an event signal EV, wherein in a first mode the event signal EV follows the comparator result signal VC and in a second mode the event signal EV changes to an active level in response to receiving an active comparator result signal VC and changes to an inactive level in response to receiving an active memory reset signal ef .2 . The pixel circuit according to claim 1 , wherein the multi-mode memory circuit is configured to be in the first mode when a memory mode signal MODL is inactive and in the second mode when the memory mode signal MODL is active .3 . The pixel circuit according to claim 1 , further comprising : a radiation sensitive circuit configured to convert incident radiation into the pixel voltage VPR, wherein the pixel voltage VPR increases with increasing radiation intensity .4 . The pixel circuit according to claim 1 , wherein the event detection circuit comprises a capacitive amplifier circuit configured to receive the floating voltage VF at an amplifier input and output an amplified voltage signal VA at an amplifier output .5 . The pixel circuit according to claim 4 , wherein the event detection circuit comprises a first comparator circuit configured to output a first comparator result signal VC1 , wherein the first comparator result signal VC2 is active when the amplified signal exceeds a first threshold voltage VT1 , and wherein the multi-mode memory circuit is configured to output an on-event signal EVI , wherein in the first mode the on-eventsignal EVI follows the first comparator result signal VC1 and in the second mode the on-event signal EVI changes to an active level in response to receiving an active first comparator result signal VC1 and changes to an inactive level in response to receiving the active memory reset signal RESL .6 . The pixel circuit according to claim 4 , wherein the event detection circuit comprises a second comparator circuit configured to output a second comparator result signal VC2 , wherein the second comparator result signal VC2 is active when the amplified signal falls below a second threshold voltage VT2 , and . wherein the multi-mode memory circuit is configured to output an off-event signal EV2 , wherein in the first mode the off-event signal EV2 follows the second comparator result signal VC2 and in the second mode the off-event signal E2 changes to an active level in response to receiving an active second comparator result signal VC2 and changes to an inactive level in response to receiving the active memory reset signal RESL .7 . The pixel circuit according to claim 1 , further comprising : an arbiter interface circuit configured to output an active request signal REQ in response to receiving an active event signal EV from the multi-mode memory circuit .8 . The pixel circuit according to claim 1 , further comprising : an event output circuit configured to output an event data signal ON / OFF on an event data bus in response to receiving an active acknowledgement signal ACK .9 . The pixel circuit according to claim 1 , further comprising : a reset output circuit configured to output the active memory reset signal RESL in response to receiving an active acknowledgement signal ACK .10 . The pixel circuit according to claim 1 , further comprising : an autozero switch circuit configured to reset the resettable floating voltage VF in response to receiving an active autozero switch signal AZSW in an autozero period .11 . The pixel circuit according to claim 10 , further comprising :an autozero control circuit configured to output the active autozero switch signal AZSW in response to receiving an active acknowledgement signal ACK .12 . The pixel circuit according to claim 1 , wherein the multi-mode memory circuit is configured to be insensitive to the comparator result signal VC when an input enable signal ENL in inactive and sensitive to the active comparator result signal VC when the input enable signal ENL is active .13 . The pixel circuit according to claim 12 , further comprising : an enable control circuit configured to output an active enable signal ENL in response to a change of an internal condition .14 . An image sensor comprising pixel circuits , wherein each pixel circuit comprises : a capacitive element configured to receive a pixel voltage VPR at a first electrode ; an event detection circuit configured to output a comparator result signal VC , wherein the comparator result signal VC changes to an active level when a resettable floating voltage VF at a floating second electrode of the capacitive element passes a predefined threshold voltage VT ; and a multi-mode memory circuit configured to output an event signal EV, wherein in a first mode the event signal EV follows the comparator result signal VC and in a second mode the event signal EV changes to an active level in response to receiving an active comparator result signal VC and changes to an inactive level in response to receiving an active memory reset signal RESL .

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