Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a highly reliable semiconductor device. In the semiconductor device, a transistor is provided on a base insulator, and includes an oxide semiconductor that has a fin shape in a cross-sectional view in the channel width direction. An insulator is provided under the oxide semiconductor. The upper end part of the insulator and the lower end part of the oxide semiconductor coincide or substantially coincide with each other. In a cross-sectional view in the channel width direction of the transistor, a first angle formed by the side surface of the insulator and the upper surface of the base insulator is less than 90°. Meanwhile, a second angle formed by the side surface of the oxide semiconductor and the upper surface of the insulator is larger than the first angle, and is 90° or around 90°. A gate insulator is disposed so as to cover the insulator and the oxide semiconductor, and a gate electrode is disposed on the gate insulator. In a cross-sectional view in the channel width direction of the transistor, the bottom surface of the gate electrode is located below the bottom surface of the oxide semiconductor.

Description

Semiconductor device and method for manufacturing the same

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic units, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs, CPUs, memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] An object of one embodiment of the present invention is to provide a low-cost semiconductor device. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high operation speed. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high yield. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a highly reliable storage device. Another object of one embodiment of the present invention is to provide a storage device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a storage device with a large storage capacity. Another object of one embodiment of the present invention is to provide a storage device with high operation speed. Another object of one embodiment of the present invention is to provide a storage device with low power consumption. Another object of one embodiment of the present invention is to provide a novel storage device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention includes a first insulator, a second insulator, and a transistor. The transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, and the third insulator. The first insulator is provided over a substrate, the oxide semiconductor is provided over the first insulator, the first conductor and the second conductor are provided over the oxide semiconductor, and the second insulator is provided over the first conductor and the second conductor. In a plan view, the second insulator has an opening that overlaps with a region between the first conductor and the second conductor in the oxide semiconductor. a third conductor is provided inside the opening so as to have a region in contact with the conductor, a third conductor is provided on the third insulator inside the opening, an upper end of the first insulator and a lower end of the oxide semiconductor are aligned or approximately aligned, an area of ​​a lower surface of the first insulator is larger than an area of ​​the upper surface of the first insulator and an area of ​​a lower surface of the oxide semiconductor, a bottom surface of the third conductor is provided below the lower surface of the oxide semiconductor in a cross-sectional view in the channel width direction of the transistor, and a height of the oxide semiconductor is larger than a width of the oxide semiconductor in a cross-sectional view in the channel width direction of the transistor.

[0013] Another embodiment of the present invention includes a base insulator, a first insulator, a second insulator, and a transistor. The transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, and the third insulator. The first insulator is provided over the base insulator. The oxide semiconductor is provided over the first insulator. The first conductor and the second conductor are provided over the oxide semiconductor. The second insulator is provided over the first conductor and the second conductor. In a plan view, the second insulator has an opening that overlaps with a region between the first conductor and the second conductor in the oxide semiconductor. the third conductor is provided inside the opening so as to have a region in contact with the oxide semiconductor, the third conductor is provided on the third insulator inside the opening, the upper end of the first insulator and the lower end of the oxide semiconductor are aligned or approximately aligned, a first angle formed by a side surface of the first insulator and an upper surface of the underlying insulator is less than 90° in a cross-sectional view in the channel width direction of the transistor, a bottom surface of the third conductor is located below a bottom surface of the oxide semiconductor in a cross-sectional view in the channel width direction of the transistor, and the height of the oxide semiconductor is longer than the width of the oxide semiconductor in a cross-sectional view in the channel width direction of the transistor.

[0014] Alternatively, in the above-described embodiment, a second angle formed by a side surface of the oxide semiconductor and a top surface of the first insulator may be larger than the first angle in a cross-sectional view of the transistor in the channel width direction.

[0015] Alternatively, in the above aspect, the second angle may be equal to or greater than 85° and equal to or less than 95°.

[0016] Alternatively, in the above embodiment, the width of the oxide semiconductor may be 2 nm to 20 nm in a cross-sectional view of the transistor in the channel width direction, and the height of the oxide semiconductor may be 1.5 to 10 times the width of the oxide semiconductor in the cross-sectional view of the transistor in the channel width direction.

[0017] Alternatively, in the above-described embodiment, the oxide semiconductor may contain indium, may be formed perpendicular or approximately perpendicular to the surface of the substrate, and when a cross section of the oxide semiconductor is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate may be observed.

[0018] Alternatively, in the above aspect, the oxide semiconductor may contain indium, may be formed perpendicular or approximately perpendicular to a surface of the substrate, and may have a first region, a second region in contact with the first region, and a third region in contact with the second region, and in cross-sectional observation of the oxide semiconductor using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate may be observed in each of the first region, the second region, and the third region.

[0019] Alternatively, in the above embodiment, the second region may contain zinc, and the second region may have crystals whose c-axes are approximately parallel to the normal to the side surfaces of the oxide semiconductor.

[0020] Alternatively, in the above aspect, the indium content in the first region may be higher than the indium content in the second region, and the indium content in the third region may be higher than the indium content in the second region.

[0021] Alternatively, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: forming a first insulator over a base insulator; processing the first insulator so that a top surface of the base insulator is not exposed; forming a convex portion on the first insulator; depositing an oxide semiconductor film to cover the first insulator; and processing the oxide semiconductor film by anisotropic etching until a top surface of the first insulator is exposed; forming an oxide semiconductor in contact with a side surface of the convex portion; and removing part of a region of the first insulator that does not overlap with the oxide semiconductor, thereby forming an oxide semiconductor film on the second insulator so that a first angle formed by a side surface of the second insulator and a top surface of the base insulator is less than 90°. a first conductor covering the oxide semiconductor and the second insulator; a third insulator over the first conductor; and processing the third insulator to form an opening in the third insulator that overlaps with the oxide semiconductor. The first conductor is processed to form a second conductor and a third conductor facing each other across the opening in a plan view. A fourth insulator is formed inside the opening to be in contact with the oxide semiconductor and the second insulator. The fourth conductor is formed on the fourth insulator to fill the opening.

[0022] Alternatively, in the above aspect, the convex portion may be formed on the first insulator so that a second angle formed by the upper surface of the first insulator in a region other than the convex portion and the side surface of the convex portion is 85° or more and 95° or less.

[0023] Alternatively, in the above embodiment, the part of the first insulator that does not overlap with the oxide semiconductor may be removed by etching using a gas containing carbon.

[0024] According to one embodiment of the present invention, a low-cost semiconductor device can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high operation speed can be provided. According to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high yield can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0025] According to one embodiment of the present invention, a highly reliable storage device can be provided. According to one embodiment of the present invention, a storage device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device with high operation speed can be provided. According to one embodiment of the present invention, a storage device with low power consumption can be provided. According to one embodiment of the present invention, a novel storage device can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0027] FIGS. 1A to 1C are perspective views illustrating an example of a semiconductor device. FIGS. 2A and 2B are plan views illustrating an example of a semiconductor device. FIGS. 2C to 2E are cross-sectional views illustrating an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 4A to 4C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 5A and 5B are plan views illustrating an example of a part of a semiconductor device. FIGS. 6A to 6D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. FIGS. 7A to 7D are cross-sectional views illustrating an example of an oxide semiconductor. FIGS. 8A and 8B are cross-sectional views illustrating an example of a semiconductor device. FIG. 9 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 10A is a plan view illustrating an example of a semiconductor device. FIGS. 10B to 10D are cross-sectional views illustrating an example of a semiconductor device. FIG. 11A is a plan view illustrating an example of a semiconductor device. FIGS. 11B and 11C are cross-sectional views illustrating an example of a semiconductor device. FIG. 12A is a plan view illustrating an example of a semiconductor device. FIG. 12B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 13A is a plan view illustrating an example of a semiconductor device. FIG. 13B is a cross-sectional view showing an example of a semiconductor device. FIG. 14A is a plan view showing an example of a semiconductor device. FIGS. 14B to 14D are cross-sectional views showing an example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing an example of a semiconductor device. FIG. 16 is a cross-sectional view showing an example of a semiconductor device. FIGS. 17A to 17D are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a semiconductor device. FIG. 18B is a cross-sectional view showing an example of a semiconductor device. FIGS. 19A and 19B are cross-sectional views showing an example of a semiconductor device. FIG. 20 is a plan view showing an example of a semiconductor device. FIGS. 21A and 21B are cross-sectional views showing an example of a semiconductor device. FIG. 22A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 22B to 22E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 23A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 23B to 23E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 24A is a plan view showing an example of a method for manufacturing a semiconductor device. 24B to 24E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.25A and 25B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 26A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 26B to 26E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 27B to 27E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 28B to 28E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 29A and 29B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 30A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 30B to 30E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 31A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 31B to 31E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 32A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 32B to 32E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 33A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 33B to 33E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 34A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 34B to 34E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 35A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 35B to 35E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 36A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 36B to 36E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 37A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 37B to 37E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 38A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 38B to 38E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 39A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 39B to 39E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 40A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS. 40B to 40E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.FIG. 41 is a block diagram illustrating an example of the configuration of a semiconductor device. FIGS. 42A to 42H are diagrams illustrating an example of the circuit configuration of a memory cell. FIGS. 43A and 43B are perspective views illustrating an example of the configuration of a semiconductor device. FIG. 44 is a block diagram illustrating a CPU. FIG. 45 is a block diagram illustrating a CPU. FIGS. 46A and 46B are perspective views of a semiconductor device. FIGS. 47A and 47B are perspective views of a semiconductor device. FIGS. 48A and 48B are diagrams illustrating the hierarchy of a memory device in a semiconductor device. FIGS. 49A and 49B are diagrams showing an example of electronic equipment, and FIGS. 49C to 49E are diagrams showing an example of a mainframe computer. FIG. 50 is a diagram showing an example of space equipment. FIG. 51 is a diagram showing an example of a storage system applicable to a data center. FIGS. 52A and 52B are circuit diagrams of a semiconductor device. FIG. 52C is a diagram showing an example of an electronic component using a semiconductor device.

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0030] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0031] In order to make the invention easier to understand, particularly in plan views (which may also be called top views) or perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0032] In this specification, the ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0033] It should be noted that the terms "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be interchanged with the term "conductive film". Or, for example, the term "insulating film" can be interchanged with the term "insulating layer". Furthermore, the term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" can be interchanged with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0034] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0035] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is perpendicular or approximately perpendicular to the substrate surface or the surface where the insulator is formed, the sidewall may have a tapered shape.

[0036] In this specification, "A is perpendicular to the substrate surface or the surface to be formed" means that the angle between the side of A and the upper surface of the substrate surface or the surface to be formed is 80 degrees or more and 100 degrees or less. "A is approximately perpendicular to the substrate surface or the surface to be formed" means that the angle between the side of A and the upper surface of the substrate surface or the surface to be formed is 70 degrees or more and 110 degrees or less. "Substrate surface" can be rephrased as "surface of the substrate."

[0037] In this specification and the like, the opening also includes, for example, a groove, a slit, and the like.

[0038] In this specification, the term "tapered shape" refers to a shape in which at least a portion of the side surface of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0039] In this specification and the like, "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are the same in a cross-sectional view. For example, in a manufacturing process of a memory device, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces to be processed by the CMP process have a configuration in which the heights from the reference surface are the same. However, the heights of multiple layers may differ depending on the processing device, processing method, or material of the processed surface during the CMP process. In this specification and the like, this case is also treated as "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less is also referred to as "having the same or approximately the same height."

[0040] In this specification, the phrase "side edges that coincide or approximately coincide" refers to a state in which at least a portion of the contours of stacked layers overlap when viewed from above (which may also be referred to as a top view). For example, this includes cases in which the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the phrase "side edges that coincide or approximately coincide" also applies.

[0041] In this specification and the like, when B is provided on A, the phrase "the upper end of A and the lower end of B coincide or approximately coincide" means that the edge of the upper surface of A and the edge of the lower surface of B overlap at least partially. For example, this includes cases where B and A are processed using the same mask pattern or a mask pattern that is partially identical. However, the upper end of A and the lower end of B may not strictly overlap, and the upper end of A may be provided inside the lower end of B, or the upper end of A may be provided outside the lower end of B. In these cases, the phrase "side ends coincide or approximately coincide" is also used.

[0042] In this specification, the phrase "shapes that match or approximately match in plan view" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be disposed inside the lower layer, or the upper layer may be disposed outside the lower layer. In these cases, the phrase "shapes that match or approximately match in plan view" may also be used. Furthermore, when the shapes match or approximately match in plan view, it can also be said that the edges are aligned or approximately aligned, or that the side edges are aligned or approximately aligned.

[0043] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0044] In this specification, "connection" includes "electrical connection."

[0045] "A and B are electrically connected" means that, among the cases where A and B are connected without an insulator (where A and B are connected via a conductor or semiconductor, or where A and B are in contact), there is a time when exchange of electrical signals or interaction of potentials occurs between A and B during circuit operation. In other words, even if there is a time when exchange of electrical signals or interaction of potentials does not occur between A and B during circuit operation, it can be said that "A and B are electrically connected" as long as there is a time when exchange of electrical signals or interaction of potentials occurs between A and B.

[0046] An "electrical connection" includes a connection (direct connection) that does not involve a circuit element (for example, a transistor, but excluding wiring), and a connection (indirect connection) that involves one or more circuit elements.

[0047] Examples of "A and B being electrically connected" include when A and B are connected without a circuit element, or when A and B are connected via the source and drain of one or more transistors. However, this is premised on the fact that there is a timing when an electrical signal is exchanged or an interaction of potential occurs between A and B.

[0048] An example in which it cannot be said that "A and B are electrically connected" because A and B are connected via an insulator is when a dielectric of a capacitive element, a gate insulating film of a transistor, etc. is interposed between A and B.

[0049] Examples of cases where A and B are connected without an insulator between them, but there is no timing at which an electrical signal is exchanged or there is no potential interaction between A and B, and therefore it cannot be said that "A and B are electrically connected" include a case where a potential V is supplied to the path from A to B from a power supply, signal source, etc. (however, this does not include a case where the potential V is supplied via a circuit element), or a case where A and C are connected via the source and drain of a transistor TrP and B and C are connected via the source and drain of a transistor TrQ, but there is no timing at which both the transistor TrP and the transistor TrQ are turned on simultaneously.

[0050] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor and a manufacturing method of the semiconductor device will be described with reference to drawings.

[0051] One embodiment of the present invention is a semiconductor device including a transistor over a base insulator. The transistor includes an oxide semiconductor that has a fin-like shape in a cross section in a channel width direction. In the semiconductor device of one embodiment of the present invention, a gate insulator is provided to cover the fin-like oxide semiconductor, and a gate electrode is provided over the gate insulator. As a result, in a cross section in the channel width direction of the transistor, the oxide semiconductor and the gate electrode are provided on both the top surface and the side surface of the oxide semiconductor, facing each other with the gate insulator interposed therebetween. Therefore, by forming the oxide semiconductor into a fin shape, the area where the oxide semiconductor and the gate electrode overlap with the gate insulator interposed therebetween can be increased compared to when the oxide semiconductor has a flat shape. Therefore, the channel width of the transistor can be increased.

[0052] In a semiconductor device according to one embodiment of the present invention, an insulator whose top edge coincides with or substantially coincides with a bottom edge of the oxide semiconductor is provided under the oxide semiconductor. The thickness of the insulator under the oxide semiconductor is made thicker than the thickness of the gate insulator. This allows the bottom surface of the gate electrode to be located below the bottom surface of the oxide semiconductor in a cross-sectional view of the transistor in the channel width direction.

[0053] By providing the bottom surface of the gate electrode below the bottom surface of the oxide semiconductor, a gate electric field can be applied sufficiently from the top to the bottom of the oxide semiconductor. In other words, in a cross-sectional view of the transistor in the channel width direction, the entire oxide semiconductor is electrically surrounded by the electric field of the gate electrode, and can function as a channel formation region. This improves the electrical characteristics of the transistor. Furthermore, the channel width of the transistor can be increased.

[0054] In a semiconductor device according to one embodiment of the present invention, the area of ​​the bottom surface of the insulator is larger than the area of ​​the top surface of the insulator and the area of ​​the bottom surface of the oxide semiconductor. Specifically, in a cross-sectional view of the transistor in the channel width direction, the first angle formed by the side surface of the insulator and the top surface of the base insulator is set to be less than 90°, that is, the side surface of the insulator is tapered, thereby making the area of ​​the bottom surface of the insulator larger than the area of ​​the top surface of the insulator. This can prevent the insulator from collapsing. Therefore, the oxide semiconductor on the insulator can also be prevented from collapsing.

[0055] On the other hand, the second angle formed by the side surface of the oxide semiconductor and the top surface of the insulator is larger than the first angle and is set to 90° or close to that. By making the area of ​​the bottom surface of the oxide semiconductor smaller than that of the insulator, for example, by making the bottom edge of the oxide semiconductor coincident or approximately coincident with the top edge of the insulator and setting the second angle to 90° or close to that, it is possible to prevent the oxide semiconductor from being deformed. For example, in a cross-sectional view of the transistor in the channel width direction, it is possible to prevent the oxide semiconductor from bending near the insulator. Thus, by tapering the side surface of the insulator and setting the angle formed by the side surface of the oxide semiconductor and the top surface of the insulator to 90° or close to that, semiconductor devices can be manufactured with a high yield. Therefore, a low-cost semiconductor device can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0056] 1A to 4C are diagrams illustrating a structural example of a semiconductor device including a transistor 200 over a substrate (not shown).

[0057] Fig. 1A is a perspective view showing a configuration example of a transistor 200. Fig. 1B is a perspective view in which some elements are omitted from Fig. 1A. Fig. 1C is a perspective view in which some elements are further omitted from Fig. 1B.

[0058] FIG. 2A is a plan view showing a configuration example of a semiconductor device including the transistor 200 shown in FIG. 1A. FIG. 2B is an enlarged plan view of some elements extracted from FIG. 2A. FIGS. 2C to 3B are cross-sectional views of the semiconductor device including the transistor 200. Here, FIGS. 2C, 2D, and 2E are cross-sectional views of the portions indicated by dashed dotted lines A1-A2, A3-A4, and A5-A6 in FIG. 2A, respectively, and are also cross-sectional views of the transistor 200 in the channel width direction. Also, FIGS. 3A and 3B are cross-sectional views of the portions indicated by dashed dotted lines B1-B2 and B3-B4 in FIG. 2A, respectively, and are also cross-sectional views of the transistor 200 in the channel length direction. Here, the dashed dotted line B1-B2 is perpendicular to the dashed dotted line A1-A2, the dashed dotted line A3-A4, and the dashed dotted line A5-A6. Similarly, the dashed-dotted line B3-B4 is perpendicular to the dashed-dotted line A1-A2, the dashed-dotted line A3-A4, and the dashed-dotted line A5-A6. The dashed-dotted line A1-A2, the dashed-dotted line A3-A4, and the dashed-dotted line A5-A6 are parallel to one another. The dashed-dotted line B1-B2 and the dashed-dotted line B3-B4 are parallel to one another. Note that in the perspective views of FIGS. 1A to 1C and the plan view of FIG. 2A, some elements are omitted for clarity. Also, in the plan view of FIG. 2A, some elements are shown transparently. In the subsequent perspective views and plan views, some elements may also be omitted. Also, in the subsequent plan views, some elements may also be shown transparently.

[0059] Fig. 4A shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 2C. Fig. 4B shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 2D. Fig. 4C shows an enlarged view of the vicinity of the conductor 260 in Fig. 3A.

[0060] The semiconductor device of this embodiment has an insulator 215 on a substrate (not shown), an insulator 216 on the insulator 215, an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, a conductor 242a1 and a conductor 242b1 on the oxide semiconductor 230 and the insulator 222, a conductor 242a2 on the conductor 242a1, a conductor 242b2 on the conductor 242b1, an insulator 255 on the conductor 242a1, the conductor 242b1, and the insulator 222, an insulator 250 on the oxide semiconductor 230, the insulator 255, and the insulator 222, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. 2A, the oxide semiconductor 230 and the insulator 255 are indicated by hatching. In the subsequent plan views, the oxide semiconductor 230 and the insulator 255 may also be indicated by hatching.

[0061] In the following, conductors 242a1 and 242a2 may be collectively referred to as conductors 242a, and conductors 242b1 and 242b2 may be collectively referred to as conductors 242a. Also, conductors 242a and 242b may be collectively referred to as conductors 242. Conductor 242a can be said to have a two-layer laminated structure consisting of conductor 242a1 and conductor 242a2 on conductor 242a1. Conductor 242b can be said to have a two-layer laminated structure consisting of conductor 242b1 and conductor 242b2 on conductor 242b1. Conductor 242a2 can be in contact with the top surface of conductor 242a1. Conductor 242b2 can be in contact with the top surface of conductor 242b1.

[0062] 1A shows the insulator 224, the oxide semiconductor 230, the conductor 242a1, the conductor 242a2, the conductor 242b1, the conductor 242b2, and the conductor 260, which are elements included in the semiconductor device according to this embodiment. In FIG. 1B, the conductor 260 is omitted from FIG. 1A. In FIG. 1C, the conductors 242a1, 242a2, conductor 242b1, and conductor 242b2 are further omitted from FIG. 1B. In FIG. 1C, the insulator 224 and the oxide semiconductor 230 are shown. In addition, in FIG. 2B, one insulator 224 and one oxide semiconductor 230 are extracted from FIG. 2A and shown enlarged.

[0063] The insulators 215, 216, 221, and 222 function as base films. The transistor 200 including the oxide semiconductor 230, the conductors 242a, 242b, 260, and the insulator 250 is provided over the insulator 222. Note that the transistor 200 may include the insulator 224. The transistor 200 may also include the insulator 255.

[0064] An insulator 275 is provided over the conductor 242a2, the conductor 242b2, and the insulator 222, and an insulator 280 is provided over the insulator 275. The insulator 280 functions as an interlayer film. Note that the insulator 275 may also be included in the interlayer film.

[0065] In this specification and the like, an insulator that functions as a base film is called a base insulator, and an insulator that functions as an interlayer film is called an interlayer insulator.

[0066] 2C , 3A, and 3B , the insulator 275 and the insulator 280 have openings 201 that overlap with a region between the conductor 242a2 and the conductor 242b2 in a plan view of the oxide semiconductor 230. The conductors 242a1 and 242b1 are in contact with the oxide semiconductor 230. In a plan view, the conductors 242a and 242b are provided to face each other with the opening 201 interposed therebetween.

[0067] 3A and 3B, the opening 201 overlaps with the region between the conductor 242a2 and the conductor 242b2. The conductor 242a1 has a region that protrudes toward the opening 201 more than the conductor 242a2. The conductor 242b1 has a region that protrudes toward the opening 201 more than the conductor 242b2. In a plan view, the side end of the conductor 242a2 on the opening 201 side and the side end of the conductor 242b2 on the opening 201 side can be aligned or approximately aligned with the side wall of the opening 201. As described above, the protruding region of the conductor 242a1 and the protruding region of the conductor 242b1 can be regions that overlap with the opening 201.

[0068] 3A and 3B , insulator 255 is provided inside opening 201 so as to have a region in contact with the top surface of conductor 242a1, a region in contact with the top surface of conductor 242b1, a region in contact with the side surface of conductor 242a2, a region in contact with the side surface of conductor 242b2, and a region in contact with the side surface of insulator 280 on the opening 201 side. A portion of the side edge of insulator 255 can be aligned or approximately aligned with the side edge of conductor 242a1 on the opening 201 side. In addition, another portion of the side edge of insulator 255 can be aligned or approximately aligned with the side edge of conductor 242b1 on the opening 201 side.

[0069] The insulator 255 is preferably an insulator having a barrier property against oxygen (also referred to as an oxygen barrier insulator). The insulator 255 is preferably at least less permeable to oxygen than the insulator 280.

[0070] As described above, the insulator 255 is provided in contact with the side surfaces of the conductor 242a2 and the conductor 242b2. As a result, the insulator 255 has a function of protecting the conductor 242a2 and the conductor 242b2. As will be described in detail later, after separating the conductor 242a1 and the conductor 242b1, it is preferable to perform heat treatment in an oxygen-containing atmosphere before forming the insulator 250. At this time, since the insulator 255 is provided in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, oxidation of the side surfaces of the conductor 242a2 and the conductor 242b2 can be suppressed. This can suppress a decrease in the on-state current or the field-effect mobility of the transistor 200. Therefore, a semiconductor device with excellent electrical characteristics can be provided.

[0071] Examples of oxygen barrier insulators include nitrides, specifically silicon nitride, silicon nitride oxide, and aluminum nitride. Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, and gallium oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, hafnium aluminate, and hafnium silicate.

[0072] In this specification and the like, a barrier insulator refers to an insulator with barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. Furthermore, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0073] The insulator 255 may have a stacked structure of two or more layers using, for example, the above-mentioned materials. In this case, it is preferable that at least one layer be the above-mentioned oxygen barrier insulator. For example, it is preferable that the layer in contact with the conductor 242a2 and the conductor 242b2 be the oxygen barrier insulator. The insulator 255 can have, for example, a two-layer structure of a silicon nitride film and a silicon oxide film on the silicon nitride film.

[0074] The insulator 250 is provided inside the opening 201 so as to have a region in contact with the oxide semiconductor 230, a region in contact with the side surface of the conductor 242a1, and a region in contact with the side surface of the conductor 242b1. The insulator 250 is provided inside the insulator 255 so as to have a region provided on the insulator 255 inside the opening 201. The insulator 250 can have a region in contact with the side surface of the insulator 255, a region in contact with the top surface of the insulator 255 in the opening 201, a region in contact with the top surface of the insulator 222, and a region in contact with the side surface of the insulator 224.

[0075] The conductor 260 is provided on the insulator 250 inside the opening 201. Specifically, the conductor 260 is provided on the insulator 250 so as to fill the opening 201. Furthermore, an insulator 282 is provided on the insulator 280 and the conductor 260. Furthermore, an insulator 283 is provided on the insulator 282.

[0076] The oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200.

[0077] The conductor 242a has a region which functions as one of the source electrode and the drain electrode of the transistor 200. The conductor 242b has a region which functions as the other of the source electrode and the drain electrode of the transistor 200.

[0078] As shown in FIGS. 2A and 2B , the insulator 224 and the oxide semiconductor 230 have a circumferential shape (which may also be referred to as a top view shape) in a plan view (which may also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape). The oxide semiconductor 230 is provided in contact with the top surface of the insulator 224. FIGS. 2A and 2B show an example in which the insulator 224 and the oxide semiconductor 230 have a hollow rectangle, specifically, a hollow rectangle with rounded corners, in a plan view. The insulator 224 and the oxide semiconductor 230 can also be said to have a shape having an opening in the center. As shown in FIG. 2B , the oxide semiconductor 230 includes a region 233 that is parallel to the channel width direction and a region 234 that is parallel to the channel length direction. FIG. 2E shows an example cross-sectional structure of the region 233 of the oxide semiconductor 230. FIG. 3A shows an example cross-sectional structure of the region 234 of the oxide semiconductor 230. Note that the transistor 200 does not necessarily require the region 233 to be provided in the oxide semiconductor 230. In this case, the oxide semiconductor 230 may have a rectangular shape extending in the channel length direction in a plan view.

[0079] In a plan view, the oxide semiconductor 230 overlaps with the insulator 224. The bottom surface of the insulator 224 is in contact with the insulator 222, the side surfaces of the insulator 224 are in contact with the insulator 250, the conductor 242a, and the conductor 242b, and the top surface of the insulator 224 is in contact with the bottom surface of the oxide semiconductor 230. Note that the insulators 221 and 222 do not necessarily have to be provided. In this case, the bottom surface of the insulator 224 is in contact with the insulator 216.

[0080] 4A and 4B , in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230 has a shape with a high aspect ratio. Therefore, the oxide semiconductor 230 can be said to have a fin-like shape. In addition, a stack including the insulator 224 and the oxide semiconductor 230 over the insulator 224 can also be said to have a fin-like shape.

[0081] Here, the aspect ratio of the oxide semiconductor 230 in a cross-sectional view of the transistor 200 in the channel width direction refers to the ratio of the length L3 of the oxide semiconductor 230 in the A1-A2 direction (which can also be referred to as the width L3 of the oxide semiconductor 230) to the length H of the oxide semiconductor 230 in a direction perpendicular to the surface on which the oxide semiconductor 230 is formed (for example, the insulator 222) (which can also be referred to as the height H of the oxide semiconductor 230). Here, when the height H is equal to or greater than the width L3, the oxide semiconductor 230 is said to have a fin-like shape. When the height H is less than the width L3, the oxide semiconductor 230 may be said to have a plate-like shape. Note that the width L3 can be the width of the bottom surface of the oxide semiconductor 230.

[0082] The aspect ratio of the oxide semiconductor 230 is preferably as large as possible within a range in which the oxide semiconductor 230 does not collapse during the manufacturing process of the transistor 200. The height H of the oxide semiconductor 230 is 1 to 100 times, preferably 1 to 50 times, more preferably 1 to 30 times, and even more preferably 1.5 to 10 times the width L3 of the oxide semiconductor 230. For example, the width L3 is 1 to 100 nm, preferably 1 to 50 nm, and more preferably 2 to 20 nm. For example, the height H is 1 to 2000 nm, preferably 2 to 1000 nm, more preferably 5 to 500 nm, and even more preferably 10 to 300 nm. By setting the aspect ratio of the oxide semiconductor 230 within the above range, the insulator 250, the conductor 260, the conductor 242, and the like can be provided to cover the oxide semiconductor 230 with good coverage.

[0083] The insulator 250, the conductor 260, and the conductor 242 are provided to cover the oxide semiconductor 230 having such a high aspect ratio. In the transistor 200, as shown in FIG. 4A , parts of the insulator 250 and the conductor 260 are provided so as to sandwich the oxide semiconductor 230 in two. As a result, in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided to face each other with the insulator 250 sandwiched between them on the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. That is, in addition to the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 each function as a channel formation region. Therefore, the channel width of the transistor 200 is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 than when the oxide semiconductor 230 is flat.

[0084] The increase in the channel width as described above can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by providing the oxide semiconductor 230, the channel width can be increased without increasing the area occupied by the transistor 200. This enables miniaturization or high integration of the semiconductor device. Furthermore, the memory capacity of a memory device using the semiconductor device can be increased. Furthermore, the above structure increases the area where the conductor 260 and the oxide semiconductor 230 face each other, so that the transistor 200 can be made normally off by controlling the threshold voltage.

[0085] 4A and 4B, the top surface of the oxide semiconductor 230 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulator 250 and the conductor 242 near the top surface of the oxide semiconductor 230. While FIGS. 4A and 4B illustrate a symmetrical structure in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the top surface of the oxide semiconductor 230, the present invention is not limited to this. For example, an asymmetrical structure in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the top surface of the oxide semiconductor 230 may also be used.

[0086] Because the oxide semiconductor 230 has a high aspect ratio, it is preferably formed in a sidewall shape on the side surface of the pillar (the protrusion 206 of the insulator 223 described later). Therefore, the oxide semiconductor 230 is preferably formed by atomic layer deposition (ALD), which has good coverage. When the oxide semiconductor 230 has a stacked structure, it is preferable to form at least one layer, preferably a layer in contact with the pillar, by the ALD method.

[0087] 2A , by forming the oxide semiconductor 230 in a sidewall shape in contact with the side surfaces of the pillars, the oxide semiconductors 230 can be formed simultaneously. By forming the oxide semiconductors 230 in this manner, the distance between adjacent oxide semiconductors 230 can be set according to the size and shape of the pillars. Therefore, the distance between the oxide semiconductors 230 can be reduced, the area occupied by the transistor 200 can be reduced, and the semiconductor device can be highly integrated.

[0088] Since the oxide semiconductor 230 is formed in a sidewall shape in contact with the pillar, the shape of the oxide semiconductor 230 in plan view is a circumferential shape as described above, as shown in Fig. 2A . Note that in Fig. 2A and Fig. 2B , the shape of the oxide semiconductor 230 in plan view is line-symmetrical about A1-A2, but the present invention is not limited to this. For example, the shape of the oxide semiconductor 230 in plan view may be asymmetrical.

[0089] In the structure illustrated in FIG. 2A , two pillars are arranged in the A1-A2 direction, and a circumferential oxide semiconductor 230 is formed in contact with the side surface of each pillar. As illustrated in FIG. 2A , the oxide semiconductor 230 preferably overlaps with the conductor 260 at two or more locations in a plan view. That is, the semiconductor device of one embodiment of the present invention has two or more regions where the oxide semiconductor 230 and the conductor 260 overlap. With this structure, as illustrated in FIG. 2C , a plurality of fin-shaped oxide semiconductors 230 are provided in a cross-sectional view of the transistor 200 in the channel width direction. Each of the plurality of fin-shaped oxide semiconductors 230 functions as a channel formation region. That is, the transistor 200 functions as a multi-channel transistor. Therefore, the channel width of the transistor 200 can be further increased.

[0090] 4A , the thickness t2 of the insulator 250 inside the opening 201 is preferably thinner than the thickness t1 of the insulator 224. In other words, the thickness t1 is preferably thicker than the thickness t2. With this structure, in a cross-sectional view of the transistor 200 in the channel width direction, the bottom surface of the conductor 260 (conductor 260 a) provided inside the opening 201 can be located lower than the bottom surface of the oxide semiconductor 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0091] By providing the bottom surface of the conductor 260 below the bottom surface of the oxide semiconductor 230, a gate electric field can be applied sufficiently from the top end to the bottom end of the oxide semiconductor 230. In other words, in a cross-sectional view of the transistor 200 in the channel width direction, the entire oxide semiconductor 230 is electrically surrounded by the electric field of the conductor 260, allowing it to function as a channel formation region. This structure prevents the bottom end of the oxide semiconductor 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, poor characteristics of the transistor, such as normally-on, due to the parasitic channel can be suppressed. That is, the electrical characteristics of the transistor 200 can be improved.

[0092] Furthermore, as described above, the oxide semiconductor 230 functions as a channel formation region from the top end to the bottom end, whereby the channel width can be increased, thereby improving the on-state current, transconductance, frequency characteristics, and the like of the transistor 200.

[0093] When the bottom surface of the conductor 260 is located below the bottom surface of the oxide semiconductor 230, at least a part of the insulator 224 can function as a gate insulator of the transistor 200. For example, a region of the insulator 224 between the bottom surface of the conductor 260 (the conductor 260a) and the oxide semiconductor 230 in a cross-sectional view can function as the gate insulator of the transistor 200.

[0094] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is provided so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0095] Note that the S-channel structure electrically surrounds the channel formation region, and therefore, can be said to be substantially equivalent to a gate all around (GAA) structure or a lateral gate all around (LGAA) structure. When the transistor 200 has the S-channel structure, the GAA structure, or the LGAA structure, a channel formation region formed at or near the interface between the oxide semiconductor 230 and a gate insulator can be the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, which is expected to result in an increase in the on-state current or the field-effect mobility of the transistor. In one embodiment of the present invention, the oxide semiconductor 230 has a CAAC structure and a fin-shaped structure. The CAAC structure is formed so that the a-b plane is parallel or approximately parallel to the channel length direction. With this structure, a current path flowing from one of the source and drain of the transistor to the other can be parallel to the a-b plane of the CAAC structure. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path equivalent to that of a two-dimensional semiconductor material. By using such an oxide semiconductor for a semiconductor layer of a transistor, a device having two-dimensional conduction can be manufactured.

[0096] The thickness t1 of the insulator 224 can be equal to or less than the height H of the oxide semiconductor 230. The thickness t1 can be equal to or greater than 1 nm and equal to or less than 1,000 nm, preferably equal to or greater than 5 nm and equal to or less than 500 nm, more preferably equal to or greater than 5 nm and equal to or less than 100 nm, more preferably equal to or greater than 10 nm and equal to or less than 70 nm, more preferably equal to or greater than 10 nm and equal to or less than 50 nm, and still more preferably equal to or greater than 10 nm and equal to or less than 30 nm. By setting the thickness t1 in the above range, the bottom surface of the conductor 260 can be positioned lower than the bottom surface of the oxide semiconductor 230, and the insulator 250, for example, can be provided to cover the insulator 224 with good coverage.

[0097] In the semiconductor device of one embodiment of the present invention, as shown in FIG. 4A , in a cross-sectional view of the transistor 200 in the channel width direction, the angle θ1 formed by the side surface of the insulator 224 and the top surface of the base insulator (the insulator 222 in the example shown in FIG. 4A ) is less than 90°. That is, the side surface of the insulator 224 has a tapered shape. As a result, the length L4 of the bottom surface of the insulator 224 in the A1-A2 direction (which can also be referred to as the width L4 of the insulator 224) can be made longer than the length of the top surface of the insulator 224 in the A1-A2 direction. Therefore, the area of ​​the bottom surface of the insulator 224 can be made larger than the area of ​​the top surface of the insulator 224. As a result, the insulator 224 can be prevented from tipping over. Therefore, the oxide semiconductor 230 over the insulator 224 can also be prevented from tipping over.

[0098] The smaller the angle θ1, the larger the area of ​​the lower surface of the insulator 224 can be relative to the area of ​​the upper surface of the insulator 224. In other words, the value obtained by dividing the area of ​​the lower surface of the insulator 224 by the area of ​​the upper surface of the insulator 224 can be increased. This makes it possible to preferably prevent the insulator 224 from tipping over. On the other hand, the closer the angle θ1 is to 90°, the easier it is to fabricate the insulator 224. Specifically, this makes it easier to process the film that becomes the insulator 224. The angle θ1 can be set to be 45° or more and less than 90°, preferably 60° or more and less than 90°, and more preferably 60° or more and 80° or less.

[0099] On the other hand, in a cross-sectional view of the transistor 200 in the channel width direction, the angle θ2 formed by the side surface of the oxide semiconductor 230 and the top surface of the insulator 224 is larger than the angle θ1. The angle θ2 is preferably 90° or close to 90°. The angle θ2 is, for example, preferably 80° to 100°, more preferably 85° to 95°.

[0100] As described above, the oxide semiconductor 230 overlaps the insulator 224 in a planar view. For example, the lower end of the oxide semiconductor 230 and the upper end of the insulator 224 can be aligned or approximately aligned. When the lower end of the oxide semiconductor 230 and the upper end of the insulator 224 are aligned, the length of the upper surface of the insulator 224 in the A1-A2 direction is equal to the width L3. In this case, the area of ​​the lower surface of the oxide semiconductor 230 is equal to the area of ​​the upper surface of the insulator 224. As described above, the area of ​​the lower surface of the insulator 224 can be made larger than the area of ​​the upper surface of the insulator 224. As described above, the area of ​​the lower surface of the insulator 224 can be made larger than the area of ​​the upper surface of the insulator 224 and the area of ​​the lower surface of the oxide semiconductor 230. In this case, as shown in FIGS. 2A and 2B , the area of ​​the insulator 224 in a planar view can be made larger than the area of ​​the oxide semiconductor 230 in a planar view. Note that, for example, the larger of the upper surface A and the lower surface A can be used as the area of ​​A in a planar view.

[0101] By making the area of ​​the bottom surface of the oxide semiconductor 230 smaller than the area of ​​the bottom surface of the insulator 224 and making the angle θ2 larger than the angle θ1, for example, making the angle θ2 90° or close to that, it is possible to prevent the oxide semiconductor 230 from being deformed. For example, in a cross-sectional view of the transistor 200 in the channel width direction, it is possible to prevent the oxide semiconductor 230 from bending near the insulator 224. As described above, by tapering the side surface of the insulator 224 and making the angle θ2 larger than the angle θ1, for example, making the angle θ2 90° or close to that, semiconductor devices can be manufactured with a high yield. Therefore, a low-cost semiconductor device can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0102] The insulator 224 may be, for example, silicon nitride, silicon nitride oxide, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, aluminum oxide, or a resin. Here, silicon nitride and silicon nitride oxide have high barrier properties against hydrogen, and therefore, when used for the insulator 224, for example, hydrogen can be prevented from diffusing from a base insulator to the oxide semiconductor 230. As a result, defects (V) in which hydrogen has entered oxygen vacancies in the channel formation region can be formed. Ｏ H) can be reduced. Therefore, it is possible to provide a semiconductor device having good electrical characteristics, which is preferable.

[0103] The insulators 275, 280, 282, and 283 each have an opening 202a that reaches the conductor 242a and an opening 202b that reaches the conductor 242b. The insulator 241a is provided in contact with the sidewall of the opening 202a, and the conductor 240a is provided in contact with the side surface of the insulator 241a. The bottom surface of the conductor 240a is in contact with the top surface of the conductor 242a. The insulator 241b is provided in contact with the sidewall of the opening 202b, and the conductor 240b is provided in contact with the side surface of the insulator 241b. The bottom surface of the conductor 240b is in contact with the top surface of the conductor 242b. 2A , 2E , and 3B show an example in which the conductors 240a and 240b cover the entire region 233 of the oxide semiconductor 230 shown in FIG. 2B . Note that hereinafter, the conductor 240a and the conductor 240b may be collectively referred to as the conductor 240. Furthermore, the insulator 241a and the insulator 241b may be collectively referred to as the insulator 241. Furthermore, the opening 202a and the opening 202b may be collectively referred to as the opening 202. The conductor 240 may or may not be included in the transistor 200. Furthermore, the insulator 241 may or may not be included in the transistor 200.

[0104] The conductor 240a functions as a plug that connects to the conductor 242a. The conductor 240b functions as a plug that connects to the conductor 242b. Note that in FIG. 2A , the shape of the conductor 240 is rectangular in plan view, but this is not limited to this. For example, the conductor 240 may be circular, approximately circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in plan view.

[0105] As shown in FIG. 4C , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L1 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L2 between the conductor 242a2 and the conductor 242b2. Here, the distance L1 refers to the shortest distance between the opposing side surfaces of the conductor 242a1 and the conductor 242b1. Furthermore, the distance L2 refers to the shortest distance between the opposing side surfaces of the conductor 242a2 and the conductor 242b2. This configuration can further shorten the distance between the source and drain, thereby shortening the channel length. This improves the frequency characteristics of the transistor 200. In this way, miniaturization of the semiconductor device can provide a semiconductor device with high operating speed.

[0106] The conductors 242a1 and 242b1 in contact with the oxide semiconductor 230 are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. This can suppress, for example, a decrease in the conductivity of the conductors 242a and 242b, which would otherwise be caused by oxidation of the conductors 242a1 and 242b1 by oxygen contained in the oxide semiconductor 230. Furthermore, it can suppress the formation of excessive oxygen vacancies due to oxygen being extracted from the oxide semiconductor 230. Examples of conductive materials that are resistant to oxidation or that have a function of suppressing oxygen diffusion include metal nitrides. Examples of such metal nitrides include nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum. In one embodiment of the present invention, nitrides containing tantalum are particularly preferable. Furthermore, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used as the conductor 242a1 and the conductor 242b1.

[0107] Furthermore, when a material that easily absorbs (extracts) hydrogen is used for the conductors 242a1 and 242b1, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. Ｏ H) can be reduced.

[0108] When VoH is formed in the oxide semiconductor 230, electrons that serve as carriers may be generated. Therefore, when VoH is formed in the channel formation region of the oxide semiconductor 230, the transistor 200 may have normally-on characteristics (characteristics in which a channel exists and a current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, when VoH in the channel formation region is reduced, the channel formation region becomes i-type or substantially i-type, and a semiconductor device with favorable electrical characteristics can be provided.

[0109] The conductors 242a2 and 242b2 preferably have higher conductivity than the conductors 242a1 and 242b1. For example, the film thicknesses of the conductors 242a2 and 242b2 are preferably greater than the film thicknesses of the conductors 242a1 and 242b1, respectively. Conductive materials containing, for example, tungsten, copper, or aluminum as a main component can be used for the conductors 242a2 and 242b2. The above structure can reduce the electrical resistance of the conductors 242a2 and 242b2. This can increase the on-current of the transistor 200. Therefore, a semiconductor device with high operating speed can be provided.

[0110] For example, tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.

[0111] 4C shows an example in which a recess is formed in a region between the conductor 242a1 and the conductor 242b1 of the oxide semiconductor 230. As will be described in detail later, when the conductors to be the conductors 242a1 and 242b1 are processed, the oxide semiconductor 230 is also processed, and thus a recess may be formed in the oxide semiconductor 230.

[0112] Although the above description has been given of a configuration in which two circumferential oxide semiconductors 230 are provided, the present invention is not limited to this. For example, one or three or more circumferential oxide semiconductors 230 may be provided. Furthermore, the circumferential oxide semiconductors 230 may be joined to form an oxide semiconductor 230 having a shape with multiple openings. For example, as shown in FIG. 5A , an oxide semiconductor 230 having three openings arranged in the A1-A2 direction in a planar view may be provided. In this case, for example, three pillars may be formed adjacent to each other at a short distance, and the oxide semiconductor 230 may be formed between the pillars. Furthermore, as shown in FIG. 5B , an oxide semiconductor 230 having a lattice shape in a planar view may be provided. In this case, for example, lattice-shaped grooves may be formed in the pillars, and the oxide semiconductor 230 may be formed to fill the grooves. The number of oxide semiconductors 230 is not limited to two, and one or three or more may be provided. In this way, it is preferable that the oxide semiconductor 230 has a structure including a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (B1-B2 direction), which can prevent the oxide semiconductor 230 from collapsing during the manufacturing process of the transistor when the oxide semiconductor 230 has a high aspect ratio.

[0113] [Oxide Semiconductor Layer] Here, an oxide semiconductor layer that can be used for the oxide semiconductor 230 will be described. The oxide semiconductor layer contains a metal oxide.

[0114] Note that it is preferable that hydrogen in the oxide semiconductor layer be reduced as much as possible. Hydrogen in the oxide semiconductor layer is generated by oxygen vacancies (V Ｏ ) and V Ｏ Defects with hydrogen in the ＯSince a gate insulating film (H) is formed, transistor characteristics (e.g., the Id-Vg characteristics of the transistor at an initial stage or the Id-Vg characteristics in a long-term reliability test) may be deteriorated. Therefore, a material that releases little hydrogen is preferably used as a material surrounding the oxide semiconductor layer, for example, as a material used for an insulator in contact with the oxide semiconductor layer. Examples of such a material that releases little hydrogen include silicon nitride, silicon nitride oxide, aluminum oxide, and hafnium oxide. This can prevent hydrogen from entering the oxide semiconductor layer. In particular, using silicon nitride for at least one of the insulators in contact with the oxide semiconductor layer can improve the reliability of the transistor. Note that a material that releases little hydrogen may have a function of capturing or fixing (also referred to as gettering) hydrogen inside the insulator.

[0115] When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0116] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure.

[0117] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0118] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a crystal structure different from either a single-crystal structure or a polycrystalline structure. In particular, the oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure.

[0119] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the a-b plane without any clear grain boundaries. When a cross section of an oxide semiconductor layer having the CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as a row of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0120] In addition, a structure in which metal atoms in each of the multiple microcrystals are arranged in layers parallel or approximately parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the surface on which the metal atoms are formed, may be referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the multiple microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0121] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel to or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0122] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the a-b plane, so a highly reliable semiconductor device can be realized. Furthermore, because there are fewer crystal grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor including an oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, so that the transistor can be suitable for high-speed operation.

[0123] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0124] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0125] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of the surface of the oxide semiconductor layer.

[0126] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0127] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is obtained, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. A region in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface on which the film is formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0128] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0129] The method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of the line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0130] An example of the observation range of the TEM in creating the Voronoi diagram is a rectangular region of 50 nm in length and 50 nm in width, although the observation range is not limited to this.

[0131] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0132] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0133] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not limited. The oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0134] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain the element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, the element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain the element M. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may also include metalloid elements.

[0135] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0136] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel to or approximately parallel to the surface on which the oxide semiconductor layer is formed. The metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0137] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0138] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0139] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0140] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0141] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0142] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0143] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide using two types of film formation methods.

[0144] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. A sputtering method can be used to form a metal oxide with high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or another method may be used.

[0145] Here, when a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface on which the metal oxide is to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface on which the metal oxide is to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, etc., which are described as the first film formation method, and then providing a metal oxide formed using the first film formation method as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface on which the metal oxide is to be formed can be suppressed. Furthermore, impurities contained in the surface on which the metal oxide is to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0146] The ALD method and the chemical vapor deposition (CVD) method are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to the sputtering method. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes less damage to the surface to be formed. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed, and examples of the wet method include spray coating.

[0147] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0148] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0149] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (the first and third layers) can be increased by using the second layer (i.e., CAAC) having high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming oxide semiconductor layers with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0150] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0151] 6A to 6D , an example of a method for manufacturing the oxide semiconductor 30 will be described. The oxide semiconductor 30 can be used as the oxide semiconductor 230, for example.

[0152] First, a layer 29 is formed. The layer 29 corresponds to an insulating film or a conductive film included in the semiconductor device. For example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used as the layer 29. Alternatively, for example, a conductive film that functions as an electrode of the semiconductor device can be used as the layer 29. The layer 29 does not need to be crystalline. In other words, the layer 29 may have an amorphous structure. Furthermore, when the layer 29 is crystalline, it may have a crystal structure that has low lattice matching with the metal oxide included in the oxide semiconductor 30.

[0153] Next, an oxide semiconductor 30a is formed on the layer 29 (FIG. 6A).

[0154] In a manufacturing method of one embodiment of the present invention, the oxide semiconductor 30b is formed by a sputtering method, as described later. When a metal oxide film is formed by a sputtering method, a mixed layer (also called alloying) of components of the metal oxide film to be formed and components contained in a layer on which the film is to be formed may be formed due to sputtering particles emitted from a target or the like, or energy imparted to the substrate by the sputtering particles or the like. There is a concern that alloying may inhibit crystallization of the oxide semiconductor layer thereover. Furthermore, when alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. There is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor.

[0155] Therefore, before forming the oxide semiconductor 30b, the oxide semiconductor 30a is formed in advance using a film formation method that causes minimal damage to the surface on which the oxide semiconductor 30b is to be formed. This suppresses alloying of the components contained in the oxide semiconductor 30 with the components contained in the layer 29, and reduces the thickness of the alloyed region, or makes the alloyed region thin enough that it cannot be observed. Here, the oxide semiconductor 30a is formed using the ALD method.

[0156] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0157] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Because the ALD method can deposit atoms layer by layer, it has the following advantages: it is possible to form an ultrathin film; it is possible to form a film on a surface with a high aspect ratio or large steps; it is possible to form a film with few defects such as pinholes; it is possible to form a film with excellent coverage; and it is possible to form a film at a low temperature. By using the ALD method for the oxide semiconductor 30a and the oxide semiconductor 30c (described later), the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with a high aspect ratio.

[0158] Furthermore, the PEALD method may be preferable because it allows film formation at lower temperatures by utilizing plasma. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods.

[0159] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 30a by ALD will be described.

[0160] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of layer 29. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer in which indium and oxygen are combined.

[0161] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0162] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer in which element M and oxygen are bonded. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0163] By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 30a on the layer 29 by the ALD method.

[0164] The substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0165] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the chamber, and then discharge the excess precursor and reaction products, etc. from the chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the chamber, and then discharge the excess reactant and reaction products, etc. from the chamber.

[0166] Furthermore, unless otherwise specified in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, it is understood that these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states.

[0167] When the oxide semiconductor 30a is formed using the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed.

[0168] Next, an In-M-Zn oxide is formed as the oxide semiconductor 30b on the oxide semiconductor 30a by sputtering (FIG. 6B). The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure.

[0169] When the oxide semiconductor 30b is formed by sputtering, a mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. Furthermore, sputtering particles during the formation of the oxide semiconductor 30b or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 31. In a subsequent heat treatment step, the mixed layer 31 or the minute crystalline regions formed in the mixed layer 31 may act as nuclei, causing at least a portion of the oxide semiconductor 30a to crystallize.

[0170] Sputtering methods include RF sputtering, which uses a high-frequency power supply as a sputtering power supply; DC sputtering, which uses a direct-current power supply; and pulsed DC sputtering, which changes the voltage applied to an electrode in a pulsed manner. DC sputtering can be suitably used to form a metal conductive film and can improve productivity due to its high film formation rate. Pulsed DC sputtering can be suitably used to form a metal conductive film and a semiconductor film. RF sputtering can be suitably used to form an insulating film. Compounds such as oxides, nitrides, and carbides can be formed by reactive sputtering using a reactive gas. The metal oxide used for the oxide semiconductor layer of one embodiment of the present invention can be formed by a method appropriately selected from these methods depending on the conductivity of the sputtering target and the like.

[0171] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0172] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0173] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0174] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.

[0175] In forming the oxide semiconductor 30b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, increasing the substrate temperature (stage temperature) during metal oxide formation may result in the formation of a metal oxide with high crystallinity. In forming the oxide semiconductor 30b by sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0176] Here, a model for forming a CAAC structure using a sputtering method will be described. First, microcrystals are formed during sputtering film formation. The microcrystals may be formed by energy imparted to the substrate by sputtered particles (sometimes referred to as atomic particles) or gas particles. Alternatively, planar or pellet-shaped sputtered particles (sometimes referred to as nanoclusters) that peel off from the sputtering target and deposit on the surface to be formed may become the microcrystals. Subsequently, sputtered particles are adsorbed to the ends of the microcrystals, causing the microcrystals to grow laterally (in a direction roughly parallel to the surface to be formed). As the microcrystals grow laterally, adjacent microcrystals connect to each other, eliminating the ends of the microcrystals. Once the ends of the microcrystals are eliminated, sputtered particles are adsorbed onto the microcrystals, causing the microcrystals to grow vertically (in a direction roughly perpendicular to the surface to be formed). Sputtered particles are adsorbed to the ends of the vertically grown microcrystals, causing the microcrystals to grow laterally. In this way, the CAAC structure is formed by the microcrystals repeatedly growing in the lateral and vertical directions. That is, the CAAC structure is formed by the growth of microcrystals contained in an oxide semiconductor, using the microcrystals as nuclei or seeds.

[0177] Note that a CAAC structure is difficult to form in an oxide semiconductor containing impurities such as silicon, carbon, or water. Therefore, the oxide semiconductor 30b is preferably formed using a deposition method that is less likely to introduce impurities. Sputtering is suitable for forming the oxide semiconductor 30b because it can form an oxide semiconductor with a low impurity concentration by using a sputtering target with a reduced impurity concentration and a deposition gas with a reduced amount of impurities.

[0178] Next, the oxide semiconductor 30c is formed on the oxide semiconductor 30b (FIG. 6C). Here, the oxide semiconductor 30c is formed by the ALD method. For the formation of the oxide semiconductor 30c by the ALD method, the method for forming the oxide semiconductor 30a can be referred to.

[0179] When an oxide semiconductor 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor 30b having a CAAC structure by using an ALD method, the oxide semiconductor 30c may grow epitaxially around the oxide semiconductor 30b as a nucleus. Therefore, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 30c.

[0180] The oxide semiconductor 30c can be used, for example, as a layer in contact with a gate insulator of a transistor. By increasing the crystallinity of the layer in contact with the gate insulator, carrier mobility can be increased when the transistor is in an on state.

[0181] Furthermore, by forming the oxide semiconductor 30c using the ALD method, damage to the oxide semiconductor 30b is reduced, and the oxide semiconductor 30 as a whole can have high crystallinity.

[0182] By using the ALD method, which has high coverage, as a method for forming the oxide semiconductors 30a and 30c, the oxide semiconductor layer as a whole can be provided with coverage. Furthermore, by forming the oxide semiconductor 30b with high crystallinity using a sputtering method, the crystallinity of the oxide semiconductor layers above and below (the oxide semiconductor 30a and the oxide semiconductor 30c) can be increased by epitaxial growth or the like from the oxide semiconductor 30b. This allows the oxide semiconductor 30 to have high crystallinity throughout the entire layer. Therefore, the oxide semiconductor 30 can have both high coverage and high crystallinity.

[0183] Next, a heat treatment step may be carried out.

[0184] The heat treatment can be performed at a temperature of, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, the temperature can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When a rapid thermal annealing (RTA) apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 30b with the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method).

[0185] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0186] The heat treatment step may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c. Furthermore, if the region is formed only below the oxide semiconductor 30c after the ALD deposition, the heat treatment step may cause the region to expand upward ( FIG. 6D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 30c.

[0187] Furthermore, the heat treatment process may further repair the oxide semiconductor 30b by the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method) filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor 30b.

[0188] Furthermore, it is preferable that at least a portion of the oxide semiconductor 30a is converted into CAAC by the heat treatment ( FIG. 6D ). It is expected that the CAAC conversion is facilitated by the mixed layer 31 formed in the oxide semiconductor 30a during the deposition of the oxide semiconductor 30b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 30a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 29.

[0189] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 30a, the CAAC can be formed up to the vicinity of the layer 29 regardless of the material or crystallinity of the layer 29. For example, even if the layer 29 has an amorphous structure, the oxide semiconductor 30a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0190] After the oxide semiconductor 30c is formed, a microwave plasma treatment may be performed.

[0191] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0192] It is preferable to reduce the impurity concentration in the oxide semiconductor 30 by performing microwave plasma treatment in an atmosphere containing oxygen. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0193] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or more and 1000 Pa or less, and more preferably being 300 Pa or more and 700 Pa or less. The microwave plasma treatment is preferably carried out in a heated state. The substrate temperature is preferably set to be room temperature (e.g., 25°C) or more and 500°C or less, preferably 100°C or more and 500°C or less, more preferably 200°C or more and 500°C or less, even more preferably 300°C or more and 500°C or less, and even more preferably 400°C or more and 500°C or less. For example, the temperature can be set to be 400°C or more and 450°C or less.

[0194] Alternatively, after the microwave plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The heat treatment temperature is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0195] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave plasma treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the oxide semiconductor layer. By the action of plasma, microwaves, or the like, defects (V) in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer can be formed. Ｏ In this way, the V contained in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen impurities can be removed from the oxide semiconductor layer. ＯH can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, oxygen vacancies formed in the oxide semiconductor layer can be further reduced by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the oxide semiconductor layer.

[0196] Oxygen to be implanted into the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that the oxygen to be implanted into the oxide semiconductor layer can be in one or more of the above forms, and is particularly preferably an oxygen radical.

[0197] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0198] Note that one or both of the heat treatment and the microwave plasma treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0199] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher one or more of a relative dielectric constant, a film density, and a film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0200] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, or the like) can be realized.

[0201] In the oxide semiconductor 30, it is preferable that a region having a CAAC structure is widely present throughout the entire layer including the oxide semiconductors 30a and 30c. Fig. 7A shows the crystallization of the oxide semiconductors 30a, 30b, and 30c. The crystals in the region having a CAAC structure in the oxide semiconductor 30a are connected to the crystals in the region having a CAAC structure in the oxide semiconductor 30b. The crystals in the region having a CAAC structure in the oxide semiconductor 30c are connected to the crystals in the region having a CAAC structure in the oxide semiconductor 30b. The oxide semiconductor 30 can sometimes be expressed as a single layer with no clearly observed interface. The oxide semiconductor 30 can sometimes be expressed as a single layer.

[0202] The regions having the CAAC structure in the oxide semiconductors 30a, 30b, and 30c can be observed as bright spots aligned parallel to the surface on which they are formed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axes of the CAAC structures in the oxide semiconductors 30a, 30b, and 30c are each approximately parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0203] Furthermore, there are cases where a portion of the oxide semiconductor 30a or the oxide semiconductor 30c is not crystallized. The example shown in Fig. 7B shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a is not crystallized. Fig. 7C shows a state in which the vicinity of the surface in the oxide semiconductor 30c is not crystallized. Fig. 7D shows a state in which the vicinity of the interface with the layer 29 in the oxide semiconductor 30a and the vicinity of the surface of the oxide semiconductor 30c are not crystallized.

[0204] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 30, the boundaries between the stacked oxide semiconductors 30a, 30b, and 30c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0205] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small. This allows the oxide semiconductor 30a or the oxide semiconductor 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 30b. In this case, for example, when a cross section of the oxide semiconductor 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0206] As long as the lattice mismatch between the crystal of the oxide semiconductor 30b and the crystal of the oxide semiconductor 30a or the oxide semiconductor 30c is small, the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c is not particularly limited. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0207] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0208] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the film thickness of the oxide semiconductor 30 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, and further preferably 5 nm to 12 nm.

[0209] The oxide semiconductor 30b preferably has a thickness of, for example, 200 nm or less. When the oxide semiconductor 30b has a layer shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0210] Alternatively, if the oxide semiconductor 30b can function as a crystal nucleus, the oxide semiconductor 30b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 30b exist discretely.

[0211] The oxide semiconductor 30a and the oxide semiconductor 30c each have a thickness of, for example, 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm.

[0212] The thickness of the region where the component contained in the oxide semiconductor 30 and the component contained in the layer 29 are alloyed is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 6A and 6B show an example in which no alloy region is formed between the layer 29 and the oxide semiconductor 30a.

[0213] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0214] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 30a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 30a contains In) that is the main component of the oxide semiconductor 30a but is not the main component of the layer that will become the surface (here, layer 29) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 30a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 30a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0215] For example, when a silicon oxide layer is used as the layer 29 and an SIMS analysis is performed on the oxide semiconductor 30 formed on the layer 29, the interface is defined as a depth at which the silicon concentration is 50% of the maximum concentration of the layer 29, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 0.5 nm and the interface is defined as thickness t_s. The thickness t_s is preferably 3 nm or less, and more preferably 2 nm or less.

[0216] Note that by reducing the alloyed region, it is possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor 30.

[0217] The oxide semiconductor 30a has a region that is provided, for example, at a depth of 0 nm to 3 nm from the top surface of the layer 29. The oxide semiconductor 30c is provided, for example, at a depth of 0 nm to 3 nm from the top surface of the oxide semiconductor 30. The oxide semiconductors 30a, 30b, and 30c have, for example, approximately the same thickness. Alternatively, the oxide semiconductors 30a, 30b, and 30c may have different thicknesses.

[0218] Although the oxide semiconductor 30 has a three-layer structure of the oxide semiconductors 30a to 30c in the above description, the present invention is not limited to this. The oxide semiconductor 30 may have a two-layer structure or a stacked structure of four or more layers.

[0219] When the oxide semiconductor 30 has a two-layer structure, the oxide semiconductor 30 can have a configuration in which an oxide semiconductor 30a and an oxide semiconductor 30b are stacked in this order. By using such a configuration, alloying of the components contained in the oxide semiconductor 30 and the components contained in the layer 29 can be suppressed, and the thickness of the alloyed region can be reduced, or the thickness can be made so thin that the alloyed region is not observable.

[0220] Alternatively, when the oxide semiconductor 30 has a five-layer structure, the oxide semiconductor 30 can have a structure in which a first oxide semiconductor, a second oxide semiconductor, a third oxide semiconductor, a fourth oxide semiconductor, and a fifth oxide semiconductor are stacked in this order. For example, the first oxide semiconductor, the third oxide semiconductor, and the fifth oxide semiconductor are preferably formed by the second film formation method, more preferably by an ALD method. The second oxide semiconductor and the fourth oxide semiconductor are preferably formed by the first film formation method, more preferably by a sputtering method. With such a structure, even if the third oxide semiconductor has a composition that makes it difficult to form a CAAC structure, crystal growth can be promoted from one or both of the second oxide semiconductor and the fourth oxide semiconductor, thereby improving the crystallinity of the third oxide semiconductor.

[0221] When the oxide semiconductor 30 has a stacked structure of two or more layers, typically a stacked structure of two to five layers, it is preferable to deposit each layer successively without exposing it to the atmosphere. For example, each layer can be deposited successively using a multi-chamber deposition apparatus. This allows the oxide semiconductor 30 to be deposited while suppressing impurities that may be mixed into each layer.

[0222] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0223] The CAAC structure of an oxide semiconductor layer can sometimes be evaluated from a map showing crystal orientation. For example, in a region having the CAAC structure, it is observed that crystals are c-axis oriented.

[0224] A map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the direction of the crystal axis of each region. Specifically, for example, two spots of high intensity are observed in the FFT pattern of a region having layered crystal portions. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0225] The c-axis orientation rate can be calculated by calculating the proportion of the c-axis oriented region in the map showing the crystal orientation.

[0226] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0227] Furthermore, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image can be, for example, a region with a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0228] In the oxide semiconductor layer of one embodiment of the present invention, when the c-axis orientation rate is calculated as the percentage of regions whose orientation is within 20° of the c-axis, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0229] The c-axis orientation rates of the region where the oxide semiconductor 30a is formed, the region where the oxide semiconductor 30b is formed, and the region where the oxide semiconductor 30c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Here, the c-axis orientation rate is calculated as, for example, the percentage of regions where the difference from the c-axis is within 20°. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. It is preferable that Rc3 / Rc1 be greater than 1. It is also preferable that Rc2 / Rc1 be greater than 1.

[0230] [Composition of Oxide Semiconductor Layer] The oxide semiconductor 30a preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30c preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30a may have the same composition as the oxide semiconductor 30c. Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may have different compositions.

[0231] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 30b preferably contains, in addition to zinc, the element M. By containing the element M in the oxide semiconductor 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Specifically, the oxide semiconductor 30b may be a metal oxide having an In:M:Zn=1:1:1 atomic ratio or a composition thereof, an In:M:Zn=1:1:1.2 atomic ratio or a composition thereof, an In:M:Zn=1:1:0.5 atomic ratio or a composition thereof, an In:M:Zn=1:1:2 atomic ratio or a composition thereof, an In:M:Zn=4:2:3 atomic ratio or a composition thereof, an In:M:Zn=1:3:2 atomic ratio or a composition thereof, or an In:M:Zn=1:3:4 atomic ratio or a composition thereof. Note that a composition thereof includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, tin, yttrium, and aluminum as the element M.

[0232] The oxide semiconductor 30b may not contain the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition with an atomic ratio of In:Zn=1:1 or a ratio therebetween, an atomic ratio of In:Zn=2:1 or a ratio therebetween, or an atomic ratio of In:Zn=4:1 or a ratio therebetween. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductor 30b may have a trace amount of the element M. For example, it may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Ga:Zn=2:0.1:1 or a ratio therebetween. Furthermore, it may have a composition with an atomic ratio of In:Sn:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a ratio therebetween.

[0233] The oxide semiconductor 30a and the oxide semiconductor 30c can be metal oxides having a high proportion of In. It is particularly preferable that the oxide semiconductor 30a and the oxide semiconductor 30c be metal oxides having a higher proportion of In than the oxide semiconductor 30b. For example, the ALD method can be used to form the oxide semiconductor 30a and the oxide semiconductor 30c. It is particularly preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-current and frequency characteristics can be increased.

[0234] An oxide semiconductor with a high In content tends to be polycrystalline. Using a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. In the oxide semiconductor layer of one embodiment of the present invention, the crystal orientation of the oxide semiconductor 30b can be reflected in the oxide semiconductors 30a and 30c with a high In content. Therefore, even when a metal oxide with a high In content is used for the oxide semiconductors 30a and 30c, polycrystallization can be suppressed.

[0235] Alternatively, the oxide semiconductors 30a and 30c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition with an atomic ratio of In:Zn=1:1 or a ratio therebetween, an atomic ratio of In:Zn=2:1 or a ratio therebetween, or an atomic ratio of In:Zn=4:1 or a ratio therebetween. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductors 30a and 30c may contain a trace amount of the element M. Specifically, they may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a ratio therebetween, an atomic ratio of In:Ga:Zn=2:0.1:1 or a ratio therebetween, an atomic ratio of In:Sn:Zn=4:0.1:1 or a ratio therebetween, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a ratio therebetween.

[0236] Alternatively, metal oxides with a high Ga content may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with a higher Ga content than the oxide semiconductor 30b may be used for the oxide semiconductors 30a and 30c. For example, metal oxides with an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, metal oxides with an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or metal oxides with an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout are preferably used for the oxide semiconductors 30a and 30c, respectively. Increasing the Ga content may result in the band gaps of the oxide semiconductors 30a and 30c being larger than those of the oxide semiconductor 30b. As a result, the oxide semiconductor 30b is sandwiched between the oxide semiconductors 30a and 30c, which have larger band gaps, allowing the oxide semiconductor 30b to function primarily as a current path (channel). Furthermore, the trap levels at and near the interface of the oxide semiconductor 30b can be reduced. This allows a buried channel transistor in which the channel is located away from the insulator interface to be realized, thereby increasing the . In addition, the influence of interface states that may be formed on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving the reliability of the transistor.

[0237] Alternatively, one of the oxide semiconductors 30a and 30c may be a metal oxide having a higher proportion of In than the oxide semiconductor 30b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor 30b.

[0238] The oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may each have a plurality of layers each having the above-described composition stacked together. For example, the oxide semiconductor 30c may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0239] The oxide semiconductor 30a and the oxide semiconductor 30c may be made of a metal oxide having the same composition as the oxide semiconductor 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0240] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 30a and 30c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs with the oxide semiconductor 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 30a and 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductors 30a and 30c and the oxide semiconductor 30b.

[0241] The composition of the metal oxide used in the oxide semiconductor 30 can be analyzed by, for example, EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0242] [Impurities in Oxide Semiconductor] Here, a description will be given of the influence of each impurity in the oxide semiconductor 30. The impurities contained in the oxide semiconductor 30 can be quantified using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0243] It is preferable that the channel formation region of a transistor using the oxide semiconductor 30 as a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ), and impurities may cause fluctuations in electrical characteristics and reduce reliability. Ｏ H may be formed, and electrons serving as carriers may be generated. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor 30, the transistor is likely to have normally-on characteristics. Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0244] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor 30. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor 30 refer to, for example, elements other than the main components constituting the oxide semiconductor 30. For example, an element with a concentration of less than 1 atomic % or less than 0.1 atomic % may be referred to as an impurity.

[0245] When the oxide semiconductor 30 contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor 30. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10１８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0246] Furthermore, when nitrogen is contained in the oxide semiconductor 30, electrons serving as carriers are generated, the carrier concentration increases, and the oxide semiconductor 30 is likely to become n-type. As a result, a transistor using the oxide semiconductor 30 containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in the oxide semiconductor 30, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0247] Furthermore, hydrogen contained in the oxide semiconductor 30 may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor 30 containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor 30. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor 30 obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0248] Furthermore, when the oxide semiconductor 30 contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using the oxide semiconductor 30 containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor 30 obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0249] When the oxide semiconductor 30 in which the impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0250] The average thickness of the oxide semiconductor 30 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and even more preferably 10 nm or less.

[0251] The oxide semiconductor 30a is an oxide semiconductor layer formed on a surface to be formed. The thickness of the oxide semiconductor 30a is preferably 0.5 nm or more and 3 nm or less.

[0252] In addition, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to see that metal atoms of the metal oxide are arranged in a layered manner in a region having a CAAC structure. In this case, for example, the metal atoms are arranged in a direction perpendicular or approximately perpendicular to the substrate surface.

[0253] The metal atoms arranged in a layered manner in the region having the CAAC structure can be observed as an array of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. Therefore, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to confirm that the bright spots are arranged in a direction perpendicular or approximately perpendicular to the substrate surface.

[0254] The oxide semiconductor 30, which is AG CAAC, can be used as the oxide semiconductor 230 of the transistor 200. For example, as shown in Figures 4A and 4B, the oxide semiconductor 230 can have a structure including an oxide semiconductor 230a, an oxide semiconductor 230b in contact with the oxide semiconductor 230a, and an oxide semiconductor 230c in contact with the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c.

[0255] Here, the pillars (protrusions 206 of the insulator 223 described later) correspond to the layer 29. That is, the surface on which the oxide semiconductor 230 is formed is the pillar, and the pillars are removed in the transistor 200. During the manufacturing process, one side surface of the oxide semiconductor 230a is in contact with the pillar, and the other side surface is in contact with the oxide semiconductor 230b. After the pillars are removed, one side surface of the oxide semiconductor 230a is in contact with the insulator 250. One side surface of the oxide semiconductor 230b is in contact with the oxide semiconductor 230a, and the other side surface is in contact with the oxide semiconductor 230c. One side surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b, and the other side surface is in contact with the insulator 250. Here, since the side surfaces of the pillars are formed perpendicular or approximately perpendicular to the substrate surface (which can also be referred to as the surface of the insulator 222), the side surfaces of the oxide semiconductors 230 (oxide semiconductors 230a to 230c) are also perpendicular or approximately perpendicular to the substrate surface.

[0256] As described above, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that metal atoms are arranged in layers parallel to or substantially parallel to the surface where the oxide semiconductor 230 is formed. In other words, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that metal atoms are arranged in layers perpendicular to or substantially perpendicular to the surface of the substrate. It can also be said that the c-axis of AG CAAC is substantially parallel to the normal direction to the side surface of the oxide semiconductor 230.

[0257] In this manner, by using the oxide semiconductor 230 which is AG CAAC for the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0258] Furthermore, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c as described above, the oxide semiconductor 230 is formed in the order of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c, centered on the region where the pillars were formed. Therefore, as shown in FIG. 8A , in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged symmetrically in this order. That is, to make the oxide semiconductor 230 have a bilaterally symmetric structure in a cross-sectional view, it is preferable that the oxide semiconductors 230a and 230c have approximately the same composition. It is also preferable that the oxide semiconductors 230a and 230c have approximately the same film thickness. When the angle formed by the side surface of the oxide semiconductor 230 and the top surface of the insulator 222 is equal to or greater than 80° and less than 90°, that is, when the side surface of the oxide semiconductor 230 is slightly tilted, the tilt of the oxide semiconductor 230 is arranged symmetrically as shown in Fig. 8B. When the oxide semiconductor 230 is formed at an angle, the upper part of the oxide semiconductor 230 may be thinner than the lower part of the oxide semiconductor 230, as shown in Fig. 8B.

[0259] A channel formation region and a source region and a drain region sandwiching the channel formation region in the transistor 200 are formed in the oxide semiconductor 230. At least part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0260] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0261] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0262] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0263] Note that when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0264] To stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0265] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide semiconductor 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0266] As described above, impurities, oxygen vacancies, and V Ｏ In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is i-type (intrinsic) or substantially i-type. Here, by providing an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0267] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce the V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0268] Therefore, in this embodiment, the semiconductor device has a structure that reduces the hydrogen concentration in the channel formation region, suppresses oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppresses a reduction in the hydrogen concentration in the source and drain regions.

[0269] [Insulator and Conductor] The insulator 250 in contact with the channel formation region of the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0270] 4A and 4C , the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b over the insulator 250a, an insulator 250c over the insulator 250b, and an insulator 250d over the insulator 250c. In this case, the insulator 250a and the insulator 250c preferably have a function of capturing or fixing hydrogen.

[0271] Examples of insulators capable of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulators 250a and 250c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium.

[0272] Furthermore, it is preferable to use a high-k material for the insulator 250a and the insulator 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulator 250a and the insulator 250c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0273] In this specification and the like, a high-k material refers to a material having a higher relative dielectric constant than silicon oxide.

[0274] For the insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0275] In this embodiment, an aluminum oxide film is used as the insulator 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively captured and fixed.

[0276] In this embodiment, hafnium oxide is used as the insulator 250c. By providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0277] Next, it is preferable to use a thermally stable insulator such as silicon oxide or silicon oxynitride for the insulator 250b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0278] The silicon oxide film used as the insulator 250b is preferably formed using a PEALD method.

[0279] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250d, the insulator 250c, the insulator 255, and the insulator 275.

[0280] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a1 and the side surface of the conductor 242b1. The insulator 250a having a barrier property against oxygen can prevent the side surfaces of the conductor 242a1 and the conductor 242b1 from being oxidized and forming an oxide film on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. Therefore, a semiconductor device with good electrical characteristics can be provided.

[0281] The insulator 250a is provided in contact with the top surface and side surface of the oxide semiconductor 230, the side surface of the insulator 224, and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide semiconductor 230 during heat treatment or the like. Thus, oxygen vacancies can be reduced in the oxide semiconductor 230.

[0282] Furthermore, the insulator 250a prevents excessive oxygen from being supplied from the insulator 280 to the oxide semiconductor 230, and enables an appropriate amount of oxygen to be supplied to the oxide semiconductor 230. Therefore, excessive oxidation of the source and drain regions can be suppressed, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0283] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and can therefore be suitably used as the insulator 250a.

[0284] The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. Furthermore, oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0285] The insulator 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230.

[0286] It is preferable that the insulator 275 also has barrier properties against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This prevents oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, it is possible to prevent the conductor 242 from being oxidized by the oxygen contained in the insulator 280 and increasing its electrical resistivity. It is preferable that the insulator 275 is at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0287] In order to suppress a decrease in the hydrogen concentrations in the source and drain regions in the oxide semiconductor 230, an insulator having a barrier property against hydrogen (also referred to as a hydrogen barrier insulator) is preferably provided near each of the source and drain regions. In the semiconductor device described in this embodiment, the hydrogen barrier insulator is the insulator 275, for example.

[0288] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0289] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making it possible to make the source and drain regions n-type.

[0290] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0291] The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d are provided together with the conductor 260 inside the opening 201 formed in the insulator 275 and the insulator 280. To miniaturize the transistor 200, the insulators 250a to 250d preferably have a small thickness. The thickness of the insulators 250a to 250d is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that the insulators 250a to 250d preferably have at least a portion having a thickness as described above.

[0292] Furthermore, the thickness of the silicon oxide film used as the insulator 250b is preferably 0.7 nm or more and 3 nm or less.

[0293] In order to thin the film thicknesses of the insulators 250a to 250d as described above, it is preferable to deposit the insulators by an ALD method. Furthermore, in order to provide the insulators 250a to 250d inside the opening 201, it is preferable to deposit the insulators by an ALD method. Examples of ALD methods include thermal ALD (thermal ALD), which causes a reaction between a precursor and a reactant using only thermal energy, and plasma-enhanced ALD (PEALD), which uses a plasma-excited reactant. The PEALD method may be preferable because it uses plasma, which enables film deposition at a lower temperature.

[0294] As described above, the ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling extremely thin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the opening 201 provided in the insulators 275 and 280, the side edges of the conductors 242a and 242b, and the like, with a thin film thickness as described above. Furthermore, by forming the insulator 255 using the ALD method, like the insulator 250, the insulator 255 can also be formed with good coverage on the side surfaces of the opening 201, the side edges of the conductors 242a and 242b, and the like, which is preferable.

[0295] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0296] Although the above description has been given of a structure in which the insulator 250 has a four-layer structure of the insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0297] For example, as shown in Fig. 9, the insulator 250 may have a three-layer structure. In this case, it is preferable that the insulator 250 has a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In other words, this is a structure obtained by removing the insulator 250d from the structure shown in Fig. 4C.

[0298] It is preferable to use the ALD process two or more times in forming the insulator 250. For example, the insulator 250 preferably has a stacked structure of multiple insulating films, and two or more of the multiple insulating films are preferably formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulator 250. Furthermore, it is possible to increase productivity by continuously forming two or more different films, for example, two or more insulating films, using the ALD process.

[0299] In addition to the above structure, it is preferable to have a structure that suppresses hydrogen from being mixed into the transistor 200 or the like. For example, it is preferable to provide an insulator that has a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, the insulator 221, or the like. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0300] It is preferable that one or more of the insulators 283, 282, 222, and 221 function as barrier insulators that suppress diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or more of the insulators 283, 282, 222, and 221 suppress diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., impurities are less likely to permeate through the insulating material), or that has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., oxygen is less likely to permeate through the insulating material).

[0301] The insulators 283, 282, 222, and 221 each preferably have an insulator that functions to suppress the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, hafnium aluminate, an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulators 283 and 221 are preferably made of silicon nitride or the like, which has a higher barrier property against hydrogen. Furthermore, for example, the insulator 282 is preferably made of aluminum oxide or the like, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulator 222 is preferably made of hafnium oxide or the like, which is a high-k material and has a high ability to capture or fix hydrogen.

[0302] At least one of the insulators 221 and 222 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulator 221 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 222 can have a stacked structure of hafnium oxide and silicon oxide.

[0303] With this structure, impurities such as water and hydrogen can be prevented from diffusing from interlayer insulators provided above the insulator 283 to the transistor 200 and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from interlayer insulators provided below the insulator 221 to the transistor 200 and the like. Furthermore, hydrogen contained in the insulator 280, the insulator 250, and the like can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, the provision of the insulators 282 and 283 can prevent oxygen contained in the insulator 280 and the like from diffusing upward from the transistor 200 and the like. Furthermore, the provision of the insulators 222 and 221 can prevent oxygen contained in the oxide semiconductor 230 and the like from diffusing downward from the transistor 200 and the like. Thus, by surrounding the transistor 200 from above and below with insulators that have a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen into the oxide semiconductor can be reduced. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0304] Furthermore, it is preferable to use silicon nitride or the like, which has a higher barrier property against hydrogen, for the insulators 275 and 250d. It is also preferable to use aluminum oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250a. It is also preferable to use hafnium oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250c.

[0305] The conductor 242a and the conductor 242b are provided to be spaced apart from each other, and the conductor 242a1 and the conductor 242b1 are provided to be in contact with the oxide semiconductor 230. For example, as shown in FIG. 4B , the conductor 242 is provided to cover the oxide semiconductor 230 having a high aspect ratio. In addition, in a cross-sectional view, the conductor 242a1 (conductor 242b1) is preferably structured to be in contact with two or more fin-shaped oxide semiconductors 230, as shown in FIG. 2D .

[0306] Here, near the source or drain of the transistor 200, the conductor 242a is provided so as to be folded in half with the oxide semiconductor 230 sandwiched therebetween, as shown in FIG. 4B . As a result, in a cross-sectional view of the transistor 200 in the channel width direction, the conductor 242a1 is in contact with the oxide semiconductor 230 on the top surface, the side surface on the A3 side, and the side surface on the A4 side. Therefore, compared to when the oxide semiconductor 230 is flat, the contact area between the conductor 242a1 and the oxide semiconductor 230 is larger by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, by using a structure in which a plurality of fin-shaped oxide semiconductors 230 are in contact with the conductor 242a1 as shown in FIG. 2D , the contact area can be further increased. Note that although the vicinity of the conductor 242a is shown in FIGS. 2D , 2E , and 4B , the same applies to the conductor 242b. That is, similar to the contact area between the conductor 242a1 and the oxide semiconductor 230 described above, the contact area between the conductor 242b1 and the oxide semiconductor 230 is large.

[0307] By increasing the contact area between the conductor 242 and the oxide semiconductor 230 as described above, the on-state current, frequency characteristics, and the like of the transistor 200 can be improved without increasing the area occupied by the transistor 200. As a result, a semiconductor device with high operating speed can be provided. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, as a result, miniaturization or high integration of the semiconductor device can be achieved. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0308] Note that hydrogen contained in the oxide semiconductor 230 and the like might diffuse to the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used for the conductor 242a and the conductor 242b, for example, hydrogen contained in the oxide semiconductor 230 might easily diffuse to the conductor 242a or the conductor 242b, and the diffused hydrogen might bond with nitrogen contained in the conductor 242a or the conductor 242b. That is, for example, hydrogen contained in the oxide semiconductor 230 might be absorbed by the conductor 242a or the conductor 242b. For example, when a nitride containing tantalum is used for the conductor 242a1 and the conductor 242b1 in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 might be absorbed by the conductor 242a1 and the conductor 242b1.

[0309] Furthermore, to suppress a decrease in the conductivity of the conductor 242a and the conductor 242b, a crystalline oxide such as CAAC-OS can be used as the oxide semiconductor 230. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can suppress the extraction of oxygen from the oxide semiconductor 230 by the conductor 242a or the conductor 242b. For example, the extraction of oxygen from the oxide semiconductor 230 by the conductor 242a1 or the conductor 242b1 can be suppressed. Furthermore, a decrease in the conductivity of the conductor 242a and the conductor 242b can be suppressed.

[0310] 2C and 3A , the conductor 260 is provided inside the opening 201. In a cross-sectional view of the transistor 200 in the channel width direction, the conductor 260 is provided to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. The top surface of the conductor 260 is provided so as to be flush or approximately flush with the top of the insulator 250 and the top surface of the insulator 280.

[0311] The sidewall of the opening 201 may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may have a tapered shape. By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening 201 can be improved, and defects such as voids can be reduced.

[0312] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 2A and 2C. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0313] A part of the conductor 260 is folded in half to sandwich the fin-shaped oxide semiconductor 230. As a result, as described above, in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided to face each other with the insulator 250 sandwiched between them on the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. That is, in addition to the top surface, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 each function as a channel formation region. Therefore, compared to when the oxide semiconductor 230 is flat, the channel width of the transistor 200 is increased by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230.

[0314] 2C, 3A, 3B, 4A, 4C, etc., the conductor 260 is shown as a two-layer structure consisting of a conductor 260a and a conductor 260b provided on the conductor 260a. For example, the conductor 260a is provided inside the opening 201 so as to be in contact with the insulator 250. Furthermore, the conductor 260b is provided on the conductor 260a so as to fill the opening 201. In other words, the conductor 260a is provided so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0315] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0316] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0317] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0318] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill the opening 201. Here, the side surface of the insulator 280 in the opening 201 coincides or approximately coincides with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Therefore, the conductor 260 can be provided so as to overlap the region between the conductor 242a2 and the conductor 242b2 without alignment.

[0319] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, for example, parasitic capacitance occurring between wirings (not shown) can be reduced.

[0320] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0321] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0322] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0323] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon such as silicon oxide or silicon oxynitride.

[0324] Conductor 240a is provided inside opening 202a. Conductor 240b is provided inside opening 202b. The lower surface of conductor 240a contacts the upper surface of conductor 242a, and the lower surface of conductor 240b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.

[0325] The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may also have a layered structure in which a first conductor is provided in contact with the side surface of the insulator 241 and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor. Here, the first conductor corresponds to the conductor 240a1 shown in FIG. 4B , and the second conductor corresponds to the conductor 240a2 shown in FIG. 4B .

[0326] When the conductor 240 has a stacked structure, a first conductor provided near the insulators 283, 282, 280, and 275 is preferably made of a conductive material that has a function of suppressing permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. A conductive material that has a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulator 283 can be prevented from entering the oxide semiconductor 230 through the conductors 240a and 240b.

[0327] As described above, the insulator 241a is provided in contact with the sidewall of the opening 202a. The insulator 241b is provided in contact with the sidewall of the opening 202b. The inner side surface of the insulator 241a is in contact with the conductor 240a, and the inner side surface of the insulator 241b is in contact with the conductor 240b.

[0328] The insulator 241 can be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 can be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Providing the insulator 241 can prevent impurities such as water and hydrogen contained in the insulator 280, etc. from entering the oxide semiconductor 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0329] The insulator 241 may have a stacked structure. In this case, the insulator 241 may have a first insulator in contact with the sidewall of the opening 202 and a second insulator inside the first insulator. For the first insulator and the second insulator, the insulator 241 preferably uses, for example, a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0330] For example, the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD, which can suppress oxidation of the conductor 240 and reduce hydrogen contamination of the conductor 240.

[0331] Note that the insulator 241 may have a stacked structure of three or more layers. Although the conductor 240 has a two-layer stacked structure in the above description, the conductor 240 may have a single layer or a stacked structure of three or more layers.

[0332] For example, as shown in FIG. 4B , a structure may be used in which the conductor 240a covers the oxide semiconductor 230 and the conductor 242a that is folded in half with the oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view of the transistor 200 in the channel width direction, the conductor 240a contacts the conductor 242a on the top surface, the side surface on the A3 side, and the side surface on the A4 side of the oxide semiconductor 230. Therefore, compared to when the oxide semiconductor 230 is flat, the contact area between the conductor 240a and the conductor 242a is increased by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, as shown in FIG. 2D , a structure in which the conductor 240a covers multiple fin-shaped oxide semiconductors 230 can further increase the contact area between the conductor 240a and the conductor 242a. 2D and 4B show the conductors 240a and 242a, the same applies to the conductors 240b and 242b. In other words, the contact area between the conductors 240b and 242b is large, similar to the contact area between the conductors 240a and 242a described above.

[0333] As described above, by increasing the contact area between the conductor 240 and the conductor 242, the contact resistance between the conductor 240 and the conductor 242 can be reduced. This allows the on-state current, frequency characteristics, and the like of the transistor 200 to be improved without significantly increasing the area occupied by the transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0334] <Structure Example 2 of Semiconductor Device> Hereinafter, examples of the semiconductor device of one embodiment of the present invention that have a structure different from those illustrated in FIGS. 1A to 3B will be described.

[0335] 10A, 10B, 10C, and 10D correspond to FIGS. 2A, 2C, 3A, and 3B, respectively, and show an example in which the insulator 255 is not provided. Also, FIGS. 10A to 10D show an example in which the side end of the conductor 242a1 on the opening 201 side coincides or roughly coincides with the side end of the conductor 242a2 on the opening 201 side. Furthermore, FIGS. 10A to 10D show an example in which the side end of the conductor 242b1 on the opening 201 side coincides or roughly coincides with the side end of the conductor 242b2 on the opening 201 side. 10A to 10D , in plan view, not only the side end portion of the conductor 242a2 on the opening 201 side and the side end portion of the conductor 242b2 on the opening 201 side, but also the side end portion of the conductor 242a1 on the opening 201 side and the side end portion of the conductor 242b1 on the opening 201 side can be aligned or approximately aligned with the sidewall of the opening 201. Furthermore, in the example shown in Figures 10A to 10D , the insulator 250 can be provided inside the opening 201 so as to have a region in contact with the oxide semiconductor 230, a region in contact with the side surface of the conductor 242a1, and a region in contact with the side surface of the conductor 242b1, as well as a region in contact with the side surface of the conductor 242a2, a region in contact with the side surface of the conductor 242b2, a region in contact with the side surface of the insulator 275, and a region in contact with the side surface of the insulator 280. 10A to 10D, the conductor 242a and the conductor 242b may have a single-layer structure. Alternatively, the conductor 242a and the conductor 242b may have a stacked structure of three or more layers.

[0336] 10A to 10D can simplify the manufacturing process and improve productivity compared to the semiconductor device shown in Fig. 1A to 3B. On the other hand, the semiconductor device shown in Fig. 1A to 3B can have better electrical characteristics compared to the semiconductor device shown in Fig. 10A to 10D.

[0337] 11A, 11B, and 11C correspond to FIGS. 2A, 3A, and 3B, respectively, and illustrate an example in which the conductor 240a and the conductor 240b do not overlap with the oxide semiconductor 230. In the examples illustrated in FIGS. 11A to 11C, the openings 202a and 202b are provided outside the circumferential oxide semiconductor 230.

[0338] 11A to 11C , when the opening 202 is formed, it is not necessary to remove, for example, regions of the insulators 275, 280, 282, and 283 that overlap with the oxide semiconductor 230 by etching. Therefore, the region of the conductor 242 that overlaps with the oxide semiconductor 230 can be prevented from being exposed to an etching gas for a long time compared to the region that does not overlap with the oxide semiconductor 230. As a result, the opening 202 can be formed more easily in the example shown in FIGS. 1A to 11C than in the example shown in FIGS. 1A to 3B . Meanwhile, the area occupied by the conductor 242 can be made smaller in the example shown in FIGS. 1A to 3B than in the example shown in FIGS. 11A to 11C . This enables the transistor 200 to be miniaturized.

[0339] 12A and 12B correspond to FIGS. 2A and 3A , respectively, and illustrate an example in which the conductor 240a and the conductor 240b overlap with the region 234 of the oxide semiconductor 230 illustrated in FIG. 2B but do not overlap with the region 233. In the examples illustrated in FIGS. 12A and 12B , it can be said that the conductor 240a and the conductor 240b are provided inside (on the conductor 260 side) the region 233 of the oxide semiconductor 230 illustrated in FIG. 2B .

[0340] 2A , 3A , 3B , 11A , 11B , and 11C , the conductor 240a and the conductor 240b are arranged symmetrically with respect to the conductor 260, but the present invention is not limited to this. For example, as shown in FIGS. 13A and 13B , a part of the conductor 240a may overlap with the oxide semiconductor 230, and the conductor 240b may not overlap with the oxide semiconductor 230. Note that FIG. 13A is a plan view, and FIG. 13B is a cross-sectional view taken along the B1-B2 direction.

[0341] 14A, 14B, 14C, and 14D correspond to FIGS. 2A, 2C, 3A, and 3B, respectively, and illustrate an example in which a conductor 205 is provided under an insulator 221. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulators 222 and 221 each have a region that functions as a second gate insulator of the transistor 200.

[0342] In the transistor 200, the conductor 205 is provided to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided to be embedded in an opening 203 formed in the insulator 216. The conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 14A and 14B . With such a structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0343] The conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening 203. The conductor 205b is provided so as to fill a recess of the conductor 205a formed along the opening 203. Here, the height of the upper surface of the conductor 205 coincides with or approximately coincides with the height of the upper surface of the insulator 216.

[0344] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0345] By using a conductive material that can reduce hydrogen diffusion for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 via the insulator 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0346] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0347] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0348] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore, diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0349] Although the above describes a layered structure of conductor 205a and conductor 205b, the present invention is not limited to this, and conductor 205 may have a single-layer structure or a layered structure of three or more layers. For example, when conductor 205 has a three-layer layered structure, the above-mentioned layered structure of conductor 205a and conductor 205b can be further configured such that a conductor made of the same material as conductor 205a is provided on conductor 205b. In this case, the above-mentioned conductor may be configured so that the top surface of conductor 205b is lower than the top of conductor 205a, and so as to fill the recess formed by conductor 205a and conductor 205b.

[0350] FIG. 15A is a cross-sectional view of the transistor 200 taken along the A1-A2 direction, illustrating an example in which the transistor 200 includes a layer 231. The layer 231 covers the bottom surface and part of the side surface of the oxide semiconductor 230. Providing the layer 231 in the transistor 200 can prevent the oxide semiconductor 230 from contacting the insulator 224. This can prevent impurities from being mixed into the oxide semiconductor 230. For example, this can prevent elements (such as silicon) that constitute the insulator 224 and impurities (such as hydrogen) contained in the insulator 224 from being mixed into the oxide semiconductor 230. Therefore, forming the layer 231 can improve the reliability of the transistor 200 in some cases.

[0351] 15B shows an example in which the layer 231 shown in FIG. 15A has a stacked structure of a layer 231a and a layer 231b on the layer 231a. The layer 231a can be made of, for example, gallium oxide or zinc oxide.

[0352] The layer 231b preferably contains a metal element contained in the oxide semiconductor 230. The layer 231b preferably contains an oxide containing a metal element contained in the oxide semiconductor 230 but not contained in the layer 231a. For example, when indium gallium zinc oxide is used as the oxide semiconductor 230 and gallium oxide or zinc oxide is used as the layer 231a, the layer 231b preferably contains indium zinc oxide. In this case, the layer 231b may have a composition of In:Zn=2:1 (atomic ratio) or a composition therearound. Alternatively, the layer 231b may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound.

[0353] <Configuration Example of Memory Cell> A configuration example of a memory cell including the transistor 200 will be described below.

[0354] 16, a 2T (transistor) 1C (capacitor) memory cell can be formed by using a capacitor 460 and a transistor 310 formed on a silicon substrate in addition to the transistor 200. As shown in FIG. 16, a structure can be adopted in which a layer including the transistor 200 and the capacitor 460 is provided over a layer including the transistor 310. FIG. 17A shows a cross-sectional view of the transistor 200 in the channel width direction, FIG. 17B shows a cross-sectional view including the conductor 240a in the same direction, FIG. 17C shows a cross-sectional view of the capacitor 460 in the same direction, and FIG. 17D shows a cross-sectional view of the transistor 310 in the channel width direction.

[0355] The transistor 310 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes part of the substrate 311, a low-resistance region 314a that functions as one of a source region and a drain region, and a low-resistance region 314b that functions as the other of the source region and the drain region. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0356] As shown in FIG. 17D , the transistor 310 has a semiconductor region 313 (a part of the substrate 311) where a channel is formed, which has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0357] Note that the transistor 310 illustrated in FIG. 16 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or the driving method.

[0358] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0359] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 and the like are embedded in the insulators 320 and 322. A conductor 330 and the like are embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0360] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0361] The transistor 200 and the capacitor 460 are provided over the insulator 326. The structures of the layers in which the transistor 200 and the capacitor 460 are provided are the same as those described above and are indicated by the same hatching patterns and symbols. For detailed structures, refer to the above description. An insulator 285 is provided over the insulator 283, and a conductor 413 connected to the conductor 240a is provided over the insulator 285. The insulator 285 can be made of an insulating material that can be used for the insulator 216. The conductor 413 can be made of a conductive material that can be used for the conductor 242. In the example shown in FIG. 16, the opening 202a is provided not only in the insulators 275, 280, 282, and 283 but also in the insulator 285.

[0362] The capacitor 460 includes an oxide semiconductor 452, a conductor 242b1 over the oxide semiconductor 230 and the oxide semiconductor 452, an insulator 454 over the conductor 242b1, and a conductor 456 over the insulator 454. As shown in FIG. 16 and FIGS. 17A to 17C , the oxide semiconductor 452 has a structure similar to that of the oxide semiconductor 230 and can be formed in the same process. The conductor 242b1 is also used in the transistor 200. The insulator 454 has a structure similar to that of the insulator 250 and can be formed in the same process. The conductor 456 has a structure similar to that of the conductor 260 and can be formed in the same process. Specifically, the conductor 456 can include a conductor 456a and a conductor 456b over the conductor 456a. In this case, the conductor 456a has a structure similar to that of the conductor 260a and can be formed in the same process. Furthermore, the conductor 456b has a similar structure to the conductor 260b and can be formed in the same process.

[0363] Here, the capacitor 460 has a conductor 242b1 that functions as a first electrode, a conductor 456 that functions as a second electrode, and an insulator 454 that functions as a dielectric. That is, the capacitor 460 constitutes a metal-insulator-metal (MIM) capacitor.

[0364] The capacitor 460 has a structure similar to that of the transistor 200 and can be formed in parallel on the same formation surface as the transistor 200. Specifically, the insulator 275 and the insulator 280 have an opening 461 that overlaps with the oxide semiconductor 452. However, the capacitor 460 differs from the transistor 200 in that the conductor 242b1 overlaps with the opening 461. Therefore, the opening 461 reaches the conductor 242b1.

[0365] The insulator 454 overlaps with the conductor 242b1 and is provided inside the opening 461. Here, inside the opening 461, an insulator 455 is provided between the insulator 454 and the top surface of the conductor 242b1, the side surface of the conductor 242b2, the side surface of the insulator 275, and the side surface of the insulator 280. The insulator 455 has a similar structure to the insulator 255 and can be formed in the same process.

[0366] The insulator 455 is in contact with the top surface of the conductor 242b1 inside the opening 461. The insulator 454 is in contact with the top surface and side surfaces of the insulator 455 inside the opening 461. The conductor 456 is provided on the insulator 454 inside the opening 461.

[0367] 17C , the oxide semiconductor 452 of the capacitor 460 has a structure with a high aspect ratio, similar to the oxide semiconductor 230, and a plurality of oxide semiconductors 230 can be provided. Therefore, similar to the oxide semiconductor 230, the height of the oxide semiconductor 452 is larger than the width of the oxide semiconductor 452 in a certain cross-sectional view. Furthermore, the semiconductor device of one embodiment of the present invention has two or more regions where the oxide semiconductor 452 and the conductor 456 overlap in a plan view. Therefore, the area where the conductor 242b1, the insulator 454, and the conductor 456, which are provided along the top surface and side surface of the oxide semiconductor 452, face each other can be increased. This allows the capacitance to be increased without significantly increasing the area occupied by the capacitor 460.

[0368] 16 and 17A to 17C, the insulator 424 has a similar structure to the insulator 224 and can be formed in the same process. The insulator 224 and the insulator 424 are provided on the substrate 311, specifically, on the insulator 222. That is, the insulator 224 and the insulator 424 are provided on the same formation surface of the substrate 311.

[0369] The oxide semiconductor 452 has a structure similar to that of the oxide semiconductor 230 and can be formed in the same process. The oxide semiconductor 452 is provided over the insulator 424.

[0370] As described above, the thickness of the insulator 224 is preferably thicker than the thickness of the insulator 250 inside the opening 201. The insulator 424 has a structure similar to that of the insulator 224, and the insulator 454 has a structure similar to that of the insulator 250. For the above reasons, the thickness of the insulator 424 is preferably thicker than the thickness of the insulator 454. In this case, the bottom surface of the conductor 456 provided inside the opening 461 can be located below the bottom surface of the oxide semiconductor 452.

[0371] As described above, the side surface of the insulator 224 has a tapered shape. Therefore, the side surface of the insulator 424 can also have a tapered shape. Furthermore, the angle formed by the side surface of the oxide semiconductor 230 and the top surface of the insulator 224 is larger than the angle formed by the side surface of the insulator 224 and the top surface of the insulator 222. Therefore, the angle formed by the side surface of the oxide semiconductor 452 and the top surface of the insulator 424 can be larger than the angle formed by the side surface of the insulator 424 and the top surface of the insulator 222.

[0372] A conductor 458 is preferably provided in an opening 462 formed in the insulators 215, 216, 221, and 222. The conductor 458 can have a structure similar to that of the conductor 240, for example. The upper surface of the conductor 458 is in contact with the lower surface of the conductor 242b1 and can be connected to the conductor 330. Note that while only one conductor 458 is shown in FIG. 16 , this is not limiting, and two or more conductors may be used to connect the conductor 242b1 and the conductor 330. Furthermore, a configuration in which a portion of the conductor 242b1 is embedded in the opening 462 may also be used.

[0373] With the above-described structure, one of the source and drain of the transistor 200, one electrode of the capacitor 460, and the gate of the transistor 310 are connected to form a 2T1C memory cell. Note that a 1T1C memory cell can also be formed by using a configuration that does not include the transistor 310. Also, a 2T0C memory cell can be formed by using a configuration that does not include the capacitor 460.

[0374] Here, the transistor 310 is preferably provided so as to overlap with at least one of the transistor 200 and the capacitor 460. For example, the transistor 310 is preferably configured to overlap with the transistor 200. With such a configuration, the area occupied by the memory cell can be reduced.

[0375] 18A is a plan view showing a configuration example of a semiconductor device including a transistor 200 and a capacitor 460. FIG. 18B is a cross-sectional view of a portion indicated by a dashed dotted line C1-C2 in FIG. 18A . Here, FIGS. 18A and 18B show a configuration example of a memory cell 100 including a transistor 200 and a capacitor 460. Note that for the cross-sectional view of the portion indicated by a dashed dotted line D1-D2 in FIG. 18A , the cross-sectional view of the portion indicated by a dashed dotted line D3-D4, and the cross-sectional view of the portion indicated by a dashed dotted line D5-D6, refer to FIGS. 17A , 17B, and 17C , respectively.

[0376] 18A and 18B illustrate an example in which the oxide semiconductor 230 is provided over the insulator 224, and the insulators 255, 250, conductor 260, insulator 455, insulator 454, and conductor 456 are provided over the oxide semiconductor 230. That is, an example is illustrated in which the transistor 200 and the capacitor 460 share the oxide semiconductor 230. Also, an example is illustrated in which the insulator 224 overlaps not only with the transistor 200 but also with the capacitor 460. As described above, it is not necessary to separately pattern the oxide semiconductor 230 and the insulator 224 for the transistor 200 and the capacitor 460, and therefore the area occupied by the transistor 200 and the capacitor 460 can be reduced.

[0377] Although the structure shown in FIG. 16 illustrates a configuration in which the transistor 310 is formed on a silicon substrate, the present invention is not limited to this. For example, as shown in FIG. 19A , two transistors (hereinafter referred to as transistors 200a and 200b) having the same structure as the transistor 200 described above may be provided. Here, the transistors 200a and 200b are provided on the same formation surface, and their channel length directions intersect with each other. Note that the transistors 200a and 200b have the same structure as the transistor 200, and therefore, the components are indicated by the same hatched patterns and symbols. FIG. 19A illustrates an example in which the transistors 200a and 200b have the same structure as the transistor 200 shown in FIGS. 2C and 3A.

[0378] 19A , a capacitor 400 is provided on the insulator 285. The capacitor 400 includes a conductor 410 on the insulator 285, an insulator 430 on the conductor 410, and a conductor 420 on the insulator 430. The conductor 240b, the insulator 241b, the conductor 240c, and the insulator 241c are provided in contact with the bottom surface of the conductor 410. The conductor 240c and the insulator 241c are provided so as to be embedded in the opening 202c of the insulators 282, 283, and 285, and have the same structures as the conductor 240b and the insulator 241c. The bottom surface of the conductor 240c is in contact with the top surface of the conductor 260 of the transistor 200b. With this structure, one of the source and drain of the transistor 200a, one of the electrodes of the capacitor 400, and the gate of the transistor 200b are connected.

[0379] The capacitor 400 includes a conductor 410 that functions as a first electrode, a conductor 420 that functions as a second electrode, and an insulator 430 that functions as a dielectric. In other words, the capacitor 400 constitutes an MIM capacitor.

[0380] The conductor 410 and the conductor 420 can be formed using a conductive material that can be used for the conductor 260. For example, tungsten can be used for the conductor 410 and the conductor 420. Here, by using a structure in which the conductor 420 covers the conductor 410, the conductor 420 can function as the capacitor 400 on the side of the conductor 410. This increases the electrostatic capacitance of the capacitor 400. Furthermore, the conductor 413 can be formed simultaneously with the conductor 410.

[0381] Although the conductors 410, 413, and 420 each have a single-layer structure, the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a stacked structure of a conductor having barrier properties and a conductor with high conductivity may be used. For example, a stacked structure of titanium nitride and tungsten on titanium nitride may be used.

[0382] A high-k material is preferably used for the insulator 430 of the capacitor 400. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the insulator 430 can be made thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor 400. Furthermore, since the insulator 430 is formed to cover the conductor 410, it is preferable to form the insulator 430 using a film formation method with good coverage, such as an ALD method or a CVD method.

[0383] The insulator 430 may also have a stacked structure. It is preferable to use a stacked structure of a high-k material and a material with a higher dielectric strength than the high-k material. Examples of materials with a high dielectric strength (materials with a low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. The insulator 430 can have a stacked structure of aluminum oxide, which is a high-k material, and silicon oxide with a high dielectric strength on the aluminum oxide.

[0384] For example, the insulator 430 can be an insulator stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, for example, an insulator stacked in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. Alternatively, for example, an insulating film stacked in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By stacking and using an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor 400 can be suppressed.

[0385] Furthermore, a material that can have ferroelectricity may be used as the insulator 430. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO.Ｘ (X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of zirconium atoms to the number of element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0386] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0387] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0388] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0389] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulator 430 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0390] 19A, the shape of the capacitor 400 is a planar type, but the shape of the capacitor 400 in the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 400 may be a cylinder type or a pillar type.

[0391] An insulator 487 is provided to cover the capacitor 400, and an insulator 488 is provided to cover the insulator 487. The insulator 487 is preferably an insulator that has a function of capturing or fixing hydrogen. For example, aluminum oxide is preferably used for the insulator 487. The insulator 488 is preferably an insulator that has a function of suppressing diffusion of hydrogen. For example, silicon nitride, which has a higher barrier property against hydrogen, is preferably used for the insulator 488.

[0392] 19A illustrates a structure in which the transistors 200a and 200b are provided on the same surface, but the present invention is not limited to this. For example, as illustrated in FIG. 19B, a layer 401a including the transistor 200a may be stacked on a layer 401b including the transistor 200b. Note that the layers 401a and 401b have the same structure as the layers from the insulator 215 to the insulator 285 shown in FIG. 19A.

[0393] 19B , the conductor 240c and the insulator 241c can be formed in the openings 202c provided in the insulators 282 to 285 of the layer 401b and the insulators 215 to 285 of the layer 401a. With this structure, the conductor 410 of the capacitor 400 can be connected to the conductor 260 of the transistor 200b. Note that the conductor 410 and the conductor 260 of the transistor 200b do not need to be connected only by the conductor 240c. Two or more conductors may be used to connect the conductor 410 and the conductor 260 of the transistor 200b.

[0394] Here, the transistor 200b is preferably provided so as to overlap with at least one of the transistor 200a and the capacitor 400. For example, the oxide semiconductor 230 of the transistor 200b is preferably provided so as to overlap with at least one of the oxide semiconductor 230 of the transistor 200a and the conductor 410 of the capacitor 400. With such a structure, the area occupied by the memory cell can be reduced.

[0395] 20 is a plan view showing an example in which the memory cells 100 shown in FIG. 18A are arranged in a matrix of two rows and two columns. FIG. 21A is a cross-sectional view of the portion indicated by the dashed dotted line E1-E2 in FIG. 20. In FIG. 20, the memory cell 100 in the first row and first column, the memory cell 100 in the first row and second column, the memory cell 100 in the second row and first column, and the memory cell 100 in the second row and second column are respectively referred to as memory cell 100_11, memory cell 100_12, memory cell 100_21, and memory cell 100_22. Note that in FIG. 20, the oxide semiconductor 230, the conductor 260, the conductor 456, and the conductor 413 are hatched.

[0396] 20 and 21A, the transistors 200 included in the memory cell 100_11, the memory cell 100_12, the memory cell 100_21, and the memory cell 100_22 are respectively referred to as transistor 200_11, transistor 200_12, transistor 200_21, and transistor 200_22. The capacitors 460 included in the memory cell 100_11, the memory cell 100_12, the memory cell 100_21, and the memory cell 100_22 are respectively referred to as capacitor 460_11, capacitor 460_12, capacitor 460_21, and capacitor 460_22. Furthermore, the conductors 242b included in the memory cell 100_11, the memory cell 100_12, the memory cell 100_21, and the memory cell 100_22 will be referred to as the conductor 242b_11, the conductor 242b_12, the conductor 242b_21, and the conductor 242b_22, respectively.

[0397] 20 , in a plan view, the conductor 260, the insulator 250, and the insulator 255 have regions extending in the row direction. As a result, the transistors 200 in the same row share the conductor 260, the insulator 250, and the insulator 255, respectively. Therefore, the first gate electrodes of the transistors 200 in the same row are connected to each other.

[0398] Here, the conductor 260, the insulator 250, and the insulator 255 included in the transistors 200_11 and 200_12 are referred to as the conductor 260_1, the insulator 250_1, and the insulator 255_1, respectively. The conductor 260, the insulator 250, and the insulator 255 included in the transistors 200_21 and 200_22 are referred to as the conductor 260_2, the insulator 250_2, and the insulator 255_2, respectively. In FIG. 21A , the opening 201 where the conductor 260_1, the insulator 250_1, and the insulator 255_1 are provided is referred to as the opening 201_1, and the opening 201 where the conductor 260_2, the insulator 250_2, and the insulator 255_2 are provided is referred to as the opening 201_2.

[0399] 20 , in a plan view, the conductor 456, the insulator 454, and the insulator 455 have regions extending in the row direction. As a result, the capacitors 460 in the same row share the conductor 456, the insulator 454, and the insulator 455, respectively. Therefore, the second electrodes of the capacitors 460 in the same row are connected to each other. Note that the capacitors 460 in the same column may share the conductor 456, the insulator 454, and the insulator 455, respectively. Furthermore, for example, all the capacitors 460 may share the conductor 456.

[0400] Here, the conductor 456, the insulator 454, and the insulator 455 included in the capacitors 460_11 and 460_12 are referred to as conductor 456_1, insulator 454_1, and insulator 455_1, respectively. The conductor 456, the insulator 454, and the insulator 455 included in the capacitors 460_21 and 460_22 are referred to as conductor 456_2, insulator 454_2, and insulator 455_2, respectively. Furthermore, in FIG. 21A , the opening 461 where the conductor 456_1, the insulator 454_1, and the insulator 455_1 are provided is referred to as opening 461_1, and the opening 461 where the conductor 456_2, the insulator 454_2, and the insulator 455_2 are provided is referred to as opening 461_2. Note that, for example, the conductor 456_1 and the conductor 456_2 may be connected to each other. In this case, for example, the conductor 456_1 and the conductor 456_2 can be regarded as one conductor.

[0401] The memory cell 100_11 and the memory cell 100_21 share the insulator 224 and the oxide semiconductor 230. The memory cell 100_12 and the memory cell 100_22 share the insulator 224 and the oxide semiconductor 230. Here, the insulator 224 and the oxide semiconductor 230 included in the memory cell 100_11 and the memory cell 100_21 are referred to as the insulator 224_1 and the oxide semiconductor 230_1, respectively. The insulator 224 and the oxide semiconductor 230 included in the memory cell 100_12 and the memory cell 100_22 are referred to as the insulator 224_2 and the oxide semiconductor 230_2, respectively.

[0402] The transistors 200_11 and 200_21 share the conductor 242a. Similarly, the transistors 200_12 and 200_22 share the conductor 242a. Here, the conductor 242a included in the transistors 200_11 and 200_21 is referred to as conductor 242a_1. The conductor 242a included in the transistors 200_12 and 200_22 is referred to as conductor 242a_2.

[0403] 21A shows an example in which the conductors 242a_1, 242a_2, 242b_11, 242b_12, 242b_21, and 242b_22 each have a two-layer stacked structure. The lower layers of the conductors 242a_1 and 242a_2 (corresponding to the conductor 242a1) each have a region that protrudes toward the opening 201 more than the upper layers of the conductors 242a_1 and 242a_2 (corresponding to the conductor 242a2). The lower layers (corresponding to conductor 242b1) of conductor 242b_11, conductor 242b_12, conductor 242b_21, and conductor 242b_22 each have a region that protrudes toward the opening 201 more than the upper layers (corresponding to conductor 242b2) of conductor 242b_11, conductor 242b_12, conductor 242b_21, and conductor 242b_22.

[0404] In a cross-sectional view of the transistor 200_11 in the channel length direction, the distance between the lower layer of the conductor 242a_1 and the lower layer of the conductor 242b_11 is shorter than the distance between the upper layer of the conductor 242a_1 and the upper layer of the conductor 242b_11. In a cross-sectional view of the transistor 200_21 in the channel length direction, the distance between the lower layer of the conductor 242a_1 and the lower layer of the conductor 242b_21 is shorter than the distance between the upper layer of the conductor 242a_1 and the upper layer of the conductor 242b_21. Although not shown in FIG. 21A , in a cross-sectional view of the transistor 200_12 in the channel length direction, the distance between the lower layer of the conductor 242a_2 and the lower layer of the conductor 242b_12 is shorter than the distance between the upper layer of the conductor 242a_2 and the upper layer of the conductor 242b_12. Furthermore, in a cross-sectional view of the transistor 200_22 in the channel length direction, the distance between the lower layer of the conductor 242a_2 and the lower layer of the conductor 242b_22 is shorter than the distance between the upper layer of the conductor 242a_2 and the upper layer of the conductor 242b_22.

[0405] The above-described configuration can shorten the distance between the source and drain, thereby shortening the channel length. As a result, the frequency characteristics of the transistor 200 can be improved as described above. As a result, a semiconductor device with high operating speed can be provided.

[0406] The insulators 275, 280, 282, 283, and 285 are provided with an opening 202a reaching the conductor 242a_1 and an opening 202a reaching the conductor 242a_2, respectively. In FIG. 21A , the opening 202a reaching the conductor 242a_1 is referred to as an opening 202a_1. The insulator 241a and the conductor 240a provided inside the opening 202a_1 are referred to as an insulator 241a_1 and a conductor 240a_1, respectively. Furthermore, in FIG. 20 , the conductor 240a provided inside the opening 202a reaching the conductor 242a_2 is referred to as a conductor 240a_2.

[0407] In a plan view, the conductor 413 has a region extending in the column direction. This allows the conductors 242a included in the transistors 200 in the same column to be connected to each other. Here, in FIGS. 20 and 21A, the conductor 413 connected to the conductor 242a_1 and the conductor 240a_1 is referred to as the conductor 413_1. In addition, in FIG. 20, the conductor 413 connected to the conductor 242a_2 and the conductor 240a_2 is referred to as the conductor 413_2.

[0408] 20 and 21A , the oxide semiconductor 230 provided in the memory cell 100_11 and the oxide semiconductor 230 provided in the memory cell 100_21 are not separated but are provided as a continuous oxide semiconductor 230_1. Also, as shown in FIG. 20 , the oxide semiconductor 230 provided in the memory cell 100_12 and the oxide semiconductor 230 provided in the memory cell 100_22 are not separated but are provided as a continuous oxide semiconductor 230_2. In this manner, for example, when multiple memory cells 100 in adjacent rows share the oxide semiconductor 230, the memory cells 100 can be arranged at high density. This enables high integration of the semiconductor device. Furthermore, the manufacturing process of the semiconductor device can be simplified.

[0409] 21B is a cross-sectional view illustrating an example in which the oxide semiconductor 230_1 illustrated in Fig. 21A is separated into each memory cell 100. In Fig. 21B, the oxide semiconductor 230 included in the memory cell 100_11 is referred to as an oxide semiconductor 230_11, and the oxide semiconductor 230 included in the memory cell 100_21 is referred to as an oxide semiconductor 230_21.

[0410] 21B , by separating the oxide semiconductor 230 for each memory cell 100, it becomes easier to drive the transistors of each memory cell independently than when the oxide semiconductor 230 is shared by multiple memory cells 100 as shown in FIG. 21A . Furthermore, the reliability of each memory cell can be improved. On the other hand, when the oxide semiconductor 230 is shared by multiple memory cells 100 as shown in FIG. 21A , the memory cells 100 can be arranged at a higher density than when the oxide semiconductor 230 is separated for each memory cell 100 as shown in FIG. 21B .

[0411] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0412] <<Substrate>> Examples of substrates for forming transistors include insulating substrates, semiconductor substrates, and conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulator region within the semiconductor substrate, such as SOI (Silicon-On-Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductor substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0413] <<Insulators>> Examples of insulators that can be used for at least one of the insulators 215, 216, 221, 222, 223, 224, 241, 250, 255, 275, 280, 282, 283, 285, 315, 320, 322, 324, 326, 424, 430, 454, 455, 487, and 488 include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.

[0414] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for an insulator functioning as a gate insulator, such as insulator 250, enables lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for an insulator functioning as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0415] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0416] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0417] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0418] The insulator functioning as the gate insulator preferably has a region containing oxygen that is released by heating. For example, when silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with an oxide semiconductor, oxygen vacancies in the oxide semiconductor can be compensated for.

[0419] <<Conductor>> Examples of conductors that can be used for at least one of conductor 205, conductor 240, conductor 242, conductor 260, conductor 316, conductor 328, conductor 330, conductor 410, conductor 413, conductor 420, conductor 456, and conductor 458 include metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-mentioned metal elements, and alloys combining the above-mentioned metal elements. Furthermore, examples of conductors include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Also, semiconductors with high conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0420] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0421] When an oxide is used for the channel formation region of a transistor, a conductor that functions as a gate electrode, such as the conductor 260, preferably has a stacked structure in which a material containing the metal element described above and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is more easily supplied to the channel formation region.

[0422] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0423] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below. Here, the case of manufacturing the semiconductor device illustrated in FIGS. 1A to 3B will be described as an example.

[0424] Unless otherwise specified, A in each figure represents a plan view. B, C, and D in each figure represent cross-sectional views corresponding to the portions indicated by dashed dotted lines A1-A2, A3-A4, and A5-A6 in A of each figure, respectively, and are also cross-sectional views in the channel width direction of the transistor 200. E in each figure represents a cross-sectional view of the portion indicated by dashed dotted line B1-B2 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200.

[0425] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0426] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0427] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0428] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0429] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0430] The CVD method and the ALD method are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0431] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases while depositing the film. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when depositing a film using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0432] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0433] First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see FIGS. 22A to 22E ). As described above, the insulator 215 can be formed using an insulator similar to one or a stack of the insulators 282 and 283. The insulator 215 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0434] Next, the insulator 216 is formed over the insulator 215. The insulator 216 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the formation of the insulator 216 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is formed as the insulator 216 by a sputtering method.

[0435] The insulators 215 and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen content and further reduces hydrogen contamination between film formation steps.

[0436] 14A to 14D can be formed by forming an opening 203 in the insulator 216 that reaches the insulator 215 and forming a conductor 205 inside the opening 203. The conductor 205 can be formed by depositing a conductive film that can be used for the conductor 205 so as to fill the opening 203 and removing part of the conductive film by CMP treatment.

[0437] Next, an insulator 221 is formed over the insulator 216 (see FIGS. 22A to 22E).

[0438] The insulator 221 can be formed using any of the above insulators that have barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon nitride film is formed as the insulator 221 by a PEALD method.

[0439] Next, the insulator 222 is formed over the insulator 221 (see FIGS. 22A to 22E).

[0440] The insulator 222 may be an insulator containing one or both of an oxide of aluminum and hafnium. As the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or hafnium aluminate is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the transistor through the insulator 222, and thus oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0441] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a hafnium oxide film is formed as the insulator 222 by a thermal ALD method.

[0442] In this embodiment, silicon nitride is deposited as the insulator 221 by a PEALD method, and hafnium oxide is deposited as the insulator 222 by a thermal ALD method. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 221 in this manner, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has a function of capturing or fixing hydrogen, for the insulator 222, hydrogen contained in the oxide semiconductor 230 can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0443] Next, the insulator 223 is formed over the insulator 222 (see FIGS. 22A to 22E ). The insulator 223 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 223 is an insulator that will become the insulator 224 in a later process. It is preferable to form a film having a high barrier property against hydrogen, such as silicon nitride or silicon nitride oxide, as the insulator 223 because, for example, hydrogen can be prevented from diffusing from a base insulator to the oxide semiconductor 230.

[0444] Next, the insulator 223 is processed so that the top surface of the insulator 222 is not exposed. As a result, convex portions 206 are formed in the insulator 223 (see FIGS. 23A to 23E ). The convex portions 206 of the insulator 223 function as a template for forming the oxide semiconductor 230. The convex portions 206 are also called pillars.

[0445] The insulator 223 can be processed using lithography. Specifically, a mask is formed on the insulator 223, and half etching is performed to form the convex portions 206 on the insulator 223. For example, dry etching can be used for half etching. Processing using dry etching is suitable for fine processing. In this embodiment, two convex portions 206 are formed as shown in FIGS. 23A to 23C.

[0446] 23B and 23C , the convex portion 206 is formed on the insulator 223 so that the angle θ3 formed between the upper surface of the insulator 223 in a region other than the convex portion 206 (also referred to as the bottom surface of the convex portion 206 or the bottom surface of the pillar) and the side surface of the convex portion 206 is larger than the angle θ1 formed between the side surface of the insulator 224 and the upper surface of the insulator 222 shown in FIG. 4A . The angle θ3 is preferably 90° or close to 90°. The angle θ3 is preferably, for example, 80° or more and 100° or less, and more preferably 85° or more and 95° or less.

[0447] By making the angle θ3 larger than the angle θ1, the angle θ2 formed by the side surface of the oxide semiconductor 230 and the top surface of the insulator 224 shown in FIG. 4A can be made larger than the angle θ1. For example, by making the angle θ3 90° or approximately 90°, the angle θ2 can be made 90° or approximately 90°. This can prevent the oxide semiconductor 230 from being defective in shape. For example, in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230 can be prevented from bending near the bottom surface of the protrusion 206. Therefore, semiconductor devices can be manufactured with a high yield. Furthermore, highly reliable semiconductor devices can be manufactured.

[0448] Here, for example, when a pillar is formed by processing the insulator 223 until the top surface of the insulator 222 is exposed, not only the insulator 223 but also the insulator 222 may be processed. As a result, even if the insulator 223 is processed under conditions such that the angle between the side surface of the insulator 223 and the top surface of the insulator 222 is 90° or approximately 90°, the side surface of the insulator 222 may be tapered if, for example, the material used for the insulator 222 is different from the material used for the insulator 223. As a result, part of the side surface of the pillar, specifically the side surface of the insulator 222 in a region that functions as a pillar, may be tapered, which may cause a shape defect in the oxide semiconductor 230 formed in contact with the side surface of the pillar. Specifically, in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230 may bend near the interface between the insulator 222 and the insulator 223. On the other hand, when a pillar is formed by half-etching the insulator 223, it is not necessary to process, for example, multiple layers made of different materials. Therefore, the side surface of the pillar can be prevented from becoming tapered near the bottom surface of the pillar, i.e., the base of the pillar can be prevented from becoming wider. This allows semiconductor devices to be manufactured with high yield and high reliability.

[0449] The insulator 223 may have a stacked structure of two or more layers. For example, it can have a stacked structure of two or more layers formed using different film formation methods. For example, it can have a two-layer stacked structure of a layer formed using an ALD method and a layer formed on the layer formed using a sputtering method. In this case, it is preferable to use the same material for the layer formed using the ALD method and the layer formed using the sputtering method. For example, it is preferable to use silicon nitride or silicon nitride oxide for both the layer formed using the ALD method and the layer formed using the sputtering method. Note that different materials may be used for each layer of the insulator 223. In this case, it is preferable to form the convex portion 206 in the insulator 223 by processing only the top layer of the insulator 223, as this makes it easier to make the angle θ3 90° or close to 90°.

[0450] 22A to 22E , the thickness of the insulator 223 and the height of the convex portion 206, i.e., the distance between the bottom surface of the convex portion 206 and the top surface of the convex portion 206, can be determined based on the design values ​​of the height H of the oxide semiconductor 230 and the thickness t1 of the insulator 224 shown in FIG. 4A . For example, the thickness of the insulator 223 corresponds to the sum of the thickness t1 and the height H. The height of the convex portion 206 corresponds to the height H. Note that the height of the convex portion 206 can also be referred to as the depth of half-etching of the insulator 223.

[0451] Next, an oxide semiconductor film 230f that will become the oxide semiconductor 230 is formed to cover the insulator 223 (see FIGS. 24A to 24E ). The oxide semiconductor film 230f is a metal oxide film that will become the oxide semiconductor 230 in a later step, and any of the above-described metal oxide films can be used. The oxide semiconductor film 230f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0452] Since the oxide semiconductor film 230f is formed along the convex portions 206 of the insulator 223, it is preferable that the oxide semiconductor film 230f has good coverage. Therefore, it is preferable that the oxide semiconductor film 230f is formed by an ALD method or the like, which has good coverage. Furthermore, it is preferable that the oxide semiconductor 230 has a high aspect ratio. Therefore, it is preferable that the oxide semiconductor film 230f has a thin film thickness. Therefore, it is preferable that the oxide semiconductor film 230f is formed by an ALD method, which allows for adjustment of the film thickness to a thin film thickness. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed in contact with the top surface and side surface of the insulator 223.

[0453] Here, the oxide semiconductor film 230f is preferably formed by the same method as the above-described method for forming the oxide semiconductor 30. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f and the oxide semiconductor 230 can be formed so as to adequately cover, for example, the protrusions 206 of the insulator 223.

[0454] For example, as shown in FIGS. 4A and 4B , when the oxide semiconductor 230 has a three-layer structure including oxide semiconductors 230a to 230c, films to be the oxide semiconductors 230a and 230c can be deposited by an ALD method, and a film to be the oxide semiconductor 230b can be deposited by a sputtering method. Specifically, the film to be the oxide semiconductor 230a can be deposited to have a composition of In:Zn=2:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230a. The film to be the oxide semiconductor 230b can be deposited using an oxide target having a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout. Alternatively, the film to be the oxide semiconductor 230c can be deposited to have a composition of In:Zn=2:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230c. The three-layer structure of the oxide semiconductors 230a to 230c is not limited to the above structure. For example, the oxide semiconductors 230a to 230c may be formed by an ALD method. In this structure, the oxide semiconductors 230a to 230c can be successively formed using a single manufacturing apparatus without using a sputtering method, thereby reducing manufacturing costs. After the oxide semiconductors 230a, 230b, and 230c are formed, microwave treatment may be performed on each of them. The microwave treatment can improve the crystallinity of the oxide semiconductor 230.

[0455] Next, heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230f does not become polycrystallized. The heat treatment of the oxide semiconductor film 230f can be performed by the same method as the heat treatment of the oxide semiconductor 30 described above.

[0456] For example, the heat treatment can be carried out at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0457] By forming the oxide semiconductor 230 using the above method and then performing heat treatment, the oxide semiconductor 230 can be converted into an AG CAAC. As a result, the on-state current, the S value, the field-effect mobility, the frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0458] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0459] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f and the like as much as possible. Note that highly purified gas can also be used in the heat treatment before and after this step.

[0460] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor film 230f, reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0461] Furthermore, by performing heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, and oxygen vacancies in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0462] Furthermore, by the heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulator 223 and is absorbed into the insulator 223. In other words, hydrogen in the oxide semiconductor film 230f diffuses into the insulator 223. Therefore, the hydrogen concentration in the insulator 223 increases, but the hydrogen concentration in each oxide semiconductor film 230f decreases. Note that by providing the insulator 221 under the insulator 223, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0463] In particular, the oxide semiconductor film 230f (later the oxide semiconductor 230) functions as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f in which the hydrogen concentration is reduced has high reliability, which is preferable.

[0464] Note that it is preferable to perform a treatment for increasing the crystallinity of the oxide semiconductor film 230f during or after the formation of the oxide semiconductor film 230f. Examples of the treatment for increasing the crystallinity of the oxide semiconductor film 230f include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0465] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor film 230f multiple times during the formation of the oxide semiconductor film 230f. For example, when the oxide semiconductor film 230f is formed by an ALD method, it is preferable to perform a microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity after each oxide semiconductor film 230f having a thickness within a predetermined range, which can improve productivity. Specifically, it is preferable to form a first oxide semiconductor film having a thickness of 1 nm to 10 nm as the oxide semiconductor film 230f, perform the first microwave plasma treatment, and then form a second oxide semiconductor film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the methods for forming the first oxide semiconductor film and the second oxide semiconductor film are not particularly limited, and ALD or sputtering can be used for each. In particular, forming the first oxide semiconductor film by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed into the first oxide semiconductor film and the second oxide semiconductor film. This is particularly suitable when the elements contained in the layers constituting the formation surface inhibit crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Although a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is illustrated here, the present invention is not limited to this. The oxide semiconductor film 230f can be formed as a single layer or a stacked structure of three or more layers.

[0466] Furthermore, treatment for increasing the crystallinity of the oxide semiconductor film 230f may be performed after the oxide semiconductor film 230f is formed. Specifically, this treatment may be performed directly on the formed oxide semiconductor film 230f, or may be performed via another film, such as an insulating film, formed on the oxide semiconductor film 230f. For example, microwave plasma treatment may be performed after the oxide semiconductor film 230f is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like) may be formed after the oxide semiconductor film 230f is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor film 230f via the insulating film.

[0467] Note that the above-described treatment for increasing the crystallinity of the oxide semiconductor film 230f can also serve as treatment for removing impurities contained in the oxide semiconductor film 230f. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor film 230f can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor film 230f in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor film 230f can be reduced.

[0468] When the treatment for increasing the crystallinity of the oxide semiconductor film 230f is performed, the substrate temperature is preferably set to room temperature (for example, 25° C.) or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably set to 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0469] By increasing the crystallinity of the oxide semiconductor film 230f, a highly reliable transistor can be realized.

[0470] 25A , after the layer 231 is formed to cover the insulator 223, the oxide semiconductor film 230f may be formed over the layer 231. This prevents the oxide semiconductor film 230f from contacting the insulator 223. Therefore, impurities can be prevented from being mixed into the oxide semiconductor film 230f. For example, elements (such as silicon) that constitute the insulator 223 and impurities (such as hydrogen) contained in the insulator 223 can be prevented from being mixed into the oxide semiconductor film 230f. Therefore, forming the layer 231 can improve the reliability of the transistor 200 in some cases. Note that FIG. 25A is a cross-sectional view taken along the A1-A2 direction.

[0471] The layer 231 preferably contains an element contained in the oxide semiconductor film 230f. For example, the layer 231 preferably contains one or both of gallium and zinc. The layer 231 preferably contains one or both of gallium oxide and zinc oxide. This can suppress changes in the electrical characteristics of the transistor 200 due to impurities being mixed into the oxide semiconductor film 230f. For example, even when silicon oxide, silicon nitride, or the like is used for the insulator 223, it can suppress silicon from being mixed into the oxide semiconductor film 230f, which makes it difficult to form a CAAC structure in the oxide semiconductor film 230f. Therefore, the reliability of the transistor 200 can be improved.

[0472] The thickness of the layer 231 is preferably equal to or less than the thickness of the oxide semiconductor film 230f, because this enables miniaturization of the transistor 200. The thickness of the layer 231 is, for example, preferably 0.01 nm to 100 nm, more preferably 0.01 nm to 50 nm, still more preferably 0.01 nm to 20 nm, still more preferably 0.01 nm to 10 nm, still more preferably 0.1 nm to 10 nm, and still more preferably 1 nm to 10 nm. In order to form such a thin layer 231 so as to cover, for example, the protrusions 206 of the insulator 223 with good coverage, the layer 231 is preferably formed by an ALD method. Note that the layer 231 may be formed by a sputtering method, a CVD method, an MBE method, or a PLD method, for example.

[0473] 25B illustrates an example in which the layer 231 has a stacked structure of a layer 231a and a layer 231b over the layer 231a. The layer 231a can be made of the same material as that of the layer 231 illustrated in FIG. 25A. For example, gallium oxide or zinc oxide can be used for the layer 231a.

[0474] The layer 231b preferably contains a metal element contained in the oxide semiconductor film 230f. The layer 231b preferably contains an oxide containing a metal element contained in the oxide semiconductor film 230f but not contained in the layer 231a. For example, when indium gallium zinc oxide is used as the oxide semiconductor film 230f and gallium oxide or zinc oxide is used as the layer 231a, the layer 231b preferably contains indium zinc oxide. In this case, the layer 231b may have a composition of In:Zn=2:1 (atomic ratio) or a composition therearound. Alternatively, the layer 231b may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound.

[0475] The thickness of layer 231a can be within the range of thickness that can be assumed by layer 231 shown in Fig. 25A. The thickness of layer 231 can be, for example, 0.01 nm to 100 nm, preferably 0.01 nm to 10 nm, more preferably 0.1 nm to 10 nm, even more preferably 0.1 nm to 5 nm, still more preferably 0.1 nm to 3 nm, even more preferably 0.1 nm to 2 nm, and even more preferably 0.1 nm to 1 nm.

[0476] The thickness of the layer 231b can be, for example, thicker than the thickness of the layer 231a. The thickness of the layer 231b can be, for example, 0.1 nm to 200 nm, preferably 0.1 nm to 100 nm, more preferably 0.1 nm to 50 nm, even more preferably 0.1 nm to 20 nm, still more preferably 0.1 nm to 10 nm, even more preferably 1 nm to 7 nm, even more preferably 1 nm to 5 nm, and even more preferably 1 nm to 3 nm.

[0477] 25A , the layer 231a and the layer 231b can be formed by the same method as that used to form the layer 231. In particular, the layer 231a and the layer 231b are preferably formed by an ALD method, because the layer 231a and the layer 231b can be formed to cover the protrusion 206 of the insulator 223 with good coverage.

[0478] It is preferable to perform microwave plasma treatment after the formation of the layers 231a and 231b and before the formation of the oxide semiconductor film 230f. This allows the components contained in the layer 231a and the layer 231b to be alloyed. For example, when gallium oxide is used for the layer 231a and indium zinc oxide is used for the layer 231b, the alloyed region can contain indium gallium zinc oxide. This can prevent impurities from being mixed into the oxide semiconductor film 230f, which can cause variations in the electrical characteristics of the transistor 200. For example, the introduction of impurities into the oxide semiconductor film 230f may be more easily prevented than in the example shown in FIG. 25A . In this case, even when silicon oxide, silicon nitride, or the like is used for the insulator 223, the introduction of silicon into the oxide semiconductor film 230f, which can prevent a CAAC structure from being formed in the oxide semiconductor film 230f, can be further prevented. Therefore, the reliability of the transistor 200 can be further improved.

[0479] A thick alloyed region is preferable because, for example, impurities may be more easily prevented from being mixed into the oxide semiconductor film 230f. The thickness of the alloyed region is preferably 5% to 100%, more preferably 10% to 100%, still more preferably 30% to 100%, and even more preferably 50% to 100% of the film thickness of the layer 231. The thickness of the alloyed region can be, for example, 0.1 nm to 0.5 nm.

[0480] Note that the layer 231b can be regarded as the oxide semiconductor 30a in some cases. In this case, a layer of the oxide semiconductor film 230f that is in contact with the layer 231b can be regarded as the oxide semiconductor 30b.

[0481] When the microwave plasma treatment is performed after the formation of the layers 231a and 231b and before the formation of the oxide semiconductor film 230f, the substrate is preferably heated. The heating temperature of the substrate is from room temperature (e.g., 25° C.) to 500° C., preferably from 100° C. to 500° C., more preferably from 200° C. to 500° C., and still more preferably from 250° C. to 450° C. The power of a power source that applies microwaves in the microwave plasma treatment apparatus is preferably from 1,000 W to 10,000 W, more preferably from 2,000 W to 5,000 W.

[0482] 25A , when the layer 231 is formed to cover the insulator 223 and then the oxide semiconductor film 230f is formed over the layer 231, the transistor 200 to be manufactured has the structure shown in FIG 15A . On the other hand, when the layer 231 has a stacked-layer structure of a layer 231a and a layer 231b over the layer 231a as shown in FIG 25B , the transistor 200 to be manufactured has the structure shown in FIG 15B .

[0483] Next, a portion of the oxide semiconductor film 230f is removed by anisotropic etching (see FIGS. 26A to 26E ). Specifically, the oxide semiconductor film 230f is processed by anisotropic etching until the top surface of the insulator 223 is exposed, thereby removing the portion of the oxide semiconductor film 230f. The oxide semiconductor film 230f is etched mainly in a region parallel to the substrate surface, and a sidewall-shaped oxide semiconductor 230 is formed in contact with the side surface of the protrusion 206 of the insulator 223. Note that when removing the portion of the oxide semiconductor film 230f by anisotropic etching, an insulator serving as a hard mask may be provided in the portion. Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be suitably used as the insulating film.

[0484] Anisotropic etching can form the oxide semiconductor 230 with a high aspect ratio. By using the oxide semiconductor 230, the channel width of the transistor 200 can be increased without increasing the occupation area. Therefore, the on-state current and frequency characteristics of the transistor 200 can be improved. Furthermore, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the occupation area, thereby improving the on-state current and frequency characteristics of the transistor 200.

[0485] 26A , the oxide semiconductor 230 has a circumferential shape in a plan view. The oxide semiconductor 230 can also be said to have a shape having an opening in the center. When the oxide semiconductor 230 has a three-layer structure including the oxide semiconductors 230a to 230c as described above, the circumferential oxide semiconductor 230 is formed in this order, with the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c positioned around the convex portion 206 of the insulator 223. Therefore, as shown in FIG. 8A , in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged symmetrically in this order.

[0486] Although the above description has been given of a configuration in which two circumferential oxide semiconductors 230 are formed, the present invention is not limited to this. For example, one or three or more circumferential oxide semiconductors 230 may be formed. Furthermore, the circumferential oxide semiconductors 230 may be joined to form an oxide semiconductor 230 having a shape with multiple openings. For example, as shown in FIG. 5A , the oxide semiconductor 230 may have a shape in which three openings are arranged in the A1-A2 direction in a planar view. In this case, for example, three convex portions 206 are formed adjacent to each other at a short distance in the steps shown in FIGS. 23A to 23E . Furthermore, for example, as shown in FIG. 5B , the oxide semiconductor 230 may have a lattice shape in a planar view. In this case, for example, a lattice-shaped groove is formed in the insulator 223 in the steps shown in FIGS. 23A to 23E .

[0487] 26A , the oxide semiconductor 230 has a circumferential structure in plan view, but etching may be further performed to remove a portion of the oxide semiconductor 230. For example, in the structure shown in FIG. 26A , by removing a portion, the oxide semiconductor 230 can be made to have a rectangular shape extending in the B1-B2 direction in plan view.

[0488] The anisotropic etching of the oxide semiconductor film 230f is preferably performed by dry etching.

[0489] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３ Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing no halogen gas but hydrocarbon gas or hydrogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0490] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. The DF-CCP etching apparatus may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus. The etching apparatus can be appropriately configured according to the object to be etched. In the above-mentioned dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thereby enabling highly anisotropic etching.

[0491] 25A or 25B , not only a part of the oxide semiconductor film 230f but also a part of the layer 231 is removed by anisotropic etching. Specifically, the oxide semiconductor film 230f and the layer 231 are processed by anisotropic etching until the top surface of the insulator 223 is exposed, for example, thereby removing a part of the oxide semiconductor film 230f and a part of the layer 231. In this case, the layer 231 has a sidewall-like structure in contact with the side surface of the protrusion 206 of the insulator 223, and a sidewall-like oxide semiconductor 230 is formed outside the layer 231.

[0492] Next, the insulator 223 is processed to remove a part of a region that does not overlap with the oxide semiconductor 230. As a result, the insulator 224 is formed to have a region that overlaps with the oxide semiconductor 230 (see FIGS. 27A to 27E and FIGS. 28A to 28E ). The insulator 223 can be processed using the oxide semiconductor 230 as a mask, for example.

[0493] 27A to 27E show an example in which part of the top surface of the insulator 222 is exposed, but the insulator 223 remains in the region where the convex portion 206 was formed, i.e., the region that overlaps with the opening in the hollow oxide semiconductor 230 in a plan view. 27A to 27E show an example in which, in a cross-sectional view, the position of the top surface of the insulator 223 is lower than the position of the top surface of the oxide semiconductor 230. This state is a state in which the convex portion 206 of the insulator 223 has been removed, i.e., a state in which the pillar has been removed.

[0494] 28A to 28E show an example in which the insulator 223 is further processed from the state shown in FIGS. 27A to 27E to form an insulator 224. The insulator 224 is formed so that the angle θ1 formed by the side surface of the insulator 224 and the top surface of the insulator 222 is less than 90°. That is, the insulator 224 is formed so that the side surface has a tapered shape. Therefore, the insulator 224 can be formed so that the area of ​​the bottom surface is larger than the area of ​​the top surface. As a result, the insulator 224 can be prevented from falling. Therefore, the oxide semiconductor 230 on the insulator 224 can also be prevented from falling. This allows semiconductor devices to be manufactured with a high yield.

[0495] As described above, the smaller the angle θ1, the larger the area of ​​the lower surface of the insulator 224 can be relative to the area of ​​the upper surface of the insulator 224. This makes it possible to preferably prevent the insulator 224 from tipping over. On the other hand, it is easier to process the insulator 223 so that the angle θ1 is closer to 90° than to process the insulator 223 so that the angle θ1 is smaller. As described above, the angle θ1 can be set to be equal to or greater than 45° and less than 90°, preferably equal to or greater than 60° and less than 90°, and more preferably equal to or greater than 60° and less than 80°.

[0496] As shown in FIG. 4A , the oxide semiconductor 230 can be formed so that the angle θ2 formed by the side surface of the oxide semiconductor 230 and the top surface of the insulator 224 is larger than the angle θ1. For example, the oxide semiconductor 230 can be formed so that the angle θ2 is 90° or approximately 90°. This can prevent the oxide semiconductor 230 from being deformed. For example, in a cross-sectional view of the transistor 200 in the channel width direction, the oxide semiconductor 230 can be prevented from bending near the insulator 224. As described above, by forming the protrusion 206 so that the angle θ3 shown in FIGS. 23B and 23C is larger than the angle θ1, the oxide semiconductor 230 can be formed so that the angle θ2 is larger than the angle θ1. For example, by forming the protrusion 206 so that the angle θ3 is 90° or approximately 90°, the oxide semiconductor 230 can be formed so that the angle θ2 is 90° or approximately 90°.

[0497] The processing of the insulator 223, that is, removal of part of the region of the insulator 223 that does not overlap with the oxide semiconductor 230, is preferably performed by etching using a gas containing carbon, such as dry etching. As a result, carbon adheres to the side surface of the insulator 224, and reaction products are deposited, which makes it easier to form the side surface of the insulator 224 into a tapered shape. A hydrocarbon gas can be used as the carbon-containing gas. For example, methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ As the carbon-containing gas, a gas containing one or more of fluorine, chlorine, and bromine can be used. For example, C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ gas, and CCl ４ One or more of the gases may be used.

[0498] For example, dry etching can be used to process the insulator 223. Dry etching is suitable for fine processing. The above description can be referred to for the conditions of the dry etching and the dry etching apparatus.

[0499] When processing the insulator 223, the insulator 222 below the insulator 223 may also be processed. In this case, the film thickness of the region of the insulator 222 that does not overlap with the insulator 224 may be thinner than the film thickness of the region of the insulator 222 that overlaps with the insulator 224.

[0500] 26A to 26C show an example in which two convex portions 206 of the insulator 223 and two oxide semiconductors 230 are formed for one transistor 200, but the present invention is not limited thereto. As shown in the cross-sectional view of FIG. 29A , two transistors (transistor 200_1 and transistor 200_2) may each have two convex portions 206 of the insulator 223 and two oxide semiconductors 230. As shown in the cross-sectional view of FIG. 29B , convex portions 206 with different widths may be formed, and three fin-shaped oxide semiconductors 230 may be formed for each of the transistors 200_1 and 200_2 in the cross section viewed in the A1-A2 direction. In this case, part of the oxide semiconductor 230 is removed so that the shape in a plan view becomes a straight line extending in the B1-B2 direction, thereby separating the oxide semiconductor 230 of the transistor 200_1 from the oxide semiconductor 230 of the transistor 200_2.

[0501] Next, a conductive film 242f1 is formed over the insulator 222 and the oxide semiconductor 230, and a conductive film 242f2 is formed over the conductive film 242f1 (see FIGS. 30A to 30E ). The conductive film 242f1 can be formed using a conductor corresponding to the above-described conductor 242a1 and conductor 242b1. The conductive film 242f2 can be formed using a conductor corresponding to the above-described conductor 242a2 and conductor 242b2. Note that hereinafter, the conductive films 242f1 and 242f2 may be collectively referred to as conductive films 242f.

[0502] The conductive films 242f1 and 242f2 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, tantalum nitride can be formed as the conductive film 242f1 by a sputtering method. Tungsten can be formed as the conductive film 242f2 by a sputtering method. By forming the conductive film 242f to cover the oxide semiconductor 230, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the occupation area. This can improve the on-state current and frequency characteristics of the transistor 200.

[0503] Next, the conductive film 242f2 is processed into an island shape by lithography to form the conductor 242A2, and the conductive film 242f1 is processed into an island shape to form the conductor 242A1 (see FIGS. 31A to 31E). Note that, hereinafter, the conductors 242A1 and 242A2 may be collectively referred to as the conductor 242A.

[0504] The conductor 242A is preferably formed to cover the oxide semiconductor 230 and the insulator 224. The conductor 242A1 can be formed to be in contact with the oxide semiconductor 230. Furthermore, the insulator 222 is exposed in a region that does not overlap with the conductor 242A.

[0505] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus.

[0506] The side surface of the conductor 242A may be configured to be perpendicular or approximately perpendicular to the upper surface of the insulator 222. By using such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors.

[0507] However, the present invention is not limited to the above, and the side surface of the conductor 242A may have a tapered shape. The taper angle of the side surface of the conductor 242A may be, for example, 60° or more and less than 90°. By tapering the side surface in this manner, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0508] In the lithography method, first, a resist is exposed through a mask. Next, the exposed region is removed or left using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, insulator, or the like to be p...

Claims

a first insulator, a second insulator, and a transistor; the transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, and a third insulator; the first insulator is provided on a substrate; the oxide semiconductor is provided on the first insulator, the first conductor and the second conductor are provided on the oxide semiconductor; the second insulator is provided on the first conductor and the second conductor; the second insulator has an opening overlapping a region between the first conductor and the second conductor in the oxide semiconductor in a plan view; the third insulator is provided inside the opening so as to have a region in contact with the oxide semiconductor; the third conductor is provided on the third insulator within the opening, an upper end of the first insulator and a lower end of the oxide semiconductor are aligned or approximately aligned; an area of ​​a lower surface of the first insulator is larger than an area of ​​an upper surface of the first insulator and an area of ​​a lower surface of the oxide semiconductor; In a cross-sectional view of the transistor in a channel width direction, a bottom surface of the third conductor is provided below a lower surface of the oxide semiconductor, A semiconductor device in which, in a cross-sectional view in a channel width direction of the transistor, a height of the oxide semiconductor is greater than a width of the oxide semiconductor. 　 a first insulator, a second insulator, and a transistor; the transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, and a third insulator; the first insulator is provided on the underlying insulator; the oxide semiconductor is provided on the first insulator, the first conductor and the second conductor are provided on the oxide semiconductor; the second insulator is provided on the first conductor and the second conductor; the second insulator has an opening overlapping a region between the first conductor and the second conductor in the oxide semiconductor in a plan view; the third insulator is provided inside the opening so as to have a region in contact with the oxide semiconductor; the third conductor is provided on the third insulator within the opening, an upper end of the first insulator and a lower end of the oxide semiconductor are aligned or approximately aligned; a first angle formed by a side surface of the first insulator and a top surface of the underlying insulator is less than 90° in a cross-sectional view of the transistor in a channel width direction; In a cross-sectional view of the transistor in a channel width direction, a bottom surface of the third conductor is provided below a lower surface of the oxide semiconductor, A semiconductor device in which, in a cross-sectional view in a channel width direction of the transistor, a height of the oxide semiconductor is greater than a width of the oxide semiconductor. 　 In claim 2, In a cross-sectional view of the transistor in a channel width direction, a second corner formed by a side surface of the oxide semiconductor and a top surface of the first insulator is larger than the first corner. 　 In claim 3, The second angle is greater than or equal to 85° and less than or equal to 95°. 　 In any one of claims 1 to 4, When viewed in a cross section of the transistor in a channel width direction, a width of the oxide semiconductor is 2 nm to 20 nm. In a cross-sectional view of the transistor in a channel width direction, the height of the oxide semiconductor is 1.5 to 10 times the width of the oxide semiconductor. 　 In claim 1, the oxide semiconductor contains indium; the oxide semiconductor is formed perpendicular or substantially perpendicular to a surface of the substrate; A semiconductor device in which bright points arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in cross-sectional observation of the oxide semiconductor using a transmission electron microscope. 　 In claim 1, the oxide semiconductor contains indium; the oxide semiconductor is formed perpendicular or substantially perpendicular to a surface of the substrate; the oxide semiconductor has a first region, a second region in contact with the first region, and a third region in contact with the second region; A semiconductor device in which, when a cross-section of the oxide semiconductor is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in each of the first region, the second region, and the third region. 　 In claim 7, the second region comprises zinc; the second region has crystals; The c-axis of the crystal is approximately parallel to a normal direction to a side surface of the oxide semiconductor. 　 In claim 7, a content of indium in the first region is higher than a content of indium in the second region; The semiconductor device, wherein the third region has a higher indium content than the second region. 　 forming a first insulator on the underlying insulator; forming a convex portion on the first insulator by processing the first insulator so that an upper surface of the base insulator is not exposed; forming an oxide semiconductor film to cover the first insulator; The oxide semiconductor film is processed by anisotropic etching until a top surface of the first insulator is exposed, thereby forming an oxide semiconductor in contact with a side surface of the protrusion; forming the second insulator by removing a portion of a region of the first insulator that does not overlap with the oxide semiconductor such that a first angle formed by a side surface of the second insulator and an upper surface of the underlying insulator is less than 90°; forming a first conductor covering the oxide semiconductor and the second insulator; forming a third insulator on the first conductor; forming an opening in the third insulator that overlaps with the oxide semiconductor by processing the third insulator; forming a second conductor and a third conductor that face each other across the opening in a plan view by processing the first conductor; forming a fourth insulator in contact with the oxide semiconductor and the second insulator inside the opening; The method for manufacturing a semiconductor device further comprises forming a fourth conductor on the fourth insulator so as to fill the opening. 　 In claim 10, A method for manufacturing a semiconductor device, comprising forming a convex portion on a first insulator so that a second angle formed by an upper surface of the first insulator in a region other than the convex portion and a side surface of the convex portion is 85° or greater and 95° or less. 　 In claim 10 or 11, a region of the first insulator that does not overlap with the oxide semiconductor is partially removed by etching using a gas containing carbon;

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