Semiconductor device

Abstract

This semiconductor device includes: a chip that has a main surface; a semiconductor region of a first conductivity type that is formed in a surface layer section of the main surface; a trench-type gate structure that is formed in the main surface and is located within the semiconductor region; a rectification region of the first conductivity type that is formed in the surface layer section of the main surface, neighboring the gate structure; and a main surface electrode that is electrically isolated from the gate structure on the main surface, and forms a Schottky junction with the rectification region.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-166565 filed with the Japan Patent Office on September 27, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2021 / 0083094A1) discloses a semiconductor device including a planar gate field effect transistor and a Schottky barrier diode.

[0003] US Patent Application Publication No. 2021-083094

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; a trench-type gate structure formed on the main surface and positioned within the semiconductor region; a rectifying region of the first conductivity type formed in the surface layer portion of the main surface adjacent to the gate structure; and a main surface electrode on the main surface that is electrically isolated from the gate structure and forms a Schottky junction with the rectifying region.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; a trench-type gate structure formed on the main surface and positioned within the semiconductor region; a rectifying region of the first conductivity type formed in the surface layer portion of the main surface along the gate structure; a body region of a second conductivity type formed in the surface layer portion of the main surface along the gate structure; a source region of the first conductivity type formed in the surface layer portion of the body region; and a main surface electrode electrically separated from the gate structure on the main surface, electrically connected to the body region, and forming a Schottky junction with the rectifying region.

[0007] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a circuit diagram showing an example of the electrical configuration of a semiconductor device according to a first embodiment. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a plan view showing an example of the layout of a first main surface. FIG. 5 is an enlarged plan view showing a main portion of an active region. FIG. 6 is an enlarged plan view showing another main portion of the active region. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5. FIG. 10 is a cross-sectional view taken along line XX in FIG. 5. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 6. FIG. 12 is an enlarged cross-sectional view of a region shown in FIG. 7. FIG. 13 is an enlarged cross-sectional view of a region shown in FIG. 8. FIG. 14 is an enlarged cross-sectional view of a region shown in FIG. 9. FIG. 15 is an enlarged plan view showing a main portion of an active region of a semiconductor device according to a second embodiment. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 15 . FIG. 18 is an enlarged plan view showing a main portion of an active region of a semiconductor device according to the third embodiment. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 18 . FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18 . FIG. 21 is an enlarged plan view showing a main portion of an active region of a semiconductor device according to the fourth embodiment. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21 . FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 21 . FIG. 24 is an enlarged plan view showing a main portion of an active region of a semiconductor device according to the fifth embodiment. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 24 . FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 24 . FIG. 27 is an enlarged plan view showing a main portion of an active region of a semiconductor device according to the sixth embodiment. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in Fig. 27. Fig. 29 is a cross-sectional view taken along line XIX-XIX shown in Fig. 27. Fig. 30 is a cross-sectional view showing a semiconductor device according to a first modified example. Fig. 31 is a cross-sectional view showing a semiconductor device according to a second modified example. Fig. 32 is a cross-sectional view showing a semiconductor device according to a third modified example. Fig. 33 is a cross-sectional view showing a semiconductor device according to a fourth modified example. Fig. 34 is a cross-sectional view showing a semiconductor device according to a fifth modified example.FIG. 35 is a cross-sectional view showing a semiconductor device according to a sixth modification.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0012] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] 1 is a circuit diagram showing an example of the electrical configuration of a semiconductor device 1A according to the first embodiment. Referring to FIG. 1, the semiconductor device 1A is a "semiconductor switching device" including a drain terminal DT, a source terminal ST, a gate terminal GT, and a switching device SW.

[0014] The drain terminal DT is a terminal electrode to which a drain potential as a first potential is externally applied, the source terminal ST is a terminal electrode to which a source potential as a second potential different from the first potential is externally applied, and the gate terminal GT is a terminal electrode to which a gate potential (control potential) as a third potential different from the first and second potentials is externally applied.

[0015] The drain potential may be a high potential, the source potential may be a low potential lower than the high potential, or the source potential may be a reference potential (for example, ground potential) that serves as a reference for circuit operation.

[0016] The switching device SW includes an insulated gate transistor structure Tr, which in this embodiment is a field effect transistor (MISFET), including a drain electrically connected to a drain terminal DT, a source electrically connected to a source terminal ST, and a gate electrically connected to a gate terminal GT.

[0017] The switching device SW includes a first diode D1 electrically connected to the transistor structure Tr. The first diode D1 may also be referred to as a "first freewheeling diode." The first diode D1 is a pn junction diode (body diode). The first diode D1 is connected in parallel to the transistor structure Tr. Specifically, the first diode D1 includes a cathode electrically connected to the drain terminal DT and an anode electrically connected to the source terminal ST.

[0018] The first diode D1 has a first threshold voltage Vth1. The first threshold voltage Vth1 may be 0.5 V or more and 5 V or less. The first threshold voltage Vth1 may have a value belonging to at least one of the ranges of 0.5 V or more and 1 V or less, 1 V or more and 1.5 V or less, 1.5 V or more and 2 V or less, 2 V or more and 2.5 V or less, 2.5 V or more and 3 V or less, 3 V or more and 3.5 V or less, 3.5 V or more and 4 V or less, 4 V or more and 4.5 V or less, and 4.5 V or more and 5 V or less. The first threshold voltage Vth1 may be 2 V or more and 4 V or less.

[0019] The switching device SW includes a second diode D2 electrically connected to the transistor structure Tr. The second diode D2 may be referred to as a "second freewheeling diode." The second diode D2 has electrical characteristics different from the electrical characteristics of the first diode D1. The second diode D2 is a Schottky barrier diode.

[0020] The second diode D2 is connected in parallel to the transistor structure Tr. Specifically, the second diode D2 includes a cathode electrically connected to the drain terminal DT and an anode electrically connected to the source terminal ST. That is, the second diode D2 is connected in parallel in the forward direction to the first diode D1.

[0021] The second diode D2 has a second threshold voltage Vth2 that is less than the first threshold voltage Vth1. The second threshold voltage Vth2 may be 0.3 V or more and 3 V or less. The second threshold voltage Vth2 may have a value that belongs to at least one of the ranges of 0.3 V or more and 0.5 V or less, 0.5 V or more and 1 V or less, 1 V or more and 1.5 V or less, 1.5 V or more and 2 V or less, 2 V or more and 2.5 V or less, and 2.5 V or more and 3 V or less. The second threshold voltage Vth2 may be 0.5 V or more and 2 V or less.

[0022] The transistor structure Tr generates a drain current as an output current in an on-state. When the transistor structure Tr transitions from an on-state to an off-state, a reverse bias voltage is generated in the transistor structure Tr. The reverse bias voltage is a terminal voltage between the drain terminal DT at a negative potential and the source terminal ST at a positive potential. The reverse bias voltage is a forward voltage across the first diode D1 and the second diode D2.

[0023] The second diode D2 turns on when the reverse bias voltage becomes equal to or greater than the second threshold voltage Vth2. That is, the second diode D2 turns on before the first diode D1 at a reverse bias voltage (forward voltage) lower than the first threshold voltage Vth1. This allows the second diode D2 to handle the reverse current through the transistor structure Tr.

[0024] On the other hand, the first diode D1 does not turn on when the reverse bias voltage is less than the first threshold voltage Vth1, and turns on when the reverse bias voltage continues to increase until it becomes equal to or greater than the first threshold voltage Vth1 after the second diode D2 turns on.

[0025] In this case, a relatively large reverse current through the transistor structure Tr is handled by the first diode D1 and the second diode D2. The second diode D2 handles the reverse current before the first diode D1 is turned on, thereby preventing a relatively large reverse current from occurring when the first diode D1 is turned on.

[0026] For example, a power conversion device such as an inverter may include the semiconductor device 1A as an arm circuit. For example, the power conversion device may be mounted on a vehicle using a motor as a drive source, such as a hybrid vehicle, an electric vehicle, or a fuel cell vehicle.

[0027] Fig. 2 is a plan view of the semiconductor device 1A shown in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 1. Fig. 4 is a plan view showing an example layout of the first main surface 3. Fig. 5 is an enlarged plan view showing a main portion of the active region 8. Fig. 6 is an enlarged plan view showing another main portion of the active region 8.

[0028] Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 5. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 5. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 5. Fig. 10 is a cross-sectional view taken along line XX shown in Fig. 5. Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 6. Fig. 12 is an enlarged cross-sectional view of a region shown in Fig. 7. Fig. 13 is an enlarged cross-sectional view of a region shown in Fig. 8. Fig. 14 is an enlarged cross-sectional view of a region shown in Fig. 9.

[0029] 2 to 14, semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0030] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0031] The semiconductor device 1A may be referred to as a "SiC-MISFET." Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0032] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0033] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0034] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0035] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0036] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0037] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0038] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0039] The semiconductor device 1A includes an n-type base region 6 formed in a surface layer portion of the second main surface 4. The base region 6 forms the drain of the transistor structure Tr. The base region 6 may also be referred to as a "base layer," a "semiconductor region (layer)," a "first semiconductor region (layer)," a "drain region (layer)," or the like. A drain potential is applied to the base region 6 as a first potential (high potential).

[0040] The base region 6 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base region 6 is made of an n-type semiconductor layer. Specifically, the base region 6 is made of a substrate (SiC substrate) containing a SiC single crystal (semiconductor single crystal). The base region 6 (substrate) has the off direction and off angle described above.

[0041] The base region 6 may have a thickness of 10 μm to 500 μm. The thickness of the base region 6 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 300 μm, 300 μm to 400 μm, and 400 μm to 500 μm.

[0042] The semiconductor device 1A includes an n-type drift region 7 formed in a surface layer portion of the first main surface 3. The drift region 7 forms the drain of the transistor structure Tr. The drift region 7 may also be referred to as a "drain region," a "drain drift region," a "semiconductor region (layer)," a "second semiconductor region (layer)," or the like.

[0043] The drift region 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the base region 6. The drift region 7 is formed in a region on the first main surface 3 side of the base region 6 in a cross-sectional view, and is electrically connected to the base region 6.

[0044] Drift region 7 is formed in a layer shape extending along first main surface 3 and is exposed from first main surface 3 and first to fourth side surfaces 5A to 5D. In this embodiment, drift region 7 is made of an n-type semiconductor layer. Specifically, drift region 7 is made of an epitaxial layer (SiC epitaxial layer) including SiC single crystal (semiconductor single crystal).

[0045] The drift region 7 (epitaxial layer) has the off direction and off angle described above. The drift region 7 preferably has a thickness less than that of the base region 6. Of course, the thickness of the drift region 7 may be greater than that of the base region 6.

[0046] The thickness of the drift region 7 may be 5 μm or more and 20 μm or less. The thickness of the drift region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, and 17.5 μm or more and 20 μm or less.

[0047] The semiconductor device 1A includes an active region 8 defined in a chip 2. The active region 8 includes a switching device SW and is a region where a drain current (output current) is generated. The active region 8 is defined in an inner portion of the first main surface 3. The active region 8 is defined in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0048] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include the switching device SW (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2.

[0049] The peripheral region 9 is set in a ring shape in plan view so as to surround the active region 8. In this embodiment, the peripheral region 9 is set in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in plan view.

[0050] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 10 formed on the first main surface 3 in the active region 8. The gate structures 10 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential is applied to the plurality of gate structures 10. The plurality of gate structures 10 form gates of a transistor structure Tr.

[0051] The multiple gate structures 10 are arranged in an inner portion (active region 8) of the first main surface 3 at intervals inward from the periphery of the first main surface 3. The multiple gate structures 10 are arranged at intervals in a first direction X (= m-axis direction) in a plan view, and each extends in a strip shape in a second direction Y (= a-axis direction).

[0052] That is, the multiple gate structures 10 are arranged in a stripe pattern extending in the second direction Y (= the a-axis direction) in a plan view. The extending direction of the multiple gate structures 10 coincides with the off-direction of the SiC single crystal. Of course, the multiple gate structures 10 may be arranged at intervals in the second direction Y in a plan view and each extend in a strip pattern in the first direction X.

[0053] The multiple gate structures 10 may be arranged at a gate pitch of 1 μm to 5 μm, which is the distance in the horizontal direction (first direction X) between the centers of the multiple gate structures 10. The gate pitch may have a value belonging to at least one of the following ranges: 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0054] The plurality of gate structures 10 are formed on the first main surface 3 so as to be located within the drift region 7. Specifically, the plurality of gate structures 10 are formed at intervals from the depth position of the bottom of the drift region 7 toward the first main surface 3, and face the base region 6 with part of the drift region 7 in between. In this embodiment, the plurality of gate structures 10 are formed substantially perpendicular to the first main surface 3. Of course, the plurality of gate structures 10 may also be formed in a shape tapering toward the bottom of the drift region 7.

[0055] The side walls (long sides) of the plurality of gate structures 10 are each formed by an m-plane ((1-100) plane) of the SiC single crystal. Of course, the side walls (long sides) of the plurality of gate structures 10 may each be formed by an a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 10. The side walls of the plurality of gate structures 10 are formed approximately perpendicular to the first main surface 3.

[0056] The bottom walls of the gate structures 10 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 10 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the gate structures 10 may be curved in an arc shape toward the second main surface 4.

[0057] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 10 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0058] The gate structure 10 may have a width of 0.1 μm to 2 μm, and may have a width in at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0059] The depth of the gate structure 10 may be 0.1 μm or more and 3 μm or less. The depth of the gate structure 10 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 10 is preferably 0.5 μm or more and 1.5 μm or less.

[0060] The gate structure 10 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 10 is the ratio of the depth of the gate structure 10 to the width of the gate structure 10. The aspect ratio may have a value belonging to at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0061] The plurality of gate structures 10 includes trenches 11, insulating films 12, buried electrodes 13, and cap insulating films 14. The trenches 11 may be referred to as "gate trenches," the insulating films 12 may be referred to as "gate insulating films," the buried electrodes 13 may be referred to as "gate electrodes," and the cap insulating films 14 may be referred to as "buried insulators."

[0062] The trench 11 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 10. The insulating film 12 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 12 has a single-layer structure made of a silicon oxide film. The insulating film 12 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0063] The insulating film 12 covers the wall surface of the trench 11. In this embodiment, the insulating film 12 has an upper end portion positioned on the bottom wall side of the trench 11 relative to the height position of the first main surface 3, and exposes a part of the chip 2 from the wall surface of the opening end of the trench 11. The upper end portion of the insulating film 12 is preferably positioned on the opening side of the trench 11 relative to the depth position of the intermediate part of the trench 11.

[0064] The insulating film 12 includes a first film portion and a second film portion. The first film portion covers the sidewall of the trench 11 in a film-like manner. The second film portion covers the bottom wall of the trench 11 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to that of the first film portion.

[0065] The insulating film 12 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0066] The buried electrode 13 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 13 is buried in the trench 11 with the insulating film 12 sandwiched therebetween. The buried electrode 13 is buried in the trench 11 at a distance from the height position of the first main surface 3 on the bottom wall side of the trench 11.

[0067] The buried electrode 13 may be located closer to the first main surface 3 than the upper end of the insulating film 12, or may be located closer to the bottom wall of the trench 11 than the upper end of the insulating film 12. In this embodiment, the buried electrode 13 is located closer to the bottom wall of the trench 11 than the upper end of the insulating film 12, and a portion of the insulating film 12 covering the sidewall (first film portion) is exposed at the opening side of the trench 11.

[0068] The buried electrode 13 has an electrode surface exposed from the trench 11. The electrode surface is located closer to the bottom wall of the trench 11 than the height position of the first main surface 3. In this embodiment, the electrode surface is buried closer to the bottom wall of the trench 11 than the upper end of the insulating film 12.

[0069] The electrode surface is preferably located on the opening side of the trench 11 relative to the depth position of the intermediate portion of the trench 11. The electrode surface may have a recess in its inner portion that faces the bottom wall of the trench 11. The electrode surface defines a recess space within the trench 11 together with the side wall of the trench 11 (the first film portion of the insulating film 12).

[0070] The cap insulating film 14 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The cap insulating film 14 may include an insulating material different from the insulating material of the insulating film 12, or may include the same type of insulating material as the insulating film 12. In this form, the cap insulating film 14 includes a silicon oxide film having properties different from the properties of the insulating film 12.

[0071] The cap insulating film 14 may have a single layer structure or a stacked structure including at least one of a silicon oxide film without added impurities, a single layer structure consisting of a silicon oxide film containing phosphorus, and a silicon oxide film containing both phosphorus and boron.

[0072] A silicon oxide film without added impurities may be called an NSG film (nondoped silicate glass film), a silicon oxide film containing phosphorus may be called a PSG film (phosphorus silicon glass film), and a silicon oxide film containing both phosphorus and boron may be called a BPSG film (boron phosphorus silicon glass film).

[0073] The cap insulating film 14 preferably has a single-layer structure or a multi-layer structure including at least an NSG film. The cap insulating film 14 may have a multi-layer structure including an NSG film and a PSG film stacked in this order from the chip 2 side. The cap insulating film 14 may have a multi-layer structure including an NSG film, a PSG film, and a BPSG film stacked in this order from the chip 2 side. Of course, the cap insulating film 14 may have a single-layer structure or a multi-layer structure including a silicon oxide film including an oxide of the buried electrode 13.

[0074] The cap insulating film 14 is embedded in the trench 11 on top of the buried electrode 13 and covers the buried electrode 13. In this embodiment, the cap insulating film 14 is embedded in the trench 11 with the insulating film 12 sandwiched therebetween, and is in contact with the insulating film 12 and the buried electrode 13 within the trench 11. The cap insulating film 14 is embedded in the trench 11 at a distance from the height position of the first main surface 3 toward the bottom wall of the trench 11.

[0075] That is, the cap insulating film 14 has a portion that faces the chip 2 in the horizontal direction across the insulating film 12, and exposes the first main surface 3. In this embodiment, the cap insulating film 14 exposes a portion of the chip 2 from the wall surface of the opening end of the trench 11. The cap insulating film 14 may be located closer to the first main surface 3 than the upper end of the insulating film 12, or may be located closer to the bottom wall of the trench 11 than the upper end of the insulating film 12. Of course, the cap insulating film 14 may be formed flush with the first main surface 3.

[0076] The cap insulating film 14 has an insulating surface exposed from the trench 11. The insulating surface is located closer to the bottom wall of the trench 11 than the height position of the first main surface 3. The insulating surface may be located closer to the first main surface 3 than the upper end of the insulating film 12, or may be located closer to the bottom wall of the trench 11 than the upper end of the insulating film 12.

[0077] The insulating surface is preferably located on the opening side of trench 11 relative to the depth position of the intermediate portion of trench 11. The insulating surface may have a recess in the inner portion that faces the bottom wall of trench 11. Of course, the electrode surface may be formed flush with first main surface 3.

[0078] In this embodiment, the cap insulating film 14 has a thickness greater than that of the first film portion of the insulating film 12. Of course, the thickness of the cap insulating film 14 may be less than that of the first film portion of the insulating film 12. In this embodiment, the thickness of the cap insulating film 14 is greater than that of the second film portion of the insulating film 12. Of course, the thickness of the cap insulating film 14 may be less than that of the second film portion of the insulating film 12.

[0079] The thickness of the cap insulating film 14 is preferably less than the thickness of the buried electrode 13. The ratio of the thickness of the cap insulating film 14 to the depth of the trench 11 may be 0.01 or more and 0.3 or less. The ratio may have a value belonging to at least one of the ranges of 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or less, 0.2 or more and 0.25 or less, and 0.25 or more and 0.3 or less.

[0080] The semiconductor device 1A includes a plurality of mesas 15 defined on the first main surface 3 in the active region 8. The plurality of mesas 15 are defined in regions between adjacent gate structures 10, respectively.

[0081] The multiple mesas 15 are partitioned at intervals in the first direction X and extend in a band shape in the second direction Y. In other words, the multiple mesas 15 extend in a stripe shape in the second direction Y. The width of each mesa 15 corresponds to the value obtained by subtracting the width of one gate structure 10 from one gate pitch.

[0082] The semiconductor device 1A includes a plurality of n-type rectification regions 20 formed in the surface layer portion of the first main surface 3 in the active region 8. The rectification regions 20 may also be referred to as "impurity regions," "diode regions," "cathode regions," etc. The plurality of rectification regions 20 form the cathode of the second diode D2. The plurality of rectification regions 20 have an n-type impurity concentration that is lower than the n-type impurity concentration of the base region 6.

[0083] The n-type impurity concentrations of the multiple rectification regions 20 may be different from the n-type impurity concentration of the drift region 7, or may be approximately equal to the n-type impurity concentration of the drift region 7. In other words, the n-type impurity concentrations of the multiple rectification regions 20 may be higher than the n-type impurity concentration of the drift region 7, or may be lower than the n-type impurity concentration of the drift region 7.

[0084] In this embodiment, the multiple rectification regions 20 are formed by utilizing a portion of the drift region 7. That is, the n-type impurity concentration of the multiple rectification regions 20 is approximately equal to the n-type impurity concentration of the drift region 7. Of course, the multiple rectification regions 20 may be high-concentration regions formed by introducing n-type impurities into the surface layer portion of the drift region 7. In this case, the n-type impurity concentration of the multiple rectification regions 20 is higher than the n-type impurity concentration in the bottom portion of the drift region 7.

[0085] The plurality of rectification regions 20 are adjacent to the plurality of gate structures 10 respectively in the surface layer portion of the first main surface 3. Specifically, the plurality of rectification regions 20 are formed in the plurality of mesa portions 15 respectively.

[0086] In this embodiment, the plurality of rectification regions 20 are formed in a one-to-many correspondence with each corresponding mesa portion 15. The plurality of rectification regions 20 are formed in the corresponding mesa portion 15 at intervals in the second direction Y, and are adjacent to two gate structures 10 corresponding to the first direction X.

[0087] In this embodiment, the multiple rectification regions 20 extend in a strip shape in the second direction Y in plan view, following the extension direction of the multiple gate structures 10. The multiple rectification regions 20 on one side in the first direction X face the multiple rectification regions 20 on the other side in the first direction X, with a corresponding one gate structure 10 sandwiched between them.

[0088] That is, the plurality of rectification regions 20 are arranged in a line in the first direction X in a plan view. The plurality of rectification regions 20 are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0089] The plurality of body regions 21 each have a portion located on the bottom wall side of the corresponding trench 11 with respect to the electrode surface of the corresponding buried electrode 13, and a portion located on the first main surface 3 side with respect to the electrode surface of the corresponding buried electrode 13. The plurality of rectification regions 20 face the corresponding buried electrode 13 with the corresponding insulating film 12 interposed therebetween.

[0090] The plurality of rectification regions 20 each have a portion facing the corresponding cap insulating film 14. In this embodiment, the plurality of rectification regions 20 face the cap insulating film 14 with the insulating film 12 interposed therebetween. In this embodiment, the plurality of rectification regions 20 each have a portion exposed from the opening end of the corresponding trench 11.

[0091] The plurality of rectification regions 20 are formed across the entire thickness range of the corresponding mesa portion 15 in the thickness direction of the chip 2. In other words, the plurality of rectification regions 20 are adjacent to the corresponding gate structures 10 across the entire depth range of the corresponding gate structures 10.

[0092] The semiconductor device 1A includes a plurality of p-type body regions 21 formed in the surface layer portion of the first main surface 3 in the active region 8. The plurality of body regions 21 form the anode of the first diode D1. The body regions 21 may also be referred to as "anode regions." The plurality of body regions 21 have a p-type impurity concentration higher than the n-type impurity concentration of the drift region 7, and convert the conductivity type of the drift region 7 from n-type to p-type.

[0093] The body regions 21 are formed in regions other than the rectification regions 20 in the surface layer portion of the first main surface 3, adjacent to the gate structures 10 in the first direction X, and adjacent to the rectification regions 20 in the second direction Y. The body regions 21 are formed in the mesa portions 15, respectively. In this embodiment, the body regions 21 are each formed in a one-to-many correspondence with a corresponding one of the mesa portions 15.

[0094] The plurality of body regions 21 are formed in the corresponding mesa portion 15 at intervals in the second direction Y, adjacent to two gate structures 10 corresponding to the first direction X, and adjacent to one or more rectification regions 20 corresponding to the second direction Y. In this embodiment, the plurality of body regions 21 are arranged alternately with the plurality of rectification regions 20 in the second direction Y in the corresponding mesa portion 15, and define the plurality of rectification regions 20.

[0095] In other words, the multiple body regions 21 are arranged at intervals in the second direction Y in the corresponding mesa portion 15, and define multiple rectification regions 20. In this embodiment, the multiple body regions 21 each extend in a strip shape in the second direction Y in accordance with the extension direction of the multiple gate structures 10 in a plan view. It is preferable that the multiple body regions 21 have a length in the second direction Y that is greater than the length of the rectification region 20. Of course, the length of the multiple body regions 21 may be less than the length of the rectification region 20.

[0096] The plurality of body regions 21 on one side in the first direction X face the plurality of body regions 21 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them. That is, the plurality of body regions 21 are arranged in a line in the first direction X. The plurality of body regions 21 are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0097] The body regions 21 are formed at intervals from the bottom of the drift region 7 toward the first main surface 3, and face the base region 6 across a part of the drift region 7. Specifically, the body regions 21 are formed at intervals from the depth positions of the bottom walls of the gate structures 10 toward the first main surface 3.

[0098] The plurality of body regions 21 may have bottoms located on the bottom wall side of the plurality of gate structures 10 with respect to the depth position of the intermediate portions of the plurality of gate structures 10. Of course, the bottoms of the plurality of body regions 21 may be located on the first main surface 3 side with respect to the depth position of the intermediate portions of the plurality of gate structures 10.

[0099] Each of the body regions 21 has a portion located on the bottom wall side of the corresponding trench 11 with respect to the electrode surface of the corresponding buried electrode 13, and a portion located on the first main surface 3 side with respect to the electrode surface of the corresponding buried electrode 13. The body regions 21 face the corresponding buried electrode 13 with the corresponding insulating film 12 interposed therebetween.

[0100] Each of the body regions 21 has a portion facing the corresponding cap insulating film 14. In this embodiment, the body regions 21 face the cap insulating film 14 with the insulating film 12 interposed therebetween. In this embodiment, the body regions 21 each have a portion exposed from the opening end of the corresponding trench 11.

[0101] The plurality of body regions 21 each form a pn junction with the drift region 7. This forms a first diode D1 (pn junction diode) including the drift region 7 as a cathode and the plurality of body regions 21 as anodes. Furthermore, the plurality of body regions 21 each form a pn junction with the plurality of rectification regions 20 in portions that partition the plurality of rectification regions 20. In other words, the first diode D1 includes the plurality of rectification regions 20 as cathodes and the plurality of body regions 21 as anodes.

[0102] The semiconductor device 1A includes a plurality of n-type source regions 22 formed in the surface layer portion of the first main surface 3 in the active region 8. The plurality of source regions 22 form the sources of the transistor structures Tr.

[0103] The plurality of source regions 22 have a higher n-type impurity concentration than the p-type impurity concentration of the plurality of body regions 21, thereby converting the conductivity type of the plurality of body regions 21 from p-type to n-type. The n-type impurity concentration of the plurality of source regions 22 is higher than the n-type impurity concentration of the drift region 7. The n-type impurity concentration of the plurality of source regions 22 is higher than the n-type impurity concentration of the plurality of rectification regions 20.

[0104] The source regions 22 are formed in the surface layer portions of the body regions 21, respectively, and together with the drift region 7 define channels along the sidewalls of the gate structures 10. In this embodiment, the source regions 22 are formed in a one-to-one correspondence with the body regions 21, respectively.

[0105] Of course, the plurality of source regions 22 may be formed in a one-to-many correspondence in the surface layer portion of one corresponding body region 21. In this case, the plurality of source regions 22 may be formed at intervals in the second direction Y in the surface layer portion of one corresponding body region 21.

[0106] In this embodiment, the source regions 22 each extend in a strip shape in the second direction Y in a plan view, following the extension direction of the gate structures 10 (body regions 21). The source regions 22 preferably have a length in the second direction Y that is greater than the length of the rectification region 20. This configuration is effective in increasing the channel length (channel area) of the transistor structure Tr. Of course, the length of the source regions 22 may be less than the length of the rectification region 20.

[0107] The plurality of source regions 22 on one side in the first direction X face the plurality of source regions 22 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them. That is, the plurality of source regions 22 are arranged in a line in the first direction X. The plurality of source regions 22 are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0108] The plurality of source regions 22 are formed at intervals from the bottoms of the corresponding body regions 21 toward the first main surface 3, and face the drift region 7 with a portion of the corresponding body region 21 interposed therebetween. The plurality of source regions 22 are adjacent to the plurality of gate structures 10 in the first direction X. In this embodiment, the plurality of source regions 22 are formed at intervals from the peripheral portions of the corresponding body regions 21 in the second direction Y, and face the corresponding rectification region 20 with a portion of the corresponding body region 21 interposed therebetween.

[0109] Each of the plurality of source regions 22 has a portion located on the bottom wall side of the corresponding trench 11 with respect to the electrode surface of the corresponding buried electrode 13, and a portion located on the first main surface 3 side with respect to the electrode surface of the corresponding buried electrode 13. The plurality of source regions 22 face the corresponding buried electrode 13 with the corresponding insulating film 12 interposed therebetween.

[0110] Each of the plurality of source regions 22 has a portion facing the corresponding cap insulating film 14. In this embodiment, the plurality of source regions 22 face the cap insulating film 14 with the insulating film 12 interposed therebetween. In this embodiment, the plurality of source regions 22 each have a portion exposed from the opening end of the corresponding trench 11.

[0111] The semiconductor device 1A includes a plurality of p-type contact regions 23 formed in the active region 8 in a surface layer portion of the first main surface 3. The plurality of contact regions 23 have a p-type impurity concentration higher than the p-type impurity concentration of the plurality of body regions 21. The p-type impurity concentration of the plurality of contact regions 23 is higher than the n-type impurity concentration of the plurality of rectification regions 20. The p-type impurity concentration of the plurality of contact regions 23 may be higher than the n-type impurity concentration of the plurality of source regions 22 or may be lower than the n-type impurity concentration of the plurality of source regions 22.

[0112] The plurality of contact regions 23 are respectively formed in the surface layer portions of the plurality of body regions 21. In this embodiment, the plurality of contact regions 23 are respectively formed in a one-to-one correspondence with the plurality of body regions 21. In this embodiment, the plurality of contact regions 23 are respectively formed in the center portions of the corresponding body regions 21.

[0113] Of course, the multiple contact regions 23 may be arranged shifted to one side or the other in the second direction Y from the center of the corresponding body region 21. Furthermore, the multiple contact regions 23 may be formed in a one-to-many correspondence in the surface layer portion of the corresponding one body region 21. In this case, the multiple contact regions 23 may be formed at intervals in the second direction Y in the surface layer portion of the corresponding one body region 21.

[0114] In this embodiment, the plurality of contact regions 23 penetrate the corresponding source regions 22 in the thickness direction and are electrically connected to the corresponding body regions 21. The plurality of contact regions 23 each have a bottom located closer to the bottom of the corresponding body region 21 than the depth positions of the bottoms of the plurality of source regions 22. The plurality of contact regions 23 are formed at intervals from the bottoms of the corresponding body regions 21 toward the first main surface 3, and face the drift region 7 with a part of the corresponding body region 21 sandwiched therebetween.

[0115] When a plurality of source regions 22 are formed in one corresponding body region 21, the plurality of contact regions 23 may be formed in regions outside the plurality of source regions 22 in the surface layer portion of the body region 21. For example, the plurality of contact regions 23 may be interposed in regions between the plurality of source regions 22.

[0116] In this embodiment, the plurality of contact regions 23 extend in a strip shape in the second direction Y in a plan view following the extension direction of the plurality of gate structures 10 (body regions 21). The plurality of contact regions 23 on one side in the first direction X face the plurality of contact regions 23 on the other side in the first direction X, with a corresponding one of the gate structures 10 sandwiched therebetween.

[0117] That is, the multiple contact regions 23 are arranged in a row in the first direction X in a plan view. The multiple contact regions 23 are arranged in a matrix with gaps in the first direction X and the second direction Y in a plan view. It is preferable that the multiple contact regions 23 have a length in the second direction Y that is shorter than the length of the rectification region 20. Of course, the length of the multiple contact regions 23 may be longer than the length of the rectification region 20.

[0118] The plurality of contact regions 23 face the corresponding rectification regions 20 across a part of the corresponding body region 21 and a part of the corresponding source region 22. The plurality of contact regions 23 are adjacent to the plurality of gate structures 10 in the first direction X.

[0119] Each of the plurality of contact regions 23 has a portion located on the bottom wall side of the corresponding trench 11 with respect to the electrode surface of the corresponding buried electrode 13, and a portion located on the first main surface 3 side with respect to the electrode surface of the corresponding buried electrode 13. The plurality of contact regions 23 face the corresponding buried electrode 13 with the corresponding insulating film 12 interposed therebetween.

[0120] Each of the plurality of contact regions 23 has a portion facing the corresponding cap insulating film 14. In this embodiment, the plurality of contact regions 23 face the cap insulating film 14 with the insulating film 12 interposed therebetween. In this embodiment, the plurality of contact regions 23 each have a portion exposed from the opening end of the corresponding trench 11.

[0121] The semiconductor device 1A includes a plurality of p-type deep well regions 24 formed in the chip 2 in the active region 8. The deep well regions 24 may also be referred to as "well regions," "first impurity regions," "first column regions," "first pillar regions," etc.

[0122] The deep well region 24 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 7. The p-type impurity concentration of the deep well region 24 is higher than the n-type impurity concentrations of the multiple rectification regions 20. The p-type impurity concentration of the deep well region 24 may be higher than the p-type impurity concentration of the body region 21 or may be lower than the p-type impurity concentration of the body region 21. The p-type impurity concentration of the deep well region 24 is lower than the p-type impurity concentration of the multiple contact regions 23.

[0123] The deep well regions 24 are formed at intervals in the chip 2 in regions below the gate structures 10. Specifically, the deep well regions 24 are formed in the drift region 7 in a thickness range between the bottom of the drift region 7 and the bottom walls of the gate structures 10, and change the conductivity type of the drift region 7 from n-type to p-type.

[0124] The deep well regions 24 are formed at intervals in the first direction X and extend in a strip shape in the second direction Y. That is, the deep well regions 24 extend in a stripe shape in the second direction Y in a plan view. The extension direction of the deep well regions 24 coincides with the off-direction of the SiC single crystal.

[0125] The deep well regions 24 overlap the gate structures 10 in a one-to-one correspondence in the thickness direction. When the gate structures 10 extend in the first direction X, the deep well regions 24 may be formed at intervals in the second direction Y and extend in strips in the first direction X. In this case, the deep well regions 24 intersect (specifically, are perpendicular to) the off-direction.

[0126] The deep well regions 24 are formed at intervals from the periphery of the first main surface 3 inward of the first main surface 3. Both ends of the deep well regions 24 may be located inward of the gate structures 10 relative to both ends of the corresponding gate structures 10. Both ends of the deep well regions 24 may be located on the periphery of the first main surface 3 relative to both ends of the corresponding gate structures 10.

[0127] The deep well regions 24 are arranged at a column pitch that is approximately equal to the gate pitch of the gate structures 10. The deep well regions 24 have widths that are approximately equal to the widths of the gate structures 10. Of course, the widths of the deep well regions 24 may be greater than or less than the widths of the gate structures 10.

[0128] The width of the deep well region 24 may be 0.1 μm or more and 2 μm or less. The width of the deep well region 24 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0129] The ratio (width ratio) of the width of the plurality of deep well regions 24 to the width of the gate structure 10 may be 0.8 to 1.2. The width ratio may have a value belonging to any one of the ranges of 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The width ratio is preferably 0.9 to 1.1.

[0130] The deep well regions 24 are formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view. Each of the deep well regions 24 has an upper end located on the bottom wall side of the corresponding gate structure 10 and a lower end (bottom) located on the bottom side of the drift region 7. The upper ends of the deep well regions 24 are located on the bottom wall side of the corresponding gate structure 10 relative to a depth position of an intermediate portion between the bottom of the drift region 7 and the bottom wall of the corresponding gate structure 10.

[0131] The upper ends of the deep well regions 24 may be connected to the bottom walls of the corresponding gate structures 10 and may face the buried electrodes 13 across the insulating film 12. In this case, the upper ends of the deep well regions 24 may have portions along the side walls of the corresponding gate structures 10 and face the corresponding buried electrodes 13 in the horizontal direction across the corresponding insulating film 12. The upper ends of the deep well regions 24 may be formed at intervals from the bottom walls of the corresponding gate structures 10 toward the bottom of the drift region 7.

[0132] The top ends of the deep well regions 24 may be formed at a top distance of 0 μm or more and 1 μm or less from the bottom wall of the corresponding gate structure 10. The top distance may have a value belonging to at least one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0133] The lower ends of the plurality of deep well regions 24 are located on the bottom side of the drift region 7 with respect to the depth position of the intermediate portion between the bottom of the drift region 7 and the bottom wall of the corresponding gate structure 10. In this embodiment, the lower ends of the plurality of deep well regions 24 are formed at intervals from the bottom of the drift region 7 to the bottom wall side of the corresponding gate structure 10, and face the base region 6 with a part of the drift region 7 interposed therebetween.

[0134] The lower ends of the plurality of deep well regions 24 may be formed at a lower end distance of 0 μm or more and 5 μm or less from the bottom of the drift region 7. The lower end distance may have a value belonging to at least one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or more, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or more, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0135] The lower ends of the plurality of deep well regions 24 may cross the boundary between the base region 6 and the drift region 7 and have a portion located within the base region 6. In this case, the amount of protrusion of the lower ends of the plurality of deep well regions 24 from the bottom of the drift region 7 may be greater than 0 μm and equal to or less than 5 μm.

[0136] The amount of protrusion may have a value belonging to at least one of the ranges of greater than 0 μm and not more than 0.5 μm, 0.5 μm or more and not more than 1 μm, 1 μm or more and not more than 1.5 μm, 1.5 μm or more and not more than 2 μm, 2 μm or more and not more than 2.5 μm, 2.5 μm or more and not more than 3 μm, 3 μm or more and not more than 3.5 μm, 3.5 μm or more and not more than 4 μm, 4 μm or more and not more than 4.5 μm, and 4.5 μm or more and not more than 5 μm.

[0137] The deep well regions 24 may have a depth greater than the depth of the gate structures 10. Of course, the depth of the deep well regions 24 may be less than the depth of the gate structures 10.

[0138] The ratio (depth ratio) of the depth of the plurality of deep well regions 24 to the depth of the gate structure 10 may be 0.5 or more and 5 or less. The depth ratio may have a value belonging to at least one of the ranges of 0.5 to 1, 1 to 1.5, 1.5 to 2, 2 to 2.5, 2.5 to 3, 3 to 3.5, 3.5 to 4, 4 to 4.5, and 4.5 to 5 or less.

[0139] The depth of the deep well regions 24 may be 1 μm or more and 5 μm or less. The depth of the deep well regions 24 may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0140] The deep well regions 24 may have an aspect ratio of 1 to 10. The aspect ratio of the deep well regions 24 is the ratio of the depth of the deep well regions 24 to the width of the deep well regions 24. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0141] The deep well regions 24 may be formed by a single impurity region extending in the thickness direction in a cross-sectional view. In this case, the deep well regions 24 may be formed by a channeling region extending along the axial channel of the chip 2 (drift region 7) in a cross-sectional view. In other words, the deep well regions 24 may be formed by a channeling ion implantation method.

[0142] In the channeling ion implantation method, a trivalent element (p-type impurity) is introduced into the drift region 7 from the bottom wall of the trench 11 along an axial channel of the chip 2 (drift region 7). The axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the chip 2 (drift region 7), and is surrounded by atomic rows constituting a crystal axis extending in the thickness direction (crystal growth direction).

[0143] That is, the axial channel is a region in which the atomic rows are sparse extending in the thickness direction and the atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The axial channel is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1", "a2", "a3", and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).

[0144] In this embodiment, the axial channel is composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. That is, the axial channel extends along the c-axis and has the off-direction and off-angle described above. In other words, the axial channel is inclined by the off-angle from the vertical axis toward the off-direction.

[0145] When the multiple deep well regions 24 consist of channeling regions, the multiple deep well regions 24 consist of impurity regions introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low-index crystal axis within the chip 2, and may be obliquely inclined with respect to the first main surface 3.

[0146] In this case, the deep well regions 24 preferably have a depth (thickness) of 0.5 μm or more. For example, when the upper ends of the deep well regions 24 are used as a reference, the rate of decrease in the p-type impurity concentration of the deep well regions 24 within a depth (thickness) range of 0.5 μm is preferably 50% or less.

[0147] Of course, the deep well regions 24 may be formed by multiple impurity regions stacked in multiple stages in the thickness direction in a cross-sectional view. The deep well regions 24 may also be composed of p-type random regions extending in a random direction intersecting the axial channel of the chip 2 (drift region 7). For example, the random direction may be the vertical direction Z.

[0148] The semiconductor device 1A includes a plurality of n-type deep drift regions 25 formed in the chip 2 in the active region 8. The deep drift regions 25 may also be referred to as "second impurity regions," "second column regions," "second pillar regions," etc. Each of the plurality of deep drift regions 25 is made up of an area of ​​the drift region 7 partitioned by a plurality of deep well regions 24.

[0149] The deep drift regions 25 are arranged alternately with the deep well regions 24 in the first direction X in accordance with the arrangement of the deep well regions 24, and each extends in a stripe shape in the second direction Y. In other words, the deep drift regions 25 are arranged in a stripe shape extending in the second direction Y. The extension direction of the deep drift regions 25 coincides with the off-direction of the SiC single crystal.

[0150] Of course, when the plurality of deep well regions 24 (the plurality of gate structures 10) extend in the first direction X, the plurality of deep drift regions 25 may also extend in the first direction X. In this case, the plurality of deep drift regions 25 intersect (specifically, are perpendicular to) the off direction.

[0151] The multiple deep drift regions 25 include multiple deep drift regions 25 facing multiple rectification regions 20 in the thickness direction, and multiple deep drift regions 25 facing multiple body regions 21 (multiple source regions 22) in the thickness direction.

[0152] The deep drift regions 25 are electrically connected to the rectification regions 20 in the thickness direction, respectively, and form current paths extending in the thickness direction (vertical direction Z) together with the rectification regions 20. The deep drift regions 25 are electrically connected to the body regions 21 (source regions 22) in the thickness direction, respectively, and form current paths extending in the thickness direction (vertical direction Z) together with the body regions 21 (source regions 22).

[0153] The deep drift regions 25 form pn junctions with the deep well regions 24. The pn junctions may function as part of the first diode D1. That is, the first diode D1 may include the deep drift regions 25 as cathodes and the deep well regions 24 as anodes.

[0154] The plurality of deep drift regions 25 may form a charge balance together with the plurality of deep well regions 24. The charge balance means a state in which a depletion layer extending from one deep well region 24 side and a depletion layer extending from the other deep well region 24 side are connected within the deep drift region 25 when a reverse bias voltage is applied.

[0155] In this case, the deep drift regions 25 form a superjunction structure together with the deep well regions 24. The deep drift regions 25 do not necessarily have to form a superjunction structure, and may simply form a pn junction diode (part of the first diode D1) together with the deep well regions 24.

[0156] The semiconductor device 1A includes a plurality of p-type well regions 26 formed in the chip 2 in the active region 8. The well regions 26 have a p-type impurity concentration higher than the n-type impurity concentration of the drift region 7. The p-type impurity concentration of the well regions 26 may be higher than the p-type impurity concentration of the body region 21 or may be lower than the p-type impurity concentration of the body region 21.

[0157] The p-type impurity concentration of the well region 26 may be higher than the p-type impurity concentration of the deep well region 24, or may be lower than the p-type impurity concentration of the deep well region 24. The p-type impurity concentration of the well region 26 may be higher than the p-type impurity concentration of the contact region 23, or may be lower than the p-type impurity concentration of the contact region 23. In this embodiment, the p-type impurity concentration of the well region 26 is approximately equal to the p-type impurity concentration of the contact region 23.

[0158] The multiple well regions 26 are formed in regions within the chip 2 that are aligned with the multiple gate structures 10. Specifically, the multiple well regions 26 are formed in a one-to-many correspondence with the multiple gate structures 10. The multiple well regions 26 are formed at intervals in the second direction Y, following the extension direction of a corresponding one of the gate structures 10. The multiple well regions 26 are interposed in regions between the multiple contact regions 23 in the first direction X.

[0159] That is, the multiple well regions 26 are arranged in a row with the multiple contact regions 23 in the first direction X. The multiple well regions 26 are arranged in a matrix with gaps in the first direction X and the second direction Y in a plan view. It is preferable that the multiple well regions 26 have a length in the second direction Y that is smaller than the length of the rectification region 20. Of course, the length of the multiple well regions 26 may be greater than the length of the rectification region 20.

[0160] In this embodiment, the length of the multiple well regions 26 is approximately equal to the length of the multiple contact regions 23. Of course, the length of the multiple well regions 26 may be greater than the length of the multiple contact regions 23, or may be shorter than the length of the multiple contact regions 23.

[0161] In this embodiment, each of the multiple well regions 26 has one first portion 26a along the bottom wall of the corresponding gate structure 10 and two second portions 26b along the sidewalls of the corresponding gate structure 10. The first portion 26a extends along the bottom wall of the corresponding gate structure 10. In this embodiment, the first portion 26a extends horizontally across the entire area of ​​the bottom wall of the corresponding gate structure 10 in a cross-sectional view.

[0162] The first portion 26a is connected to the upper end of the corresponding deep well region 24. In other words, the first portion 26a is electrically connected to the deep well region 24 and increases the p-type impurity concentration at the upper end of the deep well region 24. The first portion 26a has a bottom located closer to the bottom wall of the gate structure 10 than the bottom of the deep well region 24. The bottom of the first portion 26a is preferably located closer to the bottom wall of the gate structure 10 than the depth position of the intermediate portion of the deep well region 24.

[0163] The second portions 26b extend in the thickness direction along one sidewall and the other sidewall of the corresponding gate structure 10. The second portions 26b face the buried electrodes 13 with the corresponding insulating film 12 interposed therebetween. The second portions 26b are connected to the corresponding body regions 21 on the first main surface 3 side, and are connected to the first portions 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portions 26b electrically connect the corresponding deep well regions 24 to the body regions 21.

[0164] In this embodiment, the second portions 26b are connected to the corresponding contact regions 23 in the surface layer portions of the corresponding body regions 21. In this embodiment, the second portions 26b are integrally formed with the corresponding contact regions 23. That is, the second portions 26b electrically connect the corresponding deep well regions 24 to the corresponding contact regions 23.

[0165] The second portions 26b have a thickness smaller than that of the first portions 26a. The thickness of the first portions 26a is the thickness of the first portions 26a along the vertical direction Z when the bottom wall of the gate structure 10 is used as a reference. The thickness of the second portions 26b is the thickness of the second portions 26b along the horizontal direction (first direction X) when the sidewall of the gate structure 10 is used as a reference.

[0166] The semiconductor device 1A includes a p-type outer well region 27 formed in the outer peripheral region 9 (the peripheral portion of the first main surface 3) in a surface layer portion of the first main surface 3. A source potential is applied to the outer well region 27. The outer well region 27 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 7.

[0167] The outer well region 27 has a p-type impurity concentration that is lower than the p-type impurity concentration of the contact region 23. The p-type impurity concentration of the outer well region 27 may be higher than the p-type impurity concentration of the body region 21, or may be lower than the p-type impurity concentration of the body region 21. The p-type impurity concentration of the outer well region 27 may be higher than the p-type impurity concentration of the well region 26, or may be lower than the p-type impurity concentration of the well region 26.

[0168] The outer well region 27 is formed in a surface layer portion of the drift region 7. The outer well region 27 extends in a layered manner along the first main surface 3. The outer well region 27 is formed at an interval from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) to the inward side of the first main surface 3 (toward the active region 8). The outer well region 27 extends in a band shape along the periphery of the first main surface 3 (the periphery of the active region 8) in a plan view.

[0169] In this embodiment, the outer well region 27 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. In other words, the outer well region 27 collectively surrounds the multiple gate structures 10. The outer well region 27 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0170] The outer well region 27 has an inner edge on the inner side (active region 8 side) of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer well region 27 defines the boundary between the active region 8 and the outer peripheral region 9. The inner edge of the outer well region 27 is connected to the ends of the multiple gate structures 10 in a portion extending in the first direction X. The inner edge of the outer well region 27 may be located closer to the inner parts of the multiple gate structures 10 than the ends of the multiple gate structures 10.

[0171] The inner edge of the outer well region 27 may have a portion located in a region between the plurality of gate structures 10 and connected to the plurality of body regions 21. The inner edge of the outer well region 27 is connected to the outermost gate structure 10 in a portion extending in the second direction Y. The outer edge of the outer well region 27 is formed spaced inward from the periphery of the chip 2 and extends approximately parallel to the inner edge of the outer well region 27.

[0172] The outer well region 27 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 27 may have a value belonging to at least one of the ranges of greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0173] The outer well region 27 is formed at a distance from the bottom of the drift region 7 toward the first main surface 3, and faces the base region 6 across a part of the drift region 7. The outer well region 27 may also be formed at a distance from a depth position in the middle of the drift region 7 toward the first main surface 3.

[0174] In this embodiment, the outer well region 27 is formed at an interval from the depth position of the bottom walls of the plurality of gate structures 10 toward the first main surface 3. Of course, the outer well region 27 may have a portion located on the bottom side of the drift region 7 with respect to the depth position of the bottom walls of the plurality of gate structures 10. In this embodiment, the outer well region 27 is formed deeper than the plurality of body regions 21. Of course, the outer well region 27 may be formed shallower than the plurality of body regions 21.

[0175] The outer well region 27 forms a pn junction with the drift region 7. The outer well region 27 spreads a depletion layer in the drift region 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 27 spreads horizontally and in the thickness direction, and merges with the depletion layer spreading from the active region 8. The outer well region 27 expands the depletion layer spreading from the active region 8 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (outer peripheral region 9) of the first main surface 3.

[0176] The semiconductor device 1A includes a main surface insulating film 30 that selectively covers the first main surface 3. The main surface insulating film 30 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 30 preferably includes the same type of insulating material as the insulating film 12. In this embodiment, the main surface insulating film 30 has a single-layer structure made of a silicon oxide film. The main surface insulating film 30 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0177] The main surface insulating film 30 covers the first main surface 3 in the peripheral region 9 in a film form. Specifically, the main surface insulating film 30 covers the outer well region 27 in the peripheral region 9. The main surface insulating film 30 is extended from the peripheral region 9 to the active region 8, and is selectively connected to the insulating films 12 of the plurality of gate structures 10 in the peripheral portion of the active region 8, exposing the buried electrodes 13 of the plurality of gate structures 10.

[0178] In this embodiment, the main surface insulating film 30 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. Of course, the main surface insulating film 30 may be formed at an interval inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3.

[0179] The semiconductor device 1A includes one or more (in this embodiment, multiple) gate wirings 31 arranged on the first main surface 3 in the peripheral region 9. The multiple gate wirings 31 apply a gate potential to the multiple gate structures 10. The multiple gate wirings 31 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the multiple gate wirings 31 have the same conductivity type as the conductivity type of the buried electrodes 13 of the multiple gate structures 10.

[0180] The plurality of gate wirings 31 are disposed on the main surface insulating film 30. The plurality of gate wirings 31 are selectively routed on the main surface insulating film 30 at intervals from the periphery of the first main surface 3 toward the active region 8, and face the outer well region 27 with the main surface insulating film 30 in between.

[0181] The plurality of gate wirings 31 include a gate wiring 31 on one side in the second direction Y and a gate wiring 31 on the other side in the second direction Y. One of the gate wirings 31 is formed in a band shape with ends extending in the first direction X so as to intersect (specifically, perpendicular to) one end of the plurality of gate structures 10. The other gate wiring 31 is formed in a band shape with ends extending in the first direction X so as to intersect (specifically, perpendicular to) the other end of the plurality of gate structures 10.

[0182] The plurality of gate wirings 31 each have an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portions of the plurality of gate wirings 31 cover one end or the other end of the plurality of gate structures 10 and are mechanically and electrically connected to the plurality of gate structures 10. Specifically, the plurality of gate wirings 31 are mechanically and electrically connected to the plurality of buried electrodes 13. In this embodiment, the plurality of gate wirings 31 are formed integrally with the plurality of buried electrodes 13 as lead-out portions of the plurality of buried electrodes 13.

[0183] In this embodiment, the outer edges of the plurality of gate wirings 31 are spaced apart from the outer edge of the outer well region 27 toward the active region 8. Of course, the plurality of gate wirings 31 may have a portion that is drawn out toward the periphery of the first main surface 3 beyond the outer edge of the outer well region 27 and faces the drift region 7 with the main surface insulating film 30 interposed therebetween.

[0184] Of course, the semiconductor device 1A may include a single gate wiring 31. In this case, the gate wiring 31 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view. For example, the gate wiring 31 may have a portion extending along the first side surface 5A, a portion extending along the second side surface 5B, and a portion extending along the third side surface 5C, and may intersect (specifically, perpendicular to) both one end and the other end of the plurality of gate structures 10.

[0185] In this case, the gate wiring 31 may have a portion extending along the fourth side surface 5D. Furthermore, the portion of the gate wiring 31 extending in the second direction Y may be mechanically and electrically connected to one or both of the plurality of gate structures 10 (buried electrodes 13) arranged on both sides in the first direction X.

[0186] In this embodiment, the gate wiring 31 may be formed in the shape of an endless band having four sides parallel to the periphery of the first main surface 3 and may surround a plurality of gate structures 10 (active regions 8). The gate wiring 31 may be formed in the shape of an endless polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate wiring 31 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view.

[0187] The semiconductor device 1A includes an insulating interlayer film 32 that covers the main surface insulating film 30. The interlayer film 32 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 32 preferably includes a silicon oxide film.

[0188] The interlayer film 32 may contain an insulating material different from that of the main surface insulating film 30, or may contain the same type of insulating material as that of the main surface insulating film 30. In this embodiment, the interlayer film 32 contains a silicon oxide film having properties different from those of the main surface insulating film 30. The interlayer film 32 may have a single layer structure or a multilayer structure including at least one of an NSG film, a PSG film, and a BPSG film.

[0189] The interlayer film 32 preferably has a single layer structure or a laminated structure including at least an NSG film. The interlayer film 32 may have a laminated structure including an NSG film and a PSG film laminated in this order from the chip 2 side. The interlayer film 32 may have a laminated structure including an NSG film, a PSG film, and a BPSG film laminated in this order from the chip 2 side.

[0190] The interlayer film 32 covers the first main surface 3 in a film-like manner, sandwiching the main surface insulating film 30 therebetween. The interlayer film 32 covers the outer well region 27 in the peripheral region 9, sandwiching the main surface insulating film 30 therebetween. In this embodiment, the interlayer film 32 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the first main surface 3. Of course, the interlayer film 32 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D, exposing the periphery of the first main surface 3.

[0191] The interlayer film 32 covers the gate wiring 31 in the peripheral region 9. The interlayer film 32 is drawn from the peripheral region 9 to the active region 8, and covers both ends of the plurality of gate structures 10 in the periphery of the active region 8. Specifically, the interlayer film 32 covers the plurality of buried electrodes 13 at both ends of the plurality of gate structures 10, and is connected to the plurality of cap insulating films 14.

[0192] The interlayer film 32 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 32 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0193] The semiconductor device 1A includes one or more (one in this embodiment) source openings 33 formed in the interlayer film 32. The source openings 33 collectively expose the plurality of gate structures 10 and the plurality of mesa portions 15 in the inner part of the active region 8.

[0194] The source openings 33 are formed at intervals from both ends of the plurality of gate structures 10 toward the inner portion of the first main surface 3, exposing the inner portions of the plurality of gate structures 10 and the inner portions of the plurality of mesa portions 15. In this embodiment, the source openings 33 are formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0195] The semiconductor device 1A includes the aforementioned source terminal ST disposed on the first main surface 3. The source terminal ST may also be referred to as a "first main surface electrode," a "first terminal electrode," a "first pad electrode," a "source pad electrode," or the like. The source terminal ST is disposed on the interlayer film 32.

[0196] In this embodiment, the source terminal ST has a first pad portion STa, a second pad portion STb, and a third pad portion STc. The first pad portion STa has a relatively large planar area and forms the main body of the source terminal ST. In this embodiment, the first pad portion STa is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located toward the fourth side surface 5D with respect to the center of the first main surface 3.

[0197] The second pad portion STb has a planar area smaller than that of the first pad portion STa, and is drawn out in a strip (rectangular) shape from one end of the first pad portion STa in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion STc has a planar area smaller than that of the first pad portion STa, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion STa in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion STb in the second direction Y.

[0198] The planar area of ​​the third pad portion STc may be approximately equal to the planar area of ​​the second pad portion STb. Of course, the planar area of ​​the third pad portion STc may be larger than the planar area of ​​the second pad portion STb, or may be smaller than the planar area of ​​the second pad portion STb. Either or both of the second pad portion STb and the third pad portion STc may be used as a terminal portion for monitoring current.

[0199] The source terminal ST does not necessarily have to have both the second pad portion STb and the third pad portion STc at the same time. The source terminal ST may have only one of the second pad portion STb and the third pad portion STc. Of course, the source terminal ST does not necessarily have to be made up of only the first pad portion STa and have both the second pad portion STb and the third pad portion STc.

[0200] The source terminal ST covers the entire region of the interlayer film 32 where the source opening 33 is formed, in a film-like manner, and extends from above the interlayer film 32 into the source opening 33. The source terminal ST has a portion that covers the interlayer film 32 in a film-like manner, a portion that covers the wall surface of the source opening 33 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 33. The source terminal ST has a portion that covers the multiple gate structures 10 within the source opening 33, and a portion that covers the multiple mesa portions 15.

[0201] The source terminal ST directly covers the plurality of cap insulating films 14 in the portion covering the plurality of gate structures 10 , and is electrically separated from the plurality of buried electrodes 13 by the plurality of cap insulating films 14 .

[0202] In this embodiment, the source terminal ST enters the plurality of trenches 11 from above the first main surface 3 and covers the plurality of cap insulating films 14 within the plurality of trenches 11. In this embodiment, the source terminal ST has portions that cover the insulating surfaces of the plurality of cap insulating films 14 in regions on the bottom wall side of the plurality of trenches 11 relative to the height position of the first main surface 3.

[0203] The source terminal ST has a portion covering the opening ends and sidewalls of the trenches 11 within the trenches 11. The source terminal ST is mechanically and electrically connected to the rectification regions 20, the body regions 21, the source regions 22, and the contact regions 23 at the portion covering the opening ends and sidewalls of the trenches 11.

[0204] The source terminal ST is mechanically and electrically connected to the rectification regions 20 , the body regions 21 , the source regions 22 and the contact regions 23 in the portion covering the mesas 15 .

[0205] The source terminal ST forms a Schottky junction with the plurality of rectification regions 20 to constitute a second diode D2. This forms a second diode D2 (Schottky diode) including the plurality of rectification regions 20 as a cathode and the source terminal ST as an anode. The source terminal ST forms ohmic contact with the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23.

[0206] The source terminal ST has a peripheral portion facing the ends (both ends) of the plurality of gate structures 10 with the interlayer film 32 sandwiched therebetween. The peripheral portion of the source terminal ST may be drawn out from the active region 8 to the peripheral region 9 and may face one or more gate wirings 31 with the interlayer film 32 sandwiched therebetween. The peripheral portion of the source terminal ST may face the outer well region 27 with the interlayer film 32 sandwiched therebetween.

[0207] In this embodiment, the source terminal ST has a laminated structure including a lower electrode film 34 and a main electrode film 35 laminated in this order from the chip 2 side. In this embodiment, the lower electrode film 34 has a laminated structure including a first electrode film 36 and a second electrode film 37. In this embodiment, the first electrode film 36 is formed as a barrier metal film. The metal species constituting the first electrode film 36 is appropriately selected depending on the barrier height (second threshold voltage Vth2) to be achieved.

[0208] The first electrode film 36 may include at least one metal species selected from the group consisting of a magnesium (Mg) film, an aluminum (Al) film, a titanium (Ti) film, a vanadium (V) film, a chromium (Cr) film, a manganese (Mn) film, a cobalt (Co) film, a nickel (Ni) film, a copper (Cu) film, a zirconium (Zr) film, a niobium (Nb) film, a molybdenum (Mo) film, a palladium (Pd) film, a silver (Ag) film, an indium (In) film, a tin (Sn) film, a tantalum (Ta) film, a tungsten (W) film, a platinum (Pt) film, and a gold (Au) film.

[0209] The first electrode film 36 may contain at least one metal species selected from the group consisting of a magnesium alloy film, an aluminum alloy film, a titanium alloy film, a vanadium alloy film, a chromium alloy film, a manganese alloy film, a cobalt alloy film, a nickel alloy film, a copper alloy film, a zirconium alloy film, a niobium alloy film, a molybdenum alloy film, a palladium alloy film, a silver alloy film, an indium alloy film, a tin alloy film, a tantalum alloy film, a tungsten alloy film, a platinum alloy film, and a gold alloy film.

[0210] The first electrode film 36 may contain at least one metal species selected from the group consisting of a magnesium compound film, an aluminum compound film, a titanium compound film, a vanadium compound film, a chromium compound film, a manganese compound film, a cobalt compound film, a nickel compound film, a copper compound film, a zirconium compound film, a niobium compound film, a molybdenum compound film, a palladium compound film, a silver compound film, an indium compound film, a tin compound film, a tantalum compound film, a tungsten compound film, a platinum compound film, and a gold compound film. In this embodiment, the first electrode film 36 includes a Ti film.

[0211] The first electrode film 36 has a thickness less than the thickness of the interlayer film 32. The thickness of the first electrode film 36 may be 10 nm or more and 200 nm or less. The thickness of the first electrode film 36 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0212] The first electrode film 36 collectively covers the region of the interlayer film 32 where the source opening 33 is formed, and extends from above the interlayer film 32 into the source opening 33. The first electrode film 36 has a portion that covers the insulating main surface of the interlayer film 32 in a film-like manner, a portion that covers the wall surface of the source opening 33 in a film-like manner, and a portion that covers the first main surface 3 within the source opening 33. The first electrode film 36 has a portion that covers the multiple gate structures 10 within the source opening 33 and a portion that covers the multiple mesa portions 15.

[0213] The first electrode film 36 directly covers the cap insulating films 14 in the portions covering the gate structures 10 , and is electrically isolated from the buried electrodes 13 by the cap insulating films 14 .

[0214] In this embodiment, the first electrode film 36 enters the plurality of trenches 11 from above the first main surface 3 and covers the plurality of cap insulating films 14 within the plurality of trenches 11. In this embodiment, the first electrode film 36 has portions that cover the insulating surfaces of the plurality of cap insulating films 14 in regions on the bottom wall side of the plurality of trenches 11 relative to the height position of the first main surface 3.

[0215] The first electrode film 36 has portions that cover the opening ends and sidewalls of the trenches 11 within the trenches 11. The first electrode film 36 is mechanically and electrically connected to the rectification regions 20, the body regions 21, the source regions 22, and the contact regions 23 in the portions that cover the opening ends and sidewalls of the trenches 11.

[0216] The first electrode film 36, in a portion covering the plurality of mesas 15, is mechanically and electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23. The first electrode film 36 forms Schottky junctions with the plurality of rectification regions 20, thereby constituting the second diode D2.

[0217] The first electrode film 36 has a peripheral portion facing the ends (both ends) of the multiple gate structures 10 with the interlayer film 32 sandwiched therebetween. The peripheral portion of the first electrode film 36 may be drawn out from the active region 8 to the peripheral region 9 and face one or more gate wirings 31 with the interlayer film 32 sandwiched therebetween. The peripheral portion of the first electrode film 36 may face the outer well region 27 with the interlayer film 32 sandwiched therebetween.

[0218] The second electrode film 37 contains a metal material different from the metal material of the first electrode film 36. In this embodiment, the second electrode film 37 is made of a TiN film. The second electrode film 37 has a thickness less than that of the interlayer film 32. The thickness of the second electrode film 37 is preferably greater than that of the first electrode film 36.

[0219] The thickness of the second electrode film 37 may be 50 nm or more and 300 nm or less. The thickness of the second electrode film 37 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, 225 nm or more and 250 nm or less, 250 nm or more and 275 nm or less, and 275 nm or more and 300 nm or less.

[0220] The second electrode film 37 directly covers the first electrode film 36. The second electrode film 37 collectively covers the region of the interlayer film 32 where the source opening 33 is formed, sandwiching the first electrode film 36 therebetween, and extends from above the interlayer film 32 into the source opening 33.

[0221] The second electrode film 37 has a portion that covers the interlayer film 32 in a film state with the first electrode film 36 sandwiched therebetween, a portion that covers the wall surface of the source opening 33 in a film state with the first electrode film 36 sandwiched therebetween, and a portion that covers the first main surface 3 in a film state with the first electrode film 36 sandwiched therebetween within the source opening 33. The second electrode film 37 has a portion that covers the multiple gate structures 10 in the source opening 33 with the first electrode film 36 sandwiched therebetween, and a portion that covers the multiple mesa portions 15 with the first electrode film 36 sandwiched therebetween.

[0222] The second electrode film 37 covers the plurality of cap insulating films 14 with the first electrode film 36 interposed therebetween, and is electrically isolated from the plurality of buried electrodes 13. In this embodiment, the second electrode film 37 enters the plurality of trenches 11 from above the first main surface 3, and covers the plurality of cap insulating films 14 in the plurality of trenches 11 with the first electrode film 36 interposed therebetween.

[0223] In this embodiment, the second electrode film 37 covers the first electrode film 36 in regions on the bottom wall side of the plurality of trenches 11 relative to the height position of the first main surface 3. In this embodiment, the second electrode film 37 has portions that cover the opening ends and side walls of the plurality of trenches 11 with the first electrode film 36 sandwiched therebetween.

[0224] The second electrode film 37 is electrically connected to the rectification regions 20, the body regions 21, the source regions 22, and the contact regions 23 via the first electrode film 36 in a portion covering the opening ends and sidewalls of the trenches 11. Of course, the second electrode film 37 may be connected to the first electrode film 36 above the first main surface 3.

[0225] The second electrode film 37 is mechanically and electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22 and the plurality of contact regions 23 via the first electrode film 36 in the portion covering the plurality of mesa portions 15.

[0226] The main electrode film 35 contains a metal material different from the metal material of the lower electrode film 34 (the first electrode film 36 and the second electrode film 37). The main electrode film 35 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film (Cu alloy film) may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 35 has a thickness greater than the thickness (total thickness) of the lower electrode film 34. The thickness of the main electrode film 35 is preferably greater than the thickness of the interlayer film 32.

[0227] The thickness of the main electrode film 35 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 35 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0228] The main electrode film 35 directly covers the lower electrode film 34 (second electrode film 37). The main electrode film 35 backfills the source opening 33 and collectively covers the region of the interlayer film 32 where the source opening 33 is formed. The main electrode film 35 has a portion that covers the interlayer film 32 with the lower electrode film 34 in between, a portion that covers the wall surface of the source opening 33 with the lower electrode film 34 in between, and a portion that covers the first main surface 3 with the lower electrode film 34 in between.

[0229] The main electrode film 35 has a portion that covers the plurality of gate structures 10 with the lower electrode film 34 sandwiched therebetween in the source opening 33, and a portion that covers the plurality of mesa portions 15 with the lower electrode film 34 sandwiched therebetween. The main electrode film 35 covers the plurality of cap insulating films 14 with the lower electrode film 34 sandwiched therebetween, and is electrically isolated from the plurality of buried electrodes 13. In this embodiment, the main electrode film 35 may be connected to the lower electrode film 34 above the first main surface 3.

[0230] Of course, the main electrode film 35 may enter the plurality of trenches 11 from above the first main surface 3 and cover the plurality of cap insulating films 14 within the plurality of trenches 11 with the lower electrode film 34 sandwiched therebetween. In this case, the main electrode film 35 may have a portion that covers the opening ends and sidewalls of the plurality of trenches 11 with the lower electrode film 34 sandwiched therebetween in a region on the bottom wall side of the plurality of trenches 11 with respect to the height position of the first main surface 3.

[0231] The main electrode film 35, in a portion covering the opening ends and sidewalls of the plurality of trenches 11, is electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23 via the lower electrode film 34. The main electrode film 35, in a portion covering the plurality of mesa portions 15, is mechanically and electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23 via the lower electrode film 34.

[0232] The semiconductor device 1A includes one or more (multiple in this embodiment) gate openings 38 formed in the interlayer film 32. The multiple gate openings 38 penetrate the interlayer film 32 and selectively expose the multiple gate wirings 31. In this embodiment, the multiple gate openings 38 extend in a strip shape following the extension direction of the multiple gate wirings 31.

[0233] Of course, the gate openings 38 may be formed at intervals along the extension direction of the gate wirings 31. The gate openings 38 may be formed in a polygonal or circular shape in a plan view. For example, the gate structures 10 may be formed in a quadrangular or hexagonal shape in a plan view.

[0234] The plurality of gate openings 38 may have a portion extending in a band shape in the first direction X in a plan view and a portion extending in a band shape in the second direction Y. The plurality of gate openings 38 may have an edge portion connecting the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.

[0235] The semiconductor device 1A includes a gate terminal GT disposed on the first main surface 3. The gate terminal GT may also be referred to as a "second pad electrode," a "second main surface electrode," a "gate terminal electrode," or the like. The gate terminal GT is disposed on the interlayer film 32 at a distance from the source terminal ST.

[0236] In this embodiment, the gate terminal GT is disposed in a region on the third side surface 5C side of the first pad portion STa, and faces the center of the third side surface 5C and the first pad portion STa in the first direction X. The gate terminal GT is interposed in a region between the second pad portion STb and the third pad portion STc, and faces both the second pad portion STb and the third pad portion STc in the second direction Y.

[0237] The gate terminal GT is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate terminal GT has a planar area less than the planar area of ​​the source terminal ST. The gate terminal GT has a planar area less than the planar area of ​​the first pad portion STa. The gate terminal GT may also have a planar area less than the planar area of ​​the second pad portion STb (third pad portion STc).

[0238] The gate terminal GT faces the plurality of gate structures 10 with the interlayer film 32 sandwiched therebetween. Specifically, the gate terminal GT is disposed inwardly from both ends of the plurality of gate structures 10 with a gap therebetween, and faces the inner portions of the plurality of gate structures 10 with the interlayer film 32 sandwiched therebetween. The portion of the plurality of gate structures 10 located at the gate terminal GT may be removed. In this case, the gate terminal GT may face at least one of the drift region 7, the body region 21, and the outer well region 27 with the main surface insulating film 30 and the interlayer film 32 sandwiched therebetween.

[0239] Although not shown in the figure, the gate terminal GT, like the source terminal ST, includes a lower electrode film 34 and a main electrode film 35 that are laminated in this order from the side of the interlayer film 32. In this embodiment, the lower electrode film 34 has a laminated structure that includes a first electrode film 36 and a second electrode film 37.

[0240] The semiconductor device 1A includes a gate finger electrode 39 extending from the gate terminal GT onto the first main surface 3. The gate finger electrode 39 may be referred to as a "gate finger" or the like. The gate finger electrode 39 transmits the gate potential applied to the gate terminal GT to other regions.

[0241] The gate finger electrode 39 is drawn out from the gate terminal GT onto a portion of the interlayer film 32 that covers the multiple gate wirings 31. The gate finger electrode 39 is routed in a strip-like manner in the region between the periphery of the first main surface 3 and the source terminal ST. The gate finger electrode 39 has a portion that extends in a strip-like manner in the first direction X and a portion that extends in a strip-like manner in the second direction Y in plan view.

[0242] In this embodiment, the gate finger electrode 39 is formed in a strip shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source terminal ST. The gate finger electrode 39 is disposed closer to the periphery of the first main surface 3 than both ends of the multiple gate structures 10.

[0243] The gate finger electrode 39 penetrates into the plurality of gate openings 38 from above the interlayer film 32, and is mechanically and electrically connected to the plurality of gate wirings 31 within the plurality of gate openings 38. As a result, the gate potential applied to the gate terminal GT is applied to the plurality of gate structures 10 via the gate finger electrode 39.

[0244] The gate finger electrode 39 is drawn out from above the plurality of gate wirings 31 toward the peripheral edge of the first main surface 3, and has a portion facing the outer well region 27 in a region outside the plurality of gate wirings 31, with the main surface insulating film 30 and the interlayer film 32 sandwiched between them. The peripheral portion of the gate finger electrode 39 may be located closer to the peripheral edge of the first main surface 3 than the outer edge of the outer well region 27, or may be located closer to the plurality of gate wirings 31 than the outer edge of the outer well region 27.

[0245] In this embodiment, the gate finger electrode 39 has a laminated structure including a lower electrode film 34 and a main electrode film 35 laminated in this order from the chip 2 side, similar to the source terminal ST. In this embodiment, the lower electrode film 34 has a laminated structure including a first electrode film 36 and a second electrode film 37.

[0246] The first electrode film 36 collectively covers the region of the interlayer film 32 where the multiple gate openings 38 are formed, and extends into the multiple gate openings 38 from above the interlayer film 32. The first electrode film 36 has a portion that covers the insulating main surface of the interlayer film 32 in a film-like manner, a portion that covers the wall surfaces of the multiple gate openings 38 in a film-like manner, and a portion that covers the multiple gate wirings 31 in the multiple gate openings 38. The first electrode film 36 is mechanically and electrically connected to the multiple gate wirings 31 in the multiple gate openings 38.

[0247] The second electrode film 37 directly covers the first electrode film 36. The second electrode film 37 collectively covers the region of the interlayer film 32 where the multiple gate openings 38 are formed, sandwiching the first electrode film 36 therebetween, and extends from above the interlayer film 32 into the multiple gate openings 38.

[0248] The second electrode film 37 has a portion that covers the interlayer film 32 in a film state with the first electrode film 36 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of gate openings 38 in a film state with the first electrode film 36 sandwiched therebetween, and a portion that covers the first main surface 3 in a film state with the first electrode film 36 sandwiched therebetween within the plurality of gate openings 38. The second electrode film 37 is electrically connected to the plurality of gate wirings 31 with the first electrode film 36 sandwiched therebetween within the plurality of gate openings 38.

[0249] The main electrode film 35 directly covers the lower electrode film 34 (second electrode film 37). The main electrode film 35 backfills the gate openings 38, and collectively covers the region of the interlayer film 32 where the gate openings 38 are formed.

[0250] The main electrode film 35 has a portion that covers the interlayer film 32 with the lower electrode film 34 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of gate openings 38 with the lower electrode film 34 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 34 sandwiched therebetween. The main electrode film 35 is electrically connected to the plurality of gate wirings 31 within the plurality of gate openings 38 with the lower electrode film 34 sandwiched therebetween.

[0251] The semiconductor device 1A includes a drain terminal DT covering the second main surface 4. The drain terminal DT may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like. The drain terminal DT is electrically connected to the base region 6. The drain terminal DT forms ohmic contact with the base region 6.

[0252] The drain terminal DT may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain terminal DT may also cover part of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0253] A breakdown voltage that can be applied between the source terminal ST and the drain terminal DT (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0254] As described above, the semiconductor device 1A includes the chip 2, the n-type (first conductivity type) drift region 7 (semiconductor region), the trench gate structure 10, the n-type rectification region 20, and the source terminal ST (main surface electrode). The chip 2 has a first main surface 3. The drift region 7 is formed in a surface layer portion of the first main surface 3.

[0255] The gate structure 10 is formed on the first main surface 3 and is located within the drift region 7. The rectification region 20 is formed in a surface layer portion of the first main surface 3 adjacent to the gate structure 10. The source terminal ST is electrically isolated from the gate structure 10 on the first main surface 3 and forms a Schottky junction with the rectification region 20.

[0256] This configuration provides a semiconductor device 1A having a novel layout. For example, in this semiconductor device 1A, a Schottky barrier diode (second diode D2) having a relatively small threshold voltage (second threshold voltage Vth2) due to a Schottky barrier is formed by the rectification region 20 and the source terminal ST.

[0257] As a result, when a reverse voltage is applied to the chip 2 (drift region 7), the Schottky barrier diode quickly turns on, and the reverse current caused by the reverse voltage is quickly processed. This configuration is effective in suppressing the expansion of stacking faults in the chip 2 caused by the reverse current and the increase in on-resistance caused by the expansion of stacking faults.

[0258] The chip 2 may include SiC. This configuration provides a semiconductor device 1A as a SiC semiconductor device having a novel layout. In this semiconductor device 1A, the source terminal ST forms a SiC Schottky barrier diode together with the rectification region 20.

[0259] Since SiC semiconductor devices are used under high-load conditions with high voltages and currents, they are prone to generate relatively high reverse voltages and relatively large reverse currents. In this regard, SiC Schottky barrier diodes can quickly process relatively large reverse currents.

[0260] The gate structure 10 may include a trench 11, an insulating film 12, and a buried electrode 13. The trench 11 may be formed on the first main surface 3. The insulating film 12 may cover the wall surface of the trench 11. The buried electrode 13 may be buried in the trench 11 with the insulating film 12 sandwiched between them. In this case, the rectification region 20 may face the buried electrode 13 with the insulating film 12 sandwiched between them.

[0261] According to this configuration, the rectification region 20 is properly electrically separated from the gate structure 10. This allows a Schottky barrier diode to be properly formed between the rectification region 20 and the source terminal ST.

[0262] The gate structure 10 may include a cap insulating film 14. In this case, the buried electrode 13 may be buried in the trench 11 at a distance from the height position of the first main surface 3 toward the bottom wall of the trench 11. The cap insulating film 14 may cover the buried electrode 13 within the trench 11. In this case, the rectification region 20 may have a portion facing the cap insulating film 14 within the chip 2. The source terminal ST may be covered with the cap insulating film 14 and electrically isolated from the buried electrode 13 by the cap insulating film 14.

[0263] According to this configuration, the breakdown voltage on the opening end side of the gate structure 10 can be improved by the cap insulating film 14. As a result, when the Schottky barrier diode is in an on-state, a decrease in the breakdown voltage due to electric field concentration near the opening end of the gate structure 10 is suppressed.

[0264] The cap insulating film 14 may have an insulating surface located on the bottom wall side of the trench 11 with respect to the height position of the first main surface 3. In this case, the source terminal ST may be in contact with the insulating surface of the cap insulating film 14 within the trench 11. This configuration makes it possible to increase the connection area of ​​the source terminal ST with respect to the rectification region 20. This allows the current path of the Schottky barrier diode to be appropriately expanded.

[0265] The rectification region 20 may have a portion exposed from the sidewall of the trench 11. In this case, the source terminal ST may have a portion covering the sidewall of the trench 11 within the trench 11, and may form a Schottky junction with the rectification region 20 on the sidewall of the trench 11. With this configuration, the formation area of ​​the Schottky diode can be expanded into the trench 11.

[0266] The rectification region 20 may be formed on the side of the gate structure 10 over the entire depth range of the gate structure 10. With this configuration, a current path of the Schottky barrier diode can be formed on the side of the gate structure 10 over the entire depth range of the gate structure 10. The rectification region 20 may be made of a part of the drift region 7. With this configuration, the rectification region 20 can be formed by utilizing a part of the drift region 7.

[0267] The semiconductor device 1A may include a p-type (second conductivity type) body region 21. The body region 21 may be formed in a surface layer portion of the first main surface 3 adjacent to the gate structure 10 so as to be adjacent to the rectification region 20. The body region 21 may form a pn junction with the drift region 7. In this case, the source terminal ST may be electrically connected to the body region 21 on the first main surface 3.

[0268] According to this configuration, a pn junction diode (first diode D1) having a relatively large threshold voltage (first threshold voltage Vth1) is formed by the drift region 7 and the body region 21. When a reverse bias voltage is applied, the pn junction diode (body region 21) emits holes as a reverse current into the drift region 7. The expansion of stacking faults in the chip 2 may be caused by these holes.

[0269] In this regard, in the semiconductor device 1A, a Schottky barrier diode having a threshold voltage lower than that of the pn junction diode can be formed by the rectification region 20 and the source terminal ST. Therefore, when a reverse bias voltage is applied, the Schottky barrier diode turns on before the pn junction diode turns on, thereby suppressing the emission of holes caused by the pn junction diode (body region 21). This appropriately suppresses the expansion of stacking faults in the chip 2 caused by the reverse current (holes) and the increase in on-resistance caused by the expansion of stacking faults.

[0270] The semiconductor device 1A may include an n-type source region 22. The source region 22 may be formed in a region along the gate structure 10 in a surface layer portion of the body region 21. The source region 22 may face the rectification region 20 along a wall surface of the gate structure 10. According to this configuration, a channel of the transistor structure Tr can be formed in a region facing the rectification region 20 along the wall surface of the gate structure 10.

[0271] The semiconductor device 1A may include a p-type (second conductivity type) body region 21. The body region 21 may be formed in a surface layer portion of the first main surface 3 adjacent to the gate structure 10 in a region on the opposite side of the gate structure 10 from the rectification region 20. The body region 21 may form a pn junction with the drift region 7. In this case, the source terminal ST may be electrically connected to the body region 21 on the first main surface 3.

[0272] This configuration can appropriately suppress the expansion of stacking faults in the chip 2 caused by the reverse current (holes) and the increase in on-resistance caused by the expansion of stacking faults. In this configuration, the body region 21 may or may not face the rectification region 20 across the gate structure 10.

[0273] In these cases, the semiconductor device 1A may include an n-type source region 22. The source region 22 may be formed in a region along the gate structure 10 in a surface layer portion of the body region 21. With this configuration, a channel of the transistor structure Tr can be formed in a region on the opposite side of the gate structure 10 from the rectification region 20. In this case, the source region 22 may or may not face the rectification region 20 across the gate structure 10.

[0274] The semiconductor device 1A may include a p-type deep well region 24 (impurity region). The deep well region 24 may be formed in a region below the gate structure 10 in the chip 2 and electrically connected to the drift region 7. When a reverse bias voltage is applied, the deep well region 24 emits holes into the drift region 7 as a reverse current. The expansion of stacking faults in the chip 2 may be caused by these holes.

[0275] In this regard, in the semiconductor device 1A, a Schottky barrier diode having a relatively low threshold voltage is formed by the rectification region 20 and the source terminal ST. Therefore, the emission of holes caused by the deep well region 24 is suppressed. This makes it possible to appropriately suppress the expansion of stacking faults in the chip 2 caused by the reverse current (holes) and the increase in on-resistance caused by the expansion of stacking faults.

[0276] The semiconductor device 1A may include a p-type contact region 23. The contact region 23 may be formed along the gate structure 10 in a surface layer portion of the first main surface 3. In this case, the source terminal ST may be electrically connected to the contact region 23 on the first main surface 3.

[0277] The semiconductor device 1A may include a p-type well region 26. The well region 26 may be formed along one or both of the sidewall and the bottom wall of the gate structure 10 in the chip 2. The well region 26 may have one or both of a portion electrically connected to the body region 21 and a portion electrically connected to the deep well region 24.

[0278] The well region 26 may electrically connect the deep well region 24 to the body region 21. According to this configuration, the electrical response speed of the deep well region 24 is increased by the well region 26. The well region 26 may have a portion electrically connected to the contact region 23.

[0279] From another perspective, the semiconductor device 1A may include a chip 2, an n-type (first conductivity type) drift region 7 (semiconductor region), a trench-type gate structure 10, an n-type rectification region 20, a p-type (second conductivity type) body region 21, and a source terminal ST (main surface electrode). The chip 2 may have a first main surface 3. The drift region 7 may be formed in a surface layer portion of the first main surface 3.

[0280] The gate structure 10 may be formed on the first main surface 3 and located within the drift region 7. The rectification region 20 may be formed in a surface layer portion of the first main surface 3 along the gate structure 10. The body region 21 may be formed in a surface layer portion of the first main surface 3 along the gate structure 10. The source terminal ST may be electrically separated from the gate structure 10 on the first main surface 3, electrically connected to the body region 21, and form a Schottky junction with the rectification region 20.

[0281] This configuration allows for the formation of a semiconductor device 1A including a pn junction diode and a Schottky barrier diode. The pn junction diode is formed by the drift region 7 and the body region 21 and may have a relatively large first threshold voltage Vth1. The Schottky barrier diode is formed by the rectification region 20 and the source terminal and may have a second threshold voltage Vth2 that is less than the first threshold voltage Vth1.

[0282] For example, when a reverse voltage is applied to the chip 2 (drift region 7), the pn junction diode (body region 21) emits holes as a reverse current into the drift region 7. The expansion of stacking faults in the chip 2 may be caused by such holes.

[0283] In contrast, in the case of the semiconductor device 1A, when a reverse bias voltage is applied, the Schottky barrier diode turns on before the pn junction diode turns on, thereby suppressing the emission of holes caused by the pn junction diode (body region 21). This makes it possible to appropriately suppress the expansion of stacking faults in the chip 2 caused by the reverse current (holes) and the increase in on-resistance caused by the expansion of stacking faults.

[0284] The chip 2 may include SiC. This configuration provides a semiconductor device 1A as a SiC semiconductor device with a novel layout. In this semiconductor device 1A, the source terminal ST forms a SiC Schottky barrier diode with the rectification region 20. SiC semiconductor devices are used under high-load environments with high voltages and large currents, and therefore are prone to relatively high reverse voltages and relatively large reverse currents. In this regard, the SiC Schottky barrier diode quickly processes a relatively large reverse current.

[0285] The gate structure 10 may extend in a strip shape in one direction (second direction Y). The rectification region 20 may be adjacent to the gate structure 10. The body region 21 may be adjacent to the rectification region 20 in one direction.

[0286] The semiconductor device 1A may include an n-type source region 22. The source region 22 may be formed in a surface layer portion of the body region 21 so as to face the rectification region 20 in one direction. The source region 22 may have a length in one direction that is greater than the length of the rectification region 20.

[0287] The semiconductor device 1A may include a p-type contact region 23. The contact region 23 may be formed in a surface layer portion of the body region 21. The contact region 23 may have a length in one direction that is shorter than the length of the rectification region 20. The contact region 23 may have a length in one direction that is shorter than the length of the source region 22.

[0288] The semiconductor device 1A may include a p-type deep well region 24 (impurity region). The deep well region 24 may be formed in a region below the gate structure 10 within the chip 2. The deep well region 24 may extend in a strip shape in one direction. The deep well region 24 may have a length in one direction that is greater than the length of the rectification region 20.

[0289] The semiconductor device 1A may include a p-type well region 26. The well region 26 may be formed along the sidewalls and bottom wall of the gate structure 10 in the chip 2. The well region 26 may have a length in one direction that is shorter than the length of the rectification region 20. The well region 26 may have a length in one direction that is shorter than the length of the source region 22.

[0290] Fig. 15 is an enlarged plan view showing a main portion of the active region 8 of a semiconductor device 1B according to the second embodiment. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 15. Fig. 17 is a cross-sectional view taken along line XVII-XVII in Fig. 15. The semiconductor device 1B has a layout that is a modification of the layout within the multiple mesas 15 in the semiconductor device 1A.

[0291] In this embodiment, the rectification regions 20 are arranged in a staggered pattern in a plan view. That is, the rectification regions 20 on one side in the first direction X face regions between the rectification regions 20 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them.

[0292] The multiple rectification regions 20 on one side may be arranged offset in the second direction Y so as not to face the rectification regions 20 on the other side in the first direction X. Of course, the multiple rectification regions 20 on one side may face a part of the rectification region 20 on the other side in the first direction X (for example, one end in the second direction Y or the other end in the second direction Y).

[0293] In this embodiment, the body regions 21 are arranged in a staggered pattern in a plan view in accordance with the arrangement of the rectification regions 20. That is, the body regions 21 on one side in the first direction X face regions between the body regions 21 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them. The body regions 21 on one side in the first direction X face regions between the rectification regions 20 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them.

[0294] In this embodiment, the multiple body regions 21 on one side face, in the first direction X, one rectification region 20, one end of the body region 21 on one side in the second direction Y, and the other end of the body region 21 on the other side in the second direction Y. Of course, the multiple body regions 21 on one side may be arranged shifted in the second direction Y with respect to the multiple body regions 21 on the other side so as to face only one rectification region 20 in the first direction X.

[0295] In this embodiment, the multiple source regions 22 are arranged in a staggered pattern in plan view in accordance with the arrangement of the multiple rectification regions 20 and the multiple body regions 21. That is, the multiple source regions 22 on one side in the first direction X face regions between the multiple source regions 22 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them. The multiple source regions 22 on one side in the first direction X face regions between the multiple rectification regions 20 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them.

[0296] In this embodiment, the multiple source regions 22 on one side face, in the first direction X, one rectification region 20, one end of the body region 21 on one side in the second direction Y, and the other end of the body region 21 on the other side in the second direction Y. Of course, the multiple source regions 22 on one side may be arranged shifted in the second direction Y with respect to the multiple source regions 22 on the other side so as to face only one rectification region 20 in the first direction X.

[0297] In this embodiment, the multiple contact regions 23 are arranged in a staggered pattern in a plan view in accordance with the arrangement of the multiple rectification regions 20 and the multiple body regions 21. That is, the multiple contact regions 23 on one side in the first direction X each face a region between the multiple contact regions 23 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them. The multiple contact regions 23 on one side in the first direction X each face a region between the multiple rectification regions 20 on the other side in the first direction X, with a corresponding gate structure 10 sandwiched between them.

[0298] In this embodiment, the multiple contact regions 23 on one side face one rectification region 20 in the first direction X. Of course, the multiple contact regions 23 on one side may be arranged shifted in the second direction Y so as not to face one rectification region 20 in the first direction X. In this case, the multiple contact regions 23 on one side may face multiple source regions 22 on the other side across one corresponding gate structure 10.

[0299] As in the case of the semiconductor device 1A, the multiple well regions 26 are formed in a one-to-many correspondence with the multiple gate structures 10, and are interposed in regions between the multiple contact regions 23 in the first direction X. The multiple well regions 26 have first portions 26a along the bottom walls of the corresponding gate structures 10 and second portions 26b along the sidewalls of the corresponding gate structures 10 on the contact region 23 side. In this embodiment, the multiple well regions 26 do not have portions along the sidewalls of the corresponding gate structures 10 on the rectification region 20 side.

[0300] The first portion 26a extends along the bottom wall of the corresponding gate structure 10. In this embodiment, the first portion 26a is formed at a distance from the sidewall of the corresponding gate structure 10 on the contact region 23 side in a cross-sectional view, and extends horizontally along part of the bottom wall of the corresponding gate structure 10. In other words, the first portion 26a is not formed so as to extend along the entire bottom wall of the corresponding gate structure 10 in a cross-sectional view. Of course, the first portion 26a may be formed along the entire bottom wall of the corresponding gate structure 10 in a cross-sectional view.

[0301] The first portion 26a is connected to the upper end of the corresponding deep well region 24. In other words, the first portion 26a is electrically connected to the deep well region 24 and increases the p-type impurity concentration at the upper end of the deep well region 24. The first portion 26a has a bottom located closer to the bottom wall of the gate structure 10 than the bottom of the deep well region 24. The bottom of the first portion 26a is preferably located closer to the bottom wall of the gate structure 10 than the depth position of the intermediate portion of the deep well region 24.

[0302] The second portions 26b extend from the first portions 26a along the sidewalls of the corresponding gate structures 10 on the contact region 23 side. The second portions 26b are connected to the corresponding body regions 21 on the first main surface 3 side, and are connected to the first portions 26a on the bottom wall side of the corresponding gate structures 10. In this way, the multiple second portions 26b electrically connect the corresponding deep well regions 24 to the corresponding body regions 21.

[0303] In this embodiment, the second portion 26b is connected to the corresponding contact region 23 in the surface layer portion of the corresponding body region 21. In this embodiment, the second portion 26b is formed integrally with the corresponding contact region 23. That is, the second portion 26b electrically connects the corresponding deep well region 24 to the corresponding contact region 23. The second portion 26b has a thickness smaller than that of the first portion 26a.

[0304] Fig. 18 is an enlarged plan view showing a main portion of the active region 8 of a semiconductor device 1C according to the third embodiment. Fig. 19 is a cross-sectional view taken along line XIX-XIX in Fig. 18. Fig. 20 is a cross-sectional view taken along line XX-XX in Fig. 18. The semiconductor device 1C has a layout that is a modification of the layout within the multiple mesas 15 in the semiconductor device 1A.

[0305] In this embodiment, the multiple mesas 15 include one or more (multiple in this embodiment) first mesas 15A for the second diode D2 and one or more (multiple in this embodiment) second mesas 15B for the transistor structure Tr. The multiple first mesas 15A are provided at intervals in the first direction X so as to sandwich the one or more (one in this embodiment) mesa 15 therebetween.

[0306] The second mesas 15B are provided on all of the mesas 15 except for the first mesas 15A. In this embodiment, the second mesas 15B are provided at intervals in the first direction X so as to sandwich one or more (one in this embodiment) first mesas 15A therebetween. In this embodiment, the second mesas 15B and the first mesas 15A are arranged alternately in the first direction X.

[0307] The multiple rectification regions 20 are formed in the surface layer portion of the first main surface 3 in the multiple first mesas 15A, but are not formed in the multiple second mesas 15B. The multiple rectification regions 20 are formed over the entire areas of the multiple first mesas 15A in a plan view. The multiple rectification regions 20 extend in a strip shape in the second direction Y following the extension direction of the multiple first mesas 15A, and are adjacent to the multiple gate structures 10 in the first direction X. As in the case of the semiconductor device 1A, the multiple rectification regions 20 are formed over the entire depth range of the multiple gate structures 10.

[0308] In this embodiment, the body regions 21 are formed in the surface layer portions of the first main surface 3 in the second mesas 15B, but are not formed in the first mesas 15A. The body regions 21 extend in a strip shape in the second direction Y following the extension direction of the second mesas 15B, and are adjacent to the gate structures 10 in the first direction X.

[0309] The body regions 21 are formed at intervals inward from both ends of the gate structures 10 in the second direction Y. Of course, the body regions 21 may be formed over the entire areas of the second mesas 15B in plan view.

[0310] In this embodiment, the source regions 22 are formed in the surface layer portions of the corresponding body regions 21 in the second mesas 15B, but are not formed in the first mesas 15A. In this embodiment, the source regions 22 are formed in a one-to-one correspondence with the body regions 21, respectively. Of course, the source regions 22 may also be formed at intervals in the second direction Y in the surface layer portions of the corresponding body regions 21.

[0311] The plurality of source regions 22 extend in a strip shape in the second direction Y following the extension direction of the corresponding body regions 21 in a plan view, and are adjacent to the plurality of gate structures 10 in the first direction X. In other words, the plurality of source regions 22 face the rectification region 20 in the first direction X with the corresponding gate structures 10 interposed therebetween. The plurality of source regions 22 may be formed at intervals inward from both end portions of the corresponding body regions 21 in the second direction Y.

[0312] The plurality of contact regions 23 are formed in the plurality of first mesas 15A and the plurality of second mesas 15B, respectively, in the surface layer portion of the first main surface 3. The plurality of contact regions 23 include one or more (plurality in this embodiment) first contact regions 23A formed in a corresponding one of the first mesa portions 15A, and one or more (plurality in this embodiment) second contact regions 23B formed in a corresponding one of the second mesa portions 15B.

[0313] The multiple first contact regions 23A are formed in the multiple first mesas 15A at intervals in the second direction Y. The multiple first contact regions 23A divide one rectification region 20 in the corresponding first mesa 15A into multiple regions in the second direction Y. The multiple first contact regions 23A are adjacent to the multiple gate structures 10 in the first direction X.

[0314] The second contact regions 23B are formed in the second mesas 15B at intervals in the second direction Y. The second contact regions 23B divide one source region 22 into a plurality of regions in the second direction Y in the surface layer portion of the corresponding body region 21.

[0315] Of course, when a plurality of source regions 22 are formed at intervals in the second direction Y in the surface layer portion of a corresponding one body region 21, the plurality of second contact regions 23B may be formed in regions between the plurality of source regions 22. The plurality of second contact regions 23B are adjacent to the plurality of gate structures 10 in the first direction X.

[0316] In this embodiment, the plurality of second contact regions 23B face the plurality of first contact regions 23A in a one-to-one correspondence in the first direction X, with the corresponding gate structures 10 sandwiched between them. In other words, the plurality of first contact regions 23A and the plurality of second contact regions 23B are formed in a matrix in plan view.

[0317] In this embodiment, the multiple well regions 26 are respectively interposed in regions between the multiple first contact regions 23A and the multiple second contact regions 23B adjacent to each other in the first direction X. The multiple well regions 26 are arranged in a line with the multiple first contact regions 23A and the multiple second contact regions 23B in the first direction X. The multiple well regions 26 are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0318] Similar to the semiconductor device 1A, the multiple well regions 26 include a first portion 26 a and multiple second portions 26 b. The multiple second portions 26 b include the second portion 26 b on the first mesa portion 15A side and the second portion 26 b on the second mesa portion 15B side.

[0319] The second portion 26b on the first mesa portion 15A side extends in the thickness direction along the sidewall on the first mesa portion 15A side of the corresponding gate structure 10. The second portion 26b on the first mesa portion 15A side is connected to the corresponding first contact region 23A on the first main surface 3 side of the first mesa portion 15A, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the first mesa portion 15A side electrically connects the corresponding deep well region 24 to the corresponding first contact region 23A.

[0320] The second portion 26b on the second mesa portion 15B side extends in the thickness direction along the sidewall on the second mesa portion 15B side of the corresponding gate structure 10. The second portion 26b on the second mesa portion 15B side is connected to the corresponding body region 21 on the first main surface 3 side of the second mesa portion 15B, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the corresponding body region 21.

[0321] In this embodiment, the second portion 26b on the second mesa portion 15B side is connected to the corresponding second contact region 23B in the surface layer portion of the corresponding body region 21. In this embodiment, the second portion 26b on the second mesa portion 15B side is formed integrally with the corresponding second contact region 23B.

[0322] That is, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the plurality of contact regions 23. As a result, the well region 26 electrically connects the plurality of second contact regions 23B to the plurality of first contact regions 23A.

[0323] Fig. 21 is an enlarged plan view showing a main portion of the active region 8 of a semiconductor device 1D according to the fourth embodiment. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 21. Fig. 23 is a cross-sectional view taken along line XXIII-XXIII in Fig. 21. The semiconductor device 1D has a layout that is a modification of the layout within the multiple mesas 15 in the semiconductor device 1A.

[0324] In this embodiment, the multiple mesas 15 include one or more (multiple in this embodiment) first mesas 15A for the second diode D2 and one or more (multiple in this embodiment) second mesas 15B for the transistor structure Tr. The multiple first mesas 15A are provided at intervals in the first direction X so as to sandwich the multiple mesas 15 (two in this embodiment, for example).

[0325] The second mesas 15B are provided in all of the mesas 15 except for the first mesas 15A. The second mesas 15B are provided adjacent to each other in the first direction X in regions between the first mesas 15A. This results in mesa groups MG, each including a plurality of second mesas 15B, being provided in regions between the first mesas 15A. The mesa groups MG are arranged alternately with the first mesas 15A in the first direction X.

[0326] In this embodiment, the multiple rectification regions 20 are formed in the surface layer portion of the first main surface 3 in the multiple first mesas 15A, but are not formed in the multiple second mesas 15B. The multiple rectification regions 20 are formed over the entire areas of the multiple first mesas 15A in a plan view. The multiple rectification regions 20 extend in a strip shape in the second direction Y following the extension direction of the multiple first mesas 15A, and are adjacent to the multiple gate structures 10 in the first direction X. As in the case of the semiconductor device 1A, the multiple rectification regions 20 are formed over the entire depth range of the multiple gate structures 10.

[0327] In this embodiment, the body regions 21 are formed in the surface layer portions of the first main surface 3 in the second mesas 15B, but are not formed in the first mesas 15A. The body regions 21 extend in a strip shape in the second direction Y following the extension direction of the second mesas 15B, and are adjacent to the gate structures 10 in the first direction X.

[0328] The body regions 21 are formed at intervals inward from both ends of the gate structures 10 in the second direction Y. Of course, the body regions 21 may be formed over the entire areas of the second mesas 15B in plan view.

[0329] Focusing on the three gate structures 10 (one gate structure 10, the central gate structure 10, and the other gate structure 10) that define the two second mesa portions 15B, one body region 21 faces the rectification region 20 in the first direction X across one gate structure 10, and faces the other body region 21 in the first direction X across the central gate structure 10.

[0330] Similarly, the other body region 21 faces the rectification region 20 in the first direction X with the other gate structure 10 interposed therebetween, and faces one body region 21 in the first direction X with the central gate structure 10 interposed therebetween.

[0331] In this embodiment, the source regions 22 are formed in the surface layer portions of the corresponding body regions 21 in the second mesas 15B, but are not formed in the first mesas 15A. In this embodiment, the source regions 22 are formed in a one-to-one correspondence with the body regions 21, respectively. Of course, the source regions 22 may also be formed at intervals in the second direction Y in the surface layer portions of the corresponding body regions 21.

[0332] The plurality of source regions 22 extend in a strip shape in the second direction Y following the extension direction of the corresponding body regions 21 in a plan view, and are adjacent to the plurality of gate structures 10 in the first direction X. The plurality of source regions 22 may be formed at intervals inward from both end portions of the corresponding body regions 21 in the second direction Y.

[0333] Focusing on the three gate structures 10 (one gate structure 10, the central gate structure 10, and the other gate structure 10) that define the two second mesa portions 15B, one source region 22 faces the rectification region 20 in the first direction X across one gate structure 10, and faces the other source region 22 in the first direction X across the central gate structure 10.

[0334] Similarly, the other source region 22 faces the rectification region 20 in the first direction X with the other gate structure 10 interposed therebetween, and faces one source region 22 in the first direction X with the central gate structure 10 interposed therebetween.

[0335] The plurality of contact regions 23 are formed in the plurality of first mesas 15A and the plurality of second mesas 15B, respectively, in the surface layer portion of the first main surface 3. The plurality of contact regions 23 include one or more (plurality in this embodiment) first contact regions 23A formed in a corresponding one of the first mesa portions 15A, and one or more (plurality in this embodiment) second contact regions 23B formed in a corresponding one of the second mesa portions 15B.

[0336] The multiple first contact regions 23A are formed in the multiple first mesas 15A at intervals in the second direction Y. The multiple first contact regions 23A divide one rectification region 20 into multiple regions in the second direction Y in the corresponding first mesa 15A, and are adjacent to the multiple gate structures 10 in the first direction X.

[0337] The second contact regions 23B are formed in the second mesas 15B at intervals in the second direction Y. In this embodiment, the second contact regions 23B have a p-type impurity concentration higher than the n-type impurity concentration of the source regions 22, and convert the conductivity type of the source regions 22 from n-type to p-type.

[0338] Of course, when a plurality of source regions 22 are formed at intervals in the second direction Y in the surface layer portion of a corresponding one body region 21, the plurality of second contact regions 23B may be formed in regions between the plurality of source regions 22. The plurality of second contact regions 23B are adjacent to the plurality of gate structures 10 in the first direction X.

[0339] In a plan view, the multiple second contact regions 23B face the multiple first contact regions 23A in the first direction X. That is, the multiple first contact regions 23A and the multiple second contact regions 23B are formed in a matrix in a plan view.

[0340] Focusing on the three gate structures 10 (one gate structure 10, the central gate structure 10, and the other gate structure 10) that define the two second mesa portions 15B, one second contact region 23B faces the first contact region 23A in the first direction X across one gate structure 10, and faces the other second contact region 23B in the first direction X across the central gate structure 10.

[0341] Similarly, the other second contact region 23B faces the first contact region 23A in the first direction X across the other gate structure 10, and faces one second contact region 23B in the first direction X across the central gate structure 10.

[0342] In this embodiment, the multiple well regions 26 are respectively interposed in regions between the multiple contact regions 23 adjacent to each other in the first direction X. Specifically, the multiple well regions 26 include a multiple first well regions 26A and a multiple second well regions 26B.

[0343] The multiple first well regions 26A are respectively interposed in regions between the multiple first contact regions 23A and the multiple second contact regions 23B adjacent to each other in the first direction X. The multiple first well regions 26A are arranged in a line with the multiple first contact regions 23A and the multiple second contact regions 23B in the first direction X. The multiple first well regions 26A are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0344] Similar to the semiconductor device 1A, the plurality of first well regions 26A include a first portion 26a and a plurality of second portions 26b. The plurality of second portions 26b include the second portion 26b on the first mesa portion 15A side and the second portion 26b on the second mesa portion 15B side.

[0345] The second portion 26b on the first mesa portion 15A side extends in the thickness direction along the sidewall on the first mesa portion 15A side of the corresponding gate structure 10. The second portion 26b on the first mesa portion 15A side is connected to the corresponding first contact region 23A on the first main surface 3 side of the first mesa portion 15A, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the first mesa portion 15A side electrically connects the corresponding deep well region 24 to the corresponding first contact region 23A.

[0346] The second portion 26b on the second mesa portion 15B side extends in the thickness direction along the sidewall on the second mesa portion 15B side of the corresponding gate structure 10. The second portion 26b on the second mesa portion 15B side is connected to the corresponding body region 21 on the first main surface 3 side of the second mesa portion 15B, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the corresponding body region 21.

[0347] In this embodiment, the second portion 26b on the second mesa portion 15B side is connected to the corresponding second contact region 23B in the surface layer portion of the corresponding body region 21. In this embodiment, the second portion 26b on the second mesa portion 15B side is formed integrally with the corresponding second contact region 23B.

[0348] That is, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the plurality of contact regions 23. Furthermore, the plurality of first well regions 26A electrically connects the plurality of second contact regions 23B to the plurality of first contact regions 23A.

[0349] The plurality of second well regions 26B are respectively interposed in regions between the plurality of second contact regions 23B adjacent to each other in the first direction X. The plurality of second well regions 26B are arranged in a line with the plurality of first contact regions 23A, the plurality of second contact regions 23B, and the plurality of first well regions 26A in the first direction X. The plurality of second well regions 26B are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0350] Similar to the semiconductor device 1A, the second well regions 26B include a first portion 26a and a plurality of second portions 26b. The second portions 26b include a second portion 26b on the first mesa portion 15A side and a second portion 26b on the second mesa portion 15B side.

[0351] The plurality of second portions 26b extend in the thickness direction along one sidewall and the other sidewall of the corresponding gate structure 10. The plurality of second portions 26b are connected to the corresponding body region 21 on the first main surface 3 side, and are connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. In this way, the plurality of second portions 26b electrically connect the corresponding deep well region 24 to the body region 21.

[0352] In this embodiment, the second portions 26b are connected to the corresponding second contact regions 23B in the surface layer portions of the corresponding body regions 21. In this embodiment, the second portions 26b are integrally formed with the second contact regions 23B. That is, the second portions 26b electrically connect the corresponding deep well regions 24 to the second contact regions 23B.

[0353] Fig. 24 is an enlarged plan view showing a main portion of the active region 8 of a semiconductor device 1E according to the fifth embodiment. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 24. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI in Fig. 24. The semiconductor device 1E has a layout that is a modification of the layout within the multiple mesas 15 in the semiconductor device 1A.

[0354] In this embodiment, the multiple mesa portions 15 include one or more (multiple in this embodiment) first mesa portions 15A for the second diode D2 and one or more (multiple in this embodiment) second mesa portions 15B for the transistor structure Tr.

[0355] In this embodiment, the multiple mesa portions 15 include multiple mesa groups MG, each including multiple (two in this embodiment, as an example) first mesa portions 15A arranged adjacent to each other in the first direction X. The multiple mesa groups MG are arranged at intervals in the first direction X so as to sandwich one or multiple (one in this embodiment) mesa portions 15 therebetween.

[0356] The second mesa portions 15B are provided in the mesa portions 15 other than the mesa groups MG (first mesa portions 15A) among the mesa portions 15. That is, in this embodiment, the second mesa portions 15B are provided one by one in the regions between the first mesa portions 15A. The second mesa portions 15B and the mesa groups MG are arranged alternately in the first direction X.

[0357] In this embodiment, the multiple rectification regions 20 are formed in the surface layer portions of the first main surface 3 in the multiple first mesas 15A, but are not formed in the multiple second mesas 15B. The multiple rectification regions 20 are formed over the entire areas of the multiple first mesas 15A in a plan view. The multiple rectification regions 20 extend in a strip shape in the second direction Y following the extension direction of the multiple first mesas 15A, and are adjacent to the multiple gate structures 10 in the first direction X.

[0358] Similar to the semiconductor device 1A, the plurality of rectification regions 20 are formed across the entire depth range of the plurality of gate structures 10. The plurality of rectification regions 20 on one side in the first direction X face each other in the first direction X with the corresponding gate structure 10 therebetween.

[0359] In this embodiment, the body regions 21 are formed in the surface layer portions of the first main surface 3 in the second mesas 15B, but are not formed in the first mesas 15A. The body regions 21 extend in a strip shape in the second direction Y following the extension direction of the second mesas 15B, and are adjacent to the gate structures 10 in the first direction X.

[0360] The body regions 21 are formed at intervals inward from both ends of the gate structures 10 in the second direction Y. Of course, the body regions 21 may be formed over the entire areas of the second mesas 15B in plan view.

[0361] Focusing on the two gate structures 10 (one gate structure 10 and the other gate structure 10) that define one second mesa portion 15B, the body region 21 faces the rectification region 20 in the first direction X across one gate structure 10, and faces the rectification region 20 in the first direction X across the other gate structure 10.

[0362] In this embodiment, the source regions 22 are formed in the surface layer portions of the corresponding body regions 21 in the second mesas 15B, but are not formed in the first mesas 15A. In this embodiment, the source regions 22 are formed in a one-to-one correspondence with the body regions 21, respectively. Of course, the source regions 22 may also be formed at intervals in the second direction Y in the surface layer portions of the corresponding body regions 21.

[0363] The plurality of source regions 22 extend in a strip shape in the second direction Y following the extension direction of the corresponding body regions 21 in a plan view, and are adjacent to the plurality of gate structures 10 in the first direction X. The plurality of source regions 22 may be formed at intervals inward from both end portions of the corresponding body regions 21 in the second direction Y.

[0364] Focusing on the two gate structures 10 (one gate structure 10 and the other gate structure 10) that define one second mesa portion 15B, the source region 22 faces the rectification region 20 in the first direction X across one gate structure 10, and faces the rectification region 20 in the first direction X across the other gate structure 10.

[0365] The plurality of contact regions 23 are formed in the plurality of first mesas 15A and the plurality of second mesas 15B, respectively, in the surface layer portion of the first main surface 3. The plurality of contact regions 23 include one or more (plurality in this embodiment) first contact regions 23A formed in a corresponding one of the first mesa portions 15A, and one or more (plurality in this embodiment) second contact regions 23B formed in a corresponding one of the second mesa portions 15B.

[0366] The multiple first contact regions 23A are formed in the multiple first mesas 15A at intervals in the second direction Y. The multiple first contact regions 23A divide one rectification region 20 in the corresponding first mesa 15A into multiple regions in the second direction Y. The multiple first contact regions 23A are adjacent to the multiple gate structures 10 in the first direction X.

[0367] The multiple second contact regions 23B are formed at intervals in the second direction Y in the multiple second mesa portions 15B, and divide one source region 22 into multiple regions in the second direction Y in the surface portion of the corresponding body region 21.

[0368] Of course, when a plurality of source regions 22 are formed at intervals in the second direction Y in the surface layer portion of a corresponding one body region 21, the plurality of second contact regions 23B may be formed in regions between the plurality of source regions 22. The plurality of second contact regions 23B are adjacent to the plurality of gate structures 10 in the first direction X.

[0369] In a plan view, the multiple second contact regions 23B face the multiple first contact regions 23A in the first direction X. That is, the multiple first contact regions 23A and the multiple second contact regions 23B are formed in a matrix in a plan view.

[0370] Focusing on the two gate structures 10 (one gate structure 10 and the other gate structure 10) that define one second mesa portion 15B, the second contact region 23B faces the first contact region 23A in the first direction X across one gate structure 10, and faces the first contact region 23A in the first direction X across the other gate structure 10.

[0371] In this embodiment, the multiple well regions 26 are respectively interposed in regions between the multiple contact regions 23 adjacent to each other in the first direction X. Specifically, the multiple well regions 26 include a multiple first well regions 26A and a multiple second well regions 26B.

[0372] The multiple first well regions 26A are respectively interposed in regions between the multiple first contact regions 23A adjacent to each other in the first direction X. The multiple first well regions 26A are arranged in a line with the multiple first contact regions 23A and the multiple second contact regions 23B in the first direction X. The multiple first well regions 26A are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0373] Similar to the semiconductor device 1A, the plurality of first well regions 26A include a first portion 26a and a plurality of second portions 26b. The plurality of second portions 26b extend in the thickness direction along one sidewall and the other sidewall of the corresponding gate structure 10.

[0374] The second portions 26b are connected to the first contact regions 23A on the first main surface 3 side, and are connected to the first portions 26a on the bottom wall sides of the corresponding gate structures 10. As a result, the second portions 26b electrically connect the corresponding deep well regions 24 to the first contact regions 23A.

[0375] The plurality of second well regions 26B are respectively interposed in regions between the plurality of first contact regions 23A and the plurality of second contact regions 23B adjacent to each other in the first direction X. The plurality of second well regions 26B are arranged in a line with the plurality of first contact regions 23A and the plurality of second contact regions 23B in the first direction X. The plurality of second well regions 26B are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0376] Similar to the semiconductor device 1A, the second well regions 26B include a first portion 26a and a plurality of second portions 26b. The second portions 26b include a second portion 26b on the first mesa portion 15A side and a second portion 26b on the second mesa portion 15B side.

[0377] The second portion 26b on the first mesa portion 15A side extends in the thickness direction along the sidewall on the first mesa portion 15A side of the corresponding gate structure 10. The second portion 26b on the first mesa portion 15A side is connected to the corresponding first contact region 23A on the first main surface 3 side of the first mesa portion 15A, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the first mesa portion 15A side electrically connects the corresponding deep well region 24 to the corresponding first contact region 23A.

[0378] The second portion 26b on the second mesa portion 15B side extends in the thickness direction along the sidewall on the second mesa portion 15B side of the corresponding gate structure 10. The second portion 26b on the second mesa portion 15B side is connected to the corresponding body region 21 on the first main surface 3 side of the second mesa portion 15B, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the corresponding body region 21.

[0379] In this embodiment, the second portion 26b on the second mesa portion 15B side is connected to the corresponding second contact region 23B in the surface layer portion of the corresponding body region 21. In this embodiment, the second portion 26b on the second mesa portion 15B side is formed integrally with the corresponding second contact region 23B.

[0380] That is, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the plurality of contact regions 23. Furthermore, the plurality of second well regions 26B electrically connects the plurality of second contact regions 23B to the plurality of first contact regions 23A.

[0381] Fig. 27 is an enlarged plan view showing a main part of an active region 8 of a semiconductor device 1F according to the sixth embodiment. Fig. 28 is a cross-sectional view taken along line XXVIII-XXVIII shown in Fig. 27. Fig. 29 is a cross-sectional view taken along line XIX-XIX shown in Fig. 27.

[0382] In this embodiment, the multiple mesa portions 15 include multiple first mesa groups MG1 and multiple second mesa groups MG2. Each of the multiple first mesa groups MG1 includes multiple (two, in this embodiment, as an example) first mesa portions 15A for the second diode D2, which are arranged adjacent to each other in the first direction X. The multiple first mesa groups MG1 are arranged at intervals in the first direction X so as to sandwich one or multiple (multiple, in this embodiment) mesa portions 15 therebetween.

[0383] The second mesa groups MG2 each include a plurality of second mesa portions 15B (two, for example, in this embodiment) for the transistor structures Tr, which are adjacent to each other in the first direction X. The second mesa groups MG2 are respectively interposed in regions between the first mesa groups MG1. The second mesa groups MG2 and the first mesa groups MG1 are alternately arranged in the first direction X.

[0384] In this embodiment, the multiple rectification regions 20 are formed in the surface layer portions of the first main surface 3 in the multiple first mesas 15A, but are not formed in the multiple second mesas 15B. The multiple rectification regions 20 are formed over the entire areas of the multiple first mesas 15A in a plan view. The multiple rectification regions 20 extend in a strip shape in the second direction Y following the extension direction of the multiple first mesas 15A, and are adjacent to the multiple gate structures 10 in the first direction X.

[0385] Similar to the semiconductor device 1A, the rectification regions 20 are formed across the entire depth range of the gate structures 10. The rectification regions 20 face each other in the first direction X, with the corresponding gate structures 10 sandwiched therebetween.

[0386] In this embodiment, the body regions 21 are formed in the surface layer portions of the first main surface 3 in the second mesas 15B, but are not formed in the first mesas 15A. The body regions 21 extend in a strip shape in the second direction Y following the extension direction of the second mesas 15B, and are adjacent to the gate structures 10 in the first direction X.

[0387] The body regions 21 are formed at intervals inward from both ends of the gate structures 10 in the second direction Y. Of course, the body regions 21 may be formed over the entire areas of the second mesas 15B in plan view. The body regions 21 face each other in the first direction X, with the corresponding gate structures 10 sandwiched between them.

[0388] Focusing on the three gate structures 10 (one gate structure 10, the central gate structure 10, and the other gate structure 10) that define the two second mesa portions 15B, one body region 21 faces the rectification region 20 in the first direction X across one gate structure 10, and faces the other body region 21 in the first direction X across the central gate structure 10.

[0389] Similarly, the other body region 21 faces the rectification region 20 in the first direction X with the other gate structure 10 interposed therebetween, and faces one body region 21 in the first direction X with the central gate structure 10 interposed therebetween.

[0390] In this embodiment, the source regions 22 are formed in the surface layer portions of the corresponding body regions 21 in the second mesas 15B, but are not formed in the first mesas 15A. In this embodiment, the source regions 22 are formed in a one-to-one correspondence with the body regions 21, respectively. Of course, the source regions 22 may also be formed at intervals in the second direction Y in the surface layer portions of the corresponding body regions 21.

[0391] The source regions 22 extend in a strip shape in the second direction Y following the extension direction of the corresponding body regions 21 in a plan view, and are adjacent to the gate structures 10 in the first direction X. The source regions 22 may be formed spaced apart inward from both ends of the corresponding body regions 21 in the second direction Y. The source regions 22 face each other in the first direction X with the corresponding gate structures 10 sandwiched therebetween.

[0392] Focusing on the three gate structures 10 (one gate structure 10, the central gate structure 10, and the other gate structure 10) that define the two second mesa portions 15B, one source region 22 faces the rectification region 20 in the first direction X across one gate structure 10, and faces the other source region 22 in the first direction X across the central gate structure 10.

[0393] Similarly, the other source region 22 faces the rectification region 20 in the first direction X with the other gate structure 10 interposed therebetween, and faces one source region 22 in the first direction X with the central gate structure 10 interposed therebetween.

[0394] The plurality of contact regions 23 are formed in the plurality of first mesas 15A and the plurality of second mesas 15B, respectively, in the surface layer portion of the first main surface 3. The plurality of contact regions 23 include a plurality of first contact regions 23A formed in the plurality of first mesas 15A and a plurality of second contact regions 23B formed in the plurality of second mesas 15B.

[0395] The multiple first contact regions 23A are formed at intervals in the second direction Y in the multiple first mesas 15A, and divide one rectification region 20 in the corresponding first mesa 15A into multiple regions in the second direction Y. The multiple first contact regions 23A are adjacent to the multiple gate structures 10 in the first direction X. The multiple first contact regions 23A face each other in the first direction X, with the corresponding gate structure 10 sandwiched between them.

[0396] The second contact regions 23B are formed in the second mesas 15B at intervals in the second direction Y. The second contact regions 23B divide one source region 22 into a plurality of regions in the second direction Y in the surface layer portion of the corresponding body region 21.

[0397] Of course, when a plurality of source regions 22 are formed at intervals in the second direction Y in the surface layer portion of a corresponding one body region 21, the plurality of second contact regions 23B may be formed in regions between the plurality of source regions 22. The plurality of second contact regions 23B are adjacent to the plurality of gate structures 10 in the first direction X.

[0398] The second contact regions 23B face the first contact regions 23A in the first direction X in a plan view. That is, the first contact regions 23A and the second contact regions 23B are formed in a matrix in a plan view. The second contact regions 23B face each other in the first direction X with the corresponding gate structures 10 interposed therebetween.

[0399] Focusing on the three gate structures 10 (one gate structure 10, the central gate structure 10, and the other gate structure 10) that define the two second mesa portions 15B, one second contact region 23B faces the rectification region 20 in the first direction X across one gate structure 10, and faces the other second contact region 23B in the first direction X across the central gate structure 10.

[0400] Similarly, the other second contact region 23B faces the rectification region 20 in the first direction X across the other gate structure 10, and faces one second contact region 23B in the first direction X across the central gate structure 10.

[0401] In this embodiment, the multiple well regions 26 are respectively interposed in regions between multiple contact regions 23 adjacent to each other in the first direction X. Specifically, the multiple well regions 26 include multiple first well regions 26A, multiple second well regions 26B, and multiple third well regions 26C.

[0402] The multiple first well regions 26A are respectively interposed in regions between the multiple first contact regions 23A adjacent to each other in the first direction X. The multiple first well regions 26A are arranged in a line with the multiple first contact regions 23A and the multiple second contact regions 23B in the first direction X. The multiple first well regions 26A are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0403] Similar to the semiconductor device 1A, the plurality of first well regions 26A include a first portion 26a and a plurality of second portions 26b. The plurality of second portions 26b extend in the thickness direction along one sidewall and the other sidewall of the corresponding gate structure 10.

[0404] The second portions 26b are connected to the first contact regions 23A on the first main surface 3 side, and are connected to the first portions 26a on the bottom wall sides of the corresponding gate structures 10. As a result, the second portions 26b electrically connect the corresponding deep well regions 24 to the first contact regions 23A.

[0405] The plurality of second well regions 26B are respectively interposed in regions between the plurality of second contact regions 23B adjacent to each other in the first direction X. The plurality of second well regions 26B are arranged in a line with the plurality of first contact regions 23A, the plurality of second contact regions 23B, and the plurality of first well regions 26A in the first direction X. The plurality of second well regions 26B are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0406] Similar to the semiconductor device 1A, the second well regions 26B include a first portion 26a and a plurality of second portions 26b. The second portions 26b include a second portion 26b on the first mesa portion 15A side and a second portion 26b on the second mesa portion 15B side.

[0407] The plurality of second portions 26b extend in the thickness direction along one sidewall and the other sidewall of the corresponding gate structure 10. The plurality of second portions 26b are connected to the corresponding body region 21 on the first main surface 3 side, and are connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. In this way, the plurality of second portions 26b electrically connect the corresponding deep well region 24 to the body region 21.

[0408] In this embodiment, the second portions 26b are connected to the corresponding second contact regions 23B in the surface layer portions of the corresponding body regions 21. In this embodiment, the second portions 26b are integrally formed with the second contact regions 23B. That is, the second portions 26b electrically connect the corresponding deep well regions 24 to the second contact regions 23B.

[0409] The plurality of third well regions 26C are respectively interposed in regions between the plurality of first contact regions 23A and the plurality of second contact regions 23B adjacent to each other in the first direction X. The plurality of third well regions 26C are arranged in a line with the plurality of first contact regions 23A, the plurality of second contact regions 23B, the plurality of first well regions 26A, and the plurality of second well regions 26B in the first direction X. The plurality of third well regions 26C are arranged in a matrix with intervals in the first direction X and the second direction Y in a plan view.

[0410] Similar to the semiconductor device 1A, the plurality of third well regions 26C include a first portion 26a and a plurality of second portions 26b. The plurality of second portions 26b include the second portion 26b on the first mesa portion 15A side and the second portion 26b on the second mesa portion 15B side.

[0411] The second portion 26b on the first mesa portion 15A side extends in the thickness direction along the sidewall on the first mesa portion 15A side of the corresponding gate structure 10. The second portion 26b on the first mesa portion 15A side is connected to the corresponding first contact region 23A on the first main surface 3 side of the first mesa portion 15A, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the first mesa portion 15A side electrically connects the corresponding deep well region 24 to the corresponding first contact region 23A.

[0412] The second portion 26b on the second mesa portion 15B side extends in the thickness direction along the sidewall on the second mesa portion 15B side of the corresponding gate structure 10. The second portion 26b on the second mesa portion 15B side is connected to the corresponding body region 21 on the first main surface 3 side of the second mesa portion 15B, and is connected to the first portion 26a on the bottom wall side of the corresponding gate structure 10. As a result, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the corresponding body region 21.

[0413] In this embodiment, the second portion 26b on the second mesa portion 15B side is connected to the corresponding second contact region 23B in the surface layer portion of the corresponding body region 21. In this embodiment, the second portion 26b on the second mesa portion 15B side is formed integrally with the corresponding second contact region 23B. That is, the second portion 26b on the second mesa portion 15B side electrically connects the corresponding deep well region 24 to the multiple contact regions 23. Furthermore, the well region 26 electrically connects the multiple second contact regions 23B to the multiple first contact regions 23A.

[0414] 30 to 35, first to sixth modified examples that are applied to semiconductor devices 1A to 1F are shown below. FIGS. 30 to 35 show examples (cross-sectional views) in which the first to sixth modified examples are applied to semiconductor device 1A. Naturally, the first to sixth modified examples are also applicable to semiconductor devices 1B to 1F. Furthermore, semiconductor devices 1A to 1F may simultaneously include at least two of the features of the first to sixth modified examples.

[0415] 30 (first modified example), the semiconductor device 1A may not include the second electrode film 37 in the lower electrode film 34. In other words, the lower electrode film 34 has a single-layer structure made of the first electrode film 36. In this embodiment, the main electrode film 35 directly covers the first electrode film 36 (lower electrode film 34).

[0416] The main electrode film 35 backfills the source opening 33 and collectively covers the region of the interlayer film 32 where the source opening 33 is formed. The main electrode film 35 has a portion that covers the interlayer film 32 with the first electrode film 36 in between, a portion that covers the wall surface of the source opening 33 with the first electrode film 36 in between, and a portion that covers the first main surface 3 with the first electrode film 36 in between.

[0417] The main electrode film 35 covers the plurality of cap insulating films 14 in the source opening 33 with the first electrode film 36 sandwiched therebetween, and is electrically insulated from the plurality of buried electrodes 13 by the plurality of cap insulating films 14 .

[0418] The main electrode film 35 covers the mesas 15 in the source opening 33 with the first electrode film 36 interposed therebetween, and is electrically connected to the mesas 15 via the first electrode film 36. Specifically, the main electrode film 35 is electrically connected to the rectification regions 20, the body regions 21, the source regions 22, and the contact regions 23 via the first electrode film 36 in the portion covering the mesas 15.

[0419] In this case, the lower electrode film 34 relating to the gate terminal GT may have a single layer structure made of the first electrode film 36, similar to the source terminal ST. Also, the lower electrode film 34 relating to the gate finger may have a single layer structure made of the first electrode film 36, similar to the source terminal ST.

[0420] 31 (second modified example), the semiconductor device 1A does not necessarily have to have the lower electrode film 34. That is, the source terminal ST may have a single-layer structure made of the main electrode film 35. In this case, the main electrode film 35 is formed as a barrier metal film.

[0421] As described above, the main electrode film 35 may have a single layer structure made of an Al film, an Al alloy film, a Cu film, or a Cu alloy film. The Al alloy film (Cu alloy film) may be an AlSi alloy film, an AlCu alloy film, or an AlSiCu alloy film.

[0422] Of course, the main electrode film 35 may have a single layer structure made of a magnesium film, a titanium film, a vanadium film, a chromium film, a manganese film, a cobalt film, a nickel film, a zirconium film, a niobium film, a molybdenum film, a palladium film, a silver film, an indium film, a tin film, a tantalum film, a tungsten film, a platinum film, or a gold film.

[0423] Of course, the main electrode film 35 may have a single layer structure made of a magnesium alloy film, an aluminum alloy film, a titanium alloy film, a vanadium alloy film, a chromium alloy film, a manganese alloy film, a cobalt alloy film, a nickel alloy film, a copper alloy film, a zirconium alloy film, a niobium alloy film, a molybdenum alloy film, a palladium alloy film, a silver alloy film, an indium alloy film, a tin alloy film, a tantalum alloy film, a tungsten alloy film, a platinum alloy film, or a gold alloy film.

[0424] Of course, the main electrode film 35 may have a single layer structure made of a magnesium compound film, an aluminum compound film, a titanium compound film, a vanadium compound film, a chromium compound film, a manganese compound film, a cobalt compound film, a nickel compound film, a copper compound film, a zirconium compound film, a niobium compound film, a molybdenum compound film, a palladium compound film, a silver compound film, an indium compound film, a tin compound film, a tantalum compound film, a tungsten compound film, a platinum compound film, or a gold compound film.

[0425] The thickness of the main electrode film 35 may be 10 nm or more and 500 nm or less. The thickness of the main electrode film 35 may have a value belonging to at least one of the ranges of 10 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, and 450 nm or more and 500 nm or less.

[0426] The thickness of the main electrode film 35 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 35 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0427] The main electrode film 35 covers the entire region of the interlayer film 32 where the source opening 33 is formed, and extends from above the interlayer film 32 into the source opening 33. The main electrode film 35 has a portion that covers the insulating main surface of the interlayer film 32 in a film-like manner, a portion that covers the wall surface of the source opening 33 in a film-like manner, and a portion that covers the first main surface 3 inside the source opening 33 in a film-like manner.

[0428] The main electrode film 35 covers the plurality of cap insulating films 14 in the source opening 33 in a film form, and is electrically insulated from the plurality of buried electrodes 13 by the plurality of cap insulating films 14. The main electrode film 35 covers the plurality of mesas 15 in the source opening 33 in a film form, and is electrically connected to the plurality of mesas 15. Specifically, the main electrode film 35 is mechanically and electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23 in the portions covering the plurality of mesas 15.

[0429] In this embodiment, the main electrode film 35 extends from above the first major surface 3 into the trenches 11 and covers the cap insulating films 14 within the trenches 11. The main electrode film 35 has portions that cover the opening ends and sidewalls of the trenches 11 within the trenches 11. The main electrode film 35 is mechanically and electrically connected to the rectification regions 20, the body regions 21, the source regions 22, and the contact regions 23 in the portions that cover the opening ends and sidewalls of the trenches 11.

[0430] The main electrode film 35 forms a Schottky junction with the plurality of rectification regions 20 to constitute the second diode D2. This forms the second diode D2 (Schottky diode) including the plurality of rectification regions 20 as a cathode and the main electrode film 35 as an anode. The main electrode film 35 forms ohmic contact with the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23.

[0431] The main electrode film 35 has portions facing both ends of the plurality of gate structures 10 with the interlayer film 32 sandwiched therebetween. The main electrode film 35 is drawn out from the active region 8 to the peripheral region 9 and has a portion (peripheral edge portion) facing the outer well region 27 with the interlayer film 32 sandwiched therebetween.

[0432] 32 (third modification), semiconductor device 1A may include cap insulating film 14 embedded in trench 11 above the upper end of insulating film 12 and the electrode surface of buried electrode 13. That is, cap insulating film 14 may directly cover the upper end of insulating film 12 and the electrode surface of buried electrode 13 in trench 11, and may also directly cover the sidewall of trench 11.

[0433] In such a configuration, the upper end of the insulating film 12 may be located on the bottom wall side of the trench 11 relative to the electrode surface of the buried electrode 13. Of course, the upper end of the insulating film 12 may also be located on the first main surface 3 side relative to the electrode surface of the buried electrode 13.

[0434] The plurality of rectification regions 20 may have portions in direct contact with the cap insulating films 14 of the corresponding gate structures 10. The plurality of body regions 21 may have portions in direct contact with the cap insulating films 14 of the corresponding gate structures 10. The plurality of source regions 22 may have portions in direct contact with the cap insulating films 14 of the corresponding gate structures 10.

[0435] The plurality of contact regions 23 may have portions that are in direct contact with the cap insulating films 14 of the corresponding gate structures 10. The plurality of well regions 26 may have portions that are in direct contact with the cap insulating films 14 of the corresponding gate structures 10.

[0436] 33 (fourth modification), semiconductor device 1A may not have deep well region 24 and deep drift region 25. In this case, semiconductor device 1A may have well region 26 or may not have well region 26.

[0437] 34 (fifth modification), the semiconductor device 1A may include a plurality of gate structures 10 without a cap insulating film 14. In this case, the main surface insulating film 30 may cover the first main surface 3 (a plurality of mesa portions 15) so as to expose a plurality of buried electrodes 13 in the active region 8, and may be connected to a plurality of insulating films 12. The interlayer film 32 may cover the plurality of gate structures 10 (buried electrodes 13) in the active region 8.

[0438] In this case, a plurality of source openings 33 may be formed in the interlayer film 32. The plurality of source openings 33 penetrate the main surface insulating film 30 and the interlayer film 32, and selectively expose a plurality of mesa portions 15. The plurality of source openings 33 may be formed in a one-to-one correspondence with one mesa portion 15.

[0439] In this case, the plurality of source openings 33 are formed in strip shapes extending in the second direction Y in accordance with the extension direction of the corresponding mesa portion 15. The plurality of source openings 33 selectively expose the rectification region 20, the body region 21, the source region 22, and the contact region 23, respectively, in accordance with the layout within the corresponding mesa portion 15.

[0440] Of course, the multiple source openings 33 may be formed in a one-to-many correspondence with one mesa portion 15. In this case, the multiple source openings 33 are formed at intervals following the extension direction of the corresponding mesa portion 15. The multiple source openings 33 may be formed in a strip shape, a square shape, a circle shape, or the like extending in the second direction Y. The multiple source openings 33 selectively expose at least one of the rectification region 20, the body region 21, the source region 22, and the contact region 23 according to the layout in the corresponding mesa portion 15.

[0441] The source terminal ST extends from above the interlayer film 32 into the multiple source openings 33 and is electrically connected to the multiple rectification regions 20, the multiple body regions 21, the multiple source regions 22, and the multiple contact regions 23 within the multiple source openings 33.

[0442] The source terminal ST includes either or both of a lower electrode film 34 and a main electrode film 35. The lower electrode film 34 has a laminated structure including a first electrode film 36 and a second electrode film 37. Of course, the lower electrode film 34 may have a single-layer structure made of the first electrode film 36. Here, as an example, an example is shown in which the source terminal ST includes the first electrode film 36, the second electrode film 37, and the main electrode film 35.

[0443] The first electrode film 36 collectively covers the region of the interlayer film 32 where the multiple source openings 33 are formed, and extends from above the interlayer film 32 into the multiple source openings 33. The first electrode film 36 has a portion that covers the insulating main surface of the interlayer film 32 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 33 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 33 in a film-like manner. The first electrode film 36 is mechanically and electrically connected to the multiple rectification regions 20, the multiple body regions 21, the multiple source regions 22, and the multiple contact regions 23.

[0444] The first electrode film 36 forms Schottky junctions with the rectification regions 20 in the source openings 33, constituting the second diode D2. This forms the second diode D2 (Schottky diode) including the rectification regions 20 as cathodes and the first electrode film 36 as anodes. The first electrode film 36 forms ohmic contact with the body regions 21, the source regions 22, and the contact regions 23.

[0445] The second electrode film 37 directly covers the first electrode film 36. The second electrode film 37 collectively covers the region of the interlayer film 32 where the plurality of source openings 33 are formed, sandwiching the first electrode film 36 therebetween, and extends from above the interlayer film 32 into the plurality of source openings 33.

[0446] The second electrode film 37 has a portion that covers the insulating principal surface of the interlayer film 32 in a film-like manner with the first electrode film 36 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 33 in a film-like manner with the first electrode film 36 sandwiched therebetween, and a portion that covers the first principal surface 3 in a film-like manner with the first electrode film 36 sandwiched therebetween within the plurality of source openings 33. The second electrode film 37 is electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23 via the first electrode film 36 within the source openings 33.

[0447] The main electrode film 35 directly covers the lower electrode film 34 (second electrode film 37). The main electrode film 35 collectively covers the region of the interlayer film 32 where the plurality of source openings 33 are formed, and backfills the plurality of source openings 33.

[0448] The main electrode film 35 has a portion that covers the insulating principal surface of the interlayer film 32 with the lower electrode film 34 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 33 with the lower electrode film 34 sandwiched therebetween, and a portion that covers the first principal surface 3 with the lower electrode film 34 sandwiched therebetween. The main electrode film 35 is electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23 via the lower electrode film 34 within the plurality of source openings 33.

[0449] Of course, as in the second modified example (see FIG. 31 ), the source terminal ST may have a single-layer structure made of the main electrode film 35. In this case, the main electrode film 35 collectively covers the region of the interlayer film 32 where the multiple source openings 33 are formed, and extends from above the interlayer film 32 into the multiple source openings 33.

[0450] The main electrode film 35 has a portion that covers the insulating main surface of the interlayer film 32 in a film-like manner, a portion that covers the wall surfaces of the plurality of source openings 33 in a film-like manner, and a portion that covers the first main surface 3 in the plurality of source openings 33. The main electrode film 35 is mechanically and electrically connected to the plurality of rectification regions 20, the plurality of body regions 21, the plurality of source regions 22, and the plurality of contact regions 23.

[0451] The main electrode film 35 forms Schottky junctions with the rectification regions 20 in the source openings 33 to form second diodes D2. This forms the second diodes D2 (Schottky diodes) including the rectification regions 20 as cathodes and the first electrode film 36 as anodes. The main electrode film 35 forms ohmic contacts with the body regions 21, the source regions 22, and the contact regions 23.

[0452] Referring to Figure 35 (sixth variant), in the above-mentioned form, multiple source regions 22 were formed at intervals inward from both ends of the corresponding body region 21 in the second direction Y, but the semiconductor device 1A may also include multiple source regions 22 each having either or both of a first drawer portion 22a and a second drawer portion 22b.

[0453] The first lead portion 22a crosses one end of the corresponding body region 21 on one side in the second direction Y and is electrically connected to the adjacent rectification region 20. The second lead portion 22b crosses the other end of the corresponding body region 21 on the other side in the second direction Y and is electrically connected to the adjacent rectification region 20. In this manner, the peripheral portion of the source region 22 may define the rectification region 20 together with the peripheral portion of the body region 21.

[0454] The above-described embodiments (including variations) can be implemented in other forms. For example, the features (layouts) of semiconductor devices 1A-1F according to the first to sixth embodiments can be combined as appropriate. Therefore, semiconductor devices 1A-1F may have at least one or more of the features (layouts) of semiconductor devices 1A-1F in one or more regions (e.g., multiple mesa portions 15) of the first main surface 3.

[0455] For example, in the above-described embodiment, a structure may be adopted in which the conductivity type of the “n-type” semiconductor region is inverted to “p-type” and the conductivity type of the “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0456] For example, in the above-described embodiment, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the base region 6 may include a silicon single crystal. Similarly, the drift region 7 may include a silicon single crystal.

[0457] For example, in the above-described embodiment, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure.

[0458] A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0459] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc., as necessary.

[0460] [A1] A semiconductor device (1A-1F) including: a chip (2) having a main surface (3); a semiconductor region (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a trench-type gate structure (10) formed in the main surface (3) and positioned within the semiconductor region (7); a rectification region (20) of the first conductivity type (n-type) formed in a surface layer portion of the main surface (3) adjacent to the gate structure (10); and a main surface electrode (ST) on the main surface (3) that is electrically separated from the gate structure (10) and forms a Schottky junction with the rectification region (20).

[0461] [A2] The semiconductor device (1A to 1F) according to A1, wherein the chip (2) includes SiC.

[0462] [A3] The semiconductor device (1A-1F) according to A1 or A2, wherein the gate structure (10) includes a trench (11) formed in the main surface (3), an insulating film (12) covering the wall surface of the trench (11), and a buried electrode (13) buried in the trench (11) with the insulating film (12) sandwiched between them, and the rectification region (20) faces the buried electrode (13) with the insulating film (12) sandwiched between them.

[0463] [A4] The semiconductor device (1A-1F) described in A3, wherein the gate structure (10) includes the buried electrode (13) buried in the trench (11) at a distance from a height position of the main surface (3) toward the bottom wall of the trench (11), and a cap insulating film (14) covering the buried electrode (13) within the trench (11), the rectification region (20) has a portion facing the cap insulating film (14) within the chip (2), and the main surface electrode (ST) covers the cap insulating film (14) and is electrically isolated from the buried electrode (13) by the cap insulating film (14).

[0464] [A5] The semiconductor device (1A to 1F) described in A4, wherein the cap insulating film (14) has an insulating surface positioned on the bottom wall side of the trench (11) relative to the height position of the main surface (3), and the main surface electrode (ST) is in contact with the insulating surface of the cap insulating film (14) within the trench (11).

[0465] [A6] A semiconductor device (1A to 1F) according to any one of A1 to A5, wherein the rectification region (20) is formed on the side of the gate structure (10) over the entire depth range of the gate structure (10).

[0466] [A7] The semiconductor device (1A to 1F) according to A6, wherein the rectification region (20) is made up of a part of the semiconductor region (7).

[0467] [A8] A semiconductor device (1A to 1F) according to any one of A1 to A7, further comprising a body region (21) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3) adjacent to the gate structure (10) so as to be adjacent to the rectification region (20), and forming a pn junction with the semiconductor region (7), wherein the main surface electrode (ST) is electrically connected to the body region (21) on the main surface (3).

[0468] [A9] The semiconductor device (1A to 1F) according to A8, further including a first conductivity type (n-type) source region (22) formed in a region along the gate structure (10) in a surface layer portion of the body region (21) and facing the rectification region (20) along a wall surface of the gate structure (10).

[0469] [A10] A semiconductor device (1A to 1F) according to any one of A1 to A7, further comprising a body region (21) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3) adjacent to the gate structure (10) in a region opposite the rectification region (20) with respect to the gate structure (10), and forming a pn junction with the semiconductor region (7), and the main surface electrode (ST) is electrically connected to the body region (21) on the main surface (3).

[0470] [A11] The semiconductor device (1A to 1F) according to A10, wherein the body region (21) faces the rectification region (20) across the gate structure (10).

[0471] [A12] A semiconductor device (1A to 1F) according to A11, further including a first conductivity type (n-type) source region (22) formed in a surface layer portion of the body region (21) in a region along the gate structure (10).

[0472] [A13] The semiconductor device (1A to 1F) according to A12, wherein the source region (22) faces the rectification region (20) across the gate structure (10).

[0473] [A14] A semiconductor device (1A to 1F) according to any one of A1 to A13, further including a second conductivity type (p-type) impurity region (24) formed in a region below the gate structure (10) within the chip (2) and electrically connected to the semiconductor region (7).

[0474] [A15] A semiconductor device (1A-1F) according to any one of A1 to A14, further including a second conductivity type (p-type) contact region (23) formed in a region along the gate structure (10) in a surface layer portion of the main surface (3).

[0475] [A16] A semiconductor device (1A to 1F) according to any one of A1 to A15, further including a second conductivity type (p-type) well region (26) formed along the sidewalls and bottom wall of the gate structure (10) within the chip (2).

[0476] [A17] A semiconductor device (1A-1F) including: a chip (2) having a main surface (3); a semiconductor region (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a trench-type gate structure (10) formed in the main surface (3) and positioned within the semiconductor region (7); a rectification region (20) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3) along the gate structure (10); a body region (21) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3) along the gate structure (10); and a main surface electrode (ST) on the main surface (3) that is electrically separated from the gate structure (10), electrically connected to the body region (21), and forms a Schottky junction with the rectification region (20).

[0477] [A18] The semiconductor device (1A to 1F) according to A17, further including a first conductivity type (n-type) source region (22) formed in a surface layer portion of the body region (21), and a second conductivity type (p-type) contact region (23) formed in a surface layer portion of the body region (21).

[0478] [A19] A semiconductor device (1A to 1F) according to A17 or A18, further including a second conductivity type (p-type) impurity region (24) formed in a region below the gate structure (10) within the chip (2).

[0479] [A20] A semiconductor device (1A to 1F) according to any one of A17 to A19, further including a second conductivity type (p-type) well region (26) formed along the sidewalls and bottom wall of the gate structure (10) within the chip (2).

[0480] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0481] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 1E Semiconductor device 1F Semiconductor device 2 Chip 3 First main surface 7 Drift region (semiconductor region) 10 Gate structure 11 Trench 12 Insulating film 13 Buried electrode 14 Cap insulating film 20 Rectification region 21 Body region 22 Source region 23 Contact region 24 Deep well region (impurity region) 26 Well region ST Source terminal (main surface electrode)

Claims

1. A semiconductor device comprising: a chip having a principal surface; a semiconductor region of a first conductivity type formed on a surface layer of the principal surface; a trench-type gate structure formed on the principal surface and positioned within the semiconductor region; a rectification region of the first conductivity type formed on the surface layer of the principal surface adjacent to the gate structure; and a principal surface electrode on the principal surface, electrically isolated from the gate structure and forming a Schottky junction with the rectification region.

2. The semiconductor device according to claim 1, wherein the chip comprises SiC.

3. The semiconductor device according to claim 1 or 2, wherein the gate structure includes a trench formed in the main surface, an insulating film covering a wall surface of the trench, and a buried electrode buried in the trench with the insulating film sandwiched between them, and the rectification region faces the buried electrode with the insulating film sandwiched between them.

4. The semiconductor device described in claim 3, wherein the gate structure includes: a buried electrode buried in the trench at a distance from a height position of the main surface toward a bottom wall side of the trench; and a cap insulating film covering the buried electrode within the trench; the rectification region has a portion facing the cap insulating film within the chip; and the main surface electrode covers the cap insulating film and is electrically separated from the buried electrode by the cap insulating film.

5. The semiconductor device according to claim 4, wherein the cap insulating film has an insulating surface positioned on the bottom wall side of the trench relative to the height position of the main surface, and the main surface electrode is in contact with the insulating surface of the cap insulating film within the trench.

6. The semiconductor device according to claim 1, wherein the rectification region is formed on the side of the gate structure across the entire depth range of the gate structure.

7. The semiconductor device according to claim 6, wherein the rectification region is made up of a part of the semiconductor region.

8. A semiconductor device according to any one of claims 1 to 7, further comprising a body region of a second conductivity type formed in a surface layer portion of the main surface adjacent to the gate structure so as to be adjacent to the rectification region, forming a pn junction with the semiconductor region, and the main surface electrode is electrically connected to the body region on the main surface.

9. The semiconductor device according to claim 8, further comprising a first conductivity type source region formed in a surface portion of said body region in a region along said gate structure and facing said rectification region along a wall surface of said gate structure.

10. A semiconductor device as claimed in any one of claims 1 to 7, further comprising a body region of a second conductivity type formed in a surface layer portion of the main surface adjacent to the gate structure in a region opposite the rectification region with respect to the gate structure, forming a pn junction with the semiconductor region, and the main surface electrode is electrically connected to the body region on the main surface.

11. The semiconductor device according to claim 10, wherein the body region faces the rectification region with the gate structure interposed therebetween.

12. The semiconductor device according to claim 11, further comprising a source region of the first conductivity type formed in a surface portion of said body region in a region along said gate structure.

13. The semiconductor device according to claim 12, wherein the source region faces the rectification region with the gate structure interposed therebetween.

14. The semiconductor device according to claim 1, further comprising a second conductivity type impurity region formed in a region below said gate structure within said chip and electrically connected to said semiconductor region.

15. The semiconductor device according to claim 1, further comprising a contact region of the second conductivity type formed in a surface portion of the main surface in a region along the gate structure.

16. The semiconductor device according to claim 1, further comprising a well region of a second conductivity type formed within said chip along side walls and a bottom wall of said gate structure.

17. A semiconductor device comprising: a chip having a main surface; a first conductivity type semiconductor region formed in a surface portion of the main surface; a trench-type gate structure formed on the main surface and positioned within the semiconductor region; a first conductivity type rectification region formed in the surface portion of the main surface along the gate structure; a second conductivity type body region formed in the surface portion of the main surface along the gate structure; and a main surface electrode electrically separated from the gate structure on the main surface, electrically connected to the body region, and forming a Schottky junction with the rectification region.

18. The semiconductor device according to claim 17, further comprising: a source region of a first conductivity type formed in a surface portion of said body region; and a contact region of a second conductivity type formed in a surface portion of said body region.

19. The semiconductor device according to claim 17 or 18, further comprising an impurity region of a second conductivity type formed in a region below said gate structure within said chip.

20. The semiconductor device according to claim 17, further comprising a well region of a second conductivity type formed within said chip along side walls and a bottom wall of said gate structure.

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