Semiconductor device

Abstract

A semiconductor device includes: a chip which has a main surface; an active region which is provided in the main surface; a pad region which is provided outside the active region in the main surface; an insulated gate typed transistor structure which is formed on the main surface of the active region; a trench electrode typed capacitor structure which is formed on the main surface of the pad region and forms a capacitive coupling with the chip; and a pad electrode which is disposed on the main surface of the pad region and is electrically connected to the capacitor structure.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-168420 filed with the Japan Patent Office on September 28, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2023 / 0106733A1) discloses a semiconductor device including a semiconductor substrate, a trench gate structure, an interlayer insulating film, a source electrode, an isolation insulating film, and a gate pad. The trench gate structure is formed in the semiconductor substrate. The interlayer insulating film is formed on the trench gate structure. The source electrode is formed on the interlayer insulating film. The isolation insulating film is formed on the source electrode. The gate pad is disposed on the source electrode via the isolation insulating film.

[0003] US Patent Application Publication No. 2023 / 0106733

[0004] [Summary] The present disclosure provides a semiconductor device that can improve electrical characteristics.

[0005] The present disclosure provides a semiconductor device including: a chip having a main surface; an active region provided on the main surface; a pad region provided on the main surface outside the active region; an insulated gate type transistor structure formed on the main surface of the active region; a trench electrode type capacitor structure formed on the main surface of the pad region and forming a capacitive coupling with the chip; and a pad electrode disposed on the main surface of the pad region and electrically connected to the capacitor structure.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; an active region provided on the main surface; a pad region provided on the main surface outside the active region; a transistor structure formed in the active region; a main surface insulating film having a thickness of 10 nm or more and 200 nm or less and having a portion covering the main surface of the pad region; an electrode film disposed on the main surface insulating film in the pad region and forming a capacitive coupling with the chip via the main surface insulating film; and a pad electrode disposed on the electrode film in the pad region and electrically connected to the electrode film.

[0007] The present disclosure provides a semiconductor device including: a chip having a main surface; an active region provided on the main surface; a pad region provided on the main surface outside the active region; a transistor structure formed on the main surface of the active region; and a trench electrode type capacitor structure formed on the main surface of the pad region and forming a capacitive coupling with the chip.

[0008] The present disclosure provides a semiconductor device including: a chip having a main surface; an active region provided on the main surface; a pad region provided on the main surface outside the active region; an insulated gate type transistor structure formed in the active region; a trench formed on the main surface of the pad region; a dielectric film covering a wall surface of the trench; and a buried electrode that forms a capacitive coupling with the chip within the trench via the dielectric film and is applied with a potential other than a gate potential.

[0009] The present disclosure provides a semiconductor device including a chip having a main surface, a diode region provided on the main surface, a pad region provided on the main surface outside the diode region, a diode structure formed in the diode region, and a trench electrode type capacitor structure formed on the main surface of the pad region and forming a capacitive coupling with the chip.

[0010] The present disclosure provides a semiconductor device including a chip having a main surface, a monitor region provided on the main surface, a pad region provided on the main surface outside the monitor region, an insulated gate type monitor transistor structure for monitoring current formed in the monitor region, and a trench electrode type capacitor structure formed on the main surface of the pad region and forming a capacitive coupling with the chip.

[0011] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0012] FIG. 1 is a circuit diagram showing an example of the electrical configuration of a semiconductor device according to a first embodiment. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of an active region. FIG. 5 is an enlarged plan view showing another main portion of the active region. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is an enlarged plan view showing a main portion of a monitor region. FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 9. FIG. 12 is an enlarged plan view showing a temperature detection region. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is an enlarged plan view showing a pad structure according to the first layout example, a pad opening according to the first layout example, and the configuration within the pad region. FIG. 15 is an enlarged plan view showing a main portion of the pad region. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 15. FIG. 18A is a plan view showing a pad structure according to a second layout example. FIG. 18B is a plan view showing a pad structure according to a third layout example. FIG. 18C is a plan view showing a pad structure according to a fourth layout example. FIG. 18D is a plan view showing a pad structure according to a fifth layout example. FIG. 18E is a plan view showing a pad structure according to a sixth layout example. FIG. 18F is a plan view showing a pad structure according to a seventh layout example. FIG. 18G is a plan view showing a pad structure according to an eighth layout example. FIG. 18H is a plan view showing a pad structure according to a ninth layout example. FIG. 18I is a plan view showing a pad structure according to a tenth layout example. FIG. 18J is a plan view showing a pad structure according to an eleventh layout example. Fig. 18K is a plan view showing a pad structure according to a twelfth layout example. Fig. 18L is a plan view showing a pad structure according to a thirteenth layout example. Fig. 18M is a plan view showing a pad structure according to a fourteenth layout example. Fig. 18N is a plan view showing a pad structure according to a fifteenth layout example. Fig. 18O is a plan view showing a pad structure according to a sixteenth layout example.FIG. 18P is a plan view showing a pad structure according to a seventeenth layout example. FIG. 18Q is a plan view showing a pad structure according to an eighteenth layout example. FIG. 18R is a plan view showing a pad structure according to a nineteenth layout example. FIG. 19A is a plan view showing a pad opening according to a second layout example. FIG. 19B is a plan view showing a pad opening according to a third layout example. FIG. 19C is a plan view showing a pad opening according to a fourth layout example. FIG. 19D is a plan view showing a pad opening according to a fifth layout example. FIG. 19E is a plan view showing a pad opening according to a sixth layout example. FIG. 19F is a plan view showing a pad opening according to a seventh layout example. FIG. 20 is a plan view illustrating an electrical test on the gate pad electrode side. FIG. 21 is a plan view illustrating an electrical test on the monitor pad electrode side. FIG. 22 is a plan view illustrating an electrical test on the anode pad electrode side. FIG. 23 is a plan view illustrating an electrical test on the cathode pad electrode side. FIG. 24 is a plan view illustrating a layout example of a first main surface of a semiconductor device according to the second embodiment. FIG. 25 is an enlarged plan view showing a main portion of the active region of the semiconductor device shown in FIG. 24 . FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 25 . FIG. 27 is a cross-sectional view showing a main portion of a semiconductor device according to the third embodiment. FIG. 28 is a cross-sectional view showing a main portion of a semiconductor device according to the fourth embodiment. FIG. 29 is a cross-sectional view showing a main portion of a semiconductor device according to the fifth embodiment. FIG. 30 is a plan view showing a pad region of a semiconductor device according to the sixth embodiment. FIG. 31 is an enlarged plan view showing a main portion of the pad region shown in FIG. 30 . FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 31 . FIG. 33 is a plan view showing a first modified example of the semiconductor device according to the first to sixth embodiments. FIG. 34 is a plan view showing a second modified example of the semiconductor device according to the first to sixth embodiments. FIG. 35 is a plan view showing a third modified example of the semiconductor device according to the first to sixth embodiments. FIG. 36 is a plan view showing a fourth modified example of the semiconductor device according to the first to sixth embodiments.

[0013] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0014] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0015] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0016] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0017] 1 is a circuit diagram showing an example of the electrical configuration of a semiconductor device 1A according to the first embodiment. The semiconductor device 1A includes a gate pad GP, an emitter pad EP, a monitor pad MP, a collector pad CoP, an anode pad AP, a cathode pad CaP, an insulated gate main transistor structure T1, an insulated gate monitor transistor structure T2, and a temperature sensitive diode structure D. In other words, the semiconductor device 1A is a semiconductor switching device.

[0018] The main transistor structure T1 is composed of one or more transistor structures T3. In this embodiment, the main transistor structure T1 includes a parallel circuit composed of a plurality of (four in this embodiment) transistor structures T3. The transistor structure T3 includes either or both of a MISFET structure and an IGBT structure. In this embodiment, the transistor structure T3 has a trench gate vertical IGBT structure.

[0019] The main transistor structure T1 (transistor structure T3) includes a gate electrically connected to a gate pad GP, an emitter electrically connected to an emitter pad EP, and a collector electrically connected to a collector pad CoP.

[0020] The main transistor structure T1 is turned on and off in response to a gate potential applied from the gate pad GP, and generates an output current Ice between the emitter pad EP and the collector pad CoP. The output current Ice is an emitter-collector current of the main transistor structure T1.

[0021] In this configuration, the monitor transistor structure T2 is connected in parallel to the main transistor structure T1. In this configuration, the monitor transistor structure T2 has a trench-gate vertical IGBT structure. The monitor transistor structure T2 includes a monitor gate electrically connected to the gate pad GP, a monitor emitter electrically connected to the monitor pad MP, and a monitor collector electrically connected to the collector pad CoP.

[0022] The monitor transistor structure T2 is controlled to be turned on and off at the same timing as the main transistor structure T1 in response to a gate potential applied from the gate pad GP, and generates a monitor current Im for monitoring the output current Ice between the monitor pad MP and the collector pad CoP. The monitor current Im is an emitter-collector current of the monitor transistor structure T2.

[0023] The monitor current Im is less than the output current Ice. A current ratio Im / Iec of the monitor current Im to the output current Ice may be 1 / 2000 or more and 1 / 10 or less. The current ratio Im / Iec may have a value belonging to at least one of the ranges of 1 / 2000 or more and 1 / 1750 or less, 1 / 1750 or more and 1 / 1500 or less, 1 / 1500 or more and 1 / 1250 or less, 1 / 1250 or more and 1 / 1000 or less, 1 / 1000 or more and 1 / 750 or less, 1 / 750 or more and 1 / 500 or less, 1 / 500 or more and 1 / 250 or less, 1 / 250 or more and 1 / 100 or less, 1 / 100 or more and 1 / 75 or less, 1 / 75 or more and 1 / 50 or less, 1 / 50 or more and 1 / 25 or less, and 1 / 25 or more and 1 / 10 or less.

[0024] The temperature sensitive diode structure D has a parallel circuit PC including one or more (four in this embodiment) first diodes D1 and one or more (four in this embodiment) second diodes D2. The number of second diodes D2 is the same as the number of first diodes D1. Of course, the number of second diodes D2 may be greater than or less than the number of first diodes D1.

[0025] The first diodes D1 are connected in series in the forward direction to form a first series circuit SC1, the anode of which is electrically connected to the anode pad AP, and the cathode of which is electrically connected to the cathode pad CaP.

[0026] The second diodes D2 are connected in series in the forward direction to form a second series circuit SC2. The cathode of the second series circuit SC2 is electrically connected to the anode pad AP. The anode of the second series circuit SC2 is electrically connected to the cathode pad CaP. In other words, the second series circuit SC2 is connected in reverse bias parallel to the first series circuit SC1, and together with the first series circuit SC1, forms a parallel circuit PC.

[0027] The first series circuit SC1 functions as a temperature sensor, and the second series circuit SC2 functions as a protection circuit. The first series circuit SC1 (plurality of first diodes D1) has a temperature characteristic (e.g., a positive temperature characteristic) that varies with temperature in relation to a forward voltage, and outputs a forward current that corresponds to the temperature of the chip 2.

[0028] The second series circuit SC2 provides immunity to noise signals. It is preferable that the second series circuit SC2 has electrical characteristics (high-frequency impedance characteristics) substantially equal to those of the first series circuit SC1. If the protection function of the second series circuit SC2 is not required, the second series circuit SC2 may be omitted.

[0029] The semiconductor device 1A includes a monitor capacitor structure CM electrically interposed between the emitter pad EP and the monitor pad MP. When a voltage is applied between the emitter pad EP and the monitor pad MP, the monitor capacitor structure CM functions as a capacitor between the emitter pad EP and the monitor pad MP.

[0030] The monitor capacitor structure CM also functions as a capacitor between the gate pad GP and the monitor pad MP when a voltage is applied between the gate pad GP and the monitor pad MP.

[0031] The semiconductor device 1A includes an anode capacitor structure CA electrically interposed between the emitter pad EP and the anode pad AP. When a voltage is applied between the emitter pad EP and the anode pad AP, the anode capacitor structure CA functions as a capacitor between the emitter pad EP and the anode pad AP.

[0032] The anode capacitor structure CA also functions as a capacitor between the gate pad GP and the anode pad AP when a voltage is applied between the gate pad GP and the anode pad AP.

[0033] The semiconductor device 1A includes a cathode capacitor structure CC electrically interposed between the emitter pad EP and the cathode pad CaP. When a voltage is applied between the emitter pad EP and the cathode pad CaP, the cathode capacitor structure CC functions as a capacitor between the emitter pad EP and the cathode pad CaP.

[0034] The cathode capacitor structure CC also functions as a capacitor between the gate pad GP and the cathode pad CaP when a voltage is applied between the gate pad GP and the cathode pad CaP.

[0035] FIG. 2 is a plan view of the semiconductor device 1A shown in FIG. 1. FIG. 3 is a plan view showing an example layout of the first main surface 3. FIG. 4 is an enlarged plan view showing a main portion of the active region 6. FIG. 5 is an enlarged plan view showing another main portion of the active region 6. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.

[0036] 2 to 8, semiconductor device 1A includes a hexahedral (specifically, rectangular parallelepiped) chip 2. Chip 2 includes either or both of silicon single crystal and wide bandgap semiconductor single crystal.

[0037] A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). The chip 2 may be referred to as a "semiconductor chip," a "silicon chip," a "wide bandgap semiconductor chip," or the like.

[0038] When SiC single crystal is used as the wide bandgap semiconductor single crystal, the chip 2 is preferably made of hexagonal SiC single crystal. Hexagonal SiC single crystal has a variety of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. The chip 2 preferably includes 4H-SiC single crystal. Of course, the chip 2 may also include other polytypes. In this embodiment, the chip 2 has a single-layer structure made of silicon single crystal.

[0039] The chip 2 may have a thickness of 50 μm or more and 500 μm or less. The thickness of the chip 2 may have a value belonging to at least one of the ranges of 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0040] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0041] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face away from (oppose to) a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face away from (oppose to) the first direction X.

[0042] Hereinafter, the direction extending along the first main surface 3 may be referred to as the “horizontal direction.” The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0043] The semiconductor device 1A includes one or more active regions 6 provided on the first main surface 3. The active regions 6 are regions having a transistor structure T3. The number of active regions 6 is arbitrary and is adjusted appropriately depending on the size of the chip 2 (first main surface 3).

[0044] In this embodiment, the semiconductor device 1A includes a plurality (four in this embodiment) of active regions 6. The plurality of active regions 6 include a first active region 6A, a second active region 6B, a third active region 6C, and a fourth active region 6D, which are arranged from the third side surface 5C side toward the fourth side surface 5D side.

[0045] The active regions 6 are provided in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active regions 6 are arranged at intervals in the first direction X and extend in strip shapes in the second direction Y. The active regions 6 are unevenly distributed closer to the second side surface 5B than the first side surface 5A.

[0046] The planar shape of the multiple active regions 6 is arbitrary. In this embodiment, the multiple active regions 6 are defined in the shape of a polygon having four sides parallel to the periphery of the chip 2. The width in the first direction X, the length in the second direction Y, the planar area, etc. of the multiple active regions 6 may be different from one another. At least two of the multiple active regions 6 may be partially connected.

[0047] The semiconductor device 1A includes a monitor region 7 provided on the first main surface 3. The monitor region 7 is a region having a monitor transistor structure T2. The monitor region 7 is provided in a region outside the plurality of active regions 6. The layout location of the monitor region 7 is arbitrary. In this embodiment, the monitor region 7 is arranged on the first side surface 5A side with respect to the plurality of active regions 6.

[0048] In this embodiment, the monitor region 7 is disposed near a corner connecting the first side surface 5A and the fourth side surface 5D. The monitor region 7 may face at least one active region 6 in the second direction Y. The monitor region 7 has a planar area smaller than the planar areas of the multiple active regions 6. The planar area of ​​the monitor region 7 is arbitrary and is adjusted appropriately depending on the size of the chip 2 (first main surface 3) and the monitor current Im.

[0049] The semiconductor device 1A includes a peripheral region 8 provided on the periphery of the first main surface 3. The peripheral region 8 is a region that does not have the monitor transistor structure T2 or the transistor structure T3. The peripheral region 8 is provided in a region outside the multiple active regions 6 and the monitor region 7 on the periphery of the first main surface 3. The peripheral region 8 is formed in an annular shape extending along the periphery of the first main surface 3 and surrounds the multiple active regions 6 and the monitor region 7.

[0050] The semiconductor device 1A includes one or more (multiple in this embodiment) street regions 9 provided on the first main surface 3. The street regions 9 are regions that do not have the monitor transistor structure T2 or the transistor structure T3.

[0051] The plurality of street regions 9 are provided in regions outside the plurality of active regions 6 and the monitor region 7. The plurality of street regions 9 are partitioned into regions between adjacent plurality of active regions 6, and extend in strip shapes along the second direction Y following the extension direction of the plurality of active regions 6.

[0052] The semiconductor device 1A includes a temperature detection region 10 provided on the first main surface 3. The temperature detection region 10 is a region including a temperature sensing diode structure D for detecting the temperature of the chip 2. The temperature detection region 10 may also be referred to as a "diode region," a "temperature sensing diode region," or the like. The temperature detection region 10 is provided in a region outside the multiple active regions 6 and the monitor region 7.

[0053] In this embodiment, the temperature measurement region 10 is formed in a region between the plurality of active regions 6 by utilizing a part of the street region 9, and faces the plurality of active regions 6 in the first direction X. In this embodiment, the temperature measurement region 10 is formed in a region between the second active region 6B and the third active region 6C.

[0054] The temperature measurement region 10 has a planar area smaller than the planar area of ​​the plurality of active regions 6. The layout location of the temperature measurement region 10 is arbitrary. The temperature rises relatively easily in the inner part of the first main surface 3 (chip 2). Therefore, it is preferable that the temperature measurement region 10 be provided in the inner part of the first main surface 3 (for example, near the center).

[0055] In this case, the temperature of the chip 2 is appropriately detected. When a first imaginary line passing through the center of the first main surface 3 in the first direction X and a second imaginary line passing through the center of the first main surface 3 in the second direction Y are set, a part of the temperature measurement region 10 may overlap either or both of the first imaginary line and the second imaginary line.

[0056] The semiconductor device 1A includes a plurality of pad regions 11 provided on the first main surface 3. The plurality of pad regions 11 are regions where external terminals for external connection are arranged. The plurality of pad regions 11 are provided in regions outside the plurality of active regions 6, the monitor region 7, the plurality of street regions 9, and the temperature detection region 10. The layout locations of the plurality of pad regions 11 are arbitrary. In this embodiment, the plurality of pad regions 11 are formed by utilizing a part of the outer peripheral region 8 in a region on the first side surface 5A side of the plurality of active regions 6.

[0057] The pad regions 11 include a gate pad region 11G, a monitor pad region 11M, an anode pad region 11A, and a cathode pad region 11C. The gate pad region 11G is a region where a gate pad GP is arranged.

[0058] The monitor pad region 11M is a region where the monitor pad MP is arranged, the anode pad region 11A is a region where the anode pad AP is arranged, and the cathode pad region 11C is a region where the cathode pad CaP is arranged.

[0059] The gate pad region 11G is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the gate pad region 11G may be provided near the center of the first side surface 5A and face one or multiple active regions 6 in either or both of the first direction X and the second direction Y. In this embodiment, the gate pad region 11G faces the temperature measurement region 10 in the second direction Y.

[0060] The monitor pad region 11M is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the monitor pad region 11M is provided in a region on the fourth side surface 5D side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X. In this embodiment, the monitor pad region 11M faces the gate pad region 11G across a part of at least one active region 6 (in this embodiment, the third active region 6C).

[0061] The monitor pad region 11M is provided in a region on the first side surface 5A side of the monitor region 7, and faces the monitor region 7 in the second direction Y. The monitor pad region 11M faces one or more active regions 6 (third active region 6C in this embodiment) in the second direction Y, with the monitor region 7 in between.

[0062] The anode pad region 11A is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the anode pad region 11A is provided in a region on the third side surface 5C side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X. The anode pad region 11A may face one or multiple active regions 6 in the second direction Y.

[0063] The cathode pad region 11C is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the cathode pad region 11C is provided in a region on the third side surface 5C side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X.

[0064] More specifically, the cathode pad region 11C is interposed in a region between the gate pad region 11G and the anode pad region 11A, and faces both the gate pad region 11G and the anode pad region 11A in the first direction X. The cathode pad region 11C may face one or more active regions 6 in the second direction Y.

[0065] The semiconductor device 1A includes an n-type drift region 12 formed inside the chip 2. The drift region 12 may also be referred to as a "semiconductor region." The drift region 12 is formed throughout the thickness range between the first main surface 3 and the second main surface 4, and extends in a layered form along the first main surface 3 (second main surface 4).

[0066] In this embodiment, drift region 12 is formed throughout the interior of chip 2 and is exposed from first main surface 3 and first to fourth side surfaces 5A to 5D. In this embodiment, chip 2 is made of an n-type semiconductor substrate (n-type chip 2), and drift region 12 is formed using n-type chip 2.

[0067] The semiconductor device 1A includes an n-type buffer region 13 formed in a surface layer portion of the second main surface 4. The buffer region 13 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. In this embodiment, the buffer region 13 is formed in a layer shape extending along the second main surface 4 over the entire area of ​​the second main surface 4, and is exposed from the first to fourth side surfaces 5A to 5D. The presence or absence of the buffer region 13 is optional, and a configuration without the buffer region 13 may also be employed.

[0068] The semiconductor device 1A includes a p-type collector region 14 formed in a surface layer portion of the second main surface 4. The collector region 14 forms the collector of the main transistor structure T1 (transistor structure T3). The collector region 14 is formed in a region on the second main surface 4 side of the buffer region 13. The collector region 14 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, and converts the conductivity type of the drift region 12 from n-type to p-type.

[0069] Collector region 14 has a p-type impurity concentration higher than the n-type impurity concentration of buffer region 13, thereby converting the conductivity type of buffer region 13 from n-type to p-type. In this embodiment, collector region 14 is formed in a layer shape extending along second main surface 4 over the entire area of ​​second main surface 4, and is exposed from second main surface 4 and first to fourth side surfaces 5A to 5D.

[0070] The following describes the configuration of the active regions 6, the monitor region 7, the peripheral region 8, the street regions 9, the temperature detection region 10, and the pad regions 11. The semiconductor device 1A includes a plurality of transistor structures T3 formed in the active regions 6, respectively.

[0071] The plurality of transistor structures T3 are connected in parallel to each other to form one main transistor structure T1. Since the plurality of transistor structures T3 have the same configuration, the following describes the configuration of one transistor structure T3 as one component of the semiconductor device 1A.

[0072] The transistor structure T3 includes a p-type base region 15 formed in a surface layer portion of the first main surface 3 of the corresponding active region 6. The base region 15 may also be referred to as a "body region," a "channel region," or the like. The base region 15 is formed in a surface layer portion of the drift region 12. In this embodiment, the base region 15 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, thereby converting the conductivity type of the drift region 12 from n-type to p-type.

[0073] The base regions 15 are each formed in a layer shape extending along the first main surface 3 in the corresponding active region 6. The base regions 15 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with the drift region 12 sandwiched therebetween.

[0074] The transistor structure T3 includes a plurality of trench electrode type gate structures 20 formed on the first main surface 3 of the corresponding active region 6. The plurality of gate structures 20 form the gate of the main transistor structure T1 (transistor structure T3). The gate structures 20 may also be referred to as "first trench structures," "trench gate structures," etc. A gate potential is applied to the gate structures 20.

[0075] The multiple gate structures 20 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. That is, the multiple gate structures 20 are arranged in a stripe shape extending in the first direction X. Each of the multiple gate structures 20 has one end on one side (the third side surface 5C side) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X).

[0076] The multiple gate structures 20 may each have a width that is less than the width of the multiple street regions 9. The width of the gate structure 20 is the width in a direction (second direction Y) perpendicular to the extension direction of the gate structure 20 (first direction X).

[0077] The width of the gate structure 20 may be 0.5 μm or more and 5 μm or less. The width of the gate structure 20 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the gate structure 20 is preferably 1 μm or more and 2.5 μm or less.

[0078] The plurality of gate structures 20 penetrates the base region 15 to reach the drift region 12. The plurality of gate structures 20 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with part of the drift region 12 sandwiched therebetween in the thickness direction.

[0079] The plurality of gate structures 20 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of gate structures 20 may be formed substantially perpendicular to the first main surface 3. The plurality of gate structures 20 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of gate structures 20 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of gate structures 20 may be formed in a curved shape.

[0080] The plurality of gate structures 20 may each have a depth of 1 μm to 10 μm. The depth of the gate structure 20 may have a value belonging to at least one of the ranges of 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the gate structure 20 is preferably 4 μm to 8 μm.

[0081] Each of the plurality of gate structures 20 includes a gate trench 21, a gate insulating film 22, and a buried gate electrode 23. The gate trench 21 is formed in the first main surface 3, and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 20.

[0082] The gate insulating film 22 covers the wall surface of the gate trench 21. The gate insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 22 include a silicon oxide film made of an oxide of the chip 2.

[0083] The gate insulating film 22 may have a thickness of 10 nm or more and 200 nm or less. The thickness of the gate insulating film 22 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the gate insulating film 22 is preferably 100 nm or more and 150 nm or less.

[0084] The buried gate electrode 23 is buried in the gate trench 21 with the gate insulating film 22 sandwiched therebetween. The buried gate electrode 23 faces the drift region 12 and the base region 15 with the gate insulating film 22 sandwiched therebetween. An electrode surface of the buried gate electrode 23 may be located on the bottom wall side of the gate trench 21 with respect to the first main surface 3. The buried gate electrode 23 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0085] The transistor structure T3 includes a plurality of trench electrode type gate connection structures 25 formed on the first main surface 3 so as to be connected to the plurality of gate structures 20 in the corresponding active regions 6. A gate potential is applied to the plurality of gate connection structures 25. The gate connection structures 25 may also be referred to as "first trench connection structures," "trench gate connection structures," etc.

[0086] The plurality of gate connection structures 25 are respectively arranged on both end sides of the plurality of gate structures 20 in the first direction X so as to be connected to one end and the other end of the plurality of gate structures 20, and together with the outermost plurality of gate structures 20, define corresponding active regions 6.

[0087] The multiple gate connection structures 25 include a gate connection structure 25 on one end side of the multiple gate structures 20 and a gate connection structure 25 on the other end side of the multiple gate structures 20. The gate connection structure 25 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple gate structures 20. The gate connection structure 25 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple gate structures 20.

[0088] The plurality of gate connection structures 25 may each have a width approximately equal to the width of the gate structure 20. Of course, the width of the gate connection structure 25 may be larger or smaller than the width of the gate structure 20.

[0089] The width of the gate connection structure 25 may be 0.5 μm or more and 5 μm or less. The width of the gate connection structure 25 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the gate connection structure 25 is preferably 1 μm or more and 2.5 μm or less.

[0090] The plurality of gate connection structures 25 penetrate the base region 15 to reach the drift region 12. The plurality of gate connection structures 25 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 across a part of the drift region 12 in the thickness direction.

[0091] The plurality of gate connection structures 25 may be formed in a tapered shape toward their bottom walls. Of course, the plurality of gate connection structures 25 may be formed substantially perpendicular to the first main surface 3. The plurality of gate connection structures 25 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of gate connection structures 25 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of gate connection structures 25 may be formed in a curved shape.

[0092] The plurality of gate connection structures 25 may each have a depth approximately equal to the depth of the gate structure 20. Of course, the depth of the gate connection structures 25 may be greater than or less than the depth of the gate structure 20.

[0093] The depth of the plurality of gate connection structures 25 may be 0.5 μm or more and 10 μm or less. The depth of the gate connection structures 25 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the gate connection structures 25 is preferably 4 μm or more and 8 μm or less.

[0094] Each of the plurality of gate connection structures 25 includes a gate connection trench 26, a gate connection insulating film 27, and a gate connection buried electrode 28. The gate connection trench 26 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the gate connection structure 25. The gate connection trench 26 communicates with the plurality of gate trenches 21.

[0095] The gate connection insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The gate connection insulating film 27 preferably includes the same type of insulator as the gate insulating film 22. In this embodiment, the gate connection insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate connection insulating film 27 includes a silicon oxide film made of an oxide of the chip 2.

[0096] The gate connection insulating film 27 covers the wall surface of the gate connection trench 26 in a film form. The gate connection insulating film 27 is connected to the gate insulating film 22 at the communicating portion between the gate trench 21 and the gate connection trench 26.

[0097] The gate connection insulating film 27 may have a thickness substantially equal to that of the gate insulating film 22. Of course, the thickness of the gate connection insulating film 27 may be greater than or less than that of the gate insulating film 22.

[0098] The thickness of the gate connection insulating film 27 may be 10 nm or more and 200 nm or less. The thickness of the gate connection insulating film 27 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the gate connection insulating film 27 is preferably 100 nm or more and 150 nm or less.

[0099] The gate connection buried electrode 28 is buried in the gate connection trench 26 with the gate connection insulating film 27 sandwiched therebetween. The gate connection buried electrode 28 is connected to the gate buried electrode 23 at the communicating portion between the gate trench 21 and the gate connection trench 26. The gate connection buried electrode 28 faces the drift region 12 and the base region 15 with the gate connection insulating film 27 sandwiched therebetween.

[0100] The electrode surface of the gate connection buried electrode 28 may be located on the bottom wall side of the gate connection trench 26 with respect to the first main surface 3. The gate connection buried electrode 28 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate connection buried electrode 28 preferably includes the same type of conductor as the gate buried electrode 23.

[0101] The transistor structure T3 includes a plurality of trench electrode type emitter structures 30 formed on the first main surface 3 in the corresponding active regions 6. The emitter structures 30 may also be referred to as "second trench structures," "trench emitter structures," etc. A potential (emitter potential in this form) different from the gate potential is applied to the emitter structures 30.

[0102] In this embodiment, at least two emitter structures 30 are disposed in the regions between adjacent pairs of gate structures 20. Specifically, the multiple emitter structures 30 are formed in mesa regions defined by a pair of gate structures 20 and a pair of gate connection structures 25.

[0103] The plurality of emitter structures 30 extend in a strip shape in the first direction X following the extension direction of the plurality of gate structures 20 , and are formed at intervals in the second direction Y from the plurality of gate connection structures 25 .

[0104] The plurality of emitter structures 30 each have a length in the longitudinal direction (first direction X) that is shorter than the length of the plurality of gate structures 20. The plurality of emitter structures 30 each have one end on one side (the third side surface 5C side) and another end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X).

[0105] The multiple emitter structures 30 may each have a width that is less than the width of the multiple street regions 9. The width of the emitter structure 30 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the emitter structure 30. The width of the emitter structure 30 may be approximately equal to the width of the gate structure 20. Of course, the width of the emitter structure 30 may be greater than or smaller than the width of the gate structure 20.

[0106] The width of the emitter structure 30 may be 0.5 μm or more and 5 μm or less. The width of the emitter structure 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the emitter structure 30 is preferably 1 μm or more and 2.5 μm or less.

[0107] The plurality of emitter structures 30 penetrate the base region 15 to reach the drift region 12. The plurality of emitter structures 30 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with part of the drift region 12 sandwiched therebetween in the thickness direction.

[0108] The plurality of emitter structures 30 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of emitter structures 30 may be formed substantially perpendicular to the first main surface 3. The plurality of emitter structures 30 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of emitter structures 30 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of emitter structures 30 may be formed in a curved shape.

[0109] The emitter structure 30 may have a depth that is approximately equal to the depth of the gate structure 20. Of course, the depth of the emitter structure 30 may be greater than or less than the depth of the gate structure 20.

[0110] The depth of the plurality of emitter structures 30 may be 0.5 μm or more and 10 μm or less. The depth of the emitter structures 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the emitter structures 30 is preferably 4 μm or more and 8 μm or less.

[0111] The first trench pitch between the central portion of the gate structure 20 and the central portion of the emitter structure 30 may be 1 μm or more and 5 μm or less. The first trench pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first trench pitch is preferably 1.5 μm or more and 3.5 μm or less.

[0112] Each of the plurality of emitter structures 30 includes an emitter trench 31, an emitter insulating film 32, and a buried emitter electrode 33. The emitter trench 31 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the emitter structure 30.

[0113] The emitter insulating film 32 covers the wall surface of the emitter trench 31. The emitter insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The emitter insulating film 32 preferably includes the same type of insulator as the gate insulating film 22. In this embodiment, the emitter insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the emitter insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.

[0114] The emitter insulating film 32 may have a thickness approximately equal to that of the gate insulating film 22. Of course, the thickness of the emitter insulating film 32 may be greater than or less than that of the gate insulating film 22.

[0115] The emitter insulating film 32 may have a thickness of 10 nm to 200 nm. The thickness of the emitter insulating film 32 may be a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm. The thickness of the emitter insulating film 32 is preferably 100 nm to 150 nm.

[0116] The buried emitter electrode 33 is buried in the emitter trench 31 with the emitter insulating film 32 interposed therebetween. The buried emitter electrode 33 faces the drift region 12 and the base region 15 with the emitter insulating film 32 interposed therebetween.

[0117] The electrode surface of the buried emitter electrode 33 may be located on the bottom wall side of the emitter trench 31 with respect to the first main surface 3. The buried emitter electrode 33 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried emitter electrode 33 preferably includes the same type of conductor as the buried gate electrode 23.

[0118] The transistor structure T3 includes a plurality of emitter connection structures 35 formed on the first main surface 3 so as to be connected to the plurality of emitter structures 30 in the corresponding active regions 6. An emitter potential is applied to the plurality of emitter connection structures 35. The emitter connection structures 35 may also be referred to as "second trench connection structures," "trench emitter connection structures," etc.

[0119] The plurality of emitter connection structures 35 are arranged on both end sides of the plurality of emitter structures 30 in the first direction X so as to be connected to one end and the other end of the plurality of emitter structures 30 .

[0120] The multiple emitter connection structures 35 include an emitter connection structure 35 on one end side of the multiple emitter structures 30 and an emitter connection structure 35 on the other end side of the multiple emitter structures 30. The emitter connection structure 35 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple adjacent emitter structures 30. The emitter connection structure 35 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple adjacent emitter structures 30.

[0121] The plurality of emitter connection structures 35 penetrate the base region 15 to reach the drift region 12. The plurality of emitter connection structures 35 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with part of the drift region 12 sandwiched therebetween in the thickness direction.

[0122] The plurality of emitter connection structures 35 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of emitter connection structures 35 may be formed substantially perpendicular to the first main surface 3. The plurality of emitter connection structures 35 may have a bottom wall formed in a curved shape toward the second main surface 4.

[0123] Of course, the bottom walls of the plurality of emitter connection structures 35 may be formed substantially parallel to the first main surface 3. In this case, the corners of the bottom walls of the plurality of emitter connection structures 35 may be formed in a curved shape.

[0124] The plurality of emitter connection structures 35 may each have a width approximately equal to the width of the emitter structure 30 (gate structure 20). Of course, the width of the emitter connection structure 35 may be greater than or smaller than the width of the emitter structure 30.

[0125] The width of the emitter connection structure 35 may be 0.5 μm or more and 5 μm or less. The width of the emitter connection structure 35 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the emitter connection structure 35 is preferably 1 μm or more and 2.5 μm or less.

[0126] The plurality of emitter connection structures 35 may each have a depth approximately equal to the depth of the emitter structure 30 (gate structure 20). Of course, the depth of the emitter connection structure 35 may be greater than or less than the depth of the emitter structure 30.

[0127] The depth of the emitter connection structure 35 may be 0.5 μm or more and 10 μm or less. The depth of the emitter connection structure 35 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the emitter connection structure 35 is preferably 4 μm or more and 8 μm or less.

[0128] Each of the plurality of emitter connection structures 35 includes an emitter connection trench 36, an emitter connection insulating film 37, and an emitter connection buried electrode 38. The emitter connection trench 36 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the emitter connection structure 35. The emitter connection trench 36 communicates with the plurality of emitter trenches 31.

[0129] The emitter connection insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The emitter connection insulating film 37 preferably includes the same type of insulator as the emitter insulating film 32 (gate insulating film 22). In this embodiment, the emitter connection insulating film 37 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the emitter connection insulating film 37 includes a silicon oxide film made of an oxide of the chip 2.

[0130] The emitter connection insulating film 37 coats the wall surfaces of the emitter connection trench 36 in a film form. The emitter connection insulating film 37 is connected to the emitter insulating film 32 at the communicating portion between the emitter trench 31 and the emitter connection trench 36.

[0131] The emitter connection insulating film 37 may have a thickness substantially equal to that of the emitter insulating film 32 (gate insulating film 22). Of course, the thickness of the emitter connection insulating film 37 may be greater than or less than the thickness of the emitter insulating film 32 (gate insulating film 22).

[0132] The emitter connection insulating film 37 may have a thickness of 10 nm to 200 nm. The thickness of the emitter connection insulating film 37 may be a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm. The thickness of the emitter connection insulating film 37 is preferably 100 nm to 150 nm.

[0133] The emitter connection buried electrode 38 is buried in the emitter connection trench 36 with the emitter connection insulating film 37 interposed therebetween. The emitter connection buried electrode 38 is connected to the emitter buried electrode 33 at the communicating portion between the emitter trench 31 and the emitter connection trench 36. The emitter connection buried electrode 38 faces the drift region 12 and the base region 15 with the emitter connection insulating film 37 interposed therebetween.

[0134] The electrode surface of the emitter-connection buried electrode 38 may be located closer to the bottom wall of the emitter-connection trench 36 than the first main surface 3. The emitter-connection buried electrode 38 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The emitter-connection buried electrode 38 preferably includes the same type of conductor as the emitter-connection buried electrode 33 (gate buried electrode 23).

[0135] The transistor structure T3 includes a plurality of n-type emitter regions 40 (impurity regions) formed in the surface layer portion of the first main surface 3 of the corresponding active region 6. The plurality of emitter regions 40 form the emitters of the main transistor structure T1.

[0136] The emitter region 40 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. In this embodiment, the emitter region 40 has an n-type impurity concentration higher than the p-type impurity concentration of the base region 15, thereby converting the conductivity type of the base region 15 from p-type to n-type.

[0137] The plurality of emitter regions 40 are formed in the surface layer portion of the base region 15 on both sides of the plurality of gate structures 20, and extend in a strip shape in the first direction X following the extension direction of the plurality of gate structures 20. The plurality of emitter regions 40 are formed at intervals from the bottom of the base region 15 toward the first main surface 3.

[0138] The plurality of emitter regions 40 face the buried gate electrodes 23 of the corresponding gate structures 20, with the gate insulating films 22 of the corresponding gate structures 20 interposed therebetween. The plurality of emitter regions 40 may face the buried emitter electrodes 33 of the corresponding emitter structures 30, with the emitter insulating films 32 of the corresponding emitter structures 30 interposed therebetween. Of course, the plurality of emitter regions 40 may be formed at intervals from the plurality of emitter structures 30.

[0139] The transistor structure T3 includes a plurality of p-type contact regions 41 formed in regions different from the plurality of emitter regions 40 in the surface layer portion of the base region 15. The plurality of contact regions 41 have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. The plurality of contact regions 41 are formed on both sides of the plurality of gate structures 20 at intervals from the plurality of gate structures 20 and the plurality of emitter structures 30.

[0140] The plurality of contact regions 41 are formed in regions on the bottom side of the base region 15 relative to the plurality of emitter regions 40. The plurality of contact regions 41 are formed at intervals from the bottom of the base region 15 toward the first main surface 3. The plurality of contact regions 41 each extend in a strip shape in the first direction X following the extension direction of the plurality of gate structures 20.

[0141] The transistor structure T3 includes a plurality of n-type storage regions 42 formed in a surface layer portion of the first main surface 3 of the corresponding active region 6. The storage regions 42 may be referred to as "carrier storage regions." The plurality of storage regions 42 have a higher n-type impurity concentration than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the plurality of storage regions 42 may be lower than the n-type impurity concentration of the emitter region 40.

[0142] The storage regions 42 are formed in regions immediately below the base region 15 on both sides of the gate structures 20, and face the emitter regions 40 corresponding to them in the thickness direction. The storage regions 42 extend in a strip shape in the first direction X, following the extension direction of the gate structures 20.

[0143] The plurality of storage regions 42 are formed in a thickness range between the bottom of the base region 15 and the bottom wall of the gate structure 20. The plurality of storage regions 42 are formed at intervals from the depth position of the bottom wall of the gate structure 20 to the bottom side of the base region 15.

[0144] The bottoms of the plurality of storage regions 42 may be located closer to the first main surface 3 than the depth position of the intermediate portion of the gate structure 20. The bottoms of the plurality of storage regions 42 may be located closer to the bottom wall of the gate structure 20 than the depth position of the intermediate portion of the gate structure 20.

[0145] The transistor structure T3 includes a plurality of p-type well regions 43 formed in the surface layer portion of the first main surface 3 in the corresponding active region 6. The plurality of well regions 43 have a p-type impurity concentration lower than the p-type impurity concentration of the contact region 41.

[0146] The multiple well regions 43 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the multiple well regions 43 may be lower than the p-type impurity concentration of the base region 15. In this embodiment, the multiple well regions 43 are formed in an electrically floating state.

[0147] The multiple well regions 43 are formed in regions between adjacent pairs of emitter structures 30. Specifically, the multiple well regions 43 are formed in mesa regions defined by the multiple emitter structures 30 and the multiple emitter connection structures 35.

[0148] The plurality of well regions 43 each have a bottom located closer to the bottom wall of the plurality of emitter structures 30 than the depth position of the bottom of the base region 15. The bottoms of the plurality of well regions 43 are located closer to the bottom wall of the plurality of emitter structures 30 than the depth positions of the intermediate portions of the plurality of emitter structures 30. In this embodiment, the bottoms of the plurality of well regions 43 are located closer to the second main surface 4 than the bottom walls of the plurality of emitter structures 30.

[0149] The multiple well regions 43 may have portions (bottoms) covering the bottom walls of the multiple emitter structures 30 and the bottom walls of the multiple emitter connection structures 35. The multiple well regions 43 each extend in a strip shape in the first direction X following the extension direction of the emitter structures 30, and are connected to the multiple emitter structures 30 and the multiple emitter connection structures 35.

[0150] The multiple well regions 43, together with the multiple emitter structures 30, form an IE (Injection Enhanced) structure. The IE structure restricts the movement path of holes flowing into the base region 15, causing the holes to accumulate in the region directly below the base region 15. In other words, the IE structure promotes low on-resistance and low on-voltage from inside the chip 2.

[0151] 7 , semiconductor device 1A includes a p-type peripheral well region 44 formed in a surface layer portion of first main surface 3 in peripheral region 8. Peripheral well region 44 has a p-type impurity concentration that is lower than the p-type impurity concentration of contact region 41.

[0152] The peripheral well region 44 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the peripheral well region 44 may be lower than the p-type impurity concentration of the base region 15.

[0153] The p-type impurity concentration of the peripheral well region 44 may be approximately equal to the p-type impurity concentration of the well region 43. Of course, the p-type impurity concentration of the peripheral well region 44 may be higher than the p-type impurity concentration of the well region 43, or may be lower than the p-type impurity concentration of the well region 43.

[0154] The peripheral well region 44 is formed at a distance inward from the periphery of the first main surface 3, and extends in a band shape along the periphery of the first main surface 3. In this embodiment, the peripheral well region 44 is formed in an annular shape surrounding the multiple active regions 6.

[0155] The peripheral well region 44 is formed deeper than the base region 15 and is in contact with the outermost gate connection structure 25. The peripheral well region 44 is formed deeper than the outermost gate connection structure 25 and has a portion that runs along the bottom wall of the outermost gate connection structure 25. In this embodiment, the peripheral well region 44 is drawn from outside the plurality of active regions 6 into the plurality of active regions 6 and has a portion that covers the bottom walls of the plurality of gate structures 20.

[0156] The peripheral well region 44 extends in the vertical direction Z along the sidewalls of the gate structures 20 and the sidewalls of the gate connection structures 25 in the active regions 6, and is connected to the base regions 15 in the surface layer portion of the first main surface 3. An emitter potential is applied to the peripheral well region 44 via the base regions 15.

[0157] The depth of the peripheral well region 44 may be approximately equal to the depth of the multiple well regions 43. Of course, the depth of the peripheral well region 44 may be greater than the depth of the multiple well regions 43, or may be smaller than the depth of the multiple well regions 43.

[0158] 8 , the semiconductor device 1A includes a plurality of p-type street well regions 45 formed in the surface layer portion of the first main surface 3 in the plurality of street regions 9. One street well region 45 has a portion formed in the surface layer portion of the first main surface 3 in the temperature detection region 10.

[0159] The street well region 45 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the street well region 45 may be lower than the p-type impurity concentration of the base region 15.

[0160] The p-type impurity concentration of the street well region 45 may be approximately equal to the p-type impurity concentration of the well region 43. Of course, the p-type impurity concentration of the street well region 45 may be higher than the p-type impurity concentration of the well region 43, or may be lower than the p-type impurity concentration of the well region 43.

[0161] The p-type impurity concentration of the street well region 45 may be approximately equal to the p-type impurity concentration of the peripheral well region 44. Of course, the p-type impurity concentration of the street well region 45 may be higher than the p-type impurity concentration of the peripheral well region 44, or may be lower than the p-type impurity concentration of the peripheral well region 44.

[0162] The plurality of street well regions 45 are formed in layers extending along the first main surface 3 in a region between the gate connection structure 25 on one active region 6 side and the gate connection structure 25 on the other active region 6 side, and are exposed from the first main surface 3. The plurality of street well regions 45 each extend in a strip shape in the second direction Y following the extension direction of the plurality of street regions 9. The plurality of street well regions 45 are connected to the peripheral well region 44 in the peripheral region 8.

[0163] The plurality of street well regions 45 are formed deeper than the plurality of base regions 15 and are in contact with the plurality of gate connection structures 25. Specifically, the plurality of street well regions 45 are formed deeper than the plurality of gate connection structures 25 and have portions along the bottom walls of the plurality of gate connection structures 25.

[0164] In this form, the plurality of street well regions 45 have widths greater than the widths of the corresponding street regions 9, extend from the corresponding street regions 9 into the plurality of active regions 6, and have portions covering the bottom walls of the plurality of gate structures 20.

[0165] The plurality of street well regions 45 extend in the vertical direction Z along the sidewalls of the plurality of gate structures 20 and the sidewalls of the plurality of gate connection structures 25 in the plurality of active regions 6, and are connected to the plurality of base regions 15 in the surface layer portion of the first main surface 3. An emitter potential is applied to the plurality of street well regions 45 via the plurality of base regions 15.

[0166] The depth of the plurality of street well regions 45 may be approximately equal to the depth of the plurality of well regions 43. Of course, the depth of the plurality of street well regions 45 may be greater than the depth of the plurality of well regions 43 or may be smaller than the depth of the plurality of street well regions 45.

[0167] The depth of the plurality of street well regions 45 may be approximately equal to the depth of the periphery well region 44. Of course, the depth of the plurality of street well regions 45 may be greater than the depth of the periphery well region 44 or may be less than the depth of the periphery well region 44.

[0168] Fig. 9 is an enlarged plan view showing a main part of the monitor area 7. Fig. 10 is a cross-sectional view taken along line XX in Fig. 9. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 9.

[0169] 9 to 11 , semiconductor device 1A includes a monitor transistor structure T2 in monitor region 7. Similar to transistor structure T3 (active region 6), monitor transistor structure T2 (monitor region 7) includes a base region 15, a plurality of gate structures 20, a plurality of gate connection structures 25, a plurality of emitter structures 30, a plurality of emitter connection structures 35, a plurality of emitter regions 40, a contact region 41, a plurality of storage regions 42, and a plurality of well regions 43.

[0170] The base region 15, gate structure 20, gate connection structure 25, emitter structure 30, emitter connection structure 35, emitter region 40, contact region 41, storage region 42 and well region 43 of the monitor region 7 may be referred to as the "monitor base region (15)", "monitor gate structure (20)", "monitor gate connection structure (25)", "monitor emitter structure (30)", "monitor emitter connection structure (35)", "monitor emitter region (40)", "monitor contact region (41)", "monitor storage region (42)" and "monitor well region (43)", respectively.

[0171] These components in the monitor region 7 have a layout similar to that of the corresponding components in the active region 6. The description of the corresponding components in the active region 6 also applies to the description of these components in the monitor region 7. These components in the monitor region 7 are laid out in a plane area smaller than the total plane area of ​​the multiple active regions 6.

[0172] In other words, since the channel area of ​​the monitor region 7 (the total area of ​​the emitter region 40) is smaller than the channel area of ​​the active region 6 (the total area of ​​the emitter region 40), the monitor current Im of the monitor transistor structure T2 is less than the output current Ice of the main transistor structure T1 (transistor structure T3).

[0173] The semiconductor device 1A includes a main surface insulating film 48 that selectively covers the first main surface 3. The main surface insulating film 48 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0174] The main surface insulating film 48 preferably contains the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the main surface insulating film 48 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 48 contains a silicon oxide film made of an oxide of the chip 2.

[0175] The main surface insulating film 48 has a portion that selectively covers the multiple active regions 6, a portion that selectively covers the monitor region 7, a portion that selectively covers the peripheral region 8, and a portion that selectively covers the multiple street regions 9.

[0176] The main surface insulating film 48 covers the base regions 15, the emitter regions 40, and the well regions 43 in the active regions 6. The main surface insulating film 48 is connected to the gate insulating films 22, the gate connection insulating films 27, the emitter insulating films 32, and the emitter connection insulating films 37 in the active regions 6, and exposes the gate buried electrodes 23, the gate connection buried electrodes 28, the emitter buried electrodes 33, and the emitter connection buried electrodes 38.

[0177] The main surface insulating film 48 covers the plurality of base regions 15, the plurality of emitter regions 40, and the plurality of well regions 43 in the monitor region 7. The main surface insulating film 48 is connected to the plurality of gate insulating films 22, the plurality of gate connection insulating films 27, the plurality of emitter insulating films 32, and the plurality of emitter connection insulating films 37 in the monitor region 7, and exposes the plurality of gate buried electrodes 23, the plurality of gate connection buried electrodes 28, the plurality of emitter buried electrodes 33, and the plurality of emitter connection buried electrodes 38.

[0178] The main surface insulating film 48 covers the peripheral well region 44 in the peripheral region 8. The main surface insulating film 48 is connected to the plurality of gate connection insulating films 27 in the peripheral region 8, and exposes the plurality of gate connection buried electrodes 28.

[0179] The main surface insulating film 48 may be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Of course, the main surface insulating film 48 may be formed at a distance inward from the periphery of the chip 2, exposing the drift region 12 from the periphery of the chip 2.

[0180] The main surface insulating film 48 covers the plurality of street well regions 45 in the plurality of street regions 9. The main surface insulating film 48 is connected to the plurality of gate connection insulating films 27 in the plurality of street regions 9, and exposes the plurality of gate connection buried electrodes 28.

[0181] The main surface insulating film 48 may have a thickness substantially equal to that of the gate insulating film 22 (gate connection insulating film 27). Of course, the thickness of the main surface insulating film 48 may be greater than or less than the thickness of the gate insulating film 22 (gate connection insulating film 27).

[0182] The thickness of the main surface insulating film 48 may be approximately equal to the thickness of the emitter insulating film 32 (emitter connection insulating film 37). Of course, the thickness of the main surface insulating film 48 may be greater than the thickness of the emitter insulating film 32 (emitter connection insulating film 37) or may be smaller than the thickness of the emitter insulating film 32 (emitter connection insulating film 37).

[0183] The thickness of the main surface insulating film 48 may be 10 nm or more and 200 nm or less. The thickness of the main surface insulating film 48 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the main surface insulating film 48 is preferably 100 nm or more and 150 nm or less.

[0184] Fig. 12 is an enlarged plan view showing the temperature measurement region 10. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 12. With reference to Figs. 12 and 13, the semiconductor device 1A includes a temperature sensing diode structure D arranged on the main surface insulating film 48 in the temperature measurement region 10. The configuration of the temperature sensing diode structure D as one component of the semiconductor device 1A will be described below.

[0185] The temperature sensitive diode structure D includes one or more (multiple in this embodiment) polysilicon layers 50 disposed on the main surface insulating film 48. The number of polysilicon layers 50 is arbitrary and is adjusted as appropriate depending on the number of first diodes D1 and the number of second diodes D2.

[0186] In this embodiment, the semiconductor device 1A includes four polysilicon layers 50 for the first diode D1 and four polysilicon layers 50 for the second diode D2. In this embodiment, the multiple polysilicon layers 50 are arranged in a matrix of 4 rows and 2 columns with intervals in the first direction X and the second direction Y.

[0187] In this embodiment, four polysilicon layers 50 for the first diode D1 are arranged in a row in a first column (one side in the second direction Y), and four polysilicon layers 50 for the second diode D2 are arranged in a row in a second column (the other side in the second direction Y).

[0188] The multiple polysilicon layers 50 are disposed directly on the main surface insulating film 48 and face the street well region 45 across the main surface insulating film 48. In this embodiment, the multiple polysilicon layers 50 are formed in a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view. The multiple polysilicon layers 50 may also be formed in a rectangular, hexagonal, circular, or other shape in a plan view.

[0189] The multiple polysilicon layers 50 have a thickness greater than the thickness of the main surface insulating film 48. The thickness of the multiple polysilicon layers 50 may be less than the depth (thickness) of the street well region 45. The thickness of the multiple polysilicon layers 50 may be less than the depth of the gate structure 20 (emitter structure 30). The thickness of the multiple polysilicon layers 50 may be less than the depth of the gate connection structure 25 (emitter connection structure 35).

[0190] The thickness of the multiple polysilicon layers 50 may be 0.1 μm or more and 2 μm or less. The thickness of the polysilicon layer 50 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the polysilicon layer 50 is preferably 0.25 μm or more and 1.25 μm or less.

[0191] The temperature sensitive diode structure D includes a plurality of p-type anode regions 51 formed in each of a plurality of polysilicon layers 50. The anode regions 51 are formed in the inner portion (preferably the central portion) of the corresponding polysilicon layer 50 at intervals from the periphery of the corresponding polysilicon layer 50.

[0192] The plurality of anode regions 51 are formed in a polygonal or circular shape in plan view. The plurality of anode regions 51 may also be formed in a quadrangular, hexagonal, or other shape in plan view. The plurality of anode regions 51 are formed throughout the thickness range of the corresponding polysilicon layer 50.

[0193] The temperature sensitive diode structure D includes a plurality of n-type cathode regions 52 formed in a plurality of polysilicon layers 50. The plurality of cathode regions 52 are formed in the peripheral portions of the corresponding polysilicon layers 50, respectively.

[0194] In plan view, the plurality of cathode regions 52 each extend in a band shape along the periphery of the corresponding anode region 51. In this embodiment, the plurality of cathode regions 52 each extend in an annular shape along the periphery of the corresponding polysilicon layer 50 in plan view, and are each electrically connected to the corresponding anode region 51 over the entire periphery.

[0195] The plurality of cathode regions 52 are formed throughout the thickness range of the corresponding polysilicon layer 50, and are exposed from the sidewalls of the corresponding polysilicon layer 50. The plurality of cathode regions 52 and the corresponding anode regions 51 form pn junctions as the first diode D1 or pn junctions as the second diode D2, respectively.

[0196] 1 to 11 , the semiconductor device 1A includes a plurality of emitter interconnections 55 that are electrically connected to corresponding emitter connection structures 35 on the first main surface 3 in the plurality of active regions 6 and the monitor region 7.

[0197] The plurality of emitter wirings 55 are respectively disposed on the main surface insulating film 48 and connected to the corresponding emitter connection structures 35. In this embodiment, the plurality of emitter wirings 55 are respectively formed integrally with the corresponding emitter connection buried electrodes 38, and each comprises an extension portion that is extended from the corresponding emitter connection buried electrode 38 onto the main surface insulating film 48.

[0198] That is, the plurality of emitter wirings 55 are each made of the same type of conductor (either p-type conductive polysilicon or n-type conductive polysilicon, or both) as the emitter connection buried electrode 38. The plurality of emitter wirings 55 are formed at intervals from the plurality of gate connection structures 25 toward the corresponding emitter connection structures 35, and face the base region 15 in the thickness direction with the main surface insulating film 48 sandwiched therebetween.

[0199] The plurality of emitter interconnections 55 have a thickness greater than the thickness of the main surface insulating film 48. The thickness of the plurality of emitter interconnections 55 may be less than the depth (thickness) of the well region 43. The thickness of the plurality of emitter interconnections 55 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the plurality of emitter interconnections 55 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0200] The thickness of the plurality of emitter wirings 55 may be approximately equal to the thickness of the plurality of polysilicon layers 50. Of course, the thickness of the plurality of emitter wirings 55 may be greater than the thickness of the plurality of polysilicon layers 50 or may be smaller than the thickness of the plurality of polysilicon layers 50.

[0201] The thickness of the plurality of emitter interconnections 55 may be 0.1 μm or more and 2 μm or less. The thickness of the emitter interconnections 55 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the emitter interconnections 55 is preferably 0.25 μm or more and 1.25 μm or less.

[0202] The semiconductor device 1A includes a plurality of gate wirings 56 electrically connected to corresponding gate connection structures 25 on the first main surface 3 in the periphery region 8 and a plurality of street regions 9 .

[0203] The plurality of gate wirings 56 are respectively disposed on the main surface insulating film 48 and connected to the corresponding gate connection structures 25. In this embodiment, the plurality of gate wirings 56 are respectively formed integrally with the corresponding gate connection buried electrodes 28, and each comprises an extension portion that is extended from the corresponding gate connection buried electrode 28 onto the main surface insulating film 48. In other words, the plurality of gate wirings 56 are each made of the same type of conductor as the gate connection buried electrode 28 (either one or both of p-type conductive polysilicon and n-type conductive polysilicon).

[0204] The multiple gate wirings 56 include one or more (multiple in this embodiment) first gate wirings 56A arranged in the peripheral region 8, and one or more (multiple in this embodiment) second gate wirings 56B arranged in the multiple street regions 9.

[0205] The plurality of first gate wirings 56A are arranged on the main surface insulating film 48 in the peripheral region 8, and are routed in strip-like fashion in the region between the gate pad region 11G and the corresponding gate connection structure 25 (gate connection buried electrode 28). The plurality of first gate wirings 56A are formed along the plurality of active regions 6, and each have a portion extending in the first direction X and a portion extending in the second direction Y.

[0206] The plurality of first gate wirings 56A face the peripheral well region 44 across the main surface insulating film 48. The plurality of first gate wirings 56A are drawn from above the main surface insulating film 48 onto the gate connection structure 25 (gate connection buried electrode 28) adjacent to the peripheral region 8, and are connected to the gate connection structure 25 (gate connection buried electrode 28). The plurality of first gate wirings 56A are electrically connected to the plurality of gate structures 20 via the gate connection structure 25 (gate connection buried electrode 28).

[0207] The multiple second gate wirings 56B are respectively arranged on the main surface insulating film 48 in the multiple street regions 9, and are routed in a strip-like manner in the region between the gate pad region 11G and the corresponding gate connection structure 25 (gate connection buried electrode 28).

[0208] The plurality of second gate wirings 56B each extend in a strip shape in the second direction Y following the extension direction of the plurality of street regions 9. One second gate wiring 56B is routed in the street region 9 so as to bypass the plurality of polysilicon layers 50 (temperature sensitive diode structures D).

[0209] The plurality of second gate wirings 56B are respectively connected to the gate connection structures 25 (gate connection buried electrodes 28) of one and the other active regions 6 adjacent to each other in the first direction X. In other words, the plurality of second gate wirings 56B are electrically connected to the plurality of gate structures 20 via the plurality of gate connection structures 25 (gate connection buried electrodes 28) that define the plurality of street regions 9.

[0210] At least one of the gate wirings 56 (one second gate wiring 56B in this embodiment) is connected to the gate connection structure 25 (gate connection buried electrode 28) in the monitor region 7. As a result, the gate structure 20 in the monitor region 7 is on / off controlled simultaneously with the gate structure 20 in the active region 6.

[0211] The gate wirings 56 have a thickness greater than that of the main surface insulating film 48. The thickness of the gate wirings 56 may be less than the depth (thickness) of the well region 43. The thickness of the gate wirings 56 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the gate wirings 56 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0212] The thickness of the plurality of gate wirings 56 may be approximately equal to the thickness of the plurality of polysilicon layers 50. Of course, the thickness of the plurality of gate wirings 56 may be greater than the thickness of the plurality of polysilicon layers 50 or may be smaller than the thickness of the plurality of polysilicon layers 50.

[0213] The thickness of the plurality of gate wirings 56 may be approximately equal to the thickness of the plurality of emitter wirings 55. Of course, the thickness of the plurality of gate wirings 56 may be greater than the thickness of the plurality of emitter wirings 55 or may be smaller than the thickness of the plurality of emitter wirings 55.

[0214] The thickness of the plurality of gate wirings 56 may be 0.1 μm or more and 2 μm or less. The thickness of the gate wirings 56 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the gate wirings 56 is preferably 0.25 μm or more and 1.25 μm or less.

[0215] The semiconductor device 1A includes an interlayer film 57 that selectively covers the main surface insulating film 48. The interlayer film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 57 may have a single-layer structure made of a single insulating film, or a layered structure including a plurality of insulating films.

[0216] The interlayer film 57 may include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film, which are examples of silicon oxide films.

[0217] The interlayer film 57 has a portion covering a plurality of active regions 6, a portion covering the monitor region 7, a portion covering the peripheral region 8, a portion covering a plurality of street regions 9, and a portion covering the temperature measurement region 10.

[0218] The interlayer film 57 covers the base regions 15, the emitter regions 40, and the well regions 43 with the main surface insulating film 48 sandwiched therebetween in the active regions 6 and the monitor region 7. The interlayer film 57 covers the gate structures 20, the gate connection structures 25, the emitter structures 30, and the emitter connection structures 35 in the active regions 6 and the monitor region 7.

[0219] Specifically, the interlayer film 57 covers the plurality of gate buried electrodes 23, the plurality of gate connection buried electrodes 28, the plurality of emitter buried electrodes 33, and the plurality of emitter connection buried electrodes 38. In this embodiment, the interlayer film 57 extends from above the main surface insulating film 48 into the plurality of gate trenches 21, the plurality of gate connection trenches 26, the plurality of emitter trenches 31, and the plurality of emitter connection trenches 36.

[0220] The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried gate electrodes 23 in the plurality of gate trenches 21. The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried gate connection electrodes 28 in the plurality of gate connection trenches 26.

[0221] The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried emitter electrodes 33 in the plurality of emitter trenches 31. The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried emitter electrodes 38 in the plurality of emitter connection trenches 36.

[0222] The interlayer film 57 covers the peripheral well region 44 in the peripheral region 8, sandwiching the main surface insulating film 48. The interlayer film 57 may be continuous with the peripheral edge (first to fourth side surfaces 5A to 5D) of the chip 2. Of course, the interlayer film 57 may be formed at a distance inward from the peripheral edge of the chip 2, exposing the drift region 12 from the peripheral portion of the chip 2.

[0223] The interlayer film 57 covers the street well regions 45 in the street regions 9 with the main surface insulating film 48 interposed therebetween. The interlayer film 57 covers the polysilicon layers 50 in the temperature detection region 10.

[0224] The interlayer film 57 fills the gaps between the polysilicon layers 50 and collectively covers the polysilicon layers 50. The interlayer film 57 contacts the main surface insulating film 48 at the gaps. That is, the interlayer film 57 faces the street well region 45 at the gaps, with the main surface insulating film 48 sandwiched therebetween.

[0225] The interlayer film 57 has a thickness greater than that of the main surface insulating film 48. The thickness of the interlayer film 57 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the interlayer film 57 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0226] The thickness of the interlayer film 57 is preferably greater than the thickness of the plurality of polysilicon layers 50. Of course, the thickness of the interlayer film 57 may be less than the thickness of the plurality of polysilicon layers 50. The thickness of the interlayer film 57 is preferably greater than the thickness of the plurality of emitter wirings 55.

[0227] Of course, the thickness of the interlayer film 57 may be smaller than the thickness of the plurality of emitter wirings 55. The thickness of the interlayer film 57 is preferably larger than the thickness of the plurality of gate wirings 56. Of course, the thickness of the interlayer film 57 may be smaller than the thickness of the plurality of gate wirings 56.

[0228] The interlayer film 57 may have a thickness of 0.1 μm or more and 3 μm or less. The thickness of the interlayer film 57 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The thickness of the interlayer film 57 is preferably 0.5 μm or more and 2 μm or less.

[0229] The semiconductor device 1A includes a plurality of first emitter openings 58 formed in an interlayer film 57 in the plurality of active regions 6 and the monitor region 7. The plurality of first emitter openings 58 are formed on both sides of the plurality of gate structures 20 at intervals from the plurality of gate structures 20, and penetrate the main surface insulating film 48 and the interlayer film 57 to expose the chip 2. Specifically, the plurality of first emitter openings 58 expose the corresponding emitter regions 40 and the corresponding contact regions 41, respectively.

[0230] The plurality of first emitter openings 58 are dug down from the height position of the first main surface 3 in the thickness direction of the chip 2, and each have a bottom wall located inside the chip 2. The bottom walls of the plurality of first emitter openings 58 are formed at intervals from the bottoms of the corresponding base regions 15 toward the first main surface 3, and each exposes the corresponding contact region 41. The bottom walls of the plurality of first emitter openings 58 are formed at intervals from the bottoms of the corresponding contact regions 41 toward the first main surface 3.

[0231] The first emitter openings 58 may be tapered toward the bottom wall. Of course, the first emitter openings 58 may be formed substantially perpendicular to the first main surface 3. The first emitter openings 58 may have a bottom wall that is curved toward the second main surface 4.

[0232] Of course, the plurality of first emitter openings 58 may be formed substantially parallel to the first main surface 3. In this case, the corners of the bottom walls of the plurality of first emitter openings 58 may be formed in a curved shape.

[0233] The multiple first emitter openings 58 each extend in a strip shape in the first direction X following the extension direction of the multiple gate structures 20. The multiple first emitter openings 58 each have a length in the longitudinal direction (first direction X) that is shorter than the length of the multiple gate structures 20. The length of the multiple first emitter openings 58 may be shorter than the length of the multiple emitter structures 30.

[0234] The semiconductor device 1A includes a plurality of first emitter via electrodes 59 respectively embedded in the plurality of first emitter openings 58. The plurality of first emitter via electrodes 59 are electrically connected to the corresponding emitter regions 40 and the corresponding contact regions 41 in the plurality of first emitter openings 58.

[0235] The plurality of first emitter via electrodes 59 may have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the wall surface side of the plurality of first emitter openings 58 .

[0236] The first electrode 60 is formed as a film on the wall surface of the first emitter opening 58 as a barrier electrode. The first electrode 60 is electrically connected to the emitter region 40 and the contact region 41 within the first emitter opening 58.

[0237] The first electrode 60 may have a single layer structure including a titanium film or a titanium nitride film. The first electrode 60 may have a layered structure including a titanium film and a titanium nitride film. In this case, the titanium nitride film may be layered on the titanium film.

[0238] The second electrode 61 is embedded in the first emitter opening 58 with the first electrode 60 sandwiched therebetween, and is electrically connected to the emitter region 40 and the contact region 41 via the first electrode 60. The second electrode 61 may include at least one of a tungsten film, a molybdenum film, a nickel film, a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The second electrode 61 preferably includes a tungsten film.

[0239] The semiconductor device 1A includes a plurality of second emitter openings 62 formed in the interlayer film 57 in the plurality of active regions 6 and the monitor region 7. The plurality of second emitter openings 62 penetrate the interlayer film 57 and expose the corresponding emitter wirings 55, respectively.

[0240] In this embodiment, the plurality of second emitter openings 62 are dug further downward from the wiring surface of the corresponding emitter wiring 55 toward the main surface insulating film 48 side, and each have a bottom wall positioned within the corresponding emitter wiring 55.

[0241] The second emitter openings 62 may be formed in a tapered shape toward the bottom wall. Of course, the second emitter openings 62 may be formed substantially perpendicular to the first main surface 3. The second emitter openings 62 may be formed in a polygonal shape, a circular shape, or the like in a plan view. The second emitter openings 62 may be formed in a quadrangular shape or a hexagonal shape in a plan view.

[0242] The semiconductor device 1A includes a plurality of second emitter via electrodes 63 respectively embedded in the plurality of second emitter openings 62. The plurality of second emitter via electrodes 63 are mechanically and electrically connected to the corresponding emitter wirings 55 in the plurality of second emitter openings 62. Like the first emitter via electrode 59, the plurality of second emitter via electrodes 63 may have a stacked structure including a first electrode 60 and a second electrode 61.

[0243] The semiconductor device 1A includes the aforementioned emitter pad EP that collectively covers the multiple active regions 6 on the first main surface 3. The emitter pad EP is a terminal to which an emitter potential is applied from the outside. The emitter pad EP may also be called an "emitter pad electrode," an "emitter terminal electrode," an "emitter external terminal," or the like.

[0244] The emitter pad EP is disposed on a portion of the interlayer film 57 that covers the active regions 6. The emitter pad EP is electrically isolated from the gate structures 20 and the gate connection structures 25 by the interlayer film 57.

[0245] The emitter pad EP is mechanically and electrically connected to a plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63 on the interlayer film 57, and is electrically connected to a plurality of emitter structures 30, a plurality of emitter connection structures 35, a plurality of emitter regions 40 and a plurality of contact regions 41 via the plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63.

[0246] The emitter pad EP has a plurality of street removal portions 64. The plurality of street removal portions 64 expose portions of the interlayer film 57 that cover the plurality of street regions 9, and extend in a strip shape in the second direction Y following the extension direction of the corresponding street regions 9.

[0247] The emitter pad EP may have a thickness greater than that of the interlayer film 57. The thickness of the emitter pad EP may be 0.5 μm or more and 10 μm or less. The thickness of the emitter pad EP may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less.

[0248] The emitter pad EP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is electrically connected to a plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63 on the interlayer film 57.

[0249] The first electrode film 65 is connected to the first electrodes 60 of the plurality of first emitter via electrodes 59 and the first electrodes 60 of the plurality of second emitter via electrodes 63. Of course, the first electrode film 65 may cover the first electrodes 60 of the plurality of first emitter via electrodes 59 and the first electrodes 60 of the plurality of second emitter via electrodes 63.

[0250] The first electrode film 65 may have a single layer structure including a titanium film or a titanium nitride film. The first electrode film 65 may have a laminated structure including a titanium film and a titanium nitride film. In this case, the titanium nitride film may be laminated on the titanium film.

[0251] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 covers the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63 in a film-like manner.

[0252] The second electrode film 66 is electrically connected to the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63. The second electrode 61 may include at least one of a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0253] The semiconductor device 1A includes a monitor electrode 67 covering the monitor region 7 on the first main surface 3. The monitor electrode 67 is disposed on a portion of the interlayer film 57 covering the monitor region 7. The monitor electrode 67 is electrically isolated from the plurality of gate structures 20 and the plurality of gate connection structures 25 by the interlayer film 57 in the monitor region 7. The monitor electrode 67 is mechanically and electrically connected to the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63 on the interlayer film 57 in the monitor region 7.

[0254] The monitor electrode 67 is electrically connected to the plurality of emitter structures 30, the plurality of emitter connection structures 35, the plurality of emitter regions 40, and the plurality of contact regions 41 via the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63. Similar to the emitter pad EP, the monitor electrode 67 may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side.

[0255] The monitor electrode 67 may have a thickness greater than that of the interlayer film 57. The thickness of the monitor electrode 67 may be approximately equal to that of the emitter pad EP. The thickness range of the monitor electrode 67 is the same as the thickness range of the emitter pad EP (0.5 μm to 10 μm).

[0256] The semiconductor device 1A includes a plurality of gate openings 68 formed in the interlayer film 57 in the peripheral region 8 and the plurality of street regions 9. The plurality of gate openings 68 penetrate the interlayer film 57 and selectively expose portions of the plurality of gate wirings 56.

[0257] The multiple gate openings 68 may each extend in a strip shape following the extension direction of the multiple gate wirings 56. The multiple gate openings 68 may also be formed at intervals following the extension direction of the multiple gate wirings 56. In this case, the multiple gate openings 68 may be formed in a polygonal or circular shape in a plan view. The multiple gate openings 68 may also be formed in a quadrangular, hexagonal, or other shape in a plan view.

[0258] In this embodiment, the plurality of gate openings 68 are dug further downward from the wiring surface of the corresponding gate wiring 56 toward the main surface insulating film 48, and each have a bottom wall located within the corresponding gate wiring 56. The plurality of gate openings 68 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of gate openings 68 may also be formed approximately perpendicular to the first main surface 3.

[0259] The semiconductor device 1A includes a plurality of gate via electrodes 69 embedded in the plurality of gate openings 68. The plurality of gate via electrodes 69 are mechanically and electrically connected to the corresponding gate wirings 56 in the plurality of gate openings 68. Like the first emitter via electrode 59, the plurality of gate via electrodes 69 may have a stacked structure including a first electrode 60 and a second electrode 61.

[0260] The semiconductor device 1A includes a plurality of gate fingers 70 arranged on an interlayer film 57. The gate fingers 70 may also be referred to as "gate finger electrodes" or "finger electrodes." The plurality of gate fingers 70 are arranged on portions of the interlayer film 57 that cover the plurality of gate wirings 56.

[0261] The plurality of gate fingers 70 are mechanically and electrically connected to the plurality of gate via electrodes 69 on the interlayer film 57, and are electrically connected to the plurality of gate wirings 56 through the plurality of gate via electrodes 69. The plurality of gate fingers 70 are electrically connected to the plurality of gate structures 20 in the plurality of active regions 6 and the plurality of gate structures 20 in the monitor region 7 through the plurality of gate wirings 56.

[0262] The multiple gate fingers 70 include multiple first gate fingers 70A arranged in the outer periphery region 8 and multiple second gate fingers 70B arranged in multiple street regions 9.

[0263] The first gate fingers 70A are respectively arranged on the first gate wirings 56A in the peripheral region 8. The first gate fingers 70A are routed in a strip shape in the region between the gate pad region 11G and the corresponding gate connection structures 25 (gate connection buried electrodes 28) following the extension direction of the first gate wirings 56A.

[0264] The first gate fingers 70A are formed along the active regions 6, and each have a portion extending in the first direction X and a portion extending in the second direction Y. The first gate fingers 70A are mechanically and electrically connected to the gate via electrodes 69 on the interlayer film 57, and are electrically connected to the first gate wirings 56A via the gate via electrodes 69.

[0265] The second gate fingers 70B are respectively arranged on the second gate wirings 56B in the street regions 9. The second gate fingers 70B are routed in a strip shape in the region between the gate pad region 11G and the corresponding gate connection structures 25 (gate connection buried electrodes 28) following the extension direction of the first gate wirings 56A.

[0266] The second gate fingers 70B each have a portion interposed in the street removal portions 64 of the emitter pad EP, and extend in a strip shape in the second direction Y following the extension direction of the corresponding street region 9. One second gate finger 70B is routed through the street region 9 so as to bypass the polysilicon layers 50 (temperature sensitive diode structures D).

[0267] The second gate fingers 70B are mechanically and electrically connected to the gate via electrodes 69 on the interlayer film 57, and are electrically connected to the second gate wirings 56B via the gate via electrodes 69. Similar to the emitter pad EP, the gate fingers 70 may have a layered structure including a first electrode film 65 and a second electrode film 66 layered in this order from the interlayer film 57 side.

[0268] The gate finger 70 may have a thickness greater than that of the interlayer film 57. The thickness of the gate finger 70 may be approximately equal to that of the emitter pad EP. The thickness range of the gate finger 70 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0269] 12 and 13 , the semiconductor device 1A includes, in the temperature detection region 10, a plurality of anode openings 71 formed in portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of anode openings 71 penetrate the interlayer film 57 and expose the corresponding anode regions 51. The plurality of anode openings 71 each extend in a strip shape along the corresponding anode region 51 in a plan view.

[0270] In this embodiment, the multiple anode openings 71 are formed in an annular shape extending along the corresponding anode regions 51 in a plan view, and surround the corresponding cathode regions 52. The multiple anode openings 71 may be formed in a square, hexagonal, polygonal, circular, or other annular shape in a plan view. Of course, the multiple anode openings 71 may also be formed in an annular shape with ends extending along the corresponding anode openings 71.

[0271] The semiconductor device 1A includes, in the temperature detection region 10, a plurality of cathode openings 72 formed in portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of cathode openings 72 penetrate the interlayer film 57 at intervals corresponding to the plurality of anode openings 71, and expose the corresponding cathode regions 52. The plurality of cathode openings 72 each extend in a strip shape along the corresponding cathode region 52.

[0272] In this embodiment, the multiple cathode openings 72 are formed in an annular shape with ends that extends along the corresponding cathode regions 52 in a plan view and surround the corresponding anode regions 51. The multiple cathode openings 72 may be formed in an annular shape with ends, such as a square annular shape, a hexagonal annular shape with ends, a polygonal annular shape with ends, or a circular annular shape with ends in a plan view. Of course, the multiple cathode openings 72 may be formed in a square, hexagonal, polygonal, or circular shape in a plan view.

[0273] The semiconductor device 1A includes a plurality of anode via electrodes 73 respectively embedded in the plurality of anode openings 71. The anode via electrodes 73 are mechanically and electrically connected to the corresponding anode regions 51 in the corresponding anode openings 71. The anode via electrodes 73 may have a stacked structure including a first electrode 60 and a second electrode 61, similar to the plurality of first emitter via electrodes 59.

[0274] The semiconductor device 1A includes a plurality of cathode via electrodes 74 respectively embedded in the plurality of cathode openings 72. The plurality of cathode via electrodes 74 are mechanically and electrically connected to the corresponding cathode regions 52 in the corresponding cathode openings 72. The plurality of cathode via electrodes 74 may have a stacked structure including a first electrode 60 and a second electrode 61, similar to the plurality of first emitter via electrodes 59.

[0275] The semiconductor device 1A includes an anode wiring 75 disposed on the interlayer film 57. The anode wiring 75 is routed from the temperature detection region 10 to the anode pad region 11A via the street region 9. The anode wiring 75 has a portion that extends in a strip shape in the second direction Y within the street region 9 following the extension direction of the street region 9, and a portion that extends in a strip shape in an arbitrary direction (first direction X) outside the street region 9 toward the anode pad region 11A.

[0276] The anode wiring 75 has a portion that extends parallel to the gate finger 70 in the street region 9. Like the emitter pad EP, the anode wiring 75 may have a laminated structure including a first electrode film 65 and a second electrode film 66 that are laminated in this order from the interlayer film 57 side.

[0277] The anode wiring 75 may have a thickness greater than that of the interlayer film 57. The thickness of the anode wiring 75 may be approximately equal to that of the emitter pad EP. The thickness range of the anode wiring 75 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0278] The semiconductor device 1A includes a cathode wiring 76 disposed on the interlayer film 57. The cathode wiring 76 is routed from the temperature detection region 10 to the cathode pad region 11C via the street region 9. The cathode wiring 76 has a portion that extends in a strip shape in the second direction Y in the street region 9 following the extension direction of the street region 9, and a portion that extends in a strip shape in an arbitrary direction (first direction X) outside the street region 9 toward the cathode pad region 11C.

[0279] The cathode wiring 76 has a portion that extends parallel to both the gate finger 70 and the anode wiring 75 within the street region 9. Like the emitter pad EP, the cathode wiring 76 may have a laminated structure including a first electrode film 65 and a second electrode film 66 that are laminated in this order from the interlayer film 57 side.

[0280] The cathode wiring 76 may have a thickness greater than that of the interlayer film 57. The thickness of the cathode wiring 76 may be approximately equal to that of the emitter pad EP. The thickness range of the cathode wiring 76 is the same as the thickness range of the emitter pad EP (0.5 μm to 10 μm).

[0281] The semiconductor device 1A includes a plurality of anode connection wirings 77 formed on portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The anode connection wirings 77 have portions that extend along the corresponding anode via electrodes 73 on the interlayer film 57, and are mechanically and electrically connected to the corresponding anode via electrodes 73, respectively.

[0282] The multiple anode connection wirings 77 may be formed in a polygonal shape, a circular shape, etc. in a planar view. The multiple anode connection wirings 77 may be formed in a quadrangular shape, a hexagonal shape, etc. in a planar view. Similar to the emitter pad EP, the multiple anode connection wirings 77 may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side.

[0283] The anode connecting wiring 77 may have a thickness greater than that of the interlayer film 57. The thickness of the anode connecting wiring 77 may be approximately equal to that of the emitter pad EP. The thickness range of the anode connecting wiring 77 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0284] The semiconductor device 1A includes a plurality of cathode connection wirings 78 formed on portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of cathode connection wirings 78 have portions that extend in strip shapes along the corresponding cathode via electrodes 74 on the interlayer film 57, and are mechanically and electrically connected to the corresponding cathode via electrodes 74, respectively.

[0285] Similar to the emitter pad EP, each of the plurality of cathode connecting wirings 78 may have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the interlayer film 57 side.

[0286] The cathode connecting wiring 78 may have a thickness greater than that of the interlayer film 57. The thickness of the cathode connecting wiring 78 may be approximately equal to that of the emitter pad EP. The thickness range of the cathode connecting wiring 78 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0287] The semiconductor device 1A includes a plurality of connection wirings 79 formed on portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of connection wirings 79 are respectively interposed in regions between the plurality of polysilicon layers 50 adjacent to each other in the second direction Y on the interlayer film 57, and electrically connect the corresponding anode wirings 75 to the corresponding cathode wirings 76. The plurality of connection wirings 79 each extend in a strip shape in the second direction Y in a plan view.

[0288] One connection wiring 79 positioned at the outermost position on one side in the second direction Y electrically connects the outermost anode connection wiring 77 to the anode wiring 75. The other connection wiring 79 positioned at the outermost position on one side in the second direction Y electrically connects the outermost cathode connection wiring 78 to the anode wiring 75. This forms a first series circuit SC1 including a plurality of first diodes D1.

[0289] One connection wiring 79 positioned outermost on the other side in the second direction Y electrically connects the outermost cathode connection wiring 78 to the cathode wiring 76. The other connection wiring 79 positioned outermost on the other side in the second direction Y electrically connects the outermost anode connection wiring 77 to the cathode wiring 76. This forms a second series circuit SC2 including a plurality of second diodes D2.

[0290] The connection wiring 79 may have a thickness greater than that of the interlayer film 57. The thickness of the connection wiring 79 may be approximately equal to that of the emitter pad EP. The thickness range of the connection wiring 79 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0291] The configuration within the multiple pad regions 11 will be described below. Fig. 14 is an enlarged plan view showing the configuration within the pad region 11 together with the pad capacitor structure 84 according to the first layout example and the pad opening 91 according to the first layout example. Fig. 15 is an enlarged plan view showing a main part of the pad region 11. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 15. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 15.

[0292] The semiconductor device 1A includes a plurality of p-type pad well regions 80 formed in the surface layer portion of the first main surface 3 in the plurality of pad regions 11. The pad well regions 80 have a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, and convert the conductivity type of the drift region 12 from n-type to p-type.

[0293] The pad well region 80 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the pad well region 80 may be lower than the p-type impurity concentration of the base region 15. The p-type impurity concentration of the pad well region 80 is lower than the p-type impurity concentration of the contact region 41.

[0294] The p-type impurity concentration of the pad well region 80 may be approximately equal to the p-type impurity concentration of the peripheral well region 44. Of course, the p-type impurity concentration of the pad well region 80 may be higher than the p-type impurity concentration of the peripheral well region 44, or may be lower than the p-type impurity concentration of the peripheral well region 44.

[0295] The p-type impurity concentration of the pad well region 80 may be approximately equal to the p-type impurity concentration of the street well region 45. Of course, the p-type impurity concentration of the pad well region 80 may be higher than the p-type impurity concentration of the street well region 45, or may be lower than the p-type impurity concentration of the street well region 45.

[0296] An emitter potential is applied to the plurality of pad well regions 80. The plurality of pad well regions 80 are formed over the entire area of ​​the corresponding pad region 11. In this embodiment, the plurality of pad well regions 80 are connected to the peripheral well region 44 and the plurality of street well regions 45, and are formed integrally with the plurality of street well regions 45 and the peripheral well region 44.

[0297] That is, the plurality of pad well regions 80 are electrically connected to the plurality of base regions 15 via the plurality of street well regions 45 and the peripheral well region 44. In this embodiment, the plurality of pad well regions 80 have a width in the first direction X that is greater than the width of the plurality of street well regions 45.

[0298] The pad well regions 80 are formed deeper than the base regions 15. Specifically, the pad well regions 80 are formed deeper than the gate structures 20, the gate connection structures 25, the emitter structures 30, and the emitter connection structures 35.

[0299] The plurality of pad well regions 80 may have a depth approximately equal to the depth of the plurality of well regions 43. Of course, the depth of the plurality of pad well regions 80 may be greater than the depth of the plurality of well regions 43 or may be less than the depth of the plurality of well regions 43.

[0300] The depth of the multiple pad well regions 80 may be approximately equal to the depth of the periphery well region 44. Of course, the depth of the multiple pad well regions 80 may be greater than the depth of the periphery well region 44 or may be less than the depth of the periphery well region 44.

[0301] The depth of the plurality of pad well regions 80 may be approximately equal to the depth of the plurality of street well regions 45. Of course, the depth of the plurality of pad well regions 80 may be greater than the depth of the plurality of street well regions 45 or may be less than the depth of the plurality of street well regions 45.

[0302] The semiconductor device 1A includes a plurality of pad capacitor structures 84 formed in the plurality of pad regions 11 (see also FIG. 3). In this embodiment, the plurality of pad capacitor structures 84 include a monitor capacitor structure CM formed in the monitor pad region 11M, an anode capacitor structure CA formed in the anode pad region 11A, and a cathode capacitor structure CC formed in the cathode pad region 11C.

[0303] A monitor potential is applied to the monitor capacitor structure CM, an anode potential is applied to the anode capacitor structure CA, and a cathode potential is applied to the cathode capacitor structure CC. The pad capacitor structures 84 have the same configuration. The configuration of the anode capacitor structure CA will be described below as an example of the pad capacitor structure 84.

[0304] The configuration of the monitor capacitor structure CM can be obtained by replacing "anode capacitor structure CA" with "monitor capacitor structure CM" and "anode pad area 11A" with "monitor pad area 11M" in the following description.

[0305] The configuration of the cathode capacitor structure CC can be obtained by replacing "anode capacitor structure CA" with "cathode capacitor structure CC" and "anode pad area 11A" with "cathode pad area 11C" in the following description.

[0306] The anode capacitor structure CA includes a plurality of trench electrode type capacitor structures 85 formed on the first main surface 3 and forming capacitive coupling with the chip 2. The number of the capacitor structures 85 is less than the number of the gate structures 20.

[0307] The total area (total length) of the plurality of capacitor structures 85 is less than the total area (total length) of the plurality of gate structures 20. The number of capacitor structures 85 is less than the number of emitter structures 30. The total area (total length) of the plurality of capacitor structures 85 is less than the total area (total length) of the plurality of emitter structures 30.

[0308] The plurality of capacitor structures 85 extend in a strip shape in the first direction X in the anode pad region 11A and are arranged at intervals in the second direction Y. That is, the plurality of capacitor structures 85 are arranged in stripes extending in the first direction X. The extension direction of the plurality of capacitor structures 85 coincides with the extension direction of the plurality of gate structures 20. The extension direction of the plurality of capacitor structures 85 coincides with the extension direction of the plurality of emitter structures 30.

[0309] The plurality of capacitor structures 85 may each have a width that is less than the width of the plurality of street regions 9. The width of the capacitor structure 85 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the capacitor structure 85.

[0310] The width of the capacitor structure 85 may be approximately equal to the width of the gate structure 20. Of course, the width of the capacitor structure 85 may be greater than or less than the width of the gate structure 20. The width of the capacitor structure 85 may be approximately equal to the width of the gate connection structure 25. Of course, the width of the capacitor structure 85 may be greater than or less than the width of the gate connection structure 25.

[0311] The width of the capacitor structure 85 may be approximately equal to the width of the emitter structure 30. Of course, the width of the emitter structure 30 may be greater than or smaller than the width of the emitter structure 30. The width of the capacitor structure 85 may be approximately equal to the width of the emitter connection structure 35. Of course, the width of the capacitor structure 85 may be greater than or smaller than the width of the emitter connection structure 35.

[0312] The width of the capacitor structure 85 may be 0.5 μm or more and 5 μm or less. The width of the capacitor structure 85 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the capacitor structure 85 is preferably 1 μm or more and 2.5 μm or less.

[0313] The second trench pitch between the centers of the capacitor structures 85 may be approximately equal to the first trench pitch between the centers of the gate structures 20 and the emitter structures 30. Of course, the second trench pitch may be larger or smaller than the first trench pitch.

[0314] The second trench pitch may be 1 μm or more and 5 μm or less. The second trench pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second trench pitch is preferably 1.5 μm or more and 3.5 μm or less.

[0315] The plurality of capacitor structures 85 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3. Specifically, the plurality of capacitor structures 85 are formed on the first main surface 3 so as to be positioned within the pad well region 80, and are capacitively coupled with the pad well region 80.

[0316] More specifically, the plurality of capacitor structures 85 are formed at intervals from the bottom of the pad well region 80 toward the first main surface 3, and face the drift region 12 across a part of the pad well region 80 in the thickness direction. In other words, the plurality of capacitor structures 85 form capacitive coupling with the pad well region 80 throughout the entire depth direction.

[0317] The plurality of capacitor structures 85 may each have a bottom wall located on the bottom side of the pad well region 80 relative to the depth position of the intermediate portion of the pad well region 80. Of course, the bottom walls of the plurality of capacitor structures 85 may be located on the first main surface 3 side relative to the depth position of the intermediate portion of the pad well region 80. Furthermore, the plurality of capacitor structures 85 may penetrate the pad well region 80 to reach the drift region 12.

[0318] The plurality of capacitor structures 85 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of capacitor structures 85 may be formed substantially perpendicular to the first main surface 3. The bottom walls of the plurality of capacitor structures 85 may be formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of capacitor structures 85 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of capacitor structures 85 may be formed in a curved shape.

[0319] The plurality of capacitor structures 85 may have a depth approximately equal to the depth of the plurality of gate structures 20. Of course, the depth of the capacitor structures 85 may be greater than or less than the depth of the gate structures 20.

[0320] The depth of the capacitor structure 85 may be approximately equal to the depth of the gate connection structure 25. Of course, the depth of the capacitor structure 85 may be greater than the depth of the gate connection structure 25 or may be less than the depth of the gate connection structure 25.

[0321] The depth of the capacitor structure 85 may be approximately equal to the depth of the emitter structure 30. Of course, the depth of the emitter structure 30 may be greater than the depth of the emitter structure 30 or may be less than the depth of the emitter structure 30.

[0322] The depth of the capacitor structure 85 may be approximately equal to the depth of the emitter connection structure 35. Of course, the depth of the capacitor structure 85 may be greater than the depth of the emitter connection structure 35 or may be less than the depth of the emitter connection structure 35.

[0323] The depth of the capacitor structure 85 may be 0.5 μm or more and 10 μm or less. The depth of the capacitor structure 85 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the capacitor structure 85 is preferably 4 μm or more and 8 μm or less.

[0324] Each of the plurality of capacitor structures 85 includes a capacitor trench 86, a capacitor insulating film 87 (dielectric film), and a capacitor buried electrode 88. The capacitor trench 86 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the capacitor structure 85.

[0325] The capacitor insulating film 87 covers the wall surface of the capacitor trench 86. The capacitor insulating film 87 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0326] The capacitor insulating film 87 preferably contains the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the capacitor insulating film 87 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the capacitor insulating film 87 contains a silicon oxide film made of an oxide of the chip 2.

[0327] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the gate insulating film 22. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the gate insulating film 22 or may be smaller than the thickness of the gate insulating film 22.

[0328] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the gate connecting insulating film 27. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the gate connecting insulating film 27 or may be smaller than the thickness of the gate connecting insulating film 27.

[0329] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the emitter insulating film 32. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the emitter insulating film 32 or may be smaller than the thickness of the emitter insulating film 32.

[0330] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the emitter connection insulating film 37. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the emitter connection insulating film 37 or may be smaller than the thickness of the emitter connection insulating film 37.

[0331] The thickness of the capacitor insulating film 87 may be 10 nm or more and 200 nm or less. The thickness of the capacitor insulating film 87 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the capacitor insulating film 87 is preferably 100 nm or more and 150 nm or less.

[0332] The capacitor buried electrode 88 is buried in the capacitor trench 86 with the capacitor insulating film 87 interposed therebetween, and forms a capacitive coupling with the chip 2. Specifically, the capacitor buried electrode 88 faces the pad well region 80 with the capacitor insulating film 87 interposed therebetween, and forms a capacitive coupling with the pad well region 80.

[0333] In this embodiment, the capacitor buried electrode 88 forms capacitive coupling with the pad well region 80 on the sidewalls and bottom wall of the capacitor trench 86. The plurality of capacitor structures 85 form a plurality of first capacitances C1 with the chip 2 (pad well region 80). The plurality of first capacitances C1 are connected in parallel.

[0334] When the capacitor trench 86 penetrates the pad well region 80, the capacitor buried electrode 88 may have a portion that forms a capacitive coupling with the pad well region 80 via the capacitor insulating film 87, and a portion that forms a capacitive coupling with the drift region 12 via the capacitor insulating film 87.

[0335] The capacitor buried electrode 88 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The capacitor buried electrode 88 preferably includes the same type of conductor as the gate buried electrode 23 (emitter buried electrode 33).

[0336] The anode capacitor structure CA includes the aforementioned main surface insulating film 48 that covers the first main surface 3 of the anode pad region 11 A. The main surface insulating film 48 covers the pad well region 80 on the first main surface 3.

[0337] The main surface insulating film 48 is connected to the capacitor insulating film 87 in the anode pad region 11A. The thickness of the main surface insulating film 48 may be approximately equal to the thickness of the capacitor insulating film 87. Of course, the thickness of the main surface insulating film 48 may be greater than the thickness of the capacitor insulating film 87 or may be smaller than the thickness of the capacitor insulating film 87.

[0338] The anode capacitor structure CA includes one or more (one in this embodiment) capacitor electrode films 90 that cover the plurality of capacitor structures 85 on the main surface insulating film 48 in the anode pad region 11A. In this embodiment, the capacitor electrode film 90 collectively covers the plurality of capacitor structures 85 in the anode pad region 11A in the form of a film.

[0339] In this embodiment, the capacitor electrode film 90 is formed integrally with the plurality of capacitor buried electrodes 88, and is made of lead-out portions that are led out from the plurality of capacitor buried electrodes 88 onto the main surface insulating film 48. In other words, the capacitor electrode films 90 are each made of the same type of conductor as the capacitor buried electrodes 88 (either one or both of p-type conductive polysilicon and n-type conductive polysilicon).

[0340] Of course, the capacitor electrode film 90 may be made of a metal film. In this case, the capacitor electrode film 90 may be mechanically and electrically connected to a plurality of capacitor structures 85 (capacitor buried electrodes 88) on the main surface insulating film 48.

[0341] The capacitor electrode film 90 faces the first main surface 3 via the main surface insulating film 48 serving as a main surface dielectric film, and forms a capacitive coupling with the chip 2. Specifically, the capacitor electrode film 90 faces the pad well region 80 via the main surface insulating film 48, and forms a capacitive coupling with the pad well region 80.

[0342] The capacitor electrode film 90 forms a plurality of second capacitances C2 together with the chip 2 (pad well region 80) in the regions between the plurality of capacitor structures 85. The plurality of second capacitances C2 are connected in parallel to each other. The plurality of second capacitances C2 are connected in parallel to the plurality of first capacitances C1.

[0343] In this embodiment, the capacitor electrode film 90 is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The capacitor electrode film 90 may also be formed in a circular shape in plan view.

[0344] The capacitor electrode film 90 has a thickness greater than the thickness of the main surface insulating film 48. The thickness of the capacitor electrode film 90 is preferably less than the depth (thickness) of the pad well region 80.

[0345] The thickness of the capacitor electrode film 90 is preferably less than the depth of the capacitor structure 85. The thickness of the capacitor electrode film 90 is preferably less than the depth of the gate structure 20 (emitter structure 30). The thickness of the capacitor electrode film 90 is preferably less than the depth of the gate connection structure 25 (emitter connection structure 35).

[0346] The thickness of the capacitor electrode film 90 may be approximately equal to the thickness of the polysilicon layer 50. Of course, the thickness of the capacitor electrode film 90 may be greater than the thickness of the polysilicon layer 50 or may be smaller than the thickness of the polysilicon layer 50.

[0347] The thickness of the capacitor electrode film 90 may be approximately equal to the thickness of the emitter wiring 55. Of course, the thickness of the capacitor electrode film 90 may be greater than the thickness of the emitter wiring 55 or may be smaller than the thickness of the emitter wiring 55.

[0348] The thickness of the capacitor electrode film 90 may be approximately equal to the thickness of the gate wiring 56. Of course, the thickness of the capacitor electrode film 90 may be greater than the thickness of the gate wiring 56 or may be smaller than the thickness of the gate wiring 56.

[0349] The thickness of the capacitor electrode film 90 may be 0.1 μm or more and 2 μm or less. The thickness of the capacitor electrode film 90 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the capacitor electrode film 90 is preferably 0.25 μm or more and 1.25 μm or less.

[0350] The anode capacitor structure CA includes the aforementioned interlayer film 57 that covers the capacitor electrode film 90 in the anode pad region 11A. The interlayer film 57 covers the pad well region 80 with the main surface insulating film 48 and the capacitor electrode film 90 sandwiched between them, and covers the plurality of capacitor structures 85 with the capacitor electrode film 90 sandwiched between them. The thickness of the interlayer film 57 is preferably greater than the thickness of the capacitor electrode film 90. Of course, the thickness of the interlayer film 57 may be smaller than the thickness of the capacitor electrode film 90.

[0351] The anode capacitor structure CA includes one or more (one in this embodiment) pad openings 91 formed in the interlayer film 57 in the anode pad region 11A. The pad openings 91 are formed around the plurality of capacitor structures 85 in plan view, and extend in a strip shape along the periphery of the capacitor electrode film 90.

[0352] In this embodiment, the pad opening 91 is formed in a ring shape extending along the periphery of the capacitor electrode film 90 in a plan view, and surrounds the plurality of capacitor structures 85. The pad opening 91 penetrates the interlayer film 57 and exposes the capacitor electrode film 90. In this embodiment, the pad opening 91 is dug further downward from the electrode surface of the capacitor electrode film 90 toward the first main surface 3, and has a bottom wall located within the capacitor electrode film 90.

[0353] The bottom wall of the pad opening 91 is preferably formed at a distance from the thickness position of the intermediate portion of the capacitor electrode film 90 toward the electrode surface of the capacitor electrode film 90. Of course, the bottom wall of the pad opening 91 may be located on the chip 2 side relative to the thickness position of the intermediate portion of the capacitor electrode film 90. The pad opening 91 may be formed in a tapered shape toward the bottom wall. Of course, the pad opening 91 may be formed approximately perpendicular to the first main surface 3.

[0354] The anode capacitor structure CA includes a pad via electrode 92 embedded in a pad opening 91 in the anode pad region 11A. The pad via electrode 92 has portions that contact the interlayer film 57 and the capacitor electrode film 90. The pad via electrode 92 is mechanically and electrically connected to the capacitor electrode film 90 within the pad opening 91, and is electrically connected to a plurality of capacitor embedded electrodes 88 via the capacitor electrode film 90.

[0355] Similar to the first emitter via electrode 59, the pad via electrode 92 may have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the wall surface side of the pad opening 91. The first electrode 60 is formed in the form of a film on the wall surface of the pad opening 91, and is mechanically and electrically connected to the capacitor electrode film 90 within the pad opening 91. The second electrode 61 is embedded in the pad opening 91 with the first electrode 60 sandwiched therebetween, and is electrically connected to the capacitor electrode film 90 via the first electrode 60.

[0356] The semiconductor device 1A does not have a pad capacitor structure 84 (a capacitor structure 85, a capacitor electrode film 90, a pad opening 91, and a pad via electrode 92) in the gate pad region 11G because the capacitance value between the gate pad region 11G and the chip 2 is guaranteed by the multiple gate structures 20 arranged in the multiple active regions 6.

[0357] 2 again, the semiconductor device 1A includes a plurality of pad electrodes 95 arranged in the plurality of pad regions 11. The pad electrodes 95 may also be referred to as "pads," "terminal electrodes," "external terminals," etc.

[0358] The multiple pad electrodes 95 include a gate pad GP arranged in the gate pad region 11G, a monitor pad MP arranged in the monitor pad region 11M, an anode pad AP arranged in the anode pad region 11A, and a cathode pad CaP arranged in the cathode pad region 11C.

[0359] The gate pad GP is a terminal to which a gate potential is applied from the outside. The gate pad GP may also be referred to as a "gate pad electrode," a "gate terminal electrode," a "gate external terminal," or the like. The gate pad GP is disposed on a portion of the interlayer film 57 that covers the gate pad region 11G, and is connected to multiple gate fingers 70. As a result, the gate potential applied to the gate pad GP is applied to multiple gate structures 20 via the multiple gate wirings 56 and the multiple gate fingers 70.

[0360] In this embodiment, the gate pad GP faces the pad well region 80 across the main surface insulating film 48 and the interlayer film 57. In this embodiment, the gate pad GP is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view. The gate pad GP may also be formed in a circular shape in plan view.

[0361] The gate pad GP may have a thickness greater than that of the interlayer film 57. The thickness of the gate pad GP is preferably greater than that of the capacitor electrode film 90. The thickness of the gate pad GP may be 0.5 μm or more and 10 μm or less.

[0362] The thickness of the gate pad GP may have a value belonging to at least one of the ranges of 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm.

[0363] Like the emitter pad EP, the gate pad GP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is connected to the first electrode films 65 of the multiple gate fingers 70 on the interlayer film 57.

[0364] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 is connected to the second electrode films 66 of the multiple gate fingers 70 on the first electrode film 65.

[0365] The monitor pad MP is a terminal to which a monitor potential is applied from the outside. The monitor pad MP may also be referred to as a "monitor pad electrode," a "monitor terminal electrode," a "monitor external terminal," etc. The monitor pad MP is disposed on a portion of the interlayer film 57 that covers the monitor pad region 11M.

[0366] In this embodiment, the monitor pad MP has a plane area smaller than that of the capacitor electrode film 90 of the monitor capacitor structure CM, and is disposed on the inner part of the capacitor electrode film 90 at a distance from the periphery of the capacitor electrode film 90. In other words, the monitor pad MP has a periphery (electrode sidewall) located inward from the periphery of the capacitor electrode film 90.

[0367] Of course, the monitor pad MP may have a planar area larger than the planar area of ​​the capacitor electrode film 90. In this case, the periphery (electrode sidewall) of the monitor pad MP may be positioned outward from the periphery of the capacitor electrode film 90 and may surround the capacitor electrode film 90.

[0368] In this embodiment, the monitor pad MP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The monitor pad MP may also be formed in a circular shape in plan view.

[0369] The monitor pad MP is mechanically and electrically connected to the pad via electrode 92 on the interlayer film 57. As a result, the monitor pad MP is electrically connected to the plurality of capacitor structures 85 (capacitor buried electrodes 88) via the capacitor electrode film 90. In other words, the monitor pad MP applies a monitor potential to the plurality of capacitor structures 85 and the capacitor electrode film 90 of the monitor capacitor structure CM.

[0370] The monitor pad MP is disposed on the first side surface 5A side of the monitor electrode 67, and has a lead portion that is led out toward the monitor electrode 67. The lead portion extends in a strip shape in the second direction Y, and is mechanically and electrically connected to the monitor electrode 67.

[0371] As a result, the monitor potential applied to the monitor pad MP is applied to the plurality of emitter structures 30, the plurality of emitter connection structures 35, the plurality of emitter regions 40 and the plurality of contact regions 41 via the monitor electrode 67, the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63.

[0372] The monitor pad MP may have a thickness greater than that of the interlayer film 57. The thickness of the monitor pad MP is preferably greater than that of the capacitor electrode film 90. The thickness range of the monitor pad MP is the same as that of the gate pad GP (0.5 μm or more and 10 μm or less).

[0373] Like the emitter pad EP, the monitor pad MP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is mechanically and electrically connected to the pad via electrode 92 on the interlayer film 57.

[0374] Specifically, the first electrode film 65 is connected to the first electrode 60 of the pad via electrode 92. Of course, the first electrode film 65 may cover the first electrode 60 of the pad via electrode 92. The first electrode film 65 is connected to the first electrode film 65 of the monitor electrode 67 on the interlayer film 57.

[0375] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 and the pad via electrode 92 in a film-like manner. The second electrode film 66 is mechanically and electrically connected to the pad via electrode 92. The second electrode film 66 is connected to the second electrode film 66 of the monitor electrode 67 on the first electrode film 65.

[0376] The anode pad AP is a terminal to which an anode potential is applied from the outside. The anode pad AP may also be referred to as an "anode pad electrode," an "anode terminal electrode," an "anode external terminal," or the like. The anode pad AP is disposed on a portion of the interlayer film 57 that covers the anode pad region 11A, and is connected to the anode wiring 75. As a result, the anode potential applied to the anode pad AP is applied to the temperature-sensitive diode structure D via the anode wiring 75.

[0377] In this embodiment, the anode pad AP has a plane area smaller than that of the capacitor electrode film 90 of the anode capacitor structure CA, and is disposed on the inner part of the capacitor electrode film 90 at a distance from the periphery of the capacitor electrode film 90. In other words, the anode pad AP has a periphery (electrode sidewall) located inward from the periphery of the capacitor electrode film 90.

[0378] Of course, the anode pad AP may have a planar area larger than the planar area of ​​the capacitor electrode film 90. In this case, the periphery (electrode sidewall) of the anode pad AP may be positioned outward from the periphery of the capacitor electrode film 90 and may surround the capacitor electrode film 90.

[0379] In this embodiment, the anode pad AP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The anode pad AP may also be formed in a circular shape in plan view.

[0380] The anode pad AP is mechanically and electrically connected to the pad via electrode 92 on the interlayer film 57. As a result, the anode pad AP is electrically connected to the plurality of capacitor structures 85 (capacitor buried electrodes 88) via the capacitor electrode film 90. In other words, the anode pad AP applies an anode potential to the plurality of capacitor structures 85 and the capacitor electrode film 90 of the anode capacitor structure CA.

[0381] The anode pad AP may have a thickness greater than that of the interlayer film 57. The thickness of the anode pad AP is preferably greater than that of the capacitor electrode film 90. The thickness range of the anode pad AP is the same as the thickness range of the gate pad GP (0.5 μm or more and 10 μm or less).

[0382] Similar to the emitter pad EP, the anode pad AP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is mechanically and electrically connected to the pad via electrode 92 on the interlayer film 57.

[0383] Specifically, the first electrode film 65 is connected to the first electrode 60 of the pad via electrode 92. Of course, the first electrode film 65 may cover the first electrode 60 of the pad via electrode 92. The first electrode film 65 is connected to the first electrode film 65 of the anode wiring 75 on the interlayer film 57.

[0384] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 and the pad via electrode 92 in a film-like manner. The second electrode film 66 is mechanically and electrically connected to the pad via electrode 92. The second electrode film 66 is connected to the second electrode film 66 of the anode wiring 75 on the first electrode film 65.

[0385] The cathode pad CaP is a terminal to which a cathode potential is applied from the outside. The cathode pad CaP may be called a "cathode pad electrode," a "cathode terminal electrode," a "cathode external terminal," or the like.

[0386] The cathode pad CaP is disposed on a portion of the interlayer film 57 that covers the cathode pad region 11C, and is connected to the cathode wiring 76. As a result, the cathode potential applied to the cathode pad CaP is applied to the temperature-sensitive diode structure D via the cathode wiring 76.

[0387] The cathode pad CaP is disposed on a portion of the interlayer film 57 that covers the cathode pad region 11C. In this embodiment, the cathode pad CaP has a planar area smaller than the planar area of ​​the capacitor electrode film 90 of the cathode capacitor structure CC, and is disposed on an inner portion of the capacitor electrode film 90 at a distance from the periphery of the capacitor electrode film 90. In other words, the cathode pad CaP has a periphery (electrode sidewall) that is positioned inward from the periphery of the capacitor electrode film 90.

[0388] Of course, the cathode pad CaP may have a planar area larger than the planar area of ​​the capacitor electrode film 90. In this case, the periphery (electrode sidewall) of the cathode pad CaP may be positioned outward from the periphery of the capacitor electrode film 90 and may surround the capacitor electrode film 90.

[0389] In this embodiment, the cathode pad CaP is formed in a polygonal shape (a quadrangular shape in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The cathode pad CaP may also be formed in a circular shape in plan view.

[0390] The cathode pad CaP is mechanically and electrically connected to the pad via electrode 92 on the interlayer film 57. As a result, the cathode pad CaP is electrically connected to the plurality of capacitor structures 85 (capacitor buried electrodes 88) via the capacitor electrode film 90. In other words, the cathode pad CaP applies a cathode potential to the plurality of capacitor structures 85 and the capacitor electrode film 90 of the cathode capacitor structure CC.

[0391] The cathode pad CaP may have a thickness greater than that of the interlayer film 57. The thickness of the cathode pad CaP is preferably greater than that of the capacitor electrode film 90. The thickness range of the cathode pad CaP is the same as that of the gate pad GP (not less than 0.5 μm and not more than 10 μm).

[0392] Like the emitter pad EP, the cathode pad CaP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is mechanically and electrically connected to the pad via electrode 92 on the interlayer film 57.

[0393] Specifically, the first electrode film 65 is connected to the first electrode 60 of the pad via electrode 92. Of course, the first electrode film 65 may cover the first electrode 60 of the pad via electrode 92. The first electrode film 65 is connected to the first electrode film 65 of the cathode wiring 76 on the interlayer film 57.

[0394] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 and the pad via electrode 92 in a film-like manner. The second electrode film 66 is mechanically and electrically connected to the pad via electrode 92. The second electrode film 66 is connected to the second electrode film 66 of the cathode wiring 76 on the first electrode film 65.

[0395] The semiconductor device 1A includes a collector pad CoP covering the second main surface 4. The collector pad CoP is a terminal to which a collector potential is applied from the outside. The collector pad CoP may also be referred to as a "collector pad electrode," a "collector terminal electrode," an "external collector terminal," or the like. The collector pad CoP is formed in the form of a film along the second main surface 4 and is electrically connected to the collector region 14.

[0396] The collector pad CoP covers, from the second main surface 4 side, the multiple active regions 6, the monitor region 7, the outer periphery region 8, the multiple street regions 9, the multiple temperature measurement regions 10, and the multiple pad regions 11. The collector pad CoP may cover the entire second main surface 4. Of course, the collector pad CoP may be formed at a distance inward from the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D), leaving the periphery of the second main surface 4 exposed (collector region 14).

[0397] A breakdown voltage that can be applied between the emitter pad EP and the collector pad CoP (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0398] Other layout examples of the pad capacitor structure 84 are shown below. Figures 18A to 18R are plan views showing the pad capacitor structures 84 according to second to nineteenth layout examples. Each of the multiple pad regions 11 may include at least one of the pad capacitor structures 84 according to the second to nineteenth layout examples, instead of or in addition to the pad capacitor structure 84 according to the first layout example.

[0399] That is, the monitor pad region 11M may include at least one of the pad capacitor structures 84 (monitor capacitor structures CM) according to the first to nineteenth layout examples. The anode pad region 11A may include at least one of the pad capacitor structures 84 (anode capacitor structures CA) according to the first to nineteenth layout examples.

[0400] The cathode pad region 11C may include at least one of the pad capacitor structures 84 (cathode capacitor structures CC) according to the first to nineteenth layout examples. The monitor pad region 11M, the anode pad region 11A, and the cathode pad region 11C do not necessarily have to have pad capacitor structures 84 according to the same layout example, and may have pad capacitor structures 84 according to different layout examples.

[0401] 18A (second layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe shape in the first direction X and one second capacitor structure 85B extending in the second direction Y.

[0402] Each of the multiple first capacitor structures 85A has one end on one side (the third side surface 5C side) in the longitudinal direction (the first direction X) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (the first direction X).

[0403] The second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to one end of each of the plurality of first capacitor structures 85A. That is, the plurality of capacitor structures 85 form a single comb-tooth-shaped capacitor structure 85 in plan view. Of course, the second capacitor structure 85B may also be connected to the other end of each of the plurality of first capacitor structures 85A.

[0404] 18B (third layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in a first direction X and a plurality of second capacitor structures 85B extending in a second direction Y.

[0405] Each of the multiple first capacitor structures 85A has one end on one side (the third side surface 5C side) in the longitudinal direction (the first direction X) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (the first direction X).

[0406] The plurality of second capacitor structures 85B are arranged on both sides of the plurality of first capacitor structures 85A in the first direction X. One of the second capacitor structures 85B extends in a strip shape in the second direction Y and is connected to one end of the first capacitor structure 85A.

[0407] The other second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to the other end of the first capacitor structure 85A. In other words, the multiple capacitor structures 85 form a single ladder-shaped capacitor structure 85 in plan view.

[0408] 18C (fourth layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in a first direction X and a plurality of second capacitor structures 85B extending in a second direction Y.

[0409] Each of the multiple first capacitor structures 85A has one end on one side (the third side surface 5C side) in the longitudinal direction (the first direction X) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (the first direction X).

[0410] The plurality of second capacitor structures 85B are respectively arranged on both sides of the plurality of first capacitor structures 85A in the first direction X. One of the plurality of second capacitor structures 85B is formed at intervals in the second direction Y and is respectively connected to one end of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the second direction Y.

[0411] The other plurality of second capacitor structures 85B are formed at intervals in the second direction Y so as to face one of the plurality of second capacitor structures 85B in a one-to-one correspondence in the first direction X, and are respectively connected to the other ends of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the second direction Y. In other words, the plurality of capacitor structures 85 form a ring-shaped (quadratic ring-shaped) plurality of capacitor structures 85 extending in the first direction X in a plan view.

[0412] 18D (fifth layout example), similar to the first layout example, pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in a first direction X and a plurality of second capacitor structures 85B extending in a second direction Y.

[0413] Each of the multiple first capacitor structures 85A has one end on one side (the third side surface 5C side) in the longitudinal direction (the first direction X) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (the first direction X).

[0414] The plurality of second capacitor structures 85B are respectively arranged on both sides of the plurality of first capacitor structures 85A in the first direction X. One of the plurality of second capacitor structures 85B is formed at intervals in the second direction Y and is respectively connected to one end of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the second direction Y.

[0415] The other plurality of second capacitor structures 85B are arranged to be shifted in the second direction Y with respect to one of the plurality of second capacitor structures 85B so as to face the one of the two second capacitor structures 85B in the first direction X.

[0416] The other plurality of second capacitor structures 85B are formed at intervals in the second direction Y and are respectively connected to the other ends of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the second direction Y. In other words, the plurality of capacitor structures 85 form a single zigzag-shaped capacitor structure 85 having a portion extending in the first direction X and a portion extending in the second direction Y in plan view.

[0417] 18E (sixth layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. The plurality of capacitor structures 85 have a layout in which the extension direction of the capacitor structures 85 in the first layout example is changed from the first direction X to the second direction Y.

[0418] That is, the plurality of capacitor structures 85 extend in a stripe pattern in the second direction Y. In this embodiment, the extension direction of the plurality of capacitor structures 85 intersects (specifically, is perpendicular to) the extension direction of the plurality of gate structures 20 (the plurality of emitter structures 30).

[0419] 18F (seventh layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the second direction Y and one second capacitor structure 85B extending in the first direction X.

[0420] Each of the multiple first capacitor structures 85A has one end on one side (first side surface 5A side) in the longitudinal direction (second direction Y) and the other end on the other side (second side surface 5B side) in the longitudinal direction (second direction Y).

[0421] The second capacitor structure 85B extends in a strip shape in the first direction X and is connected to one end of the plurality of first capacitor structures 85A. That is, the plurality of capacitor structures 85A form a single comb-tooth-shaped capacitor structure 85 in plan view. Of course, the second capacitor structure 85B may be connected to the other end of the plurality of second capacitor structures 85B.

[0422] 18G (eighth layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in stripes in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X.

[0423] Each of the multiple first capacitor structures 85A has one end on one side (first side surface 5A side) in the longitudinal direction (second direction Y) and the other end on the other side (second side surface 5B side) in the longitudinal direction (second direction Y).

[0424] The second capacitor structures 85B are arranged on both sides of the first capacitor structures 85A in the second direction Y. One of the second capacitor structures 85B extends in a strip shape in the second direction Y and is connected to one end of the first capacitor structures 85A.

[0425] The other second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to the other ends of the plurality of first capacitor structures 85A. In other words, the plurality of capacitor structures 85 form a single ladder-shaped capacitor structure 85 in plan view.

[0426] 18H (ninth layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in stripes in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X.

[0427] Each of the multiple first capacitor structures 85A has one end on one side (first side surface 5A side) in the longitudinal direction (second direction Y) and the other end on the other side (second side surface 5B side) in the longitudinal direction (second direction Y).

[0428] The plurality of second capacitor structures 85B are respectively arranged on both sides of the plurality of first capacitor structures 85A in the second direction Y. One of the plurality of second capacitor structures 85B is formed at intervals in the first direction X and is respectively connected to one end of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X.

[0429] The other plurality of second capacitor structures 85B are formed at intervals in the first direction X so as to face one of the plurality of first capacitor structures 85A in a one-to-one correspondence in the second direction Y, and are respectively connected to the other ends of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X. In other words, the plurality of capacitor structures 85 form a ring-shaped (quadratic ring-shaped) plurality of capacitor structures 85 extending in the second direction Y in a plan view.

[0430] 18I (10th layout example), similar to the first layout example, the pad capacitor structure 84 includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in stripes in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X.

[0431] Each of the multiple first capacitor structures 85A has one end on one side (first side surface 5A side) in the longitudinal direction (second direction Y) and the other end on the other side (second side surface 5B side) in the longitudinal direction (second direction Y).

[0432] The plurality of second capacitor structures 85B are respectively arranged on both sides of the plurality of first capacitor structures 85A in the second direction Y. One of the plurality of second capacitor structures 85B is formed at intervals in the first direction X and is respectively connected to one end of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X.

[0433] The other plurality of second capacitor structures 85B are arranged offset in the first direction X relative to the plurality of second capacitor structures 85B so as to face the two second capacitor structures 85B in the second direction Y.

[0434] The other plurality of second capacitor structures 85B are formed at intervals in the first direction X and are respectively connected to the other ends of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X. In other words, the plurality of capacitor structures 85 form one zigzag-shaped capacitor structure 85 having a portion extending in the first direction X and a portion extending in the second direction Y in plan view.

[0435] 18J (eleventh layout example), similar to the first layout example, pad capacitor structure 84 includes a plurality of capacitor structures 85. The plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in a first direction X and a plurality of second capacitor structures 85B extending in a second direction Y.

[0436] The second capacitor structures 85B are each disposed in a region between the first capacitor structures 85A adjacent to each other in the second direction Y, and are arranged at intervals in the first direction X. The second capacitor structures 85B disposed on one side of one first capacitor structure 85A in the second direction Y face the second capacitor structures 85B disposed on the other side of one first capacitor structure 85A in the second direction Y, in a one-to-one correspondence.

[0437] The second capacitor structures 85B form a plurality of crosses with the first capacitor structures 85A, and define a plurality of mesa portions arranged in a matrix in the first direction X and the second direction Y. In other words, the capacitor structures 85 constitute one capacitor structure 85 that extends in a lattice (mesh) shape along the first direction X and the second direction Y in plan view.

[0438] 18K (twelfth layout example), similar to the first layout example, pad capacitor structure 84 includes a plurality of capacitor structures 85. The plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in a first direction X and a plurality of second capacitor structures 85B extending in a second direction Y.

[0439] The multiple second capacitor structures 85B are respectively arranged in regions between multiple first capacitor structures 85A adjacent to each other in the second direction Y, and are arranged at intervals in the first direction X. The multiple second capacitor structures 85B arranged on one side of one first capacitor structure 85A in the second direction Y face the regions between the multiple second capacitor structures 85B arranged on the other side of one first capacitor structure 85A in the second direction Y in a one-to-one correspondence.

[0440] The second capacitor structures 85B form a plurality of T-junctions with the first capacitor structures 85A, and define a plurality of mesa portions arranged in a staggered pattern in the first direction X and the second direction Y. In other words, the capacitor structures 85 constitute a single capacitor structure 85 that extends in a staggered pattern (mesh pattern) along the first direction X and the second direction Y in a plan view.

[0441] 18L (thirteenth layout example), pad capacitor structure 84 includes a plurality of capacitor structures 85 each formed in an annular shape in a plan view. The plurality of capacitor structures 85 are formed at intervals from the inner part of pad region 11 toward the periphery of pad region 11 so as to surround inner capacitor structures 85 in order.

[0442] In this embodiment, the plurality of capacitor structures 85 are formed in a polygonal ring shape (a square ring shape in this embodiment) in a plan view, and each have a plurality of portions extending in the first direction X and a plurality of portions extending in the second direction Y. The plurality of capacitor structures 85 may also be formed in a hexagonal ring shape, a circular ring shape, or the like.

[0443] 18M (fourteenth layout example), pad capacitor structure 84 includes a single capacitor structure 85 formed in a spiral shape in plan view. In this embodiment, capacitor structure 85 is formed in a polygonal spiral shape (a square spiral shape in this embodiment) and has multiple portions extending in a first direction X and multiple portions extending in a second direction Y. Capacitor structure 85 may also be formed in a hexagonal spiral shape, a circular spiral shape, or the like.

[0444] 18N (a fifteenth layout example), a pad capacitor structure 84 includes a plurality of capacitor structures 85 arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view. That is, the plurality of capacitor structures 85 may define a lattice-shaped (mesh-shaped) mesa portion having a plurality of cross paths on the first main surface 3.

[0445] The plurality of capacitor structures 85 are formed in a polygonal shape (quadrilateral in this embodiment) in plan view. The plurality of capacitor structures 85 may be formed in a hexagonal shape, a circular shape, or the like in plan view. Of course, the plurality of capacitor structures 85 may be formed in a strip shape (rectangular shape) extending in the first direction X or a strip shape (rectangular shape) extending in the second direction Y in plan view.

[0446] 18O (a sixteenth layout example), a pad capacitor structure 84 includes a plurality of capacitor structures 85 that are arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view. In other words, the plurality of capacitor structures 85 may define a lattice-shaped (mesh-like) mesa portion having a plurality of T-junctions on the first main surface 3.

[0447] The plurality of capacitor structures 85 are formed in a polygonal shape (quadrilateral in this embodiment) in plan view. The plurality of capacitor structures 85 may be formed in a hexagonal shape, a circular shape, or the like in plan view. Of course, the plurality of capacitor structures 85 may be formed in a strip shape (rectangular shape) extending in the first direction X or a strip shape (rectangular shape) extending in the second direction Y in plan view.

[0448] Referring to FIG. 18P (seventeenth layout example), a pad capacitor structure 84 includes a plurality of capacitor structures 85 arranged in a matrix at intervals in the first direction X and the second direction Y in plan view.

[0449] That is, the plurality of capacitor structures 85 may define a lattice-shaped (mesh-shaped) mesa portion having a plurality of crosses on the first main surface 3. The plurality of capacitor structures 85 may be formed in a polygonal ring shape (a square ring in this embodiment) in plan view. The plurality of capacitor structures 85 may also be formed in a hexagonal ring shape, a circular ring shape, or the like in plan view.

[0450] Referring to FIG. 18Q (an eighteenth layout example), a pad capacitor structure 84 includes a plurality of capacitor structures 85 arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view.

[0451] That is, the plurality of capacitor structures 85 may define a lattice-shaped (mesh-shaped) mesa portion having a plurality of T-junctions on the first main surface 3. The plurality of capacitor structures 85 are formed in a polygonal ring shape (a quadrangular ring in this embodiment) in plan view. The plurality of capacitor structures 85 may also be formed in a hexagonal ring shape, a circular ring shape, or the like in plan view.

[0452] 18R (a nineteenth layout example), pad capacitor structure 84 may include two or more layout regions 97. For example, the number of layout regions 97 may be ten or less. In this example, pad capacitor structure 84 includes four layout regions 97, for example.

[0453] The multiple layout regions 97 may be arranged in a line in the first direction X. The multiple layout regions 97 may be arranged in a line in the second direction Y. The multiple layout regions 97 may be arranged in a matrix along the first direction X and the second direction Y. The multiple layout regions 97 may have substantially the same planar area as each other, or may have different planar areas as each other.

[0454] The pad capacitor structure 84 includes a plurality of capacitor structures 85 formed in a plurality of layout regions 97 at intervals from one another. The plurality of capacitor structures 85 may have the same layout or different layouts. Each of the plurality of capacitor structures 85 may have one of the first to sixteenth layout examples.

[0455] Other layout examples of the pad opening 91 are shown below. Figures 19A to 19F are plan views showing the pad opening 91 according to second to seventh layout examples. In Figures 19A to 19F, the portion of the capacitor electrode film 90 exposed from the pad opening 91 is indicated by hatching.

[0456] The pad openings 91 according to the first to seventh layout examples can be combined with any one of the pad capacitor structures 84 according to the first to nineteenth layout examples. In addition, the pad openings 91 according to the first to seventh layout examples can be combined as appropriate.

[0457] That is, the monitor pad region 11M may have at least one of the pad openings 91 according to the first to seventh layout examples. The anode pad region 11A may have at least one of the pad openings 91 according to the first to seventh layout examples. The cathode pad region 11C may have at least one of the pad openings 91 according to the first to seventh layout examples.

[0458] The monitor pad region 11M, the anode pad region 11A, and the cathode pad region 11C do not necessarily have to have pad openings 91 according to the same layout example, and may have pad openings 91 according to different layout examples.

[0459] 19A (second layout example), the pad capacitor structure 84 has a planar area smaller than the planar area of ​​the capacitor electrode film 90 and includes a single pad opening 91 that exposes an inner portion of the capacitor electrode film 90 at a distance from the periphery of the capacitor electrode film 90. The pad opening 91 has a wall surface that extends along the periphery of the capacitor electrode film 90 in a plan view, and is formed in a region that overlaps with a plurality of capacitor structures 85.

[0460] The area ratio of the plane area of ​​the pad opening 91 to the plane area of ​​the capacitor electrode film 90 may be equal to or greater than 0.1 and less than 1. The area ratio may have a value belonging to at least one of the ranges of 0.1 to 0.25, 0.25 to 0.5, 0.5 to 0.75, and 0.75 to less than 1. The area ratio is preferably 0.5 or greater.

[0461] 19B (third layout example), the pad capacitor structure 84 includes a plurality of pad openings 91. The plurality of pad openings 91 each extend in a strip shape in the first direction X and are formed at intervals in the second direction Y. In other words, the plurality of pad openings 91 extend in a stripe shape in the first direction X.

[0462] The multiple pad openings 91 may have portions that overlap one or more capacitor structures 85 in the stacking direction. The multiple pad openings 91 may each be formed in a region that does not overlap the capacitor structure 85 in the stacking direction. When the pad capacitor structure 84 includes one or more capacitor structures 85 extending in the second direction Y, the multiple pad openings 91 may intersect (orthogonally intersect) the one or more capacitor structures 85.

[0463] 19C (fourth layout example), the pad capacitor structure 84 includes a plurality of pad openings 91. The plurality of pad openings 91 each extend in a strip shape in the second direction Y and are formed at intervals in the first direction X. In other words, the plurality of pad openings 91 extend in a stripe shape in the second direction Y.

[0464] The multiple pad openings 91 may have portions that overlap one or more capacitor structures 85 in the stacking direction. The multiple pad openings 91 may each be formed in a region that does not overlap the capacitor structure 85 in the stacking direction. When the pad capacitor structure 84 includes one or more capacitor structures 85 extending in the first direction X, the multiple pad openings 91 may intersect (orthogonal to) the one or more capacitor structures 85.

[0465] 19D (fifth layout example), pad capacitor structure 84 may include a single pad opening 91 formed in a grid pattern in a plan view. Pad opening 91 may intersect with a plurality of capacitor structures 85 in a plan view.

[0466] 19E (sixth layout example), the pad capacitor structure 84 may include a plurality of pad openings 91 arranged in a dot pattern in the first direction X and the second direction Y in a plan view. The plurality of pad openings 91 may be arranged in a matrix at intervals in the first direction X and the second direction Y so as to define a plurality of crossroads on the insulating surface of the interlayer film 57.

[0467] The multiple pad openings 91 may have portions that overlap one or multiple capacitor structures 85 in the stacking direction. The multiple pad openings 91 may each be formed in a region that does not overlap the capacitor structure 85 in the stacking direction. The multiple pad openings 91 may be formed in a polygonal shape, a circular shape, or the like in a plan view. In this embodiment, the multiple pad openings 91 are formed in a quadrangular shape.

[0468] 19F (seventh layout example), the pad capacitor structure 84 may include a plurality of pad openings 91 arranged in a dot pattern in the first direction X and the second direction Y in a plan view. The plurality of pad openings 91 may be arranged in a staggered pattern at intervals in the first direction X and the second direction Y so as to define a plurality of T-junctions on the insulating surface of the interlayer film 57.

[0469] The multiple pad openings 91 may have portions that overlap one or multiple capacitor structures 85 in the stacking direction. The multiple pad openings 91 may each be formed in a region that does not overlap the capacitor structure 85 in the stacking direction. The multiple pad openings 91 may be formed in a polygonal shape, a circular shape, or the like in a plan view. In this embodiment, the multiple pad openings 91 are formed in a quadrangular shape.

[0470] An example of an electrical test performed on the semiconductor device 1A is shown below. Fig. 20 is a plan view illustrating an electrical test on the gate pad GP side. Fig. 21 is a plan view illustrating an electrical test on the monitor pad MP side. Fig. 22 is a plan view illustrating an electrical test on the anode pad AP side. Fig. 23 is a plan view illustrating an electrical test on the cathode pad CaP side.

[0471] The electrical test is a human body model (HBM) ESD (Electro Static Discharge) tolerance measurement test for the semiconductor device 1A (plurality of pad electrodes 95). The HBM is a model that assumes that ESD occurs between a human body and the plurality of pad electrodes 95.

[0472] 20 , in a test on the gate pad GP side, a predetermined first test voltage V1 is applied between the emitter pad EP and the gate pad GP. Various values ​​are adopted for the first test voltage V1 depending on the specifications of the semiconductor device 1A. The first test voltage V1 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0473] When the first test voltage V1 is applied, a predetermined test current is generated in the emitter pad EP and the gate pad GP, and the ESD resistance between the emitter pad EP and the gate pad GP is measured. A relatively high capacitance value is ensured between the emitter pad EP and the gate pad GP by the multiple gate structures 20, so that a relatively high ESD resistance is achieved.

[0474] 21 , in a test on the monitor pad MP side, a predetermined second test voltage V2 is applied between the emitter pad EP and the monitor pad MP. The second test voltage V2 may be applied between the gate pad GP and the monitor pad MP. Various values ​​are adopted for the second test voltage V2 depending on the specifications of the semiconductor device 1A. The second test voltage V2 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0475] When the second test voltage V2 is applied, a predetermined test current is generated in the emitter pad EP and the monitor pad MP, and the ESD resistance between the emitter pad EP and the monitor pad MP is measured.

[0476] In the monitor region 7, the number of gate structures 20 formed is less than the number of gate structures 20 associated with the active regions 6. In other words, the capacitance value associated with the gate structures 20 in the monitor region 7 is lower than the capacitance value associated with the gate structures 20 in the active regions 6. Therefore, the ESD tolerance between the emitter pad EP and the monitor pad MP is less than the ESD tolerance between the emitter pad EP and the gate pad GP.

[0477] In this regard, in the semiconductor device 1A, a plurality of capacitor structures 85 are formed in the monitor pad region 11M, and the capacitance value between the emitter pad EP and the monitor pad MP is complemented by the plurality of capacitor structures 85. Furthermore, in the monitor pad region 11M, the capacitance value is further increased by the capacitor electrode film 90. This increases the ESD tolerance compared to when the pad capacitor structure 84 is not present in the monitor pad region 11M.

[0478] 22 , in a test on the anode pad AP side, a predetermined third test voltage V3 is applied between the emitter pad EP and the anode pad AP. The third test voltage V3 may be applied between the gate pad GP and the anode pad AP. Various values ​​are adopted for the third test voltage V3 depending on the specifications of the semiconductor device 1A. The third test voltage V3 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0479] When the third test voltage V3 is applied, a predetermined test current is generated in the emitter pad EP and the anode pad AP, and the ESD resistance between the emitter pad EP and the anode pad AP is measured. The gate structure 20 is not electrically interposed in the region between the emitter pad EP and the anode pad AP. Therefore, the ESD resistance between the emitter pad EP and the anode pad AP is less than the ESD resistance between the emitter pad EP and the gate pad GP.

[0480] In this regard, in the semiconductor device 1A, a plurality of capacitor structures 85 are formed in the anode pad region 11A, and the capacitance between the emitter pad EP and the anode pad AP is complemented by the plurality of capacitor structures 85. Furthermore, in the anode pad region 11A, the capacitance is further increased by the capacitor electrode film 90. This increases the ESD tolerance compared to when the pad capacitor structure 84 is not present in the anode pad region 11A.

[0481] 23 , in a test on the cathode pad CaP side, a predetermined fourth test voltage V4 is applied between the emitter pad EP and the cathode pad CaP. The fourth test voltage V4 may be applied between the gate pad GP and the cathode pad CaP. Various values ​​are adopted for the fourth test voltage V4 depending on the specifications of the semiconductor device 1A. The fourth test voltage V4 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0482] When the fourth test voltage V4 is applied, a predetermined test current is generated in the emitter pad EP and the cathode pad CaP, and the ESD resistance between the emitter pad EP and the cathode pad CaP is measured.

[0483] The gate structure 20 is not electrically interposed in the region between the emitter pad EP and the cathode pad CaP. Therefore, the ESD resistance between the emitter pad EP and the cathode pad CaP is less than the ESD resistance between the emitter pad EP and the gate pad GP.

[0484] In this regard, in the semiconductor device 1A, a plurality of capacitor structures 85 are formed on the cathode pad CaP, and the capacitance value between the emitter pad EP and the cathode pad CaP is complemented by the plurality of capacitor structures 85. Furthermore, the capacitance value of the cathode pad CaP is further increased by the capacitor electrode film 90. This increases the ESD resistance compared to when the pad capacitor structure 84 is not present on the cathode pad CaP.

[0485] As described above, the semiconductor device 1A may include the chip 2, the active region 6, the pad region 11, the insulated gate transistor structure T3, the trench electrode capacitor structure 85, and the pad electrode 95. The chip 2 may have a first main surface 3. The active region 6 may be provided on the first main surface 3.

[0486] The pad region 11 may be provided outside the active region 6 on the first main surface 3. The transistor structure T3 may be formed on the first main surface 3 of the active region 6. The capacitor structure 85 may be formed on the first main surface 3 of the pad region 11 and may form capacitive coupling with the chip 2. The pad electrode 95 may be disposed on the first main surface 3 of the pad region 11 and electrically connected to the capacitor structure 85.

[0487] This configuration provides the semiconductor device 1A with improved electrical characteristics. Specifically, in the semiconductor device 1A, the capacitance value below the pad electrode 95 is increased by the capacitor structure 85, resulting in improved ESD resistance.

[0488] The transistor structure T3 may include a trench electrode type gate structure 20 to which a gate potential is applied. In this case, the pad electrode 95 may apply a potential other than the gate potential to the capacitor structure 85. This configuration can improve the capacitance value in the region below the pad electrode 95 to which a potential other than the gate potential is applied.

[0489] The capacitor structure 85 may have a depth equal to that of the gate structure 20. According to this configuration, the capacitance value below the pad electrode 95 is increased by the capacitor structure 85 having a depth equal to that of the gate structure 20. In this case, the capacitor structure 85 can be manufactured simultaneously with the gate structure 20.

[0490] The transistor structure T3 may include a trench electrode type emitter structure 30 to which an emitter potential is applied. In this case, the pad electrode 95 may apply a potential other than the emitter potential to the capacitor structure 85. This configuration can improve the capacitance value in the region below the pad electrode 95 to which a potential other than the emitter potential is applied.

[0491] The capacitor structure 85 may have a depth equal to that of the emitter structure 30. According to this configuration, the capacitance value below the pad electrode 95 is increased by the capacitor structure 85 having a depth equal to that of the emitter structure 30. In this case, the capacitor structure 85 can be manufactured simultaneously with the emitter structure 30.

[0492] The semiconductor device 1A may include a monitor region 7 and a monitor transistor structure T2 for monitoring current. The monitor region 7 may be provided outside the active region 6 on the first main surface 3. The monitor transistor structure T2 may be formed on the first main surface 3 in the monitor region 7.

[0493] In this case, a potential for the monitor transistor structure T2 may be applied to the pad electrode 95. According to this configuration, the capacitance value can be improved in the region below the pad electrode 95 where the potential for the monitor transistor structure T2 is applied.

[0494] The semiconductor device 1A may include a monitor electrode 67. The monitor electrode 67 may be electrically connected to the monitor transistor structure T2 on the first main surface 3 of the monitor region 7. In this case, the pad electrode 95 may be electrically connected to the monitor electrode 67 and apply a potential to the monitor transistor structure T2 via the monitor electrode 67.

[0495] The semiconductor device 1A may include a temperature detection region 10 (diode region) and a temperature sensing diode structure D (diode structure). The temperature detection region 10 may be provided outside the active region 6 on the first main surface 3. The temperature sensing diode structure D may be formed on the first main surface 3 in the temperature detection region 10.

[0496] In this case, a potential may be applied to the pad electrode 95 relative to the temperature sensitive diode structure D. According to this configuration, the capacitance value can be improved in the region below the pad electrode 95 where the potential is applied to the temperature sensitive diode structure D.

[0497] The semiconductor device 1A may include an anode wiring 75. The anode wiring 75 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the pad electrode 95 may be electrically connected to the anode wiring 75, and an anode potential may be applied to the temperature sensitive diode structure D via the anode wiring 75. This configuration can improve the capacitance value in the region below the pad electrode 95 to which the anode potential is applied.

[0498] The semiconductor device 1A may include a cathode wiring 76. The cathode wiring 76 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the pad electrode 95 may be electrically connected to the cathode wiring 76 and apply a cathode potential to the temperature sensitive diode structure D via the cathode wiring 76. This configuration can improve the capacitance value in the region below the pad electrode 95 to which the cathode potential is applied.

[0499] The semiconductor device 1A may include a main surface insulating film 48 and a capacitor electrode film 90 (electrode film). The main surface insulating film 48 may cover the first main surface 3 of the pad region 11. The capacitor electrode film 90 may cover the capacitor structure 85 on the main surface insulating film 48 and form a capacitive coupling with the chip 2 via the main surface insulating film 48.

[0500] In this case, the pad electrode 95 may be disposed on the capacitor electrode film 90 and electrically connected to the capacitor structure 85 via the capacitor electrode film 90. According to this configuration, the capacitance value below the pad electrode 95 is increased by both the capacitor structure 85 and the capacitor electrode film 90.

[0501] The semiconductor device 1A may include an insulating interlayer film 57 and a pad opening 91. The interlayer film 57 may cover the capacitor electrode film 90. The pad opening 91 may be formed in the interlayer film 57 so as to expose the capacitor electrode film 90.

[0502] In this case, the pad electrode 95 may be disposed on the interlayer film 57 and electrically connected to the capacitor electrode film 90 through the pad opening 91. According to this configuration, the pad electrode 95 can be appropriately electrically connected to the capacitor electrode film 90 while suppressing contact of the pad electrode 95 with other structures.

[0503] The capacitor structure 85 may include a capacitor trench 86, a capacitor insulating film 87 (dielectric film), and a capacitor buried electrode 88. The capacitor trench 86 may be formed in the first main surface 3.

[0504] The capacitor insulating film 87 may cover the wall surface of the capacitor trench 86. The capacitor buried electrode 88 may form a capacitive coupling with the chip 2 within the capacitor trench 86 via the capacitor insulating film 87. With this structure, the capacitance value of the capacitor structure 85 can be adjusted by the film thickness of the capacitor insulating film 87.

[0505] In such a configuration, the semiconductor device 1A may include a main surface insulating film 48 and a capacitor electrode film 90. The main surface insulating film 48 may cover the first main surface 3 of the pad region 11 so as to be connected to the capacitor insulating film 87. The capacitor electrode film 90 may be disposed on the main surface insulating film 48 so as to be connected to the capacitor buried electrode 88, and may form a capacitive coupling with the chip 2 via the main surface insulating film 48.

[0506] In this case, the pad electrode 95 may be disposed on the capacitor electrode film 90 and electrically connected to the buried electrode via the capacitor electrode film 90. According to this configuration, the capacitance value below the pad electrode 95 is increased by both the capacitor structure 85 and the capacitor electrode film 90.

[0507] The semiconductor device 1A may include an n-type (first conductivity type) drift region 12 and a p-type (second conductivity type) pad well region 80. The drift region 12 may be formed in the pad region 11 within the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 of the pad region 11 and electrically connected to the drift region 12.

[0508] In this case, the capacitor structure 85 may be disposed in the pad well region 80 and may form a capacitive coupling with the pad well region 80. According to this configuration, the capacitance value below the pad electrode 95 can be increased by the capacitor structure 85 that forms a capacitive coupling with the pad well region 80.

[0509] The capacitor structure 85 may be located in the pad well region 80 at a distance from the bottom of the pad well region 80 toward the first main surface 3. With this configuration, the capacitor structure 85 can be capacitively coupled to the pad well region 80 over the entire area in the thickness direction.

[0510] The semiconductor device 1A may include a p-type base region 15. The base region 15 may be formed in a surface layer portion of the first main surface 3 of the active region 6 and electrically connected to the drift region 12. In this case, the pad well region 80 may be formed deeper than the base region 15. With this configuration, the capacitance value below the pad electrode 95 can be increased by the capacitor structure 85 that forms capacitive coupling with the pad well region 80 that is deeper than the base region 15.

[0511] From another perspective, the semiconductor device 1A may include a chip 2, an active region 6, a pad region 11, an insulated gate type transistor structure T3, a main surface insulating film 48, a capacitor electrode film 90, and a pad electrode 95. The chip 2 may have a first main surface 3. The active region 6 may be provided on the first main surface 3. The pad region 11 may be provided outside the active region 6 on the first main surface 3. The transistor structure T3 may be formed in the active region 6.

[0512] The main surface insulating film 48 may have a portion covering the first main surface 3 in the pad region 11. The main surface insulating film 48 may have a thickness of 10 nm or more and 200 nm or less. The capacitor electrode film 90 may be disposed on the main surface insulating film 48 in the pad region 11 and may form a capacitive coupling with the chip 2 via the main surface insulating film 48. The pad electrode 95 may be disposed on the capacitor electrode film 90 in the pad region 11 and may be electrically connected to the capacitor electrode film 90.

[0513] This configuration provides a semiconductor device 1A capable of improving electrical characteristics. Specifically, in the pad region 11, the capacitance between the capacitor electrode film 90 and the chip 2 is increased by the main surface insulating film 48 serving as a dielectric thin film. As a result, the capacitance below the pad electrode 95 is increased by the capacitor electrode film 90, thereby improving the ESD resistance.

[0514] The semiconductor device 1A may include a p-type pad well region 80. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 in the pad region 11. In this case, the capacitor electrode film 90 may form a capacitive coupling with the pad well region 80 via the main surface insulating film 48. With this configuration, the capacitance value below the pad electrode 95 can be increased by the capacitor electrode film 90 that forms a capacitive coupling with the pad well region 80.

[0515] The semiconductor device 1A may include a p-type base region 15. The base region 15 may be formed in a surface layer portion of the first main surface 3 of the active region 6. In this case, the pad well region 80 may be formed deeper than the base region 15. With this configuration, the capacitance value below the pad electrode 95 can be increased by the capacitor electrode film 90 that forms capacitive coupling with the pad well region 80 that is deeper than the base region 15.

[0516] The semiconductor device 1A may include a gate trench 21, a gate insulating film 22, and a buried gate electrode 23. The gate trench 21 may be formed in the first main surface 3 of the active region 6. The gate insulating film 22 may cover the wall surface of the gate trench 21. The gate insulating film 22 may have a thickness of 10 nm or more and 200 nm or less.

[0517] The gate buried electrode 23 may be buried in the gate trench 21 with the gate insulating film 22 sandwiched therebetween. In this case, the main surface insulating film 48 may have a portion connected to the gate insulating film 22. According to this semiconductor device 1A, the capacitor electrode film 90 can form capacitive coupling with the chip 2 via the main surface insulating film 48 having a portion connected to the gate insulating film 22.

[0518] The semiconductor device 1A may include an insulating interlayer film 57 and a pad opening 91. The interlayer film 57 may have a thickness greater than that of the main surface insulating film 48 and may cover the capacitor electrode film 90. The pad opening 91 may be formed in the interlayer film 57 so as to expose the capacitor electrode film 90.

[0519] In this case, the pad electrode 95 may be disposed on the interlayer film 57 and electrically connected to the capacitor electrode film 90 through the pad opening 91. With this configuration, the capacitance value below the pad electrode 95 can be increased by utilizing the main surface insulating film 48 having a thickness smaller than that of the interlayer film 57. Furthermore, the pad electrode 95 can be appropriately electrically connected to the capacitor electrode film 90 while suppressing contact of the pad electrode 95 with other structures.

[0520] Fig. 24 is a plan view showing an example of the layout of the first main surface 3 of a semiconductor device 1B according to the second embodiment. Fig. 25 is an enlarged plan view showing a main portion of the active region 6 of the semiconductor device 1B shown in Fig. 24. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 25. The semiconductor device 1B is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT (Reverse Conducting - IGBT) structure having a transistor structure T3 and a freewheeling diode structure WD.

[0521] The semiconductor device 1B includes one or more (multiple in this embodiment) transistor regions 100 provided in each of the active regions 6, and one or more (multiple in this embodiment) freewheeling diode regions 101 provided in each of the active regions 6. The multiple transistor regions 100 are regions including the above-described transistor structure T3. The multiple transistor regions 100 are provided at intervals in the second direction Y in the corresponding active regions 6.

[0522] With respect to the plurality of adjacent active regions 6, the plurality of transistor regions 100 arranged in one active region 6 face the plurality of transistor regions 100 arranged in the other active region 6 in a one-to-one correspondence in the first direction X. In other words, the plurality of transistor regions 100 are arranged in a matrix on the first main surface 3 at intervals in the first direction X and the second direction Y.

[0523] The free wheel diode regions 101 are regions including a free wheel diode structure WD. Each of the free wheel diode regions 101 is provided in a region adjacent to one or more transistor regions 100 in the second direction Y in the corresponding active region 6. Specifically, the free wheel diode regions 101 and the transistor regions 100 are arranged alternately in the second direction Y.

[0524] With respect to the plurality of adjacent active regions 6, the plurality of free wheel diode regions 101 arranged in one active region 6 face the plurality of free wheel diode regions 101 arranged in the other active region 6 in a one-to-one correspondence in the first direction X. In other words, the plurality of free wheel diode regions 101 are arranged in a matrix on the first main surface 3 at intervals in the first direction X and the second direction Y. Of course, the plurality of free wheel diode regions 101 may face the plurality of transistor regions 100 in the first direction X.

[0525] The semiconductor device 1B includes, in each transistor region 100, a base region 15, a plurality of gate structures 20, a plurality of gate connection structures 25, a plurality of emitter structures 30, a plurality of emitter connection structures 35, a plurality of emitter regions 40, a contact region 41, a plurality of storage regions 42 and a plurality of well regions 43.

[0526] The layout of these components in the transistor region 100 is similar to the layout of the corresponding components in the active region 6 according to the first embodiment. For the description of the layout of these components in the transistor region 100, the description of the layout of the corresponding components in the active region 6 according to the first embodiment applies.

[0527] The semiconductor device 1B includes an n-type return cathode region 103 formed in a surface layer portion of the second main surface 4 in the return diode region 101. The return cathode region 103 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12.

[0528] The n-type impurity concentration of the return cathode region 103 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the return cathode region 103 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, thereby converting the conductivity type of the collector region 14 from p-type to n-type.

[0529] The return cathode region 103 passes through the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the return cathode region 103 has an upper end located within the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The return cathode region 103 may pass through the buffer region 13 and have an upper end located within the drift region 12.

[0530] The semiconductor device 1B includes a freewheeling diode structure WD formed on the first main surface 3 in the freewheeling diode region 101. The configuration of one freewheeling diode structure WD as one component of the semiconductor device 1B will be described below.

[0531] The freewheeling diode structure WD includes a p-type freewheeling anode region 104 formed in a surface layer portion of the first main surface 3 in the freewheeling diode region 101. The freewheeling anode region 104 is formed in a surface layer portion of the drift region 12. In this form, the freewheeling anode region 104 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, thereby converting the conductivity type of the drift region 12 from n-type to p-type.

[0532] The p-type impurity concentration of the reflux anode region 104 may be approximately equal to the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the reflux anode region 104 may be higher than the p-type impurity concentration of the base region 15, or may be lower than the p-type impurity concentration of the base region 15.

[0533] The return anode regions 104 are formed in the return diode region 101 in the form of layers extending along the first main surface 3, and face the return cathode region 103 across the drift region 12 in the thickness direction. The return anode regions 104 are formed at an interval from a depth position in the middle of the drift region 12 toward the first main surface 3.

[0534] The return anode region 104 may have a depth approximately equal to that of the base region 15. Of course, the depth of the return anode region 104 may be greater than or less than that of the base region 15. The depth of the return anode region 104 is preferably less than that of the well region 43. Of course, the depth of the return anode region 104 may be approximately equal to or greater than that of the well region 43.

[0535] The freewheeling diode structure WD includes a plurality of trench electrode type anode structures 105 formed on the first main surface 3 in the freewheeling diode region 101. An emitter potential is applied to the plurality of anode structures 105. The plurality of anode structures 105 extend in a strip shape in the first direction X in the anode pad region 11A and are arranged at intervals in the second direction Y.

[0536] That is, the multiple anode structures 105 are arranged in stripes extending in the first direction X. The extending direction of the multiple anode structures 105 coincides with the extending direction of the multiple gate structures 20. The extending direction of the multiple anode structures 105 coincides with the extending direction of the multiple emitter structures 30.

[0537] The multiple anode structures 105 may each have a width that is less than the width of the multiple street regions 9. The width of the anode structure 105 is the width in a direction (second direction Y) perpendicular to the extension direction of the anode structure 105 (first direction X).

[0538] The width of the anode structure 105 may be approximately equal to the width of the gate structure 20 (gate connection structure 25). Of course, the width of the anode structure 105 may be larger or smaller than the width of the gate structure 20 (gate connection structure 25).

[0539] The width of the anode structure 105 may be approximately equal to the width of the emitter structure 30 (emitter connection structure 35). Of course, the width of the emitter structure 30 may be greater than or smaller than the width of the emitter structure 30 (emitter connection structure 35).

[0540] The width of the anode structure 105 may be 0.5 μm or more and 5 μm or less. The width of the anode structure 105 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the anode structure 105 is preferably 1 μm or more and 2.5 μm or less.

[0541] The plurality of anode structures 105 penetrate the return anode region 104 to reach the drift region 12. The plurality of anode structures 105 are formed at intervals from a depth position in the middle of the drift region 12 toward the first main surface 3. The plurality of anode structures 105 face the return cathode region 103 in the thickness direction, sandwiching a part of the drift region 12 therebetween.

[0542] The plurality of anode structures 105 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of anode structures 105 may be formed substantially perpendicular to the first main surface 3. The bottom walls of the plurality of anode structures 105 may be formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of anode structures 105 may be formed substantially parallel to the first main surface 3. In this case, the corners of the bottom walls of the plurality of anode structures 105 may be formed in a curved shape.

[0543] The plurality of anode structures 105 may have a depth approximately equal to the depth of the plurality of gate structures 20 (gate connection structures 25). Of course, the depth of the anode structures 105 may be greater than or less than the depth of the gate structures 20 (gate connection structures 25).

[0544] The depth of the anode structure 105 may be approximately equal to the depth of the emitter structure 30 (emitter connection structure 35). Of course, the depth of the anode structure 105 may be greater than or less than the depth of the emitter structure 30 (emitter connection structure 35).

[0545] The depth of the anode structure 105 may be 0.5 μm or more and 10 μm or less. The depth of the anode structure 105 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the anode structure 105 is preferably 4 μm or more and 8 μm or less.

[0546] The third trench pitch between the centers of the multiple anode structures 105 may be approximately equal to the first trench pitch between the centers of the gate structures 20 and the emitter structures 30. Of course, the third trench pitch may be larger or smaller than the first trench pitch.

[0547] The third trench pitch may be 1 μm or more and 5 μm or less. The third trench pitch may have a value belonging to at least one range of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The third trench pitch is preferably 1.5 μm or more and 3.5 μm or less.

[0548] Each of the plurality of anode structures 105 includes an anode trench 106, an anode insulating film 107, and a buried anode electrode 108. The anode trench 106 is formed in the first main surface 3 and defines the wall surfaces (side walls and bottom wall) of the anode structure 105.

[0549] The anode insulating film 107 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The anode insulating film 107 preferably includes the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the anode insulating film 107 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the anode insulating film 107 includes a silicon oxide film made of an oxide of the chip 2.

[0550] The anode insulating film 107 covers the wall surface of the anode trench 106. The thickness of the anode insulating film 107 may be approximately equal to the thickness of the gate insulating film 22 (gate connecting insulating film 27). Of course, the thickness of the anode insulating film 107 may be greater than the thickness of the gate insulating film 22 (gate connecting insulating film 27) or may be smaller than the thickness of the gate insulating film 22 (gate connecting insulating film 27).

[0551] The thickness of the anode insulating film 107 may be approximately equal to the thickness of the emitter insulating film 32 (emitter connection insulating film 37). Of course, the thickness of the anode insulating film 107 may be greater than the thickness of the emitter insulating film 32 (emitter connection insulating film 37) or may be smaller than the thickness of the emitter insulating film 32 (emitter connection insulating film 37).

[0552] The thickness of the anode insulating film 107 may be 10 nm or more and 200 nm or less. The thickness of the anode insulating film 107 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the anode insulating film 107 is preferably 100 nm or more and 150 nm or less.

[0553] The buried anode electrode 108 is buried in the anode trench 106 with the anode insulating film 107 sandwiched therebetween. The buried anode electrode 108 faces the drift region 12 and the return anode region 104 with the anode insulating film 107 sandwiched therebetween.

[0554] The electrode surface of the buried anode electrode 108 may be located on the bottom wall side of the anode trench 106 with respect to the first main surface 3. The buried anode electrode 108 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried anode electrode 108 preferably includes the same type of conductor as the buried gate electrode 23.

[0555] The freewheeling diode structure WD includes a plurality of trench electrode type anode connection structures 110 formed on the first main surface 3 so as to be connected to the plurality of anode structures 105. An emitter potential is applied to the plurality of anode connection structures 110. The anode connection structures 110 may also be referred to as "trench anode connection structures."

[0556] The multiple anode connection structures 110 are respectively arranged on both end sides of the multiple anode structures 105 so as to be connected to one end and the other end of the multiple anode structures 105 in the first direction X, and together with the outermost multiple anode structures 105, define corresponding freewheeling diode regions 101.

[0557] The multiple anode connection structures 110 include an anode connection structure 110 on one end side of the multiple anode structures 105 in the first direction X and an anode connection structure 110 on the other end side of the multiple anode structures 105. The anode connection structure 110 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple anode structures 105. The anode connection structure 110 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple anode structures 105.

[0558] The multiple anode connection structures 110 may each have a width approximately equal to the width of the anode structure 105 (gate structure 20). Of course, the width of the anode connection structure 110 may be greater than or smaller than the width of the anode structure 105.

[0559] The width of the anode connection structure 110 may be 0.5 μm or more and 5 μm or less. The width of the anode connection structure 110 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the anode connection structure 110 is preferably 1 μm or more and 2.5 μm or less.

[0560] The plurality of anode connection structures 110 penetrate the return anode region 104 to reach the drift region 12. The plurality of anode connection structures 110 are formed at intervals from a depth position in the middle of the drift region 12 toward the first main surface 3, and face the return cathode region 103 across a part of the drift region 12 in the thickness direction.

[0561] The plurality of anode connection structures 110 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of anode connection structures 110 may be formed substantially perpendicular to the first main surface 3.

[0562] The multiple anode connection structures 110 may have bottom walls that are curved toward the second main surface 4. Of course, the bottom walls of the multiple anode connection structures 110 may be formed substantially parallel to the first main surface 3. In this case, the corners of the bottom walls of the multiple anode connection structures 110 may be formed in a curved shape.

[0563] The plurality of anode connection structures 110 may each have a depth approximately equal to the depth of the anode structure 105 (gate structure 20). Of course, the depth of the anode connection structure 110 may be greater than or less than the depth of the anode structure 105.

[0564] The depth of the anode connection structure 110 may be 0.5 μm or more and 10 μm or less. The depth of the anode connection structure 110 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the anode connection structure 110 is preferably 4 μm or more and 8 μm or less.

[0565] Each of the multiple anode connection structures 110 includes an anode connection trench 111, an anode connection insulating film 112, and an anode connection buried electrode 113. The anode connection trench 111 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the anode connection structure 110. The anode connection trench 111 communicates with the multiple anode trenches 106.

[0566] The anode connection insulating film 112 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The anode connection insulating film 112 preferably includes the same type of insulator as the anode insulating film 107 (gate insulating film 22). In this embodiment, the anode connection insulating film 112 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the anode connection insulating film 112 includes a silicon oxide film made of an oxide of the chip 2.

[0567] The anode connection insulating film 112 covers the wall surfaces of the anode connection trench 111 in a film-like manner. The anode connection insulating film 112 is connected to the anode insulating film 107 at the communicating portion between the anode trench 106 and the anode connection trench 111.

[0568] The anode-connection insulating film 112 may have a thickness substantially equal to that of the anode insulating film 107. Of course, the thickness of the anode-connection insulating film 112 may be greater than or less than that of the anode insulating film 107.

[0569] The anode-connection insulating film 112 may have a thickness of 10 nm or more and 200 nm or less. The thickness of the anode-connection insulating film 112 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the anode-connection insulating film 112 is preferably 100 nm or more and 150 nm or less.

[0570] The anode connection buried electrode 113 is buried in the anode connection trench 111 with the anode connection insulating film 112 sandwiched therebetween. The anode connection buried electrode 113 is connected to the anode buried electrode 108 at the communicating portion between the anode trench 106 and the anode connection trench 111.

[0571] The anode connection buried electrode 113 faces the drift region 12 and the return anode region 104 across the anode connection insulating film 112. The anode connection buried electrode 113 is partially covered with the interlayer film 57.

[0572] The electrode surface of the anode connection buried electrode 113 may be located closer to the bottom wall of the anode connection trench 111 than the first main surface 3. The anode connection buried electrode 113 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The anode connection buried electrode 113 preferably contains the same type of conductor as the anode buried electrode 108.

[0573] The freewheel diode structure WD includes a p-type boundary well region 115 formed in a surface layer portion of the first main surface 3 in the freewheel diode region 101. The boundary well region 115 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15.

[0574] Of course, the p-type impurity concentration of the boundary well region 115 may be lower than the p-type impurity concentration of the base region 15. The p-type impurity concentration of the boundary well region 115 may be approximately equal to the p-type impurity concentration of the well region 43. In this embodiment, the boundary well region 115 is formed in an electrically floating state.

[0575] The boundary well region 115 is formed in a region between a pair of anode structures 105 among the multiple anode structures 105 that are adjacent to the transistor region 100. Specifically, the boundary well region 115 is formed in a mesa region defined by the pair of anode structures 105 and the pair of anode connection structures 110.

[0576] The boundary well regions 115 each have a bottom located closer to the bottom walls of the anode structures 105 than the depth position of the bottom of the base region 15. The bottoms of the anode regions 51 are located closer to the bottom walls of the anode structures 105 than the depth positions of the intermediate portions of the anode structures 105. In this embodiment, the bottoms of the boundary well regions 115 are located closer to the second main surface 4 than the bottom walls of the anode structures 105.

[0577] The boundary well regions 115 extend in a strip shape in the first direction X following the extension direction of the multiple anode structures 105, and are connected to the multiple anode structures 105 and the multiple anode connection structures 110. The boundary well regions 115 may have a portion (bottom) covering the bottom walls of the multiple anode structures 105 and the multiple anode connection structures 110.

[0578] The semiconductor device 1B includes the aforementioned main surface insulating film 48 that selectively covers the first main surface 3 in the freewheeling diode region 101. The main surface insulating film 48 covers the freewheeling anode region 104 and the boundary well region 115 in the freewheeling diode region 101. The main surface insulating film 48 is connected to the anode insulating film 107 and the anode connection insulating film 112 in the freewheeling diode region 101, and exposes the anode buried electrode 108 and the anode connection buried electrode 113.

[0579] The main surface insulating film 48 may have a thickness substantially equal to that of the anode insulating film 107 (anode connecting buried electrode 113). Of course, the thickness of the main surface insulating film 48 may be greater than or less than the thickness of the anode insulating film 107 (anode connecting buried electrode 113).

[0580] The semiconductor device 1B includes the aforementioned interlayer film 57 that selectively covers the main surface insulating film 48 in the freewheeling diode region 101. The interlayer film 57 covers the freewheeling anode region 104 and the boundary well region 115 with the main surface insulating film 48 in between in the freewheeling diode region 101. The interlayer film 57 selectively covers the plurality of anode structures 105 and the plurality of anode connection structures 110.

[0581] In this embodiment, the interlayer film 57 extends from above the main surface insulating film 48 into the multiple anode trenches 106 and the multiple anode connection trenches 111. The interlayer film 57 has portions that cover the electrode surfaces of the multiple anode buried electrodes 108 in the multiple anode trenches 106. The interlayer film 57 has portions that cover the electrode surfaces of the multiple anode connection buried electrodes 113 in the multiple anode connection trenches 111.

[0582] The semiconductor device 1B includes a diode opening 116 formed in the interlayer film 57 in the freewheeling diode region 101. In this embodiment, the diode opening 116 exposes the inner portion of the anode region 51 and the inner portions of the plurality of anode structures 105.

[0583] The diode opening 116 exposes all of the anode structures 105. The emitter pad EP described above extends from above the interlayer film 57 into the diode opening 116, and is mechanically and electrically connected to the anode region 51 and the plurality of anode structures 105 within the diode opening 116.

[0584] In this embodiment, an example in which a plurality of anode structures 105 and a plurality of anode connection structures 110 are formed is shown, but the plurality of anode structures 105 and the plurality of anode connection structures 110 are not necessarily required and may be removed.

[0585] 27 is a cross-sectional view showing a main part of a semiconductor device 1C according to the third embodiment. The semiconductor device 1C is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT structure having a transistor structure T3 and a freewheeling diode structure WD. The configuration of the semiconductor device 1C may be combined with the semiconductor device 1B.

[0586] The semiconductor device 1C includes an n-type peripheral cathode region 120 formed in a surface layer portion of the second main surface 4 around the plurality of active regions 6. The peripheral cathode region 120 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12.

[0587] The n-type impurity concentration of the peripheral cathode region 120 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the peripheral cathode region 120 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, thereby converting the conductivity type of the collector region 14 from p-type to n-type.

[0588] The peripheral cathode region 120 is formed in a region facing the peripheral well region 44 in the thickness direction of the chip 2 in the surface layer portion of the second main surface 4. The peripheral cathode region 120 is preferably formed narrower than the peripheral well region 44 and faces the peripheral well region 44 with a gap inward from both ends of the peripheral well region 44. In other words, the entire peripheral cathode region 120 preferably faces the peripheral well region 44 in the thickness direction in a cross-sectional view.

[0589] The peripheral cathode region 120 penetrates the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the peripheral cathode region 120 has an upper end located in the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The peripheral cathode region 120 may also penetrate the buffer region 13 and have an upper end located in the drift region 12.

[0590] The peripheral cathode region 120 extends in a band shape along the periphery of the first main surface 3 at a distance inward from the periphery of the first main surface 3. In this embodiment, the peripheral cathode region 120 extends in a band shape along the extension direction of the peripheral well region 44 in a plan view. The peripheral cathode region 120 may be formed in an annular shape surrounding a plurality of active regions 6.

[0591] As described above, semiconductor device 1C may include a freewheeling diode structure WD including peripheral well region 44 as an anode and peripheral cathode region 120 as a cathode.

[0592] 28 is a cross-sectional view showing a main part of a semiconductor device 1D according to the fourth embodiment. The semiconductor device 1D is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT structure having a transistor structure T3 and a freewheeling diode structure WD. The configuration of the semiconductor device 1D may be combined with the semiconductor device 1B and the semiconductor device 1C.

[0593] The semiconductor device 1D includes an n-type street cathode region 121 formed in a surface layer portion of the second main surface 4 in the street region 9. The street cathode region 121 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12.

[0594] The n-type impurity concentration of the street cathode region 121 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the street cathode region 121 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, and converts the conductivity type of the collector region 14 from p-type to n-type.

[0595] The street cathode region 121 is formed in a region facing the street well region 45 in the thickness direction of the chip 2 in the surface layer portion of the second main surface 4. The street cathode region 121 is preferably formed to be narrower than the street well region 45, and faces the street well region 45 with a gap inward from both ends of the street well region 45.

[0596] The street cathode region 121 is preferably formed at a distance from the plurality of active regions 6. That is, the street cathode region 121 is preferably formed at a distance from the plurality of gate structures 20 and the plurality of gate connection structures 25 on the inward side of the street region 9. The entire area of ​​the street cathode region 121 is preferably opposed to the street well region 45 in the thickness direction in a cross-sectional view.

[0597] Of course, the street cathode region 121 may have a width larger than that of the street region 9, and may have portions extending from the street region 9 into the multiple active regions 6. In this case, the street cathode region 121 may face the multiple gate structures 20 and the multiple gate connection structures 25 in the thickness direction. The street cathode region 121 is formed in a strip shape extending in the second direction Y in line with the extension direction of the street region 9.

[0598] The street cathode region 121 penetrates the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the street cathode region 121 has an upper end located in the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The street cathode region 121 may also penetrate the buffer region 13 and have an upper end located in the drift region 12.

[0599] As described above, the semiconductor device 1D may include a freewheeling diode structure WD including the street well region 45 as an anode and the street cathode region 121 as a cathode.

[0600] 29 is a cross-sectional view showing a main part of a semiconductor device 1E according to a fifth embodiment. The semiconductor device 1E is a semiconductor switching device including a main transistor structure T1 as an RC-IGBT structure having a transistor structure T3 and a freewheeling diode structure WD. The configuration of the semiconductor device 1E may be combined with the semiconductor device 1B, the semiconductor device 1C, and the semiconductor device 1D.

[0601] The semiconductor device 1E includes an n-type pad cathode region 122 formed in a surface layer portion of the second main surface 4 in one or more pad regions 11. Fig. 29 shows an example in which the pad cathode region 122 is formed in the anode pad region 11A. Of course, the pad cathode region 122 may be formed in at least one of the gate pad region 11G, the monitor pad region 11M, and the cathode pad region 11C.

[0602] The pad cathode region 122 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the pad cathode region 122 may be higher than the n-type impurity concentration of the buffer region 13. In this embodiment, the pad cathode region 122 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, and converts the conductivity type of the collector region 14 from p-type to n-type.

[0603] The pad cathode region 122 is formed in a region facing the pad well region 80 in the thickness direction of the chip 2 in the surface layer portion of the second main surface 4. In this embodiment, the pad cathode region 122 faces the pad well region 80 and the plurality of capacitor structures 85 in the thickness direction.

[0604] The pad cathode region 122 may be formed over the entire area of ​​the corresponding pad region 11, or may be formed partially in a part of the corresponding pad region 11. The pad cathode region 122 may face all of the capacitor structures 85, or may face some of the capacitor structures 85. The pad cathode region 122 may face the entire areas of a plurality of capacitor structures 85, or may face only some of the plurality of capacitor structures 85.

[0605] The pad cathode region 122 passes through the collector region 14 and is electrically connected to the drift region 12. In this embodiment, the pad cathode region 122 has an upper end located in the buffer region 13 and is electrically connected to the drift region 12 via the buffer region 13. The pad cathode region 122 may pass through the buffer region 13 and have an upper end located in the drift region 12.

[0606] As described above, the semiconductor device 1E may include a freewheeling diode structure WD including the pad well region 80 as an anode and the pad cathode region 122 as a cathode.

[0607] Fig. 30 is a plan view showing a pad region 11 of a semiconductor device 1F according to a sixth embodiment. Fig. 31 is an enlarged plan view showing a main part of the pad region 11 shown in Fig. 30. Fig. 32 is a cross-sectional view taken along line XXXII-XXXII shown in Fig. 31.

[0608] 30 to 32, the semiconductor device 1F has a configuration obtained by modifying the plurality of pad capacitor structures 84 (monitor capacitor structure CM, anode capacitor structure CA, and cathode capacitor structure CC) of the semiconductor device 1A. The pad capacitor structure 84 of the semiconductor device 1F is also applicable to the semiconductor devices 1B to 1D.

[0609] The multiple pad capacitor structures 84 have the same configuration. In the following, the configuration of the anode capacitor structure CA will be described as an example of the pad capacitor structure 84. The configuration of the monitor capacitor structure CM can be obtained by replacing "anode capacitor structure CA" with "monitor capacitor structure CM" and "anode pad region 11A" with "monitor pad region 11M" in the following description.

[0610] The configuration of the cathode capacitor structure CC can be obtained by replacing "anode capacitor structure CA" with "cathode capacitor structure CC" and "anode pad area 11A" with "cathode pad area 11C" in the following description.

[0611] As in the semiconductor device 1A, the anode capacitor structure CA includes a plurality of capacitor structures 85 according to the first layout example. The anode capacitor structure CA may have at least one of the capacitor structures 85 according to the second to nineteenth layout examples (see FIGS. 18A to 18R).

[0612] In this embodiment, the plurality of capacitor buried electrodes 88 are buried in the plurality of capacitor trenches 86 so as to be exposed from the openings of the plurality of capacitor trenches 86. The plurality of capacitor buried electrodes 88 may each have an electrode surface located on the bottom wall side of the plurality of capacitor trenches 86 with respect to the height position of the first main surface 3.

[0613] In this embodiment, the anode capacitor structure CA does not have a capacitor electrode film 90. In this embodiment, the anode capacitor structure CA includes the aforementioned interlayer film 57 that directly covers the plurality of capacitor structures 85 in the anode pad region 11A. The interlayer film 57 has portions that cover the electrode surfaces of the plurality of capacitor buried electrodes 88 in the plurality of capacitor trenches 86.

[0614] The semiconductor device 1F includes one or more (multiple in this embodiment) pad openings 91 formed in the interlayer film 57 in the anode pad region 11A. The multiple pad openings 91 penetrate the interlayer film 57 and expose the multiple capacitor structures 85, respectively. In this embodiment, the multiple pad openings 91 are formed in a one-to-one correspondence with the multiple capacitor structures 85, and each extends in a strip shape following the extension direction of the corresponding capacitor structure 85 (first direction X in this embodiment).

[0615] Of course, the pad openings 91 may be formed at intervals following the extension direction of the corresponding capacitor structures 85. In this case, the pad openings 91 may be arranged in a matrix at intervals in the first direction X and the second direction Y. In this case, the pad openings 91 may be formed in a polygonal shape (such as a square or hexagonal shape) or a circular shape in a plan view.

[0616] The pad openings 91 are formed narrower than the corresponding capacitor structures 85 and are spaced inward from the sidewalls of the corresponding capacitor structures 85 to expose the inner portions of the corresponding capacitor structures 85. In other words, the pad openings 91 are formed narrower than the corresponding capacitor trenches 86 and are spaced inward from the sidewalls of the corresponding capacitor trenches 86 to expose the inner portions of the corresponding capacitor buried electrodes 88.

[0617] That is, the plurality of pad openings 91 expose only the corresponding capacitor structures 85 (capacitor buried electrodes 88), and do not expose the first main surface 3 (chip 2) or the main surface insulating film 48. The plurality of pad openings 91 each have a portion positioned above the height position of the first main surface 3, and a portion positioned on the bottom wall side of the corresponding capacitor structure 85 (capacitor trench 86) relative to the height position of the first main surface 3.

[0618] In this embodiment, the plurality of pad openings 91 are dug further downward from the electrode surfaces of the corresponding buried capacitor electrodes 88 toward the bottom wall sides of the corresponding capacitor trenches 86, and have bottom walls positioned within the buried capacitor electrodes 88. The bottom walls of the plurality of pad openings 91 are preferably formed at intervals from the depth position of the intermediate parts of the corresponding capacitor structures 85 (capacitor trenches 86) toward the opening sides of the capacitor structures 85 (capacitor trenches 86).

[0619] The anode capacitor structure CA includes a plurality of pad via electrodes 92 embedded in a plurality of pad openings 91 in the anode pad region 11A. In this embodiment, the plurality of pad via electrodes 92 each extend in a strip shape following the extension direction of the corresponding pad opening 91 (in this embodiment, the first direction X).

[0620] Of course, if multiple pad openings 91 are formed at intervals in the extension direction of the corresponding capacitor structures 85, multiple pad via electrodes 92 may be arranged at intervals in the extension direction of the corresponding capacitor structures 85.

[0621] The plurality of pad via electrodes 92 each have a portion in contact with the interlayer film 57 and the corresponding capacitor buried electrode 88 in the corresponding pad opening 91. The plurality of pad via electrodes 92 are mechanically and electrically connected to the corresponding capacitor buried electrode 88 in the plurality of pad openings 91.

[0622] The multiple pad via electrodes 92 each have a portion positioned above the height position of the first main surface 3 in the thickness direction, and a portion positioned on the bottom wall side of the capacitor structure 85 (capacitor trench 86) corresponding to the height position of the first main surface 3.

[0623] That is, the plurality of pad via electrodes 92 have portions facing the chip 2 across the corresponding capacitor insulating film 87 and capacitor buried electrode 88 in the horizontal direction in the corresponding capacitor trench 86. In this embodiment, the plurality of pad via electrodes 92 face the pad well region 80 across the capacitor insulating film 87 and capacitor buried electrode 88.

[0624] Each of the multiple pad via electrodes 92 may have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the wall surface side of the corresponding pad opening 91. The first electrode 60 is formed in the form of a film on the wall surface of the pad opening 91 as a barrier electrode. The first electrode 60 is mechanically and electrically connected to the capacitor buried electrode 88 in the corresponding pad opening 91.

[0625] The first electrode 60 may have a single layer structure including a titanium film or a titanium nitride film. The first electrode 60 may have a layered structure including a titanium film and a titanium nitride film. In this case, the titanium nitride film may be layered on the titanium film.

[0626] The second electrode 61 is embedded in the corresponding pad opening 91 across the first electrode 60, and is electrically connected to the capacitor embedded electrode 88 via the first electrode 60. The second electrode 61 may include at least one of a tungsten film, a molybdenum film, a nickel film, a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The second electrode 61 preferably includes a tungsten film.

[0627] In this embodiment, the anode pad AP collectively covers the plurality of capacitor structures 85 in a plan view and has a periphery (electrode sidewall) surrounding the plurality of capacitor structures 85. The anode pad AP is mechanically and electrically connected to the plurality of pad via electrodes 92 on the interlayer film 57, and is electrically connected to the plurality of capacitor structures 85 (capacitor buried electrodes 88) through the plurality of pad via electrodes 92.

[0628] As described above, the semiconductor device 1F may include the chip 2, the active region 6, the pad region 11, the insulated gate transistor structure T3, and the trench electrode capacitor structure 85. The chip 2 has a first main surface 3. The active region 6 is provided on the first main surface 3. The pad region 11 is provided outside the active region 6 on the first main surface 3.

[0629] The transistor structure T3 is formed on the first main surface 3 of the active region 6. The capacitor structure 85 is formed on the first main surface 3 of the pad region 11, and forms capacitive coupling with the chip 2. This configuration provides a semiconductor device 1F that can improve electrical characteristics. Specifically, in this semiconductor device 1F, the capacitance value of the pad region 11 is increased by the capacitor structure 85, resulting in improved ESD resistance.

[0630] The transistor structure T3 may include a trench electrode type gate structure 20 to which a gate potential is applied. In this case, a potential other than the gate potential may be applied to the capacitor structure 85. With this configuration, the capacitance value of the pad region 11 can be improved by the capacitor structure 85 to which a potential other than the gate potential is applied.

[0631] The capacitor structure 85 may have a depth equal to that of the gate structure 20. According to this configuration, the capacitance value of the pad region 11 is increased by the capacitor structure 85 having a depth equal to that of the gate structure 20. In this case, the capacitor structure 85 can be manufactured simultaneously with the gate structure 20.

[0632] The transistor structure T3 may include a trench electrode type emitter structure 30 to which an emitter potential is applied. In this case, a potential other than the emitter potential may be applied to the capacitor structure 85. With this configuration, the capacitance value of the pad region 11 can be improved by the capacitor structure 85 to which a potential other than the emitter potential is applied.

[0633] The capacitor structure 85 may have a depth equal to that of the emitter structure 30. According to this configuration, the capacitance value of the pad region 11 is increased by the capacitor structure 85 having a depth equal to that of the emitter structure 30. In this case, the capacitor structure 85 can be manufactured simultaneously with the emitter structure 30.

[0634] The semiconductor device 1F may include a monitor region 7 and a monitor transistor structure T2 for monitoring current. The monitor region 7 may be provided outside the active region 6 on the first main surface 3.

[0635] The monitor transistor structure T2 may be formed on the first main surface 3 of the monitor region 7. In this case, a potential for the monitor transistor structure T2 may be applied to the capacitor structure 85. With this configuration, the capacitance value of the pad region 11 can be improved by the capacitor structure 85 to which a potential for the monitor transistor structure T2 is applied.

[0636] The semiconductor device 1F may include a monitor electrode 67. The monitor electrode 67 may be electrically connected to the monitor transistor structure T2 on the first main surface 3 of the monitor region 7. In this case, the capacitor structure 85 may be electrically connected to the monitor electrode 67.

[0637] The semiconductor device 1F may include a temperature detection region 10 as a diode region and a temperature sensing diode structure D as a diode structure. The temperature detection region 10 may be provided outside the active region 6 on the first main surface 3. The temperature sensing diode structure D may be formed on the first main surface 3 in the temperature detection region 10.

[0638] In this case, the capacitor structure 85 may be applied with a potential relative to the temperature-sensitive diode structure D. According to this configuration, the capacitance value of the pad region 11 can be improved by the capacitor structure 85 to which the potential relative to the temperature-sensitive diode structure D is applied.

[0639] The semiconductor device 1F may include an anode wiring 75. The anode wiring 75 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the capacitor structure 85 may be electrically connected to the anode wiring 75. With this configuration, the capacitance value of the pad region 11 can be improved by the capacitor structure 85 to which an anode potential is applied.

[0640] The semiconductor device 1F may include a cathode wiring 76. The cathode wiring 76 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the capacitor structure 85 may be electrically connected to the cathode wiring 76. According to this configuration, the capacitance value of the pad region 11 can be improved by the capacitor structure 85 to which a cathode potential is applied.

[0641] The semiconductor device 1F may include an insulating interlayer film 57, a pad via electrode 92, and a pad electrode 95. The interlayer film 57 may cover the capacitor structure 85. The pad via electrode 92 may be embedded in the interlayer film 57 so as to be electrically connected to the capacitor structure 85.

[0642] The pad electrode 95 may be disposed on the interlayer film 57 and electrically connected to the capacitor structure 85 through the pad via electrode 92. According to this configuration, the pad electrode 95 can be appropriately electrically connected to the capacitor structure 85 while suppressing contact of the pad electrode 95 with other structures.

[0643] In this case, the pad via electrode 92 may be connected to the capacitor structure 85 in a region closer to the bottom wall of the capacitor structure 85 than the height position of the first main surface 3. According to this configuration, the pad via electrode 92 can be appropriately connected mechanically and electrically to the capacitor structure 85.

[0644] The capacitor structure 85 may include a capacitor trench 86, a capacitor insulating film 87 (capacitive insulating film), and a capacitor buried electrode 88. The capacitor trench 86 may be formed on the first main surface 3. The capacitor insulating film 87 may cover the wall surface of the capacitor trench 86.

[0645] The capacitor buried electrode 88 may form a capacitive coupling with the chip 2 in the capacitor trench 86 via a capacitor insulating film 87. With this structure, the capacitance value of the capacitor structure 85 can be adjusted by the film thickness of the capacitor insulating film 87. The capacitor insulating film 87 may have a thickness of 10 nm or more and 200 nm or less.

[0646] In this case, the semiconductor device 1F may include an interlayer film 57, a pad via electrode 92, and a pad electrode 95. The interlayer film 57 may cover the capacitor structure 85. The pad via electrode 92 may be buried in the interlayer film 57 so as to be electrically connected to the capacitor buried electrode 88.

[0647] The pad electrode 95 may be disposed on the interlayer film 57 and electrically connected to the capacitor-embedded electrode 88 through the pad via electrode 92. According to this configuration, the pad electrode 95 can be appropriately electrically connected to the capacitor-embedded electrode 88 while suppressing contact of the pad electrode 95 with other structures.

[0648] The buried capacitor electrode 88 may have an electrode surface located on the bottom wall side of the capacitor trench 86 relative to the height position of the first main surface 3. The interlayer film 57 may have a portion that covers the electrode surface of the buried capacitor electrode 88 in the capacitor trench 86.

[0649] The pad via electrode 92 may be mechanically and electrically connected to the capacitor buried electrode 88 in the capacitor trench 86. According to this configuration, the pad via electrode 92 can be appropriately mechanically and electrically connected to the capacitor buried electrode 88.

[0650] The semiconductor device 1F may include a main surface insulating film 48. The main surface insulating film 48 may cover the first main surface 3 of the pad region 11 so as to be connected to the capacitor insulating film 87. In this case, the interlayer film 57 may cover the main surface insulating film 48.

[0651] The semiconductor device 1F may include an n-type (first conductivity type) drift region 12 and a p-type (second conductivity type) pad well region 80. The drift region 12 may be formed in the pad region 11 within the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 of the pad region 11 and electrically connected to the drift region 12.

[0652] In this case, the capacitor structure 85 may be disposed in the pad well region 80 and may form a capacitive coupling with the pad well region 80. According to this configuration, the capacitance value of the pad region 11 can be increased by the capacitor structure 85 that forms a capacitive coupling with the pad well region 80.

[0653] The capacitor structure 85 may be located in the pad well region 80 at a distance from the bottom of the pad well region 80 toward the first main surface 3. With this configuration, the capacitor structure 85 can form capacitive coupling with the pad well region 80 over the entire area in the thickness direction.

[0654] The semiconductor device 1F may include a p-type base region 15. The base region 15 may be formed in a surface layer portion of the first main surface 3 of the active region 6 and electrically connected to the drift region 12. In this case, the pad well region 80 may be formed deeper than the base region 15. With this configuration, the capacitance value of the pad region 11 can be increased by the capacitor structure 85 that forms capacitive coupling with the pad well region 80 that is deeper than the base region 15.

[0655] From another perspective, the semiconductor device 1F may include a chip 2, an active region 6, a pad region 11, an insulated gate transistor structure T3, a capacitor trench 86, a capacitor insulating film 87 (insulating film), and a capacitor buried electrode 88. The chip 2 may have a first main surface 3. The active region 6 may be provided on the first main surface 3. The pad region 11 may be provided outside the active region 6 on the first main surface 3. The transistor structure T3 may be formed in the active region 6.

[0656] The capacitor trench 86 may be formed on the first main surface 3 of the pad region 11. A capacitor insulating film 87 may cover the wall surface of the capacitor trench 86. The capacitor buried electrode 88 may form a capacitive coupling with the chip 2 within the capacitor trench 86 via the capacitor insulating film 87. A potential other than the gate potential may be applied to the capacitor buried electrode 88.

[0657] This configuration provides a semiconductor device 1F capable of improving electrical characteristics. Specifically, in this semiconductor device 1F, the capacitance value of the pad region 11 is increased by the capacitor buried electrode 88 to which a potential other than the gate potential is applied, thereby improving ESD resistance. The capacitor insulating film 87 may have a thickness of 10 nm to 200 nm.

[0658] The semiconductor device 1F may include a p-type pad well region 80. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 in the pad region 11. In this case, the capacitor buried electrode 88 may be capacitively coupled to the pad well region 80 via a capacitor insulating film 87. According to this configuration, the capacitance value of the pad region 11 can be increased by the capacitor buried electrode 88 that is capacitively coupled to the pad well region 80.

[0659] The semiconductor device 1F may include a p-type base region 15. The base region 15 may be formed in a surface layer portion of the first main surface 3 of the active region 6. In this case, the pad well region 80 may be formed deeper than the base region 15. With this configuration, the capacitance value of the pad region 11 can be increased by the capacitor buried electrode 88 that forms capacitive coupling with the pad well region 80 that is deeper than the base region 15.

[0660] The semiconductor device 1F may include a gate trench 21, a gate insulating film 22, and a buried gate electrode 23. The gate trench 21 may be formed in the first main surface 3 of the active region 6. The gate insulating film 22 may cover the wall surface of the gate trench 21. The buried gate electrode 23 may be buried in the gate trench 21 with the gate insulating film 22 sandwiched therebetween.

[0661] The gate insulating film 22 may have a thickness of 10 nm or more and 200 nm or less. The semiconductor device 1F may include a main surface insulating film 48 that covers the first main surface 3. The main surface insulating film 48 may be connected to the gate insulating film 22 and the capacitor insulating film 87.

[0662] Modified examples applied to semiconductor devices 1A to 1F according to the first to sixth embodiments are shown below. Figures 33 to 36 are plan views showing first to fourth modified examples of semiconductor devices 1A to 1F according to the first to sixth embodiments. Semiconductor devices 1A to 1F according to the first to sixth embodiment examples may have at least one of the configurations according to the first to fourth modified examples. Of course, semiconductor devices 1A to 1F according to the first to sixth embodiment examples may have a configuration that combines at least two of the configurations according to the first to fourth modified examples.

[0663] With reference to Fig. 33 (first modification), semiconductor devices 1A to 1F that do not have a monitor capacitor structure CM may be employed. With reference to Fig. 34 (second modification), semiconductor devices 1A to 1F that do not have an anode capacitor structure CA may be employed. With reference to Fig. 35 (third modification), semiconductor devices 1A to 1F that do not have a cathode capacitor structure CC may be employed.

[0664] 36 (fourth modification), the semiconductor devices 1A to 1F may include a gate capacitor structure CG formed in the gate pad region 11G as a pad capacitor structure 84. A gate potential is applied to the gate capacitor structure CG.

[0665] The gate capacitor structure CG has a configuration similar to that of the anode capacitor structure CA, etc. The configuration of the gate capacitor structure CG can be obtained by replacing the "anode capacitor structure CA" with the "gate capacitor structure CG" and the "anode pad region 11A" with the "gate pad region 11G" in the above description.

[0666] Of course, the gate capacitor structure CG may have at least one feature of the pad capacitor structures 84 according to the first to nineteenth layout examples (see FIGS. 18A to 18R). Also, the gate capacitor structure CG may have at least one feature of the pad opening 91 according to the first to seventh layout examples (see FIGS. 19A to 19F). The aforementioned gate pad GP is electrically connected to the gate capacitor structure CG.

[0667] The above-described embodiments (including modifications) may be implemented in other forms. For example, each of the above-described embodiments (including modifications) may have a configuration that does not include the monitor region 7 (monitor transistor structure T2) but includes the active region 6 (transistor structure T3) and the temperature measurement region 10 (temperature-sensitive diode structure D).

[0668] In each of the above-described embodiments, a configuration may be adopted in which the temperature detection region 10 (temperature sensitive diode structure D) is not included, but the active region 6 (transistor structure T3) and the monitor region 7 (monitor transistor structure T2) are included.

[0669] In each of the above-described forms (including modified examples), a configuration may be adopted in which the active region 6 (transistor structure T3) is not included, but the monitor region 7 (monitor transistor structure T2) and / or the temperature measurement region 10 (temperature-sensitive diode structure D) are included.

[0670] In the above-described embodiments, a structure may be adopted in which the conductivity type of the “n-type” semiconductor region is inverted to “p-type” and the conductivity type of the “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0671] In the above-described embodiment, the collector region 14 may be removed. In this case, the main transistor structure T1 (transistor structure T3) includes a MISFET structure instead of an IGBT structure.

[0672] A specific configuration in this case can be obtained by replacing the "emitter" of the IGBT structure with the "source" of the MISFET structure and the "collector" of the IGBT structure with the "drain" of the MISFET structure in the above description. In this case, the chip 2 may have a layered structure including an n-type semiconductor substrate on the second main surface 4 side and an n-type epitaxial layer on the first main surface 3 side.

[0673] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "IGBT device," "RC-IGBT device," "MISFET device," "semiconductor rectifier device," etc., as necessary.

[0674] [A1] A chip (2) having a main surface (3), active regions (6, 6A to 6D) provided on the main surface (3), pad regions (11, 11A, 11C, 11G, 11M) provided outside the active regions (6, 6A to 6D) on the main surface (3), insulated gate type transistor structures (T1, T3) formed on the main surface (3) of the active regions (6, 6A to 6D), and pad regions (11, 11A, 11C, 11G, 11M) provided on the main surface (3) of the active regions (6, 6A to 6D). a trench electrode type capacitor structure (85, 85A, 85B) formed on the main surface (3) of the pad region (11, 11A, 11C, 11G, 11M) and forming a capacitive coupling with the chip (2), and a pad electrode (95, GP, MP, AP, CaP) arranged on the main surface (3) of the pad region (11, 11A, 11C, 11G, 11M) and electrically connected to the capacitor structure (85, 85A, 85B).

[0675] [A2] A semiconductor device (1A to 1F) according to A1, wherein the transistor structure (T1, T3) includes a trench electrode type gate structure (20) to which a gate potential is applied, and the pad electrode (95, GP, MP, AP, CaP) applies a potential other than the gate potential to the capacitor structure (85, 85A, 85B).

[0676] [A3] The semiconductor device (1A to 1F) according to A2, wherein the capacitor structure (85, 85A, 85B) has a depth equal to the depth of the gate structure (20).

[0677] [A4] A semiconductor device (1A to 1F) described in any one of A1 to A3, wherein the transistor structure (T1, T3) includes a trench electrode type emitter structure (30) to which an emitter potential is applied, and the pad electrode (95, GP, MP, AP, CaP) applies a potential other than the emitter potential to the capacitor structure (85, 85A, 85B).

[0678] [A5] The semiconductor device (1A to 1F) according to A4, wherein the capacitor structure (85, 85A, 85B) has a depth equal to the depth of the emitter structure (30).

[0679] [A6] A semiconductor device (1A to 1F) according to any one of A1 to A5, further including a monitor region (7) provided outside the active region (6, 6A to 6D) on the main surface (3), and a monitor transistor structure (T2) for monitoring a current formed on the main surface (3) of the monitor region (7), wherein a potential for the monitor transistor structure (T2) is applied to the pad electrode (95, GP, MP, AP, CaP).

[0680] [A7] The semiconductor device (1A to 1F) according to A6 further includes a monitor electrode (67) electrically connected to the monitor transistor structure (T2) on the main surface (3) of the monitor region (7), and the pad electrode (95, GP, MP, AP, CaP) is electrically connected to the monitor electrode (67) and applies a potential to the monitor transistor structure (T2) via the monitor electrode (67).

[0681] [A8] A semiconductor device (1A to 1F) according to any one of A1 to A5, further including a diode region (10) provided outside the active region (6, 6A to 6D) on the main surface (3), and a diode structure (D) formed on the main surface (3) of the diode region (10), wherein a potential relative to the diode structure (D) is applied to the pad electrode (95, GP, MP, AP, CaP).

[0682] [A9] The semiconductor device (1A to 1F) according to A8, further including wiring (75, 76) electrically connected to the diode structure (D) on the main surface (3), wherein the pad electrode (95, GP, MP, AP, CaP) is electrically connected to the wiring (75, 76) and applies a potential to the diode structure (D) via the wiring (75, 76).

[0683] [A10] A semiconductor device (1A to 1F) according to any one of A1 to A9, further comprising: a main surface insulating film (48) covering the main surface (3) of the pad region (11, 11A, 11C, 11G, 11M); and an electrode film (90) covering the capacitor structure (85, 85A, 85B) on the main surface insulating film (48) and forming a capacitive coupling with the chip (2) via the main surface insulating film (48), wherein the pad electrode (95, GP, MP, AP, CaP) is arranged on the electrode film (90) and is electrically connected to the capacitor structure (85, 85A, 85B) via the electrode film (90).

[0684] [A11] The semiconductor device (1A to 1F) according to A10 further includes an insulating interlayer film (57) covering the electrode film (90), and a pad opening (91) formed in the interlayer film (57) so as to expose the electrode film (90), and the pad electrode (95, GP, MP, AP, CaP) is disposed on the interlayer film (57) and is electrically connected to the electrode film (90) via the pad opening (91).

[0685] [A12] A semiconductor device (1A to 1F) described in any one of A1 to A9, wherein the capacitor structure (85, 85A, 85B) includes a trench (86) formed in the main surface (3), an insulating film (87) covering the wall surface of the trench (86), and a buried electrode (88) that forms a capacitive coupling with the chip (2) within the trench (86) via the insulating film (87).

[0686] [A13] The semiconductor device (1A to 1F) according to A12 further includes: a main surface insulating film (48) covering the main surface (3) of the pad region (11, 11A, 11C, 11G, 11M) so as to be connected to the insulating film (87); and an electrode film (90) arranged on the main surface insulating film (48) so as to be connected to the buried electrode (88), and forming a capacitive coupling with the chip (2) via the main surface insulating film (48), wherein the pad electrode (95, GP, MP, AP, CaP) is arranged on the electrode film (90) and is electrically connected to the buried electrode (88) via the electrode film (90).

[0687] [A14] A semiconductor device (1A to 1F) according to any one of A1 to A13, further comprising: a semiconductor region (12) of a first conductivity type (n-type) formed in the chip (2) in the pad region (11, 11A, 11C, 11G, 11M); and a well region (80) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3) of the pad region (11, 11A, 11C, 11G, 11M) and electrically connected to the semiconductor region (12), wherein the capacitor structure (85, 85A, 85B) is arranged in the well region (80) and forms capacitive coupling with the well region (80).

[0688] [A15] A semiconductor device (1A to 1F) according to A14, wherein the capacitor structure (85, 85A, 85B) is positioned within the well region (80) at a distance from the bottom of the well region (80) toward the main surface (3).

[0689] [A16] The semiconductor device (1A-1F) according to A14 or A15 further includes the semiconductor region (12) formed in the chip (2) in the active region (6, 6A-6D), and a second conductivity type (p-type) channel region (15) formed in a surface layer portion of the main surface (3) of the active region (6, 6A-6D) and electrically connected to the semiconductor region (12), wherein the well region (80) is formed deeper than the channel region (15).

[0690] [A17] A chip (2) having a main surface (3), active regions (6, 6A to 6D) provided on the main surface (3), pad regions (11, 11A, 11C, 11G, 11M) provided outside the active regions (6, 6A to 6D) on the main surface (3), transistor structures (T1, T3) formed in the active regions (6, 6A to 6D), and portions of the pad regions (11, 11A, 11C, 11G, 11M) covering the main surface (3), and having a thickness of 10 nm to 200 nm. a main surface insulating film (48) having a thickness of 1000 nm; an electrode film (90) disposed on the main surface insulating film (48) in the pad region (11, 11A, 11C, 11G, 11M) and forming a capacitive coupling with the chip (2) via the main surface insulating film (48); and a pad electrode (95, GP, MP, AP, CaP) disposed on the electrode film (90) in the pad region (11, 11A, 11C, 11G, 11M) and electrically connected to the electrode film (90).

[0691] [A18] A semiconductor device (1A to 1F) according to A17, further including a p-type well region (80) formed in a surface layer portion of the main surface (3) in the pad region (11, 11A, 11C, 11G, 11M), and the electrode film (90) forms a capacitive coupling with the well region (80) via the main surface insulating film (48).

[0692] [A19] The semiconductor device (1A to 1F) according to A18, wherein the transistor structure (T1, T3) includes a p-type channel region (15) formed in a surface layer portion of the main surface (3), and the well region (80) is formed deeper than the channel region (15).

[0693] [A20] The semiconductor device (1A-1F) according to any one of A17 to A19, wherein the transistor structure (T1, T3) includes a trench (21) formed in the main surface (3), an insulating film (22) covering the wall surface of the trench (21) and having a thickness of 10 nm or more and 200 nm or less, and a buried electrode (23) buried in the trench (21) across the insulating film (22), and the main surface insulating film (48) has a portion connected to the insulating film (22) in the active region (6, 6A-6D).

[0694] [B1] A semiconductor device (1A-1F) including: a chip (2) having a main surface (3); active regions (6, 6A-6D) provided on the main surface (3); pad regions (11, 11A, 11C, 11G, 11M) provided outside the active regions (6, 6A-6D) on the main surface (3); transistor structures (T1, T3) formed on the main surface (3) of the active regions (6, 6A-6D); and trench electrode type capacitor structures (85, 85A, 85B) formed on the main surface (3) of the pad regions (11, 11A, 11C, 11G, 11M) and forming capacitive coupling with the chip (2).

[0695] [B2] The semiconductor device (1A to 1F) according to B1, wherein the transistor structure (T1, T3) includes a trench electrode type gate structure (20) to which a gate potential is applied.

[0696] [B3] The semiconductor device (1A to 1F) according to B2, wherein a potential other than the gate potential is applied to the capacitor structure (85, 85A, 85B).

[0697] [B4] The semiconductor device (1A to 1F) according to B2 or B3, wherein the capacitor structure (85, 85A, 85B) has a depth equal to the depth of the gate structure (20).

[0698] [B5] The semiconductor device (1A to 1F) according to any one of B1 to B4, wherein the transistor structure (T1, T3) includes a trench electrode type emitter structure (30) to which an emitter potential is applied.

[0699] [B6] The semiconductor device (1A to 1F) according to B5, wherein a potential other than the emitter potential is applied to the capacitor structure (85, 85A, 85B).

[0700] [B7] The semiconductor device (1A to 1F) according to B5 or B6, wherein the capacitor structure (85, 85A, 85B) has a depth equal to the depth of the emitter structure (30).

[0701] [B8] A semiconductor device (1A to 1F) according to any one of B1 to B7, further including a monitor region (7) provided outside the active region (6, 6A to 6D) on the main surface (3), and a monitor transistor structure (T2) for monitoring current formed on the main surface (3) of the monitor region (7), wherein a potential is applied to the capacitor structure (85, 85A, 85B) relative to the monitor transistor structure (T2).

[0702] [B9] A semiconductor device (1A to 1F) according to any one of B1 to B7, further including a diode region (10) provided outside the active region (6, 6A to 6D) on the main surface (3), and a diode structure (D) formed on the main surface (3) of the diode region (10), wherein a potential relative to the diode structure (D) is applied to the capacitor structure (85, 85A, 85B).

[0703] [B10] A semiconductor device (1A-1F) according to any one of B1 to B9, further including: an insulating interlayer film (57) covering the capacitor structure (85, 85A, 85B); a via electrode (92) embedded in the interlayer film (57) so as to be electrically connected to the capacitor structure (85, 85A, 85B); and a pad electrode (95, GP, MP, AP, CaP) arranged on the interlayer film (57) and electrically connected to the capacitor structure (85, 85A, 85B) through the via electrode (92).

[0704] [B11] The semiconductor device (1A to 1F) described in B10, wherein the via electrode (92) is connected to the capacitor structure (85, 85A, 85B) in a region closer to the bottom wall of the capacitor structure (85, 85A, 85B) than the height position of the main surface (3).

[0705] [B12] A semiconductor device (1A to 1F) described in any one of B1 to B9, wherein the capacitor structure (85, 85A, 85B) includes a trench (86) formed in the main surface (3), an insulating film (87) covering the wall surface of the trench (86), and a buried electrode (88) that forms a capacitive coupling with the chip (2) within the trench (86) via the insulating film (87).

[0706] [B13] The semiconductor device (1A-1F) according to B12 further includes an insulating interlayer film (57) covering the capacitor structure (85, 85A, 85B), a via electrode (92) embedded in the interlayer film (57) so as to be electrically connected to the embedded electrode (88), and a pad electrode (95, GP, MP, AP, CaP) disposed on the interlayer film (57) and electrically connected to the embedded electrode (88) through the via electrode (92).

[0707] [B14] A semiconductor device (1A to 1F) according to B13, wherein the buried electrode (88) has an electrode surface positioned on the bottom wall side of the trench (86) relative to the height position of the main surface (3), the interlayer film (57) has a portion that covers the electrode surface of the buried electrode (88) within the trench (86), and the via electrode (92) is mechanically and electrically connected to the buried electrode (88) within the trench (86).

[0708] [B15] The semiconductor device (1A to 1F) according to B13 or B14, further comprising a main surface insulating film (48) covering the main surface (3) of the pad region (11, 11A, 11C, 11G, 11M) so as to be connected to the insulating film (87), and the interlayer film (57) covering the main surface insulating film (48).

[0709] [B16] A semiconductor device (1A to 1F) according to any one of B1 to B15, further comprising: a semiconductor region (12) of a first conductivity type (n-type) formed in the chip (2) in the pad region (11, 11A, 11C, 11G, 11M); and a well region (80) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3) of the pad region (11, 11A, 11C, 11G, 11M) and electrically connected to the semiconductor region (12), wherein the capacitor structure (85, 85A, 85B) is arranged in the well region (80) and forms capacitive coupling with the well region (80).

[0710] [B17] A semiconductor device (1A to 1F) according to B16, wherein the capacitor structure (85, 85A, 85B) is positioned within the well region (80) at a distance from the bottom of the well region (80) toward the main surface (3).

[0711] [B18] The semiconductor device (1A to 1F) according to B16 or B17 further includes a second conductivity type (p-type) channel region (15) formed in a surface layer portion of the main surface (3) of the active region (6, 6A to 6D) and electrically connected to the semiconductor region (12), and the well region (80) is formed deeper than the channel region (15).

[0712] [B19] A semiconductor device (1A-1F) including: a chip (2) having a main surface (3); active regions (6, 6A-6D) provided on the main surface (3); pad regions (11, 11A, 11C, 11G, 11M) provided on the main surface (3) outside the active regions (6, 6A-6D); insulated gate type transistor structures (T1, T3) formed in the active regions (6, 6A-6D); trenches (86) formed in the main surface (3) of the pad regions (11, 11A, 11C, 11G, 11M); a dielectric film (87) covering the wall surfaces of the trenches (86); and a buried electrode (88) that forms a capacitive coupling with the chip (2) through the dielectric film (87) within the trenches (86) and to which a potential other than a gate potential is applied.

[0713] [B20] A semiconductor device (1A to 1F) according to B19, further comprising a p-type well region (80) formed in the surface layer portion of the main surface (3) in the pad region (11, 11A, 11C, 11G, 11M), and the buried electrode (88) forms a capacitive coupling with the well region (80) via the dielectric film (87).

[0714] [C1] A semiconductor device (1A-1F) including: a chip (2) having a main surface (3); a diode region (10) provided on the main surface (3); a pad region (11, 11A, 11C) provided outside the diode region (10) on the main surface (3); a diode structure (D) formed in the diode region (10); and a trench electrode type capacitor structure (85, 85A, 85B) formed on the main surface (3) of the pad region (11, 11A, 11C) and forming a capacitive coupling with the chip (2).

[0715] [C2] A semiconductor device (1A to 1F) according to C1, further comprising a pad electrode (95, AP, CaP) arranged on the main surface (3) of the pad region (11, 11A, 11C) and electrically connected to the capacitor structure (85, 85A, 85B).

[0716] [D1] A semiconductor device (1A-1F) including: a chip (2) having a main surface (3); a monitor region (7) provided on the main surface (3); a pad region (11, 11M) provided outside the monitor region (7) on the main surface (3); an insulated gate type monitor transistor structure (TM) for current monitoring formed in the monitor region (7); and a trench electrode type capacitor structure (85, 85A, 85B) formed on the main surface (3) of the pad region (11, 11M) and forming a capacitive coupling with the chip (2).

[0717] [D2] A semiconductor device (1A to 1F) according to D1, further comprising a pad electrode (95, MP) arranged on the main surface (3) of the pad region (11, 11M) and electrically connected to the capacitor structure (85, 85A, 85B).

[0718] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification and the accompanying drawings can be appropriately combined without being limited by the order of explanation in the specification, the order of the embodiment examples, the order of the modified examples, etc.

[0719] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 1E Semiconductor device 1F Semiconductor device 2 Chip 3 First main surface 6 Active region 6A First active region 6B Second active region 6C Third active region 6D Fourth active region 7 Monitor region 10 Temperature measurement region (diode region) 11 Pad region 11G Gate pad region 11M Monitor pad region 11A Anode pad region 11C Cathode pad region 12 Drift region (semiconductor region) 15 Base region (channel region) 20 Gate structure 21 Gate trench 22 Gate insulating film 23 Gate buried electrode 30 Emitter structure 48 Main surface insulating film 57 Interlayer film 67 Monitor electrode 75 Anode wiring 76 Cathode wiring 80 Pad well region 85 Capacitor structure 85A First capacitor structure 85B Second capacitor structure 86 Capacitor trench 87 Capacitor insulating film (dielectric film) 88 Capacitor buried electrode 90 Capacitor electrode film 91 Pad opening 92 Pad via electrode 95 Pad electrode GP Gate pad (pad electrode) MP Monitor pad (pad electrode) AP Anode pad (pad electrode) CaP Cathode pad (pad electrode) D Diode structure T1 Transistor structure T2 Monitor transistor structure T3 Transistor structure

Claims

1. A semiconductor device comprising: a chip having a main surface; an active region provided on the main surface; a pad region provided on the main surface outside the active region; an insulated gate type transistor structure formed on the main surface of the active region; a trench electrode type capacitor structure formed on the main surface of the pad region and forming a capacitive coupling with the chip; and a pad electrode disposed on the main surface of the pad region and electrically connected to the capacitor structure.

2. The semiconductor device according to claim 1, wherein the transistor structure includes a trench electrode type gate structure to which a gate potential is applied, and a potential other than the gate potential is applied to the pad electrode.

3. The semiconductor device according to claim 2, wherein said capacitor structure has a depth equal to a depth of said gate structure.

4. A semiconductor device according to any one of claims 1 to 3, wherein the transistor structure includes a trench electrode type emitter structure to which an emitter potential is applied, and a potential other than the emitter potential is applied to the pad electrode.

5. The semiconductor device according to claim 4, wherein said capacitor structure has a depth equal to a depth of said emitter structure.

6. A semiconductor device according to any one of claims 1 to 5, further comprising: a monitor region provided on said main surface outside said active region; and a monitor transistor structure for monitoring current formed on said main surface of said monitor region, wherein a potential for said monitor transistor structure is applied to said pad electrode.

7. The semiconductor device according to claim 6, further comprising a monitor electrode electrically connected to said monitor transistor structure on said main surface of said monitor region, said pad electrode being electrically connected to said monitor electrode and applying a potential to said monitor transistor structure via said monitor electrode.

8. The semiconductor device according to any one of claims 1 to 5, further comprising: a diode region provided on the main surface outside the active region; and a diode structure formed on the main surface of the diode region, wherein a potential for the diode structure is applied to the pad electrode.

9. The semiconductor device according to claim 8, further comprising wiring electrically connected to said diode structure on said main surface, said pad electrode being electrically connected to said wiring and applying a potential to said diode structure via said wiring.

10. A semiconductor device as claimed in any one of claims 1 to 9, further comprising: a main surface insulating film covering the main surface of the pad region; and an electrode film covering the capacitor structure on the main surface insulating film and forming a capacitive coupling with the chip via the main surface insulating film, wherein the pad electrode is disposed on the electrode film and is electrically connected to the capacitor structure via the electrode film.

11. The semiconductor device according to claim 10, further comprising: an insulating interlayer film covering the electrode film; and a pad opening formed in the interlayer film so as to expose the electrode film, wherein the pad electrode is disposed on the interlayer film and is electrically connected to the electrode film via the pad opening.

12. A semiconductor device according to any one of claims 1 to 9, wherein the capacitor structure includes a trench formed in the main surface, an insulating film covering a wall surface of the trench, and a buried electrode that forms a capacitive coupling with the chip within the trench via the insulating film.

13. The semiconductor device according to claim 12, further comprising: a main surface insulating film covering the main surface of the pad region so as to be connected to the insulating film; and an electrode film arranged on the main surface insulating film so as to be connected to the buried electrode, and forming a capacitive coupling with the chip via the main surface insulating film, wherein the pad electrode is arranged on the electrode film and is electrically connected to the buried electrode via the electrode film.

14. A semiconductor device according to any one of claims 1 to 13, further comprising: a semiconductor region of a first conductivity type formed within the chip in the pad region; and a well region of a second conductivity type formed in a surface layer of the main surface of the pad region and electrically connected to the semiconductor region, wherein the capacitor structure is disposed within the well region and forms a capacitive coupling with the well region.

15. The semiconductor device according to claim 14, wherein said capacitor structure is positioned in said well region with a space therebetween from a bottom of said well region toward said main surface.

16. The semiconductor device according to claim 14 or 15, further comprising: a semiconductor region formed within the chip in the active region; and a base region of a second conductivity type formed in a surface layer of the main surface of the active region and electrically connected to the semiconductor region, wherein the well region is formed deeper than the base region.

17. A semiconductor device comprising: a chip having a main surface; an active region provided on the main surface; a pad region provided on the main surface outside the active region; a transistor structure formed in the active region; a main surface insulating film having a portion covering the main surface of the pad region and having a thickness of 10 nm or more and 200 nm or less; an electrode film disposed on the main surface insulating film in the pad region and forming a capacitive coupling with the chip via the main surface insulating film; and a pad electrode disposed on the electrode film in the pad region and electrically connected to the electrode film.

18. The semiconductor device according to claim 17, further comprising a p-type well region formed in a surface layer portion of the main surface in the pad region, the electrode film forming a capacitive coupling with the well region via the main surface insulating film.

19. The semiconductor device according to claim 18, wherein the transistor structure includes a p-type channel region formed in a surface layer portion of the main surface, and the well region is formed deeper than the channel region.

20. A semiconductor device according to any one of claims 17 to 19, wherein the transistor structure includes a trench formed in the main surface, an insulating film covering a wall surface of the trench and having a thickness of 10 nm or more and 200 nm or less, and a buried electrode buried in the trench across the insulating film, and the main surface insulating film has a portion connected to the insulating film in the active region.

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