Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a pad region provided on the main surface; a first electrode that is disposed on the main surface of the pad region, a first potential being applied to the first electrode; a side wall dielectric film that covers the side wall of the first electrode in the pad region; and a second electrode that is disposed on the main surface so as to form a capacitive coupling with the first electrode via the side wall dielectric film in the pad region, a second potential different from the first potential being applied to the second electrode.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-168423 filed with the Japan Patent Office on September 28, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2023 / 0106733A1) discloses a semiconductor device including a semiconductor substrate, a trench gate structure, an interlayer insulating film, a source electrode, an isolation insulating film, and a gate pad. The trench gate structure is formed in the semiconductor substrate. The interlayer insulating film is formed on the trench gate structure. The source electrode is formed on the interlayer insulating film. The isolation insulating film is formed on the source electrode. The gate pad is disposed on the source electrode via the isolation insulating film.

[0003] US Patent Application Publication No. 2023 / 0106733

[0004] [Summary] The present disclosure provides a semiconductor device that can improve electrical characteristics.

[0005] The present disclosure provides a semiconductor device including a chip having a main surface, a pad region provided on the main surface, a first electrode disposed on the main surface in the pad region and to which a first potential is applied, a sidewall dielectric film covering a sidewall of the first electrode in the pad region, and a second electrode disposed on the main surface in the pad region so as to face the first electrode across the sidewall dielectric film, forming a capacitive coupling with the first electrode via the sidewall dielectric film, and to which a second potential different from the first potential is applied.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a first electrode disposed on the main surface and to which a first potential is applied; a first dielectric film covering the main surface; a second dielectric film covering a sidewall of the first electrode; and a second electrode disposed on the first dielectric film so as to form a capacitive coupling with the chip via the first dielectric film and to form a capacitive coupling with the first electrode via the second dielectric film, the second electrode being applied with a second potential different from the first potential.

[0007] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a circuit diagram showing an example of the electrical configuration of a semiconductor device according to a first embodiment. FIG. 2 is a plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of an active region. FIG. 5 is an enlarged plan view showing another main portion of the active region. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is an enlarged plan view showing a main portion of a monitor region. FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 9. FIG. 12 is an enlarged plan view showing a temperature detection region. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is an enlarged plan view showing the configuration of the pad region together with the pad structure according to the first layout example. FIG. 15 is an enlarged plan view showing a main portion of the pad region. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 15 . FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 15 . FIG. 19 is an enlarged cross-sectional view of a main portion shown in FIG. 16 . FIG. 20A is a plan view showing a pad structure according to a second layout example. FIG. 20B is a plan view showing a pad structure according to a third layout example. FIG. 20C is a plan view showing a pad structure according to a fourth layout example. FIG. 20D is a plan view showing a pad structure according to a fifth layout example. FIG. 20E is a plan view showing a pad structure according to a sixth layout example. FIG. 20F is a plan view showing a pad structure according to a seventh layout example. FIG. 20G is a plan view showing a pad structure according to an eighth layout example. FIG. 20H is a plan view showing a pad structure according to a ninth layout example. FIG. 20I is a plan view showing a pad structure according to a tenth layout example. Fig. 20J is a plan view showing a pad structure according to an eleventh layout example. Fig. 20K is a plan view showing a pad structure according to a twelfth layout example. Fig. 20L is a plan view showing a pad structure according to a thirteenth layout example. Fig. 20M is a plan view showing a pad structure according to a fourteenth layout example. Fig. 21 is a plan view illustrating an electrical test on the gate pad electrode side.FIG. 22 is a plan view illustrating an electrical test on the monitor pad electrode side. FIG. 23 is a plan view illustrating an electrical test on the anode pad electrode side. FIG. 24 is a plan view illustrating an electrical test on the cathode pad electrode side. FIG. 25 is a cross-sectional view showing a main portion of a semiconductor device according to the second embodiment. FIG. 26 is a cross-sectional view showing a main portion of a semiconductor device according to the third embodiment. FIG. 27 is a cross-sectional view showing a main portion of a semiconductor device according to the fourth embodiment. FIG. 28 is a cross-sectional view showing a main portion of a semiconductor device according to the fifth embodiment. FIG. 29 is a cross-sectional view showing a main portion of a semiconductor device according to the sixth embodiment. FIG. 30 is a cross-sectional view showing a main portion of a semiconductor device according to the seventh embodiment. FIG. 31 is a plan view showing an example layout of a first main surface of a semiconductor device according to the eighth embodiment. FIG. 31 is an enlarged plan view showing a main portion of an active region of the semiconductor device shown in FIG. 28. FIG. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in FIG. 29. FIG. 34 is a cross-sectional view showing a main portion of a semiconductor device according to the ninth embodiment. FIG. 35 is a cross-sectional view showing a main portion of a semiconductor device according to the tenth embodiment. Fig. 36 is a cross-sectional view showing a main part of a semiconductor device according to the eleventh embodiment. Fig. 37 is a plan view showing a first modified example of the semiconductor device according to the first to eleventh embodiments. Fig. 38 is a plan view showing a second modified example of the semiconductor device according to the first to eleventh embodiments. Fig. 39 is a plan view showing a third modified example of the semiconductor device according to the first to eleventh embodiments. Fig. 40 is a plan view showing a fourth modified example of the semiconductor device according to the first to eleventh embodiments.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0012] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] 1 is a circuit diagram showing an example of the electrical configuration of a semiconductor device 1A according to the first embodiment. The semiconductor device 1A includes a gate pad GP, an emitter pad EP, a monitor pad MP, a collector pad CoP, an anode pad AP, a cathode pad CaP, an insulated gate main transistor structure T1, an insulated gate monitor transistor structure T2, and a temperature sensitive diode structure D. In other words, the semiconductor device 1A is a semiconductor switching device.

[0014] The main transistor structure T1 is composed of one or more transistor structures T3, and in this embodiment, the main transistor structure T1 includes a parallel circuit composed of multiple (four in this embodiment) transistor structures T3.

[0015] The transistor structure T3 includes either or both of a MISFET structure and an IGBT structure, and in this embodiment, the transistor structure T3 has a trench gate vertical IGBT structure.

[0016] The main transistor structure T1 (transistor structure T3) includes a gate electrically connected to a gate pad GP, an emitter electrically connected to an emitter pad EP, and a collector electrically connected to a collector pad CoP.

[0017] The main transistor structure T1 is turned on and off in response to a gate potential applied from the gate pad GP, and generates an output current Ice between the emitter pad EP and the collector pad CoP. The output current Ice is an emitter-collector current of the main transistor structure T1.

[0018] In this configuration, the monitor transistor structure T2 is connected in parallel to the main transistor structure T1. In this configuration, the monitor transistor structure T2 has a trench-gate vertical IGBT structure. The monitor transistor structure T2 includes a monitor gate electrically connected to the gate pad GP, a monitor emitter electrically connected to the monitor pad MP, and a monitor collector electrically connected to the collector pad CoP.

[0019] The monitor transistor structure T2 is controlled to be turned on and off at the same timing as the main transistor structure T1 in response to a gate potential applied from the gate pad GP, and generates a monitor current Im for monitoring the output current Ice between the monitor pad MP and the collector pad CoP. The monitor current Im is an emitter-collector current of the monitor transistor structure T2.

[0020] The monitor current Im is less than the output current Ice. A current ratio Im / Iec of the monitor current Im to the output current Ice may be 1 / 2000 or more and 1 / 10 or less. The current ratio Im / Iec may have a value belonging to at least one of the ranges of 1 / 2000 or more and 1 / 1750 or less, 1 / 1750 or more and 1 / 1500 or less, 1 / 1500 or more and 1 / 1250 or less, 1 / 1250 or more and 1 / 1000 or less, 1 / 1000 or more and 1 / 750 or less, 1 / 750 or more and 1 / 500 or less, 1 / 500 or more and 1 / 250 or less, 1 / 250 or more and 1 / 100 or less, 1 / 100 or more and 1 / 75 or less, 1 / 75 or more and 1 / 50 or less, 1 / 50 or more and 1 / 25 or less, and 1 / 25 or more and 1 / 10 or less.

[0021] The temperature sensitive diode structure D has a parallel circuit PC including one or more (four in this embodiment) first diodes D1 and one or more (four in this embodiment) second diodes D2. The number of second diodes D2 is the same as the number of first diodes D1. Of course, the number of second diodes D2 may be greater than or less than the number of first diodes D1.

[0022] The first diodes D1 are connected in series in the forward direction to form a first series circuit SC1, the anode of which is electrically connected to the anode pad AP, and the cathode of which is electrically connected to the cathode pad CaP.

[0023] The second diodes D2 are connected in series in the forward direction to form a second series circuit SC2. The cathode of the second series circuit SC2 is electrically connected to the anode pad AP. The anode of the second series circuit SC2 is electrically connected to the cathode pad CaP. In other words, the second series circuit SC2 is connected in reverse bias parallel to the first series circuit SC1, and together with the first series circuit SC1, forms a parallel circuit PC.

[0024] The first series circuit SC1 functions as a temperature sensor, and the second series circuit SC2 functions as a protection circuit. The first series circuit SC1 (plurality of first diodes D1) has a temperature characteristic (e.g., a positive temperature characteristic) that varies with temperature in relation to a forward voltage, and outputs a forward current that corresponds to the temperature of the chip 2.

[0025] The second series circuit SC2 provides immunity to noise signals. It is preferable that the second series circuit SC2 has electrical characteristics (high-frequency impedance characteristics) substantially equal to those of the first series circuit SC1. If the protection function of the second series circuit SC2 is not required, the second series circuit SC2 may be omitted.

[0026] The semiconductor device 1A includes a monitor capacitor structure CM electrically interposed between the emitter pad EP and the monitor pad MP. When a voltage is applied between the emitter pad EP and the monitor pad MP, the monitor capacitor structure CM functions as a capacitor between the emitter pad EP and the monitor pad MP.

[0027] The monitor capacitor structure CM also functions as a capacitor between the gate pad GP and the monitor pad MP when a voltage is applied between the gate pad GP and the monitor pad MP.

[0028] The semiconductor device 1A includes an anode capacitor structure CA electrically interposed between the emitter pad EP and the anode pad AP. When a voltage is applied between the emitter pad EP and the anode pad AP, the anode capacitor structure CA functions as a capacitor between the emitter pad EP and the anode pad AP.

[0029] The anode capacitor structure CA also functions as a capacitor between the gate pad GP and the anode pad AP when a voltage is applied between the gate pad GP and the anode pad AP.

[0030] The semiconductor device 1A includes a cathode capacitor structure CC electrically interposed between the emitter pad EP and the cathode pad CaP. When a voltage is applied between the emitter pad EP and the cathode pad CaP, the cathode capacitor structure CC functions as a capacitor between the emitter pad EP and the cathode pad CaP.

[0031] The cathode capacitor structure CC also functions as a capacitor between the gate pad GP and the cathode pad CaP when a voltage is applied between the gate pad GP and the cathode pad CaP.

[0032] FIG. 2 is a plan view of the semiconductor device 1A shown in FIG. 1. FIG. 3 is a plan view showing an example layout of the first main surface 3. FIG. 4 is an enlarged plan view showing a main portion of the active region 6. FIG. 5 is an enlarged plan view showing another main portion of the active region 6. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.

[0033] 2 to 8, semiconductor device 1A includes a hexahedral (specifically, rectangular parallelepiped) chip 2. Chip 2 includes either or both of silicon single crystal and wide bandgap semiconductor single crystal.

[0034] A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). The chip 2 may be referred to as a "semiconductor chip," a "silicon chip," a "wide bandgap semiconductor chip," or the like.

[0035] When SiC single crystal is used as the wide bandgap semiconductor single crystal, the chip 2 is preferably made of hexagonal SiC single crystal. Hexagonal SiC single crystal has a variety of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. The chip 2 preferably includes 4H-SiC single crystal. Of course, the chip 2 may also include other polytypes. In this embodiment, the chip 2 has a single-layer structure made of silicon single crystal.

[0036] The chip 2 may have a thickness of 50 μm or more and 500 μm or less. The thickness of the chip 2 may have a value belonging to at least one of the ranges of 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0037] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0038] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face away from (oppose to) a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face away from (oppose to) the first direction X.

[0039] Hereinafter, the direction extending along the first main surface 3 may be referred to as the “horizontal direction.” The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0040] The semiconductor device 1A includes one or more active regions 6 provided on the first main surface 3. The active regions 6 are regions having a transistor structure T3. The number of active regions 6 is arbitrary and is adjusted appropriately depending on the size of the chip 2 (first main surface 3).

[0041] In this embodiment, the semiconductor device 1A includes a plurality (four in this embodiment) of active regions 6. The plurality of active regions 6 include a first active region 6A, a second active region 6B, a third active region 6C, and a fourth active region 6D, which are arranged from the third side surface 5C side toward the fourth side surface 5D side.

[0042] The active regions 6 are provided in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active regions 6 are arranged at intervals in the first direction X and extend in strip shapes in the second direction Y. The active regions 6 are unevenly distributed closer to the second side surface 5B than the first side surface 5A.

[0043] The planar shape of the multiple active regions 6 is arbitrary. In this embodiment, the multiple active regions 6 are defined in the shape of a polygon having four sides parallel to the periphery of the chip 2. The width in the first direction X, the length in the second direction Y, the planar area, etc. of the multiple active regions 6 may be different from one another. At least two of the multiple active regions 6 may be partially connected.

[0044] The semiconductor device 1A includes a monitor region 7 provided on the first main surface 3. The monitor region 7 is a region having a monitor transistor structure T2. The monitor region 7 is provided in a region outside the plurality of active regions 6. The layout location of the monitor region 7 is arbitrary. In this embodiment, the monitor region 7 is arranged on the first side surface 5A side with respect to the plurality of active regions 6.

[0045] In this embodiment, the monitor region 7 is disposed near a corner connecting the first side surface 5A and the fourth side surface 5D. The monitor region 7 may face at least one active region 6 in the second direction Y. The monitor region 7 has a planar area smaller than the planar areas of the multiple active regions 6. The planar area of ​​the monitor region 7 is arbitrary and is adjusted appropriately depending on the size of the chip 2 (first main surface 3) and the monitor current Im.

[0046] The semiconductor device 1A includes a peripheral region 8 provided on the periphery of the first main surface 3. The peripheral region 8 is a region that does not have the monitor transistor structure T2 or the transistor structure T3. The peripheral region 8 is provided in a region outside the multiple active regions 6 and the monitor region 7 on the periphery of the first main surface 3. The peripheral region 8 is formed in an annular shape extending along the periphery of the first main surface 3 and surrounds the multiple active regions 6 and the monitor region 7.

[0047] The semiconductor device 1A includes one or more (multiple in this embodiment) street regions 9 provided on the first main surface 3. The street regions 9 are regions that do not have the monitor transistor structure T2 or the transistor structure T3.

[0048] The plurality of street regions 9 are provided in regions outside the plurality of active regions 6 and the monitor region 7. The plurality of street regions 9 are partitioned into regions between adjacent plurality of active regions 6, and extend in strip shapes along the second direction Y following the extension direction of the plurality of active regions 6.

[0049] The semiconductor device 1A includes a temperature detection region 10 provided on the first main surface 3. The temperature detection region 10 is a region including a temperature sensing diode structure D for detecting the temperature of the chip 2. The temperature detection region 10 may also be referred to as a "diode region," a "temperature sensing diode region," or the like. The temperature detection region 10 is provided in a region outside the multiple active regions 6 and the monitor region 7.

[0050] In this embodiment, the temperature measurement region 10 is formed in a region between the plurality of active regions 6 by utilizing a part of the street region 9, and faces the plurality of active regions 6 in the first direction X. In this embodiment, the temperature measurement region 10 is formed in a region between the second active region 6B and the third active region 6C.

[0051] The temperature measurement region 10 has a planar area smaller than the planar area of ​​the plurality of active regions 6. The layout location of the temperature measurement region 10 is arbitrary. The temperature rises relatively easily in the inner part of the first main surface 3 (chip 2). Therefore, it is preferable that the temperature measurement region 10 be provided in the inner part of the first main surface 3 (for example, near the center).

[0052] In this case, the temperature of the chip 2 is appropriately detected. When a first imaginary line passing through the center of the first main surface 3 in the first direction X and a second imaginary line passing through the center of the first main surface 3 in the second direction Y are set, a part of the temperature measurement region 10 may overlap either or both of the first imaginary line and the second imaginary line.

[0053] The semiconductor device 1A includes a plurality of pad regions 11 provided on the first main surface 3. The plurality of pad regions 11 are regions where external terminals for external connection are arranged. The plurality of pad regions 11 are provided in regions outside the plurality of active regions 6, the monitor region 7, the plurality of street regions 9, and the temperature detection region 10.

[0054] The layout locations of the plurality of pad regions 11 are arbitrary. In this embodiment, the plurality of pad regions 11 are formed by utilizing a part of the outer peripheral region 8 in the region on the first side surface 5A side of the plurality of active regions 6.

[0055] The multiple pad regions 11 include a gate pad region 11G, a monitor pad region 11M, an anode pad region 11A, and a cathode pad region 11C. The gate pad region 11G is a region where a gate pad GP is arranged. The monitor pad region 11M is a region where a monitor pad MP is arranged. The anode pad region 11A is a region where an anode pad AP is arranged. The cathode pad region 11C is a region where a cathode pad CaP is arranged.

[0056] The gate pad region 11G is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the gate pad region 11G may be provided near the center of the first side surface 5A and face one or multiple active regions 6 in either or both of the first direction X and the second direction Y. In this embodiment, the gate pad region 11G faces the temperature measurement region 10 in the second direction Y.

[0057] The monitor pad region 11M is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the monitor pad region 11M is provided in a region on the fourth side surface 5D side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X. In this embodiment, the monitor pad region 11M faces the gate pad region 11G across a part of at least one active region 6 (in this embodiment, the third active region 6C).

[0058] The monitor pad region 11M is provided in a region on the first side surface 5A side of the monitor region 7, and faces the monitor region 7 in the second direction Y. The monitor pad region 11M faces one or more active regions 6 (third active region 6C in this embodiment) in the second direction Y, with the monitor region 7 in between.

[0059] The anode pad region 11A is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the anode pad region 11A is provided in a region on the third side surface 5C side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X. The anode pad region 11A may face one or multiple active regions 6 in the second direction Y.

[0060] The cathode pad region 11C is provided in a region on the first side surface 5A side of the multiple active regions 6. Specifically, the cathode pad region 11C is provided in a region on the third side surface 5C side of the gate pad region 11G, and faces the gate pad region 11G in the first direction X.

[0061] More specifically, the cathode pad region 11C is interposed in a region between the gate pad region 11G and the anode pad region 11A, and faces both the gate pad region 11G and the anode pad region 11A in the first direction X. The cathode pad region 11C may face one or more active regions 6 in the second direction Y.

[0062] The semiconductor device 1A includes an n-type drift region 12 formed inside the chip 2. The drift region 12 may also be referred to as a "semiconductor region." The drift region 12 is formed throughout the thickness range between the first main surface 3 and the second main surface 4, and extends in a layered form along the first main surface 3 (second main surface 4).

[0063] In this embodiment, drift region 12 is formed throughout the interior of chip 2 and is exposed from first main surface 3 and first to fourth side surfaces 5A to 5D. In this embodiment, chip 2 is made of an n-type semiconductor substrate (n-type chip 2), and drift region 12 is formed using n-type chip 2.

[0064] The semiconductor device 1A includes an n-type buffer region 13 formed in a surface layer portion of the second main surface 4. The buffer region 13 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. In this embodiment, the buffer region 13 is formed in a layer shape extending along the second main surface 4 over the entire area of ​​the second main surface 4, and is exposed from the first to fourth side surfaces 5A to 5D. The presence or absence of the buffer region 13 is optional, and a configuration without the buffer region 13 may also be employed.

[0065] The semiconductor device 1A includes a p-type collector region 14 formed in a surface layer portion of the second main surface 4. The collector region 14 forms the collector of the main transistor structure T1 (transistor structure T3). The collector region 14 is formed in a region on the second main surface 4 side of the buffer region 13. The collector region 14 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, and converts the conductivity type of the drift region 12 from n-type to p-type.

[0066] Collector region 14 has a p-type impurity concentration higher than the n-type impurity concentration of buffer region 13, thereby converting the conductivity type of buffer region 13 from n-type to p-type. In this embodiment, collector region 14 is formed in a layer shape extending along second main surface 4 over the entire area of ​​second main surface 4, and is exposed from second main surface 4 and first to fourth side surfaces 5A to 5D.

[0067] The following describes the configuration of the active regions 6, the monitor region 7, the peripheral region 8, the street regions 9, the temperature detection region 10, and the pad regions 11. The semiconductor device 1A includes a plurality of transistor structures T3 formed in the active regions 6, respectively.

[0068] The plurality of transistor structures T3 are connected in parallel to each other to form one main transistor structure T1. Since the plurality of transistor structures T3 have the same configuration, the following describes the configuration of one transistor structure T3 as one component of the semiconductor device 1A.

[0069] The transistor structure T3 includes a p-type base region 15 formed in a surface layer portion of the first main surface 3 of the corresponding active region 6. The base region 15 may also be referred to as a "body region," a "channel region," or the like. The base region 15 is formed in a surface layer portion of the drift region 12. In this embodiment, the base region 15 has a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, thereby converting the conductivity type of the drift region 12 from n-type to p-type.

[0070] The base regions 15 are each formed in a layer shape extending along the first main surface 3 in the corresponding active region 6. The base regions 15 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with the drift region 12 sandwiched therebetween.

[0071] The transistor structure T3 includes a plurality of trench electrode type gate structures 20 formed on the first main surface 3 of the corresponding active region 6. The plurality of gate structures 20 form the gate of the main transistor structure T1 (transistor structure T3). The gate structures 20 may also be referred to as "first trench structures," "trench gate structures," etc. A gate potential is applied to the gate structures 20.

[0072] The multiple gate structures 20 each extend in a strip shape in the first direction X and are arranged at intervals in the second direction Y. That is, the multiple gate structures 20 are arranged in a stripe shape extending in the first direction X. Each of the multiple gate structures 20 has one end on one side (the third side surface 5C side) and the other end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X).

[0073] The multiple gate structures 20 may each have a width that is less than the width of the multiple street regions 9. The width of the gate structure 20 is the width in a direction (second direction Y) perpendicular to the extension direction of the gate structure 20 (first direction X).

[0074] The width of the gate structure 20 may be 0.5 μm or more and 5 μm or less. The width of the gate structure 20 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the gate structure 20 is preferably 1 μm or more and 2.5 μm or less.

[0075] The plurality of gate structures 20 penetrates the base region 15 to reach the drift region 12. The plurality of gate structures 20 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with part of the drift region 12 sandwiched therebetween in the thickness direction.

[0076] The plurality of gate structures 20 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of gate structures 20 may be formed substantially perpendicular to the first main surface 3. The plurality of gate structures 20 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of gate structures 20 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of gate structures 20 may be formed in a curved shape.

[0077] The plurality of gate structures 20 may each have a depth of 1 μm to 10 μm. The depth of the gate structure 20 may have a value belonging to at least one of the ranges of 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, and 8 μm to 10 μm. The depth of the gate structure 20 is preferably 4 μm to 8 μm.

[0078] Each of the plurality of gate structures 20 includes a gate trench 21, a gate insulating film 22, and a buried gate electrode 23. The gate trench 21 is formed in the first main surface 3, and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 20.

[0079] The gate insulating film 22 covers the wall surface of the gate trench 21. The gate insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 22 include a silicon oxide film made of an oxide of the chip 2.

[0080] The gate insulating film 22 may have a thickness of 10 nm or more and 200 nm or less. The thickness of the gate insulating film 22 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the gate insulating film 22 is preferably 100 nm or more and 150 nm or less.

[0081] The buried gate electrode 23 is buried in the gate trench 21 with the gate insulating film 22 sandwiched therebetween. The buried gate electrode 23 faces the drift region 12 and the base region 15 with the gate insulating film 22 sandwiched therebetween. An electrode surface of the buried gate electrode 23 may be located on the bottom wall side of the gate trench 21 with respect to the first main surface 3. The buried gate electrode 23 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0082] The transistor structure T3 includes a plurality of trench electrode type gate connection structures 25 formed on the first main surface 3 so as to be connected to the plurality of gate structures 20 in the corresponding active regions 6. A gate potential is applied to the plurality of gate connection structures 25. The gate connection structures 25 may also be referred to as "first trench connection structures," "trench gate connection structures," etc.

[0083] The plurality of gate connection structures 25 are respectively arranged on both end sides of the plurality of gate structures 20 in the first direction X so as to be connected to one end and the other end of the plurality of gate structures 20, and together with the outermost plurality of gate structures 20, define corresponding active regions 6.

[0084] The multiple gate connection structures 25 include a gate connection structure 25 on one end side of the multiple gate structures 20 and a gate connection structure 25 on the other end side of the multiple gate structures 20. The gate connection structure 25 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple gate structures 20. The gate connection structure 25 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple gate structures 20.

[0085] The plurality of gate connection structures 25 may each have a width approximately equal to the width of the gate structure 20. Of course, the width of the gate connection structure 25 may be larger or smaller than the width of the gate structure 20.

[0086] The width of the gate connection structure 25 may be 0.5 μm or more and 5 μm or less. The width of the gate connection structure 25 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the gate connection structure 25 is preferably 1 μm or more and 2.5 μm or less.

[0087] The plurality of gate connection structures 25 penetrate the base region 15 to reach the drift region 12. The plurality of gate connection structures 25 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 across a part of the drift region 12 in the thickness direction.

[0088] The plurality of gate connection structures 25 may be formed in a tapered shape toward their bottom walls. Of course, the plurality of gate connection structures 25 may be formed substantially perpendicular to the first main surface 3. The plurality of gate connection structures 25 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of gate connection structures 25 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of gate connection structures 25 may be formed in a curved shape.

[0089] The plurality of gate connection structures 25 may each have a depth approximately equal to the depth of the gate structure 20. Of course, the depth of the gate connection structures 25 may be greater than or less than the depth of the gate structure 20.

[0090] The depth of the plurality of gate connection structures 25 may be 0.5 μm or more and 10 μm or less. The depth of the gate connection structures 25 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the gate connection structures 25 is preferably 4 μm or more and 8 μm or less.

[0091] Each of the plurality of gate connection structures 25 includes a gate connection trench 26, a gate connection insulating film 27, and a gate connection buried electrode 28. The gate connection trench 26 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the gate connection structure 25. The gate connection trench 26 communicates with the plurality of gate trenches 21.

[0092] The gate connection insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The gate connection insulating film 27 preferably includes the same type of insulator as the gate insulating film 22. In this embodiment, the gate connection insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate connection insulating film 27 includes a silicon oxide film made of an oxide of the chip 2.

[0093] The gate connection insulating film 27 covers the wall surface of the gate connection trench 26 in a film form. The gate connection insulating film 27 is connected to the gate insulating film 22 at the communicating portion between the gate trench 21 and the gate connection trench 26.

[0094] The gate connection insulating film 27 may have a thickness substantially equal to that of the gate insulating film 22. Of course, the thickness of the gate connection insulating film 27 may be greater than or less than that of the gate insulating film 22.

[0095] The thickness of the gate connection insulating film 27 may be 10 nm or more and 200 nm or less. The thickness of the gate connection insulating film 27 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the gate connection insulating film 27 is preferably 100 nm or more and 150 nm or less.

[0096] The gate connection buried electrode 28 is buried in the gate connection trench 26 with the gate connection insulating film 27 sandwiched therebetween. The gate connection buried electrode 28 is connected to the gate buried electrode 23 at the communicating portion between the gate trench 21 and the gate connection trench 26. The gate connection buried electrode 28 faces the drift region 12 and the base region 15 with the gate connection insulating film 27 sandwiched therebetween.

[0097] The electrode surface of the gate connection buried electrode 28 may be located on the bottom wall side of the gate connection trench 26 with respect to the first main surface 3. The gate connection buried electrode 28 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate connection buried electrode 28 preferably includes the same type of conductor as the gate buried electrode 23.

[0098] The transistor structure T3 includes a plurality of trench electrode type emitter structures 30 formed on the first main surface 3 in the corresponding active regions 6. The emitter structures 30 may also be referred to as "second trench structures," "trench emitter structures," etc. A potential (emitter potential in this form) different from the gate potential is applied to the emitter structures 30.

[0099] In this embodiment, at least two emitter structures 30 are disposed in the regions between adjacent pairs of gate structures 20. Specifically, the multiple emitter structures 30 are formed in mesa regions defined by a pair of gate structures 20 and a pair of gate connection structures 25.

[0100] The plurality of emitter structures 30 extend in a strip shape in the first direction X following the extension direction of the plurality of gate structures 20 , and are formed at intervals in the second direction Y from the plurality of gate connection structures 25 .

[0101] The plurality of emitter structures 30 each have a length in the longitudinal direction (first direction X) that is shorter than the length of the plurality of gate structures 20. The plurality of emitter structures 30 each have one end on one side (the third side surface 5C side) and another end on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X).

[0102] The multiple emitter structures 30 may each have a width that is less than the width of the multiple street regions 9. The width of the emitter structure 30 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the emitter structure 30. The width of the emitter structure 30 may be approximately equal to the width of the gate structure 20. Of course, the width of the emitter structure 30 may be greater than or smaller than the width of the gate structure 20.

[0103] The width of the emitter structure 30 may be 0.5 μm or more and 5 μm or less. The width of the emitter structure 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the emitter structure 30 is preferably 1 μm or more and 2.5 μm or less.

[0104] The plurality of emitter structures 30 penetrate the base region 15 to reach the drift region 12. The plurality of emitter structures 30 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with part of the drift region 12 sandwiched therebetween in the thickness direction.

[0105] The plurality of emitter structures 30 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of emitter structures 30 may be formed substantially perpendicular to the first main surface 3. The plurality of emitter structures 30 may have bottom walls formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of emitter structures 30 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of emitter structures 30 may be formed in a curved shape.

[0106] The emitter structure 30 may have a depth that is approximately equal to the depth of the gate structure 20. Of course, the depth of the emitter structure 30 may be greater than or less than the depth of the gate structure 20.

[0107] The depth of the plurality of emitter structures 30 may be 0.5 μm or more and 10 μm or less. The depth of the emitter structures 30 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the emitter structures 30 is preferably 4 μm or more and 8 μm or less.

[0108] The first trench pitch between the central portion of the gate structure 20 and the central portion of the emitter structure 30 may be 1 μm or more and 5 μm or less. The first trench pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first trench pitch is preferably 1.5 μm or more and 3.5 μm or less.

[0109] Each of the plurality of emitter structures 30 includes an emitter trench 31, an emitter insulating film 32, and a buried emitter electrode 33. The emitter trench 31 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the emitter structure 30.

[0110] The emitter insulating film 32 covers the wall surface of the emitter trench 31. The emitter insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The emitter insulating film 32 preferably includes the same type of insulator as the gate insulating film 22. In this embodiment, the emitter insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the emitter insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.

[0111] The emitter insulating film 32 may have a thickness approximately equal to that of the gate insulating film 22. Of course, the thickness of the emitter insulating film 32 may be greater than or less than that of the gate insulating film 22.

[0112] The emitter insulating film 32 may have a thickness of 10 nm to 200 nm. The thickness of the emitter insulating film 32 may be a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm. The thickness of the emitter insulating film 32 is preferably 100 nm to 150 nm.

[0113] The buried emitter electrode 33 is buried in the emitter trench 31 with the emitter insulating film 32 interposed therebetween. The buried emitter electrode 33 faces the drift region 12 and the base region 15 with the emitter insulating film 32 interposed therebetween.

[0114] The electrode surface of the buried emitter electrode 33 may be located on the bottom wall side of the emitter trench 31 with respect to the first main surface 3. The buried emitter electrode 33 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried emitter electrode 33 preferably includes the same type of conductor as the buried gate electrode 23.

[0115] The transistor structure T3 includes a plurality of emitter connection structures 35 formed on the first main surface 3 so as to be connected to the plurality of emitter structures 30 in the corresponding active regions 6. An emitter potential is applied to the plurality of emitter connection structures 35. The emitter connection structures 35 may also be referred to as "second trench connection structures," "trench emitter connection structures," etc.

[0116] The plurality of emitter connection structures 35 are arranged on both end sides of the plurality of emitter structures 30 in the first direction X so as to be connected to one end and the other end of the plurality of emitter structures 30 .

[0117] The multiple emitter connection structures 35 include an emitter connection structure 35 on one end side of the multiple emitter structures 30 and an emitter connection structure 35 on the other end side of the multiple emitter structures 30. The emitter connection structure 35 on the one end side extends in a strip shape in the second direction Y and is connected to one end of the multiple adjacent emitter structures 30. The emitter connection structure 35 on the other end side extends in a strip shape in the second direction Y and is connected to the other end of the multiple adjacent emitter structures 30.

[0118] The plurality of emitter connection structures 35 penetrate the base region 15 to reach the drift region 12. The plurality of emitter connection structures 35 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3, and face the buffer region 13 and the collector region 14 with part of the drift region 12 sandwiched therebetween in the thickness direction.

[0119] The plurality of emitter connection structures 35 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of emitter connection structures 35 may be formed substantially perpendicular to the first main surface 3.

[0120] The plurality of emitter connection structures 35 may have bottom walls that are curved toward the second main surface 4. Of course, the bottom walls of the plurality of emitter connection structures 35 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of emitter connection structures 35 may be formed in a curved shape.

[0121] The plurality of emitter connection structures 35 may each have a width approximately equal to the width of the emitter structure 30 (gate structure 20). Of course, the width of the emitter connection structure 35 may be greater than or smaller than the width of the emitter structure 30.

[0122] The width of the emitter connection structure 35 may be 0.5 μm or more and 5 μm or less. The width of the emitter connection structure 35 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the emitter connection structure 35 is preferably 1 μm or more and 2.5 μm or less.

[0123] The plurality of emitter connection structures 35 may each have a depth approximately equal to the depth of the emitter structure 30 (gate structure 20). Of course, the depth of the emitter connection structure 35 may be greater than or less than the depth of the emitter structure 30.

[0124] The depth of the emitter connection structure 35 may be 0.5 μm or more and 10 μm or less. The depth of the emitter connection structure 35 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the emitter connection structure 35 is preferably 4 μm or more and 8 μm or less.

[0125] Each of the plurality of emitter connection structures 35 includes an emitter connection trench 36, an emitter connection insulating film 37, and an emitter connection buried electrode 38. The emitter connection trench 36 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the emitter connection structure 35. The emitter connection trench 36 communicates with the plurality of emitter trenches 31.

[0126] The emitter connection insulating film 37 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The emitter connection insulating film 37 preferably includes the same type of insulator as the emitter insulating film 32 (gate insulating film 22). In this embodiment, the emitter connection insulating film 37 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the emitter connection insulating film 37 includes a silicon oxide film made of an oxide of the chip 2.

[0127] The emitter connection insulating film 37 covers the wall surface of the emitter connection trench 36 in a film form. The emitter connection insulating film 37 is connected to the emitter insulating film 32 at the communicating portion between the emitter trench 31 and the emitter connection trench 36.

[0128] The emitter connection insulating film 37 may have a thickness substantially equal to that of the emitter insulating film 32 (gate insulating film 22). Of course, the thickness of the emitter connection insulating film 37 may be greater than or less than the thickness of the emitter insulating film 32 (gate insulating film 22).

[0129] The emitter connection insulating film 37 may have a thickness of 10 nm to 200 nm. The thickness of the emitter connection insulating film 37 may be a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm. The thickness of the emitter connection insulating film 37 is preferably 100 nm to 150 nm.

[0130] The emitter connection buried electrode 38 is buried in the emitter connection trench 36 with the emitter connection insulating film 37 interposed therebetween. The emitter connection buried electrode 38 is connected to the emitter buried electrode 33 at the communicating portion between the emitter trench 31 and the emitter connection trench 36. The emitter connection buried electrode 38 faces the drift region 12 and the base region 15 with the emitter connection insulating film 37 interposed therebetween.

[0131] The electrode surface of the emitter-connection buried electrode 38 may be located closer to the bottom wall of the emitter-connection trench 36 than the first main surface 3. The emitter-connection buried electrode 38 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The emitter-connection buried electrode 38 preferably includes the same type of conductor as the emitter-connection buried electrode 33 (gate buried electrode 23).

[0132] The transistor structure T3 includes a plurality of n-type emitter regions 40 (impurity regions) formed in the surface layer portion of the first main surface 3 of the corresponding active region 6. The plurality of emitter regions 40 form the emitters of the main transistor structure T1.

[0133] The emitter region 40 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 12. In this embodiment, the emitter region 40 has an n-type impurity concentration higher than the p-type impurity concentration of the base region 15, thereby converting the conductivity type of the base region 15 from p-type to n-type.

[0134] The plurality of emitter regions 40 are formed in the surface layer portion of the base region 15 on both sides of the plurality of gate structures 20, and extend in a strip shape in the first direction X following the extension direction of the plurality of gate structures 20. The plurality of emitter regions 40 are formed at intervals from the bottom of the base region 15 toward the first main surface 3.

[0135] The plurality of emitter regions 40 face the buried gate electrodes 23 of the corresponding gate structures 20, with the gate insulating films 22 of the corresponding gate structures 20 interposed therebetween. The plurality of emitter regions 40 may face the buried emitter electrodes 33 of the corresponding emitter structures 30, with the emitter insulating films 32 of the corresponding emitter structures 30 interposed therebetween. Of course, the plurality of emitter regions 40 may be formed at intervals from the plurality of emitter structures 30.

[0136] The transistor structure T3 includes a plurality of p-type contact regions 41 formed in regions different from the plurality of emitter regions 40 in the surface layer portion of the base region 15. The plurality of contact regions 41 have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. The plurality of contact regions 41 are formed on both sides of the plurality of gate structures 20 at intervals from the plurality of gate structures 20 and the plurality of emitter structures 30.

[0137] The plurality of contact regions 41 are formed in regions on the bottom side of the base region 15 relative to the plurality of emitter regions 40. The plurality of contact regions 41 are formed at intervals from the bottom of the base region 15 toward the first main surface 3. The plurality of contact regions 41 each extend in a strip shape in the first direction X following the extension direction of the plurality of gate structures 20.

[0138] The transistor structure T3 includes a plurality of n-type storage regions 42 formed in a surface layer portion of the first main surface 3 of the corresponding active region 6. The storage regions 42 may be referred to as "carrier storage regions." The plurality of storage regions 42 have a higher n-type impurity concentration than the n-type impurity concentration of the drift region 12. The n-type impurity concentration of the plurality of storage regions 42 may be lower than the n-type impurity concentration of the emitter region 40.

[0139] The storage regions 42 are formed in regions immediately below the base region 15 on both sides of the gate structures 20, and face the emitter regions 40 corresponding to them in the thickness direction. The storage regions 42 extend in a strip shape in the first direction X, following the extension direction of the gate structures 20.

[0140] The plurality of storage regions 42 are formed in a thickness range between the bottom of the base region 15 and the bottom wall of the gate structure 20. The plurality of storage regions 42 are formed at intervals from the depth position of the bottom wall of the gate structure 20 to the bottom side of the base region 15.

[0141] The bottoms of the plurality of storage regions 42 may be located closer to the first main surface 3 than the depth position of the intermediate portion of the gate structure 20. The bottoms of the plurality of storage regions 42 may be located closer to the bottom wall of the gate structure 20 than the depth position of the intermediate portion of the gate structure 20.

[0142] The transistor structure T3 includes a plurality of p-type well regions 43 formed in the surface layer portion of the first main surface 3 in the corresponding active region 6. The plurality of well regions 43 have a p-type impurity concentration lower than the p-type impurity concentration of the contact region 41.

[0143] The multiple well regions 43 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the multiple well regions 43 may be lower than the p-type impurity concentration of the base region 15. In this embodiment, the multiple well regions 43 are formed in an electrically floating state.

[0144] The multiple well regions 43 are formed in regions between adjacent pairs of emitter structures 30. Specifically, the multiple well regions 43 are formed in mesa regions defined by the multiple emitter structures 30 and the multiple emitter connection structures 35.

[0145] The plurality of well regions 43 each have a bottom located closer to the bottom wall of the plurality of emitter structures 30 than the depth position of the bottom of the base region 15. The bottoms of the plurality of well regions 43 are located closer to the bottom wall of the plurality of emitter structures 30 than the depth positions of the intermediate portions of the plurality of emitter structures 30. In this embodiment, the bottoms of the plurality of well regions 43 are located closer to the second main surface 4 than the bottom walls of the plurality of emitter structures 30.

[0146] The multiple well regions 43 may have portions (bottoms) covering the bottom walls of the multiple emitter structures 30 and the bottom walls of the multiple emitter connection structures 35. The multiple well regions 43 each extend in a strip shape in the first direction X following the extension direction of the emitter structures 30, and are connected to the multiple emitter structures 30 and the multiple emitter connection structures 35.

[0147] The multiple well regions 43, together with the multiple emitter structures 30, form an IE (Injection Enhanced) structure. The IE structure restricts the movement path of holes flowing into the base region 15, causing the holes to accumulate in the region directly below the base region 15. In other words, the IE structure promotes low on-resistance and low on-voltage from inside the chip 2.

[0148] 7 , semiconductor device 1A includes a p-type peripheral well region 44 formed in the surface layer portion of first main surface 3 in peripheral region 8. Peripheral well region 44 has a p-type impurity concentration lower than the p-type impurity concentration of contact region 41. Peripheral well region 44 may have a p-type impurity concentration higher than the p-type impurity concentration of base region 15. Of course, the p-type impurity concentration of peripheral well region 44 may be lower than the p-type impurity concentration of base region 15.

[0149] The p-type impurity concentration of the peripheral well region 44 may be approximately equal to the p-type impurity concentration of the well region 43. Of course, the p-type impurity concentration of the peripheral well region 44 may be higher than the p-type impurity concentration of the well region 43, or may be lower than the p-type impurity concentration of the well region 43.

[0150] The peripheral well region 44 is formed at a distance inward from the periphery of the first main surface 3, and extends in a band shape along the periphery of the first main surface 3. In this embodiment, the peripheral well region 44 is formed in an annular shape surrounding the multiple active regions 6.

[0151] The peripheral well region 44 is formed deeper than the base region 15 and is in contact with the outermost gate connection structure 25. The peripheral well region 44 is formed deeper than the outermost gate connection structure 25 and has a portion that runs along the bottom wall of the outermost gate connection structure 25. In this embodiment, the peripheral well region 44 is drawn from outside the plurality of active regions 6 into the plurality of active regions 6 and has a portion that covers the bottom walls of the plurality of gate structures 20.

[0152] The peripheral well region 44 extends in the vertical direction Z along the sidewalls of the gate structures 20 and the sidewalls of the gate connection structures 25 in the active regions 6, and is connected to the base regions 15 in the surface layer portion of the first main surface 3. An emitter potential is applied to the peripheral well region 44 via the base regions 15.

[0153] The depth of the peripheral well region 44 may be approximately equal to the depth of the multiple well regions 43. Of course, the depth of the peripheral well region 44 may be greater than the depth of the multiple well regions 43, or may be smaller than the depth of the multiple well regions 43.

[0154] 8 , the semiconductor device 1A includes a plurality of p-type street well regions 45 formed in the surface layer portion of the first main surface 3 in the plurality of street regions 9. One street well region 45 has a portion formed in the surface layer portion of the first main surface 3 in the temperature detection region 10.

[0155] The street well region 45 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the street well region 45 may be lower than the p-type impurity concentration of the base region 15.

[0156] The p-type impurity concentration of the street well region 45 may be approximately equal to the p-type impurity concentration of the well region 43. Of course, the p-type impurity concentration of the street well region 45 may be higher than the p-type impurity concentration of the well region 43, or may be lower than the p-type impurity concentration of the well region 43.

[0157] The p-type impurity concentration of the street well region 45 may be approximately equal to the p-type impurity concentration of the peripheral well region 44. Of course, the p-type impurity concentration of the street well region 45 may be higher than the p-type impurity concentration of the peripheral well region 44, or may be lower than the p-type impurity concentration of the peripheral well region 44.

[0158] The plurality of street well regions 45 are formed in layers extending along the first main surface 3 in a region between the gate connection structure 25 on one active region 6 side and the gate connection structure 25 on the other active region 6 side, and are exposed from the first main surface 3. The plurality of street well regions 45 each extend in a strip shape in the second direction Y following the extension direction of the plurality of street regions 9. The plurality of street well regions 45 are connected to the peripheral well region 44 in the peripheral region 8.

[0159] The plurality of street well regions 45 are formed deeper than the plurality of base regions 15 and are in contact with the plurality of gate connection structures 25. Specifically, the plurality of street well regions 45 are formed deeper than the plurality of gate connection structures 25 and have portions along the bottom walls of the plurality of gate connection structures 25.

[0160] In this form, the plurality of street well regions 45 have widths greater than the widths of the corresponding street regions 9, extend from the corresponding street regions 9 into the plurality of active regions 6, and have portions covering the bottom walls of the plurality of gate structures 20.

[0161] The plurality of street well regions 45 extend in the vertical direction Z along the sidewalls of the plurality of gate structures 20 and the sidewalls of the plurality of gate connection structures 25 in the plurality of active regions 6, and are connected to the plurality of base regions 15 in the surface layer portion of the first main surface 3. An emitter potential is applied to the plurality of street well regions 45 via the plurality of base regions 15.

[0162] The depth of the plurality of street well regions 45 may be approximately equal to the depth of the plurality of well regions 43. Of course, the depth of the plurality of street well regions 45 may be greater than the depth of the plurality of well regions 43 or may be smaller than the depth of the plurality of street well regions 45.

[0163] The depth of the plurality of street well regions 45 may be approximately equal to the depth of the periphery well region 44. Of course, the depth of the plurality of street well regions 45 may be greater than the depth of the periphery well region 44 or may be less than the depth of the periphery well region 44.

[0164] Fig. 9 is an enlarged plan view showing a main part of the monitor area 7. Fig. 10 is a cross-sectional view taken along line XX in Fig. 9. Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 9.

[0165] 9 to 11 , semiconductor device 1A includes a monitor transistor structure T2 in monitor region 7. Similar to transistor structure T3 (active region 6), monitor transistor structure T2 (monitor region 7) includes a base region 15, a plurality of gate structures 20, a plurality of gate connection structures 25, a plurality of emitter structures 30, a plurality of emitter connection structures 35, a plurality of emitter regions 40, a contact region 41, a plurality of storage regions 42, and a plurality of well regions 43.

[0166] The base region 15, gate structure 20, gate connection structure 25, emitter structure 30, emitter connection structure 35, emitter region 40, contact region 41, storage region 42 and well region 43 of the monitor region 7 may be referred to as the "monitor base region (15)", "monitor gate structure (20)", "monitor gate connection structure (25)", "monitor emitter structure (30)", "monitor emitter connection structure (35)", "monitor emitter region (40)", "monitor contact region (41)", "monitor storage region (42)" and "monitor well region (43)", respectively.

[0167] These components in the monitor region 7 have a layout similar to that of the corresponding components in the active region 6. The description of the corresponding components in the active region 6 also applies to the description of these components in the monitor region 7. These components in the monitor region 7 are laid out in a plane area smaller than the total plane area of ​​the multiple active regions 6.

[0168] In other words, since the channel area of ​​the monitor region 7 (the total area of ​​the emitter region 40) is smaller than the channel area of ​​the active region 6 (the total area of ​​the emitter region 40), the monitor current Im of the monitor transistor structure T2 is less than the output current Ice of the main transistor structure T1 (transistor structure T3).

[0169] The semiconductor device 1A includes a main surface insulating film 48 that selectively covers the first main surface 3. The main surface insulating film 48 may be referred to as an "insulating film," a "first dielectric film," or the like. The main surface insulating film 48 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0170] The main surface insulating film 48 preferably contains the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the main surface insulating film 48 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 48 contains a silicon oxide film made of an oxide of the chip 2.

[0171] The main surface insulating film 48 has a portion that selectively covers the multiple active regions 6, a portion that selectively covers the monitor region 7, a portion that selectively covers the peripheral region 8, and a portion that selectively covers the multiple street regions 9.

[0172] The main surface insulating film 48 covers the base regions 15, the emitter regions 40, and the well regions 43 in the active regions 6. The main surface insulating film 48 is connected to the gate insulating films 22, the gate connection insulating films 27, the emitter insulating films 32, and the emitter connection insulating films 37 in the active regions 6, and exposes the gate buried electrodes 23, the gate connection buried electrodes 28, the emitter buried electrodes 33, and the emitter connection buried electrodes 38.

[0173] The main surface insulating film 48 covers the plurality of base regions 15, the plurality of emitter regions 40, and the plurality of well regions 43 in the monitor region 7. The main surface insulating film 48 is connected to the plurality of gate insulating films 22, the plurality of gate connection insulating films 27, the plurality of emitter insulating films 32, and the plurality of emitter connection insulating films 37 in the monitor region 7, and exposes the plurality of gate buried electrodes 23, the plurality of gate connection buried electrodes 28, the plurality of emitter buried electrodes 33, and the plurality of emitter connection buried electrodes 38.

[0174] The main surface insulating film 48 covers the peripheral well region 44 in the peripheral region 8. The main surface insulating film 48 is connected to the plurality of gate connection insulating films 27 in the peripheral region 8, and exposes the plurality of gate connection buried electrodes 28. The main surface insulating film 48 may be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Of course, the main surface insulating film 48 may be formed at a distance inward from the periphery of the chip 2, and expose the drift region 12 from the periphery of the chip 2.

[0175] The main surface insulating film 48 covers the plurality of street well regions 45 in the plurality of street regions 9. The main surface insulating film 48 is connected to the plurality of gate connection insulating films 27 in the plurality of street regions 9, and exposes the plurality of gate connection buried electrodes 28.

[0176] The main surface insulating film 48 may have a thickness substantially equal to that of the gate insulating film 22 (gate connection insulating film 27). Of course, the thickness of the main surface insulating film 48 may be greater than or less than the thickness of the gate insulating film 22 (gate connection insulating film 27).

[0177] The thickness of the main surface insulating film 48 may be approximately equal to the thickness of the emitter insulating film 32 (emitter connection insulating film 37). Of course, the thickness of the main surface insulating film 48 may be greater than the thickness of the emitter insulating film 32 (emitter connection insulating film 37) or may be smaller than the thickness of the emitter insulating film 32 (emitter connection insulating film 37).

[0178] The thickness of the main surface insulating film 48 may be 10 nm or more and 200 nm or less. The thickness of the main surface insulating film 48 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the main surface insulating film 48 is preferably 100 nm or more and 150 nm or less.

[0179] Fig. 12 is an enlarged plan view showing the temperature measurement region 10. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 12. With reference to Figs. 12 and 13, the semiconductor device 1A includes a temperature sensing diode structure D arranged on the main surface insulating film 48 in the temperature measurement region 10. The configuration of the temperature sensing diode structure D as one component of the semiconductor device 1A will be described below.

[0180] The temperature sensitive diode structure D includes one or more (multiple in this embodiment) polysilicon layers 50 disposed on the main surface insulating film 48. The number of polysilicon layers 50 is arbitrary and is adjusted as appropriate depending on the number of first diodes D1 and the number of second diodes D2.

[0181] In this embodiment, the semiconductor device 1A includes four polysilicon layers 50 for the first diode D1 and four polysilicon layers 50 for the second diode D2. In this embodiment, the multiple polysilicon layers 50 are arranged in a matrix of 4 rows and 2 columns with intervals in the first direction X and the second direction Y.

[0182] In this embodiment, four polysilicon layers 50 for the first diode D1 are arranged in a row in a first column (one side in the second direction Y), and four polysilicon layers 50 for the second diode D2 are arranged in a row in a second column (the other side in the second direction Y).

[0183] The multiple polysilicon layers 50 are disposed directly on the main surface insulating film 48 and face the street well region 45 across the main surface insulating film 48. In this embodiment, the multiple polysilicon layers 50 are formed in a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view. The multiple polysilicon layers 50 may also be formed in a rectangular, hexagonal, circular, or other shape in a plan view.

[0184] The multiple polysilicon layers 50 have a thickness greater than the thickness of the main surface insulating film 48. The thickness of the multiple polysilicon layers 50 may be less than the depth (thickness) of the street well region 45. The thickness of the multiple polysilicon layers 50 may be less than the depth of the gate structure 20 (emitter structure 30). The thickness of the multiple polysilicon layers 50 may be less than the depth of the gate connection structure 25 (emitter connection structure 35).

[0185] The thickness of the multiple polysilicon layers 50 may be 0.1 μm or more and 2 μm or less. The thickness of the polysilicon layer 50 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the polysilicon layer 50 is preferably 0.25 μm or more and 1.25 μm or less.

[0186] The temperature sensitive diode structure D includes a plurality of p-type anode regions 51 formed in each of a plurality of polysilicon layers 50. The anode regions 51 are formed in the inner portion (preferably the central portion) of the corresponding polysilicon layer 50 at intervals from the periphery of the corresponding polysilicon layer 50.

[0187] The plurality of anode regions 51 are formed in a polygonal or circular shape in plan view. The plurality of anode regions 51 may also be formed in a quadrangular, hexagonal, or other shape in plan view. The plurality of anode regions 51 are formed throughout the thickness range of the corresponding polysilicon layer 50.

[0188] The temperature sensitive diode structure D includes a plurality of n-type cathode regions 52 formed in a plurality of polysilicon layers 50. The plurality of cathode regions 52 are formed in the peripheral portions of the corresponding polysilicon layers 50, respectively.

[0189] In plan view, the plurality of cathode regions 52 each extend in a band shape along the periphery of the corresponding anode region 51. In this embodiment, the plurality of cathode regions 52 each extend in an annular shape along the periphery of the corresponding polysilicon layer 50 in plan view, and are each electrically connected to the corresponding anode region 51 over the entire periphery.

[0190] The plurality of cathode regions 52 are formed throughout the thickness range of the corresponding polysilicon layer 50, and are exposed from the sidewalls of the corresponding polysilicon layer 50. The plurality of cathode regions 52 and the corresponding anode regions 51 form pn junctions as the first diode D1 or pn junctions as the second diode D2, respectively.

[0191] 1 to 11 , the semiconductor device 1A includes a plurality of emitter interconnections 55 that are electrically connected to corresponding emitter connection structures 35 on the first main surface 3 in the plurality of active regions 6 and the monitor region 7.

[0192] The plurality of emitter wirings 55 are respectively disposed on the main surface insulating film 48 and connected to the corresponding emitter connection structures 35. In this embodiment, the plurality of emitter wirings 55 are respectively formed integrally with the corresponding emitter connection buried electrodes 38, and each comprises an extension portion that is extended from the corresponding emitter connection buried electrode 38 onto the main surface insulating film 48.

[0193] That is, the plurality of emitter wirings 55 are each made of the same type of conductor (either p-type conductive polysilicon or n-type conductive polysilicon, or both) as the emitter connection buried electrode 38. The plurality of emitter wirings 55 are formed at intervals from the plurality of gate connection structures 25 toward the corresponding emitter connection structures 35, and face the base region 15 in the thickness direction with the main surface insulating film 48 sandwiched therebetween.

[0194] The plurality of emitter interconnections 55 have a thickness greater than the thickness of the main surface insulating film 48. The thickness of the plurality of emitter interconnections 55 may be less than the depth (thickness) of the well region 43. The thickness of the plurality of emitter interconnections 55 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the plurality of emitter interconnections 55 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0195] The thickness of the plurality of emitter wirings 55 may be approximately equal to the thickness of the plurality of polysilicon layers 50. Of course, the thickness of the plurality of emitter wirings 55 may be greater than the thickness of the plurality of polysilicon layers 50 or may be smaller than the thickness of the plurality of polysilicon layers 50.

[0196] The thickness of the plurality of emitter interconnections 55 may be 0.1 μm or more and 2 μm or less. The thickness of the emitter interconnections 55 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the emitter interconnections 55 is preferably 0.25 μm or more and 1.25 μm or less.

[0197] The semiconductor device 1A includes a plurality of gate wirings 56 electrically connected to corresponding gate connection structures 25 on the first main surface 3 in the periphery region 8 and a plurality of street regions 9 .

[0198] The plurality of gate wirings 56 are respectively disposed on the main surface insulating film 48 and connected to the corresponding gate connection structures 25. In this embodiment, the plurality of gate wirings 56 are respectively formed integrally with the corresponding gate connection buried electrodes 28, and each comprises an extension portion that is extended from the corresponding gate connection buried electrode 28 onto the main surface insulating film 48.

[0199] That is, each of the plurality of gate wirings 56 is made of the same type of conductor as the gate connection buried electrode 28 (either p-type conductive polysilicon or n-type conductive polysilicon, or both).

[0200] The multiple gate wirings 56 include one or more (multiple in this embodiment) first gate wirings 56A arranged in the peripheral region 8, and one or more (multiple in this embodiment) second gate wirings 56B arranged in the multiple street regions 9.

[0201] The plurality of first gate wirings 56A are arranged on the main surface insulating film 48 in the peripheral region 8, and are routed in strip-like fashion in the region between the gate pad region 11G and the corresponding gate connection structure 25 (gate connection buried electrode 28). The plurality of first gate wirings 56A are formed along the plurality of active regions 6, and each have a portion extending in the first direction X and a portion extending in the second direction Y.

[0202] The plurality of first gate wirings 56A face the peripheral well region 44 across the main surface insulating film 48. The plurality of first gate wirings 56A are drawn from above the main surface insulating film 48 onto the gate connection structure 25 (gate connection buried electrode 28) adjacent to the peripheral region 8, and are connected to the gate connection structure 25 (gate connection buried electrode 28). The plurality of first gate wirings 56A are electrically connected to the plurality of gate structures 20 via the gate connection structure 25 (gate connection buried electrode 28).

[0203] The multiple second gate wirings 56B are respectively arranged on the main surface insulating film 48 in the multiple street regions 9, and are routed in a strip-like manner in the region between the gate pad region 11G and the corresponding gate connection structure 25 (gate connection buried electrode 28).

[0204] The plurality of second gate wirings 56B each extend in a strip shape in the second direction Y following the extension direction of the plurality of street regions 9. One second gate wiring 56B is routed in the street region 9 so as to bypass the plurality of polysilicon layers 50 (temperature sensitive diode structures D).

[0205] The plurality of second gate wirings 56B are respectively connected to the gate connection structures 25 (gate connection buried electrodes 28) of one and the other active regions 6 adjacent to each other in the first direction X. In other words, the plurality of second gate wirings 56B are electrically connected to the plurality of gate structures 20 via the plurality of gate connection structures 25 (gate connection buried electrodes 28) that define the plurality of street regions 9.

[0206] At least one of the gate wirings 56 (one second gate wiring 56B in this embodiment) is connected to the gate connection structure 25 (gate connection buried electrode 28) in the monitor region 7. As a result, the gate structure 20 in the monitor region 7 is on / off controlled simultaneously with the gate structure 20 in the active region 6.

[0207] The gate wirings 56 have a thickness greater than that of the main surface insulating film 48. The thickness of the gate wirings 56 may be less than the depth (thickness) of the well region 43. The thickness of the gate wirings 56 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the gate wirings 56 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0208] The thickness of the plurality of gate wirings 56 may be approximately equal to the thickness of the plurality of polysilicon layers 50. Of course, the thickness of the plurality of gate wirings 56 may be greater than the thickness of the plurality of polysilicon layers 50 or may be smaller than the thickness of the plurality of polysilicon layers 50.

[0209] The thickness of the plurality of gate wirings 56 may be approximately equal to the thickness of the plurality of emitter wirings 55. Of course, the thickness of the plurality of gate wirings 56 may be greater than the thickness of the plurality of emitter wirings 55 or may be smaller than the thickness of the plurality of emitter wirings 55.

[0210] The thickness of the plurality of gate wirings 56 may be 0.1 μm or more and 2 μm or less. The thickness of the gate wirings 56 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the gate wirings 56 is preferably 0.25 μm or more and 1.25 μm or less.

[0211] The semiconductor device 1A includes an interlayer film 57 that selectively covers the main surface insulating film 48. The interlayer film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 57 may have a single-layer structure made of a single insulating film, or a layered structure including a plurality of insulating films.

[0212] The interlayer film 57 may include at least one of a non-doped silicate glass (NSG) film, a phosphorus silicate glass (PSG) film, and a boron phosphorus silicate glass (BPSG) film, which are examples of silicon oxide films.

[0213] The interlayer film 57 has a portion covering a plurality of active regions 6, a portion covering the monitor region 7, a portion covering the peripheral region 8, a portion covering a plurality of street regions 9, and a portion covering the temperature measurement region 10.

[0214] The interlayer film 57 covers the base regions 15, the emitter regions 40, and the well regions 43 with the main surface insulating film 48 sandwiched therebetween in the active regions 6 and the monitor region 7. The interlayer film 57 covers the gate structures 20, the gate connection structures 25, the emitter structures 30, and the emitter connection structures 35 in the active regions 6 and the monitor region 7.

[0215] Specifically, the interlayer film 57 covers the plurality of gate buried electrodes 23, the plurality of gate connection buried electrodes 28, the plurality of emitter buried electrodes 33, and the plurality of emitter connection buried electrodes 38. In this embodiment, the interlayer film 57 extends from above the main surface insulating film 48 into the plurality of gate trenches 21, the plurality of gate connection trenches 26, the plurality of emitter trenches 31, and the plurality of emitter connection trenches 36.

[0216] The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried gate electrodes 23 in the plurality of gate trenches 21. The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried gate connection electrodes 28 in the plurality of gate connection trenches 26.

[0217] The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried emitter electrodes 33 in the plurality of emitter trenches 31. The interlayer film 57 has portions that cover the electrode surfaces of the plurality of buried emitter electrodes 38 in the plurality of emitter connection trenches 36.

[0218] The interlayer film 57 covers the peripheral well region 44 in the peripheral region 8, sandwiching the main surface insulating film 48. The interlayer film 57 may be continuous with the peripheral edge (first to fourth side surfaces 5A to 5D) of the chip 2. Of course, the interlayer film 57 may be formed at a distance inward from the peripheral edge of the chip 2, exposing the drift region 12 from the peripheral portion of the chip 2.

[0219] The interlayer film 57 covers the street well regions 45 in the street regions 9 with the main surface insulating film 48 interposed therebetween. The interlayer film 57 covers the polysilicon layers 50 in the temperature detection region 10.

[0220] The interlayer film 57 fills the gaps between the polysilicon layers 50 and collectively covers the polysilicon layers 50. The interlayer film 57 contacts the main surface insulating film 48 at the gaps. That is, the interlayer film 57 faces the street well region 45 at the gaps, with the main surface insulating film 48 sandwiched therebetween.

[0221] The interlayer film 57 has a thickness greater than that of the main surface insulating film 48. The thickness of the interlayer film 57 may be less than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35). Of course, the thickness of the interlayer film 57 may be greater than the depth of the gate structure 20 (gate connection structure 25) and the depth of the emitter structure 30 (emitter connection structure 35).

[0222] The thickness of the interlayer film 57 is preferably greater than the thickness of the plurality of polysilicon layers 50. Of course, the thickness of the interlayer film 57 may be less than the thickness of the plurality of polysilicon layers 50. The thickness of the interlayer film 57 is preferably greater than the thickness of the plurality of emitter wirings 55.

[0223] Of course, the thickness of the interlayer film 57 may be smaller than the thickness of the plurality of emitter wirings 55. The thickness of the interlayer film 57 is preferably larger than the thickness of the plurality of gate wirings 56. Of course, the thickness of the interlayer film 57 may be smaller than the thickness of the plurality of gate wirings 56.

[0224] The interlayer film 57 may have a thickness of 0.1 μm or more and 3 μm or less. The thickness of the interlayer film 57 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The thickness of the interlayer film 57 is preferably 0.5 μm or more and 2 μm or less.

[0225] The semiconductor device 1A includes a plurality of first emitter openings 58 formed in an interlayer film 57 in the plurality of active regions 6 and the monitor region 7. The plurality of first emitter openings 58 are formed on both sides of the plurality of gate structures 20 at intervals from the plurality of gate structures 20, and penetrate the main surface insulating film 48 and the interlayer film 57 to expose the chip 2. Specifically, the plurality of first emitter openings 58 expose the corresponding emitter regions 40 and the corresponding contact regions 41, respectively.

[0226] The plurality of first emitter openings 58 are dug down from the height position of the first main surface 3 in the thickness direction of the chip 2, and each have a bottom wall located inside the chip 2. The bottom walls of the plurality of first emitter openings 58 are formed at intervals from the bottoms of the corresponding base regions 15 toward the first main surface 3, and each exposes the corresponding contact region 41. The bottom walls of the plurality of first emitter openings 58 are formed at intervals from the bottoms of the corresponding contact regions 41 toward the first main surface 3.

[0227] The plurality of first emitter openings 58 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of first emitter openings 58 may be formed substantially perpendicular to the first main surface 3.

[0228] The plurality of first emitter openings 58 may have bottom walls that are curved toward the second main surface 4. Of course, the plurality of first emitter openings 58 may be formed substantially parallel to the first main surface 3. In this case, the corners of the bottom walls of the plurality of first emitter openings 58 may be curved.

[0229] The multiple first emitter openings 58 each extend in a strip shape in the first direction X following the extension direction of the multiple gate structures 20. The multiple first emitter openings 58 each have a length in the longitudinal direction (first direction X) that is shorter than the length of the multiple gate structures 20. The length of the multiple first emitter openings 58 may be shorter than the length of the multiple emitter structures 30.

[0230] The semiconductor device 1A includes a plurality of first emitter via electrodes 59 respectively embedded in the plurality of first emitter openings 58. The plurality of first emitter via electrodes 59 are electrically connected to the corresponding emitter regions 40 and the corresponding contact regions 41 in the plurality of first emitter openings 58.

[0231] The plurality of first emitter via electrodes 59 may have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the wall surface side of the plurality of first emitter openings 58 .

[0232] The first electrode 60 is formed as a film on the wall surface of the first emitter opening 58 as a barrier electrode. The first electrode 60 is electrically connected to the emitter region 40 and the contact region 41 within the first emitter opening 58.

[0233] The first electrode 60 may have a single layer structure including a titanium film or a titanium nitride film. The first electrode 60 may have a layered structure including a titanium film and a titanium nitride film. In this case, the titanium nitride film may be layered on the titanium film.

[0234] The second electrode 61 is embedded in the first emitter opening 58 with the first electrode 60 sandwiched therebetween, and is electrically connected to the emitter region 40 and the contact region 41 via the first electrode 60. The second electrode 61 may include at least one of a tungsten film, a molybdenum film, a nickel film, a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The second electrode 61 preferably includes a tungsten film.

[0235] The semiconductor device 1A includes a plurality of second emitter openings 62 formed in the interlayer film 57 in the plurality of active regions 6 and the monitor region 7. The plurality of second emitter openings 62 penetrate the interlayer film 57 and expose the corresponding emitter interconnects 55. In this embodiment, the plurality of second emitter openings 62 are dug further downward from the interconnect surface of the corresponding emitter interconnects 55 toward the main surface insulating film 48, and each have a bottom wall located within the corresponding emitter interconnect 55.

[0236] The second emitter openings 62 may be formed in a tapered shape toward the bottom wall. Of course, the second emitter openings 62 may be formed substantially perpendicular to the first main surface 3. The second emitter openings 62 may be formed in a polygonal shape, a circular shape, or the like in a plan view. The second emitter openings 62 may be formed in a quadrangular shape or a hexagonal shape in a plan view.

[0237] The semiconductor device 1A includes a plurality of second emitter via electrodes 63 respectively embedded in the plurality of second emitter openings 62. The plurality of second emitter via electrodes 63 are mechanically and electrically connected to the corresponding emitter wirings 55 in the plurality of second emitter openings 62. Like the first emitter via electrode 59, the plurality of second emitter via electrodes 63 may have a stacked structure including a first electrode 60 and a second electrode 61.

[0238] The semiconductor device 1A includes the aforementioned emitter pad EP that collectively covers the multiple active regions 6 on the first main surface 3. The emitter pad EP is a terminal to which an emitter potential is applied from the outside. The emitter pad EP may also be called an "emitter pad electrode," an "emitter terminal electrode," an "emitter external terminal," or the like.

[0239] The emitter pad EP is disposed on a portion of the interlayer film 57 that covers the active regions 6. The emitter pad EP is electrically isolated from the gate structures 20 and the gate connection structures 25 by the interlayer film 57.

[0240] The emitter pad EP is mechanically and electrically connected to a plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63 on the interlayer film 57, and is electrically connected to a plurality of emitter structures 30, a plurality of emitter connection structures 35, a plurality of emitter regions 40 and a plurality of contact regions 41 via the plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63.

[0241] The emitter pad EP has a plurality of street removal portions 64. The plurality of street removal portions 64 expose portions of the interlayer film 57 that cover the plurality of street regions 9, and extend in a strip shape in the second direction Y following the extension direction of the corresponding street regions 9.

[0242] The emitter pad EP may have a thickness greater than that of the interlayer film 57. The thickness of the emitter pad EP may be 0.5 μm or more and 10 μm or less. The thickness of the emitter pad EP may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less.

[0243] The emitter pad EP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is electrically connected to a plurality of first emitter via electrodes 59 and a plurality of second emitter via electrodes 63 on the interlayer film 57.

[0244] The first electrode film 65 is connected to the first electrodes 60 of the plurality of first emitter via electrodes 59 and the first electrodes 60 of the plurality of second emitter via electrodes 63. Of course, the first electrode film 65 may cover the first electrodes 60 of the plurality of first emitter via electrodes 59 and the first electrodes 60 of the plurality of second emitter via electrodes 63.

[0245] The first electrode film 65 may have a single layer structure including a titanium film or a titanium nitride film. The first electrode film 65 may have a laminated structure including a titanium film and a titanium nitride film. In this case, the titanium nitride film may be laminated on the titanium film.

[0246] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 covers the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63 in a film-like manner.

[0247] The second electrode film 66 is electrically connected to the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63. The second electrode 61 may include at least one of a pure aluminum film, a pure copper film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0248] The semiconductor device 1A includes a monitor electrode 67 covering the monitor region 7 on the first main surface 3. The monitor electrode 67 is disposed on a portion of the interlayer film 57 covering the monitor region 7. The monitor electrode 67 is electrically isolated from the plurality of gate structures 20 and the plurality of gate connection structures 25 by the interlayer film 57 in the monitor region 7. The monitor electrode 67 is mechanically and electrically connected to the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63 on the interlayer film 57 in the monitor region 7.

[0249] The monitor electrode 67 is electrically connected to the plurality of emitter structures 30, the plurality of emitter connection structures 35, the plurality of emitter regions 40, and the plurality of contact regions 41 via the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63. Similar to the emitter pad EP, the monitor electrode 67 may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side.

[0250] The monitor electrode 67 may have a thickness greater than that of the interlayer film 57. The thickness of the monitor electrode 67 may be approximately equal to that of the emitter pad EP. The thickness range of the monitor electrode 67 is the same as the thickness range of the emitter pad EP (0.5 μm to 10 μm).

[0251] The semiconductor device 1A includes a plurality of gate openings 68 formed in the interlayer film 57 in the peripheral region 8 and the plurality of street regions 9. The plurality of gate openings 68 penetrate the interlayer film 57 and selectively expose portions of the plurality of gate wirings 56.

[0252] The multiple gate openings 68 may each extend in a strip shape following the extension direction of the multiple gate wirings 56. The multiple gate openings 68 may also be formed at intervals following the extension direction of the multiple gate wirings 56. In this case, the multiple gate openings 68 may be formed in a polygonal or circular shape in a plan view. The multiple gate openings 68 may also be formed in a quadrangular, hexagonal, or other shape in a plan view.

[0253] In this embodiment, the plurality of gate openings 68 are dug further downward from the wiring surface of the corresponding gate wiring 56 toward the main surface insulating film 48, and each have a bottom wall located within the corresponding gate wiring 56. The plurality of gate openings 68 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of gate openings 68 may also be formed approximately perpendicular to the first main surface 3.

[0254] The semiconductor device 1A includes a plurality of gate via electrodes 69 embedded in the plurality of gate openings 68. The plurality of gate via electrodes 69 are mechanically and electrically connected to the corresponding gate wirings 56 in the plurality of gate openings 68. Like the first emitter via electrode 59, the plurality of gate via electrodes 69 may have a stacked structure including a first electrode 60 and a second electrode 61.

[0255] The semiconductor device 1A includes a plurality of gate fingers 70 arranged on an interlayer film 57. The gate fingers 70 may also be referred to as "gate finger electrodes" or "finger electrodes." The plurality of gate fingers 70 are arranged on portions of the interlayer film 57 that cover the plurality of gate wirings 56.

[0256] The plurality of gate fingers 70 are mechanically and electrically connected to the plurality of gate via electrodes 69 on the interlayer film 57, and are electrically connected to the plurality of gate wirings 56 through the plurality of gate via electrodes 69. The plurality of gate fingers 70 are electrically connected to the plurality of gate structures 20 in the plurality of active regions 6 and the plurality of gate structures 20 in the monitor region 7 through the plurality of gate wirings 56.

[0257] The multiple gate fingers 70 include multiple first gate fingers 70A arranged in the outer periphery region 8 and multiple second gate fingers 70B arranged in multiple street regions 9.

[0258] The first gate fingers 70A are respectively arranged on the first gate wirings 56A in the peripheral region 8. The first gate fingers 70A are routed in a strip shape in the region between the gate pad region 11G and the corresponding gate connection structures 25 (gate connection buried electrodes 28) following the extension direction of the first gate wirings 56A.

[0259] The first gate fingers 70A are formed along the active regions 6, and each have a portion extending in the first direction X and a portion extending in the second direction Y. The first gate fingers 70A are mechanically and electrically connected to the gate via electrodes 69 on the interlayer film 57, and are electrically connected to the first gate wirings 56A via the gate via electrodes 69.

[0260] The second gate fingers 70B are respectively arranged on the second gate wirings 56B in the street regions 9. The second gate fingers 70B are routed in a strip shape in the region between the gate pad region 11G and the corresponding gate connection structures 25 (gate connection buried electrodes 28) following the extension direction of the first gate wirings 56A.

[0261] The second gate fingers 70B each have a portion interposed in the street removal portions 64 of the emitter pad EP, and extend in a strip shape in the second direction Y following the extension direction of the corresponding street region 9. One second gate finger 70B is routed through the street region 9 so as to bypass the polysilicon layers 50 (temperature sensitive diode structures D).

[0262] The second gate fingers 70B are mechanically and electrically connected to the gate via electrodes 69 on the interlayer film 57, and are electrically connected to the second gate wirings 56B via the gate via electrodes 69. Similar to the emitter pad EP, the gate fingers 70 may have a layered structure including a first electrode film 65 and a second electrode film 66 layered in this order from the interlayer film 57 side.

[0263] The gate finger 70 may have a thickness greater than that of the interlayer film 57. The thickness of the gate finger 70 may be approximately equal to that of the emitter pad EP. The thickness range of the gate finger 70 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0264] 12 and 13 , the semiconductor device 1A includes, in the temperature detection region 10, a plurality of anode openings 71 formed in portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of anode openings 71 penetrate the interlayer film 57 and expose the corresponding anode regions 51. The plurality of anode openings 71 each extend in a strip shape along the corresponding anode region 51 in a plan view.

[0265] In this embodiment, the multiple anode openings 71 are formed in an annular shape extending along the corresponding anode regions 51 in a plan view, and surround the corresponding cathode regions 52. The multiple anode openings 71 may be formed in a square, hexagonal, polygonal, circular, or other annular shape in a plan view. Of course, the multiple anode openings 71 may also be formed in an annular shape with ends extending along the corresponding anode openings 71.

[0266] The semiconductor device 1A includes, in the temperature detection region 10, a plurality of cathode openings 72 formed in portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of cathode openings 72 penetrate the interlayer film 57 at intervals corresponding to the plurality of anode openings 71, and expose the corresponding cathode regions 52. The plurality of cathode openings 72 each extend in a strip shape along the corresponding cathode region 52.

[0267] In this embodiment, the multiple cathode openings 72 are formed in an annular shape with ends that extends along the corresponding cathode regions 52 in a plan view and surround the corresponding anode regions 51. The multiple cathode openings 72 may be formed in an annular shape with ends, such as a square annular shape, a hexagonal annular shape with ends, a polygonal annular shape with ends, or a circular annular shape with ends in a plan view. Of course, the multiple cathode openings 72 may be formed in a square, hexagonal, polygonal, or circular shape in a plan view.

[0268] The semiconductor device 1A includes a plurality of anode via electrodes 73 respectively embedded in the plurality of anode openings 71. The anode via electrodes 73 are mechanically and electrically connected to the corresponding anode regions 51 in the corresponding anode openings 71. The anode via electrodes 73 may have a stacked structure including a first electrode 60 and a second electrode 61, similar to the plurality of first emitter via electrodes 59.

[0269] The semiconductor device 1A includes a plurality of cathode via electrodes 74 respectively embedded in the plurality of cathode openings 72. The plurality of cathode via electrodes 74 are mechanically and electrically connected to the corresponding cathode regions 52 in the corresponding cathode openings 72. The plurality of cathode via electrodes 74 may have a stacked structure including a first electrode 60 and a second electrode 61, similar to the plurality of first emitter via electrodes 59.

[0270] The semiconductor device 1A includes an anode wiring 75 disposed on the interlayer film 57. The anode wiring 75 is routed from the temperature detection region 10 to the anode pad region 11A via the street region 9. The anode wiring 75 has a portion that extends in a strip shape in the second direction Y within the street region 9 following the extension direction of the street region 9, and a portion that extends in a strip shape in an arbitrary direction (first direction X) outside the street region 9 toward the anode pad region 11A.

[0271] The anode wiring 75 has a portion that extends parallel to the gate finger 70 in the street region 9. Like the emitter pad EP, the anode wiring 75 may have a laminated structure including a first electrode film 65 and a second electrode film 66 that are laminated in this order from the interlayer film 57 side.

[0272] The anode wiring 75 may have a thickness greater than that of the interlayer film 57. The thickness of the anode wiring 75 may be approximately equal to that of the emitter pad EP. The thickness range of the anode wiring 75 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0273] The semiconductor device 1A includes a cathode wiring 76 disposed on the interlayer film 57. The cathode wiring 76 is routed from the temperature detection region 10 to the cathode pad region 11C via the street region 9. The cathode wiring 76 has a portion that extends in a strip shape in the second direction Y in the street region 9 following the extension direction of the street region 9, and a portion that extends in a strip shape in an arbitrary direction (first direction X) outside the street region 9 toward the cathode pad region 11C.

[0274] The cathode wiring 76 has a portion that extends parallel to both the gate finger 70 and the anode wiring 75 within the street region 9. Like the emitter pad EP, the cathode wiring 76 may have a laminated structure including a first electrode film 65 and a second electrode film 66 that are laminated in this order from the interlayer film 57 side.

[0275] The cathode wiring 76 may have a thickness greater than that of the interlayer film 57. The thickness of the cathode wiring 76 may be approximately equal to that of the emitter pad EP. The thickness range of the cathode wiring 76 is the same as the thickness range of the emitter pad EP (0.5 μm to 10 μm).

[0276] The semiconductor device 1A includes a plurality of anode connection wirings 77 formed on portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The anode connection wirings 77 have portions that extend along the corresponding anode via electrodes 73 on the interlayer film 57, and are mechanically and electrically connected to the corresponding anode via electrodes 73, respectively.

[0277] The multiple anode connection wirings 77 may be formed in a polygonal shape, a circular shape, etc. in a planar view. The multiple anode connection wirings 77 may be formed in a quadrangular shape, a hexagonal shape, etc. in a planar view. Similar to the emitter pad EP, the multiple anode connection wirings 77 may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side.

[0278] The anode connecting wiring 77 may have a thickness greater than that of the interlayer film 57. The thickness of the anode connecting wiring 77 may be approximately equal to that of the emitter pad EP. The thickness range of the anode connecting wiring 77 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0279] The semiconductor device 1A includes a plurality of cathode connection wirings 78 formed on portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of cathode connection wirings 78 have portions that extend in strip shapes along the corresponding cathode via electrodes 74 on the interlayer film 57, and are mechanically and electrically connected to the corresponding cathode via electrodes 74. Similar to the emitter pad EP, the plurality of cathode connection wirings 78 may each have a layered structure including a first electrode 60 and a second electrode 61 that are layered in this order from the interlayer film 57 side.

[0280] The cathode connecting wiring 78 may have a thickness greater than that of the interlayer film 57. The thickness of the cathode connecting wiring 78 may be approximately equal to that of the emitter pad EP. The thickness range of the cathode connecting wiring 78 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0281] The semiconductor device 1A includes a plurality of connection wirings 79 formed on portions of the interlayer film 57 that cover the plurality of polysilicon layers 50. The plurality of connection wirings 79 are respectively interposed in regions between the plurality of polysilicon layers 50 adjacent to each other in the second direction Y on the interlayer film 57, and electrically connect the corresponding anode wirings 75 to the corresponding cathode wirings 76. The plurality of connection wirings 79 each extend in a strip shape in the second direction Y in a plan view.

[0282] One connection wiring 79 positioned at the outermost position on one side in the second direction Y electrically connects the outermost anode connection wiring 77 to the anode wiring 75. The other connection wiring 79 positioned at the outermost position on one side in the second direction Y electrically connects the outermost cathode connection wiring 78 to the anode wiring 75. This forms a first series circuit SC1 including a plurality of first diodes D1.

[0283] One connection wiring 79 positioned outermost on the other side in the second direction Y electrically connects the outermost cathode connection wiring 78 to the cathode wiring 76. The other connection wiring 79 positioned outermost on the other side in the second direction Y electrically connects the outermost anode connection wiring 77 to the cathode wiring 76. This forms a second series circuit SC2 including a plurality of second diodes D2.

[0284] The connection wiring 79 may have a thickness greater than that of the interlayer film 57. The thickness of the connection wiring 79 may be approximately equal to that of the emitter pad EP. The thickness range of the connection wiring 79 is the same as the thickness range of the emitter pad EP (0.5 μm or more and 10 μm or less).

[0285] The configuration within the multiple pad regions 11 will be described below. Fig. 14 is an enlarged plan view showing the configuration within the pad region 11 together with the pad capacitor structure 84 according to the first layout example and the pad opening 93 according to the first layout example. Fig. 15 is an enlarged plan view showing a main part of the pad region 11.

[0286] Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 15. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 15. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 15. Fig. 19 is an enlarged cross-sectional view of a main part shown in Fig. 16.

[0287] The semiconductor device 1A includes a plurality of p-type pad well regions 80 formed in the surface layer portion of the first main surface 3 in the plurality of pad regions 11. The pad well regions 80 have a p-type impurity concentration higher than the n-type impurity concentration of the drift region 12, and convert the conductivity type of the drift region 12 from n-type to p-type.

[0288] The pad well region 80 may have a p-type impurity concentration higher than the p-type impurity concentration of the base region 15. Of course, the p-type impurity concentration of the pad well region 80 may be lower than the p-type impurity concentration of the base region 15. The p-type impurity concentration of the pad well region 80 is lower than the p-type impurity concentration of the contact region 41.

[0289] The p-type impurity concentration of the pad well region 80 may be approximately equal to the p-type impurity concentration of the peripheral well region 44. Of course, the p-type impurity concentration of the pad well region 80 may be higher than the p-type impurity concentration of the peripheral well region 44, or may be lower than the p-type impurity concentration of the peripheral well region 44.

[0290] The p-type impurity concentration of the pad well region 80 may be approximately equal to the p-type impurity concentration of the street well region 45. Of course, the p-type impurity concentration of the pad well region 80 may be higher than the p-type impurity concentration of the street well region 45, or may be lower than the p-type impurity concentration of the street well region 45.

[0291] An emitter potential is applied to the plurality of pad well regions 80. The plurality of pad well regions 80 are formed over the entire area of ​​the corresponding pad region 11. In this embodiment, the plurality of pad well regions 80 are connected to the peripheral well region 44 and the plurality of street well regions 45, and are formed integrally with the plurality of street well regions 45 and the peripheral well region 44.

[0292] That is, the plurality of pad well regions 80 are electrically connected to the plurality of base regions 15 via the plurality of street well regions 45 and the peripheral well region 44. In this embodiment, the plurality of pad well regions 80 have a width in the first direction X that is greater than the width of the plurality of street well regions 45.

[0293] The pad well regions 80 are formed deeper than the base regions 15. Specifically, the pad well regions 80 are formed deeper than the gate structures 20, the gate connection structures 25, the emitter structures 30, and the emitter connection structures 35.

[0294] The plurality of pad well regions 80 may have a depth approximately equal to the depth of the plurality of well regions 43. Of course, the depth of the plurality of pad well regions 80 may be greater than the depth of the plurality of well regions 43 or may be less than the depth of the plurality of well regions 43.

[0295] The depth of the multiple pad well regions 80 may be approximately equal to the depth of the periphery well region 44. Of course, the depth of the multiple pad well regions 80 may be greater than the depth of the periphery well region 44 or may be less than the depth of the periphery well region 44.

[0296] The depth of the plurality of pad well regions 80 may be approximately equal to the depth of the plurality of street well regions 45. Of course, the depth of the plurality of pad well regions 80 may be greater than the depth of the plurality of street well regions 45 or may be less than the depth of the plurality of street well regions 45.

[0297] The semiconductor device 1A includes a plurality of pad capacitor structures 84 formed in the plurality of pad regions 11, respectively (see also FIG. 3). In this embodiment, the plurality of pad capacitor structures 84 include a monitor capacitor structure CM formed in the monitor pad region 11M, an anode capacitor structure CA formed in the anode pad region 11A, and a cathode capacitor structure CC formed in the cathode pad region 11C. In the following, the configuration of the anode capacitor structure CA will be mainly described as an example of the pad capacitor structure 84.

[0298] The configuration of the monitor capacitor structure CM can be obtained by replacing "anode capacitor structure CA" with "monitor capacitor structure CM" and "anode pad area 11A" with "monitor pad area 11M" in the following description.

[0299] The configuration of the cathode capacitor structure CC can be obtained by replacing "anode capacitor structure CA" with "cathode capacitor structure CC" and "anode pad area 11A" with "cathode pad area 11C" in the following description.

[0300] The anode capacitor structure CA includes a plurality of trench electrode type capacitor structures 85 formed on the first main surface 3. The emitter potential of the transistor structure T3 is applied to the plurality of capacitor structures 85. In other words, the same potential as that applied to the pad well region 80 is applied to the plurality of capacitor structures 85.

[0301] The plurality of capacitor structures 85 does not form a voltage drop due to an externally applied potential with the pad well region 80, except for a voltage drop due to an electric field distribution formed within the chip 2. The plurality of capacitor structures 85 are electrically isolated from the monitor potential of the monitor transistor structure T2.

[0302] The number of capacitor structures 85 is less than the number of gate structures 20. The total area (total length) of the plurality of capacitor structures 85 is less than the total area (total length) of the plurality of gate structures 20. The number of capacitor structures 85 is less than the number of emitter structures 30. The total area (total length) of the plurality of capacitor structures 85 is less than the total area (total length) of the plurality of emitter structures 30.

[0303] The plurality of capacitor structures 85 extend in a strip shape in the first direction X in the anode pad region 11A and are arranged at intervals in the second direction Y. That is, the plurality of capacitor structures 85 are arranged in stripes extending in the first direction X. The extension direction of the plurality of capacitor structures 85 coincides with the extension direction of the plurality of gate structures 20. The extension direction of the plurality of capacitor structures 85 coincides with the extension direction of the plurality of emitter structures 30.

[0304] The plurality of capacitor structures 85 may each have a width that is less than the width of the plurality of street regions 9. The width of the capacitor structure 85 is the width in a direction (second direction Y) perpendicular to the extension direction (first direction X) of the capacitor structure 85.

[0305] The width of the capacitor structure 85 may be approximately equal to the width of the gate structure 20. Of course, the width of the capacitor structure 85 may be greater than or less than the width of the gate structure 20. The width of the capacitor structure 85 may be approximately equal to the width of the gate connection structure 25. Of course, the width of the capacitor structure 85 may be greater than or less than the width of the gate connection structure 25.

[0306] The width of the capacitor structure 85 may be approximately equal to the width of the emitter structure 30. Of course, the width of the emitter structure 30 may be greater than or smaller than the width of the emitter structure 30. The width of the capacitor structure 85 may be approximately equal to the width of the emitter connection structure 35. Of course, the width of the capacitor structure 85 may be greater than or smaller than the width of the emitter connection structure 35.

[0307] The width of the capacitor structure 85 may be 0.5 μm or more and 5 μm or less. The width of the capacitor structure 85 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The width of the capacitor structure 85 is preferably 1 μm or more and 2.5 μm or less.

[0308] The second trench pitch between the centers of the capacitor structures 85 may be approximately equal to the first trench pitch between the centers of the gate structures 20 and the emitter structures 30. Of course, the second trench pitch may be larger or smaller than the first trench pitch.

[0309] The second trench pitch may be 1 μm or more and 5 μm or less. The second trench pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The second trench pitch is preferably 1.5 μm or more and 3.5 μm or less.

[0310] The plurality of capacitor structures 85 are formed at intervals from a depth position of the middle part of the drift region 12 toward the first main surface 3. Specifically, the plurality of capacitor structures 85 are formed on the first main surface 3 so as to be located within the pad well region 80.

[0311] More specifically, the plurality of capacitor structures 85 are formed at intervals from the bottom of the pad well region 80 toward the first main surface 3, and face the drift region 12 across a part of the pad well region 80 in the thickness direction. In other words, the plurality of capacitor structures 85 are connected to the pad well region 80 throughout the entire depth direction.

[0312] The plurality of capacitor structures 85 may each have a bottom wall located on the bottom side of the pad well region 80 relative to the depth position of the intermediate portion of the pad well region 80. Of course, the bottom walls of the plurality of capacitor structures 85 may be located on the first main surface 3 side relative to the depth position of the intermediate portion of the pad well region 80. Of course, the plurality of capacitor structures 85 may penetrate the pad well region 80 to reach the drift region 12.

[0313] The plurality of capacitor structures 85 may be formed in a tapered shape toward the bottom wall. Of course, the plurality of capacitor structures 85 may be formed substantially perpendicular to the first main surface 3.

[0314] The bottom walls of the plurality of capacitor structures 85 may be formed in a curved shape toward the second main surface 4. Of course, the bottom walls of the plurality of capacitor structures 85 may be formed substantially parallel to the first main surface 3. In this case, corners of the bottom walls of the plurality of capacitor structures 85 may be formed in a curved shape.

[0315] The plurality of capacitor structures 85 may have a depth approximately equal to the depth of the plurality of gate structures 20. Of course, the depth of the capacitor structures 85 may be greater than or less than the depth of the gate structures 20.

[0316] The depth of the capacitor structure 85 may be approximately equal to the depth of the gate connection structure 25. Of course, the depth of the capacitor structure 85 may be greater than the depth of the gate connection structure 25 or may be less than the depth of the gate connection structure 25.

[0317] The depth of the capacitor structure 85 may be approximately equal to the depth of the emitter structure 30. Of course, the depth of the emitter structure 30 may be greater than the depth of the emitter structure 30 or may be less than the depth of the emitter structure 30.

[0318] The depth of the capacitor structure 85 may be approximately equal to the depth of the emitter connection structure 35. Of course, the depth of the capacitor structure 85 may be greater than the depth of the emitter connection structure 35 or may be less than the depth of the emitter connection structure 35.

[0319] The depth of the capacitor structure 85 may be 0.5 μm or more and 10 μm or less. The depth of the capacitor structure 85 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The depth of the capacitor structure 85 is preferably 4 μm or more and 8 μm or less.

[0320] The multiple capacitor structures 85 each have an extension portion 85a that is extended from the anode pad region 11A to the active region 6 (in this embodiment, the first active region 6A), and are each electrically connected to the multiple emitter structures 30 within the active region 6.

[0321] For example, the multiple lead-out portions 85 a may be led out to the active region 6 through open portions of the gate connection structure 25 where no gate connection structure 25 is present, and may be connected to the multiple emitter structures 30 respectively within the active region 6. In this way, the emitter potential is applied to the multiple capacitor structures 85 via the multiple emitter structures 30.

[0322] The plurality of lead-out portions 85 a (capacitor structures 85) may be mechanically connected to the plurality of emitter structures 30, respectively, in the active region 6. The plurality of lead-out portions 85 a (capacitor structures 85) may be connected to the plurality of emitter connection structures 35, respectively, in the active region 6. In this case, the plurality of capacitor structures 85 are mechanically and electrically connected to the plurality of emitter structures 30 via the plurality of emitter connection structures 35.

[0323] The plurality of capacitor structures 85 (lead portions 85 a) may be led out to the anode pad region 11A in a one-to-one correspondence from the plurality of emitter structures 30. In this case, the plurality of capacitor structures 85 may be led out at the same trench pitch (third trench pitch) as the trench pitch of the plurality of emitter structures 30.

[0324] The plurality of capacitor structures 85 (lead portions 85a) do not necessarily have to be drawn out to the anode pad region 11A in a one-to-one correspondence from the plurality of emitter structures 30. Therefore, one or more capacitor structures 85 (lead portions 85a) may be drawn out to the anode pad region 11A from a corresponding one emitter structure 30. Of course, one capacitor structure 85 (lead portion 85a) may also be drawn out to the anode pad region 11A from a plurality of emitter structures 30.

[0325] The one or more lead-out portions 85 a (capacitor structures 85) may have both a portion extending in the first direction X and a portion extending in the second direction Y within the active region 6 and / or the anode pad region 11A, and may be configured to adjust the trench pitch (third trench pitch) in the anode pad region 11A.

[0326] Of course, one or more capacitor structures 85 may have one or more pull-out portions 85a extending in the second direction Y and may be connected to one or more emitter structures 30 of active regions 6 adjacent in the second direction Y (e.g., the first active region 6A or the second active region 6B).

[0327] Each of the plurality of capacitor structures 85 includes a capacitor trench 86, a capacitor insulating film 87, and a capacitor buried electrode 88. The capacitor trench 86 is formed in the first main surface 3 and defines the wall surfaces (side walls and bottom wall) of the capacitor structure 85.

[0328] The capacitor trench 86 communicates with the emitter trench 31 of the corresponding one or more emitter structures 30. When the capacitor structure 85 is connected to the emitter connection structure 35, the capacitor trench 86 may communicate with the emitter connection trench 36. That is, the capacitor trench 86 may communicate with the emitter trench 31 via the emitter connection trench 36.

[0329] The capacitor insulating film 87 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The capacitor insulating film 87 preferably includes the same type of insulator as the gate insulating film 22 (emitter insulating film 32). In this embodiment, the capacitor insulating film 87 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the capacitor insulating film 87 includes a silicon oxide film made of an oxide of the chip 2.

[0330] The capacitor insulating film 87 covers the wall surface of the capacitor trench 86. The capacitor insulating film 87 is connected to the emitter insulating film 32 at the communicating portion between the emitter trench 31 and the capacitor trench 86.

[0331] When the capacitor structure 85 is connected to the emitter connection structure 35, the capacitor insulating film 87 may be connected to the emitter connection insulating film 37 at the communicating portion between the emitter trench 31 and the capacitor trench 86. In other words, the capacitor insulating film 87 may be connected to the emitter insulating film 32 via the emitter connection insulating film 37.

[0332] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the gate insulating film 22. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the gate insulating film 22 or may be smaller than the thickness of the gate insulating film 22.

[0333] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the gate connecting insulating film 27. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the gate connecting insulating film 27 or may be smaller than the thickness of the gate connecting insulating film 27.

[0334] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the emitter insulating film 32. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the emitter insulating film 32 or may be smaller than the thickness of the emitter insulating film 32.

[0335] The thickness of the capacitor insulating film 87 may be approximately equal to the thickness of the emitter connection insulating film 37. Of course, the thickness of the capacitor insulating film 87 may be greater than the thickness of the emitter connection insulating film 37 or may be smaller than the thickness of the emitter connection insulating film 37.

[0336] The thickness of the capacitor insulating film 87 may be 10 nm or more and 200 nm or less. The thickness of the capacitor insulating film 87 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. The thickness of the capacitor insulating film 87 is preferably 100 nm or more and 150 nm or less.

[0337] The capacitor buried electrode 88 is buried in the capacitor trench 86 with a capacitor insulating film 87 therebetween. The capacitor buried electrode 88 faces the pad well region 80 with the capacitor insulating film 87 therebetween. Specifically, the capacitor buried electrode 88 faces the pad well region 80 on the sidewalls and bottom wall of the capacitor trench 86.

[0338] When the capacitor trench 86 penetrates the pad well region 80, the capacitor buried electrode 88 may have a portion facing the pad well region 80 via the capacitor insulating film 87, and a portion facing the drift region 12 via the capacitor insulating film 87.

[0339] The capacitor buried electrode 88 is connected to the emitter buried electrode 33 at the communicating portion between the emitter trench 31 and the capacitor trench 86. When the capacitor structure 85 is connected to the emitter connecting structure 35, the capacitor buried electrode 88 may be connected to the emitter connecting buried electrode 38 at the communicating portion between the emitter trench 31 and the capacitor trench 86. In other words, the capacitor insulating film 87 may be connected to the emitter buried electrode 33 via the emitter connecting buried electrode 38.

[0340] The capacitor buried electrode 88 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The capacitor buried electrode 88 preferably includes the same type of conductor as the gate buried electrode 23 (emitter buried electrode 33).

[0341] The anode capacitor structure CA includes the aforementioned main surface insulating film 48 that covers the first main surface 3 of the anode pad region 11A. The main surface insulating film 48 is formed as a main surface dielectric film (first dielectric film) in the anode pad region 11A.

[0342] In the anode capacitor structure CA, the main surface insulating film 48 covers the pad well region 80 on the first main surface 3. The main surface insulating film 48 is connected to the capacitor insulating film 87 in the anode pad region 11A. The thickness of the main surface insulating film 48 may be approximately equal to the thickness of the capacitor insulating film 87. Of course, the thickness of the main surface insulating film 48 may be greater than or less than the thickness of the capacitor insulating film 87.

[0343] The anode capacitor structure CA includes a plurality of first capacitor electrode films 90 arranged on the first main surface 3 in the anode pad region 11A. The first capacitor electrode films 90 may also be referred to as "first electrodes." The plurality of first capacitor electrode films 90 cover the plurality of capacitor structures 85, respectively, and are electrically connected to the plurality of capacitor structures 85, respectively.

[0344] That is, an emitter potential is applied to the plurality of first capacitor electrode films 90. Furthermore, the same potential as that applied to the pad well region 80 is applied to the plurality of first capacitor electrode films 90. The plurality of first capacitor electrode films 90 do not form a voltage drop caused by an externally applied potential with the pad well region 80, except for a voltage drop caused by an electric field distribution formed within the chip 2.

[0345] In this embodiment, the plurality of first capacitor electrode films 90 respectively cover the plurality of capacitor structures 85 in a one-to-one correspondence. The plurality of first capacitor electrode films 90 each extend in a strip shape in the first direction X in the anode pad region 11A, following the extension direction of the corresponding capacitor structures 85.

[0346] The plurality of first capacitor electrode films 90 may cover the entire area of ​​the portion of the corresponding capacitor structure 85 located in the anode pad region 11A (portion other than the lead portion 85a). Of course, the plurality of first capacitor electrode films 90 may also cover only part of the portion of the corresponding capacitor structure 85 located in the anode pad region 11A.

[0347] The plurality of first capacitor electrode films 90 may have portions that cover the lead-out portions 85 a of the corresponding capacitor structures 85. The plurality of first capacitor electrode films 90 may cover the entire areas of the corresponding lead-out portions 85 a. In this case, the plurality of first capacitor electrode films 90 may be connected to one or more emitter wirings 55 via the corresponding lead-out portions 85 a.

[0348] The plurality of first capacitor electrode films 90 may have a width greater than the width of the plurality of capacitor structures 85. The width of the first capacitor electrode films 90 is the width in a direction perpendicular to the extension direction of the first capacitor electrode films 90.

[0349] Of course, the first capacitor electrode film 90 may be smaller in width than the capacitor structure 85. In this embodiment, the plurality of first capacitor electrode films 90 are each formed wider than the corresponding capacitor structure 85, and have a portion located in a region outside the corresponding capacitor structure 85.

[0350] Specifically, the plurality of first capacitor electrode films 90 have portions covering the capacitor buried electrodes 88 of the corresponding capacitor structures 85 and portions covering the main surface insulating film 48. The plurality of first capacitor electrode films 90 face the first main surface 3 with the main surface insulating film 48 interposed therebetween.

[0351] Specifically, the first capacitor electrode film 90 faces the pad well region 80 across the main surface insulating film 48. Of course, the multiple first capacitor electrode films 90 may be formed only on the corresponding buried capacitor electrodes 88 and face only the buried capacitor electrodes 88 in the thickness direction.

[0352] The first capacitor electrode film 90 may have a sidewall extending substantially perpendicular to the first main surface 3. Of course, the sidewall of the first capacitor electrode film 90 may be inclined obliquely downward from the electrode main surface toward the chip 2 (first main surface 3).

[0353] The first capacitor electrode film 90 may be made of a conductive material other than metal. In this embodiment, the first capacitor electrode film 90 is made of the same type of conductive material as the capacitor buried electrode 88 (either p-type conductive polysilicon or n-type conductive polysilicon, or both).

[0354] In this embodiment, the plurality of first capacitor electrode films 90 are each formed integrally with the corresponding capacitor buried electrodes 88 as a protruding portion that protrudes from the corresponding capacitor buried electrodes 88 above the height position of the first main surface 3. The plurality of first capacitor electrode films 90 may have a recess that is recessed toward the bottom wall of the corresponding capacitor structure 85 in the portion that covers the corresponding capacitor structure 85.

[0355] Of course, the first capacitor electrode film 90 may be made of a metal film. In this case, the first capacitor electrode film 90 may be mechanically and electrically connected to a plurality of capacitor structures 85 (capacitor buried electrodes 88) on the main surface insulating film 48.

[0356] The first capacitor electrode film 90 has a thickness greater than that of the main surface insulating film 48. The thickness of the first capacitor electrode film 90 is the thickness (protrusion amount) of the first capacitor electrode film 90 based on the insulating surface of the main surface insulating film 48. The thickness of the first capacitor electrode film 90 is preferably less than the depth (thickness) of the pad well region 80. The thickness of the first capacitor electrode film 90 is preferably less than the depth of the capacitor structure 85.

[0357] The thickness of the first capacitor electrode film 90 is preferably less than the depth of the gate structure 20 (emitter structure 30). The thickness of the first capacitor electrode film 90 is preferably less than the depth of the gate connection structure 25 (emitter connection structure 35).

[0358] The thickness of the first capacitor electrode film 90 may be approximately equal to the thickness of the polysilicon layer 50. Of course, the thickness of the first capacitor electrode film 90 may be greater than the thickness of the polysilicon layer 50 or may be smaller than the thickness of the polysilicon layer 50.

[0359] The thickness of the first capacitor electrode film 90 may be approximately equal to the thickness of the emitter wiring 55. Of course, the thickness of the first capacitor electrode film 90 may be greater than the thickness of the emitter wiring 55 or may be smaller than the thickness of the emitter wiring 55.

[0360] The thickness of the first capacitor electrode film 90 may be approximately equal to the thickness of the gate wiring 56. Of course, the thickness of the first capacitor electrode film 90 may be greater than the thickness of the gate wiring 56 or may be smaller than the thickness of the gate wiring 56.

[0361] The thickness of the first capacitor electrode film 90 may be 0.1 μm or more and 2 μm or less. The thickness of the first capacitor electrode film 90 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the first capacitor electrode film 90 is preferably 0.25 μm or more and 1.25 μm or less.

[0362] The anode capacitor structure CA includes a plurality of sidewall dielectric films 91 that respectively cover the sidewalls of a plurality of first capacitor electrode films 90 in the anode pad region 11A. The sidewall dielectric films 91 may also be referred to as "sidewall insulating films," "second dielectric films," etc.

[0363] The plurality of sidewall dielectric films 91 each cover, in a film-like manner, the sidewall of the corresponding first capacitor electrode film 90. The plurality of sidewall dielectric films 91 cover the entire periphery of the sidewall of the corresponding first capacitor electrode film 90 and surround the corresponding first capacitor electrode film 90.

[0364] The plurality of sidewall dielectric films 91 extend in a film shape in the vertical direction Z (inclination direction) following the extending direction (inclination angle) of the sidewalls of the corresponding first capacitor electrode films 90. The plurality of sidewall dielectric films 91 are connected to the main surface insulating film 48 in the portions covering the sidewalls of the corresponding first capacitor electrode films 90. The plurality of sidewall dielectric films 91 face the pad well region 80 with the main surface insulating film 48 interposed therebetween.

[0365] The sidewall dielectric films 91 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The sidewall dielectric films 91 may be made of the same type of insulator as the insulator of the gate insulating film 22 (emitter insulating film 32), or may be made of an insulator different from the insulator of the gate insulating film 22 (emitter insulating film 32).

[0366] The sidewall dielectric films 91 may be made of the same type of insulator as the insulator of the main surface insulating film 48, or may be made of an insulator different from the insulator of the main surface insulating film 48. In this embodiment, the sidewall dielectric films 91 have a single-layer structure made of the same type of insulator (silicon oxide film) as the insulator of the main surface insulating film 48 (gate insulating film 22), and have a density different from the density of the insulator of the main surface insulating film 48 (gate insulating film 22).

[0367] The plurality of sidewall dielectric films 91 have a thickness less than the thickness of the first capacitor electrode film 90. The thickness of the sidewall dielectric film 91 may be greater than the thickness of the gate insulating film 22 (emitter insulating film 32). Of course, the thickness of the sidewall dielectric film 91 may be less than the thickness of the gate insulating film 22 (emitter insulating film 32). The thickness of the sidewall dielectric film 91 may be greater than the thickness of the main surface insulating film 48. Of course, the thickness of the sidewall dielectric film 91 may be less than the thickness of the main surface insulating film 48.

[0368] The thickness of the sidewall dielectric film 91 may be 10 nm or more and 500 nm or less. The thickness of the sidewall dielectric film 91 may have a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, 175 nm to 200 nm, 200 nm to 225 nm, 225 nm to 250 nm, 250 nm to 275 nm, 275 nm to 300 nm, 300 nm to 325 nm, 325 nm to 350 nm, 350 nm to 375 nm, 375 nm to 400 nm, 400 nm to 425 nm, 425 nm to 450 nm, 450 nm to 475 nm, and 475 nm to 500 nm. The thickness of the sidewall dielectric film 91 is preferably 100 nm or more and 200 nm or less.

[0369] The anode capacitor structure CA includes a plurality of second capacitor electrode films 92 arranged on the first main surface 3 in the anode pad region 11A. The second capacitor electrode films 92 may also be referred to as "second electrodes."

[0370] A potential different from the potential (emitter potential) applied to the plurality of capacitor structures 85 (the plurality of first capacitor electrode films 90) is applied to the plurality of second capacitor electrode films 92. In other words, a potential different from the potential (emitter potential) applied to the pad well region 80 is applied to the plurality of second capacitor electrode films 92.

[0371] The plurality of second capacitor electrode films 92 are disposed on the main surface insulating film 48 at intervals from the plurality of capacitor structures 85 (the plurality of first capacitor electrode films 90). The plurality of second capacitor electrode films 92 form capacitive coupling with the chip 2 via the main surface insulating film 48. Specifically, the plurality of second capacitor electrode films 92 cover the pad well region 80 with the main surface insulating film 48 in between, and form capacitive coupling with the pad well region 80 via the main surface insulating film 48.

[0372] As a result, the second capacitor electrode films 92 form a plurality of first capacitors C1 together with the chip 2 (pad well region 80) in the anode pad region 11 A. The first capacitors C1 are connected in parallel with one another.

[0373] The multiple second capacitor electrode films 92 are arranged on the first main surface 3 (main surface insulating film 48) at horizontal intervals from one or more first capacitor electrode films 90, and horizontally face the one or more first capacitor electrode films 90.

[0374] In this embodiment, the multiple second capacitor electrode films 92 are each arranged at a distance from one or more first capacitor electrode films 90 in the second direction Y, and are adjacent to one or more first capacitor electrode films 90 in the second direction Y.

[0375] Specifically, the multiple second capacitor electrode films 92 are respectively arranged in regions between the multiple first capacitor electrode films 90 adjacent to each other in the second direction Y, and are arranged alternately with the multiple first capacitor electrode films 90 in the second direction Y.

[0376] The second capacitor electrode films 92 each extend in a strip shape in the first direction X, following the extension direction of the first capacitor electrode films 90. In other words, the second capacitor electrode films 92 are arranged in stripes extending along the first direction X.

[0377] The plurality of second capacitor electrode films 92 may have a width greater than the width of the plurality of capacitor structures 85. The width of the second capacitor electrode film 92 is the width in a direction perpendicular to the extending direction of the second capacitor electrode film 92. Of course, the width of the second capacitor electrode film 92 may be smaller than the width of the capacitor structure 85.

[0378] The width of the second capacitor electrode film 92 may be approximately equal to the width of the first capacitor electrode film 90, or may be different from the width of the first capacitor electrode film 90. The width of the second capacitor electrode film 92 may be larger than the width of the first capacitor electrode film 90, or may be smaller than the width of the first capacitor electrode film 90.

[0379] In this embodiment, the plurality of second capacitor electrode films 92 include outermost second capacitor electrode films 92 arranged on both sides of the plurality of first capacitor electrode films 90 in the second direction Y. The outermost second capacitor electrode film 92 arranged on one side in the second direction Y faces one first capacitor electrode film 90 on the other side in the second direction Y.

[0380] The outermost second capacitor electrode film 92 arranged on the other side in the second direction Y faces one first capacitor electrode film 90 on one side in the second direction Y. Of course, the multiple second capacitor electrode films 92 may be arranged only in regions between the multiple first capacitor electrode films 90.

[0381] The multiple second capacitor electrode films 92 horizontally face the one or more first capacitor electrode films 90, sandwiching one or more sidewall dielectric films 91 therebetween, and form capacitive coupling with the one or more first capacitor electrode films 90 via the one or more sidewall dielectric films 91.

[0382] The second capacitor electrode films 92 are capacitively coupled only in the horizontal direction with the first capacitor electrode films 90. In other words, the second capacitor electrode films 92 do not have a portion that covers the main electrode surface of the first capacitor electrode film 90, and are not capacitively coupled with the first capacitor electrode film 90 in the thickness direction.

[0383] It is preferable that the entire sidewall of the second capacitor electrode film 92 faces the corresponding sidewall of the first capacitor electrode film 90 via the corresponding sidewall dielectric film 91. Of course, only a part of the sidewall of the second capacitor electrode film 92 may face the corresponding sidewall of the first capacitor electrode film 90 via the corresponding sidewall dielectric film 91.

[0384] The second capacitor electrode film 92 may have sidewalls that extend substantially perpendicular to the first main surface 3. Of course, the sidewalls of the second capacitor electrode film 92 may be inclined obliquely downward from the electrode main surface toward the chip 2 (first main surface 3).

[0385] The second capacitor electrode films 92 form second capacitors C2 with the corresponding first capacitor electrode films 90 in the anode pad region 11A. The second capacitors C2 are connected in parallel to each other. The second capacitors C2 are connected in parallel to the first capacitors C1.

[0386] In this embodiment, the thickness of the sidewall dielectric film 91 is greater than the thickness of the main surface insulating film 48. Therefore, the capacitance value of the second capacitor C2 is smaller than the capacitance value of the first capacitor C1. Of course, the thickness of the sidewall dielectric film 91 may be smaller than the thickness of the main surface insulating film 48. In other words, the capacitance value of the second capacitor C2 may be greater than the capacitance value of the first capacitor C1.

[0387] The second capacitor electrode film 92 may be made of a conductive material other than metal. In this embodiment, the second capacitor electrode film 92 is made of the same type of conductive material (either p-type conductive polysilicon or n-type conductive polysilicon, or both) as the first capacitor electrode film 90 (the buried capacitor electrode 88).

[0388] The conductivity type of the second capacitor electrode may be the same as or different from the conductivity type of the first capacitor electrode film 90. The second capacitor electrode film 92 may be made of a metal film.

[0389] The second capacitor electrode film 92 has a thickness greater than the thickness of the main surface insulating film 48. The thickness of the second capacitor electrode film 92 is the thickness of the second capacitor electrode film 92 based on the insulating surface of the main surface insulating film 48.

[0390] The thickness of the second capacitor electrode film 92 is preferably less than the depth (thickness) of the pad well region 80. The thickness of the second capacitor electrode film 92 is preferably less than the depth of the capacitor structure 85.

[0391] The thickness of the second capacitor electrode film 92 is preferably less than the depth of the gate structure 20 (emitter structure 30). The thickness of the second capacitor electrode film 92 is preferably less than the depth of the gate connection structure 25 (emitter connection structure 35).

[0392] The thickness of the second capacitor electrode film 92 may be approximately equal to the thickness of the polysilicon layer 50. Of course, the thickness of the second capacitor electrode film 92 may be greater than the thickness of the polysilicon layer 50 or may be smaller than the thickness of the polysilicon layer 50.

[0393] The thickness of the second capacitor electrode film 92 may be approximately equal to the thickness of the emitter wiring 55. Of course, the thickness of the second capacitor electrode film 92 may be greater than the thickness of the emitter wiring 55 or may be smaller than the thickness of the emitter wiring 55.

[0394] The thickness of the second capacitor electrode film 92 may be approximately equal to the thickness of the gate wiring 56. Of course, the thickness of the second capacitor electrode film 92 may be greater than the thickness of the gate wiring 56 or may be smaller than the thickness of the gate wiring 56.

[0395] It is preferable that the thickness of the second capacitor electrode film 92 is approximately equal to the thickness of the first capacitor electrode film 90. Of course, the thickness of the second capacitor electrode film 92 may be greater than the thickness of the first capacitor electrode film 90, or may be smaller than the thickness of the first capacitor electrode film 90.

[0396] The thickness of the second capacitor electrode film 92 may be 0.1 μm or more and 2 μm or less. The thickness of the second capacitor electrode film 92 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The thickness of the second capacitor electrode film 92 is preferably 0.25 μm or more and 1.25 μm or less.

[0397] The anode capacitor structure CA includes the aforementioned interlayer film 57 that covers the plurality of first capacitor electrode films 90 and the plurality of second capacitor electrode films 92 in the anode pad region 11A. The interlayer film 57 is connected to the plurality of sidewall dielectric films 91 on the plurality of first capacitor electrode films 90 and the plurality of second capacitor electrode films 92.

[0398] In this embodiment, the interlayer film 57 is integrally formed with the plurality of sidewall dielectric films 91. That is, the interlayer film 57 has the plurality of sidewall dielectric films 91 as the plurality of embedded portions embedded in the gaps between the plurality of first capacitor electrode films 90 and the plurality of second capacitor electrode films 92.

[0399] The interlayer film 57 covers the pad well region 80 with the main surface insulating film 48 and the plurality of first capacitor electrode films 90 sandwiched therebetween, and also covers the pad well region 80 with the main surface insulating film 48 and the plurality of second capacitor electrode films 92 sandwiched therebetween.

[0400] The thickness of the interlayer film 57 is preferably greater than the thickness of the first capacitor electrode film 90. Of course, the thickness of the interlayer film 57 may be less than the thickness of the first capacitor electrode film 90. The thickness of the interlayer film 57 is preferably greater than the thickness of the second capacitor electrode film 92. Of course, the thickness of the interlayer film 57 may be less than the thickness of the second capacitor electrode film 92.

[0401] The anode capacitor structure CA includes a plurality of pad openings 93 selectively formed in the interlayer film 57 in the anode pad region 11A. The plurality of pad openings 93 selectively expose portions of the plurality of second capacitor electrode films 92. Specifically, the plurality of pad openings 93 expose portions of the plurality of second capacitor electrode films 92 at intervals from the plurality of first capacitor electrode films 90 (capacitor structures 85).

[0402] In this embodiment, the plurality of pad openings 93 are formed in one-to-one correspondence with the plurality of second capacitor electrode films 92, and extend in a strip shape in the first direction X following the extension direction of the corresponding second capacitor electrode films 92. The plurality of pad openings 93 expose inner portions of the corresponding second capacitor electrode films 92 at intervals from the periphery of the corresponding second capacitor electrode films 92.

[0403] In this embodiment, the plurality of pad openings 93 are dug further downward from the electrode main surfaces of the corresponding second capacitor electrode films 92 toward the first main surface 3 (main surface insulating film 48) side, and have bottom walls positioned within the corresponding second capacitor electrode films 92. The bottom walls of the plurality of pad openings 93 are preferably formed at intervals from a thickness position of an intermediate portion of the corresponding second capacitor electrode films 92 toward the electrode main surface side of the corresponding second capacitor electrode films 92.

[0404] Of course, the bottom walls of the plurality of pad openings 93 may be located closer to the first main surface 3 (main surface insulating film 48) than the thickness positions of the intermediate portions of the corresponding second capacitor electrode films 92. The plurality of pad openings 93 may be formed in a tapered shape toward the bottom walls. Of course, the plurality of pad openings 93 may be formed substantially perpendicular to the first main surface 3.

[0405] The pad openings 93 may be formed in a one-to-many correspondence with the second capacitor electrode films 92, respectively, and may be formed at intervals following the extension direction (first direction X) of the corresponding second capacitor electrode films 92. In this case, the pad openings 93 may be formed in a polygonal or circular shape in a planar view. The pad openings 93 may be formed in a quadrangular or hexagonal shape in a planar view.

[0406] The anode capacitor structure CA includes a plurality of pad via electrodes 94 embedded in the plurality of pad openings 93 in the anode pad region 11A. Each of the pad via electrodes 94 has a portion in contact with the interlayer film 57 and a corresponding second capacitor electrode film 92. The pad via electrodes 94 are mechanically and electrically connected to the corresponding second capacitor electrode film 92 in the corresponding pad opening 93.

[0407] Similar to the first emitter via electrode 59 , the pad via electrode 94 may have a laminated structure including a first electrode 60 and a second electrode 61 laminated in this order from the wall surface side of the pad opening 93 .

[0408] The first electrode 60 is formed in the form of a film on the wall surface of the pad opening 93, and is mechanically and electrically connected to the corresponding second capacitor electrode film 92 within the pad opening 93. The second electrode 61 is embedded in the pad opening 93 with the first electrode 60 in between, and is electrically connected to the corresponding second capacitor electrode film 92 via the first electrode 60.

[0409] The anode capacitor structure CA includes a pad electrode 95 disposed on the interlayer film 57 in the anode pad region 11A. The pad electrode 95 may also be referred to as a "pad," a "terminal electrode," an "external terminal," or the like.

[0410] The pad electrode 95 in the anode pad region 11A constitutes the anode pad AP described above. The anode pad AP is a terminal to which an anode potential is applied from the outside. The anode pad AP may also be referred to as an "anode pad electrode," an "anode terminal electrode," an "anode external terminal," or the like.

[0411] The anode pad AP is disposed on a portion of the interlayer film 57 that covers the plurality of first capacitor electrode films 90 (the plurality of capacitor structures 85) and the plurality of second capacitor electrode films 92. The anode pad AP is electrically insulated from the plurality of first capacitor electrode films 90 (the plurality of capacitor structures 85) by the interlayer film 57, and is electrically connected to the plurality of second capacitor electrode films 92 via the plurality of pad openings 93.

[0412] Specifically, the anode pad AP is mechanically and electrically connected to a plurality of pad via electrodes 94 on the interlayer film 57, and is electrically connected to a plurality of second capacitor electrode films 92 through the plurality of pad via electrodes 94. As a result, the anode potential applied to the anode pad AP is applied to the plurality of second capacitor electrode films 92.

[0413] The anode pad AP has a periphery positioned outward from the peripheries of the plurality of first capacitor electrode films 90 (plurality of capacitor structures 85) and the peripheries of the plurality of second capacitor electrode films 92 in a planar view, and collectively covers the plurality of first capacitor electrode films 90 (plurality of capacitor structures 85) and the plurality of second capacitor electrode films 92.

[0414] In this embodiment, the anode pad AP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The anode pad AP may also be formed in a hexagonal or circular shape in plan view.

[0415] The anode pad AP is mechanically and electrically connected to the anode wiring 75 on the interlayer film 57. As a result, the anode potential applied to the anode pad AP is applied to the temperature-sensitive diode structure D via the anode wiring 75.

[0416] The anode pad AP may have a thickness greater than that of the interlayer film 57. The thickness of the anode pad AP is preferably greater than that of the plurality of first capacitor electrode films 90 and that of the plurality of second capacitor electrode films 92.

[0417] The thickness of the anode pad AP may be 0.5 μm or more and 10 μm or less. The thickness of the anode pad AP may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 7 μm or more and 8 μm or less, 8 μm or more and 9 μm or less, and 9 μm or more and 10 μm or less.

[0418] Similar to the emitter pad EP, the anode pad AP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is electrically connected to a plurality of pad via electrodes 94 on the interlayer film 57.

[0419] The first electrode film 65 is connected to the first electrodes 60 of the plurality of pad via electrodes 94. Of course, the first electrode film 65 may cover the first electrodes 60 of the plurality of pad via electrodes 94. The first electrode film 65 is connected to the first electrode film 65 of the anode wiring 75 on the interlayer film 57.

[0420] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 covers the second electrodes 61 of the multiple pad via electrodes 94 in a film-like manner. The second electrode film 66 is connected to the second electrode film 66 of the anode wiring 75 on the first electrode film 65.

[0421] Referring again to Figures 1 and 3, the monitor capacitor structure CM, like the anode capacitor structure CA, includes a plurality of capacitor structures 85, a plurality of first capacitor electrode films 90, a main surface insulating film 48, a sidewall dielectric film 91, a plurality of second capacitor electrode films 92, an interlayer film 57, a plurality of pad openings 93, a plurality of pad via electrodes 94, and a pad electrode 95.

[0422] Similar to the multiple capacitor structures 85 associated with the anode capacitor structure CA, the multiple capacitor structures 85 associated with the monitor capacitor structure CM are drawn out from the active region 6 adjacent to them in the first direction X (the third active region 6C in this embodiment) to the monitor pad region 11M.

[0423] Of course, one or more capacitor structures 85 relating to the monitor capacitor structure CM may have one or more pull-out portions 85a extending in the second direction Y and may be connected to one or more emitter structures 30 of an active region 6 (e.g., the third active region 6C) adjacent to the second direction Y.

[0424] The configuration of the multiple first capacitor electrode films 90, the main surface insulating film 48, the sidewall dielectric film 91, the multiple second capacitor electrode films 92, the interlayer film 57, the multiple pad openings 93, and the multiple pad via electrodes 94 in the monitor region 7 is the same as the layout of the anode pad region 11A.

[0425] The pad electrode 95 in the monitor region 7 constitutes the aforementioned monitor pad MP. The monitor pad MP is a terminal to which a monitor potential is applied from the outside. The monitor pad MP may also be called a "monitor pad electrode," a "monitor terminal electrode," a "monitor external terminal," etc.

[0426] The monitor pad MP is disposed on a portion of the interlayer film 57 that covers the plurality of first capacitor electrode films 90 (the plurality of capacitor structures 85) and the plurality of second capacitor electrode films 92. The monitor pad MP is electrically insulated from the plurality of first capacitor electrode films 90 (the plurality of capacitor structures 85) by the interlayer film 57, and is electrically connected to the plurality of second capacitor electrode films 92 via the plurality of pad openings 93.

[0427] Specifically, the monitor pad MP is mechanically and electrically connected to a plurality of pad via electrodes 94 on the interlayer film 57, and is electrically connected to a plurality of second capacitor electrode films 92 via the plurality of pad via electrodes 94. As a result, the monitor potential applied to the monitor pad MP is applied to the plurality of second capacitor electrode films 92.

[0428] The monitor pad MP has a periphery positioned outward from the peripheries of the plurality of first capacitor electrode films 90 (plurality of capacitor structures 85) and the peripheries of the plurality of second capacitor electrode films 92 in a planar view, and collectively covers the plurality of first capacitor electrode films 90 (plurality of capacitor structures 85) and the plurality of second capacitor electrode films 92.

[0429] In this embodiment, the monitor pad MP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The monitor pad MP may also be formed in a hexagonal or circular shape in plan view.

[0430] The monitor pad MP is disposed on the first side surface 5A side of the monitor electrode 67, and has a lead portion that is led out toward the monitor electrode 67. The lead portion extends in a strip shape in the second direction Y, and is mechanically and electrically connected to the monitor electrode 67.

[0431] As a result, the monitor potential applied to the monitor pad MP is applied to the plurality of emitter structures 30, the plurality of emitter connection structures 35, the plurality of emitter regions 40 and the plurality of contact regions 41 via the monitor electrode 67, the plurality of first emitter via electrodes 59 and the plurality of second emitter via electrodes 63.

[0432] The monitor pad MP may have a thickness greater than that of the interlayer film 57. The thickness of the monitor pad MP is preferably greater than that of the plurality of first capacitor electrode films 90 and that of the plurality of second capacitor electrode films 92. The thickness range of the monitor pad MP is the same as that of the anode pad AP (not less than 0.5 μm and not more than 10 μm).

[0433] Similar to the emitter pad EP, the monitor pad MP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is electrically connected to a plurality of pad via electrodes 94 on the interlayer film 57.

[0434] The first electrode film 65 is connected to the first electrodes 60 of the plurality of pad via electrodes 94. Of course, the first electrode film 65 may cover the first electrodes 60 of the plurality of pad via electrodes 94. The first electrode film 65 is connected to the first electrode film 65 of the monitor electrode 67 on the interlayer film 57.

[0435] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 covers the second electrodes 61 of the multiple pad via electrodes 94 in a film-like manner. The second electrode film 66 is connected to the second electrode film 66 of the monitor electrode 67 on the first electrode film 65.

[0436] Similar to the anode capacitor structure CA, the cathode capacitor structure CC includes a plurality of capacitor structures 85, a plurality of first capacitor electrode films 90, a main surface insulating film 48, a sidewall dielectric film 91, a plurality of second capacitor electrode films 92, an interlayer film 57, a plurality of pad openings 93, a plurality of pad via electrodes 94, and a pad electrode 95.

[0437] The plurality of capacitor structures 85 relating to the cathode capacitor structure CC, like the plurality of capacitor structures 85 relating to the anode capacitor structure CA, are drawn out from the active region 6 adjacent in the first direction X (in this embodiment, the first active region 6A) to the cathode pad region 11C.

[0438] In this embodiment, the plurality of capacitor structures 85 associated with the cathode capacitor structure CC are connected to the plurality of capacitor structures 85 associated with the anode capacitor structure CA via a plurality of lead-out portions 85a.

[0439] That is, the plurality of capacitor structures 85 relating to the cathode capacitor structure CC are connected to the plurality of emitter structures 30 of the active region 6 (in this form, the first active region 6A) via the plurality of capacitor structures 85 relating to the anode capacitor structure CA.

[0440] Of course, one or more capacitor structures 85 relating to the cathode capacitor structure CC may have one or more pull-out portions 85a extending in the second direction Y and may be connected to one or more emitter structures 30 of an active region 6 (e.g., the second active region 6B) adjacent in the second direction Y.

[0441] The pad electrode 95 in the cathode pad region 11C constitutes the aforementioned cathode pad CaP. The cathode pad CaP is a terminal to which a cathode potential is applied from the outside. The cathode pad CaP may also be referred to as a "cathode pad electrode," a "cathode terminal electrode," a "cathode external terminal," or the like.

[0442] The cathode pad CaP is disposed on a portion of the interlayer film 57 that covers the plurality of first capacitor electrode films 90 (the plurality of capacitor structures 85 ) and the plurality of second capacitor electrode films 92 .

[0443] The cathode pad CaP is electrically insulated from the plurality of first capacitor electrode films 90 (the plurality of capacitor structures 85) by the interlayer film 57 and is electrically connected to the plurality of second capacitor electrode films 92 via the plurality of pad openings 93.

[0444] Specifically, the cathode pad CaP is mechanically and electrically connected to a plurality of pad via electrodes 94 on the interlayer film 57, and is electrically connected to a plurality of second capacitor electrode films 92 through the plurality of pad via electrodes 94. As a result, the cathode potential applied to the cathode pad CaP is applied to the plurality of second capacitor electrode films 92.

[0445] The cathode pad CaP has a periphery positioned outward from the peripheries of the plurality of first capacitor electrode films 90 (plurality of capacitor structures 85) and the peripheries of the plurality of second capacitor electrode films 92 in a planar view, and collectively covers the plurality of first capacitor electrode films 90 (plurality of capacitor structures 85) and the plurality of second capacitor electrode films 92.

[0446] In this embodiment, the cathode pad CaP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The cathode pad CaP may also be formed in a hexagonal or circular shape in plan view.

[0447] The cathode pad CaP is connected to the cathode wiring 76 on the interlayer film 57. As a result, the cathode potential applied to the cathode pad CaP is applied to the temperature sensitive diode structure D via the cathode wiring 76.

[0448] The cathode pad CaP may have a thickness greater than that of the interlayer film 57. The thickness of the cathode pad CaP is preferably greater than that of the plurality of first capacitor electrode films 90 and that of the plurality of second capacitor electrode films 92. The thickness range of the cathode pad CaP is the same as that of the anode pad AP (not less than 0.5 μm and not more than 10 μm).

[0449] Like the emitter pad EP, the cathode pad CaP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is electrically connected to a plurality of pad via electrodes 94 on the interlayer film 57.

[0450] The first electrode film 65 is connected to the first electrodes 60 of the plurality of pad via electrodes 94. Of course, the first electrode film 65 may cover the first electrodes 60 of the plurality of pad via electrodes 94. The first electrode film 65 is connected to the first electrode film 65 of the cathode wiring 76 on the interlayer film 57.

[0451] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 covers the second electrodes 61 of the multiple pad via electrodes 94 in a film-like manner. The second electrode film 66 is connected to the second electrode film 66 of the cathode wiring 76 on the first electrode film 65.

[0452] The semiconductor device 1A does not have a plurality of capacitor structures 85, a plurality of first capacitor electrode films 90, a sidewall dielectric film 91, a plurality of second capacitor electrode films 92, a plurality of pad openings 93, or a plurality of pad via electrodes 94 in the gate pad region 11G. In other words, the gate pad region 11G does not have a pad capacitor structure 84. This is because the capacitance value is guaranteed by the plurality of gate structures 20 arranged in the plurality of active regions 6.

[0453] The semiconductor device 1A includes a pad electrode 95 arranged on the interlayer film 57 in the gate pad region 11G. The pad electrode 95 in the gate pad region 11G constitutes the aforementioned gate pad GP. The gate pad GP is a terminal to which a gate potential is applied from the outside. The gate pad GP may also be referred to as a "gate pad electrode," a "gate terminal electrode," a "gate external terminal," or the like.

[0454] The gate pad GP faces the pad well region 80 with the main surface insulating film 48 and the interlayer film 57 sandwiched therebetween. It is preferable that the entire area of ​​the gate pad GP faces the pad well region 80. The gate pad GP is connected to the plurality of gate fingers 70 on the interlayer film 57. As a result, the gate potential applied to the gate pad GP is applied to the plurality of gate structures 20 via the plurality of gate wirings 56 and the plurality of gate fingers 70.

[0455] In this embodiment, the gate pad GP is formed in a polygonal shape (a quadrangle in this embodiment) in plan view having four sides parallel to the periphery of the chip 2. The gate pad GP may also be formed in a hexagonal or circular shape in plan view.

[0456] The gate pad GP may have a thickness greater than that of the interlayer film 57. The thickness of the gate pad GP is preferably greater than the thickness of the plurality of first capacitor electrode films 90 and the thickness of the plurality of second capacitor electrode films 92. The thickness range of the gate pad GP is the same as the thickness range of the anode pad AP (0.5 μm or more and 10 μm or less).

[0457] Like the emitter pad EP, the gate pad GP may have a laminated structure including a first electrode film 65 and a second electrode film 66 laminated in this order from the interlayer film 57 side. The first electrode film 65 covers the interlayer film 57 in a film-like manner as a barrier electrode. The first electrode film 65 is connected to the first electrode films 65 of the multiple gate fingers 70 on the interlayer film 57.

[0458] The second electrode film 66 has a thickness greater than that of the first electrode film 65, and covers the first electrode film 65 in a film-like manner. The second electrode film 66 is connected to the second electrode films 66 of the multiple gate fingers 70 on the first electrode film 65.

[0459] The semiconductor device 1A includes a collector pad CoP covering the second main surface 4. The collector pad CoP is a terminal to which a collector potential is applied from the outside. The collector pad CoP may also be referred to as a "collector pad electrode," a "collector terminal electrode," an "external collector terminal," or the like. The collector pad CoP is formed in the form of a film along the second main surface 4 and is electrically connected to the collector region 14.

[0460] The collector pad CoP covers, from the second main surface 4 side, the multiple active regions 6, the monitor region 7, the outer periphery region 8, the multiple street regions 9, the multiple temperature measurement regions 10, and the multiple pad regions 11. The collector pad CoP may cover the entire second main surface 4. Of course, the collector pad CoP may be formed at a distance inward from the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D), leaving the periphery of the second main surface 4 exposed (collector region 14).

[0461] A breakdown voltage that can be applied between the emitter pad EP and the collector pad CoP (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0462] Other layout examples of capacitor structures 85 are shown below. Figures 20A to 20M are plan views showing pad capacitor structures 84 according to second to fourteenth layout examples. Each of the multiple pad capacitor structures 84 may include at least one of the pad capacitor structures 84 according to the second to fourteenth layout examples, instead of or in addition to the pad capacitor structure 84 according to the first layout example.

[0463] That is, the monitor capacitor structure CM may include at least one of the pad capacitor structures 84 according to the first to fourteenth layout examples in the monitor pad region 11M. The anode capacitor structure CA may include at least one of the pad capacitor structures 84 according to the first to fourteenth layout examples in the anode pad region 11A.

[0464] The cathode capacitor structure CC may include at least one of the pad capacitor structures 84 according to the first to fourteenth layout examples in the cathode pad region 11C. The monitor capacitor structure CM, the anode capacitor structure CA, and the cathode capacitor structure CC do not necessarily have to have the pad capacitor structure 84 according to the same layout example, and may have pad capacitor structures 84 according to different layout examples.

[0465] 20A (second layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the first direction X and one second capacitor structure 85B extending in the second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0466] Each of the first capacitor structures 85A has a base end portion on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end portion on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base end portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0467] The second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to the tip ends of the plurality of first capacitor structures 85A. That is, the plurality of capacitor structures 85 form a single comb-tooth-shaped capacitor structure 85 in plan view. Of course, the second capacitor structure 85B may be connected to regions on the base end side of the plurality of first capacitor structures 85A.

[0468] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a second electrode film 90b connected to a second capacitor structure 85B.

[0469] The multiple first electrode films 90a extend in stripes in the first direction X, following the layout of the multiple first capacitor structures 85A. The second electrode film 90b extends in stripes in the second direction Y, following the layout of the second capacitor structures 85B, and is connected to the multiple first electrode films 90a. As a result, the multiple first capacitor electrode films 90 form one comb-shaped first capacitor electrode film 90 in a plan view.

[0470] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the second electrode films 90b, respectively. The sidewall dielectric film 91 on the second electrode film 90b side is connected to the plurality of sidewall dielectric films 91 on the first electrode films 90a side at the connection portion between the plurality of first electrode films 90a and the second electrode films 90b.

[0471] As in the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. As in the first layout example, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the first direction X. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the second direction Y.

[0472] The plurality of second capacitor electrode films 92 includes a plurality of inner second capacitor electrode films 92 and a plurality of outer second capacitor electrode films 92. The plurality of inner second capacitor electrode films 92 are respectively arranged in regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b.

[0473] The inner second capacitor electrode films 92 face the first electrode films 90a in the second direction Y and have portions that form capacitive coupling with the first electrode films 90a via the sidewall dielectric films 91. The inner second capacitor electrode films 92 face the second electrode films 90b in the first direction X and have portions that form capacitive coupling with the second electrode films 90b via the sidewall dielectric films 91.

[0474] The outer second capacitor electrode films 92 are respectively disposed on both sides of the outer first capacitor electrode films 90 in the second direction Y. The outer second capacitor electrode films 92 each face the first electrode film 90 a in the second direction Y, and each have a portion that forms capacitive coupling with the first electrode film 90 a via the sidewall dielectric film 91.

[0475] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the second direction Y and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode film 90b in the first direction X and may not form a capacitive coupling with the second electrode film 90b.

[0476] 20B (third layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the first direction X and a plurality of second capacitor structures 85B extending in the second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0477] Each of the first capacitor structures 85A has a base end portion on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end portion on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base end portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0478] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the first direction X. One of the second capacitor structures 85B extends in a strip shape in the second direction Y and is connected to the tip ends of the first capacitor structures 85A.

[0479] The other second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to regions on the base end side of the plurality of first capacitor structures 85A. In other words, the plurality of capacitor structures 85 form a single ladder-shaped capacitor structure 85 in plan view.

[0480] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0481] The first electrode films 90a extend in stripes in the first direction X, following the layout of the first capacitor structures 85A. The second electrode films 90b extend in strips in the second direction Y, following the layout of the second capacitor structures 85B, and are connected to the first electrode films 90a.

[0482] The second electrode films 90b and the first electrode films 90a define a plurality of space regions each extending in the first direction X. As a result, the first capacitor electrode films 90 form a single ladder-shaped first capacitor electrode film 90 in plan view.

[0483] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0484] As in the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. As in the first layout example, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the first direction X. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the second direction Y.

[0485] The plurality of second capacitor electrode films 92 includes a plurality of inner second capacitor electrode films 92 and a plurality of outer second capacitor electrode films 92. The plurality of inner second capacitor electrode films 92 are respectively arranged in a plurality of space regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b.

[0486] The inner second capacitor electrode films 92 face the plurality of first electrode films 90 a in the second direction Y and have portions that form capacitive coupling with the plurality of first electrode films 90 a via the plurality of sidewall dielectric films 91. The inner second capacitor electrode films 92 face the plurality of second electrode films 90 b in the first direction X and have portions that form capacitive coupling with the plurality of second electrode films 90 b via the plurality of sidewall dielectric films 91.

[0487] The outer second capacitor electrode films 92 are respectively disposed on both sides of the outer first capacitor electrode films 90 in the second direction Y. The outer second capacitor electrode films 92 each face the first electrode film 90 a in the second direction Y, and each have a portion that forms capacitive coupling with the first electrode film 90 a via the sidewall dielectric film 91.

[0488] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the second direction Y and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode films 90b in the first direction X and may not form a capacitive coupling with the second electrode films 90b.

[0489] 20C (fourth layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the first direction X and a plurality of second capacitor structures 85B extending in the second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0490] Each of the first capacitor structures 85A has a base end portion on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end portion on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base end portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0491] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the first direction X. One of the second capacitor structures 85B is formed at intervals in the second direction Y and is connected to the tip ends of the first capacitor structures 85A (two in this embodiment) adjacent to each other in the second direction Y.

[0492] The other plurality of second capacitor structures 85B are formed at intervals in the second direction Y so as to face one of the plurality of second capacitor structures 85B in a one-to-one correspondence in the first direction X, and are respectively connected to regions on the base end side of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the second direction Y. In other words, the plurality of capacitor structures 85 form a plurality of annular (quadratic annular) capacitor structures 85 each extending in the first direction X in a plan view.

[0493] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0494] The first electrode films 90a extend in stripes in the first direction X, following the layout of the first capacitor structures 85A. The second electrode films 90b extend in strips in the second direction Y, following the layout of the second capacitor structures 85B, and are connected to the first electrode films 90a.

[0495] The second electrode films 90b define a plurality of space regions that extend from the first electrode films 90a in the first direction X. As a result, the first capacitor electrode films 90 form a plurality of annular (quadratic annular) first capacitor electrode films 90 that extend in the first direction X in plan view.

[0496] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0497] As in the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. As in the first layout example, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the first direction X. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the second direction Y.

[0498] The plurality of second capacitor electrode films 92 includes a plurality of inner second capacitor electrode films 92 and a plurality of outer second capacitor electrode films 92. The plurality of inner second capacitor electrode films 92 are respectively arranged in space regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b.

[0499] The inner second capacitor electrode films 92 face the plurality of first electrode films 90 a in the second direction Y and have portions that form capacitive coupling with the plurality of first electrode films 90 a via the plurality of sidewall dielectric films 91. The inner second capacitor electrode films 92 face the plurality of second electrode films 90 b in the first direction X and have portions that form capacitive coupling with the plurality of second electrode films 90 b via the plurality of sidewall dielectric films 91.

[0500] The outer second capacitor electrode films 92 are each disposed in a region between a plurality of space regions adjacent to each other in the second direction Y. The outer second capacitor electrode films 92 each face the first electrode films 90 a in the second direction Y, and each have a portion that forms capacitive coupling with the first electrode films 90 a via a plurality of sidewall dielectric films 91.

[0501] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode films 90b in the second direction Y and forms capacitive coupling with the second electrode films 90b via the sidewall dielectric films 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode films 90b in the first direction X and may not form capacitive coupling with the second electrode films 90b.

[0502] The second capacitor electrode films 92 may include a plurality of outer second capacitor electrode films 92 arranged on both sides of the plurality of first capacitor electrode films 90 in the second direction Y. The plurality of outer second capacitor electrode films 92 may each have a portion that faces the first electrode film 90a in the second direction Y and forms a capacitive coupling with the first electrode film 90a via the sidewall dielectric film 91.

[0503] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the second direction Y and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode films 90b in the first direction X and may not form a capacitive coupling with the second electrode films 90b.

[0504] 20D (fifth layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this embodiment, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the first direction X and a plurality of second capacitor structures 85B extending in the second direction Y. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0505] Each of the first capacitor structures 85A has a base end portion on one side (the third side surface 5C side) in the longitudinal direction (first direction X) and a tip end portion on the other side (the fourth side surface 5D side) in the longitudinal direction (first direction X). The base end portions of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0506] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the first direction X. One of the second capacitor structures 85B is formed at intervals in the second direction Y and is connected to the tip ends of the first capacitor structures 85A (two in this embodiment) adjacent to each other in the second direction Y.

[0507] The other plurality of second capacitor structures 85B are arranged offset in the second direction Y with respect to one of the plurality of second capacitor structures 85B so as to face the two second capacitor structures 85B in the first direction X. The other plurality of second capacitor structures 85B are formed spaced apart in the second direction Y and are respectively connected to regions on the base end side of the plurality of (two in this embodiment) first capacitor structures 85A adjacent in the second direction Y.

[0508] That is, the plurality of capacitor structures 85 form one zigzag capacitor structure 85 having a portion extending in the first direction X and a portion extending in the second direction Y in a plan view.

[0509] One end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a. The other end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a.

[0510] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0511] The first electrode films 90a extend in stripes in the first direction X, following the layout of the first capacitor structures 85A. The second electrode films 90b extend in strips in the second direction Y, following the layout of the second capacitor structures 85B, and are connected to the first electrode films 90a.

[0512] As a result, the plurality of first capacitor electrode films 90 form one zigzag first capacitor electrode film 90 having a portion extending in the first direction X and a portion extending in the second direction Y in plan view.

[0513] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0514] As in the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. As in the first layout example, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the first direction X. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the second direction Y.

[0515] The plurality of second capacitor electrode films 92 includes one plurality of second capacitor electrode films 92 and another plurality of second capacitor electrode films 92. One of the plurality of second capacitor electrode films 92 is disposed in an area defined by the plurality of first electrode films 90 a and one of the second electrode films 90 b.

[0516] One of the plurality of second capacitor electrode films 92 faces the plurality of first electrode films 90a in the second direction Y, and has a portion that forms capacitive coupling with the plurality of first electrode films 90a via the plurality of sidewall dielectric films 91. One of the plurality of second capacitor electrode films 92 faces one of the second electrode films 90b in the first direction X, and has a portion that forms capacitive coupling with one of the second electrode films 90b via the sidewall dielectric film 91.

[0517] The other plurality of second capacitor electrode films 92 are respectively arranged in regions defined by the plurality of first electrode films 90 a and the other second electrode films 90 b. The other plurality of second capacitor electrode films 92 face the plurality of first electrode films 90 a in the second direction Y and have portions that form capacitive coupling with the plurality of first electrode films 90 a via the plurality of sidewall dielectric films 91.

[0518] The other of the plurality of second capacitor electrode films 92 faces the other of the second electrode films 90b in the first direction X and has a portion that forms capacitive coupling with the other of the second electrode films 90b via the sidewall dielectric film 91.

[0519] The second capacitor electrode films 92 may include a plurality of outer second capacitor electrode films 92 arranged on both sides of the plurality of first capacitor electrode films 90 in the second direction Y. The plurality of outer second capacitor electrode films 92 may each have a portion that faces the first electrode film 90a in the second direction Y and forms a capacitive coupling with the first electrode film 90a via the sidewall dielectric film 91.

[0520] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the second direction Y and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode films 90b in the first direction X and may not form a capacitive coupling with the second electrode films 90b.

[0521] 20E (sixth layout example), similar to the first layout example, pad capacitor structure 84 includes a plurality of capacitor structures 85. The plurality of capacitor structures 85 have a layout in which the extension direction of pad capacitor structure 84 according to the first layout example is changed from the first direction X to the second direction Y.

[0522] That is, the plurality of capacitor structures 85 extend in a stripe pattern in the second direction Y. In this embodiment, the extension direction of the plurality of capacitor structures 85 intersects (specifically, is perpendicular to) the extension direction of the plurality of gate structures 20 (the plurality of emitter structures 30).

[0523] In this embodiment, the lead-out portions 85 a of the plurality of capacitor structures 85 extend in the second direction Y and are led out from the anode pad region 11A to one or more active regions 6. The plurality of lead-out portions 85 a are connected to the plurality of emitter structures 30 in the one or more active regions 6, respectively.

[0524] The multiple lead portions 85a may be connected to multiple emitter connection structures 35 in one or multiple active regions 6. The multiple lead portions 85a may have portions extending in the first direction X in a region outside the anode pad region 11A.

[0525] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 extend in stripes in the second direction Y, following the layout of the plurality of capacitor structures 85.

[0526] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. The second capacitor electrode films 92 are arranged in stripes extending along the second direction Y, following the layout of the first capacitor electrode films 90. In this embodiment, the second capacitor electrode films 92 and the first capacitor electrode films 90 are arranged alternately in the first direction X.

[0527] The multiple second capacitor electrode films 92 face one or more first capacitor electrode films 90 in the first direction X and form capacitive coupling with one or more first capacitor electrode films 90 via one or more sidewall dielectric films 91.

[0528] 20F (seventh layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this embodiment, like the sixth layout example, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the second direction Y and one second capacitor structure 85B extending in the first direction X. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0529] Each of the first capacitor structures 85A has a tip end on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base end on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0530] The second capacitor structure 85B extends in a strip shape in the first direction X and is connected to the tip ends of the plurality of first capacitor structures 85A. That is, the plurality of capacitor structures 85A form a single comb-tooth-shaped capacitor structure 85 in plan view. Of course, the second capacitor structure 85B may be connected to regions on the base end side of the plurality of second capacitor structures 85B.

[0531] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a second electrode film 90b connected to a second capacitor structure 85B.

[0532] The multiple first electrode films 90a extend in stripes in the second direction Y, following the layout of the multiple first capacitor structures 85A. The second electrode film 90b extends in stripes in the first direction X, following the layout of the second capacitor structures 85B, and is connected to the multiple first electrode films 90a. As a result, the multiple first capacitor electrode films 90 form a single comb-tooth-shaped first capacitor electrode film 90 in a plan view.

[0533] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the second electrode films 90b, respectively. The sidewall dielectric film 91 on the second electrode film 90b side is connected to the plurality of sidewall dielectric films 91 on the first electrode films 90a side at the connection portion between the plurality of first electrode films 90a and the second electrode films 90b.

[0534] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. In this embodiment, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the second direction Y. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the first direction X.

[0535] The plurality of second capacitor electrode films 92 includes a plurality of inner second capacitor electrode films 92 and a plurality of outer second capacitor electrode films 92. The plurality of inner second capacitor electrode films 92 are respectively arranged in regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b.

[0536] The inner second capacitor electrode films 92 face the first electrode films 90 a in the first direction X and have portions that form capacitive coupling with the first electrode films 90 a via the sidewall dielectric films 91. The inner second capacitor electrode films 92 face the second electrode films 90 b in the second direction Y and have portions that form capacitive coupling with the second electrode films 90 b via the sidewall dielectric films 91.

[0537] The outer second capacitor electrode films 92 are respectively disposed on both sides of the outer first capacitor electrode films 90 in the first direction X. The outer second capacitor electrode films 92 each face the first electrode film 90 a in the first direction X, and each have a portion that forms capacitive coupling with the first electrode film 90 a via the sidewall dielectric film 91.

[0538] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the first direction X and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode film 90b in the second direction Y and may not form a capacitive coupling with the second electrode film 90b.

[0539] 20G (eighth layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this embodiment, like the sixth layout example, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X. In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0540] Each of the first capacitor structures 85A has a tip end on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base end on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0541] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the second direction Y. One of the second capacitor structures 85B extends in a strip shape in the second direction Y and is connected to the tip ends of the first capacitor structures 85A.

[0542] The other second capacitor structure 85B extends in a strip shape in the second direction Y and is connected to regions on the base end side of the plurality of first capacitor structures 85A. In other words, the plurality of capacitor structures 85 form a single ladder-shaped capacitor structure 85 in plan view.

[0543] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0544] The plurality of first electrode films 90a extend in stripes in the second direction Y, following the layout of the plurality of first capacitor structures 85A. The plurality of second electrode films 90b extend in strips in the first direction X, following the layout of the plurality of second capacitor structures 85B, and are connected to the plurality of first electrode films 90a.

[0545] The second electrode films 90b and the first electrode films 90a define a plurality of space regions each extending in the first direction X. As a result, the first capacitor electrode films 90 form a single ladder-shaped first capacitor electrode film 90 in plan view.

[0546] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0547] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. In this embodiment, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the second direction Y. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the first direction X.

[0548] The plurality of second capacitor electrode films 92 includes a plurality of inner second capacitor electrode films 92 and a plurality of outer second capacitor electrode films 92. The plurality of inner second capacitor electrode films 92 are respectively arranged in a plurality of space regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b.

[0549] The inner second capacitor electrode films 92 face the plurality of first electrode films 90 a in the first direction X and have portions that form capacitive coupling with the plurality of first electrode films 90 a via the plurality of sidewall dielectric films 91. The inner second capacitor electrode films 92 face the plurality of second electrode films 90 b in the second direction Y and have portions that form capacitive coupling with the plurality of second electrode films 90 b via the plurality of sidewall dielectric films 91.

[0550] The outer second capacitor electrode films 92 are respectively disposed on both sides of the outer first capacitor electrode films 90 in the first direction X. The outer second capacitor electrode films 92 each face the first electrode film 90 a in the first direction X, and each have a portion that forms capacitive coupling with the first electrode film 90 a via the sidewall dielectric film 91.

[0551] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the first direction X and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode films 90b in the second direction Y and may not form a capacitive coupling with the second electrode films 90b.

[0552] 20H (ninth layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this configuration, like the sixth layout example, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X. In this configuration, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0553] Each of the first capacitor structures 85A has a tip end on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base end on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0554] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the second direction Y. One of the second capacitor structures 85B is formed at intervals in the first direction X and is respectively connected to the tip ends of the first capacitor structures 85A (two in this embodiment) adjacent to each other in the first direction X.

[0555] The other plurality of second capacitor structures 85B are formed at intervals in the first direction X so as to face the one plurality of first capacitor structures 85A in a one-to-one correspondence in the second direction Y, and are respectively connected to regions on the base end side of the plurality of (two in this embodiment) first capacitor structures 85A adjacent in the first direction X. In other words, the plurality of capacitor structures 85 form a ring-shaped (quadratic ring-shaped) plurality of capacitor structures 85 extending in the second direction Y in a plan view.

[0556] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0557] The plurality of first electrode films 90a extend in stripes in the second direction Y, following the layout of the plurality of first capacitor structures 85A. The plurality of second electrode films 90b extend in strips in the first direction X, following the layout of the plurality of second capacitor structures 85B, and are connected to the plurality of first electrode films 90a.

[0558] The second electrode films 90b define a plurality of space regions that extend from the first electrode films 90a in the second direction Y. As a result, the first capacitor electrode films 90 form a plurality of annular (quadratic) first capacitor electrode films 90 that extend in the second direction Y in a plan view.

[0559] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0560] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. In this embodiment, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the second direction Y. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the first direction X.

[0561] The plurality of second capacitor electrode films 92 includes a plurality of inner second capacitor electrode films 92 and a plurality of outer second capacitor electrode films 92. The plurality of inner second capacitor electrode films 92 are respectively arranged in a plurality of space regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b.

[0562] The inner second capacitor electrode films 92 face the plurality of first electrode films 90 a in the first direction X and have portions that form capacitive coupling with the plurality of first electrode films 90 a via the plurality of sidewall dielectric films 91. The inner second capacitor electrode films 92 face the plurality of second electrode films 90 b in the second direction Y and have portions that form capacitive coupling with the plurality of second electrode films 90 b via the plurality of sidewall dielectric films 91.

[0563] The outer second capacitor electrode films 92 are each disposed in a region between a plurality of space regions adjacent to each other in the first direction X. The outer second capacitor electrode films 92 each face the first electrode films 90 a in the first direction X, and each have a portion that forms capacitive coupling with the first electrode films 90 a via a plurality of sidewall dielectric films 91. The second capacitor electrode film 92 may include a plurality of second capacitor electrode films 92 disposed on both sides of the first capacitor electrode films 90 in the first direction X.

[0564] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode films 90b in the first direction X and forms capacitive coupling with the second electrode films 90b via the sidewall dielectric films 91. The outer second capacitor electrode films 92 may be formed spaced apart from the second electrode films 90b in the second direction Y and may not form capacitive coupling with the second electrode films 90b.

[0565] The second capacitor electrode films 92 may include a plurality of outer second capacitor electrode films 92 arranged on both sides of the plurality of first capacitor electrode films 90 in the first direction X. The plurality of outer second capacitor electrode films 92 may each have a portion facing the first electrode film 90 a in the first direction X and forming a capacitive coupling with the first electrode film 90 a via the sidewall dielectric film 91.

[0566] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the first direction X and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode films 90b in the second direction Y and may not form a capacitive coupling with the second electrode films 90b.

[0567] 20I (tenth layout example), the pad capacitor structure 84, like the first layout example, includes a plurality of capacitor structures 85. In this configuration, like the sixth layout example, the plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in the second direction Y and a plurality of second capacitor structures 85B extending in the first direction X. In this configuration, the plurality of first capacitor structures 85A have a plurality of lead portions 85a.

[0568] Each of the first capacitor structures 85A has a tip end on one side (the first side surface 5A side) in the longitudinal direction (the second direction Y) and a base end on the other side (the second side surface 5B side) in the longitudinal direction (the second direction Y). The base ends of the first capacitor structures 85A are boundaries between the lead portions 85a and the pad electrodes 95 (anode pads AP).

[0569] The second capacitor structures 85B are respectively arranged in a region on the tip end side and a region on the base end side of the first capacitor structures 85A in the second direction Y. One of the second capacitor structures 85B is formed at intervals in the first direction X and is respectively connected to the tip ends of the first capacitor structures 85A (two in this embodiment) adjacent to each other in the first direction X.

[0570] The other plurality of second capacitor structures 85B are arranged offset in the first direction X relative to the plurality of second capacitor structures 85B so as to face the two second capacitor structures 85B in the second direction Y. The other plurality of second capacitor structures 85B are formed at intervals in the first direction X and are respectively connected to regions on the base end side of the plurality of (two in this embodiment) first capacitor structures 85A adjacent to each other in the first direction X.

[0571] That is, the plurality of capacitor structures 85 constitute a single zigzag-shaped capacitor structure 85 having a portion extending in the first direction X and a portion extending in the second direction Y in a plan view. One end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a. The other end of the zigzag-shaped capacitor structure 85 is electrically connected to one or more emitter structures 30 via the lead-out portion 85a.

[0572] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0573] The plurality of first electrode films 90a extend in stripes in the second direction Y, following the layout of the plurality of first capacitor structures 85A. The plurality of second electrode films 90b extend in strips in the first direction X, following the layout of the plurality of second capacitor structures 85B, and are connected to the plurality of first electrode films 90a.

[0574] As a result, the plurality of first capacitor electrode films 90 form one zigzag first capacitor electrode film 90 having a portion extending in the first direction X and a portion extending in the second direction Y in plan view.

[0575] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0576] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. In this embodiment, the plurality of second capacitor electrode films 92 are arranged in stripes extending along the second direction Y. In this embodiment, the plurality of second capacitor electrode films 92 are arranged alternately with the plurality of first electrode films 90a in the first direction X.

[0577] The plurality of second capacitor electrode films 92 includes one plurality of second capacitor electrode films 92 and another plurality of second capacitor electrode films 92. One of the plurality of second capacitor electrode films 92 is disposed in an area defined by the plurality of first electrode films 90 a and one of the second electrode films 90 b.

[0578] One of the plurality of second capacitor electrode films 92 faces the plurality of first electrode films 90a in the first direction X and has a portion that forms capacitive coupling with the plurality of first electrode films 90a via the plurality of sidewall dielectric films 91. One of the plurality of second capacitor electrode films 92 faces one of the second electrode films 90b in the second direction Y and has a portion that forms capacitive coupling with one of the second electrode films 90b via the sidewall dielectric film 91.

[0579] The other plurality of second capacitor electrode films 92 are respectively arranged in regions defined by the plurality of first electrode films 90 a and the other second electrode films 90 b. The other plurality of second capacitor electrode films 92 face the plurality of first electrode films 90 a in the first direction X and have portions that form capacitive coupling with the plurality of first electrode films 90 a via the plurality of sidewall dielectric films 91.

[0580] The other of the plurality of second capacitor electrode films 92 faces the other of the second electrode films 90b in the second direction Y and has a portion that forms capacitive coupling with the other of the second electrode films 90b via the sidewall dielectric film 91.

[0581] The second capacitor electrode films 92 may include a plurality of outer second capacitor electrode films 92 arranged on both sides of the plurality of first capacitor electrode films 90 in the first direction X. The plurality of outer second capacitor electrode films 92 may each have a portion facing the first electrode film 90 a in the first direction X and forming a capacitive coupling with the first electrode film 90 a via the sidewall dielectric film 91.

[0582] The outer second capacitor electrode films 92 may each have a portion that faces the second electrode film 90b in the first direction X and forms a capacitive coupling with the second electrode film 90b via the sidewall dielectric film 91. The outer second capacitor electrode films 92 may be formed at intervals from the second electrode films 90b in the second direction Y and may not form a capacitive coupling with the second electrode films 90b.

[0583] 20J (eleventh layout example), similar to the first layout example, pad capacitor structure 84 includes a plurality of capacitor structures 85. The plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in a first direction X and a plurality of second capacitor structures 85B extending in a second direction Y.

[0584] In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a. Of course, the plurality of second capacitor structures 85B may also have a plurality of lead portions 85a.

[0585] The second capacitor structures 85B are each disposed in a region between the first capacitor structures 85A adjacent to each other in the second direction Y, and are arranged at intervals in the first direction X. The second capacitor structures 85B disposed on one side of one first capacitor structure 85A in the second direction Y face the second capacitor structures 85B disposed on the other side of one first capacitor structure 85A in the second direction Y, in a one-to-one correspondence.

[0586] The second capacitor structures 85B form a plurality of crosses with the first capacitor structures 85A, and define a plurality of mesa portions arranged in a matrix in the first direction X and the second direction Y. In other words, the capacitor structures 85 constitute one capacitor structure 85 that extends in a lattice (mesh) shape along the first direction X and the second direction Y in plan view.

[0587] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0588] The plurality of first electrode films 90a extend in stripes in the second direction Y, following the layout of the plurality of first capacitor structures 85A. The plurality of second electrode films 90b extend in stripes in the second direction Y, following the layout of the plurality of second capacitor structures 85B, and are connected to the plurality of first electrode films 90a.

[0589] The second electrode films 90b form a plurality of crosses with the first electrode films 90a, and define a plurality of space regions arranged in a matrix in the first direction X and the second direction Y. In other words, the first capacitor electrode films 90 form one first capacitor electrode film 90 that extends in a lattice (mesh) shape along the first direction X and the second direction Y in a plan view.

[0590] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0591] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. In this embodiment, the plurality of second capacitor electrode films 92 are respectively arranged in a plurality of space regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b. That is, the plurality of second capacitor electrode films 92 are arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view.

[0592] The second capacitor electrode films 92 face the first electrode films 90a in the second direction Y, and each have a portion that forms capacitive coupling with the first electrode films 90a via the sidewall dielectric films 91. The second capacitor electrode films 92 face the second electrode films 90b in the first direction X, and each have a portion that forms capacitive coupling with the second electrode films 90b via the sidewall dielectric films 91.

[0593] 20K (twelfth layout example), similar to the first layout example, pad capacitor structure 84 includes a plurality of capacitor structures 85. The plurality of capacitor structures 85 includes a plurality of first capacitor structures 85A extending in a stripe pattern in a first direction X and a plurality of second capacitor structures 85B extending in a second direction Y.

[0594] In this embodiment, the plurality of first capacitor structures 85A have a plurality of lead portions 85a. Of course, the plurality of second capacitor structures 85B may also have a plurality of lead portions 85a.

[0595] The multiple second capacitor structures 85B are respectively arranged in regions between multiple first capacitor structures 85A adjacent to each other in the second direction Y, and are arranged at intervals in the first direction X. The multiple second capacitor structures 85B arranged on one side of one first capacitor structure 85A in the second direction Y face the regions between the multiple second capacitor structures 85B arranged on the other side of one first capacitor structure 85A in the second direction Y in a one-to-one correspondence.

[0596] The second capacitor structures 85B form a plurality of T-junctions with the first capacitor structures 85A, and define a plurality of mesa portions arranged in a staggered pattern in the first direction X and the second direction Y. In other words, the capacitor structures 85 constitute a single capacitor structure 85 that extends in a staggered pattern (mesh pattern) along the first direction X and the second direction Y in a plan view.

[0597] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the plurality of first capacitor electrode films 90 includes a plurality of first electrode films 90a connected to a plurality of first capacitor structures 85A and a plurality of second electrode films 90b connected to a plurality of second capacitor structures 85B.

[0598] The plurality of first electrode films 90a extend in stripes in the second direction Y, following the layout of the plurality of first capacitor structures 85A. The plurality of second electrode films 90b are respectively disposed in regions between the plurality of first electrode films 90a adjacent in the second direction Y, following the layout of the plurality of second capacitor structures 85B, and are arranged at intervals in the first direction X.

[0599] The multiple second electrode films 90b arranged on one side of one first electrode film 90a in the second direction Y each face the area between the multiple second electrode films 90b arranged on the other side of one first electrode film 90a in the second direction Y in a one-to-one correspondence.

[0600] The second electrode films 90b form a plurality of T-junctions with the first electrode films 90a, and define a plurality of space regions arranged in a staggered pattern in the first direction X and the second direction Y. In other words, the first capacitor electrode films 90 constitute one first capacitor electrode film 90 that extends in a staggered pattern (mesh pattern) along the first direction X and the second direction Y in a plan view.

[0601] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of sidewall dielectric films 91. The plurality of sidewall dielectric films 91 cover the sidewalls of the plurality of first electrode films 90a and the sidewalls of the plurality of second electrode films 90b, respectively. The plurality of sidewall dielectric films 91 on the side of the plurality of second electrode films 90b are connected to the plurality of sidewall dielectric films 91 on the side of the plurality of first electrode films 90a at the connection portions between the plurality of first electrode films 90a and the plurality of second electrode films 90b.

[0602] Similar to the first layout example, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. In this embodiment, the plurality of second capacitor electrode films 92 are respectively arranged in a plurality of space regions defined by the plurality of first electrode films 90 a and the plurality of second electrode films 90 b. That is, the plurality of second capacitor electrode films 92 are arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view.

[0603] The second capacitor electrode films 92 face the first electrode films 90a in the second direction Y, and each have a portion that forms capacitive coupling with the first electrode films 90a via the sidewall dielectric films 91. The second capacitor electrode films 92 face the second electrode films 90b in the first direction X, and each have a portion that forms capacitive coupling with the second electrode films 90b via the sidewall dielectric films 91.

[0604] 20L (thirteenth layout example), pad capacitor structure 84 includes a single capacitor structure 85 formed in a spiral shape in plan view. In this embodiment, capacitor structure 85 is formed in a polygonal spiral shape (a square spiral shape in this embodiment) and has multiple portions extending in a first direction X and multiple portions extending in a second direction Y. Capacitor structure 85 may also be formed in a hexagonal spiral shape, a circular spiral shape, or the like.

[0605] The capacitor structure 85 defines a mesa portion that extends spirally on the first main surface 3. An outer end of the spiral capacitor structure 85 is electrically connected to one or more emitter structures 30 via an extension portion 85a. The extension portion 85a may be extended in the first direction X or in the second direction Y.

[0606] In this embodiment, the pad capacitor structure 84 includes a single first capacitor electrode film 90 formed in a spiral shape in a plan view. The first capacitor electrode film 90 extends spirally following the extension direction (spiral direction) of the capacitor structure 85, and is connected to the entire area of ​​the capacitor structure 85.

[0607] The first capacitor electrode film 90 defines a space region that extends spirally following the mesa portion on the first main surface 3 (main surface insulating film 48). The first capacitor electrode film 90 has a plurality of portions that extend in the first direction X and a plurality of portions that extend in the second direction Y.

[0608] In this embodiment, the pad capacitor structure 84 includes a single sidewall dielectric film 91. The sidewall dielectric film 91 covers the sidewall of the first capacitor electrode film 90 along the spiral direction. That is, the sidewall dielectric film 91 has multiple portions extending in the first direction X and multiple portions extending in the second direction Y.

[0609] In this embodiment, the pad capacitor structure 84 includes a single second capacitor electrode film 92 formed in a spiral shape in a plan view. The second capacitor electrode film 92 is disposed in a space region defined by the first capacitor electrode film 90. The second capacitor electrode film 92 extends in a spiral shape along the space region. The second capacitor electrode film 92 has a plurality of portions extending in the first direction X and a plurality of portions extending in the second direction Y.

[0610] The second capacitor electrode film 92 has a portion that faces the first capacitor electrode film 90 in the second direction Y in a portion extending in the first direction X and forms a capacitive coupling with the first capacitor electrode film 90 via the sidewall dielectric film 91. The second capacitor electrode film 92 has a portion that faces the first capacitor electrode film 90 in the first direction X in a portion extending in the second direction Y and forms a capacitive coupling with the first capacitor electrode film 90 via the sidewall dielectric film 91.

[0611] 20M (fourteenth layout example), pad capacitor structure 84 may include two or more layout regions 97. For example, the number of layout regions 97 may be ten or less. In this embodiment, pad capacitor structure 84 includes, as an example, four layout regions 97.

[0612] The multiple layout regions 97 may be arranged in a line in the first direction X. The multiple layout regions 97 may be arranged in a line in the second direction Y. The multiple layout regions 97 may be arranged in a matrix along the first direction X and the second direction Y. The multiple layout regions 97 may have substantially the same planar area as each other, or may have different planar areas as each other.

[0613] The pad capacitor structure 84 includes pad capacitor portions 84a formed at intervals in a plurality of layout regions 97. Each of the plurality of pad capacitor portions 84a includes a capacitor structure 85, a first capacitor electrode film 90, a main surface insulating film 48, a sidewall dielectric film 91, a second capacitor electrode film 92, an interlayer film 57, a pad opening 93, and a pad via electrode 94.

[0614] The pad capacitor portions 84a may have the same layout or different layouts, and may each have a layout similar to the pad capacitor structures 84 according to the first to thirteenth layout examples.

[0615] The first capacitor electrode film 90, the sidewall dielectric film 91, the second capacitor electrode film 92, the pad opening 93 and the pad via electrode 94 formed in the adjacent layout regions 97 may be connected to each other.

[0616] An example of an electrical test performed on the semiconductor device 1A is shown below. Fig. 21 is a plan view illustrating an electrical test on the gate pad GP side. Fig. 22 is a plan view illustrating an electrical test on the monitor pad MP side. Fig. 23 is a plan view illustrating an electrical test on the anode pad AP side. Fig. 24 is a plan view illustrating an electrical test on the cathode pad CaP side.

[0617] The electrical test is a human body model (HBM) ESD (Electro Static Discharge) tolerance measurement test for the semiconductor device 1A (plurality of pad electrodes 95). The HBM is a model that assumes that ESD occurs between a human body and the plurality of pad electrodes 95.

[0618] 21 , in a test on the gate pad GP side, a predetermined first test voltage V1 is applied between the emitter pad EP and the gate pad GP. Various values ​​are adopted for the first test voltage V1 depending on the specifications of the semiconductor device 1A. The first test voltage V1 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0619] When the first test voltage V1 is applied, a predetermined test current is generated in the emitter pad EP and the gate pad GP, and the ESD resistance between the emitter pad EP and the gate pad GP is measured. A relatively high capacitance value is ensured between the emitter pad EP and the gate pad GP by the multiple gate structures 20, so that a relatively high ESD resistance is achieved.

[0620] 22 , in a test on the monitor pad MP side, a predetermined second test voltage V2 is applied between the emitter pad EP and the monitor pad MP. The second test voltage V2 may be applied between the gate pad GP and the monitor pad MP. Various values ​​are adopted for the second test voltage V2 depending on the specifications of the semiconductor device 1A. The second test voltage V2 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0621] When the second test voltage V2 is applied, a predetermined test current is generated in the emitter pad EP and the monitor pad MP, and the ESD resistance between the emitter pad EP and the monitor pad MP is measured.

[0622] In the monitor region 7, the number of gate structures 20 formed is less than the number of gate structures 20 associated with the active regions 6. In other words, the capacitance value associated with the gate structures 20 in the monitor region 7 is lower than the capacitance value associated with the gate structures 20 in the active regions 6. Therefore, the ESD tolerance between the emitter pad EP and the monitor pad MP is less than the ESD tolerance between the emitter pad EP and the gate pad GP.

[0623] In this regard, in the semiconductor device 1A, the monitor capacitor structure CM (capacitor C) is formed in the monitor pad region 11M, and the capacitance value between the emitter pad EP and the monitor pad MP is complemented by the monitor capacitor structure CM, thereby increasing the ESD tolerance compared to when the monitor capacitor structure CM is not present in the monitor pad region 11M.

[0624] 23 , in a test on the anode pad AP side, a predetermined third test voltage V3 is applied between the emitter pad EP and the anode pad AP. The third test voltage V3 may be applied between the gate pad GP and the anode pad AP. Various values ​​are adopted for the third test voltage V3 depending on the specifications of the semiconductor device 1A. The third test voltage V3 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0625] When the third test voltage V3 is applied, a predetermined test current is generated in the emitter pad EP and the anode pad AP, and the ESD resistance between the emitter pad EP and the anode pad AP is measured.

[0626] The gate structure 20 is not electrically interposed in the region between the emitter pad EP and the anode pad AP. Therefore, the ESD resistance between the emitter pad EP and the anode pad AP is less than the ESD resistance between the emitter pad EP and the gate pad GP.

[0627] In this regard, in the semiconductor device 1A, the anode capacitor structure CA (capacitor C) is formed in the anode pad region 11A, and the capacitance between the emitter pad EP and the anode pad AP is complemented by the anode capacitor structure CA, thereby increasing the ESD resistance compared to when the anode capacitor structure CA is not present in the anode pad region 11A.

[0628] 24 , in a test on the cathode pad CaP side, a predetermined fourth test voltage V4 is applied between the emitter pad EP and the cathode pad CaP. The fourth test voltage V4 may be applied between the gate pad GP and the cathode pad CaP. Various values ​​are adopted for the fourth test voltage V4 depending on the specifications of the semiconductor device 1A. The fourth test voltage V4 is typically equal to or greater than 500 V and equal to or less than 8000 V.

[0629] When the fourth test voltage V4 is applied, a predetermined test current is generated in the emitter pad EP and the cathode pad CaP, and the ESD resistance between the emitter pad EP and the cathode pad CaP is measured.

[0630] The gate structure 20 is not electrically interposed in the region between the emitter pad EP and the cathode pad CaP. Therefore, the ESD resistance between the emitter pad EP and the cathode pad CaP is less than the ESD resistance between the emitter pad EP and the gate pad GP.

[0631] In this regard, in the semiconductor device 1A, the cathode capacitor structure CC (capacitor C) is formed in the cathode pad region 11C, and the capacitance between the emitter pad EP and the cathode pad CaP is complemented by the cathode capacitor structure CC, thereby increasing the ESD resistance compared to when the cathode capacitor structure CC is not present in the cathode pad CaP.

[0632] As described above, the semiconductor device 1A may include the chip 2, the pad region 11, the first capacitor electrode film 90 (first electrode), the sidewall dielectric film 91, and the second capacitor electrode film 92 (second electrode). The chip 2 may have a first main surface 3. The pad region 11 may be provided on the first main surface 3. The first capacitor electrode film 90 may be disposed on the first main surface 3 in the pad region 11. A first potential may be applied to the first capacitor electrode film 90.

[0633] The sidewall dielectric film 91 may cover the sidewall of the first capacitor electrode film 90 in the pad region 11. The second capacitor electrode film 92 may be disposed on the first main surface 3 so as to form a capacitive coupling with the first capacitor electrode film 90 via the sidewall dielectric film 91 in the pad region 11. A second potential different from the first potential may be applied to the second capacitor electrode film 92.

[0634] This configuration provides a semiconductor device 1A that can improve electrical characteristics. Specifically, the semiconductor device 1A has a pad capacitor structure 84 that includes a first capacitor electrode film 90, a sidewall dielectric film 91, and a second capacitor electrode film 92. This configuration increases the capacitance of the pad region 11 by the pad capacitor structure 84, thereby improving ESD resistance.

[0635] The first potential may be a potential other than the gate potential. With this configuration, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 to which a potential other than the gate potential is applied.

[0636] The first potential may be a reference potential that serves as a reference for circuit operation. With this configuration, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 to which the reference potential is applied. The first potential may be an emitter potential. With this configuration, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 to which the emitter potential is applied.

[0637] The second potential may be a potential other than the gate potential. With this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which a potential other than the gate potential is applied.

[0638] The second potential may be a potential other than the reference potential that serves as a reference for circuit operation. With this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which a potential other than the reference potential is applied. The second potential may be a potential other than the emitter potential. With this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which a potential other than the emitter potential is applied.

[0639] The semiconductor device 1A may include a pad electrode 95. The pad electrode 95 may be disposed on the first capacitor electrode film 90 and the second capacitor electrode film 92 in the pad region 11.

[0640] The pad electrode 95 may be electrically isolated from the first capacitor electrode film 90 and electrically connected to the second capacitor electrode film 92. A second potential may be applied to the pad electrode 95.

[0641] According to this configuration, the capacitance associated with the pad electrode 95 can be improved by the pad capacitor structure 84 including the first capacitor electrode film 90 , the sidewall dielectric film 91 and the second capacitor electrode film 92 .

[0642] In this case, the semiconductor device 1A may include an insulating interlayer film 57 and a pad opening 93. The interlayer film 57 may cover the first capacitor electrode film 90 and the second capacitor electrode film 92 in the pad region 11. The pad opening 93 may be formed in the interlayer film 57, exposing the second capacitor electrode film 92.

[0643] In this case, the pad electrode 95 may be disposed on the interlayer film 57 and electrically connected to the second capacitor electrode film 92 through the pad opening 93. According to this configuration, the pad electrode 95 can be appropriately electrically connected to the second capacitor electrode film 92 while suppressing contact of the pad electrode 95 with the first capacitor electrode film 90.

[0644] The semiconductor device 1A may include a pad via electrode 94 embedded in the pad opening 93. In this case, the pad electrode 95 may be mechanically and electrically connected to the pad via electrode 94 on the interlayer film 57, and may be electrically connected to the second capacitor electrode film 92 via the pad via electrode 94.

[0645] According to this configuration, the pad electrode 95 can be properly connected to the second capacitor electrode film 92. As a result, the electrical stability of the capacitance value associated with the pad electrode 95 can be improved.

[0646] The semiconductor device 1A may include a trench electrode type capacitor structure 85. The capacitor structure 85 may be formed on the first main surface 3. In this case, the first capacitor electrode film 90 may be connected to the capacitor structure 85. The second capacitor electrode film 92 may be formed at a distance from the capacitor structure 85.

[0647] According to this configuration, the second capacitor electrode film 92 forms a capacitive coupling with the capacitor structure 85 and the first capacitor electrode film 90 via the sidewall dielectric film 91. As a result, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 connected to the capacitor structure 85.

[0648] A second potential may be applied to the capacitor structure 85. In this case, the first capacitor electrode film 90 may be configured so that the second potential is applied from the capacitor structure 85. With this configuration, the second potential applied to the capacitor structure 85 can be transmitted to the first capacitor electrode film 90 via the capacitor structure 85.

[0649] The capacitor structure 85 may include a capacitor trench 86, a capacitor insulating film 87, and a capacitor buried electrode 88. The capacitor trench 86 may be formed on the first main surface 3. The capacitor insulating film 87 may cover the wall surface of the capacitor trench 86. The capacitor buried electrode 88 may be buried in the capacitor trench 86 with the capacitor insulating film 87 sandwiched therebetween.

[0650] In this case, the first capacitor electrode film 90 may be formed integrally with the capacitor buried electrode 88 as a protruding portion that protrudes from the capacitor buried electrode 88 above the height position of the first main surface 3 .

[0651] The semiconductor device 1A may include a main surface insulating film 48 as a dielectric film. The main surface insulating film 48 may cover the first main surface 3. In this case, the second capacitor electrode film 92 may be disposed on the main surface insulating film 48 and may form a capacitive coupling with the chip 2 via the main surface insulating film 48.

[0652] That is, the second capacitor electrode film 92 may have a portion that forms a capacitive coupling with the chip 2 via the main surface insulating film 48, and a portion that forms a capacitive coupling with the first capacitor electrode film 90 via the sidewall dielectric film 91. According to this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 having a portion that forms a capacitive coupling with the chip 2.

[0653] The semiconductor device 1A may include an n-type drift region 12 (semiconductor region), a p-type pad well region 80, and a main surface insulating film 48. The drift region 12 may be formed in the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 in the pad region 11 and may be electrically connected to the drift region 12. The main surface insulating film 48 may cover the pad well region 80 on the first main surface 3 in the pad region 11.

[0654] In this case, the second capacitor electrode film 92 may form a capacitive coupling with the pad well region 80 via the main surface insulating film 48. According to this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 having a portion that forms a capacitive coupling with the pad well region 80.

[0655] Furthermore, with this configuration, a depletion layer spreads from the pn junction between the drift region 12 and the pad well region 80. This improves the breakdown voltage in the pad region 11.

[0656] The semiconductor device 1A may include an active region 6 and a transistor structure T3. The active region 6 may be provided on the first main surface 3. The transistor structure T3 may be formed in the active region 6. In this case, the pad region 11 may be provided in a region outside the active region 6 on the first main surface 3. With this configuration, the capacitance value of the pad region 11 can be improved outside the active region 6.

[0657] The transistor structure T3 may include a trench electrode type gate structure 20 to which a gate potential is applied. The first capacitor electrode film 90 may be electrically isolated from the gate structure 20. With this configuration, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 being electrically isolated from the gate structure 20.

[0658] The capacitor structure 85 may have a depth equal to that of the gate structure 20. According to this configuration, the capacitance value of the pad region 11 is increased by the capacitor structure 85 having a depth equal to that of the gate structure 20. In this case, the capacitor structure 85 can be manufactured simultaneously with the gate structure 20.

[0659] The transistor structure T3 may include a trench electrode type emitter structure 30 to which an emitter potential is applied. The first capacitor electrode film 90 may be electrically connected to the emitter structure 30. With this configuration, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 electrically connected to the emitter structure 30.

[0660] The capacitor structure 85 may have a depth equal to that of the emitter structure 30. According to this configuration, the capacitance value of the pad region 11 is increased by the capacitor structure 85 having a depth equal to that of the emitter structure 30. In this case, the capacitor structure 85 can be manufactured simultaneously with the emitter structure 30.

[0661] The capacitor structure 85 may be extended from the pad region 11 to the active region 6 and connected to the emitter structure 30 in the active region 6. With this configuration, the potential applied to the emitter structure 30 can be transmitted to the first capacitor electrode film 90 via the capacitor structure 85.

[0662] As a result, the potential applied to the emitter structure 30 can be transmitted to the first capacitor electrode film 90 via the capacitor structure 85, which serves as a wiring structure located below the height position of the first main surface 3. Furthermore, the capacitance value of the pad region 11 can be appropriately improved by the capacitor structure 85 and the first capacitor electrode film 90.

[0663] The semiconductor device 1A may include a temperature detection region 10 as a diode region and a temperature sensing diode structure D as a diode structure. The temperature detection region 10 may be provided in a region outside the active region 6 on the first main surface 3. The temperature sensing diode structure D may be formed in the temperature detection region 10.

[0664] In this case, the pad region 11 may be provided in an area outside the temperature detection region 10 on the first main surface 3. According to this configuration, the capacitance value of the pad region 11 can be improved outside the temperature detection region 10.

[0665] A potential other than the potential for the temperature sensitive diode structure D may be applied to the first capacitor electrode film 90. According to this configuration, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 to which a potential other than the potential for the temperature sensitive diode structure D is applied.

[0666] The second capacitor electrode film 92 may be applied with a potential corresponding to the temperature sensitive diode structure D. According to this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which the potential corresponding to the temperature sensitive diode structure D is applied.

[0667] The semiconductor device 1A may include an anode wiring 75. The anode wiring 75 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the second capacitor electrode film 92 may be electrically connected to the anode wiring 75. With this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which an anode potential is applied.

[0668] The semiconductor device 1A may include a cathode wiring 76. The cathode wiring 76 may be electrically connected to the temperature sensitive diode structure D on the first main surface 3. In this case, the second capacitor electrode film 92 may be electrically connected to the cathode wiring 76. According to this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which a cathode potential is applied.

[0669] The semiconductor device 1A may include a monitor region 7 and a monitor transistor structure T2 for monitoring current. The monitor region 7 may be provided in a region outside the active region 6 on the first main surface 3. The monitor transistor structure T2 may be formed in the monitor region 7.

[0670] In this case, the pad region 11 may be provided in an area outside the monitor region 7 on the first main surface 3. According to this configuration, the capacitance value of the pad region 11 can be improved outside the monitor region 7.

[0671] A potential other than the potential for the monitor transistor structure T2 may be applied to the first capacitor electrode film 90. According to this configuration, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 to which a potential other than the potential for the monitor transistor structure T2 is applied.

[0672] A potential for the monitor transistor structure T2 may be applied to the second capacitor electrode film 92. According to this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which a potential for the monitor transistor structure T2 is applied.

[0673] The semiconductor device 1A may include a monitor electrode 67. The monitor electrode 67 may be electrically connected to the monitor transistor structure T2 on the first main surface 3 of the monitor region 7. In this case, the second capacitor electrode film 92 may be electrically connected to the monitor electrode 67. With this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 to which a monitor potential is applied.

[0674] The semiconductor device 1A may include a p-type base region 15. The base region 15 may be formed in a surface layer portion of the first main surface 3 of the active region 6 and may be electrically connected to the drift region 12.

[0675] In this case, the pad well region 80 may be formed deeper than the base region 15. According to this configuration, the capacitance value of the pad region 11 can be increased by the second capacitor electrode film 92 that forms capacitive coupling with the pad well region 80 that is deeper than the base region 15.

[0676] From another perspective, the semiconductor device 1A may include a chip 2, a first capacitor electrode film 90 (first electrode), a main surface insulating film 48 as a first dielectric film, a sidewall dielectric film 91 as a second dielectric film, and a second capacitor electrode film 92 (second electrode). The chip 2 may have a first main surface 3. The first capacitor electrode film 90 may be disposed on the first main surface 3. A first potential may be applied to the first capacitor electrode film 90.

[0677] The main surface insulating film 48 may cover the first main surface 3. The sidewall dielectric film 91 may cover the sidewall of the first capacitor electrode film 90. The second capacitor electrode film 92 may be disposed on the main surface insulating film 48 so as to form a capacitive coupling with the chip 2 via the main surface insulating film 48 and to form a capacitive coupling with the first capacitor electrode film 90 via the sidewall dielectric film 91. A second potential different from the first potential may be applied to the second capacitor electrode film 92.

[0678] This configuration provides a semiconductor device 1A that can improve electrical characteristics. Specifically, the semiconductor device 1A has a pad capacitor structure 84 that includes a first capacitor electrode film 90, a main surface insulating film 48, a sidewall dielectric film 91, and a second capacitor electrode film 92. This configuration increases the capacitance of the pad region 11 by the pad capacitor structure 84, thereby improving ESD resistance.

[0679] The sidewall dielectric film 91 may have a portion connected to the main surface insulating film 48. With this configuration, the capacitance value of the pad region 11 is increased by the sidewall dielectric film 91 having a portion connected to the main surface insulating film 48. The sidewall dielectric film 91 may have a thickness greater than the thickness of the main surface insulating film 48. With this configuration, the insulation between the first capacitor electrode film 90 and the second capacitor electrode film 92 can be improved.

[0680] The semiconductor device 1A may include a pad electrode 95. The pad electrode 95 may be disposed on the first capacitor electrode film 90 and the second capacitor electrode film 92. The pad electrode 95 may be electrically isolated from the first capacitor electrode film 90 and electrically connected to the second capacitor electrode film 92. A second potential may be applied to the pad electrode 95. According to this configuration, the capacitance value associated with the pad electrode 95 can be improved by the pad capacitor structure 84.

[0681] The semiconductor device 1A may include an n-type drift region 12 (semiconductor region), a p-type pad well region 80, and a main surface insulating film 48. The drift region 12 may be formed in the chip 2. The pad well region 80 may be formed in a surface layer portion of the first main surface 3 in the pad region 11 and may be electrically connected to the drift region 12. The main surface insulating film 48 may cover the pad well region 80 on the first main surface 3 in the pad region 11.

[0682] In this case, the second capacitor electrode film 92 may form a capacitive coupling with the pad well region 80 via the main surface insulating film 48. According to this configuration, the capacitance value of the pad region 11 can be improved by the second capacitor electrode film 92 having a portion that forms a capacitive coupling with the pad well region 80.

[0683] Furthermore, with this configuration, a depletion layer spreads from the pn junction between the drift region 12 and the pad well region 80. This improves the breakdown voltage in the pad region 11.

[0684] The semiconductor device 1A may include a trench electrode type capacitor structure 85. The capacitor structure 85 may be formed on the first main surface 3. In this case, the first capacitor electrode film 90 may be connected to the capacitor structure 85. The second capacitor electrode film 92 may be formed at a distance from the capacitor structure 85.

[0685] According to this configuration, the second capacitor electrode film 92 forms a capacitive coupling with the capacitor structure 85 and the first capacitor electrode film 90 via the sidewall dielectric film 91. As a result, the capacitance value of the pad region 11 can be improved by the first capacitor electrode film 90 connected to the capacitor structure 85.

[0686] 25 is a cross-sectional view showing a main part of a semiconductor device 1B according to the second embodiment. Similar to the semiconductor device 1A, the semiconductor device 1B includes a plurality of pad well regions 80 and a plurality of pad capacitor structures 84 formed in the plurality of pad regions 11, respectively.

[0687] Similar to the semiconductor device 1A, the pad capacitor structure 84 includes a plurality of capacitor structures 85, a plurality of first capacitor electrode films 90, the main surface insulating film 48, a plurality of sidewall dielectric films 91, a plurality of second capacitor electrode films 92, an interlayer film 57, a plurality of pad openings 93, a plurality of pad via electrodes 94, and a pad electrode 95. The semiconductor device 1B may include at least one of the plurality of capacitor structures 85 according to the first to fourteenth layout examples (see FIG. 14 and FIGS. 20A to 20M).

[0688] Similar to the semiconductor device 1A, the pad capacitor structure 84 includes a plurality of first capacitor electrode films 90. In this embodiment, the pad capacitor structure 84 includes one or more (multiple in this embodiment) first capacitor electrode films 90A on one side and one or more (multiple in this embodiment) first capacitor electrode films 90B on the other side.

[0689] The plurality of first capacitor electrode films 90A on one side each have a relatively large first width W1 in a cross-sectional view, and are arranged at intervals on the first main surface 3. The plurality of first capacitor electrode films 90A sandwich one or more (one in this embodiment) capacitor structures 85 in a cross-sectional view.

[0690] For example, the number of capacitor structures 85 interposed in the regions between the plurality of first capacitor electrode films 90A may be 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10 (1 in this embodiment).

[0691] The first capacitor electrode films 90A respectively cover the capacitor structures 85 in a one-to-many correspondence in cross-sectional view. That is, the first capacitor electrode films 90A respectively cover the capacitor structures 85 adjacent to each other in cross-sectional view.

[0692] For example, the plurality of first capacitor electrode films 90A may cover two, three, four, five, six, seven, eight, nine, or ten (two in this embodiment) capacitor structures 85. Of course, the plurality of first capacitor electrode films 90A may each cover a different number (two or more) of capacitor structures 85.

[0693] The plurality of first capacitor electrode films 90A have portions covering the capacitor buried electrodes 88 of the corresponding plurality of capacitor structures 85, and portions covering the main surface insulating film 48. In this embodiment, the plurality of first capacitor electrode films 90A are formed integrally with the corresponding plurality of capacitor buried electrodes 88 as protrusions that protrude above the height position of the first main surface 3 from the corresponding plurality of capacitor buried electrodes 88.

[0694] The plurality of first capacitor electrode films 90A face the first main surface 3 (pad well region 80) with the main surface insulating film 48 interposed therebetween. That is, the plurality of first capacitor electrode films 90A straddle the plurality of adjacent capacitor structures 85 and cover the chip 2 (pad well region 80) in the region between the plurality of adjacent capacitor structures 85 with the main surface insulating film 48 interposed therebetween.

[0695] The multiple first capacitor electrode films 90B on the other side each have a second width W2 that is less than the first width W1 in a cross-sectional view, and are arranged at intervals on the first main surface 3. The multiple first capacitor electrode films 90B cover the multiple capacitor structures 85 in a one-to-one correspondence, respectively, other than the multiple capacitor structures 85 connected to the multiple first capacitor electrode films 90A.

[0696] The plurality of first capacitor electrode films 90B have portions covering the capacitor buried electrodes 88 of the corresponding capacitor structures 85 and portions covering the main surface insulating film 48. The plurality of first capacitor electrode films 90A are formed integrally with the corresponding capacitor buried electrodes 88 as protruding portions that protrude from the corresponding capacitor buried electrodes 88 above the height position of the first main surface 3.

[0697] The plurality of first capacitor electrode films 90B face the first main surface 3 (pad well region 80) with the main surface insulating film 48 interposed therebetween. The facing area of ​​the first capacitor electrode films 90B with respect to the first main surface 3 is smaller than the facing area of ​​the first capacitor electrode films 90A with respect to the first main surface 3.

[0698] The width ratio W2 / W1 of the second width W2 to the first width W1 may be 0.1 or more and less than 1. The width ratio W2 / W1 may have a value belonging to at least one of the ranges of 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0699] Similar to the semiconductor device 1A, the pad capacitor structure 84 includes a plurality of second capacitor electrode films 92. In this embodiment, the plurality of second capacitor electrode films 92 each have approximately the same width.

[0700] Of course, the widths of the second capacitor electrode films 92 may be different from one another. The second capacitor electrode films 92 are respectively arranged in regions between the adjacent first capacitor electrode films 90A and the adjacent first capacitor electrode films 90B on the main surface insulating film 48.

[0701] The plurality of second capacitor electrode films 92 face the first capacitor electrode film 90A via the sidewall dielectric film 91 in one direction in the horizontal direction (first direction X), and form a capacitive coupling with the first capacitor electrode film 90A via the sidewall dielectric film 91. The plurality of second capacitor electrode films 92 face the first capacitor electrode film 90B via the sidewall dielectric film 91 in the other direction in the horizontal direction (first direction X), and form a capacitive coupling with the first capacitor electrode film 90B via the sidewall dielectric film 91.

[0702] As in the semiconductor device 1A, the pad electrode 95 is disposed on the interlayer film 57 and is electrically connected to the plurality of second capacitor electrode films 92 via the plurality of pad via electrodes 94. Otherwise, the configuration of the semiconductor device 1B is the same as that of the semiconductor device 1A. In the semiconductor device 1B, the capacitance value of the pad region 11 is appropriately adjusted by appropriately adjusting the number of first capacitor electrode films 90A, the number of first capacitor electrode films 90B, the first width W1, the second width W2, etc.

[0703] 26 is a cross-sectional view showing a main part of a semiconductor device 1C according to the third embodiment. The configuration of the semiconductor device 1C is also applicable to the semiconductor device 1B. Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of pad well regions 80 and a plurality of pad capacitor structures 84 formed in the plurality of pad regions 11, respectively.

[0704] Similar to the semiconductor device 1A, the pad capacitor structure 84 includes a plurality of capacitor structures 85, a plurality of first capacitor electrode films 90, the main surface insulating film 48, a plurality of sidewall dielectric films 91, a plurality of second capacitor electrode films 92, an interlayer film 57, a plurality of pad openings 93, a plurality of pad via electrodes 94, and a pad electrode 95. The semiconductor device 1C may include at least one of the plurality of capacitor structures 85 according to the first to fourteenth layout examples (see FIG. 14 and FIGS. 20A to 20M).

[0705] In this embodiment, the pad capacitor structure 84 includes a plurality of capacitor structures 85 arranged at different pitches in a cross-sectional view, where the pitch is the horizontal distance between the centers of adjacent capacitor structures 85 in a cross-sectional view.

[0706] In this embodiment, the pad capacitor structure 84 includes a plurality of capacitor structures 85 adjacent to each other at a first pitch P1 in a cross-sectional view, and a plurality of capacitor structures 85 adjacent to each other at a second pitch P2 that is larger than the first pitch P1 in a cross-sectional view. The plurality of capacitor structures 85 adjacent to each other at the second pitch P2 are adjacent to the plurality of capacitor structures 85 adjacent to each other at the first pitch P1 in the second direction Y.

[0707] In this embodiment, the plurality of capacitor structures 85 adjacent to each other at the second pitch P2 are alternately arranged in the second direction Y with the plurality of capacitor structures 85 adjacent to each other at the first pitch P1. Of course, the pad capacitor structure 84 may include either or both of a region where three or more capacitor structures 85 are arranged at the first pitch P1 and a region where three or more capacitor structures 85 are arranged at the second pitch P2.

[0708] The first pitch P1 may be 1 μm or more and 5 μm or less. The first pitch P1 may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The first pitch P1 is preferably 1.5 μm or more and 3.5 μm or less.

[0709] The pitch ratio P2 / P1 of the second pitch P2 to the first pitch P1 may be greater than 1 and less than or equal to 5. The pitch ratio P2 / P1 may have a value belonging to at least one of the ranges greater than 1 and less than or equal to 1.5, 1.5 or greater and less than or equal to 2, 2 or greater and less than or equal to 2.5, 2.5 or greater and less than or equal to 3, 3 or greater and less than or equal to 3.5, 3.5 or greater and less than or equal to 4, 4 or greater and less than or equal to 4.5, and 4.5 or greater and less than or equal to 5.

[0710] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of first capacitor electrode films 90. In accordance with the layout of the plurality of capacitor structures 85, the semiconductor device 1C includes a plurality of first capacitor electrode films 90 adjacent to each other at a first pitch P1 in a cross-sectional view, and a plurality of first capacitor electrode films 90 adjacent to each other at a second pitch P2 in a cross-sectional view.

[0711] A plurality of first capacitor electrode films 90 adjacent to each other at a first pitch P1 define a relatively narrow first region 98. A plurality of first capacitor electrode films 90 adjacent...

Claims

1. A semiconductor device comprising: a chip having a main surface; a pad region provided on the main surface; a first electrode disposed on the main surface in the pad region and to which a first potential is applied; a sidewall dielectric film covering a sidewall of the first electrode in the pad region; and a second electrode disposed on the main surface so as to form a capacitive coupling with the first electrode in the pad region via the sidewall dielectric film, and to which a second potential different from the first potential is applied.

2. The semiconductor device according to claim 1, wherein the first potential is a potential other than a gate potential.

3. The semiconductor device according to claim 1, wherein the first potential is a reference potential that serves as a reference for circuit operation.

4. The semiconductor device according to claim 1, wherein the first potential is an emitter potential.

5. The semiconductor device according to claim 1, wherein the second potential is a potential other than a gate potential.

6. The semiconductor device according to claim 1, wherein the second potential is a potential other than a reference potential that is a reference for circuit operation.

7. The semiconductor device according to claim 1, wherein the second potential is a potential other than the emitter potential.

8. The semiconductor device according to any one of claims 1 to 7, further comprising a pad electrode arranged on said first electrode and said second electrode in said pad region, electrically isolated from said first electrode, electrically connected to said second electrode, and to which said second potential is applied.

9. The semiconductor device according to any one of claims 1 to 8, further comprising a trench electrode type capacitor structure formed on the main surface, the first electrode being connected to the capacitor structure, and the second electrode being formed at a distance from the capacitor structure.

10. The semiconductor device described in claim 9, wherein the capacitor structure includes a trench formed in the main surface, an insulating film covering a wall surface of the trench, and a buried electrode buried in the trench with the insulating film sandwiched therebetween, and the first electrode is formed integrally with the buried electrode as a protrusion protruding from the buried electrode above a height position of the main surface.

11. The semiconductor device according to any one of claims 1 to 10, further comprising a main surface dielectric film covering the main surface, the second electrode being disposed on the main surface dielectric film and forming a capacitive coupling with the chip via the main surface dielectric film.

12. The semiconductor device according to claim 11, further comprising: a semiconductor region of a first conductivity type formed within the chip; and a well region of a second conductivity type formed in a surface layer portion of the main surface and electrically connected to the semiconductor region, wherein the main surface dielectric film covers the well region on the main surface, and the second electrode forms a capacitive coupling with the well region via the main surface dielectric film.

13. The semiconductor device according to any one of claims 1 to 12, further comprising: an active region provided on the main surface; and a transistor formed in the active region, and the pad region is provided outside the active region on the main surface.

14. The semiconductor device according to any one of claims 1 to 13, further comprising: a diode region provided on the main surface; and a diode formed in the diode region, and the pad region is provided outside the diode region on the main surface.

15. The semiconductor device according to any one of claims 1 to 14, further comprising: a monitor region provided on said main surface; and a current monitor formed in said monitor region, and said pad region is provided outside said monitor region on said main surface.

16. A semiconductor device comprising: a chip having a main surface; a first electrode disposed on the main surface and to which a first potential is applied; a first dielectric film covering the main surface; a second dielectric film covering a sidewall of the first electrode; and a second electrode disposed on the first dielectric film so as to form a capacitive coupling with the chip via the first dielectric film and to form a capacitive coupling with the first electrode via the second dielectric film, the second electrode being applied with a second potential different from the first potential.

17. The semiconductor device according to claim 16, wherein said second dielectric film has a thickness greater than a thickness of said first dielectric film.

18. The semiconductor device according to claim 16 or 17, further comprising a pad electrode that is electrically isolated from the first electrode, is arranged on the first electrode and the second electrode so as to be electrically connected to the second electrode, and is applied with the second potential.

19. The semiconductor device according to any one of claims 16 to 18, further comprising a p-type well region formed in a surface layer portion of the main surface, the first dielectric film covering the well region on the main surface, and the second electrode forming a capacitive coupling with the well region via the first dielectric film.

20. The semiconductor device according to any one of claims 16 to 19, further comprising a trench electrode type capacitor structure formed on the main surface, the first electrode being connected to the capacitor structure, and the second electrode being formed at a distance from the capacitor structure.

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