Semiconductor device

Abstract

A semiconductor device (1) includes a vertical MOS transistor (10) having a semiconductor substrate (32) of a first conductivity type containing an impurity of a first concentration, and a low-concentration impurity layer (33) of the first conductivity type formed in contact with the semiconductor substrate (32) and containing an impurity of a second concentration lower than the first concentration. In a plan view, an active region (112) of the vertical MOS transistor (10) is formed of unit cells repeatedly arranged in the plane of the active region (112). The unit cell has a hexagonal shape with the outer periphery at the center position of the width of a gate trench (17). In the unit cell, a body contact region (18a) is exposed on the upper surface of the low-concentration impurity layer (33) in a shape of which the center coincides with the center of the unit cell and that has a rotational symmetry of 60[°] or less in the clockwise direction. When the width of the gate trench (17) is Lxr [μm] and the distance between gate trenches (17) facing each other in parallel is Lxm [μm], the relationship Lxm / 3 ≤ Lxr ≤ Lxm is satisfied.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Semiconductor devices including vertical MOS (Metal-Oxide-Semiconductor) transistors are known. Patent Document 1 discloses an example in which gate trenches of a vertical MOS transistor are provided at positions corresponding to the outer periphery of hexagons that are repeatedly arranged without gaps.

[0003] JP 2021-40105 A

[0004] In order to reduce the channel conduction resistance (on-resistance) of a vertical MOS transistor, it is necessary to increase the total gate width. To increase the total gate width, it is effective to expand the area where the gate trench is installed as much as possible. It is also effective to increase the installation density of the gate trenches by reducing the width of the gate trenches and the distance between gate trenches.

[0005] Recent technology has made it possible to reduce the width of the gate trench and the distance between the gate trenches to 0.5 μm or less. In vertical MOS transistors in which the structure around the gate trench has been reduced to such dimensions, there is room for further study on the optimal structure for effectively reducing the conduction resistance of the channel.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0007] a body region of a second conductivity type formed in the lightly doped layer; a source region of the first conductivity type formed in the body region; a body contact region of the second conductivity type formed in the body region; a source electrode connected to the body contact region and the source region; a gate trench formed from an upper surface of the lightly doped layer to a depth of the body region, the source region being deep enough to reach a portion of the lightly doped layer; a gate insulating film formed in the gate trench; and a gate conductor formed on the gate insulating film and embedded in the gate trench. In the plan view, the unit cell has a hexagonal shape with the center of the width of the gate trench as its outer periphery, and in the unit cell, in the plan view, the source region in contact with the gate trench along its entire periphery and the body contact region surrounded by the source region are exposed on an upper surface of the low-concentration impurity layer, and in the unit cell, in the plan view, the shape of the body contact region exposed on the upper surface of the low-concentration impurity layer has a center that coincides with the center of the unit cell and is rotated clockwise by 60° or more. The unit cell has a rotational symmetry below, and in the plan view, when the source region is exposed on the upper surface of the low-concentration impurity layer, the width in the direction away from the gate trench is maximum on a diagonal line connecting one corner of the unit cell with another corner that faces the corner in a straight line across the center of the unit cell, and when the width of the gate trench is Lxr [μm] and the distance between the gate trenches that face each other in parallel is Lxm [μm], then a relationship of Lxm / 3≦Lxr≦Lxm holds.

[0008] a body region of a second conductivity type formed in the lightly doped layer; a source region of the first conductivity type formed in the body region; a body contact region of the second conductivity type formed in the body region; a source electrode connected to the body contact region and the source region; a gate trench formed from an upper surface of the lightly doped layer to a depth that penetrates the body region and reaches a portion of the lightly doped layer; a gate insulating film formed inside the gate trench; and a gate conductor formed on the gate insulating film and embedded in the gate trench. The active region of the vertical MOS transistor is formed by unit cells repeatedly arranged within the plane of the active region, and in the plan view, the unit cell has a hexagonal shape with its outer periphery located at the center of the width of the gate trench. In the plan view, in the unit cell, the source region in contact with the gate trench along its entire periphery and the body contact region surrounded by the source region are exposed at an upper surface of the low-concentration impurity layer. In the unit cell, in the plan view, the shape of the body contact region exposed at the upper surface of the low-concentration impurity layer is such that, on a diagonal line connecting one corner of the unit cell to another corner facing the corner in a straight line across the center of the unit cell, the distance between one corner and the body contact region is different from the distance between the other corner and the body contact region. The lower surface of the body contact region is located deeper than the lower surface of the source region, and a portion of the body contact region is located directly below the source region.

[0009] According to one aspect of the present disclosure, a semiconductor device is provided that includes a vertical MOS transistor with reduced channel conduction resistance (on-resistance).

[0010] FIG. 1A is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 1B is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 2A is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 2B is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 2C is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 3 is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 4 is a schematic plan view and a schematic cross-sectional view showing an example of the structure of a unit cell of a transistor according to Embodiment 1. FIG. 5 is a schematic plan view and a schematic cross-sectional view showing an example of the structure of a unit cell of a transistor according to Modification 1 of Embodiment 1. FIG. 6 is a graph showing the relationship between the width of a gate trench in a plan view and the total gate width per unit area of ​​the semiconductor device according to Embodiment 1. FIG. 7A is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 7B is a schematic plan view showing an example of the structure of a semiconductor device according to Embodiment 1. FIG. 8 is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 2 of Embodiment 1. FIG. 9 is a graph showing desirable dimensional ranges of the gate trench width and mesa width in a plan view of the semiconductor device according to the first embodiment. FIG. 10A is a schematic plan view showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 10B is a schematic plan view and a schematic cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 11 is a schematic plan view showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 12A is a schematic plan view and a schematic cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 12B is a schematic plan view and a schematic cross-sectional view showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 13 is a schematic plan view showing an example of the structure of a semiconductor device according to the second embodiment. FIG. 14A is a schematic plan view and a schematic cross-sectional view showing an example of the structure of a transistor according to the third embodiment. FIG. 14B is a schematic plan view and a schematic cross-sectional view showing an example of the structure of a unit cell of a transistor according to the third embodiment. FIG. 15A is a graph showing the IDS-VGS dependence of a general transistor. FIG. 15B is a graph showing the IDS-VGS dependence of a transistor according to the third embodiment.

[0011] Specific examples of semiconductor devices according to one aspect of the present disclosure will be described below with reference to the drawings. Each embodiment shown here represents a specific example of the present disclosure. Therefore, the numerical values, shapes, components, arrangements of components, and connection forms shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. In each figure, substantially identical components are assigned the same reference numerals, and redundant explanations will be omitted or simplified.

[0012] First Embodiment [1. Structure of Semiconductor Device] FIGS. 1A and 1B are cross-sectional views showing an example of the structure of a semiconductor device 1 according to a first embodiment.

[0013] 1A and 1B, the semiconductor device 1 includes a semiconductor substrate 32, a metal layer 30, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0014] The semiconductor substrate 32 is disposed on the back surface side of the semiconductor layer 40 and is made of silicon of the first conductivity type containing impurities of the first conductivity type at a first concentration. The low-concentration impurity layer 33 is disposed on the front surface side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 32. The low-concentration impurity layer 33 is of the first conductivity type and contains impurities of the first conductivity type at a second concentration that is lower than the concentration of the first-concentration impurities of the first conductivity type in the semiconductor substrate 32. The low-concentration impurity layer 33 may be formed on the semiconductor substrate 32 by, for example, epitaxial growth.

[0015] The metal layer 30 is formed in contact with the back surface of the semiconductor layer 40 (semiconductor substrate 32) and has a multilayer structure including, for example, a layer made of silver (Ag) or copper (Cu). The metal layer 30 may contain trace amounts of elements other than metals that are mixed in as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 30 does not have to be formed over the entire back surface of the semiconductor layer 40 (semiconductor substrate 32). The thickness of the metal layer 30 is, for example, 3 μm or more and 100 μm or less.

[0016] As will be described below, the semiconductor device 1 has a vertical MOS transistor 10 (hereinafter also referred to as “transistor 10 ”) formed in a semiconductor layer 40 .

[0017] A body region 18 of a second conductivity type containing impurities of a second conductivity type different from the first conductivity type is selectively formed in the semiconductor layer 40 (low-concentration impurity layer 33). A source region 14 of the first conductivity type containing impurities of the first conductivity type and a body contact region 18a of the second conductivity type containing impurities of the second conductivity type at a high concentration are selectively formed above the body region 18.

[0018] A gate trench 17 is formed that penetrates from the upper surface of the semiconductor layer 40 through the source region 14 and the body region 18 to a depth reaching a part of the low-concentration impurity layer 33. A gate insulating film 16 is formed on the inner surface of the gate trench 17, and a gate conductor 15 is formed inside the gate trench 17 and on the gate insulating film 16. The gate conductor 15 is a buried electrode buried inside the semiconductor layer 40.

[0019] A source electrode 11 is formed on the upper surface of the semiconductor layer 40. The source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the source region 14 and the body contact region 18a via the portion 13. Since the upper portion of the gate trench 17 is filled with the interlayer insulating layer 34, the gate conductor 15 is not connected to the portion 13 of the source electrode 11 on the upper surface of the semiconductor layer 40 in the active region 112 described later.

[0020] Portion 12 of source electrode 11 is a layer that is joined with solder during reflow soldering in face-down mounting, and may be made of a metal material including, but not limited to, one or more of nickel, titanium, tungsten, and palladium. The surface of portion 12 may be plated with gold or the like.

[0021] Portion 13 of source electrode 11 is a layer that connects portion 12 and semiconductor layer 40, and may be made of a metal material including, by way of non-limiting example, any one or more of aluminum, copper, gold, and silver. The thickness of source electrode 11, including portions 12 and 13, is, for example, 2 μm or more and 13 μm or less.

[0022] As shown in FIG. 1B, the semiconductor layer 40 is covered with an interlayer insulating layer 34 having an opening, and a portion 13 of the source electrode 11 is provided, which is connected to the source region 14 and the body contact region 18 a through the opening in the interlayer insulating layer 34.

[0023] The interlayer insulating layer 34 and the portion 13 of the source electrode 11 are covered with a passivation layer 35 having an opening, and a portion 12 is provided that is connected to the portion 13 of the source electrode 11 through the opening in the passivation layer 35 .

[0024] 1A and 1B, the semiconductor substrate 32 functions as the drain region of the transistor 10. A portion of the low-concentration impurity layer 33 on the side in contact with the semiconductor substrate 32 may also serve as the drain region. The low-concentration impurity layer 33 also serves as the drift layer of the transistor 10, and may also be referred to as the drift layer 33 in this disclosure. The metal layer 30 serves as the drain electrode of the transistor 10. To distinguish it from a front-surface drain electrode, which will be described later, the metal layer 30 may also be referred to as a back-surface drain electrode 30.

[0025] 2A, 2B, and 2C are planar schematic views showing an example of the structure of the semiconductor device 1 according to embodiment 1. Fig. 3 is an enlarged planar schematic view of the portion surrounded by the dashed line shown in Fig. 2C. Figs. 1A and 1B are cross sections taken along lines I-I and II-II in Figs. 2C and 3, respectively.

[0026] Although FIGS. 2A, 2B, and 2C illustrate single-configuration vertical MOS transistors, the semiconductor device 1 according to the first embodiment is not limited to a single configuration, and may have a dual configuration or a triple configuration.

[0027] 2A is a schematic diagram of the external appearance of the semiconductor device 1. In a plan view, the semiconductor device 1 is covered with a passivation layer 35 having openings. The openings in the passivation layer 35 correspond to a source pad 111, a gate pad 119, and a drain pad, respectively.

[0028] 2A without the passivation layer 35 and the interlayer insulating layer 34, but for clarity, pads that would otherwise be invisible are indicated by dashed lines. As shown in Fig. 2B, the gate electrode 19 is connected to the gate wiring 118, and the gate wiring 118 is disposed so as to surround the source electrode 11. Note that a resistor element may be connected in series between the gate electrode 19 and the gate wiring 118.

[0029] The gate pad 119 is a region where the gate electrode 19 is partially exposed on the surface of the semiconductor device 1. The source pad 111 is a region where the source electrode 11 is partially exposed on the surface of the semiconductor device 1. The drain pad is a region where the front surface drain electrode (called the front surface drain electrode in order to distinguish it from the metal layer 30 which is the back surface drain electrode) is partially exposed on the surface of the semiconductor device 1.

[0030] 2C and 3 are schematic diagrams of the state in which the source electrode 11 is further removed from FIG. 2B, but for ease of understanding, the periphery of a portion 13 of the source electrode 11 is shown by a dotted line. Also, for ease of understanding, pads that would otherwise be invisible are shown by dashed lines.

[0031] 2C , portion 13 of source electrode 11 covers active region 112 of transistor 10 in plan view. Active region 112 refers to the smallest area encompassing all of the portions where a channel is formed when a voltage equal to or greater than the threshold voltage is applied to gate conductor 15 of transistor 10. The portion where the channel is formed is near gate trench 17, where the upper portion of gate trench 17 contacts source region 14.

[0032] 2C and 3, the active region 112 of the transistor 10 is formed in a plan view by repeating hexagonal unit structures of the same size without gaps or overlaps. In a plan view, each unit structure has a hexagonal shape with its periphery at the center of the width of the gate trench 17. That is, the gate trench 17 of the transistor 10 according to the first embodiment is located at a position corresponding to the periphery of the hexagons that are repeatedly placed without gaps in a plan view. Hereinafter, the gate trenches 17 are referred to as being arranged in a honeycomb pattern.

[0033] 2C and 1B, the gate conductor 15 formed inside the gate trench 17 is connected to the gate electrode 19 via a gate wiring 118 that is placed so as to surround the active region 112 in plan view. Therefore, the gate conductor 15 is at the same potential as the gate electrode 19.

[0034] 2C schematically shows only the gate trench 17 inside the active region 112 in plan view, but as shown in FIG. 1B , the gate trench 17 may be formed outside the active region 112. However, the gate trench 17 formed outside the active region 112 does not contribute to channel formation because the source region 14 does not contact its upper portion or because it is located outside the body region 18. The gate trench 17 formed outside the active region 112 is mainly for connecting the gate conductor 15 and the gate wiring 118.

[0035] 3 , the unit structures constituting the active region 112 of the transistor 10 are hexagonal in plan view, with the center of the width of the gate trench 17 as the periphery. In each unit structure, the portion of the semiconductor layer 40 surrounded by the gate trench 17 is called a mesa. In each mesa, the source region 14 is formed in contact with the entire periphery of the gate trench 17 in plan view, and is exposed on the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33). In plan view, a body contact region 18a is formed in the remaining portion of each mesa, surrounded by the source region 14, and is exposed on the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33).

[0036] The top surface of each mesa, which has the source region 14 and the body contact region 18a, is connected to the source electrode 11, and the unit structure also has a semiconductor substrate 32 and a back surface drain electrode 30. Therefore, the unit structure is the smallest unit that functions as a transistor in the transistor 10. Hereinafter, this will be referred to as a unit transistor cell or a unit cell.

[0037] 4 is a schematic plan view and a schematic cross-sectional view, respectively, of a unit cell of the transistor 10 according to the first embodiment. Also, FIG. 5 is a schematic plan view and a schematic cross-sectional view, respectively, of a unit cell of a vertical MOS transistor 10A (transistor 10A) according to a first modification of the first embodiment.

[0038] 4 and 5, for ease of understanding, the source electrode 11, the interlayer insulating layer 34 above the semiconductor layer 40, and the passivation layer 35 are not shown. In addition, the interlayer insulating layer 34 inside the gate trench 17 is also not shown in each of the schematic plan views.

[0039] In the transistor 10A according to Modification 1 of Embodiment 1, in a unit cell, the body contact region 18a is changed to the body contact region 18aA according to Modification 1. Other components that are the same as those in the transistor 10 according to Embodiment 1 have already been described, so the same reference numerals are used and detailed description thereof will be omitted.

[0040] 4 and 5, body contact region 18a and / or body contact region 18aA is connected to body region 18 directly below, and connects portion 13 of source electrode 11 to body region 18. Body contact region 18a contains impurities of the second conductivity type at a concentration higher than the concentration of impurities of the second conductivity type contained in body region 18.

[0041] 4, the lower surface of the body contact region 18a may be located shallower than the lower surface of the source region 14. Furthermore, as in Modification 1 shown in the cross-sectional view of FIG. 5, the lower surface of the body contact region 18aA may be located deeper than the lower surface of the source region 14. Furthermore, a portion of the body contact region 18aA may be located directly below the source region 14.

[0042] In each unit cell, the shape of the body contact region 18a exposed on the upper surface of the semiconductor layer 40 in plan view has rotational symmetry of at least 60° clockwise, and its center coincides with the center of the hexagon of each unit cell. For example, it may be substantially circular, as shown in the schematic plan view of FIG. 4. The substantially circular shape does not have to be a perfect circle; for example, it may be a regular hexagon with each vertex evenly chamfered to approximate a circle, or it may have some fluctuation in the periphery. Furthermore, the shape of the body contact region 18a exposed on the upper surface of the semiconductor layer 40 in plan view may be a hexagon rotated 30° clockwise from the hexagon of the unit cell, as shown in the schematic plan view of Modification 1 of Embodiment 1 in FIG. 5.

[0043] Note that examples are not limited to the example of the unit cell of the transistor 10 according to the first embodiment shown in Fig. 4 and the example of the unit cell of the transistor 10A according to the first modification of the first embodiment shown in Fig. 5. For example, the schematic plan view of Fig. 4 and the schematic cross-sectional view of Fig. 5 may be combined, or as another example, the schematic plan view of Fig. 5 and the schematic cross-sectional view of Fig. 4 may be combined.

[0044] In the transistor 10 according to the first embodiment and / or the transistor 10A according to the first modification, in each unit cell, when the source region 14 is exposed on the upper surface of the semiconductor layer 40 in a planar view, the width in the direction away from the gate trench 17 is maximum on a diagonal line connecting one of the six corners of each unit cell (each mesa) and another corner opposite the corner of the unit cell (mesa) across the center thereof, as shown in the schematic plan view of FIG. 4 or the schematic plan view of FIG. 5 .

[0045] 4, in the transistor 10 according to the first embodiment, the width of the gate trench 17 is smaller than the width of the mesa. Note that the width of the mesa is the distance between the gate trenches 17 that are parallel to each other in a unit cell in plan view.

[0046] When the gate trenches 17 are arranged in a honeycomb pattern as shown in FIG. 3 , the gate trenches 17 extend in three directions that are 120° apart in plan view. In the first embodiment, one of these directions is defined as the Y direction. The X direction is parallel to the top surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction is perpendicular to both the X and Y directions and refers to the height direction of the semiconductor device 1. In the first embodiment, as shown in FIG. 2C , the X direction and the Y direction are parallel to the outer periphery of the semiconductor device 1, which is rectangular in plan view.

[0047] In the semiconductor device 1, for example, the first conductivity type may be N-type and the second conductivity type may be P-type, and the source region 14, the semiconductor substrate 32, and the low-concentration impurity layer 33 may be N-type semiconductors, and the body region 18 and the body contact region 18a may be P-type semiconductors.

[0048] In addition, in the semiconductor device 1, for example, the first conductivity type may be P-type and the second conductivity type may be N-type, and the source region 14, the semiconductor substrate 32, and the low-concentration impurity layer 33 may be P-type semiconductors, and the body region 18 and the body contact region 18a may be N-type semiconductors.

[0049] 2. Operation of Semiconductor Device In the following description, the conduction operation of the semiconductor device 1 will be described assuming that the transistor 10 is a so-called N-channel transistor, in which the first conductivity type is N-type and the second conductivity type is P-type.

[0050] In the semiconductor device 1, when a high voltage is applied to the back surface drain electrode 30 and a low voltage is applied to the source electrode 11, and a voltage equal to or greater than the threshold voltage is applied to the gate electrode 19 with the source electrode 11 as the reference, a channel is formed in the body region 18 near the gate insulating film 16. As a result, a current flows through the path of the metal layer 30-semiconductor substrate 32-lightly doped impurity layer 33-channel formed in the body region 18-source region 14-source electrode 11, bringing the semiconductor device 1 into a conductive state. In this conductive path, a PN junction is present at the contact surface between the body region 18 and the lightly doped impurity layer 33, which functions as a body diode.

[0051] When a high voltage is applied to the source electrode 11 and a low voltage is applied to the back surface drain electrode 30, a current flows through the body diode along the path of the source electrode 11-body contact region 18a-body region 18-low concentration impurity layer 33-semiconductor substrate 32-metal layer 30.

[0052] [3. Discussion] Hereinafter, the effects of the semiconductor device 1 according to embodiment 1 will be described based on the investigations conducted by the present inventors. The present inventors conducted investigations with the gate trench width Lxr [μm] and the distance between the gate trenches (mesa width) Lxm [μm] both in the range of approximately 0.5 [μm] or less (the gate trench width and the distance between the gate trenches together are approximately 1.0 [μm] or less).

[0053] 6 shows the relationship between the layout and structural dimensions of the gate trenches in a plan view and the total length of the gate trenches in the active region 112, i.e., the total gate width. The horizontal axis represents the gate trench pitch, i.e., the sum of the width of one gate trench and the width of one mesa (Lxr+Lxm [μm]), and the vertical axis represents the active region 1 [mm ２ ]. Hereinafter, the total gate width (Wg [mm]) per active area [1 mm ２ The total gate width per 1000 MHz is simply called the total gate width.

[0054] The open markers represent the results when the gate trenches are arranged in a honeycomb pattern as shown in Fig. 3. Furthermore, the square markers represent the results when the gate trench width is 0.10 [μm], the diamond markers represent the results when the gate trench width is 0.15 [μm], and the open circle markers represent the results when the gate trench width is 0.23 [μm].

[0055] In contrast, the thick line shows the results when the gate trench width is 0.23 μm, with the gate trenches arranged in a straight line in a plan view at equal intervals (hereinafter referred to as a striped arrangement). Among these, the black circle markers show the results when the gate trench pitch is 0.38 μm (hence the mesa width is 0.15 μm).

[0056] When gate trenches are arranged in a stripe pattern, if the gate trench pitch decreases, the number of gate trenches arranged per unit area increases, and therefore the total gate width increases. Conversely, if the gate trench pitch increases, the number of gate trenches arranged per unit area decreases, and therefore the total gate width decreases. For this reason, the thick line in Figure 6 indicates a monotonically decreasing trend.

[0057] However, when the gate trenches are arranged in a honeycomb pattern, a different trend emerges. At a gate trench width of 0.23 μm, as indicated by the open circles, the total gate width tends to decrease as the gate trench pitch decreases to 0.46 μm or less (i.e., the mesa width decreases to 0.23 μm or less). Comparing the honeycomb pattern (open circles) and the stripe pattern (black circles) for the same gate trench width of 0.23 μm on the graph in Figure 6, we can see that even with the same gate trench pitch of 0.38 μm (i.e., the mesa width of 0.15 μm), the total gate width in the honeycomb pattern is only about 0.8 times that of the stripe pattern.

[0058] This is because in the case of a honeycomb arrangement, the total gate width is the sum of the perimeters of the individual mesas in a planar view. When the width of the gate trench is larger than the width of the mesa (Lxr > Lxm) in a planar view of a unit cell, the inside of the gate trench (the gate insulating film 16 and the gate conductor 15) occupies most of the unit cell, so the mesa is inherently small. Under these conditions, even if the gate trench pitch is reduced, the perimeter of the mesa in a planar view does not improve, but rather decreases.

[0059] Conversely, when the gate trench width is smaller than the mesa width in plan view (Lxr≦Lxm), the honeycomb arrangement can increase the mesa perimeter by reducing the gate trench pitch. Under these conditions, the honeycomb arrangement can increase the total gate width compared to the stripe arrangement.

[0060] On the graph in Figure 6, when comparing a honeycomb arrangement (diamond markers, square markers) with a stripe arrangement (black circle markers) at the same gate trench pitch of 0.38 [μm], it can be seen that the total gate width increases by about 1.25 times when the gate trench width is 0.15 [μm] (diamond marker, mesa width is 0.23 [μm]), and that the total gate width increases by about 1.5 times when the gate trench width is 0.10 [μm] (square marker, mesa width is 0.28 [μm]).

[0061] This is because the honeycomb arrangement allows the gate trenches to be arranged two-dimensionally, compared to the stripe arrangement. Therefore, to take advantage of the honeycomb arrangement in terms of the increased total gate width, it is essential that the gate trench width be smaller than the mesa width (Lxr≦Lxm).

[0062] 6, the plot (diamond markers) for a honeycomb arrangement with a gate trench width of 0.15 μm shows that the total gate width is maximized when the gate trench pitch is 0.30 μm, i.e., when the mesa width is also 0.15 μm and the gate trench width is the same as the mesa width (leftmost plot). Although not plotted within the range of the graph in FIG. 6, the plot (square markers) for a honeycomb arrangement with a gate trench width of 0.10 μm shows that the total gate width is maximized when the gate trench pitch is 0.20 μm, i.e., when the mesa width is also 0.10 μm and the gate trench width is the same as the mesa width.

[0063] Next, it will be explained that it is desirable that the relationship Lxm / 3≦Lxr be established between the width Lxr of the gate trench and the width Lxm of the mesa.

[0064] When the gate trenches 17 are arranged in a honeycomb pattern, a triangular region of the gate trench 17 in plan view that is surrounded by three adjacent mesas (enclosed by dashed lines in FIGS. 7A and 7B described below) is not in contact with any of the adjacent mesas via the gate insulating film 16. For this reason, this region is unlikely to contribute to the formation of a channel that occurs when a voltage equal to or higher than the threshold voltage is applied to the gate conductor 15.

[0065] 7A and 7B are enlarged schematic plan views of three adjacent unit cells in a plan view extracted from the active region 112 of the transistor 10 according to the first embodiment.

[0066] The three unit cells adjacent in plan view are a first unit cell C1, a second unit cell C2 that is located at the same position as the first unit cell C1 in the Y direction and faces the first unit cell C1 across the gate trench 17 in the X direction, and a third unit cell C3 that is located between the first unit cell C1 and the second unit cell C2 in the X direction and at a different position from the first unit cell C1 and the second unit cell C2 in the Y direction.

[0067] In plan view, the triangular region has three vertices on its periphery: a corner P11 of the first mesa M1 included in the first unit cell C1, a corner P21 of the second mesa M2 included in the second unit cell C2, and a corner P31 of the third mesa M3 included in the third unit cell C3.

[0068] The corners of the first mesa M1, which is hexagonal in plan view, are designated clockwise from corner P11, which forms one of the vertices of the triangular region, as corner P12, corner P13, corner P14, corner P15, and corner P16. The corners of the second mesa M2 and the third mesa M3, which are also hexagonal in plan view, are similarly designated with reference numerals. Only some of the reference numerals for the corners are shown in Figures 7A and 7B.

[0069] In FIG. 7A , when the triangular region in plan view is viewed in the direction in which the first unit cell C1 and the second unit cell C2 face each other (the X direction in FIG. 7A ), it is considered that a voltage applied to the shaded region D1 in FIG. 7A contributes to the formation of a channel occurring along the side from the corner P11 to the corner P12 of the first mesa M1 in plan view, and to the formation of a channel occurring along the side from the corner P21 to the corner P26 of the second mesa M2 in plan view.

[0070] Therefore, it is desirable that the length l1 of a perpendicular line drawn from the corner P31 of the triangular region in plan view to the base connecting the corner P11 and the corner P21 is longer than the length l2 of a perpendicular line drawn from the corner P12 of the first mesa M1 to a line connecting the corner P11 and the corner P13 in the X direction in plan view. When this relationship is established, at least a portion of the triangular region (the shaded region D1 shown in FIG. 7A ) can be utilized to form a channel occurring along the entire length of the side from the corner P11 to the corner P12 of the first mesa M1 in plan view, and to form a channel occurring along the entire length of the side from the corner P21 to the corner P26 of the second mesa M2 in plan view.

[0071] In plan view, and Therefore, rearranging the above relationship (l1 ≥ l2), it is sufficient that the relationship Lxr ≥ Lxm / 3 is satisfied.

[0072] 7B shows the triangular region in plan view, viewed from the direction in which the second unit cell C2 and the third unit cell C3 face each other (a direction rotated 30° clockwise from the Y direction in FIG. 7B ). It is believed that a voltage applied to the shaded region D2 in FIG. 7B contributes to the formation of a channel along the edge from corner P21 to corner P22 of the second mesa M2 in plan view, and to the formation of a channel along the edge from corner P31 to corner P36 of the third mesa M3 in plan view.

[0073] Due to geometric symmetry, if the relationship Lxr≧Lxm / 3 holds true in FIG. 7B as well, at least a portion of the triangular region (the shaded region D2 shown in FIG. 7B ) can be utilized to form a channel that occurs along the entire length of the side from corner P21 to corner P22 of the second mesa M2 in a planar view, and to form a channel that occurs along the entire length of the side from corner P31 to corner P36 of the third mesa M3 in a planar view.

[0074] Although not shown, the same conclusion can be reached when the triangular region in plan view is viewed in the direction in which the third unit cell C3 and the first unit cell C1 face each other.

[0075] Therefore, when the gate trenches 17 are arranged in a honeycomb pattern, it is desirable that the relationship Lxr≧Lxm / 3 be satisfied in order to effectively utilize a triangular region of the gate trench 17 surrounded by three adjacent mesas in a plan view for forming channels in the three mesas. When the relationship Lxr≧Lxm / 3 is satisfied, all of the gate conductor 15 embedded inside the gate trench 17 can be effectively utilized.

[0076] Next, a description will be given of a desirable relationship between the shape of the source region 14 exposed on the top surface of each mesa and the shape of the body contact region 18a in a plan view.

[0077] When the gate trenches 17 are arranged in a honeycomb pattern and a voltage equal to or greater than the threshold is applied to the gate conductors 15 embedded in the gate trenches 17, the width of the channel formed in each mesa in plan view is largest near the corners of each mesa due to its geometric characteristics.

[0078] The channel width is the length of the channel in a plan view in a direction away from the gate trench 17. Generally, the channel width increases as the voltage applied to the gate conductor 15 increases, but when the gate trenches 17 are arranged in a honeycomb pattern, differences in the channel width appear depending on the position inside the mesa, even if the voltage applied to the gate conductor 15 is constant.

[0079] For example, in FIG. 7A, near corner P11 of the first mesa M1, voltage application from the portion of the gate trench 17 along the side from corner P11 to corner P16 and voltage application from the portion of the gate trench 17 along the side from corner P11 to corner P12 overlap, and there is also a contribution from the triangular region.

[0080] Therefore, the vicinity of the corners of each mesa (not just the corner P11) effectively reaches a state equivalent to that in which a higher gate voltage is applied than in other areas, increasing the channel width and reducing the conduction resistance. For this reason, in the case of a honeycomb arrangement, current tends to concentrate at the corners of each mesa.

[0081] However, in a miniaturized structure in which the width of both the gate trench 17 and the width of the mesa are 0.5 μm or less, the corners of each mesa are densely dispersed within the surface of the active region 112, making it difficult for problems such as localized heat generation to occur. Therefore, in a miniaturized structure, the increased channel width and current concentration at the corners of each mesa can be utilized to effectively reduce the conduction resistance of the channel.

[0082] In a plan view, a line connecting any corner of each mesa to another corner that is directly opposite the center of the mesa is called a diagonal. For example, in the first mesa M1 in Figure 7A, the diagonal lines are the line connecting corners P11 and P14, the line connecting corners P12 and P15, and the line connecting corners P13 and P16.

[0083] As described above, when utilizing the fact that the channel width increases at the corners of each mesa, it is desirable that the length of the source region 14 in the direction away from the gate trench 17 in a planar view be formed so that it is relatively large on the diagonal from each corner.

[0084] Therefore, in a planar view, when the source region 14 formed in the unit cell is exposed on the upper surface of the semiconductor layer 40 (low-concentration impurity layer 33), it is preferable that the width in the direction away from the gate trench 17 is maximized on a diagonal line connecting one of the corners of the unit cell and another corner that is directly opposite the corner across the center of the unit cell.

[0085] In a unit cell, it is desirable that the source region 14 and the body contact region 18a exposed at the top surface of the semiconductor layer 40 in the mesa be formed so as to exhibit the above-described characteristics in plan view. As an example, as shown in the schematic plan views of Figures 3 and 4, the shape of the body contact region 18a formed in the unit cell and exposed at the top surface of the semiconductor layer 40 may be a substantially circular shape with the same center as the unit cell.

[0086] As another example, as shown in the schematic plan view of FIG. 5 , the shape of the body contact region 18 a formed in the unit cell that is exposed on the upper surface of the semiconductor layer 40 in plan view is a hexagon that is centered on the same plane as the unit cell, and may be rotated 30° clockwise from the hexagon of the unit cell.

[0087] In a unit cell, when the source region 14 and the body contact region 18a are formed in the mesa so as to have the above-described exposed shape in a plan view, it becomes possible to fully utilize the channel, which expands in width particularly at the corners of the mesa, thereby obtaining the effect of reducing the conduction resistance of the channel.

[0088] The shape of the body contact region 18a in plan view, as shown in the schematic plan views of Figures 4 and 5, is characterized by its rotational symmetry of 60° or less clockwise. Furthermore, the center of the body contact region 18a coincides with the center of the hexagonal unit cell in plan view. These two features enable the same effect to be achieved at each of the six corners of the unit cell (or mesa) in plan view.

[0089] Therefore, the semiconductor device 1 according to the first embodiment includes a semiconductor substrate 32 of a first conductivity type containing an impurity of a first concentration, a low-concentration impurity layer 33 of the first conductivity type formed on and in contact with the semiconductor substrate 32 and containing an impurity of a second concentration lower than the first concentration of the semiconductor substrate 32, a body region 18 of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer 33, a source region 14 of the first conductivity type formed in the body region 18, a body contact region 18a of the second conductivity type formed in the body region 18, and a source region 14 of the first conductivity type formed in the body region 18. and a source electrode 11 connected to the source region 14, a gate trench 17 formed from an upper surface of the low-concentration impurity layer 33 to a depth that penetrates the body region 18 to a part of the low-concentration impurity layer 33, a gate insulating film 16 formed inside the gate trench 17, and a gate conductor 15 formed on the gate insulating film 16 and embedded inside the gate trench 17, wherein the semiconductor device 1 includes a vertical MOS transistor 10 having an active region 11 of the vertical MOS transistor 10 when viewed from above the low-concentration impurity layer 33. 2 is formed by unit cells repeatedly arranged within the plane of the active region 112, and in plan view, the unit cell has a hexagonal shape with the center of the width of the gate trench 17 as the periphery. In plan view, in the unit cell, the source region 14 in contact with the gate trench 17 on the entire periphery and the body contact region 18a surrounded by the source region 14 are exposed on the upper surface of the low-concentration impurity layer 33, and in plan view, the shape of the body contact region 18a exposed on the upper surface of the low-concentration impurity layer 33 coincides with the center of the unit cell and is arranged clockwise in a hexagonal shape. The unit cell has a rotational symmetry of 0° or less, and in plan view, in a shape in which the source region 14 is exposed on the upper surface of the low-concentration impurity layer 33, the width in a direction away from the gate trench 17 is maximum on a diagonal line connecting one corner of the unit cell with another corner that faces the corner in a straight line across the center of the unit cell, and is characterized in that, in plan view, when the width of the gate trench 17 is Lxr [μm] and the distance between the gate trenches 17 facing each other in parallel is Lxm [μm], the relationship is Lxm / 3≦Lxr≦Lxm.

[0090] However, in a miniaturized unit cell, if the width of the source region 14 becomes excessively large in plan view, it becomes difficult to ensure a sufficient area for the body contact region 18a, which may impair the function of the transistor 10. Therefore, it is desirable that the width of the body contact region 18a formed in the unit cell on the diagonal line is wider than the width of the source region 14 formed in the unit cell on the diagonal line in plan view.

[0091] Note that the diagonal width of the source region 14 formed in a unit cell in a planar view refers to the sum of the widths of the source regions 14 that contact the gate trenches 17 on both sides of the body contact region 18a when viewed along a diagonal line.

[0092] 6, when the gate trenches are arranged in a honeycomb pattern, it can be seen that when the gate trench width is 0.15 μm or less (plots with diamond markers and square markers), the increase in the total gate width per unit area due to the decrease in gate trench pitch is steep. This indicates that when the width of the gate trenches arranged in a honeycomb pattern is 0.15 μm or less, even a slight increase in the active region in the semiconductor device has a significant effect on increasing the total gate width.

[0093] The effect of arranging gate trenches in a honeycomb pattern makes it easier to expand the active region compared to arranging them in a stripe pattern, as will be explained below.

[0094] FIG. 8 shows a schematic plan view of a semiconductor device 1B (vertical MOS transistor 10B (transistor 10B)) according to Modification 2 of Embodiment 1. In the transistor 10B according to Modification 2 of Embodiment 1, the gate trench 17 is changed to a gate trench 17B according to Modification 2, the active region 112 is changed to an active region 112B according to Modification 2, and the gate wiring 118 is changed to a gate wiring 118B according to Modification 2. Other components that are the same as those in the transistor 10 according to Embodiment 1 have already been described, so they are assigned the same reference numerals and detailed description thereof will be omitted.

[0095] The gate wiring 118B of the transistor 10B according to Modification 2 shown in Fig. 8 is installed in a different position from the gate wiring 118 of the transistor 10 according to Embodiment 1 shown in Fig. 2C. In the transistor 10 according to Embodiment 1, as shown in Fig. 2C, the gate wiring 118 is installed on all sides surrounding the active region 112 in a plan view. In contrast, in Modification 2 shown in Fig. 8, the gate wiring 118B is installed only on the sides surrounding the active region 112B in a plan view, between the gate electrode 19 and the active region 112B, between the surface drain electrode and the active region 112B, and between the gate electrode 19 and the surface drain electrode.

[0096] Accordingly, in the transistor 10B of the second modification, compared to the transistor 10 of the first embodiment, the area in which the gate trench 17B is formed, the active region 112B, and the area where the portion where the source electrode connects to the upper surface of the semiconductor layer 40 is located, although not shown, each have an increased area in plan view.

[0097] 8, for ease of comparison with the example shown in Fig. 2C, the passivation layer 35, the interlayer insulating layer 34, and the source electrode 11 are omitted, as in Fig. 2C. Pads that would otherwise be invisible are shown by dashed lines in Fig. 8 for ease of understanding.

[0098] 8 according to the second modification, the gate conductor 15 is connected to portions of the gate wiring 118B that are provided only between the gate electrode 19 and the active region 112B, between the surface drain electrode and the active region 112B, and between the gate electrode 19 and the surface drain electrode in a plan view. Since the gate wiring 118B is not provided along portions of the other sides among the sides surrounding the active region 112B in a plan view, a portion of the gate conductor 15 terminates on the periphery of the active region 112B without being connected to the gate wiring 118B.

[0099] The gate trenches 17B (gate conductors 15) arranged in a honeycomb pattern are not divided within the surface of the active region 112B. Therefore, even if the gate wiring 118B is provided only in limited positions as described above and the gate wiring 118B and the gate conductor 15 are connected only at these positions, there is no problem in uniformly setting the gate conductors 15 within the surface of the active region 112B to the same potential.

[0100] 8, the gate wiring 118B is provided only in a limited portion of the sides surrounding the active region 112B in plan view, and therefore the area in which the gate trench 17B is formed can be expanded along the other sides compared to the example shown in Fig. 2C. Therefore, in the transistor 10B according to the second modification, the active region 112B can be expanded, and the total gate width is increased, compared to the transistor 10 according to the first embodiment shown in Fig. 2C.

[0101] As described above, arranging the gate trenches (gate conductors) in a honeycomb pattern has the effect of making it easier to expand the active region compared to arranging them in a stripe pattern. Furthermore, if the width of the gate trench is reduced to 0.15 μm or less as shown in Figure 6, even a slight expansion of the active region, as in the transistor 10B according to the second modification shown in Figure 8, can significantly increase the total gate width.

[0102] Therefore, Lxr≦0.15 μm, and in plan view, the gate conductor 15 may terminate at a location on the periphery of the active region 112 B without connecting to the gate wiring 118 B. With the above-described configuration, the area for installing the gate wiring 118 B can be reduced, and this area can be used as the active region 112 B, thereby effectively increasing the total gate width.

[0103] FIG. 9 shows the preferred range of the dimensional relationship between the gate trench width Lxr [μm] and the mesa width Lxm [μm] when the gate trenches 17 are arranged in a honeycomb pattern. If Lxr≦Lxm, the total gate width Wg can be increased compared to when the gate trenches 17 are arranged in a stripe pattern. If Lxm / 3≦Lxr, the gate conductor 15 embedded inside the gate trench 17 can be effectively utilized over its entire length. If Lxr≦0.15 [μm], the effect of increasing the total gate width by even slightly expanding the active region 112 can be easily achieved. In both cases, the effect of reducing the conduction resistance of the channel of the transistor 10 can be obtained. The shaded ranges in FIG. 9 are desirable ranges that satisfy both conditions.

[0104] The dashed lines in FIG. In the transistor 10 that satisfies this condition, the length of one side of each mesa is the same as the width of the gate trench 17 in a plan view. Therefore, in a plan view, the distances between the closest corners of each mesa in the active region 112 are all equal within the surface of the active region 112, which makes it less likely for current concentration or heat concentration to occur.

[0105] Second Embodiment Hereinafter, a semiconductor device 1C (vertical MOS transistor 10C (transistor 10C)) according to a second embodiment will be described, which is obtained by partially modifying the configuration of the semiconductor device 1 (transistor 10) according to the first embodiment.

[0106] In the transistor 10C according to the second embodiment, the gate trench 17 is changed to the gate trench 17C according to the second embodiment. Here, for the transistor 10C according to the second embodiment, the same components as those of the transistor 10 according to the first embodiment have already been described, so they are assigned the same reference numerals and detailed description thereof is omitted, and the description will focus on the differences from the transistor 10.

[0107] 1. Structure of the Semiconductor Device Figure 10A is a schematic plan view showing a portion of the structure of the active region 112 of the semiconductor device 1C (transistor 10C) according to embodiment 2. In the semiconductor device 1C according to embodiment 2, the gate trenches 17C are also arranged in a honeycomb pattern in plan view. However, as shown in Figure 10A, the gate trenches 17C of the transistor 10C according to embodiment 2 differ from the gate trenches 17 of the transistor 10 according to embodiment 1 in that regions in which the gate trenches 17C are not formed are periodically arranged two-dimensionally within the plane of the active region 112.

[0108] Each region where the gate trench 17C is not formed has a shape obtained by combining a plurality of adjacent unit cells in a plan view, and neither the source region 14 nor the body contact region 18a is formed inside.

[0109] In a region where the gate trench 17C is not formed, a shield trench 117 is formed, which extends from the upper surface of the semiconductor layer 40 to a position deeper than the gate trench 17C. A shield insulating film 116 is formed on the inner surface of the shield trench 117. The shield insulating film 116 may be made of the same material as the gate insulating film 16, for example, silicon oxide, and may be formed simultaneously with the gate insulating film 16.

[0110] A shield conductor 115 connected to the source electrode 11 is formed on the shield insulating film 116 inside the shield trench 117. The shield conductor 115 may be made of the same material as the gate conductor 15 and the source electrode 11.

[0111] Hereinafter, the regions in which no gate trenches 17C are formed, which are periodically arranged within the surface of the active region 112 in plan view as shown in FIG. 10A, will be individually referred to as shield regions.

[0112] 10B is a schematic plan view and a schematic cross-sectional view showing an enlarged view of one shield region. For ease of understanding, FIGS. 10A and 10B show a structure in which the passivation layer 35, the interlayer insulating layer 34 above the semiconductor layer 40, and the source electrode 11 are removed. The schematic plan view also removes the interlayer insulating layer 34 inside the gate trench 17C. The schematic cross-sectional view of FIG. 10B is a cross section taken along line III-III of the schematic plan view of FIG. 10B.

[0113] 10A, the centers of the shielding regions are arranged so as to coincide with the vertices of an equilateral triangle in plan view. The lengths of the sides of the equilateral triangle are selected according to the desired breakdown voltage of the semiconductor device 1.

[0114] The operation of the transistor 10C according to the second embodiment is the same as that of the transistor 10 according to the first embodiment, and therefore a description thereof will be omitted.

[0115] [2. Discussion] The following describes the effects achieved by the semiconductor device 1C (transistor 10C) according to the second embodiment.

[0116] Without distinguishing between the transistor 10 according to embodiment 1 and the transistor 10C according to embodiment 2, the potential difference between the back surface drain electrode 30 (metal layer 30) and the source electrode 11 is referred to as the drain-source voltage, or simply as the drain voltage (VDS [V]). Although typically described in a product specification (data sheet), the maximum specified voltage (BVDS [V]) that guarantees safe use of the transistor 10 or 10C even when applied between the drain and source is referred to as the drain breakdown voltage, or simply as the breakdown voltage, in the present disclosure.

[0117] The transistor 10 or 10C has a PN junction at the boundary between the body region 18 and the low-concentration impurity layer 33, and a depletion layer is generated across the PN junction. In order to increase the drain breakdown voltage, a structure is required that allows the depletion layer to expand sufficiently when the transistor 10 or 10C is off.

[0118] For example, in order to sufficiently expand the depletion layer, it is useful to lower the carrier concentration (increase the resistivity) or thicken the low-concentration impurity layer 33. However, in the case of the transistor 10 according to the first embodiment, such measures are not preferable because they increase the conduction resistance of the current path from the tip of the gate trench 17 to the back surface drain electrode 30 (metal layer 30).

[0119] In contrast, the transistor 10C according to the second embodiment has a shield trench 117 that is deeper than the gate trench 17C. Furthermore, because the shield conductor 115 has the same potential as the source electrode 11, when the transistor is off, the shield trench 117 pushes down the expansion of the depletion layer, thereby reducing the electric field strength generated near the tip of the gate trench 17C. Therefore, the withstand voltage of the transistor 10C is improved compared to the transistor 10 according to the first embodiment, in which the shield trench 117 is not formed, without controlling the physical properties of the low-concentration impurity layer 33.

[0120] Because the shield trench 117 is formed deeper than the gate trench 17C, a large area is required in plan view to form the shield trench 117. In the transistor 10 according to the first embodiment, the gate trenches 17 are arranged in a honeycomb pattern, and the transistor 10 has a microstructure in which the width of the gate trench 17 and the width of the mesa are both 0.50 μm or less. Therefore, the area of ​​each unit cell is small, making it difficult to provide a shield trench within one unit cell.

[0121] In contrast, in the transistor 10C according to the second embodiment, a shield region is provided that combines a plurality of unit cells that are adjacent in plan view, and therefore the area necessary to form the shield trench 117 can be secured. However, since the total length of the gate trench 17C, i.e., the total gate width, is somewhat reduced accordingly, the channel conduction resistance increases compared to the transistor 10 according to the first embodiment. Therefore, it is preferable that the area of ​​each shield region be as small as possible within a range that ensures an area sufficient for forming the desired shield trench 117.

[0122] There are several ways to combine multiple unit cells to form a shield region. FIG. 10A shows an example in which the smallest region is composed of three unit cells. The center of the shield region is the corner where the vertices of three unit cells overlap. In FIG. 10A, the centers of some shield regions are indicated by black circles. If the area of ​​a shield region composed of three unit cells is insufficient to form a shield trench 117 with the desired structure, it is sufficient to combine one more unit cell. An example of how to combine unit cells is shown in FIG. 11.

[0123] In Figure 11, the example of the shield region shown on the far left is the same as that shown in Figures 10A and 10B, and is made up of three unit cells. The example of the shield region shown in the center is made up of the shield region shown on the left, with one unit cell added evenly along the periphery, for a total of 12 unit cells. The example of the shield region shown on the far right is made up of the shield region shown in the center, with one more unit cell added evenly along the periphery, for a total of 27 unit cells. The centers of the shield regions in both cases remain the same and are aligned.

[0124] The shielding area shown in FIG. 11 has an area of ​​3n of a unit cell. ２ This is an example of a method of forming the shield region so that n is 1 times (n is an integer equal to or greater than 1). The shape of the shield region can be selected depending on the desired shape of shield trench 117 and the manufacturing method, but it is desirable to make n as small as possible.

[0125] It is preferable that shield trench 117 is formed so as to include the center of each shield region in plan view. The schematic plan view of Fig. 10B shows an example in which shield trench 117 has a triangular shape in plan view and is arranged so that the center of each shield region is included within this triangle.

[0126] 12A shows another method of combining a plurality of unit cells for the purpose of forming a shield region. Fig. 12A is a schematic plan view of a portion of the structure of the active region 112, illustrating an example in which the shield region is provided in a modified manner in the transistor 10C according to the second embodiment.

[0127] FIG. 12A shows an example in which the shield region is composed of seven unit cells. FIG. 12B shows an enlarged schematic plan view and a schematic cross-sectional view of one shield region. For ease of understanding, FIGS. 12A and 12B show a structure in which the passivation layer 35, the interlayer insulating layer 34 above the semiconductor layer 40, and the source electrode 11 are removed. The schematic plan view also removes the interlayer insulating layer 34 inside the gate trench 17C. The schematic cross-sectional view of FIG. 12B is a cross section taken along line IV-IV of the schematic plan view of FIG. 12B.

[0128] In the example shown in the schematic plan view of Figure 12A or Figure 12B, the center of the shield region is the center of the central unit cell. In Figure 12A, the centers of only some of the shield regions are indicated by black circles. If the area of ​​a shield region formed by combining seven unit cells is insufficient to form a shield trench 117 with the desired structure, it is sufficient to combine one more unit cell. An example of how to combine unit cells is shown in Figure 13.

[0129] In Figure 13, the example of the shield region shown on the far left is the same as that shown in Figures 12A and 12B, and is made up of a combination of seven unit cells. The example of the shield region shown in the center is made up of the shield region shown on the left, with one unit cell added evenly along the periphery, for a total of 19 unit cells. The example of the shield region shown on the far right is made up of the shield region shown in the center, with one more unit cell added evenly along the periphery, for a total of 37 unit cells. The centers of the shield regions in both cases remain the same and are aligned.

[0130] 13 is an example of a method of forming the shield region so that its area is 1+3n(n+1) times (n is an integer equal to or greater than 1) that of a unit cell. The shape of the shield region can be selected depending on the desired shape of shield trench 117 and the manufacturing method, but it is desirable to make n as small as possible.

[0131] 12B shows an example in which the shield trench 117 has a hexagonal shape rotated 30° clockwise from the hexagon of the unit cell in plan view, and the shield region is disposed so that its center coincides with the center of this hexagon.

[0132] 11 and 13, the example shown in Fig. 11 has the feature that it is easy to suppress a reduction in the total gate width, but is prone to restrictions on the shape of the shield trench 117 in plan view. On the other hand, the example shown in Fig. 13 has the feature that it is difficult to suppress a reduction in the total gate width, but is prone to restrictions on the shape of the shield trench 117 in plan view. The shape of the shield region in plan view can be selected to match the desired shape of the shield trench 117.

[0133] Therefore, in plan view, regions (shield regions) where unit cells are not formed are periodically provided in the vertical MOS transistor 10C, and the area of ​​the regions is 1+3n(n+1) times the area of ​​the unit cells, or 3×n ２ times (n is an integer of 1 or more).

[0134] Furthermore, in a region where no unit cell is formed (shield region), a shield conductor 115 may be formed to a position deeper than the gate trench 17C.

[0135] In the above-described structure, the gate trenches 17C are arranged in a honeycomb pattern, and the gate trenches 17C are designed with minute dimensions, thereby increasing the total gate width and improving the breakdown voltage.

[0136] As shown in Figures 10A and 12A, in a planar view, the three closest regions (shield regions) in which no unit cells are formed may be arranged so that their centers each correspond to the vertices of an equilateral triangle within the plane of the active region 112.

[0137] When the shield region is arranged as described above and the shield trench 117 is further provided, the electric field strength can be uniformly reduced at the tip of the gate trench 17C located inside an equilateral triangle in plan view by the shield trench 117 located at the vertex of the equilateral triangle. If the equilateral triangles are arranged without gaps within the surface of the active region 112, the electric field strength can be reduced in all of the gate trenches 17C.

[0138] Third Embodiment Hereinafter, a semiconductor device 1D (vertical MOS transistor 10D (transistor 10D)) according to a third embodiment will be described, which is obtained by partially modifying the configuration of the semiconductor device 1 (transistor 10) according to the first embodiment.

[0139] In the transistor 10D of the third embodiment, the source region 14 and the body contact region 18 in the unit cell are changed to the source region 14D of the third embodiment and the body contact region 18aD of the third embodiment.

[0140] Here, for the transistor 10D of embodiment 3, the components that are similar to those of the transistor 10 of embodiment 1 have already been explained, so they will be assigned the same symbols and their detailed explanations will be omitted, and the explanation will focus on the differences from the transistor 10.

[0141] 1. Structure of the Semiconductor Device Figure 14A is a schematic plan view showing an enlarged portion of the structure of the active region 112 of a semiconductor device 1D (transistor 10D) according to embodiment 3. Figure 14B is a schematic plan view and a schematic cross-sectional view, respectively, of a unit cell of the transistor 10D according to embodiment 3. For ease of understanding, Figures 14A and 14B do not show the source electrode 11, the interlayer insulating layer 34 above the semiconductor layer 40, and the passivation layer 35. The schematic plan view also does not show the interlayer insulating layer 34 inside the gate trench 17.

[0142] As shown in the plan view schematic diagrams of Figures 14A and 14B, the shape of the body contact region 18aD exposed on the upper surface of the semiconductor layer 40 in a planar view is such that on a diagonal line connecting one of the corners of the unit cell and another corner that faces that corner in a straight line across the center of the unit cell (in the example shown in the plan view schematic diagram of Figure 14B, a diagonal line other than the diagonal line parallel to the Y direction), the distance between one corner and the body contact region 18aD differs from the distance between the other corner and the body contact region 18aD.

[0143] 14B , the shape of the body contact region 18aD exposed on the upper surface of the semiconductor layer 40 in a plan view may be a hexagon that is not similar to the hexagon of the unit cell and does not have rotational symmetry of 360° or less clockwise. Alternatively, the shape may be a polygon whose center does not coincide with the center of the unit cell, or an ellipse.

[0144] Accordingly, the shape of the source region 14D exposed on the upper surface of the semiconductor layer 40 in plan view also varies irregularly in width in the direction away from the gate trench 17 around the mesa.

[0145] 14B , the body contact region 18aD is connected to the body region 18 directly below it, and connects the portion 13 of the source electrode 11 to the body region 18. The body contact region 18aD contains a higher concentration of the second conductivity type impurity than the concentration of the second conductivity type impurity contained in the body region 18.

[0146] 14B , the lower surface of the body contact region 18aD is located deeper than the lower surface of the source region 14D, and further, a portion of the body contact region 18aD is located directly below the source region 14D. Therefore, as shown in the cross-sectional view of Fig. 14B , even directly below the source region 14D, the distance between the body contact region 18aD and the gate trench 17 differs on one side and the other side along a diagonal line connecting one corner of the unit cell in plan view with another corner that faces the corner in a straight line across the center of the unit cell (a diagonal line other than the diagonal line parallel to the Y direction in the example shown in the plan view of Fig. 14B ).

[0147] The operation of the transistor 10D according to the third embodiment is the same as that of the transistor 10 according to the first embodiment, and therefore a description thereof will be omitted.

[0148] [2. Discussion] Hereinafter, the effects achieved by the semiconductor device 1D (transistor 10D) according to the third embodiment will be described.

[0149] 14B , in the third embodiment, a first portion in which the distance between the body contact region 18aD directly below the source region 14D and the gate trench 17 is relatively small and a second portion in which the distance is relatively large are formed within one unit cell. In the plan view of the plan view of the schematic plan view of FIG. 14B , the outer periphery of the mesa at the location corresponding to the second portion is schematically indicated by a thick line, but by adjusting the shape and position of the body contact region 18aD in the plan view, the first portion can be formed wider than the second portion.

[0150] In the first portion directly below the source region 14D, where the distance between the body contact region 18aD and the gate trench 17 is relatively small, the threshold voltage required to form a channel in the body region 18 by applying a voltage to the gate conductor 15 becomes relatively high. This is because the proximity of the body contact region 18aD to the gate trench 17 brings the concentration of the second conductivity type impurities in the body region 18 where the channel is formed closer to an effectively high state.

[0151] In contrast, in the second portion where the distance between the body contact region 18aD and the gate trench 17 directly below the source region 14D is relatively large, the impurity concentration of the second conductivity type in the body region 18 where a channel is formed is less affected by the body contact region 18aD. Therefore, in the second portion, the threshold voltage required to form a channel in the body region 18 by applying a voltage to the gate conductor 15 is relatively low.

[0152] Therefore, in the transistor 10D according to the third embodiment, a structure can be formed in which a portion having a low threshold voltage and a small gate width (second portion) and a portion having a high threshold voltage and a large gate width (first portion) are mixed within one unit cell. This will be described as follows: the transistor 10D having such a structure can have improved tolerance immediately after turning on the transistor, compared to the transistor 10A according to the first comparative example of the first embodiment.

[0153] 15A shows the dependency of the drain-source current IDS [mA] on the gate voltage VGS [V] (hereinafter referred to as IDS-VGS dependency) when a constant voltage is applied between the drain and source of a typical transistor. The horizontal axis is VGS and the vertical axis is IDS.

[0154] The left side of Figure 15A shows the calculation results when a transistor with a low threshold voltage and a small total gate width is assumed, and the dotted line and solid line respectively show the IDS-VGS dependence at 25°C and 150°C. The right side of Figure 15A shows the calculation results when a transistor with a high threshold voltage and a large total gate width is assumed, and the dotted line and solid line respectively show the IDS-VGS dependence at 25°C and 150°C.

[0155] It is known that in a typical transistor, the temperature coefficient of IDS-VGS dependency is positive when VGS is small and negative when VGS is large. Therefore, when a transistor is turned on under conditions of small VGS, the heat generated by current flow causes the transistor itself to heat up, and the positive temperature coefficient causes even more current to flow through the transistor. This increase in current then further increases the temperature, which in turn makes it easier for current to flow again, potentially resulting in thermal runaway (also known as positive feedback).

[0156] In FIG. 15A, the plotted black circles represent the points where the temperature coefficient of IDS-VGS dependency changes from positive to negative (VGS=V ＺＴＣIn the results shown on the left side of FIG. 15A, the black circles are in the low VGS range, whereas in the results shown on the right side of FIG. 15A, the black circles are in the high VGS range. In other words, for transistors with high threshold voltages and large total gate widths, V ＺＴＣ Therefore, thermal runaway is likely to occur when the transistor is driven under conditions where VGS is small immediately after it is turned on.

[0157] Fig. 15B shows the IDS-VGS dependence of a transistor formed by mixing the transistors whose IDS-VGS dependences are shown on the left and right sides of Fig. 15A. That is, the results shown in Fig. 15B correspond to the IDS-VGS dependence exhibited by the structure of transistor 10D according to embodiment 3 shown in Fig. 14B.

[0158] Looking at the IDS-VGS dependency of the transistor 10D according to the third embodiment shown in FIG. 15B, the temperature coefficient of the IDS-VGS dependency changes from positive to negative (VGS=V ＺＴＣ ) is in a low VGS range due to the presence of the second portion. That is, when a portion (second portion) with a relatively low threshold voltage is mixed in a unit cell, as in the transistor 10D, the VGS range in which the temperature coefficient of the IDS-VGS dependence can be made negative can be expanded.

[0159] 5, the transistor 10A according to the first modification of the first embodiment has the body contact region 18aA extending to directly below the source region 14. Therefore, compared to the transistor 10 according to the first embodiment, the proximity of the gate trench 17 and the body contact region 18aA results in a high threshold voltage, and the range over which the temperature coefficient of the IDS-VGS dependence is positive is widened.

[0160] 14B , the shape of the body contact region 18 aD exposed on the upper surface of the semiconductor layer 40 in plan view is formed such that, on a diagonal line connecting one corner of the unit cell with another corner directly opposite the corner and the center of the unit cell, the distance between one corner and the body contact region 18 aD is different from the distance between the other corner and the body contact region 18 aD, and further, the bottom surface of the body contact region 18 aD is positioned deeper than the bottom surface of the source region 14D, and a portion of the body contact region 18 aD is formed directly below the source region 14D. This results in a region with a relatively low threshold voltage, and can widen the range in which the temperature coefficient of IDS-VGS dependence is negative, as shown in FIG. 15B . Therefore, the transistor 10D has improved tolerance when driven under conditions of low VGS immediately after the transistor is turned on, compared to the transistor 10A.

[0161] Note that the transistor 10D according to embodiment 3 also desirably satisfies the dimensional relationship ( FIG. 9 ) described for the transistor 10 according to embodiment 1. That is, in the transistor 10D, when the width of the gate trench is Lxr [μm] and the distance between the gate trenches facing each other in parallel is Lxm [μm], it is desirable that the relationship Lxm / 3≦Lxr≦Lxm be satisfied.

[0162] Although the semiconductor device according to one aspect of the present disclosure has been described above based on Embodiments 1 to 3 and Modifications 1 and 2, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the spirit of the present disclosure, various modifications that would occur to a person skilled in the art to these embodiments and configurations constructed by combining components in different embodiments and modifications may also be included within the scope of one or more aspects of the present disclosure.

[0163] A semiconductor device including a vertical MOS transistor according to the present invention can be widely used as a device for controlling the conduction state of a current path.

[0164] 1, 1B, 1C, 1D Semiconductor device 10, 10A, 10B, 10C, 10D Vertical MOS transistor, transistor 11 Source electrode 12, 13 Portion 14, 14D Source region 15 Gate conductor 16 Gate insulating film 17, 17B, 17C Gate trench 18 Body region 18a, 18aA, 18aD Body contact region 19 Gate electrode 30 Metal layer, back surface drain electrode 32 Semiconductor substrate 33 Lightly doped layer, drift layer 34 Interlayer insulating layer 35 Passivation layer 40 Semiconductor layer 111 Source pad 112, 112B Active region 115 Shield conductor 116 Shield insulating film 117 Shield trench 118, 118B Gate wiring 119 Gate pad

Claims

a body region of a second conductivity type different from the first conductivity type formed in the low concentration impurity layer; a source region of the first conductivity type formed in the body region; a body contact region of the second conductivity type formed in the body region; a source electrode connected to the body contact region and the source region; a gate trench formed to a depth from an upper surface of the low concentration impurity layer through the body region to a portion of the low concentration impurity layer; a gate insulating film formed inside the gate trench; and a gate conductor formed on the gate insulating film and embedded inside the gate trench, wherein, in a plan view of the low concentration impurity layer, an active region of the vertical MOS transistor is formed by unit cells repeatedly arranged within a plane of the active region, and, in the plan view, the unit cell has a hexagonal shape with an outer periphery at a center position of the width of the gate trench, a source region in contact with the gate trench along its entire periphery and a body contact region surrounded by the source region, the source region being exposed at an upper surface of the low-concentration impurity layer in the unit cell in the plan view; a shape of the body contact region exposed at the upper surface of the low-concentration impurity layer in the unit cell in the plan view has a center that coincides with a center of the unit cell and has rotational symmetry of 60° or less clockwise; a width of the source region exposed at the upper surface of the low-concentration impurity layer in the unit cell in the plan view in a direction away from the gate trench is maximum on a diagonal line connecting one corner of the unit cell and another corner that faces the same corner in a straight line across the center of the unit cell; and a relationship of Lxm / 3≦Lxr≦Lxm is satisfied, where Lxm is a width of the gate trench and Lxr is a distance between the gate trenches facing each other in parallel in the plan view.

2. The semiconductor device according to claim 1, wherein in the unit cell, the shape of the body contact region exposed at the upper surface of the low concentration impurity layer is substantially circular in the plan view.

3. The semiconductor device according to claim 1, wherein in the plan view, in the unit cell, the shape of the body contact region exposed at the upper surface of the low-concentration impurity layer is a hexagon rotated 30° clockwise from the hexagon of the unit cell.

4. The semiconductor device according to claim 1, wherein, in the unit cell, in the plan view, the width of the source region exposed on the upper surface of the low-concentration impurity layer in a direction away from the gate trench on the diagonal line is smaller than the width of the body contact region exposed on the upper surface of the low-concentration impurity layer.

5. The semiconductor device according to claim 1, wherein a bottom surface of said body contact region is located deeper than a bottom surface of said source region, and a portion of said body contact region is located directly below said source region.

6. The semiconductor device according to claim 1 , wherein the following relationship is satisfied:

7. The semiconductor device according to claim 1, wherein Lxr≦0.15 μm, and in the plan view, the gate conductor has a portion that terminates at the outer periphery of the active region without being connected to a gate wiring.

8. In the plan view, the active region is periodically provided with regions in which the unit cells are not formed, and the area of ​​the regions is 1+3n(n+1) times, or 3n times, the area of ​​the unit cells. ２ 2. The semiconductor device according to claim 1, wherein n is an integer of 1 or more.

9. The semiconductor device according to claim 8, wherein the three regions in which the unit cells are not formed that are closest to each other in the planar view are arranged such that their centers correspond to vertices of an equilateral triangle within the surface of the active region.

10. The semiconductor device according to claim 8, wherein a shield electrode is formed in an area where the unit cells are not formed, to a position deeper than the gate trench.

11. A semiconductor device including a vertical MOS transistor having: a semiconductor substrate of a first conductivity type containing an impurity of a first concentration; a low-concentration impurity layer of the first conductivity type formed on and in contact with the semiconductor substrate and containing an impurity of a second concentration lower than the first concentration of the semiconductor substrate; a body region of a second conductivity type different from the first conductivity type formed in the low-concentration impurity layer; a source region of the first conductivity type formed in the body region; a body contact region of the second conductivity type formed in the body region; a source electrode connected to the body contact region and the source region; a gate trench formed to a depth from an upper surface of the low-concentration impurity layer through the body region to a portion of the low-concentration impurity layer; a gate insulating film formed inside the gate trench; and a gate conductor formed on the gate insulating film and embedded inside the gate trench, wherein, in a plan view of the low-concentration impurity layer, an active region of the vertical MOS transistor is formed by unit cells repeatedly arranged within the surface of the active region, and, in the plan view, the unit cell has a hexagonal shape with its outer periphery located at the center position of the width of the gate trench, a semiconductor device in which, in the unit cell, in the plan view, the source region in contact with the gate trench around its entire circumference and the body contact region surrounded by the source region are exposed on an upper surface of the low-concentration impurity layer, and, in the unit cell, in the plan view, the shape of the body contact region exposed on the upper surface of the low-concentration impurity layer is such that, on a diagonal line connecting one corner of the unit cell to another corner opposing the one corner in a straight line across the center of the unit cell, the distance between one of the corners and the body contact region is different from the distance between the other corner and the body contact region, a lower surface of the body contact region is located deeper than a lower surface of the source region, and a part of the body contact region is located directly below the source region.

12. The semiconductor device according to claim 11, wherein, when viewed in the plan view, the width of the gate trench is Lxr [μm] and the distance between the gate trenches facing each other in parallel is Lxm [μm], a relationship of Lxm / 3≦Lxr≦Lxm is satisfied.

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