Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor substrate 1; an insulation layer 2 provided on the semiconductor substrate 1; a resistor R embedded in the insulation layer 2 and composed of a plurality of resistance layers electrically connected together; a first electrode E1 electrically connected to a first end part of the resistor R; a second electrode E2 electrically connected to a second end part of the resistor R; and a plurality of first dummy wires 5 arranged around the first electrode E1 and respectively capacitively coupled to the plurality of resistance layers in the resistor R.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Japanese Patent Application Laid-Open No. 2003-124222 discloses a semiconductor device including a plurality of resistance elements.

[0003] International Publication No. 2023 / 085026

[0004] [Summary] The present disclosure provides a semiconductor device capable of improving breakdown voltage.

[0005] The semiconductor device of the present disclosure comprises a semiconductor substrate, an insulating layer provided on the semiconductor substrate, a resistor embedded in the insulating layer and electrically connecting a plurality of resistive layers, a first electrode electrically connected to a first end of the resistor, a second electrode electrically connected to a second end of the resistor, and a plurality of first dummy wirings arranged around the first electrode and capacitively coupled to the plurality of resistive layers in the resistor, respectively.

[0006] FIG. 1 is a plan view of a semiconductor package. FIG. 2 is a circuit diagram of a resistor chip and an amplifier chip. FIG. 3 is a graph showing the relationship between an input voltage HV (kV) and an output voltage Vout (V). FIG. 4 is a diagram showing a planar configuration for explaining the electrical connection relationship of a voltage divider circuit formed on a resistor chip. FIG. 5 is a diagram showing an example of a detailed structure of a resistor portion in a voltage divider circuit formed on a resistor chip. FIG. 6 is a diagram showing a longitudinal cross-sectional configuration of a portion taken along line A-A in FIG. 5. FIG. 7 is a diagram showing a longitudinal cross-sectional configuration of a portion taken along line B-B in FIG. 5. FIG. 8 is a diagram showing a longitudinal cross-sectional configuration of a portion taken along line C-C in FIG. 5. FIG. 9 is a diagram showing a longitudinal cross-sectional configuration of a portion taken along line D-D in FIG. 5. FIG. 10 is a diagram showing a planar configuration for explaining the electrical connection relationship of a voltage divider circuit formed on a resistor chip. FIG. 11 is a perspective view of a coupling portion indicated by a first region S1 in FIG. 10. FIG. 12 is a longitudinal cross-sectional view (FIG. 12(A)) and a plan view (FIG. 12(B)) of the coupling portion shown in FIG. 11. 13A and 13B are plan views (FIGS. 13B1, 13B2, and 13B3) of a coupling portion according to a modified example. FIG. 14 is a plan view of dummy wiring located near the substrate edge. FIG. 15 is a diagram illustrating a planar configuration for explaining the electrical connection relationship of a voltage divider circuit formed on a resistor chip. FIG. 16 is a diagram illustrating a planar configuration for explaining the electrical connection relationship of a voltage divider circuit formed on a resistor chip. FIG. 17 is a diagram illustrating a planar configuration for explaining the electrical connection relationship of a voltage divider circuit formed on a resistor chip. FIG. 18 is a perspective view of a connection portion indicated by the second region S2 in FIG. 17. FIG. 19 is a longitudinal cross-sectional view (FIG. 19A) and a plan view (FIG. 19B) of the connection portion shown in FIG. 18. FIG. 20 is a plan view (FIGS. 20B1 and 20B2) of a connection portion according to a modified example. FIG. 21 is a chart showing the breakdown voltage (kV) obtained in a sample element. FIG. 22 is a plan view of a modified structure of a voltage divider circuit portion in a resistor chip. 23A is a plan view of the vicinity of the first electrode of a capacitively coupled dummy wiring, and FIG. 23B is a plan view of the vicinity of the first electrode of an electrically connected dummy wiring. FIG. 24 is a plan view of a resistor chip equipped with capacitively coupled dummy wiring. FIG. 25 is a plan view of a resistor chip equipped with electrically connected dummy wiring.Fig. 26 is a diagram showing a longitudinal cross-sectional configuration (first modified example) of a portion taken along line A-A in Fig. 4. Fig. 27 is a diagram showing a longitudinal cross-sectional configuration (second modified example) of a portion taken along line A-A in Fig. 4.

[0007] DETAILED DESCRIPTION Various exemplary embodiments will be described in detail below with reference to the drawings. In the drawings, the same or equivalent parts are designated by the same reference numerals, and redundant explanations will be omitted.

[0008] 1 is a plan view of a semiconductor package, with the top cover removed.

[0009] The semiconductor package 100 includes a case 101 having a recess D1. The case 101 is made of an insulating material such as resin or ceramic. The depth direction of the recess D1 is the same as the thickness direction of the semiconductor package 100.

[0010] The semiconductor package 100 includes a resistor chip 10 (semiconductor device) disposed on a first die pad 110 within the recess D1, and an amplifier chip 20 (semiconductor device) disposed on a second die pad 120 within the recess D1. The open end of the recess D1 of the semiconductor package 100 is sealed with a lid (not shown), creating an airtight space within the recess D1. The lid may be made of an insulating material such as resin, and the recess D1 may be filled with a gas or an insulating material. A ground potential (GND) is applied to the first die pad 110 and the second die pad 120 via the lead frame.

[0011] The lower surface of the resistor chip 10 is fixed to the first die pad 110. The upper surface of the resistor chip 10 is electrically connected to a first inner lead 10a and a second inner lead 10b of the lead frame via bonding wires. The first inner lead 10a is electrically connected to a first input terminal HV(+). The second inner lead 10b is electrically connected to a second input terminal HV(-). The first inner lead 10a and the second inner lead 10b are outer leads exposed to the outside of the package. The first input terminal HV(+) is electrically connected to the positive electrode of the battery 200. The second input terminal HV(-) is electrically connected to the negative electrode of the battery 200.

[0012] The bottom surface of the amplifier chip 20 is fixed to the second die pad 120. The top surface of the amplifier chip 20 is electrically connected to the third inner lead 10c, the fourth inner lead 10d, the fifth inner lead 10e, the sixth inner lead 10f, the seventh inner lead 10g, the eighth inner lead 10h, the ninth inner lead 10i, and the tenth inner lead 10j of the lead frame via bonding wires. Note that connection in an electric circuit means electrical connection, and when it is clear that an electrical connection is made by a physical connection, the term "connection" may be used simply to avoid redundancy in expression.

[0013] The third inner lead 10c is supplied with the power supply potential VCC. The sixth inner lead 10f outputs a positive monitor signal P-MONI. The seventh inner lead 10g is connected to an output terminal as an outer lead, and outputs an output voltage Vout. The eighth inner lead 10h outputs a negative monitor signal N-MONI. The ninth inner lead 10i outputs a voltage monitor signal V-MONI. Note that the symbols for these signals also refer to the symbols indicating the terminals as outer leads corresponding to the signals. The fourth inner lead 10d, fifth inner lead 10e, and tenth inner lead 10j can be used for spare functions.

[0014] FIG. 2 is a circuit diagram of the resistor chip 10 and the amplifier chip 20.

[0015] The resistor chip 10 forms a voltage divider circuit including a resistor R (resistor pattern). The resistor R includes a first resistor RP electrically connected to a first electrode E1 and a second resistor RN electrically connected to a second electrode E2. The resistor R includes voltage detection resistors (RPS, RNS) that electrically connect the first resistor RP and the second resistor RN and have a lower resistance value than both the first resistor RP and the second resistor RN. The resistor chip 10 includes a first output electrode EP, a second output electrode EN, and a reference electrode EG electrically connected to different locations on the voltage detection resistors (RPS, RNS). The voltage detection resistors (RPS, RNS) include a first voltage detection resistor RPS and a second voltage detection resistor RNS.

[0016] The first resistor RP is connected between the first electrode E1 and the first output electrode EP. The second resistor RN is connected between the second electrode E2 and the second output electrode EN. The first voltage detection resistor RPS is connected between the first output electrode EP and the reference electrode EG. The second voltage detection resistor RNS is connected between the second output electrode EN and the reference electrode EG. The resistance value R of the first voltage detection resistor RPS is ＲＰＳ is the resistance value R of the first resistor RP ＲＰ is smaller than (R ＲＰＳ <R ＲＰ The resistance value R of the second voltage detection resistor RNS ＲＮＳ is the resistance value R of the second resistor RN ＲＮ is smaller than (R ＲＮＳ <R ＲＮ The resistance value of the detection resistor can be set to, for example, 1 / 100 or less of the resistance value of the corresponding resistor (R ＲＰＳ ≦1% × R ＲＰ , R ＲＮＳ ≦1% × R ＲＮ This ratio can be expressed as, for example, R ＲＰＳ ≦0.5%×R ＲＰ , R ＲＮＳ ≦0.5%×R ＲＮ , or R ＲＰＳ ≦0.2%×R ＲＰ , R ＲＮＳ ≦0.2%×R ＲＮWhen an input voltage is applied between the first electrode E1 and the second electrode E2, the input voltage is divided in accordance with the ratio of the resistance values ​​of the resistors.

[0017] For example, assume that the input voltage is 1000 V, the resistance of the resistor R (the combined series resistance of each resistor) is k×1000 MΩ, where k is a positive value, e.g., k=0.5. Also assume that the resistance of the first resistor RP is k×499.5 MΩ, the resistance of the first voltage detection resistor RPS is k×0.5 MΩ, the resistance of the second resistor RN is k×499.5 MΩ, and the resistance of the second voltage detection resistor RNS is k×0.5 MΩ.

[0018] In this case, a voltage of 499.5 V is applied across the first resistor RP, a voltage of 0.5 V is applied across the first voltage detection resistor RPS, a voltage of 499.5 V is applied across the second resistor RN, and a voltage of 0.5 V is applied across the second voltage detection resistor RNS. A voltage of 0.5 V is applied between the reference electrode EG and the first output electrode EP, and a voltage of 0.5 V is applied between the reference electrode EG and the second output electrode EN. A voltage of 1 V is applied between the first output electrode EP and the second output electrode EN. In other words, the resistor chip 10 constituting the voltage divider circuit can output an output voltage of 1 V when the input voltage is 1000 V. Of course, an output voltage of 0.5 V can also be applied when the input voltage is 500 V. The resistance value of the resistor R between the first electrode E1 and the second electrode E2 may be 1 MΩ or more and 1000 MΩ or less. The resistance value of the resistor R may be 100 MΩ or more and 800 MΩ or less. The resistance value of the resistor R may be 300 MΩ or more and 600 MΩ or less. This resistance value may be any value that can withstand high voltages and allows voltage detection.

[0019] The amplifier chip 20 is a differential amplifier circuit and includes a differential amplifier 20 D. The differential amplifier 20 D receives a positive signal output from the first output electrode EP and a negative signal output from the second output electrode EN, and outputs the difference between these signals as an output voltage Vout.

[0020] The first output electrode EP is connected to the first voltage follower 21P via a bonding wire.

[0021] The second output electrode EN is connected to the second voltage follower 21N via a bonding wire.

[0022] A power supply potential VCC is supplied to the amplifier chip 20 .

[0023] The output signal of the first voltage follower 21P is output to the outside of the amplifier chip 20 as a positive monitor signal P-MONI. The output signal of the second voltage follower 21N is output to the outside of the amplifier chip 20 as a negative monitor signal N-MONI. The reference electrode EG has a reference potential V-REG and is connected to a second voltage adjustment circuit 29 via a bonding wire. The second voltage adjustment circuit 29 generates a reference potential V-REG that is half the power supply potential VCC. The reference potential V-REG is output to the outside of the amplifier chip 20 as a voltage monitor signal V-MONI.

[0024] A first dummy wiring region DM1 is arranged around the first resistor RP. The first dummy wiring region DM1 includes a plurality of dummy wirings (dummy electrodes, dummy wiring patterns, dummy metals, and dummy conductors). A second dummy wiring region DM2 is arranged around the second resistor RN. The second dummy wiring region DM2 includes a plurality of dummy wirings (dummy electrodes, dummy wiring patterns, dummy metals, and dummy conductors). The dummy wirings do not contribute to the transmission of the input signal (input voltage), but do contribute to increasing the withstand voltage of the resistor chip 10.

[0025] FIG. 3 is a graph showing the relationship between the input voltage HV (kV) and the output voltage Vout (V).

[0026] The input voltage HV (kV) is the difference (= V1 - V2 ≈ 2 × V1) between the positive first voltage V1 applied to the first input terminal HV(+) in FIG. 2 and the negative second voltage V2 applied to the second input terminal HV(-). For example, if the positive first voltage V1 is 600 V and the negative second voltage V2 is -600 V, the input voltage HV (kV) is 1.2 kV. In this case, the detection voltage (voltage between the first output electrode EP and the second output electrode EN) in the resistor chip 10 shown in FIG. 2 is, for example, 1.2 V (= 1 / 1000 of the input voltage). The amplifier chip 20 amplifies the detection voltage and outputs it as the output voltage Vout (V). The input voltage HV (kV) and the output voltage Vout (V) have a linear relationship with a slope a (Vout (V) = a × HV (kV)). For example, if the amplification factor of the amplifier chip 20 is 3.75, the output voltage Vout is 3.75×1.2V=4.5V.

[0027] FIG. 4 is a diagram illustrating a planar configuration for explaining the electrical connection relationship of a voltage divider circuit formed in a resistor chip. An XYZ three-dimensional Cartesian coordinate system is set. The thickness direction of the resistor chip is defined as the Z-axis direction, the direction perpendicular to the Z-axis direction is defined as the X-axis direction, and the direction perpendicular to both the Z-axis and the X-axis is defined as the Y-axis direction. The positive direction of the Z-axis is defined as the depth direction of the resistor chip. The X-axis direction is the longitudinal direction of the resistor chip. The Y-axis direction is the width direction of the resistor chip. The resistor chip shown in this embodiment is an example and can take various forms. The dimensions, arrangement, and direction of each element in the resistor chip can be changed as necessary, and it is also possible to integrate it with an amplifier chip, etc.

[0028] A first positive potential is applied to the first electrode E1 of the resistor chip 10 from the first input terminal HV(+), and a second negative potential is applied to the second electrode E2 from the second input terminal HV(-). Between the first electrode E1 and the second electrode E2, the first resistor RP, the first voltage detection resistor RPS, the second voltage detection resistor RNS, and the second resistor RN are connected in series. The resistor chip 10 has a planar shape (XY planar shape) that is rectangular with four side surfaces (edges: 10U, 10L, 10R, 10D), and an annular conductor 1R is formed along each side surface. In plan view, there is a gap between these side surfaces and the annular conductor 1R. In a plan view, the first dummy wiring region DM1, the first electrode E1, the first resistor RP, the first voltage detection resistor RPS, the second voltage detection resistor RNS, the second resistor RN, the second electrode E2, the first output electrode EP, the second output electrode EN, and the reference electrode EG are arranged inside the annular conductor 1R. The annular conductor 1R prevents moisture from penetrating the insulating layer in which the resistance layer and electrodes are embedded, and prevents cracks from penetrating due to dicing. The annular conductor 1R may be omitted.

[0029] The first output electrode EP is connected to the connection point (node) between the first resistor RP and the first voltage detection resistor RPS. The second output electrode EN is connected to the connection point (node) between the second resistor RN and the second voltage detection resistor RNS. The reference electrode EG is connected to the connection point (node) between the first voltage detection resistor RPS and the second voltage detection resistor RNS. These connection points can be formed by buried electrodes connecting the resistors.

[0030] FIG. 5 is a diagram showing an example of a detailed structure of a resistor portion in a voltage dividing circuit formed on a resistor chip.

[0031] The first resistor RP includes a plurality of linear resistors 3(n) (resistance layers) (n is a natural number (1, 2, 3, ...)). The linear resistors are resistors that extend linearly. In this example, each linear resistor included in the entire resistor extends along the Y-axis direction. One end of the linear resistor 3(n) and one end of the adjacent linear resistor 3(n+1) are electrically connected by a via electrode and a connecting buried electrode BE(n). The other end of the linear resistor 3(n+1) and the other end of the adjacent linear resistor 3(n+2) are electrically connected by a via electrode and a connecting buried electrode BE(n+1). The order (n) of the first resistor RP increases in value in the direction away from the first electrode E1.

[0032] The second resistor RN includes a plurality of linear resistors 3(m) (resistance layers) (m is a natural number (1, 2, 3, ...)). The linear resistors are resistors that extend linearly. In this example, n = m. The connection relationship between the plurality of linear resistors 3(m) is the same as the connection relationship between the plurality of linear resistors 3(n). One end of the linear resistor 3(m) is electrically connected to one end of the adjacent linear resistor 3(m+1) by a via electrode and a connection buried electrode BE(m). The other end of the linear resistor 3(m+1) is electrically connected to the other end of the adjacent linear resistor 3(m+2) by a via electrode and a connection buried electrode BE(m+1). The order (m) of the second resistor RN increases in value in the direction away from the second electrode E2.

[0033] The first voltage detection resistor RPS includes a plurality of linear resistors 3(s) (resistance layers) (s is a natural number (1, 2, 3, ...)). The linear resistors are resistors that extend linearly. In this example, s<n. Except for the fact that the number of linear resistors is smaller, the connection relationship between the plurality of linear resistors 3(s) is the same as the connection relationship between the plurality of linear resistors 3(n), and adjacent linear resistors are electrically connected by via electrodes and embedded electrodes for connection. The order (s) of the first voltage detection resistor RPS may increase in value in the direction away from the first electrode E1. The number of the plurality of linear resistors 3(s) is significantly smaller than the number of linear resistors 3(n). The maximum value of s can be set, for example, between 1 and 10.

[0034] The second voltage detection resistor RNS includes a plurality of linear resistors 3(t) (resistance layers) (t is a natural number (1, 2, 3, ...)). The linear resistors are resistors that extend linearly. In this example, t<m and t=s. Except for the fact that the number of linear resistors is smaller, the connection relationship between the plurality of linear resistors 3(t) is the same as the connection relationship between the plurality of linear resistors 3(m), and adjacent linear resistors are electrically connected by via electrodes and embedded electrodes for connection. The order (t) of the second voltage detection resistor RNS may increase in value in the direction away from the second electrode E2. The number of the plurality of linear resistors 3(t) is significantly smaller than the number of linear resistors 3(m). The maximum value of t can be set, for example, between 1 and 10.

[0035] FIG. 6 is a diagram showing a longitudinal cross-sectional configuration (YZ cross-section) of a portion taken along line AA in FIG.

[0036] The resistor chip 10 (semiconductor device) includes a semiconductor substrate 1, an insulating layer 2, a resistor R, a first electrode E1, and a plurality of first dummy wirings 5(n) (first dummy wiring region).

[0037] The semiconductor substrate 1 may have conductivity. For example, the impurity concentration of the semiconductor substrate 1 may be 5×10 １３ (cm －３ ) or more 5 x 10 １４ (cm －３The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 may be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0038] The insulating layer 2 is provided on the semiconductor substrate 1. The insulating layer 2 includes a plurality of laminated dielectric layers (first dielectric layer 2A, second dielectric layer 2B). The material of at least one layer (first dielectric layer 2A) of the plurality of dielectric layers includes silicon oxide. The material of at least one layer (second dielectric layer 2B) of the plurality of dielectric layers includes silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are laminated alternately. The silicon oxide in this example is SiO ２ However, the element composition ratio may be changed and other elements may be included as necessary. ３ N ４ However, the element composition ratio may be changed and other elements may be included as necessary. The thickness of the insulating layer 2 may be, for example, 5 μm or more and 50 μm or less.

[0039] The insulating layer 2 is a lower dielectric layer 2A formed on a second dielectric layer 2B located at the top. Ｌ and the lower dielectric layer 2A. Ｌ An upper dielectric layer 2A formed on Ｈ The lower dielectric layer 2A Ｌ and upper dielectric layer 2A Ｈ The exemplary material of the upper dielectric layer 2A is the same as that of the first dielectric layer 2A. Ｈ A first protective film 4A is formed on the upper dielectric layer 2A. The material of the first protective film 4A can be an inorganic insulating material such as silicon oxide or silicon nitride. A second protective film 4B is formed on the first protective film 4A. The material of the second protective film 4B can be a resin (insulating material) such as polyimide. In the region directly above the first electrode E1, the upper dielectric layer 2A Ｈ The first protective film 4A and the second protective film 4B are removed, and the upper surface of the first electrode E1 is exposed. Wiring (bonding wire, wiring pattern) is connected to the upper surface of the first electrode E1 (electrode pad).

[0040] The resistor R is embedded in the insulating layer 2 and is formed by electrically connecting multiple resistive layers (wire resistors). The resistor R (multiple wire resistors: resistive layers) is made of a resistive material having a higher resistivity than polysilicon. Specifically, the material of the resistor R (resistive layer) is a material containing chromium (Cr) and silicon (Si), such as CrSi, CrSiC, or CrSiN. Other materials can also be used. Specifically, the material of the resistive layer constituting the resistor R can include at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN. The resistive layer constituting the resistor R can be formed using a sputtering method using a target containing a resistive material. Depending on the type of material of the resistor R, a plating method can also be used. The resistor R can be made of a single resistive material or a combination of multiple resistive materials. The thickness Rd of each resistive layer constituting the resistor R can be 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be made sufficiently high, and when the thickness Rd is equal to or more than the lower limit, the resistance and strength of the resistance layer can be maintained.

[0041] The first electrode E1 is electrically connected to a first end (the end in the X-axis direction) of the resistor R. The lower surface of the first electrode E1 is electrically connected to the upper dielectric layer 2A. Ｈ The first buried electrode BE1 is connected to the upper surface of the first buried electrode BE1 through a first via electrode VE1 extending downward in the upper dielectric layer 2A. ＨThe first electrode E1 extends horizontally within the via electrode VE1, and its end is connected to the underside of one end of the resistive layer constituting the resistor R via another second via electrode (not shown). Although the resistive layer is thin, forming the resistive layer after forming the second via electrode facilitates contact between the two. The first electrode E1 can be made of a metal material such as aluminum (Al) or copper (Cu). The various dummy wiring materials may contain aluminum, copper, tungsten, or titanium, which have lower resistivity than the resistive layer. The first via electrode VE1 can be made of a high-melting-point metal such as tungsten (W), but other electrode materials can also be used. The via electrode and resistive layer are embedded in the insulating layer 2.

[0042] The first dummy wirings 5(n) are formed in the first dummy wiring region DM1 (FIG. 5) described above. The first dummy wirings 5(n) are arranged around the first electrode E1 in a plan view and are capacitively coupled to the resistance layers of the resistor R, respectively.

[0043] The resistor chip 10 includes an annular conductor 1R embedded in an upper region of the insulating layer 2. The annular conductor 1R includes a peripheral electrode 1R1, a peripheral via electrode 1R2, and a peripheral resistor 1R3. The peripheral via electrode 1R2 connects the upper surface of the peripheral electrode 1R1 to the lower surface of the peripheral resistor 1R3. The material of the peripheral electrode 1R1 may be the same as the material of the first buried electrode BE1. The material of the peripheral via electrode 1R2 may be the same as the material of the first via electrode VE1. The material of the resistive layer constituting the peripheral resistor 1R3 may be the same as the material of the resistor R. The planar shape of the peripheral resistor 1R3 may be a continuous annular shape or an intermittent annular shape. When the peripheral resistor 1R3 has an annular shape formed by intermittently arranging multiple linear resistors, the peripheral electrode 1R1 may connect the ends of adjacent linear resistors via the peripheral via electrode 1R2.

[0044] The first buried electrode BE1 and the peripheral electrode 1R1 are formed in the lower dielectric layer 2A. Ｌ The insulating layer 2 is formed on the semiconductor substrate 1 and is embedded in the insulating layer 2 .

[0045] FIG. 7 is a diagram showing a longitudinal cross-sectional configuration (XZ cross-section) of a portion taken along line BB in FIG.

[0046] The resistor R (first resistor RP) includes a plurality of linear resistors 3(n). Each linear resistor 3(n) extends along the Y axis. The plurality of linear resistors 3(n) are aligned along the X axis. One end of the linear resistor 3(n) and one end of the adjacent linear resistor 3(n+1) are connected to the lower dielectric layer 2A. Ｌ The annular conductor 1R is electrically connected to the via electrode and the buried electrode formed thereon. This connection structure is the same as the connection structure of the annular conductor 1R.

[0047] FIG. 8 is a diagram showing a longitudinal cross-sectional configuration (YZ cross-section) of a portion taken along line CC in FIG.

[0048] The resistor chip 10 includes a second electrode E2 and a plurality of second dummy wirings 5(m).

[0049] The second electrode E2 is electrically connected to the second end (the end in the X-axis direction) of the resistor R. The lower surface of the second electrode E2 is electrically connected to the upper dielectric layer 2A. Ｈ The second buried electrode BE2 is connected to the upper surface of the second buried electrode BE2 through a third via electrode VE3 extending downward in the upper dielectric layer 2A. Ｈ The second electrode E2 extends horizontally within the via electrode VE1, and its end is connected to the underside of one end of the resistive layer constituting the resistor R via another fourth via electrode (not shown). Although the resistive layer is thin, forming the resistive layer after forming the fourth via electrode makes it easy to bring them into contact. The second electrode E2 can be made of a metal material such as aluminum (Al) or copper (Cu). The third via electrode VE3 can be made of a high-melting-point metal such as tungsten (W), but other electrode materials can also be used.

[0050] The second dummy wirings 5(m) are formed in the second dummy wiring region DM2 (FIG. 5) described above. The second dummy wirings 5(m) are arranged around the second electrode E2 in a plan view and are capacitively coupled to the resistive layers of the resistor R, respectively.

[0051] FIG. 9 is a diagram showing a longitudinal cross-sectional configuration (XZ cross-section) of a portion taken along line DD in FIG.

[0052] The resistor R (second resistor RN) includes a plurality of linear resistors 3(m). Each linear resistor 3(m) extends along the Y axis. The plurality of linear resistors 3(m) are aligned along the X axis. One end of the linear resistor 3(m) and one end of the adjacent linear resistor 3(m+1) are connected to the lower dielectric layer 2A. Ｌ The annular conductor 1R is electrically connected to the via electrode and the buried electrode formed thereon. This connection structure is the same as the connection structure of the annular conductor 1R.

[0053] FIG. 10 is a plan view illustrating the electrical connection relationship of the voltage divider circuit formed on the resistor chip 10. As shown in FIG.

[0054] A first dummy wiring region DM1 is formed around the first resistor RP. The first dummy wiring region DM1 includes a plurality of first dummy wirings 5(n), one end of each of which is coupled to one end of the linear resistor 3(n) via a first capacitor C1(n). The other end of each of the first dummy wirings 5(n) is coupled to the other end of the linear resistor 3(n) via the next first capacitor C1(n+1). A first dummy wiring (e.g., first dummy wiring 5(n)') located away from the first electrode E1 is coupled only to one end of the linear resistor via a capacitor, and is not coupled to the other end.

[0055] A second dummy wiring region DM2 is formed around the second resistor RN. The second dummy wiring region DM2 includes a plurality of second dummy wirings 5(m), one end of each second dummy wiring 5(m) being coupled to one end of the linear resistor 3(m) via a first capacitor C1(m). The other end of each second dummy wiring 5(m) being coupled to the other end of the linear resistor 3(m) via the next second capacitor C1(m+1). A second dummy wiring (e.g., second dummy wiring 5(m)') located away from the second electrode E2 is coupled only to one end of the linear resistor via a capacitor, and is not coupled to the other end.

[0056] Since one end and the other end of the dummy wiring 5, which is affected by the electric field around the first electrode E1 or the second electrode E2, are not electrically connected to the linear resistor 3, the influence of the potential difference occurring between both ends of the linear resistor 3 is suppressed.

[0057] A third dummy wiring region DM3 can be formed around the first voltage detection resistor RPS. The third dummy wiring region DM3 includes multiple third dummy wirings 5(s), each of which has one end coupled to one end of the linear resistor 3(s) via a third capacitor C1(s). Each third dummy wiring 5(s) is coupled to only one end of the linear resistor via a capacitor, but not to the other end. One end of the third dummy wiring 5(s+1) next to the third dummy wiring 5(s) is coupled to the other end of the linear resistor 3(s) via a third capacitor C1(s+1). One end of at least one linear resistor 3(s) is connected to the first output electrode EP. The first output electrode EP may be located inside the third dummy wiring region DM3, but is not required to be located therein.

[0058] A fourth dummy wiring region DM4 can be formed around the second voltage detection resistor RNS. The fourth dummy wiring region DM4 includes a plurality of fourth dummy wirings 5(t), one end of each of which is coupled to one end of the linear resistor 3(t) via a fourth capacitor C1(t). Each fourth dummy wiring 5(t) is coupled to only one end of the linear resistor via a capacitor, but not to the other end. One end of the fourth dummy wiring 5(t+1) next to the fourth dummy wiring 5(t) is coupled to the other end of the linear resistor 3(t) via a fourth capacitor C1(t+1). One end of at least one linear resistor 3(t) is connected to the second output electrode EN. The second output electrode EN may be located inside the fourth dummy wiring region DM4, but is not required to be located therein. A reference electrode EG is disposed between the third dummy-wiring region DM3 and the fourth dummy-wiring region DM4, and is connected to one end of at least one linear resistor.

[0059] The third dummy wiring region DM3 and the fourth dummy wiring region DM4 can also be omitted. However, the resistor is slightly affected by the presence or absence of surrounding dummy wiring regions. Therefore, in order to minimize the effect on the measurement results, it is desirable for the resistor chip 10 to include the third dummy wiring region DM3 and the fourth dummy wiring region DM4. In other words, since the resistor chip 10 of this embodiment is intended for voltage measurement, if dummy wiring regions are arranged around all of the first resistor RP, the second resistor RN, the first voltage detection resistor RPS, and the second voltage detection resistor RNS, the equivalence of factors affecting voltage measurement is increased, and more precise measurements can be performed.

[0060] FIG. 11 is a perspective view of the coupling portion indicated by the first region S1 in FIG.

[0061] The linear resistors 3 (linear resistors 3(n)) are embedded in the insulating layer 2, and adjacent linear resistors 3 are electrically connected via via electrodes and buried electrodes BE (buried electrodes BE(n)). That is, one end of the first linear resistor 3 is connected to the buried electrode BE via a fourth via electrode VE4, and one end of the adjacent second linear resistor 3 is connected to the buried electrode BE via a fifth via electrode VE5. One end of the linear resistor 3 is capacitively coupled to one end of the dummy wiring 5 (first dummy wiring 5(n)). In other words, a capacitor (parasitic capacitor: see capacitor C1 in FIG. 10 ) is formed between one end of the linear resistor 3 and one end of the dummy wiring 5, and the material of the insulating layer 2 (in this example, the material of the first dielectric layer 2A) is interposed between the electrodes constituting the capacitor. The structures of the coupling portions of the other resistors (second resistor RN, first voltage detection resistor RPS, second voltage detection resistor RNS) are the same as the structure of the coupling portion in the first region S1 of the first resistor RP.

[0062] 12A and 12B are a vertical cross-sectional view (FIG. 12A) and a plan view (FIG. 12B) of the coupling portion shown in FIG. 11 taken along line AA. In the vertical cross-sectional view, the upper dielectric layer 2A Ｈ and the lower dielectric layer 2A. ＬIn the plan view, the region located below the upper dielectric layer 2A is omitted. Ｈ 1 shows a state in which the region above the wire resistor 3 has been removed.

[0063] The width W5 of one dummy wiring 5 in the X-axis direction is smaller than the maximum width W3 in the X-axis direction of a group including two adjacent linear resistors 3. When viewed from the Z-axis direction, an end of one dummy wiring 5 partially overlaps the ends of two linear resistors 3 (a semi-overlapping structure), and the buried electrode BE is located below the dummy wiring 5. In the case of this semi-overlapping structure, the capacitance of the capacitor is smaller than in the full overlapping structure (FIG. 13(B2)).

[0064] 13A to 13C are plan views (FIGS. 13B1, 13B2, and 13B3) of the coupling portion according to the modified example.

[0065] 13(B1), the planar shape of the tip of the linear resistor 3 shown in FIG. 12(B) is rounded to a semicircular shape, and the corners of the planar shape of the buried electrode BE are rounded to match this shape. Since there are no right-angled corners, electric field concentration is alleviated, and the breakdown voltage can be increased.

[0066] 13(B2), the width in the X-axis direction of the dummy wiring 5 shown in Fig. 13(B1) is increased, and in plan view, the width in the X-axis direction of the dummy wiring 5 is equal to or greater than the maximum width in the X-axis direction of a group including two adjacent linear resistors 3. Since the capacitance of a capacitor depends on the electrode area, increasing the capacitor capacitance can reduce the electric field per unit area when the amount of charge stored in the capacitor is the same.

[0067] 13(B3), there is no linear resistor 3 directly below the dummy wiring 5. In other words, the overlap rate between the dummy wiring 5 and the linear resistor 3 in a plan view is 0%. Even in this case, a parasitic capacitor can be formed between the tip of the dummy wiring 5 and one end of the linear resistor 3. Note that, if the distance between the tip of the dummy wiring 5 and one end of the linear resistor 3 becomes large, the parasitic capacitor is no longer formed, the electrical coupling is released, and alternating current such as a transient current generated on the first electrode side no longer flows through the linear resistor.

[0068] FIG. 14 is a plan view of the dummy wiring 5 located near the substrate edge, and is an enlarged view of the electrode vicinity region SE in FIG.

[0069] The plurality of linear resistors 3 are aligned along the X-axis direction. One end of each linear resistor 3 is capacitively coupled to a dummy wire 5. The plurality of dummy wires 5 extend in a ring shape to surround the first electrode E1. A positive first voltage V1 is applied to the first electrode E1 from the first input terminal HV(+). For example, the first voltage V1 is 5000 V. Assume that a specific linear resistor 3 is located at a distance ΔXα from the first electrode E1 in the X-axis direction. The voltage Vα of the linear resistor 3 at the distance ΔXα is, for example, 2500 V. The shortest distance ΔY in the Y-axis direction between the dummy wire 5 connected to this specific linear resistor 3 and the annular conductor 1R is set so that the voltage gradient (Vα / ΔY) in the region defined by ΔY is 100 V / μm or less (Vα / ΔY≦100 V / μm). By making the voltage gradient smaller than the threshold value, the electric field strength near the side surface of the resistor chip substrate can be reduced, and the withstand voltage of the resistor chip can be further improved. Since Vα / 100 (μm)≦ΔY (μm), when Vα=2500V, 25 (μm)≦ΔY (μm) is satisfied.

[0070] As a specific instantaneous maximum voltage expected in electric vehicles or hybrid vehicles, Vα can be set to 10,000 V. Similarly, the lower limit of Vα can be set to 500 V. That is, the resistor chip can be designed with 500 V≦Vα≦10,000 V. When Vα is within this range, 5 (μm)≦ΔY≦100 (μm) can be satisfied.

[0071] The resistor chip 10 includes an annular conductor 1R disposed along a side surface of a semiconductor substrate so as to surround a resistor on the semiconductor substrate in a plan view and embedded in an insulating layer. The shortest distance ΔY (μm) between the plurality of dummy wirings 5 ​​and the annular conductor 1R is set to satisfy Vα(V) / 100(V / μm)≦ΔY(μm), where Vα(V) is the magnitude of the voltage between the potential of the dummy wiring 5 that gives the shortest distance ΔY and the ground potential.

[0072] In practice, there are two types of structures: one in which the linear resistor 3 and the dummy wiring 5 are not connected but are capacitively coupled, and another in which they are electrically connected. In the electrically connected structure, the potential of the linear resistor 3 is equal to the potential of the dummy wiring, but in the capacitively coupled structure, these potentials may be different. Even in such a case, assuming that the linear resistor 3 and the dummy wiring 5 are electrically connected, if ΔY satisfies the above-mentioned range, the electric field strength near the side surface of the substrate can be reduced and the withstand voltage of the resistor chip can be increased.

[0073] The resistance value R between the first electrode E1 and the linear resistor 3 at a distance ΔXα ＴＨ , the resistance value R between the first electrode E1 and the reference electrode EG ＨＡＬＦ In this case, the voltage Vα = V1 × ((R ＨＡＬＦ -R ＴＨ ) / R ＨＡＬＦ In the region indicated by the distance ΔXα, if there are N linear resistors 3, and the resistance value of each is R, then the resistance value R ＴＨ= N × R. If the number of dummy wirings 5 ​​is N / 2 when the number of linear resistors 3 is even, the potential difference ΔV5 between adjacent dummy wirings 5 ​​can be, for example, ΔV5 = 2 × (Vα / N) when these dummy wirings 5 ​​are connected to the respective linear resistors. In such a case, the distance X5 between adjacent dummy wirings 5 ​​can also be set so that ΔV5 / X5 ≦ 100 (V / μm). In reality, there are structures in which the linear resistors 3 and dummy wirings 5 ​​are capacitively coupled without being connected, and structures in which they are electrically connected. However, designing assuming that they are electrically connected is safe from the standpoint of increasing the breakdown voltage.

[0074] When the maximum value of Vα is 10,000 V and N = 100, the relationship X5 can be set to 2 (μm) ≦ X5. The electric field strength threshold of 100 (V / μm) is set based on the breakdown voltage between wirings in the insulating film. Since the breakdown voltage of an exemplary commercially available product is 373 (V / μm), the upper threshold electric field strength can be set to 100 (V / μm) as described above, taking into account a margin. When the distance between linear resistors is set to 100 (V / μm) or less, the distance X5 between adjacent dummy wirings 5 ​​can be set to 0.1 μm ≦ X5 ≦ 5 μm. While the distance relationships in the peripheral structure of the first electrode E1 have been described above, these relationships can also be applied to the peripheral structure of the second electrode.

[0075] FIG. 15 is a plan view illustrating the electrical connection relationship of the voltage divider circuit formed on the resistor chip 10. As shown in FIG.

[0076] This resistor chip 10 is a modified version of the resistor chip 10 shown in FIG. 10 , with only the connection relationship of each dummy wiring 5 changed. That is, one end of each dummy wiring 5(n) surrounding the first electrode E1 is electrically connected to one end of the linear resistor 3(n). The other ends of these dummy wirings 5(n) are not electrically connected to the linear resistor 3(n), but are capacitively coupled thereto. Similarly, one end of each dummy wiring 5(m) surrounding the second electrode E2 is electrically connected to one end of the linear resistor 3(m). The other ends of these dummy wirings 5(m) are not electrically connected to the linear resistor 3(m), but are capacitively coupled thereto.

[0077] In this example, in the third dummy wiring region DM3, one end of some of the dummy wirings 5(s) is electrically connected to one end of the linear resistor 3(s). In the fourth dummy wiring region DM4, one end of some of the dummy wirings 5(t) is electrically connected to one end of the linear resistor 3(t).

[0078] The dummy wiring 5 and the linear resistor 3 are electrically connected through a via electrode and a buried electrode. That is, a via electrode extending downward from the dummy wiring 5 is connected to a buried electrode, and the buried electrode is connected to one end of the linear resistor 3 through another via electrode (see FIG. 18 ).

[0079] One end of the dummy wiring 5, which is affected by the electric field around the first electrode E1 or the second electrode E2, is connected to the linear resistor 3, but the other end is not connected to the linear resistor 3, so it is possible to suppress the effect of the potential difference occurring across the linear resistor 3. In other words, if the two ends of the linear resistor 3, across which a potential difference occurs, are connected, a current will flow through the dummy wiring 5, but this structure does not cause this phenomenon.

[0080] FIG. 16 is a plan view illustrating the electrical connection relationship of the voltage divider circuit formed on the resistor chip 10. As shown in FIG.

[0081] 15, the capacitor C1 has been removed, and the capacitive coupling between the dummy wiring 5 and the linear resistor 3 has been released. In other words, the distance between the tip of the dummy wiring 5, which was capacitively coupled, and the linear resistor 3 has been increased, so that they are no longer capacitively coupled.

[0082] Even in this structure, one end of the dummy wiring 5, which is affected by the electric field around the first electrode E1 or the second electrode E2, is connected to the linear resistor 3, but the other end is not connected to the linear resistor 3, so it is possible to suppress the effect of the potential difference occurring across the linear resistor 3. In other words, no current caused by the potential difference across the linear resistor 3 flows through the dummy wiring 5.

[0083] FIG. 17 is a diagram showing a planar configuration for explaining the electrical connection relationship of the voltage dividing circuit formed on the resistor chip 10.

[0084] This resistor chip 10 is the resistor chip 10 shown in FIG. 16 , in which one end of the dummy wirings 5 ​​(dummy wirings (5(n), 5(m), 5(s), 5(t)) with capacitive coupling released is electrically connected to one end of the linear resistor 3. Furthermore, in this resistor chip 10, so that both ends of each linear resistor 3 are not electrically connected by the dummy wirings 5, each dummy wiring 5(n) surrounding the first electrode E1 is separated by a first space SP1, and each dummy wiring 5(m) surrounding the second electrode E2 is separated by a second space SP2. The first space SP1 is a collection of gaps between the dummy wirings 5(n) that are spaced apart and opposed to each other along the Y-axis direction, and is aligned along the X-axis direction, so that it appears as a slit as a whole. The second space SP2 is also a collection of gaps between the dummy wirings 5(m) that are spaced apart and opposed to each other along the Y-axis direction, and is aligned along the X-axis direction, so that it appears as a slit as a whole.

[0085] Even in this structure, one end of the dummy wiring 5, which is affected by the electric field around the first electrode E1 or the second electrode E2, is connected to the linear resistor 3, but the other end is not connected to the linear resistor 3, so the effect of the potential difference generated between both ends of the linear resistor 3 can be suppressed.

[0086] Specifically, one of the plurality of first dummy wirings 5(n) １ ) is electrically connected to a first location of a first linear resistor 3(n) (first resistance layer) among the plurality of linear resistors 3(n) (resistance layers). Another dummy wiring 5(n) among the plurality of first dummy wirings 5(n) is electrically connected to a first location of a first linear resistor 3(n) (first resistance layer) among the plurality of first dummy wirings 5(n). ２ ) is electrically connected to a second location, which is different from the first location, of the plurality of linear resistors 3(n) (resistance layer). １ ) and another dummy wiring 5(n ２ ) on the opposite side from the second location, faces each other via a gap (first space SP1).

[0087] Similarly, one dummy wiring 5(m) among the plurality of second dummy wirings 5(m) １ ) is electrically connected to a first location of a first linear resistor 3(m) (first resistance layer) in the plurality of linear resistors 3(m) (resistance layer). Another dummy wiring 5(m) in the plurality of first dummy wirings 5(m) is electrically connected to a first location of a first linear resistor 3(m) (first resistance layer) in the plurality of linear resistors 3(m) (resistance layer). ２ ) is electrically connected to a second location, which is different from the first location, of the plurality of linear resistors 3(m) (resistance layer). １ ) and another dummy wiring 5 (m ２ ) on the opposite side from the second location, faces each other via a gap (second space SP2).

[0088] FIG. 18 is a perspective view of the connection portion indicated by the second region S2 in FIG.

[0089] The second region S2 differs from the first region S1 shown in FIG. 11 in that one end of the linear resistor 3 is electrically connected to one end of the dummy wiring 5 (first dummy wiring 5(n)). The other structures are the same as those of the first region S1. That is, one end of the first linear resistor 3 is electrically connected to the buried electrode BE via a fourth via electrode VE4, and one end of the adjacent second linear resistor 3 is electrically connected to the buried electrode BE via a fifth via electrode VE5. The buried electrode BE is connected to one end of the dummy wiring 5 via a sixth via electrode VE6. The structures of the electrical connection portions of the other resistors (the second resistor RN, the first voltage detection resistor RPS, and the second voltage detection resistor RNS) are the same as the structure of the electrical connection portion of the first resistor RP in the second region S2.

[0090] 19A and 19B are a vertical cross-sectional view (FIG. 19A) and a plan view (FIG. 19B) of the connection portion shown in FIG. 18 taken along line AA.

[0091] The structure of the connection portion shown in the figure is a structure in which a sixth via electrode VE6 is added to the structure shown in Fig. 12, and the other structure is the same as the structure shown in Fig. 12. The sixth via electrode VE6 connects the buried electrode BE and the dummy wiring 5. The number of sixth via electrodes VE6 present at one connection point may be one or more.

[0092] 20A and 20B are plan views (FIG. 20B1 and FIG. 20B2) of a connection portion according to a modified example.

[0093] The connection portion structure shown in Figures 20(B1) and 20(B2) is a structure in which a sixth via electrode VE6 is added to the structure shown in Figures 13(B1) and 13(B2), but the other structures are the same as those shown in these structures. In plan view, the sixth via electrode VE6 is located within the gap between the ends of adjacent linear resistors 3. Since this gap extends along the Y-axis direction, when multiple sixth via electrodes VE6 are arranged at one connection point, they can be arranged along the Y-axis direction. Of course, the number of sixth via electrodes VE6 present at one connection point may be one.

[0094] Figure 21 is a graph showing the breakdown voltage (kV) obtained for a sample element. When the voltage of the first and second electrodes is increased, with the potential of the reference electrode located in the center set to ground potential, breakdown occurs at a certain voltage. The breakdown voltage is the voltage at this point.

[0095] Ten samples (sample numbers (No. 1 to No. 10)) of each type of structure of the comparative example, example A, and example B were manufactured.

[0096] The resistor chip of Example A is a type of resistor chip equipped with capacitively coupled dummy wiring, has the capacitively coupled electrical connection relationship shown in FIG. 10, has a resistor array structure as shown in FIG. 5, and is equipped with a dummy wiring pattern as shown in FIG. 23(A). The coupling structure of the dummy wiring and linear resistor is shown in FIG. 12. The maximum breakdown voltage (kV) of the resistor chip of Example A was 5.6 kV, the minimum was 5.4 kV, the average was 5.5 kV, and the variation range (maximum value - minimum value) was 0.2 kV. Note that Example A does not have a third dummy wiring region or a fourth dummy wiring region (see FIG. 24).

[0097] The resistor chip of Example B is a resistor chip of the type equipped with electrically connected dummy wiring, has the electrical connection relationship of the electrically connected type shown in FIG. 17, has a resistor array structure as shown in FIG. 5, and is equipped with a dummy wiring pattern as shown in FIG. 23(B). The coupling structure of the dummy wiring and linear resistor is shown in FIG. 19, and the spacing between adjacent dummy wirings is the same as in Example A. The maximum breakdown voltage (kV) of the resistor chip of Example B was 5.6 kV, the minimum was 5.5 kV, the average was 5.6 kV, and the variation range (maximum value - minimum value) was 0.1 kV. Note that Example B is equipped with a third dummy wiring region and a fourth dummy wiring region (see FIG. 25).

[0098] The resistor chip of the comparative example is a type of resistor chip that does not have dummy wiring, and has a structure in which the dummy wiring is removed from the resistor chip of Example A. The maximum value of the breakdown voltage (kV) of the resistor chip of the comparative example was 4.5 kV, the minimum value was 3.8 kV, the average value was 4.2 kV, and the fluctuation range (maximum value - minimum value) was 0.7 kV.

[0099] The data for Example A is superior to the data for the Comparative Example. Specifically, the maximum and average values ​​of the output voltage are increased, and the fluctuation range is narrowed. The data for Example B is also superior to the data for the Comparative Example. The maximum and average values ​​of the breakdown voltage are increased, and the fluctuation range is narrowed. When the resistor chip was broken down by the application of a high voltage exceeding the upper limit, in the Comparative Example (without dummy wiring), traces of breakdown were observed along the width direction (Y-axis direction) of the resistor chip. On the other hand, in the structures with dummy wiring, such as in Examples A and B, traces of breakdown were observed along the longitudinal axis (X-axis direction) of the resistor chip. One of the reasons for the increase in breakdown voltage due to the inclusion of multiple dummy wirings is that the electric field intensity distribution around the first and second electrodes is gentle. In other words, in this embodiment, by arranging dummy wirings around the resistive element, the electric field is relaxed, improving the breakdown voltage. The multiple dummy wirings are arranged in a stripe pattern along the direction away from the first and second electrodes, which gentles the change in electric field intensity along the direction away from the first and second electrodes. Furthermore, components such as transient currents can also flow through the wire resistor closer to the ground potential.

[0100] In this example, the data of Example B is superior to Example A in terms of the range of variation, but the difference is within the margin of error, and both exhibit excellent effects.

[0101] FIG. 22 is a plan view of a modified structure of the voltage divider circuit portion of the resistor chip.

[0102] 5, a single linear resistor 3 extending along the Y-axis direction is aligned along the X-axis direction. In contrast, in this example, multiple (two) linear resistors 3 are aligned along the Y-axis direction, and these linear resistor groups are aligned along the X-axis direction.

[0103] The first resistor RP is a linear resistor 3 (n Ｙ１ ) and linear resistor 3(n Ｙ２ ) are provided. Ｙ１ ) and linear resistor 3(n Ｙ２ ) refers to the via electrodes and buried electrodes BE(n Ｙ) are electrically connected via a linear resistor 3(n Ｙ１ ) is connected to the linear resistor 3(n) adjacent in the X-axis direction through a via electrode and a buried electrode BE(n+1). Ｙ１ +1) is electrically connected to the wire resistor 3(n Ｙ１ +1) is the via electrode and the buried electrode BE(n Ｙ +1) and a linear resistor 3(n Ｙ２ +1).

[0104] The second resistor RN is a linear resistor 3 (m Ｙ１ ) and linear resistor 3 (m Ｙ２ ) are provided. Ｙ１ ) and wire resistor 3 (m Ｙ２ ) refers to the via electrodes and buried electrodes BE(m Ｙ ) are electrically connected via a linear resistor 3 (m Ｙ１ ) is connected to the linear resistor 3(m) adjacent in the X-axis direction through a via electrode and a buried electrode BE(m+1). Ｙ１ +1) is connected to a linear resistor 3 (m Ｙ１ +1) is the via electrode and the buried electrode BE(m Ｙ +1), and the linear resistors 3 (m Ｙ２ +1).

[0105] 23A is a plan view of the vicinity of the first electrode of a capacitively coupled dummy wiring, and FIG. 23B is a plan view of the vicinity of the first electrode of an electrically connected dummy wiring.

[0106] The capacitively coupled dummy wiring 5 (FIG. 23A) is capacitively coupled to the resistor R and surrounds the first electrode E1. The planar shape of the first electrode E1 is quadrangular, but the corners are rounded, and the dummy wiring 5 forms an arc along the outer edge of the first electrode E1.

[0107] The electrically connected dummy wiring 5 (FIG. 23B) is electrically connected to the resistor R and surrounds the first electrode E1. The planar shape of the first electrode E1 is rectangular with rounded corners, and the dummy wiring 5 forms an arc along the outer edge of the first electrode E1. In the region of the first electrode E1 opposite the resistor R, a slit (first space SP1) is formed between the dummy wirings 5.

[0108] The structure on the second electrode side is the same as the structure on the first electrode side.

[0109] 24 is a plan view of a resistor chip equipped with capacitively coupled dummy wiring. Since each element is embedded in an insulating layer 2, the insulating layer located above the necessary elements is omitted from the illustration.

[0110] The first dummy wiring region DM1 includes a group of dummy wirings capacitively coupled to the first resistors RP. The first resistors RP extend along the X-axis direction as a whole. At the capacitive coupling positions between the dummy wirings and the first resistors RP, the dummy wirings extend along the Y-axis direction. That is, at the capacitive coupling positions, the longitudinal direction of the first resistors RP and the extension direction of each dummy wiring are perpendicular to each other.

[0111] The first dummy wiring region DM1 is the first electrode side region DM1 Ｔ and the first output electrode side region DM1 Ｅ An example of actual dummy wirings arranged in the first dummy wiring region DM1 is as shown in FIG.

[0112] First electrode side area DM1 Ｔ is made up of a group of dummy wirings surrounding the first electrode E1. These dummy wirings extend along the first arrow AR1 to surround the first electrode E1. Of the dummy wirings surrounding the first electrode E1, there is a gap between the dummy wirings located at the outermost periphery and the annular conductor 1R, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY. There is a gap between this dummy wiring located at the outermost periphery and the annular conductor 1R, and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0113] First output electrode side area DM1 Ｅis made up of a group of dummy wirings that do not surround the first electrode E1. These dummy wirings extend along the fifth arrow AR5, away from the first resistor RP, and approach the annular conductor 1R. There is a gap between their tips and the annular conductor 1R along the Y-axis direction, and the shortest distance between them along the Y-axis direction is ΔY as described above.

[0114] The second dummy wiring region DM2 includes a group of dummy wirings capacitively coupled to the second resistors RN. The second resistors RN extend along the X-axis direction as a whole. At the capacitive coupling positions between the dummy wirings and the second resistors RN, the dummy wirings extend along the Y-axis direction. That is, at the capacitive coupling positions, the longitudinal direction of the second resistors RN and the extension direction of each dummy wiring are perpendicular to each other.

[0115] The second dummy wiring region DM2 is the second electrode side region DM2 Ｔ and the second output electrode side region DM2 Ｅ An example of actual dummy wirings arranged in the second dummy wiring region DM2 is the same as the structure symmetrical with respect to the YZ plane of the structure in FIG.

[0116] Second electrode side area DM2 Ｔ consists of a group of dummy wirings surrounding the second electrode E2. These dummy wirings extend along the second arrow AR2 to surround the second electrode E2. Of the dummy wirings surrounding the second electrode E2, there is a gap between the dummy wirings located at the outermost periphery and the annular conductor 1R, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY. There is a gap between this dummy wiring located at the outermost periphery and the annular conductor 1R, and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0117] Second output electrode side area DM2 Ｅ is made up of a group of dummy wirings that do not surround the second electrode E2. These dummy wirings extend along the sixth arrow AR6, away from the second resistor RN, and approach the annular conductor 1R. There is a gap between their tips and the annular conductor 1R along the Y-axis direction, and the shortest distance between them along the Y-axis direction is ΔY as described above.

[0118] 25 is a plan view of a resistor chip equipped with electrically connected dummy wiring. Since each element is embedded in an insulating layer 2, the insulating layer located above the necessary elements is omitted.

[0119] The first dummy wiring region DM1 includes a group of dummy wirings electrically connected to the first resistors RP. The first resistors RP extend along the X-axis direction as a whole. At the electrical connection positions between the dummy wirings and the first resistors RP, the dummy wirings extend along the Y-axis direction. In other words, at the electrical connection positions, the longitudinal direction of the first resistors RP and the extension direction of each dummy wiring are perpendicular to each other.

[0120] The first dummy wiring region DM1 is the first electrode side region DM1 Ｔ and the first output electrode side region DM1 Ｅ An example of actual dummy wirings arranged in the first dummy wiring region DM1 is as shown in FIG.

[0121] First electrode side area DM1 Ｔ is composed of a group of dummy wirings surrounding the first electrode E1. These dummy wirings extend along the first arrow AR1 to surround the first electrode E1, but are separated by a first space SP1 in the region of the first electrode E1 opposite the first resistor RP. Of the dummy wirings that extend to the position of the first space SP1, there is a gap between the dummy wirings located at the outermost periphery and the annular conductor 1R, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY. There is a gap between this dummy wiring located at the outermost periphery and the annular conductor 1R, and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0122] First output electrode side area DM1 Ｅ is made up of a group of dummy wirings that do not surround the first electrode E1 and do not reach the first space SP1. These dummy wirings extend along the fifth arrow AR5, away from the first resistor RP, and approach the annular conductor 1R. There is a gap between their tips and the annular conductor 1R along the Y-axis direction, and the shortest distance between them along the Y-axis direction is ΔY as described above.

[0123] In this example, the first output electrode side region DM1 Ｅ Some of the dummy wirings in are also arranged around the first output electrode EP.

[0124] The second dummy wiring region DM2 includes a group of dummy wirings electrically connected to the second resistors RN. The second resistors RN extend along the X-axis direction as a whole. At the electrical connection positions between the dummy wirings and the second resistors RN, the dummy wirings extend along the Y-axis direction. In other words, at the electrical connection positions, the longitudinal direction of the second resistors RN and the extension direction of each dummy wiring are perpendicular to each other.

[0125] The second dummy wiring region DM2 is the second electrode side region DM2 Ｔ and the second output electrode side region DM2 Ｅ An example of actual dummy wirings arranged in the second dummy wiring region DM2 is the same as the structure shown in FIG.

[0126] Second electrode side area DM2 Ｔ is made up of a group of dummy wirings surrounding the second electrode E2. These dummy wirings extend along the second arrow AR2 to surround the second electrode E2, but are separated by a second space SP2 in the region of the second electrode E2 opposite the second resistor RN. Of the dummy wirings that extend to the position of the second space SP2, there is a gap between the outermost dummy wiring and the annular conductor 1R, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY. There is a gap between this outermost dummy wiring and the annular conductor 1R, and the shortest distance between them along the X-axis direction ΔX can be set to ΔX = ΔY.

[0127] Second output electrode side area DM2 Ｅ is made up of a group of dummy wirings that do not surround the second electrode E2 and do not reach the second space SP2. These dummy wirings extend along the sixth arrow AR6 away from the second resistor RN and approach the annular conductor 1R, with a gap between their tips and the annular conductor 1R along the Y-axis direction, and the shortest distance between them along the Y-axis direction is ΔY as described above.

[0128] In this example, the second output electrode side region DM2 Ｅ Some of the dummy wirings in are also arranged around the second output electrode EN.

[0129] The third dummy wiring region DM3 includes a group of dummy wirings electrically connected to the first voltage detection resistor RPS. At the electrical connection positions between the dummy wirings and the first voltage detection resistor RPS, the dummy wirings extend along the Y-axis direction.

[0130] The dummy wiring group included in the third dummy wiring region DM3 extends along the third arrow AR3, away from the first voltage detection resistor RPS, and approaches the annular conductor 1R, and there is a gap along the Y-axis direction between their tips and the annular conductor 1R, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY.

[0131] The fourth dummy wiring region DM4 includes a group of dummy wirings electrically connected to the second voltage detection resistors RNS. At the electrical connection positions between the dummy wirings and the second voltage detection resistors RNS, the dummy wirings extend along the Y-axis direction.

[0132] The dummy wiring group included in the fourth dummy wiring region DM4 extends along the fourth arrow AR4, away from the second voltage detection resistor RNS, and approaches the annular conductor 1R, and there is a gap along the Y-axis direction between their tips and the annular conductor 1R, and the shortest distance between them along the Y-axis direction is the above-mentioned ΔY.

[0133] The third and fourth dummy wiring regions can also be provided in a resistor chip of the type shown in FIG. 24. The number of dummy wirings surrounding the electrodes can be, for example, about K (e.g., K=6). In other words, the first electrode side region DM1 Ｔ , or the second electrode side region DM2 ＴThe number of dummy wirings coupled or connected to one long side (X-axis) of the rectangular resistor included in the resistor may be K, where 3≦K≦30. The length of the dummy wirings may also be shorter the closer they are to the reference electrode EG from the first electrode E1 or the second electrode E2. The reference electrode EG may also have ground potential. When the dummy wirings and the linear resistor are located at different depths, a configuration in which the dummy wirings and the linear resistor overlap over the entire length of the linear resistor (Y-axis direction) in a plan view is also possible. However, from the viewpoint of voltage resistance, a small overlap rate is considered preferable (e.g., an overlap rate of 10% or less along the Y-axis direction).

[0134] FIG. 26 is a diagram showing a longitudinal cross-sectional configuration (first modified example) of a portion taken along line AA in FIG.

[0135] The resistor chip 10 of this example has a structure in which the depth position of the first dummy wiring 5(n) is shifted to the same depth position as the first buried electrode BE1 in the resistor chip 10 shown in Fig. 6, and other points are the same as the structure shown in Fig. 6. In other words, the lower dielectric layer 2A located above the insulating layer 2 Ｌ The peripheral electrode 1R1, the first buried electrode BE1, and the first dummy wiring 5(n) are formed on the surface of the semiconductor substrate 1. This structure has the advantage that the peripheral electrode 1R1, the first buried electrode BE1, and the first dummy wiring 5(n) can be formed by the same process (a manufacturing method such as a sputtering method, a vapor deposition method, or a plating method).

[0136] Each linear resistor constituting the resistor R is capacitively coupled or electrically connected to the first dummy wiring 5(n). For capacitive coupling, the tip of the first dummy wiring 5(n) is positioned near one end of the linear resistor. For electrical connection, one end of the linear resistor is connected to the tip of the underlying first dummy wiring 5(n) via a via electrode. While the figure shows the structure on the first electrode E1 side, the structure on the second electrode side is the same as the structure on the first electrode E1 side.

[0137] In the first modified example, the cross-sectional configuration of the portions along lines B-B, C-C, and D-D in Figure 4 is a structure in which the depth position of each dummy wiring is moved to the depth position of the buried electrode in Figures 7, 8, and 9, as in the case of Figure 26.

[0138] FIG. 27 is a diagram showing a longitudinal cross-sectional configuration (second modified example) of a portion taken along line AA in FIG.

[0139] The resistor chip 10 of this example is the resistor chip 10 shown in Figure 6, in which the material of the first dummy wiring 5(n) has been replaced from a conductor such as metal to a resistive material, which is used as a dummy resistance layer. In other respects, it is the same as the structure shown in Figure 6. The dummy resistance layer does not function as a resistor in the resistor R. It is thought that the multiple dummy resistance layers function in the same way as dummy wiring by mitigating the electric field around the electrodes to which a high voltage is applied.

[0140] In the second modified example, the longitudinal cross-sectional configurations of the portions along lines B-B, C-C, and D-D in Fig. 4 are structures in which the dummy wirings are replaced with dummy resistance layers in Figs. 7, 8, and 9, similar to the case of Fig. 27. (Note) As described above, according to the resistor chip 10 (semiconductor device), the provision of dummy wirings makes it possible to increase the breakdown voltage of the resistor chip 10. Various embodiments of the present disclosure can be defined as the following notes [A1] to [A18].

[0141] [A1] A semiconductor device comprising: a semiconductor substrate 1; an insulating layer 2 provided on the semiconductor substrate 1; a resistor R embedded in the insulating layer 2 and electrically connecting a plurality of resistive layers (linear resistors 3); a first electrode E1 electrically connected to a first end of the resistor R; a second electrode E2 electrically connected to a second end of the resistor R; and a plurality of first dummy wirings 5(n) arranged around the first electrode E1 and each capacitively coupled to a plurality of resistive layers (linear resistors 3(n)) in the resistor R.

[0142] [A2] The semiconductor device described in A1, wherein the resistor R comprises a first resistor RP electrically connected to the first electrode E1, a second resistor RN electrically connected to the second electrode E2, and a voltage detection resistor (RPS, RNS) electrically connecting the first resistor RP and the second resistor RN and having a resistance value lower than that of either the first resistor RP or the second resistor RN, and wherein the semiconductor device comprises a first output electrode EP, a second output electrode EN, and a reference electrode EG electrically connected to different locations of the voltage detection resistor (RPS, RNS), respectively.

[0143] [A3] The semiconductor device described in A2 further includes a plurality of second dummy wirings 5(m) arranged around the second electrode E2 and each capacitively coupled to a plurality of resistive layers (linear resistors 3(m)) in the second resistor RN, and the plurality of first dummy wirings 5(n) are each capacitively coupled to a plurality of resistive layers (linear resistors 3(n)) in the first resistor RP.

[0144] [A4] The semiconductor device described in A3, wherein the voltage detection resistor comprises: a first voltage detection resistor RPS electrically connected to the first resistor RP and having a lower resistance value than the first resistor RP; and a second voltage detection resistor RNS electrically connected between the second resistor RN and the first voltage detection resistor RPS and having a lower resistance value than the second resistor RN; and further comprising: a plurality of third dummy wirings 5(s) capacitively coupled to the plurality of resistive layers (linear resistors 3) in the first voltage detection resistor RPS; and a plurality of fourth dummy wirings 5(t) capacitively coupled to the plurality of resistive layers (linear resistors 3) in the second voltage detection resistor RNS.

[0145] [A5] The semiconductor device according to any one of A1 to A4, further comprising a plurality of first dummy resistance layers (5(n): FIG. 27) instead of the plurality of first dummy wirings 5(n).

[0146] [A6] A semiconductor device comprising: a semiconductor substrate 1; an insulating layer 2 provided on the semiconductor substrate 1; a resistor R embedded in the insulating layer 2 and electrically connecting a plurality of resistive layers (linear resistors 3); a first electrode E1 electrically connected to a first end of the resistor R; a second electrode E2 electrically connected to a second end of the resistor R; and a plurality of first dummy wirings 5(n) arranged around the first electrode E1 and electrically connected to the plurality of resistive layers (linear resistors 3(n)) in the resistor R, respectively.

[0147] [A7] One of the plurality of first dummy wirings 5(n) １ ) is electrically connected to a first location of a first resistance layer (linear resistor 3(n)) in the plurality of resistance layers (linear resistors 3(n)), and is connected to another dummy wiring (n) in the plurality of first dummy wirings 5(n). ２ ) is electrically connected to a second location different from the first location in the plurality of resistance layers (linear resistors 3(n)), and one dummy wiring 5(n １ ) and another dummy wiring 5(n ２ The semiconductor device according to A6, wherein the end portion of the second portion opposite the second portion of the first electrode 1 faces the end portion of the second electrode 1 opposite the second portion of the first electrode 1 via a gap (first space SP1).

[0148] [A8] A semiconductor device as described in A6 or A7, wherein the resistor R comprises a first resistor RP electrically connected to the first electrode E1, a second resistor RN electrically connected to the second electrode E2, and a voltage detection resistor (RPS, RNS) electrically connecting the first resistor RP and the second resistor RN and having a resistance value lower than both the first resistor RP and the second resistor RN, and wherein a first output electrode EP, a second output electrode EN, and a reference electrode EG are electrically connected to different locations of the voltage detection resistor (RPS, RNS), respectively.

[0149] [A9] The semiconductor device described in A8 further includes a plurality of second dummy wirings 5(m) arranged around the second electrode E2 and electrically connected to a plurality of resistive layers (linear resistors 3(m)) in the second resistor RN, and the plurality of first dummy wirings 5(n) are electrically connected to a plurality of resistive layers (linear resistors 3(n)) in the first resistor RP.

[0150] [A10] The semiconductor device described in A9, wherein the voltage detection resistor comprises a first voltage detection resistor RPS electrically connected to the first resistor RP and having a lower resistance value than the first resistor RP, and a second voltage detection resistor RNS electrically connected between the second resistor RN and the first voltage detection resistor RPS and having a lower resistance value than the second resistor RN, and further comprises a plurality of third dummy wirings electrically connected to a plurality of resistive layers (linear resistors 3(n)) in the first voltage detection resistor RPS, and a plurality of fourth dummy wirings electrically connected to a plurality of resistive layers (linear resistors 3) in the second voltage detection resistor RNS.

[0151] [A11] The semiconductor device according to any one of A6 to A10, further comprising a plurality of first dummy resistance layers (5(n): FIG. 27) instead of the plurality of first dummy wirings 5(n).

[0152] [A12] The semiconductor device according to any one of A1 to A11, wherein the resistance value between the first electrode E1 and the second electrode E2 is 1 MΩ or more and 1000 MΩ or less.

[0153] [A13] The semiconductor device according to any one of A1 to A12, wherein the material of the resistive layer constituting the resistor R includes at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN.

[0154] [A14] The semiconductor device according to any one of A1 to A13, wherein the material of the first dummy wiring 5(n) includes Al, Cu, W, or Ti.

[0155] [A15] The semiconductor device according to any one of A1 to A14, further comprising an annular conductor disposed in a planar view so as to surround the resistor and embedded in the insulating layer, wherein the shortest distance ΔY (μm) between the plurality of first dummy wirings and the annular conductor is set to satisfy Vα(V) / 100(V / μm)≦ΔY(μm), where Vα(V) is the magnitude of the voltage between the potential of the first dummy wirings that gives the shortest distance ΔY and ground potential.

[0156] [A16] The semiconductor device according to A15, wherein the shortest distance ΔY (μm) satisfies 5 (μm)≦ΔY≦100 (μm).

[0157] The semiconductor substrate of the resistor chip can be removed, and an insulating substrate or a conductive substrate can be used instead of the semiconductor substrate.

[0158] [A17] A resistor chip comprising: a resistor R embedded in an insulating layer 2 and electrically connecting a plurality of resistive layers (linear resistors 3); a first electrode E1 electrically connected to a first end of the resistor R; a second electrode E2 electrically connected to a second end of the resistor R; and a plurality of first dummy wirings 5(n) arranged around the first electrode E1 and capacitively coupled to the plurality of resistive layers (linear resistors 3) in the resistor R.

[0159] [A18] A resistor chip comprising: a resistor R embedded in an insulating layer 2 and electrically connecting a plurality of resistive layers (linear resistors 3); a first electrode E1 electrically connected to a first end of the resistor; a second electrode E2 electrically connected to a second end of the resistor R; and a plurality of first dummy wirings 5(n) arranged around the first electrode E1 and electrically connected to the plurality of resistive layers (linear resistors 3) in the resistor R, respectively.

[0160] Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other embodiments without departing from the scope of the present disclosure. Various features of the described embodiments may be combined. Although individual features may be included in different claims, they may also be combined. The present invention should not be construed as limited by the embodiments, but rather should be construed according to the scope of the claims.

[0161] REFERENCE SIGNS LIST 1...Semiconductor substrate, 1R...Annular conductor, 1R1...Peripheral electrode, 1R2...Peripheral via electrode, 1R3...Peripheral resistor, 2...Insulating layer, 2A...First dielectric layer, 2B...Second dielectric layer, 2A Ｈ ...upper dielectric layer, 2A Ｌ...lower dielectric layer, 3...wire resistor (resistive layer), 4A...first protective film, 4B...second protective film, 5...dummy wiring, 10...resistor chip (semiconductor device), 10a...first inner lead, 10b...second inner lead, 10c...third inner lead, 10d...fourth inner lead, 10e...fifth inner lead, 10f...sixth inner lead, 10g...seventh inner lead, 10h...eighth inner lead, 10i...ninth inner lead, 10j...tenth inner lead , 100...semiconductor package, 101...case, 110...first die pad, 120...second die pad, 20...amplifier chip, 20D...differential amplifier, 21P...first voltage follower, 21N...second voltage follower, 29...second voltage adjustment circuit, 200...battery, AR1...first arrow, AR2...second arrow, AR3...third arrow, AR4...fourth arrow, AR5...fifth arrow, AR6...sixth arrow, BE...buried electrode, BE1...first buried electrode, BE2...second buried electrode, C1...capacitor.

Claims

1. A semiconductor device comprising: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a resistor embedded in the insulating layer and electrically connecting a plurality of resistive layers; a first electrode electrically connected to a first end of the resistor; a second electrode electrically connected to a second end of the resistor; and a plurality of first dummy wirings arranged around the first electrode and capacitively coupled to a plurality of the resistive layers in the resistor, respectively.

2. The semiconductor device of claim 1, wherein the resistors comprise: a first resistor electrically connected to the first electrode; a second resistor electrically connected to the second electrode; and a voltage detection resistor electrically connecting the first resistor and the second resistor and having a resistance value lower than both the first resistor and the second resistor; and further comprising a first output electrode, a second output electrode, and a reference electrode electrically connected to different locations of the voltage detection resistor, respectively.

3. The semiconductor device according to claim 2, further comprising a plurality of second dummy wirings arranged around the second electrode and capacitively coupled to a plurality of the resistive layers in the second resistor, and the plurality of first dummy wirings are capacitively coupled to a plurality of the resistive layers in the first resistor, respectively.

4. The semiconductor device according to claim 3, wherein the voltage detection resistor comprises: a first voltage detection resistor electrically connected to the first resistor and having a resistance value lower than that of the first resistor; and a second voltage detection resistor electrically connected between the second resistor and the first voltage detection resistor and having a resistance value lower than that of the second resistor; a plurality of third dummy wirings capacitively coupled to the plurality of resistance layers in the first voltage detection resistor, respectively; and a plurality of fourth dummy wirings capacitively coupled to the plurality of resistance layers in the second voltage detection resistor, respectively.

5. The semiconductor device according to claim 1, further comprising a plurality of first dummy resistor layers instead of the plurality of first dummy wirings.

6. A semiconductor device comprising: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a resistor embedded in the insulating layer and electrically connecting a plurality of resistance layers; a first electrode electrically connected to a first end of the resistor; a second electrode electrically connected to a second end of the resistor; and a plurality of first dummy wirings arranged around the first electrode and electrically connected to a plurality of the resistance layers in the resistor, respectively.

7. The semiconductor device described in claim 6, wherein one of the plurality of first dummy wirings is electrically connected to a first location of a first resistance layer of the plurality of resistance layers, another of the plurality of first dummy wirings is electrically connected to a second location of the plurality of resistance layers different from the first location, and an end of the one dummy wiring opposite the first location and an end of the other dummy wiring opposite the second location face each other via a gap.

8. The semiconductor device according to claim 6 or 7, wherein the resistor comprises: a first resistor electrically connected to the first electrode; a second resistor electrically connected to the second electrode; and a voltage detection resistor electrically connecting the first resistor and the second resistor and having a resistance value lower than both the first resistor and the second resistor; and further comprising a first output electrode, a second output electrode, and a reference electrode electrically connected to different locations of the voltage detection resistor, respectively.

9. The semiconductor device according to claim 8, further comprising a plurality of second dummy wirings arranged around the second electrode and electrically connected to a plurality of the resistance layers in the second resistor, and the plurality of first dummy wirings are electrically connected to a plurality of the resistance layers in the first resistor, respectively.

10. The semiconductor device according to claim 9, wherein the voltage detection resistor comprises: a first voltage detection resistor electrically connected to the first resistor and having a lower resistance value than the first resistor; and a second voltage detection resistor electrically connected between the second resistor and the first voltage detection resistor and having a lower resistance value than the second resistor; a plurality of third dummy wirings electrically connected to the plurality of resistance layers in the first voltage detection resistor, respectively; and a plurality of fourth dummy wirings electrically connected to the plurality of resistance layers in the second voltage detection resistor, respectively.

11. The semiconductor device according to claim 6, further comprising a plurality of first dummy resistor layers in place of the plurality of first dummy wirings.

12. The semiconductor device according to claim 1 or claim 6, wherein a resistance value between the first electrode and the second electrode is not less than 1 MΩ and not more than 1000 MΩ.

13. The semiconductor device according to claim 12, wherein the material of the resistive layer constituting the resistor includes at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN.

14. The semiconductor device according to claim 1 or 6, wherein the material of the first dummy wiring contains Al, Cu, W, or Ti.

15. The semiconductor device according to claim 1 or claim 6, further comprising an annular conductor disposed in a planar view so as to surround the resistor and embedded in the insulating layer, wherein a shortest distance ΔY (μm) between the first dummy wirings and the annular conductor is set so as to satisfy Vα(V) / 100(V / μm)≦ΔY(μm), where Vα(V) is the magnitude of the voltage between the potential of the first dummy wirings and ground potential that gives the shortest distance ΔY.

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