Adder, chip, and electronic device
WO2025124449A1PCT designated stage expired Publication Date: 2025-06-19HUAWEI TECH CO LTD
Patent Information
- Application Number
- PCT/CN2024/138623
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-12-13
- Filing Date
- 2024-12-11
- Publication Date
- 2025-06-19
Smart Images
Figure CN2024138623_19062025_PF_FP_ABST
Abstract
The present application provides an adder, a chip, and an electronic device. The adder comprises: a redundant coding unit, a decoder unit, and calculation units. During calculation of a first target number, i.e., a signed number, and a second target number, i.e., an unsigned number, the first target number, i.e., the signed number, is represented by a redundant number in the form of a differential pair, so as to implement an efficient redundant number coding and decoding process in the redundant coding unit and the decoder unit. By means of the circuit design of the calculation units, high-bit-width carry-free data processing can be realized, thereby increasing the data calculation speed.
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Citation Information
Patent Citations
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