Delta sigma a / d converter and battery monitoring device

Abstract

This delta-sigma A / D converter uses an operational amplifier (11) having a differential configuration. A first integrator (1) is provided with: a pair of feedback capacitors (Cf1) that have a differential configuration and are feedback-connected between differential input terminals and differential output terminals of the operational amplifier; and a switched capacitor comprising a chopping switch (14) capable of reversing the polarity between the differential input terminals of the operational amplifier and the pair of feedback capacitors. Switches (φ3, Sim, Sip; Si; Sfmp, Sfpm) reset the potential of the differential input terminals of the operational amplifier at a timing when the feedback capacitors (Cf1) and the differential input terminals of the operational amplifier are disconnected by the chopping switch in the first integrator.

Description

Delta-sigma A / D converter and battery monitoring device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Application No. 2023-209332, filed on December 12, 2023, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a delta-sigma A / D converter and a battery monitoring device using the A / D converter.

[0003] For example, Patent Document 1 proposes a technique for reducing A / D conversion errors caused by chopping by making chopping random.

[0004] Patent No. 3546017

[0005] The technology described in Patent Document 1 modulates the A / D conversion error spectrum by chopping, but does not eliminate the error. Furthermore, the reduced chopping frequency prevents flicker noise from reaching the high frequency range, instead affecting the low frequency range as random noise. Furthermore, a separate circuit for generating pseudorandom numbers is required, which increases the area and current consumption.

[0006] The present disclosure has been made in consideration of the above circumstances, and its purpose is to provide a delta-sigma A / D converter that can reduce A / D conversion errors caused by chopping, and a battery monitoring device that uses the A / D converter.

[0007] According to one aspect of the present disclosure, a delta-sigma A / D converter using a differential operational amplifier includes a pair of feedback capacitors that are feedback-connected between the differential input terminals and differential output terminals of the differential operational amplifier, and a first integrator using switched capacitors that includes a chopping switch that can switch the polarity between the differential input terminals of the operational amplifier and the pair of feedback capacitors. The first integrator also includes a switch that resets the potential of the differential input terminals of the operational amplifier when the feedback capacitors are disconnected from the differential input terminals of the operational amplifier by the chopping switch.

[0008] According to the delta-sigma A / D converter of one aspect of the present disclosure, the switch resets the potential of the differential input terminals of the operational amplifier when the feedback capacitor and the differential input terminals of the operational amplifier are disconnected by the chopping switch, thereby eliminating A / D conversion errors caused by chopping at the differential input terminals of the operational amplifier and reducing A / D conversion errors caused by chopping.

[0009] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. 1A is a diagram showing a part of the configuration of the delta-sigma A / D converter in the first embodiment, FIG. 1B is a diagram showing the electrical configuration around the operational amplifier in the first embodiment, FIG. 2 is a diagram (part 1) showing the configuration of the delta-sigma A / D converter in the first embodiment, FIG. 3 is a diagram (part 2) showing the configuration of the delta-sigma A / D converter in the first embodiment, FIG. 4 is an explanatory diagram of the first embodiment and a diagram showing waveforms of each clock signal that controls the delta-sigma A / D converter, FIG. 5 is a diagram explaining the operation of a first integrator in the first embodiment, FIG. 6 is a diagram (part 1) explaining the operation of a second integrator in the first embodiment, FIG. 7 is a diagram (part 2) explaining the operation of the second integrator in the first embodiment, FIG. 8 is a diagram (part 3) explaining the operation of the second integrator in the first embodiment, FIG. 9 is a diagram (part 4) explaining the operation of the second integrator in the first embodiment, and FIG. 10 is a diagram showing a part of the configuration of a delta-sigma A / D converter in a comparative example. 11 is a diagram illustrating the operation of a first integrator in a comparative example, FIG. 12 is a diagram illustrating degradation of integral nonlinearity error (INL) characteristics in the delta-sigma A / D converter of the comparative example, FIG. 13 is an electrical configuration diagram of the first integrator in the first embodiment, FIG. 14 is a diagram illustrating changes in the charge accumulation state of a capacitor constituting the first integrator in the first embodiment, FIG. 15 is an explanatory diagram of a second embodiment and is a diagram showing waveforms of clock signals controlling the delta-sigma A / D converter, FIG. 16 is an explanatory diagram of a third embodiment and is an electrical configuration block diagram of a battery monitoring device, FIG. 17 is an explanatory diagram of the third embodiment and is an explanatory diagram illustrating the relationship between a signal band and a noise frequency band, FIG. 18 is an explanatory diagram (part 1) of an example of a reset method in the fourth embodiment, FIG. 19 is an explanatory diagram (part 2) of an example of a reset method in the fourth embodiment, and FIG. 20 is an explanatory diagram (part 3) of an example of a reset method in the fourth embodiment.

[0010] Hereinafter, several embodiments of the data generating device and the battery monitoring device will be described with reference to the drawings. In the embodiments described later, the same or similar reference numerals as those in the embodiments described earlier will be used, and the description thereof will be omitted.

[0011] 1A shows a part of a CIFF type second-order delta-sigma A / D converter 5 according to this embodiment. In addition, in FIG. 1B, the switches φ3 around the input and output of the operational amplifier 11 shown in FIG. 1A are distinguishably labeled as switches Sip, Sim, and So.

[0012] Fig. 1A shows a partial block diagram of the delta-sigma A / D converter 5 shown in Fig. 2. The delta-sigma A / D converter 5 shown in Fig. 2 has a first integrator 1 and a second integrator 2 connected in series. An adder 3b shown in Fig. 2 adds the output of the first integrator 1, which is doubled by a gain 3a, to the output of the second integrator 2, and outputs the result to a quantizer 4. The output of the quantizer 4 is fed back via a feedback D / A converter 13 so as to be subtracted from the input signal.

[0013] The configuration shown in Fig. 2 includes a 2x gain 3a, an adder 3b, a delay device 3c, and a -2x gain 3d, but the configuration in Fig. 2 is equivalent to a configuration in which a pseudo-addition circuit 3 is arranged on the input side of the second integrator 2 as shown in Fig. 3. The pseudo-addition circuit 3 adds the output of the first integrator 1, the output of the first integrator 1 multiplied by two with the gain 3a, and the output multiplied by two with the gain 3d via the delay device 3c.

[0014] The delta-sigma A / D converter 5, a portion of which is shown in FIG. 1A, is implemented as a differential circuit based on the block configuration shown in FIG. 3. The delta-sigma A / D converter 5 has a switched-capacitor configuration in which chopping is performed on the input side of the first integrator 1 to charge and discharge each capacitor (reference numerals omitted). The delta-sigma A / D converter 5 operates with 11 types of clock signals shown in FIG. 4. Note that, for ease of understanding, in the following explanation, the reference numerals for the switches φ1, φ1c, φ1d, φ2, φ2a, φ2b, and φ3 shown in FIG. 1 may also be used directly to describe the clock phases (clock signals). φ1: Master clock signal φ1+: Output if the output of the quantizer 4 is L φ1-: Output if the output of the quantizer 4 is H φ1c: Odd-numbered clock of φ1 φ1d: Even-numbered clock of φ1 φ2: Antiphase clock signal of φ1 φ2a, φ2c: Odd-numbered clock of φ2 φ2b, φ2d: Even-numbered clock of φ2 φ3: Reset signal (synchronized with master clock) Note that the odd and even numbers are relative when the left end of φ1 of the master clock shown in Figure 4 is set to "1", for example. Also, to make the explanation easier to understand, please note that the switches described below that are turned on by each of the above clock signals may be described by adding a symbol indicating the type of clock.

[0015] As shown in FIG. 1 , the first integrator 1 includes an operational amplifier 11 with a fully differential configuration. A series circuit including a switch φ1, a capacitor Cs1 serving as a sampling capacitance element, and a chopping switch 12 is connected between the nodes of the positive input voltage VINP and the negative input voltage VINM and the differential input terminal of the operational amplifier 11. The chopping switch 12 is composed of two switches φ2a and two switches φ2b. The two switches φ2a provide a straight connection between the node of the positive input voltage VINP and the negative input terminal of the operational amplifier 11, and between the node of the negative input voltage VINM and the positive input terminal of the operational amplifier 11. The two switches φ2b are connected so as to cross between the nodes of the input voltages VINP and VINM and the differential input terminal of the operational amplifier 11.

[0016] One end of a capacitor Cd1 and a switch φ1, which constitute the D / A converter 13, are connected to a common connection point between the capacitor Cs1 and the chopping switch 12. One end of each of the switches φ1-, φ1+, and φ2, which constitute the D / A converter 13, is commonly connected to the other end of the capacitor Cd1, and the other ends of the switches φ1-, φ1+, and φ2 and the switch φ1 are connected to reference voltages Vr-, Vr+, and a reference potential VCMO, respectively. The reference potential VCMO is an output common-mode potential, and the magnitude relationship between these voltages is set to (Vr-<VCMO<Vr+).

[0017] The chopping switch 12 switches the polarity between the nodes of the input voltages VINP and VINM and the differential input terminals of the operational amplifier 11. The chopping switch 14 switches the polarity between the differential input terminals of the input-side operational amplifier 11 and a pair of feedback capacitors Cf1. An input parasitic capacitance Ci exists between the common connection point between the switches φ2a constituting the chopping switches 12 and 14 and the differential input terminals of the operational amplifier 11 and the node of the reference potential VCMO. To suppress the influence of A / D conversion errors due to this parasitic capacitance Ci, as shown in FIG. 1B , switches Sim and Sip (φ3) are connected between the negative input terminal of the operational amplifier 11 and the node of the input common potential VCMI, and between the positive input terminal and the node of the input common potential VCMI, respectively.

[0018] As shown in FIG. 1A , a series circuit of a chopping switch 14, a feedback capacitor Cf1, and a chopping switch 15 is connected between the input and output sides of the operational amplifier 11. Like the chopping switch 12, these chopping switches 14 and 15 are each composed of two switches φ2a and two switches φ2b. The switch φ2a is connected straight between the negative input terminal and the positive output terminal, and between the positive input terminal and the negative output terminal, while the switch φ2b is connected crosswise so that the polarity of the input and output sides is reversed. The chopping switch 15 corresponds to an output chopping switch. Either the positive or negative output signal of the first integrator 1 corresponds to the first output signal, and the other corresponds to the second output signal. A switch So (φ3) is connected between the differential output terminals of the operational amplifier 11 to suppress the influence of parasitic capacitance generated around the operational amplifier 11.

[0019] A second integrator 2 having a pseudo-adding circuit 3 disposed on the input side is configured downstream of the first integrator 1. A switch φ2, a parallel circuit of capacitors Cs2 and Cas, and a series circuit of a switch φ1, which configure one polarity side of the pseudo-adding circuit 3, are connected between an output line 16 of the first integrator 1 and the negative input terminal of a fully differential operational amplifier 18 that configures the second integrator 2. The configuration between the output line 17 of the first integrator 1 and the positive input terminal of the operational amplifier 18 is similar.

[0020] A series circuit of switch φ2c and capacitor Caa, and a series circuit of switch φ2d and capacitor Cab are connected between the output line 17 and the common connection point of capacitors Cs2, Cas, and switch φ1. Switches φ1c and φ1d are connected between the common connection point of each series circuit and a reference voltage, respectively. The configuration on the side connected to output line 16 is similar. A switch φ2 is connected between the common connection point of capacitors Cs2, Cas, and switch φ1 and the reference voltage. The capacitances of capacitors Cas, Caa, and Cab are set to be equal. Capacitors Cas, Caa, and Cab correspond to capacitance elements for addition, odd-number subtraction, and even-number operation, respectively.

[0021] A feedback capacitor Cf2 is connected between the differential input terminals and differential output terminals of the operational amplifier 18 that constitutes the second integrator 2, and the differential output terminals are connected to the input terminals of the quantizer 4. The pseudo-adder circuit 3 performs addition as follows, utilizing the configuration of the second integrator 2. The delta-sigma A / D converter 5 is configured as described above.

[0022] Next, the operation of this embodiment will be described. First, the operation of the first integrator 1 will be described. In this embodiment, the operation will be described when the input side of the operational amplifier 11 is chopped each time by the chopping switches 12 and 14. In the following, to make the operation easier to understand, the illustration of each switch will be omitted as appropriate, and the switches that are turned on in accordance with each clock are shown by solid lines. In this embodiment, the clock is generated to cyclically turn on switches φ1 → φ2a → φ1 → φ2b → ..., thereby repeatedly executing four phases.

[0023] <φ1: Sampling Phase> In the sampling phase shown on the left side of Fig. 5, a sampling process is performed in which capacitor Cs1 is charged by input voltages VINP and VINM. Simultaneously with the on-timing of switch φ1, switches φ1- and φ1+ are selectively turned on and off depending on the output of quantizer 4, thereby charging and discharging capacitor Cd1 of D / A converter 13. At the same time, feedback capacitor Cf1 is disconnected from the input terminal of operational amplifier 11 by chopping switch 14. Furthermore, by turning on switches Sim and Sip, the differential input terminals of operational amplifier 11 are short-circuited and connected to the input common node, and the potentials of both input terminals are reset to input common potential VCMI.

[0024] <φ2a: Integration Phase a> Next, in integration phase a shown in the upper right of Figure 5, feedback capacitor Cf1 and the differential input terminals of operational amplifier 11 are directly connected by chopping switch 14, and the charges of capacitors Cs1 and Cd1 are integrated in feedback capacitor Cf1.

[0025] <φ1: Sampling Phase> Next, the process returns to the sampling phase shown on the left side of FIG. 5 . At this time, as in the previous example, capacitor Cs1 is charged by input voltages VINP and VINM, and sampling is performed. Simultaneously with the on-timing of switch φ1, switches φ1- and φ1+ are selectively turned on and off depending on the output of quantizer 4, and capacitor Cd1 of D / A converter 13 is charged and discharged. Furthermore, feedback capacitor Cf1 is disconnected from the input terminal of operational amplifier 11 by chopping switch 14. Furthermore, by turning on switches Sim and Sip, the differential input terminals of operational amplifier 11 are short-circuited, and the potentials of both input terminals are stabilized at input common potential VCMI, resetting both potentials of the differential input terminals.

[0026] 1B are configured to set the differential input terminals of the operational amplifier 11 to a predetermined input common potential VCMI, thereby stably determining the potentials of the positive input terminal and the negative input terminal during reset. Also, the switch So is configured to connect the differential output terminals of the operational amplifier 11 to set the differential output terminals to the same potential, thereby resetting the differential output terminals to stable potentials.

[0027] <φ2b: Integration Phase b> Next, the phase transitions to integration phase b shown in the lower right of Fig. 5. At this time, the polarity of the input / output terminals of the operational amplifier 11 is switched to cross connection by the chopping switches 12, 14, and 15, and the charges of the capacitors Cs1 and Cd1 are integrated in the feedback capacitor Cf1.

[0028] In this way, the four phases are repeated periodically. After each integration phase a or b, the first integrator 1 resets the voltage at the input terminal of the operational amplifier 11 to the input common potential VCMI during the sampling phase φ1. This allows the first integrator 1 to integrate without accumulating errors as much as possible.

[0029] Next, we will explain the operation of the pseudo-addition circuit 3 and the second integrator 2. In the operation of the second integrator 2 shown in Figures 6 to 9, four phases are repeatedly executed by cyclically generating clocks such as φ1c → φ2c → φ1d → φ2d → φ1c → .... Furthermore, explanations involving positive and negative polarities will be given for the upper side in the figure, which is one side of the differential configuration.

[0030] <φ1c: First Phase> In the first phase shown in FIG. 6, the charges of the capacitors Caa, Cas, and Cs2 are added to the feedback capacitor Cf2.

[0031] <φ2c: Second Phase> In the second phase shown in FIG. 7, the capacitors Cas and Cs2 are charged with the positive output of the first integrator 1 and sampled, and the capacitor Caa is charged with the negative output of the first integrator 1 and sampled.

[0032] <φ1d: Third Phase> In the third phase shown in FIG. 8, the charges of the capacitors Cab, Cas, and Cs2 are added to the feedback capacitor Cf2.

[0033] <φ2d: Fourth Phase> In the fourth phase shown in FIG. 9, the capacitors Cas and Cs2 are charged with the positive output of the first integrator 1 and sampled, and the capacitor Cab is charged with the negative output of the first integrator 1 and sampled.

[0034] As a result of repeating the above operation, the output of each addition result in the first and third phases in time series is doubled from the input at that time, and at the timing of the next addition, the doubled value added previously is subtracted. In this way, the input voltages are cumulatively added in sequence.

[0035] <Comparative Example> The inventors originally developed a delta-sigma A / D converter 5 that performed A / D conversion processing without considering parasitic capacitance Ci, but discovered that an A / D conversion error occurred. After investigating the cause, the inventors found that parasitic capacitance Ci was occurring at the differential input terminals of the operational amplifier 11, and that charge was accumulating in this parasitic capacitance Ci. They found that when chopping causes the positive and negative terminals of the input and output terminals of the operational amplifier 11 to be reverse-connected, this error charge affects the integration value of the first integrator 1 in the initial stage.

[0036] 10 shows, as a comparative example, the configuration of a first integrator 101 that replaces the first integrator 1. This first integrator 101 shows a configuration example in which the influence of the parasitic capacitance Ci generated at the input of the operational amplifier 11 is not taken into consideration. Compared to the first integrator 1 of this embodiment, the first integrator 101 does not have a switch φ3 between the differential input terminals and the differential output terminals of the operational amplifier 11.

[0037] Then, as shown in the left diagram of FIG. 11, the operation of the first integrator 101 is as follows: in the parasitic capacitance Ci of the input of the operational amplifier 11, a charge C i V ima , C i V ipa Therefore, the influence of the error is accumulated in the integration phase b.

[0038] This operation can be expressed mathematically as follows: Consider the output error of the first integrator 101 based on the error charge when the phase transitions from φ2a to φ1 to φ2b. For simplicity, when considering this mathematically, the effects of the sampling capacitor Cs1 and the capacitor Cd1 of the D / A converter 13 are omitted, and the initial charge of the feedback capacitor Cf1 is considered to be zero.

[0039] 10, when the switch φ3 is not provided and resetting is not performed, and the phases are φ2a → φ1 → φ2b, the values ​​of the positive input voltage Vintp and negative input voltage Vintm of the operational amplifier 11 can be derived as shown in the following equation (1). These values ​​are determined based on changes in the charge accumulation state of the parasitic capacitance Ci, the capacitor Cs, and the feedback capacitor Cf1.

[0040] When Vintp-Vintm is derived from this equation (1), it can be derived as in equation (2).

[0041] In this way, the voltage "-Vipa+Vima" at the time of the phase φ2a remains, and the integration of the error charge Ci / Cf1·(-Vipa+Vima) based on this voltage is repeated many times, resulting in an accumulated integrated error. When an error occurs, as shown in Figure 12, the input level dependency of the delta-sigma A / D converter 5 becomes large, and the integral nonlinearity error (INL) becomes large.

[0042] 13 also shows the first integrator 1 when taking into consideration the parasitic capacitances Ci and Co at the input and output of the operational amplifier 11. According to the delta-sigma A / D converter 5 of this embodiment, the differential input terminals and differential output terminals of the operational amplifier 11 can be reset during the sampling phase using a switch φ3 newly provided at the input and output of the operational amplifier 11. Changes in the charge accumulation states of the parasitic capacitance Ci, capacitor Cs, and feedback capacitor Cf1 when the phase changes from φ2a to φ1 to φ2b are shown in FIG.

[0043] This operation can be expressed mathematically as follows: Consider the output error of the first integrator 1 based on the error charge when the phase shifts from φ2a to φ1 to φ2b.

[0044] When the reset process is performed as shown in FIG. 14, the values ​​of the positive input voltage Vintp and the negative input voltage Vintm of the operational amplifier 11 based on the changes in the charge storage state of the parasitic capacitance Ci, the capacitor Cs, and the feedback capacitor Cf1 when going through the phases φ2a → φ1 → φ2b can be derived as shown in the following equation (3).

[0045] When Vintp-Vintm is derived from equation (3), equation (4) can be derived. In equation (4), the voltage Vcmi element is canceled out, and the voltage "-Vipa+Vima" during the φ2a phase described above does not remain. This reduces A / D conversion errors due to chopping.

[0046] Summary of the Present Embodiment According to the present embodiment, the switch φ3 resets the potential of the input terminal of the operational amplifier 11 during the sampling phase at the timing when the feedback capacitor Cf1 and the input terminal of the operational amplifier 11 are disconnected by the chopping switch 14. In the present embodiment, resetting is achieved by shorting the positive input terminal and the negative input terminal of the operational amplifier 11 and stabilizing the voltage to the input common potential VCMI. Therefore, A / D conversion errors caused by chopping that occur at each terminal of the differential input terminal of the operational amplifier 11 can be cleared, and A / D conversion errors caused by chopping can be reduced.

[0047] Furthermore, according to this embodiment, the switches Sim and Sip (φ3) are configured to set the differential input terminals of the operational amplifier 11 to a predetermined input common potential VCMI, so that the potentials of the positive and negative input terminals can be stably determined during reset. Furthermore, the switch So is configured to connect the differential output terminals of the operational amplifier 11 to set the differential output terminals to the same potential, so that the differential output terminals can be reset to stable potentials without separately driving the reference potential VCMO, and a configuration can be achieved without the need for a separate drive circuit.

[0048] Second Embodiment A second embodiment will be described with reference to FIG. 15. In the second embodiment, an operation will be described in which the input side of the operational amplifier 11 is chopped by the chopping switches 12 and 14 every (three clocks of φ1). As shown in FIG. 15, the clocks are generated in the order of (φ2a for three clocks of φ1) → φ3 → (φ2b for three clocks of φ1) → φ3 → .... In such a case, too, the potential of the input terminal of the operational amplifier 11 can be reset at the timing of the clock signal φ3, and the same effects as those of the above-described embodiment can be obtained.

[0049] Third Embodiment A third embodiment will be described with reference to Fig. 16 and Fig. 17. Fig. 16 shows a configuration in which the delta-sigma A / D converter 5 of the first embodiment is applied to a battery monitoring IC 21 having a battery impedance measurement function using a lock-in amplifier.

[0050] The battery monitoring device 20 is composed of a battery monitoring IC 21 and an external RC filter 26. The battery monitoring IC 21 is configured using an integrated circuit and measures the impedance of each of n (e.g., 24) unit cells Ce1 to Cen that make up the assembled battery 22. A series circuit consisting of a limiting resistor 24, an N-channel MOSFET 25, and a shunt resistor Rsh is connected in parallel to the assembled battery 22. The limiting resistor 24 limits the magnitude of the intermittent current that flows by controlling the on / off of the MOSFET 25.

[0051] Each of the unit cells Ce1 to Cen, which are secondary batteries, is connected to an RC filter 26 configured as a low-pass filter of a resistor Ra and a capacitor Ca. Both ends of the capacitor Ca that configures the RC filter 26 are connected to the input terminals of the delta-sigma A / D converter 5 of the battery monitoring IC 21. Furthermore, both ends of the shunt resistor Rsh are connected to the input terminals of another delta-sigma A / D converter 5 via an RC filter 26 configured as a resistor Rz and a capacitor Cz.

[0052] The battery monitoring IC 21 includes a delta-sigma A / D converter 5, a decimation filter 27, multipliers 28I and 28Q, and LPFs 29I and 29Q, one for each unit cell Ce1, Ce2, ... Cen, plus one for current measurement. The battery monitoring IC 21 also includes a SIN / COS generator 31, a PWM / PDM modulator 33, an impedance calculator 30, and a register 32. The impedance calculator 30 is composed of a digital control circuit and a counter.

[0053] An interface 34 for communicating with the outside is connected to the register 32. An external host device or the like writes data to the register 32 via the interface 34, thereby setting the frequency of the SIN / COS generator 31 and the modulation method in the PWM / PDM modulator 33. When the register 32 receives a measurement start command via the interface 34, the SIN / COS generator 31 starts operating and the PWM / PDM modulator 33 also starts operating.

[0054] The PWM / PDM modulator 33 outputs a PWM (Pulse Width Modulation) signal or a PDM (Pulse Density Modulation) signal based on a modulation method set in the register 32 from an external higher-level control device or the like via the interface 34. The PWM / PDM modulator 33 is connected to the gate of the FET 25, and the PWM signal or PDM signal is applied to the gate. When the FET 25 is turned on, the delta-sigma A / D converter 5 detects a terminal voltage corresponding to the excitation current flowing from the battery pack 22 through the limiting resistor 24 to the shunt resistor Rsh.

[0055] The delta-sigma A / D converter 5 measures and A / D converts the terminal voltages of the unit cells Ce1, Ce2...Cen and the terminal voltage of the shunt resistor Rsh. The output data of the delta-sigma A / D converter 5 is input to a decimation filter 27. The decimation filter 27 uses a CIC (Cascaded Integrator-Comb) filter, which reduces the sampling frequency and converts the data into a multi-bit digital value.

[0056] The output of the decimation filter 27 is branched into two and input to multipliers 28I and 28Q. The multipliers 28I and 28Q input the sine and cosine signals generated by a sine / cosine generation unit 31 and perform orthogonal transformation. The outputs of the multipliers 28I and 28Q are input to LPFs 29I and 29Q, respectively. The LPFs 29I and 29Q cut off high frequencies to obtain the desired DC data, and output the real and imaginary parts, respectively, to an impedance calculation unit 30.

[0057] The impedance calculation unit 30 receives each input and outputs the calculated impedances of the unit cells Ce1, Ce2, ... Cen to a register 32. The impedance value data stored in the register 32 is transmitted to an external higher-level control device or the like.

[0058] Generally, when measuring the impedance of the battery pack 22, measurements must be made in a low frequency band of about 0.1 Hz to 10 kHz, and the delta-sigma A / D converter 5 is also required to have low noise in the same frequency band. If the delta-sigma A / D converter 5 includes an operational amplifier 11 configured with, for example, a MOSFET, the level of low-frequency noise due to flicker noise is high. If such an operational amplifier 11 is used as is in the delta-sigma A / D converter 5, the low-frequency noise will be high.

[0059] The upper diagram in Figure 17 shows an example of a frequency noise spectrum distribution as a comparative example. If the signal band is approximately 0.1 to 10 kHz and the chopping frequency is set to approximately 10 kHz, flicker noise will be mapped to the signal band, reducing the noise reduction effect. The electric charge stored in the operational amplifier 11 and the parasitic capacitances Ci and Co of the wiring becomes noise, causing errors in the conversion characteristics of the delta-sigma A / D converter 5. Deterioration of the integral nonlinearity error (INL) makes it impossible to measure DC voltage correctly, which is particularly fatal in battery monitoring applications.

[0060] To solve this problem, for example, it is advisable to set the sampling frequency of the delta-sigma A / D converter 5 to a relatively high frequency of approximately 2 MHz. Setting the sampling frequency in this manner allows the chopping frequency to be set to approximately half that frequency, 1 MHz. In the above-described embodiment and this embodiment, the chopping switches 12, 14, and 15 of the delta-sigma A / D converter 5 periodically switch between the positive and negative input terminals and the positive and negative output terminals of the operational amplifier 11 by chopping and switching. As a result, flicker noise can be configured to shift toward higher frequencies in accordance with the switched chopping frequency. This reduces flicker noise on the low-frequency side. This makes the delta-sigma A / D converter 5 suitable for the battery monitoring device 20 that measures the impedance of the unit cells Ce1 to Cen.

[0061] (Fourth Embodiment) A fourth embodiment will be described with reference to Figs. 18 to 20. In the fourth embodiment, various modified examples of the reset method will be described. Figs. 18 to 20 show how the switches Si, So, Sim, Sip, Sop, Som, Sfmp, and Sfpm configured around the first integrator 1 are connected. As shown in Figs. 18 to 20, the switches Si, So, Sim, Sip, Sop, Som, Sfmp, and Sfpm may be connected to reset the differential input terminals.

[0062] 18 , the switch Si is configured to set the differential input terminals of the operational amplifier 11 at the same potential at the timing of resetting, and the switch So is configured to set the differential output terminals at the same potential. In this case, for example, the differential input terminals of the operational amplifier 11 may be connected by a single switch Si to set the differential input terminals at the same potential, and the differential output terminals of the operational amplifier 11 may be connected by a single switch So to set the differential output terminals at the same potential. This configuration also achieves the same effects as the above-described embodiment.

[0063] Also, as shown in FIG. 19, switches Sim and Sip may be provided so that, at the timing of resetting, the positive input terminal and the negative input terminal of the operational amplifier 11 are each connected to an input common potential VCMI, which is a predetermined potential, so that the differential input terminals are at the same potential.

[0064] 19 , switches Som and Sop may be provided to connect the differential output terminals of the operational amplifier 11 together, thereby making the differential output terminals at the same potential. Alternatively, switches Som and Sop may be provided to connect the positive output terminal and the negative output terminal of the operational amplifier 11 to a reference potential VCMO, which is a predetermined potential, thereby making the differential output terminals at the same potential. This configuration also achieves the same effects as the above-described embodiment.

[0065] 20, the switches Sfmp and Sfpm may be configured to connect the positive input terminal and negative output terminal of the operational amplifier 11 at the time of resetting, and also to connect the negative input terminal and positive output terminal of the operational amplifier 11. By configuring the switches Sfmp and Sfpm as shown in Fig. 20, the output of the operational amplifier 11 is fed back at the timing of resetting, so that the potential of the differential input terminals can be fixed to the potential of the output terminal of the operational amplifier 11, and as a result, the differential input terminals of the operational amplifier 11 can each be reset.

[0066] (Other Embodiments) The present invention is not limited to the above-described embodiments, and the following modifications or extensions are possible, for example. The delta-sigma A / D converter 5 may be applied to devices other than the battery monitoring device 20 equipped with a battery impedance measurement function. While the embodiment in which the second integrator 2 is connected downstream of the first integrator 1 has been described, the present invention may also be applied to a configuration in which a differential amplifier is connected instead of the second integrator 2, or to a configuration in which the output of the first integrator 1 is input directly to the quantizer 4. Therefore, the pseudo-adder circuit 3 and the second integrator 2 may be provided as needed.

[0067] The present disclosure includes the following in addition to the content described in the claims: [1] A delta-sigma A / D converter using a differential operational amplifier (11), comprising: a first integrator (1) using switched capacitors, the first integrator having a pair of feedback capacitors (Cf1) that are feedback-connected between the differential input terminals and the differential output terminals of the operational amplifier, and a chopping switch (14) that can switch polarity between the differential input terminals of the operational amplifier and the pair of feedback capacitors, the delta-sigma A / D converter further comprising switches (Sim, Sip; Si; Sfmp, Sfpm) that reset the potential of the differential input terminals of the operational amplifier when the feedback capacitor (Cf1) is disconnected from the differential input terminals of the operational amplifier by the chopping switch in the first integrator.

[0068] [2] The delta-sigma A / D converter according to [1], which has a differential configuration and includes a second integrator (2) connected to the rear stage of the first integrator.

[0069] [3] The delta-sigma A / D converter according to [1] or [2], wherein the switches (Sim, Sip) are configured to set the differential input terminals of the operational amplifier to a predetermined potential (VCMI) when the switch is reset, and the delta-sigma A / D converter further comprises a switch (So) that sets the differential output terminals to the same potential when the switch is reset.

[0070] [4] The delta-sigma A / D converter according to [1] or [2], wherein the switch (Si) is configured to equalize the potential of the differential input terminals of the operational amplifier when the switch (Si) is reset, and further comprising a switch (So) that equalizes the potential between the differential output terminals when the switch (Si) is reset.

[0071] [5] The delta-sigma A / D converter according to [1] or [2], wherein the switch (Si) connects the differential input terminals of the operational amplifier when the switch (Si) is reset, thereby making the differential input terminals have the same potential.

[0072] [6] The delta-sigma A / D converter according to any one of [1] to [5], wherein the differential input terminals are composed of a positive input terminal and a negative input terminal, and the switches (Sim, Sip) connect the positive input terminal and the negative input terminal of the operational amplifier to predetermined potentials at the time of the resetting, thereby making the differential input terminals the same potential.

[0073] [7] The delta-sigma A / D converter according to any one of [3] to [6], wherein the switch (So) connects the differential output terminals together when resetting, thereby making the differential output terminals have the same potential.

[0074] [8] The delta-sigma A / D converter according to any one of [3] to [6], wherein the switches (Som, Sop) connect each of the differential output terminals of the operational amplifier to a predetermined potential when resetting, thereby making the differential output terminals the same potential.

[0075] [9] The delta-sigma A / D converter according to any one of [1] to [8], wherein the differential input terminal is composed of a positive input terminal and a negative input terminal, and the switch (Sfmp, Sfpm) connects the positive input terminal and the negative output terminal of the operational amplifier when resetting, and also connects the negative input terminal and the positive output terminal of the operational amplifier.

[0076]

[10] A battery monitoring device comprising the delta-sigma A / D converter (5) according to any one of [1] to [9].

[0077] In the drawing, 1 denotes a first integrator, 2 denotes a second integrator, 3 denotes a pseudo-adder circuit, 4 denotes a quantizer, 5 denotes a delta-sigma A / D converter, and Cf1 denotes a feedback capacitor.

[0078] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

Claims

1. A delta-sigma A / D converter using a differential operational amplifier (11), comprising: a first integrator (1) having a switched capacitor with a pair of feedback capacitors (Cf1) that are differentially configured and that are feedback-connected between the differential input terminals and differential output terminals of the operational amplifier, and a chopping switch (14) that can switch the polarity between the differential input terminals of the operational amplifier and the pair of feedback capacitors; and a delta-sigma A / D converter having switches (φ3, Sim, Sip; Si; Sfmp, Sfpm) that reset the potential of the differential input terminals of the operational amplifier when the feedback capacitor (Cf1) and the differential input terminals of the operational amplifier are disconnected by the chopping switch in the first integrator.

2. A delta-sigma A / D converter according to claim 1, further comprising a second integrator (2) of a differential configuration connected to the rear stage of said first integrator.

3. A delta-sigma A / D converter as claimed in claim 1 or 2, wherein the switches (Sim, Sip) are configured to set the differential input terminals of the operational amplifier to a predetermined potential (VCMI) when the operational amplifier is reset, and further comprising a switch (So) that sets the differential output terminals to the same potential when the operational amplifier is reset.

4. A delta-sigma A / D converter as claimed in claim 1 or 2, wherein the switch (Si) is configured to set the differential input terminals of the operational amplifier to the same potential when the operational amplifier is reset, and further comprising a switch (So) that sets the differential output terminals to the same potential when the operational amplifier is reset.

5. A delta-sigma A / D converter according to claim 1 or 2, wherein the switch (Si) connects the differential input terminals of the operational amplifier when the switch (Si) is reset, thereby bringing the differential input terminals to the same potential.

6. A delta-sigma A / D converter as claimed in claim 1 or 2, wherein the differential input terminals are composed of a positive input terminal and a negative input terminal, and the switches (Sim, Sip) connect the positive input terminal and the negative input terminal of the operational amplifier to a predetermined potential when resetting, thereby making the differential input terminals the same potential.

7. The delta-sigma A / D converter according to claim 3, wherein said switch (So) connects said differential output terminals together when said resetting is performed, thereby making said differential output terminals have the same potential.

8. The delta-sigma A / D converter according to claim 3, wherein said switches (Som, Sop) connect each of the differential output terminals of said operational amplifier to a predetermined potential at the time of said resetting, thereby making said differential output terminals the same potential.

9. The delta-sigma A / D converter according to claim 1, wherein the differential input terminal is composed of a positive input terminal and a negative input terminal, and the switch (Sfmp, Sfpm) connects the positive input terminal and negative output terminal of the operational amplifier when resetting, and also connects the negative input terminal and positive output terminal of the operational amplifier.

10. A battery monitoring device comprising a delta-sigma A / D converter (5) according to any one of claims 1 to 9.

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