Semiconductor structure and manufacturing method therefor

Abstract

A semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a first stack structure; the first stack structure has a first surface used for bonding; the first stack structure comprises a transistor array and a charge storage array that are stacked in a direction perpendicular to the first surface, and the transistor array is closer to the first surface than the charge storage array, wherein the charge storage array is provided with a first connecting end and a second connecting end, the first connecting end is used for connecting the charge storage array and the transistor array, and the second connecting end surrounds the periphery of the transistor array and the periphery of the charge storage array and extends to be close to the first surface. Embodiments of the present disclosure can improve the integration density and reliability of a storage circuit.

Description

Semiconductor structure and method for manufacturing the same

[0001] This disclosure claims priority to the Chinese patent application filed with the China Patent Office on December 19, 2023, with application number 202311760110.3 and invention name “Semiconductor Structure and Manufacturing Method Thereof,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0003] As the demand for storage density increases, VCT (vertical channel transistor) technology exists in related technologies. VCT technology requires connecting a storage capacitor to the first end of multiple transistors arranged perpendicular to the substrate surface and connecting a bit line to the second end of the transistor. This results in the control of transistors and capacitors requiring at least one long conductive line to be achieved, which has low control efficiency. When the number of transistors and capacitors is large, the conductive lines are dense. When there is a trend of miniaturization of memory, such dense conductive lines bring problems to processing and component layout.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0005] Summary of the Invention

[0006] The present disclosure aims to provide a semiconductor structure and a manufacturing method thereof, which are used to solve the control circuit layout problem of vertical channel transistors.

[0007] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a first stacking structure, the first stacking structure having a first surface for bonding; the first stacking structure comprising a transistor array and a charge storage array, the transistor array and the charge storage array being stacked in a direction perpendicular to the first surface, the transistor array being closer to the first surface than the charge storage array; wherein the charge storage array has a first connection end and a second connection end, the first connection end being used to connect the charge storage array to the transistor array, the second connection end surrounding the periphery of the transistor array and the charge storage array and extending close to the first surface.

[0008] In an exemplary embodiment of the present disclosure, the first stacked structure further includes a first circuit wiring layer, which connects the second connection terminal of the charge storage array and the transistor array. The first circuit wiring layer is closer to the first surface than the transistor array.

[0009] In an exemplary embodiment of the present disclosure, the first surface has a first interconnect contact pad array connected to the transistor array and a second interconnect contact pad array connected to the second connection terminal. The first interconnect contact pad array extends through the first surface to connect to the transistor array, and the second interconnect contact pad array extends through the first surface to connect to the second connection terminal.

[0010] In an exemplary embodiment of the present disclosure, the second interconnection contact pad array is formed on the periphery of the first interconnection contact pad array.

[0011] In an exemplary embodiment of the present disclosure, the charge storage array includes multiple storage capacitors, and the second connection end includes: a first conductive layer, connected to the upper electrodes of the multiple storage capacitors; a second conductive layer, covering and connecting the first conductive layer, and surrounding the periphery of the transistor array and the charge storage array.

[0012] In an exemplary embodiment of the present disclosure, a second stacking structure is further included. The second stacking structure has a second surface. The second surface of the second stacking structure is used to bond with the first surface of the first stacking structure.

[0013] In an exemplary embodiment of the present disclosure, the second stacking structure includes a substrate and a control circuit arranged on the substrate. The control circuit is closer to the second surface of the second stacking structure than the substrate. The control circuit is used to connect the transistor array, and the substrate is used to connect the second connection end of the charge storage array.

[0014] In an exemplary embodiment of the present disclosure, the second stacked structure further includes a second circuit wiring layer connecting the control circuit and the substrate, and the second circuit wiring layer is closer to the second surface of the second stacked structure than the control circuit.

[0015] In an exemplary embodiment of the present disclosure, a third interconnect contact pad array and a fourth interconnect contact pad array are provided on the second surface of the second stack structure, the third interconnect contact pad array is used to connect the transistor array and the control circuit, and the fourth interconnect contact pad array is used to connect the second connection end of the charge storage array and the substrate.

[0016] In an exemplary embodiment of the present disclosure, the fourth interconnection contact pad array surrounds the third interconnection contact pad array.

[0017] In an exemplary embodiment of the present disclosure, the second circuit wiring layer includes a third contact structure and a fourth contact structure, the third contact structure is used to connect the third interconnection contact pad array and the control circuit, and the fourth contact structure is used to connect the fourth interconnection contact pad array and the substrate.

[0018] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: forming a transistor array on a substrate; forming a charge storage array on the transistor array, the charge storage array having a first connection end and a second connection end, the first connection end being used to connect the charge storage array to the transistor array, the second connection end surrounding the periphery of the transistor array and the charge storage array and extending close to the substrate; and removing the substrate to form a first stacked structure.

[0019] In an exemplary embodiment of the present disclosure, removing the substrate to form a first stacked structure includes: removing the substrate by thinning; forming a first connection terminal connected to the second connection end; forming a first circuit wiring layer connecting the first connection terminal and the transistor array; forming a first interconnection contact pad array and a second interconnection contact pad array connected to the first circuit wiring layer, the first interconnection contact pad array being connected to the transistor array through the first circuit wiring layer, and the second interconnection contact pad array being connected to the charge storage array through the first circuit wiring layer.

[0020] In an exemplary embodiment of the present disclosure, the method further includes: forming a second stacking structure, and bonding the first stacking structure to the second stacking structure.

[0021] In an exemplary embodiment of the present disclosure, forming a second stacked structure includes: forming a control circuit on a substrate; forming a second circuit wiring layer connected to the control circuit, the second circuit wiring layer connecting the control circuit and the substrate; forming a third interconnect contact pad array and a fourth interconnect contact pad array connecting the second circuit wiring layer, the third interconnect contact pad array connected to the control circuit through the second circuit wiring layer, and the fourth interconnect contact pad array connected to the substrate of the charge storage array through the second circuit wiring layer.

[0022] In the disclosed embodiment, by having the second connection end of the charge storage array surround the periphery of the transistor array and the charge storage array, not only can the transistor array be brought close to the bonding surface, facilitating control of the transistor array, but the second connection end of the charge storage array can also be brought close to the bonding surface, facilitating centralized control of the transistor array and the charge storage array. Furthermore, since the second connection end of the charge storage array is usually grounded, the ground end surrounding the transistor array and the charge storage array can shield the transistor array and the charge storage array from external interference signals, thereby improving circuit reliability.

[0023] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0025] FIG. 1 is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0026] FIG2 is a schematic diagram of a first stacking structure in one embodiment of the present disclosure.

[0027] 3A to 3D are schematic diagrams of the second connection end in an embodiment of the present disclosure.

[0028] 4A and 4B are schematic diagrams of a second connection end and a second contact structure in an embodiment of the present disclosure.

[0029] FIG5 is a schematic diagram of a first surface in the present disclosure.

[0030] 6A to 6D are schematic diagrams of another viewing angle of the first surface in an embodiment of the present disclosure.

[0031] FIG. 7 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure.

[0032] FIG8 is a schematic diagram of a second stacking structure in one embodiment of the present disclosure.

[0033] FIG9 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0034] 10A to 10G are schematic diagrams of the process of the method shown in FIG. 9 .

[0035] 11A to 11C are schematic process flow diagrams of method 900 in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0037] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0038] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] FIG. 1 is a schematic structural diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0040] 1 , a semiconductor structure 100 may include:

[0041] A first stacked structure 1 having a first surface 10 for bonding;

[0042] The first stacked structure 1 includes a transistor array 11 and a charge storage array 12. The transistor array 11 and the charge storage array 12 are stacked in a direction perpendicular to the first surface 10. The transistor array 11 is closer to the first surface 10 than the charge storage array 12.

[0043] The charge storage array 12 has a first connection end 121 and a second connection end 122 . The first connection end 121 is used to connect the charge storage array 12 to the transistor array 11 . The second connection end 122 surrounds the periphery of the transistor array 11 and the charge storage array 12 and extends close to the first surface 10 .

[0044] In the disclosed embodiment, the transistor array 11 may include a plurality of parallel storage transistors (not shown), each of which is a vertical channel transistor (VCT). The source of each storage transistor (the end facing away from the first surface 10 in a direction perpendicular to the first surface 10) is connected to a storage capacitor, and the plurality of storage capacitors corresponding to the plurality of storage transistors together constitute a charge storage array 12. In some embodiments, the storage transistors and storage capacitors constitute a DRAM memory cell.

[0045] The drain of each storage transistor (the end close to the first surface 10 in the direction perpendicular to the first surface 10) is connected to a bit line. Multiple storage transistors can be connected to the same bit line or to different bit lines. In some cases, the transistor array 11 can be a storage transistor of one or more unit storage arrays, and the unit storage array includes but is not limited to a channel storage array, a rank storage array, a bank storage array, a row storage array, and a column storage array.

[0046] In the charge storage array 12, the top electrodes of the multiple storage capacitors are connected to a second connection terminal 122. In some embodiments, the second connection terminal 122 is a common electrode for the multiple storage capacitors. The bottom electrodes (opposite to the top electrodes) of the multiple storage capacitors are respectively connected to the source electrodes of corresponding storage transistors in the transistor array 11. Because the top electrodes of the storage capacitors in the storage array are typically grounded, the second connection terminal 122 surrounding the periphery of the transistor array 11 and the charge storage array 12 is actually a ground layer.

[0047] Providing a ground layer around the periphery of transistor array 11 and charge storage array 12 provides at least the following benefits. First, it effectively reduces interference from external signals on the memory cells (including storage transistors and storage capacitors), improving the stability and reliability of the memory cells. Second, the ground layer acts as a current loop, reducing the resistance of the interconnect path, increasing signal transmission speed, and lowering power consumption. Third, the ground layer facilitates heat dissipation, enabling better conduction and dispersion of heat within the integrated circuit, helping to maintain the chip's operating temperature within a suitable range. Finally, it effectively suppresses electromagnetic interference (EMI) generated by the memory cells, reducing their impact on other circuits and improving the anti-interference capability of the entire integrated circuit.

[0048] Since the second connection end 122 has a larger area, its electrical conductivity and thermal conductivity are better than those of conventional capacitor electrodes, which is equivalent to increasing the ground area of ​​each storage capacitor. A larger ground area can better suppress external noise and interference signals and reduce the possibility of charge loss in the storage capacitor. Therefore, increasing the ground area of ​​each storage capacitor can greatly improve the stability and reliability of the stored charge. In addition, since the storage capacitor needs to release the charge through the bit line to perform a read operation, increasing the ground area of ​​the storage capacitor can reduce the time and power consumption required for the bit line to release the charge, that is, reduce the read power consumption of the storage array. The write operation to the storage array requires storing the charge in the storage capacitor. Increasing the ground area of ​​the storage capacitor can improve the charging efficiency of the storage capacitor, thereby speeding up the write speed. Finally, a larger ground area can reduce internal noise and stray signals and improve signal quality. Therefore, increasing the ground area of ​​each storage capacitor can also improve the signal-to-noise ratio of the storage cell.

[0049] In addition, by extending the second connection terminal 122 connected to the upper electrodes of multiple storage capacitors to close to the first surface 10, the control terminals of the transistor array 11 and the charge storage array 12 can be set to the first surface 10 at the same time, so that after the bonding to the first surface 10 is completed, the transistor array 11 and the charge storage array 12 can be controlled simultaneously through the first surface 10, solving the problem that multiple structures cannot be controlled simultaneously under the vertical layout.

[0050] When the transistor array 11 is a storage transistor of one or more unit memory arrays, the second connection terminal 122 can serve as a common upper electrode of the storage capacitors of the one or more unit memory arrays, providing an overall ground terminal for the storage capacitors of the one or more unit memory arrays. At the same time, the one or more unit memory arrays are better isolated from other memory arrays, thereby optimizing the aforementioned performance of the one or more unit memory arrays as a whole, such as data writing speed, data reading power, signal transmission speed, storage charge stability and reliability, and signal-to-noise ratio.

[0051] FIG2 is a schematic diagram of a first stacking structure in one embodiment of the present disclosure.

[0052] 2 , in one embodiment, the first stacked structure 1 further includes a first circuit wiring layer 13 , which connects the second connection terminal 122 of the charge storage array 12 and the transistor array 11 . The first circuit wiring layer 13 is closer to the first surface 10 than the transistor array 11 .

[0053] The first circuit wiring layer 13 may be a redistribution layer (RDL). The first circuit wiring layer 13 simultaneously connects the transistor array 11 and the second connection terminal 122. The connection method between the first circuit wiring layer 13 and the transistor array 11 may be the same as or different from the connection method between the first circuit wiring layer 13 and the second connection terminal 122. The first circuit wiring layer 13 includes a first contact structure required for connection with the transistor array 11, and a second contact structure required for connection with the second connection terminal 122. The materials, shapes, and formation methods of the first and second contact structures may be the same or different. In some embodiments, the first circuit wiring layer 13 may also include conductive lines formed by a metal interconnection process.

[0054] In some embodiments, the transistors in transistor array 11 are connected to bit lines (BL). In this case, the signal to be drawn from one end of transistor array 11 near first surface 10 is a bit line signal. The first contact structure is a contact structure, such as a contact, between first circuit wiring layer 13 and the bit line. The material of the bit line includes metal silicide, including but not limited to cobalt silicide, titanium silicide, or nickel silicide. In this case, the first contact structure can be a metal-semiconductor contact structure.

[0055] In some embodiments, the second connection end 122 is made of metal material, and the second contact structure may be a metal contact.

[0056] In other embodiments, the second connection terminal 122 is a semiconductor material. In this case, the second contact structure can be a metal-semiconductor contact structure. Depending on whether the material of the second connection terminal 122 is the same as or different from the bit line material, the first contact structure and the second contact structure can be the same or different.

[0057] Figures 3A to 3D are schematic diagrams of the second connection terminal in an embodiment of the present disclosure. The shape, structure, and number of capacitors in the figures are for illustration only and do not limit the storage capacitor.

[0058] 3A , in one embodiment, the charge storage array 12 includes a plurality of storage capacitors C, and the second connection terminal 122 includes:

[0059] The first conductive layer 1221 is connected to the upper electrodes 31 of the plurality of storage capacitors C;

[0060] The second conductive layer 1222 covers and connects to the first conductive layer 1221 and surrounds the periphery of the transistor array 11 and the charge storage array 12 .

[0061] As shown, storage capacitor C includes an upper electrode 31, a dielectric layer 32, and a lower electrode 33. Lower electrode 33 is connected to the source of storage transistor T via a contact pad 34. Dielectric layer 32 is located between upper electrode 31 and lower electrode 33. Multiple contact pads 34 constitute a first connection terminal 121 of charge storage array 12. Storage transistor T is a vertical channel transistor (VCT), with its source connected to contact pad 34 and its drain connected to a bit line (not shown).

[0062] In some embodiments, the material of the first conductive layer 1221 includes silicon germanium, and the material of the second conductive layer 1222 includes polysilicon (poly). In some embodiments, the material of the second conductive layer 1222 includes metal, such as tungsten (W).

[0063] Compared with pure germanium and pure silicon, germanium-silicon (Ge-Si) has higher electrical conductivity and lower band gap, good temperature stability, and high mechanical strength and hardness. Applying germanium-silicon to the first conductive layer 1221 can make the second connection end 122 have good conductivity and supporting properties, and good temperature stability.

[0064] Using polysilicon (Poly) as the second conductive layer allows for precise adjustment of the polysilicon's resistance by controlling the material's grain size and doping concentration. Furthermore, polysilicon possesses high mechanical strength and stability, resisting stress and deformation during the manufacturing process. It also offers low manufacturing costs and ease of processing, further enhancing the support capabilities of the second connection terminal 122 without compromising its electrical conductivity. This allows for structural stability and uniform dimensions of the components of the second connection terminal 122 to be maintained even after its area is expanded, improving electrical uniformity.

[0065] 3B , in another embodiment, the second connection terminal 122 may also be directly connected to the upper electrodes of a plurality of storage capacitors C. In this case, the second connection terminal 122 may be formed of polysilicon.

[0066] Referring to FIG3C , in yet another embodiment, the charge storage array 12 includes multiple storage capacitors C. The second connection terminal 122 serves as a common top electrode for the multiple storage capacitors C. The material of the second connection terminal 122 is the same as the material of the bottom electrode (the electrode for connecting to the source of the transistor) of the storage capacitors C, namely, a metal or semiconductor material. The structure of the embodiment shown in FIG3B can reduce the number of manufacturing processes, improve manufacturing efficiency, and maximize the ground area of ​​the charge storage array 12.

[0067] 3D , in another embodiment, a second connection terminal 122 may be provided to connect to a common upper electrode 32 of a plurality of storage capacitors C. In this case, the material of the second connection terminal 122 and the material of the upper electrode 32 are both metal or semiconductor.

[0068] 4A and 4B are schematic diagrams of a second connection end and a second contact structure in an embodiment of the present disclosure.

[0069] When the material of the second connection end 122 is a semiconductor material, the second contact structure is a metal-semiconductor contact structure, which can be formed by a method such as a Damascene process.

[0070] Referring to FIG4A , in one embodiment, the second connection end 122 has a brim structure 1223 for forming the second contact structure 41. In this case, an interconnection hole aligned with the brim structure 1223 can be formed, and the interconnection hole can be filled with a conductive material to form the second contact structure 41. This solution is suitable for scenarios where the second connection end 122 is relatively thin in a direction parallel to the first surface 10 and is insufficient to accommodate the second contact structure.

[0071] 4B , in another embodiment, the portion of the second connection end 122 near the first surface 10 does not have a special design. If the working width allows, an interconnection hole aligned with the second connection end 122 can be directly formed, and the interconnection hole can be filled with a conductive material to form the second contact structure 41. This solution is suitable for scenarios where the second connection end 122 is relatively thick in a direction parallel to the first surface 10.

[0072] Depending on the material and shape of the second connection end 122 , there may be multiple second contact structures, which are not listed here one by one.

[0073] FIG5 is a schematic diagram of a first surface in the present disclosure.

[0074] 5 , in one embodiment, the first surface 10 has a first interconnect contact pad array 14 connected to the transistor array 11 and a second interconnect contact pad array 15 connected to the second connection terminal 122 . The first interconnect contact pad array 14 extends through the first surface 10 to connect to the transistor array 11 , and the second interconnect contact pad array 15 extends through the first surface 10 to connect to the second connection terminal 122 .

[0075] Figure 5 shows the situation where the first circuit wiring layer 13 is present. In this case, the first interconnection contact pad array 14 extends through the first surface 10 and connects to the transistor array 11 through the first circuit wiring layer 13, and the second interconnection contact pad array 15 extends through the first surface 10 and connects to the second connection terminal 122 through the first circuit wiring layer 13.

[0076] In some embodiments, first interconnection contact pad array 14 extends through first surface 10 and connects to transistor array 11 via first contact structure 51 in first circuit wiring layer 13, and second interconnection contact pad array 15 extends through first surface 10 and connects to second connection terminal 122 via second contact structure 41 in first circuit wiring layer 13. First contact structure 51 may include only contacts or may include interconnection holes and conductive lines between contacts.

[0077] Because the first surface 10 will be used for hybrid bonding later, which has very high requirements for interface flatness and dishing, the first interconnection contact pad array 14 and the second interconnection contact pad array 15 are ideally flush with the first surface 10. To account for processing tolerances, the first interconnection contact pad array 14 and the second interconnection contact pad array 15 can have a limited range of concavity or convexity relative to the first surface 10, within a range of 0-20 nm, to keep the first surface 10 as smooth and flat as possible.

[0078] In other embodiments, the first circuit wiring layer 13 may not exist, the first interconnection contact pad array 14 extends through the first surface 10 to directly connect to the transistor array 11 , and the second interconnection contact pad array 15 extends through the first surface 10 to directly connect to the second connection terminal 122 .

[0079] The first interconnection contact pad array 14 and the second interconnection contact pad array 15 provided on the first surface 10 are used for subsequent bonding with other structures.

[0080] Figures 6A to 6D are schematic diagrams of the first surface from another perspective in an embodiment of the present disclosure. The shapes and numbers of first interconnection contact pad array 14 and second interconnection contact pad array 15 in the figures are for illustration only, to illustrate the relative positional relationship between first interconnection contact pad array 14 and second interconnection contact pad array 15, and do not constitute a limitation on the actual structure, number, or internal arrangement of first interconnection contact pad array 14 and second interconnection contact pad array 15.

[0081] In the embodiment of the present disclosure, the second interconnection contact pad array 15 is formed on the periphery of the first interconnection contact pad array 14 .

[0082] 6A , in one embodiment, the second connection terminal 122 is disposed around the transistor array 11 . In this case, the second interconnection contact pad array 15 surrounds the first interconnection contact pad array 14 , forming a complete shield for the first interconnection contact pad array 14 .

[0083] 6B and 6C , in other embodiments, the second connection terminals 122 are disposed only on two sides of the transistor array 11. Correspondingly, the second interconnection contact pad array 15 is disposed on two sides of the first interconnection contact pad array 14, either in the first direction or in the second direction. This improves manufacturing efficiency and enables shielding in opposite directions. The direction in which the second connection terminals 122 are disposed can be determined based on the integrated circuit layout.

[0084] 6D , in yet other embodiments, second connection terminal 122 may be disposed only on one side of transistor array 11, and correspondingly, second interconnection contact pad array 15 may be disposed on one side of first interconnection contact pad array 14, thereby reducing processing difficulty and improving manufacturing efficiency. The direction in which second connection terminal 122 is disposed may be determined based on the integrated circuit layout.

[0085] FIG. 7 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure.

[0086] 7 , in another embodiment, the semiconductor structure 100 further includes a second stack structure 2 . The second stack structure 2 has a second surface 20 . The second surface 20 of the second stack structure 2 is configured to be bonded to the first surface 10 of the first stack structure 1 .

[0087] In the embodiment shown in FIG. 7 , the second stacked structure 2 includes a substrate 21 and a control circuit 22 disposed on the substrate 21. The control circuit 22 is closer to the second surface 20 of the second stacked structure 2 than the substrate 21. The control circuit 22 is used to connect to the transistor array 11, and the substrate 21 is used to connect to the second connection terminal 122 of the charge storage array 12. It will be understood that the control circuit 22 includes multiple transistors and other electronic components.

[0088] By bonding the second stacking structure 2 to the first stacking structure 1, the volume of the memory can be reduced; by connecting the substrate 21 in the second stacking structure 2 to the second connection terminal 122 of the charge storage array 12 in the first stacking structure 1, a better grounding connection can be provided for the charge storage array 12, so that the second stacking structure 2 can better control the first stacking structure 1.

[0089] FIG8 is a schematic diagram of a second stacking structure in one embodiment of the present disclosure.

[0090] 8 , in one embodiment, the second stacked structure 2 further includes a second circuit wiring layer 23, which connects the control circuit 22 and the substrate 21. The second circuit wiring layer 23 is closer to the second surface 20 of the second stacked structure 2 than the control circuit 22. The second circuit wiring layer 23 may also be a redistribution layer.

[0091] In addition, in some embodiments, the second surface 20 of the second stacked structure 2 is provided with a third interconnection contact pad array 24 and a fourth interconnection contact pad array 25, the third interconnection contact pad array 24 is used to connect the transistor array 11 and the control circuit 22, and the fourth interconnection contact pad array 25 is used to connect the second connection terminal 122 of the charge storage array 12 and the substrate 21.

[0092] The second circuit wiring layer 23 may include a third contact structure 81 and a fourth contact structure 82. The third contact structure 81 is used to connect the third interconnect contact pad array 24 and the control circuit 22, and the fourth contact structure 82 is used to connect the fourth interconnect contact pad array 25 and the substrate 21. As can be seen from Figure 8, the length of the fourth contact structure 82 is greater than the length of the third contact structure 81. The fourth contact structure 82 can penetrate into the substrate 21 by manufacturing TSVs (Through Silicon Vias) on the substrate 21, so that the signal of the second connection terminal 122 can be subsequently led from the back of the substrate 21 through the contact pads (pads), the fourth contact structure 82, and the second contact structure 41 to the chip package on the back of the substrate 21.

[0093] Similar to the relative positional relationship between the first interconnection contact pad array 14 and the second interconnection contact pad array 15, the fourth interconnection contact pad array 25 may also surround the third interconnection contact pad array 24. When the first interconnection contact pad array 14 and the second interconnection contact pad array 15 are in other relative positional relationships as shown in Figures 6A to 6D, the third interconnection contact pad array 24 and the fourth interconnection contact pad array 25 are also in a corresponding positional relationship, which will not be further described.

[0094] Because the second surface 20 will be used for hybrid bonding later, which has very high requirements for interface flatness and dishing, the third interconnection contact pad array 24 and the fourth interconnection contact pad array 25 are ideally flush with the second surface 20. To account for processing tolerances, the third interconnection contact pad array 24 and the fourth interconnection contact pad array 25 can have a limited range of concavity or convexity relative to the second surface 20, within a range of 0-20 nm, to keep the second surface 20 as smooth and flat as possible.

[0095] FIG9 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0096] 9 , a manufacturing method 900 may be used to manufacture the semiconductor structure according to any of the above embodiments, including:

[0097] Step S1, forming a transistor array 11 on a substrate;

[0098] Step S2: forming a charge storage array 12 on the transistor array 11. The charge storage array 12 has a first connection terminal 121 and a second connection terminal 122. The first connection terminal 121 is used to connect the charge storage array 12 to the transistor array 11. The second connection terminal 122 surrounds the periphery of the transistor array 11 and the charge storage array 12 and extends close to the substrate.

[0099] Step S3: removing the substrate to form a first stacking structure 1.

[0100] 10A to 10G are schematic diagrams of the process of the method shown in FIG. 9 .

[0101] Referring to FIG10A , in step S1, a transistor array 11 is formed on a substrate. This can be accomplished by performing photolithography, deposition, or other processes on a substrate 90 to form bit lines corresponding to a plurality of vertical channel transistors, a plurality of vertical channel transistors connected to the bit lines, and word lines connected to the plurality of vertical channel transistors, thereby forming a plurality of memory transistors connected to the word lines and bit lines. FIG10A is for illustrative purposes only, as the transistor manufacturing process is not an improvement direction for the embodiments of the present disclosure.

[0102] Referring to FIG10B , in step S2, a charge storage array 12 is formed on the transistor array 11. The charge storage array 12 has a first connection terminal 121 and a second connection terminal 122. The first connection terminal 121 is used to connect the charge storage array 12 to the transistor array 11. The second connection terminal 122 surrounds the periphery of the transistor array 11 and the charge storage array 12 and extends close to the substrate 90. The manufacturing process can be to first form a plurality of transistor-capacitor contact structures (contact) on the basis of the transistor array 11, thereby forming a first connection terminal 121 composed of a plurality of transistor-capacitor contact structures. Next, a lower electrode of a storage capacitor (see lower electrode 33 in FIG3A ) is formed on each transistor-capacitor contact structure. Next, a dielectric layer of the storage capacitor (see dielectric layer 32 in FIG3A ) is formed on the basis of the lower electrode. Finally, an upper electrode of the storage capacitor (see upper electrode 31 in FIG3A to FIG3D ) is formed on the basis of the dielectric layer to form a storage capacitor array 123. In the embodiment of the present disclosure, the storage capacitor array 123 may include a portion of the second connection terminal 122 (the second connection terminal 122 is a common upper electrode of multiple storage capacitors), or may be independent of the second connection terminal 122 .

[0103] Referring to FIG10C , when multiple storage capacitors share a common upper electrode and the upper electrode is the second connection terminal 122, the second connection terminal 122 can be manufactured by a single process (including etching, deposition, CMP grinding, etc.). When multiple storage capacitors share a common upper electrode and the upper electrode is connected to the second connection terminal 122, the second connection terminal 122 can be formed after the upper electrode is formed. When multiple storage capacitors have their own upper electrodes, it is necessary to fill the gaps between the multiple storage capacitors after forming the multiple upper electrodes of the multiple storage capacitors, and then form the second connection terminal 122 on the filled structure. Finally, the charge storage array 12 is formed.

[0104] 10D , an insulating material is deposited on the charge storage array 12 to form a structure. The insulating material may be an oxide, such as silicon dioxide. CMP (Chemical Mechanical Polishing) is then performed to smooth the upper surface of the structure.

[0105] Referring to Figure 10E, in step S3, a carrier wafer 91 is introduced, and the carrier wafer 91 is used to fix the upper surface of the structure so that the substrate 90 can be removed by thinning to facilitate subsequent processing. A carrier wafer refers to a larger wafer used to support and carry chips in semiconductor manufacturing, and is used to accommodate and support multiple chips during the manufacturing process. The carrier wafer 91 can be bonded to the upper surface of the structure to complete the fixation. The method of thinning the substrate 90 located on the back of the structure (Backside Silicon thinning) includes but is not limited to steps such as mechanical grinding and chemical mechanical polishing to expose a portion of the transistor array 11 and the second connection terminal 122.

[0106] 10F , after the substrate 90 is removed by thinning, a second contact structure connected to the second connection terminal 122 and a first contact structure connected to the first connection terminal 121 are formed on the basis of the exposed transistor array 11 and a portion of the second connection terminal 122 , thereby forming a first circuit wiring layer 13 .

[0107] 10G , next, a first interconnection contact pad array 14 and a second interconnection contact pad array 15 are formed to connect to the first circuit wiring layer 13. The first interconnection contact pad array 14 is connected to the transistor array 11 through the first circuit wiring layer 13, and the second interconnection contact pad array 15 is connected to the charge storage array 12 through the first circuit wiring layer 13. Specifically, the first interconnection contact pad array 14 and the second interconnection contact pad array 15 can be formed by a dual damascene process. After forming the RDL (Redistribution Layer) layer, the first interconnection contact pad array 14 and the second interconnection contact pad array 15 can be manufactured to achieve direct interconnection between the first stacked structure and the second stacked structure, establishing a high-speed signal transmission channel.

[0108] 11A to 11C are schematic process flow diagrams of method 900 in another embodiment of the present disclosure.

[0109] In some embodiments, the method 900 further includes forming a second stack structure 2 in step S4 , where the second stack structure 2 includes a control circuit 22 corresponding to the transistor array 11 ; and bonding the first stack structure 1 to the second stack structure 2 in step S5 .

[0110] Referring to FIG. 11A , in step S4, a control circuit 22 may be first formed on the substrate 21, and then an insulating material may be deposited. A second circuit wiring layer 23 connected to the control circuit 22 may be formed on the structure formed after the deposition. The second circuit wiring layer 23 connects the control circuit 22 and the substrate 21 and includes a third contact structure 81 connected to the control circuit 21 and a fourth contact structure 82 connected to the substrate 21, wherein the fourth contact structure 82 may partially include a TSV (Through Silicon Via) buried in the substrate 21. Next, a third interconnection contact pad array 24 and a fourth interconnection contact pad array 25 are formed to connect the second circuit wiring layer 23. The third interconnection contact pad array 24 connects to the control circuit 22 via the third contact structure 81 in the second circuit wiring layer 23, and the fourth interconnection contact pad array 25 connects to the substrate 21 via the fourth contact structure 82 in the second circuit wiring layer 23. In this way, a second stacked structure 2 and its second surface 20 are formed.

[0111] 11B , in step S5, hybrid bonding may be performed on the first surface 10 of the first stacked structure 1 and the second surface 20 of the second stacked structure 2. Hybrid bonding typically utilizes metal bonding or intermetallic bonding. In the disclosed embodiment, the third interconnection contact pad array 24 and the fourth interconnection contact pad array 25 are bonded to the first interconnection contact pad array 14 and the second interconnection contact pad array 15, respectively.

[0112] 11C , the substrate 21 may be thinned and then subjected to a BVR & Al PAD process. "BVR & Al PAD" refers to the "Backside Via Reveal and Aluminum Pad" process.

[0113] This step includes the following operations:

[0114] BVR (Backside Via Reveal): First, a hole etching step is performed on the backside of the substrate 21 to form the desired through-hole structure. These through-holes can be used for electrical connections, heat dissipation, or other specific purposes. The location and layout of the holes are determined according to the design requirements.

[0115] Al PAD (Aluminum Pad): Next, a layer of aluminum metal is coated around the backside hole to form an aluminum pad 26. The function of the aluminum pad is to provide a reliable electrical connection point to connect the backside hole of the integrated circuit and components such as the package substrate.

[0116] By performing the BVR and Al PAD steps, a through hole can be formed on the back side of the substrate 21 and an aluminum pad 26 can be created around the through hole to achieve electrical connection and other functional requirements for the manufacture of advanced packaging and three-dimensional integrated circuits (3D-ICs).

[0117] According to the embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units for embodiment.

[0118] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first stacking structure (1), the first stacking structure (1) having a first surface (10) for bonding; The first stacked structure (1) comprises a transistor array (11) and a charge storage array (12), wherein the transistor array (11) and the charge storage array (12) are stacked in a direction perpendicular to the first surface (10), and the transistor array (11) is closer to the first surface (10) than the charge storage array (12); wherein: The charge storage array (12) has a first connection end (121) and a second connection end (122), the first connection end (121) being used to connect the charge storage array (12) and the transistor array (11), and the second connection end (122) surrounding the periphery of the transistor array (11) and the charge storage array (12) and extending close to the first surface (10).

2. The semiconductor structure according to claim 1, wherein: The first stacked structure also includes a first circuit wiring layer, which connects the second connection end of the charge storage array and the transistor array. The first circuit wiring layer is closer to the first surface than the transistor array.

3. The semiconductor structure according to claim 1, wherein: The first surface has a first interconnection contact pad array connected to the transistor array and a second interconnection contact pad array connected to the second connection terminal. The first interconnection contact pad array extends through the first surface to connect the transistor array, and the second interconnection contact pad array extends through the first surface to connect the second connection terminal.

4. The semiconductor structure according to claim 3, characterized in that The second interconnection contact pad array is formed at the periphery of the first interconnection contact pad array.

5. The semiconductor structure according to claim 1, wherein: The charge storage array includes a plurality of storage capacitors, and the second connection terminal includes: A first conductive layer connected to upper electrodes of the plurality of storage capacitors; The second conductive layer covers and connects to the first conductive layer and surrounds the outer periphery of the transistor array and the charge storage array.

6. The semiconductor structure according to claim 1, wherein: The invention also includes a second stacking structure, wherein the second stacking structure has a second surface, and the second surface of the second stacking structure is used for bonding with the first surface of the first stacking structure.

7. The semiconductor structure according to claim 6, wherein: The second stacking structure includes a substrate and a control circuit arranged on the substrate, the control circuit is closer to the second surface of the second stacking structure than the substrate, the control circuit is used to connect the transistor array, and the substrate is connected to the second connection end of the charge storage array.

8. The semiconductor structure according to claim 7, wherein: The second stacked structure further includes a second circuit wiring layer, the second circuit wiring layer connects the control circuit and the substrate, and the second circuit wiring layer is closer to the second surface of the second stacked structure than the control circuit.

9. The semiconductor structure according to claim 7, wherein: The second surface of the second stacked structure is provided with a third interconnection contact pad array and a fourth interconnection contact pad array, the third interconnection contact pad array is used to connect the transistor array and the control circuit, and the fourth interconnection contact pad array is used to connect the second connection end of the charge storage array and the substrate.

10. The semiconductor structure according to claim 9, wherein: The fourth interconnect contact pad array surrounds the third interconnect contact pad array.

11. The semiconductor structure according to claim 9, wherein: The second circuit wiring layer includes a third contact structure and a fourth contact structure, wherein the third contact structure is used to connect the third interconnection contact pad array and the control circuit, and the fourth contact structure is used to connect the fourth interconnection contact pad array and the substrate.

12. A method for manufacturing a semiconductor structure, characterized in that: include: forming a transistor array on a substrate; forming a charge storage array on the transistor array, the charge storage array having a first connection end and a second connection end, the first connection end being used to connect the charge storage array with the transistor array, the second connection end surrounding the periphery of the transistor array and the charge storage array and extending close to the substrate; The substrate is removed to form a first stacking structure.

13. The manufacturing method according to claim 12, characterized in that: The removing the substrate to form a first stacking structure comprises: removing the substrate by thinning; forming a second contact structure connected to the second connection terminal and a first contact structure connected to the first connection terminal, thereby forming a first circuit wiring layer; A first interconnect contact pad array and a second interconnect contact pad array connected to the first circuit wiring layer are formed, wherein the first interconnect contact pad array is connected to the transistor array through the first circuit wiring layer, and the second interconnect contact pad array is connected to the charge storage array through the first circuit wiring layer.

14. The manufacturing method according to claim 12, characterized in that: Also includes: A second stacking structure is formed, and the first stacking structure is bonded to the second stacking structure.

15. The manufacturing method according to claim 14, characterized in that: The forming of the second stacking structure comprises: forming a control circuit on the substrate; forming a second circuit wiring layer connected to the control circuit, wherein the second circuit wiring layer connects the control circuit and the substrate; A third interconnect contact pad array and a fourth interconnect contact pad array connected to the second circuit wiring layer are formed, the third interconnect contact pad array is connected to the control circuit through the second circuit wiring layer, and the fourth interconnect contact pad array is connected to the substrate of the charge storage array through the second circuit wiring layer.

16. The semiconductor structure according to claim 1, wherein: The transistor array includes a plurality of storage transistors arranged in parallel. The storage transistors are vertical channel transistors. At one end of the storage transistors which is away from the first surface in a direction perpendicular to the first surface, the storage transistors have sources connected to the charge storage array.

17. The semiconductor structure according to claim 16, wherein: The first stack structure also includes a bit line located at an end close to the first surface in a direction perpendicular to the first surface. The storage transistor has a drain connected to the bit line.

18. The semiconductor structure according to claim 2, wherein: The first circuit wiring layer includes a first contact structure and a second contact structure, the first contact structure is connected to the transistor array, and the second contact structure is connected to the second connection terminal.

19. The semiconductor structure according to claim 7, wherein: A contact pad is formed on the back of the substrate, and the contact pad is connected to the second connection end.

20. The semiconductor structure according to claim 18, wherein: The second connecting end has a brim structure, the brim structure is closer to the first surface than the first connecting end, and the second contact structure is connected to the brim structure.

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