Semiconductor device and manufacturing method therefor, and electronic device

Abstract

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises a substrate (1), and at least one transistor provided on the substrate (1). The transistor comprises a gate electrode (26) and a semiconductor layer (23). The semiconductor layer (23) comprises a first semiconductor sub-layer (231) at least partially surrounding the gate electrode (26) and a second semiconductor sub-layer (232) arranged on the side of the first semiconductor sub-layer (231) facing away from the gate electrode (26). The doping concentration of the second semiconductor sub-layer (232) is greater than the doping concentration of the first semiconductor sub-layer (231). The second semiconductor sub-layer (232) comprises a first part (2321) and a second part (2322) arranged at an interval on the surface of the first semiconductor sub-layer (231) facing away from the gate electrode (26).

Description

Semiconductor device, manufacturing method thereof, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed on December 19, 2023, with application number 202311755964.2 and invention name “A semiconductor device, a manufacturing method thereof, and an electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0003] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0004] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a semiconductor device, comprising:

[0008] a substrate, and at least one transistor disposed on the substrate;

[0009] The transistor includes a gate electrode and a semiconductor layer; the semiconductor layer includes a first semiconductor sublayer that at least partially surrounds the gate electrode and a second semiconductor sublayer that is arranged on a side of the first semiconductor sublayer away from the gate electrode, the doping concentration of the second semiconductor sublayer is greater than the doping concentration of the first semiconductor sublayer, and the second semiconductor sublayer includes a first part and a second part that are spaced apart on a surface of the first semiconductor sublayer away from the gate electrode.

[0010] In some embodiments, along a direction perpendicular to the substrate, gate electrodes of a plurality of transistors are interconnected to form a word line perpendicular to the substrate, and semiconductor layers of the plurality of transistors are spaced apart.

[0011] In some embodiments, the second semiconductor sublayer extends in a direction parallel to the substrate.

[0012] In some embodiments, the first portion and the second portion are spaced apart along a first direction, the first portion extends along a second direction, the second portion extends along the second direction, and the first direction and the second direction intersect and are both parallel to the substrate.

[0013] In some embodiments, the transistor includes only one gate electrode; and along a plane parallel to the substrate, a cross section of the first semiconductor sublayer is a closed loop.

[0014] In some embodiments, the transistor includes a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode are spaced apart along the second direction, the first gate electrodes of the multiple transistors are interconnected to form an integrated structure extending in a direction perpendicular to the substrate, the second gate electrodes of the multiple transistors are interconnected to form an integrated structure extending in a direction perpendicular to the substrate, the first semiconductor sublayer partially surrounds the first gate electrode, and the first semiconductor sublayer partially surrounds the second gate electrode.

[0015] In some embodiments, the semiconductor device further comprises:

[0016] An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate; a first hole penetrates the insulating layer and the conductive layer; the conductive layer includes a first electrode and a second electrode of the transistor, the first electrode is connected to the first part, and the second electrode is connected to the second part.

[0017] In some embodiments, the first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and an orthographic projection of the first sub-hole on the substrate falls within an orthographic projection of the second sub-hole on the substrate.

[0018] In some embodiments, the semiconductor device further comprises:

[0019] Insulating layers and conductive layers are alternately distributed along a direction perpendicular to the substrate; a third hole and a fourth hole penetrate the insulating layer and the conductive layer; and the third hole and the fourth hole are connected in the conductive layer.

[0020] In some embodiments, the first semiconductor sublayer, the first gate insulating layer, and the first gate electrode are sequentially distributed in the third hole from outside to inside;

[0021] The first semiconductor sublayer, the second gate insulating layer, and the second gate electrode are sequentially distributed in the fourth hole from the outside to the inside.

[0022] In some embodiments, the third hole includes a fifth sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and an orthographic projection of the fifth sub-hole on the substrate falls within an orthographic projection of the sixth sub-hole on the substrate;

[0023] The fourth hole includes a seventh sub-hole located in the insulating layer and the sixth sub-hole located in the conductive layer, and an orthographic projection of the seventh sub-hole on the substrate falls within an orthographic projection of the sixth sub-hole on the substrate.

[0024] In some embodiments, the semiconductor device further includes: a multi-layer memory cell array distributed in a direction perpendicular to the substrate, each layer of the memory cell array including multiple rows and columns of memory cells distributed along a first direction and a second direction, respectively, the memory cells including the transistors, and the second electrodes of the transistors in the same layer and in the same column distributed along the second direction are interconnected to form a bit line extending along the second direction.

[0025] In some embodiments, the second portions of the transistors in the same column and in the same layer distributed along the second direction are interconnected to form an integrated structure, and the first portions of the transistors in the same column and in the same layer distributed along the second direction are separated from each other.

[0026] In some embodiments, the semiconductor device further comprises:

[0027] A second hole passes through the insulating layer and the conductive layer; the second hole includes a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, and the fourth sub-hole has a groove extending in a horizontal direction relative to the third sub-hole.

[0028] In some embodiments, the semiconductor device further includes: a plurality of capacitors, each capacitor including a first capacitor electrode and a second capacitor electrode, wherein the first electrode and the second capacitor electrode are multiplexed.

[0029] In some embodiments, the second capacitor electrode includes a first sub-electrode; the first capacitor electrode surrounding the first sub-electrode, a first dielectric layer surrounding the first sub-electrode, and the first sub-electrode are sequentially distributed in the second hole from outside to inside.

[0030] In some embodiments, the first capacitor electrode is distributed on the inner wall of the groove, and the first sub-electrode extends in a direction perpendicular to the substrate and has a protruding portion extending into the groove.

[0031] In some embodiments, the second capacitor electrode further includes a second sub-electrode;

[0032] The second sub-electrode is distributed on a side of the first capacitor electrode facing away from the substrate, a side facing the substrate, and a side of the first capacitor electrode facing away from the second semiconductor sublayer. A second dielectric layer is provided between the second sub-electrode and the first capacitor electrode.

[0033] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0034] Providing a substrate, and forming a stacked structure including alternately arranged semiconductor structure layers and sacrificial layers on the substrate;

[0035] The stacked structure is patterned to form first trenches penetrating each layer, wherein the first trenches extend along a first direction; transistor regions are located between adjacent first trenches spaced apart along a second direction, wherein the first direction intersects the second direction and is parallel to the substrate;

[0036] A hole is formed in the transistor region, penetrating the stacked structure in a direction perpendicular to the substrate, and the sacrificial layer is removed by etching through the hole, and the sacrificial layer is replaced with an insulating layer; based on the hole, the semiconductor structure layer is etched in a direction parallel to the substrate to form a second semiconductor sublayer, and the second semiconductor sublayer includes a first part and a second part disconnected from each other; a plurality of gate electrodes arranged in a direction perpendicular to the substrate and a plurality of first semiconductor sublayers surrounding the gate electrodes are formed in the hole, the plurality of gate electrodes are connected to form an integrated structure, and the plurality of first semiconductor sublayers are separated from each other.

[0037] In some embodiments, the hole formed in the transistor region and penetrating the stacked structure in a direction perpendicular to the substrate includes: a third hole and a fourth hole formed in the same transistor region and penetrating the stacked structure in a direction perpendicular to the substrate;

[0038] The etching the semiconductor structure layer along a direction parallel to the substrate based on the hole comprises:

[0039] Etching the semiconductor structure layer in the third hole along a direction parallel to the substrate so that an orthographic projection of a sub-hole of the third hole in the insulating layer on the substrate falls within an orthographic projection of a sub-hole of the semiconductor structure layer on the substrate; and laterally etching the semiconductor structure layer in the fourth hole so that an orthographic projection of a sub-hole of the fourth hole in the insulating layer on the substrate falls within an orthographic projection of a sub-hole of the semiconductor structure layer on the substrate, and the third hole and the fourth hole are connected to the sub-holes of the semiconductor structure layer;

[0040] Forming a plurality of gate electrodes arranged in a direction perpendicular to the substrate and a plurality of first semiconductor sublayers surrounding the gate electrodes in the hole comprises:

[0041] A plurality of first gate electrodes extending in a direction perpendicular to the substrate are formed in the third hole, a plurality of second gate electrodes extending in a direction perpendicular to the substrate are formed in the fourth hole, and the first semiconductor sublayer is formed in the sub-holes of the semiconductor structure layer in the third hole and the fourth hole.

[0042] In some embodiments, forming a plurality of first semiconductor sub-layers surrounding the gate electrode in the hole includes: forming a plurality of first semiconductor sub-layers surrounding the gate electrode in the hole by epitaxial growth.

[0043] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0044] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0045] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0046] Summary of the Figures

[0047] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0048] FIG1A is a top view of a semiconductor device according to some embodiments; FIG1B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG1A ; FIG1C is a cross-sectional view parallel to the substrate along the DD′ direction in FIG1B ;

[0049] FIG2A is a top view of a stacked structure after formation according to some embodiments, and FIG2B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG2A ;

[0050] 3A is a top view after forming a first trench and a first insulating layer according to some embodiments; FIG. 3B is a cross-sectional view perpendicular to the substrate along the CC' direction in FIG. 3A ;

[0051] FIG4A is a top view after forming a first hole according to some embodiments, and FIG4B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG4A ;

[0052] FIG5A is a top view after forming a second insulating layer according to some embodiments, and FIG5B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG5A ;

[0053] FIG6A is a top view after exposing the first hole according to some embodiments, and FIG6B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG6A ;

[0054] FIG7A is a top view after forming a first groove according to some embodiments, and FIG7B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG7A ;

[0055] 8A is a top view after forming a first semiconductor structure layer according to some embodiments; FIG. 8B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG. 8A ;

[0056] 9A is a top view after forming word lines and gate insulating layers according to some embodiments; FIG. 9B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG. 9A ;

[0057] FIG10A is a top view after forming a second trench according to some embodiments, and FIG10B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG10A ;

[0058] FIG11A is a top view after forming a second groove according to some embodiments, and FIG11B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG11A ;

[0059] FIG12A is a top view after forming a bit line layer according to some embodiments, and FIG12B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG12A ;

[0060] FIG13A is a top view after forming a bit line and a third insulating layer according to some embodiments; FIG13B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG13A ;

[0061] FIG14A is a top view after forming a second hole according to some embodiments, and FIG14B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG14A ;

[0062] FIG15A is a top view after forming a third groove according to some embodiments; FIG15B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG15A ;

[0063] FIG16A is a top view after forming a first electrode layer and a fourth insulating layer according to some embodiments; FIG16B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG16A ;

[0064] FIG17A is a top view after forming a first electrode according to some embodiments; FIG17B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG17A ;

[0065] FIG18A is a top view after forming a first sub-electrode and a first dielectric layer according to some embodiments; FIG18B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG18A ;

[0066] FIG19A is a top view after forming a third trench according to some embodiments; FIG19B is a cross-sectional view perpendicular to the substrate along the AA′ direction in FIG19A ;

[0067] FIG20A is a top view of a semiconductor device according to some exemplary embodiments; FIG20B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG20A ; FIG20C is a cross-sectional view perpendicular to the substrate along the direction BB′ in FIG20A ; and FIG20D is a cross-sectional view parallel to the substrate along the direction DD′ in FIG20C ;

[0068] FIG21A is a top view after forming a third hole and a fourth hole according to some embodiments; FIG21B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG21A;

[0069] FIG22A is a top view after forming a second insulating layer according to some embodiments; FIG22B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG22A ;

[0070] FIG23A is a top view after exposing the third hole and the fourth hole provided in some embodiments, and FIG23B is a cross-sectional view perpendicular to the substrate along the A1A1′ direction in FIG23A :

[0071] FIG24A is a top view after forming a fourth groove according to some embodiments; FIG24B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG24A ;

[0072] FIG25A is a top view after forming a first semiconductor structure layer according to some embodiments; FIG25B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG25A ;

[0073] FIG26A is a top view after forming a first word line, a first gate insulating layer, a second word line, and a second gate insulating layer according to some embodiments; FIG26B is a cross-sectional view perpendicular to the substrate along the A1A1′ direction in FIG26A ;

[0074] FIG27A is a top view after forming a second trench according to some embodiments; FIG27B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG27A ;

[0075] FIG28A is a top view after forming a second groove according to some embodiments; FIG28B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG28A ;

[0076] FIG29A is a top view after forming a bit line layer according to some embodiments; FIG29B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG29A ;

[0077] FIG30A is a top view after forming a bit line and a third insulating layer according to some embodiments; FIG30B is a cross-sectional view perpendicular to the substrate along the direction A1A1′ in FIG30A ;

[0078] FIG31A is a top view after forming a second hole according to some embodiments, FIG31B is a cross-sectional view perpendicular to the substrate along the A1A1′ direction in FIG31A , and FIG31C is a cross-sectional view perpendicular to the substrate along the BB′ direction in FIG31A ;

[0079] FIG32A is a top view after forming a third groove according to some embodiments, FIG32B is a cross-sectional view perpendicular to the substrate along the A1A1′ direction in FIG32A , and FIG32C is a cross-sectional view perpendicular to the substrate along the BB′ direction in FIG32A ;

[0080] FIG33A is a top view after forming a first electrode layer and a fourth insulating layer according to some embodiments; FIG33B is a cross-sectional view perpendicular to the substrate along the A1A1′ direction in FIG33A; and FIG33C is a cross-sectional view perpendicular to the substrate along the BB′ direction in FIG33A;

[0081] FIG34A is a top view after forming a first electrode according to some embodiments; FIG34B is a cross-sectional view perpendicular to the substrate along the A1A1′ direction in FIG34A; and FIG34C is a cross-sectional view perpendicular to the substrate along the BB′ direction in FIG34A;

[0082] FIG35A is a top view after forming a first sub-electrode and a first dielectric layer according to some embodiments; FIG35B is a cross-sectional view perpendicular to the substrate along the A1A1′ direction in FIG35A; and FIG35C is a cross-sectional view perpendicular to the substrate along the BB′ direction in FIG35A;

[0083] Figure 36A is a top view after the third groove is formed provided in some embodiments, Figure 36B is a cross-sectional view perpendicular to the substrate along the A1A1' direction in Figure 36A, Figure 36C is a cross-sectional view perpendicular to the substrate along the BB' direction in Figure 36A, and Figure 36D is a cross-sectional view parallel to the substrate along the DD' direction in Figure 36B.

[0084] Details

[0085] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0086] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0087] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0088] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0089] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0090] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0091] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0092] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0093] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0094] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0095] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0096] In the embodiment of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0097] Figure 1A is a top view of a semiconductor device provided by some embodiments; Figure 1B is a cross-sectional view perpendicular to substrate 1 along the AA' direction in Figure 1A; and Figure 1C is a cross-sectional view parallel to substrate 1 along the DD' direction in Figure 1B. As shown in Figures 1A, 1B, and 1C, embodiments of the present disclosure provide a semiconductor device comprising a multi-layer memory cell array vertically stacked on substrate 1. The multi-layer memory cell array may be distributed along a third direction Z. The third direction Z may be perpendicular to substrate 1.

[0098] The memory cell array may include a plurality of bit lines 30, a plurality of word lines 40, and a plurality of memory cells. Each memory cell array may include a plurality of memory cells distributed in an array along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. The first direction X and the second direction Y may intersect. As shown in FIG1C , the bit lines 30 may be conductive lines extending along the second direction Y. The plurality of bit lines 30 of the same memory cell array may be spaced apart from each other, and the plurality of bit lines 30 of the same memory cell array may be spaced apart from each other along the first direction X. The bit lines 30 of different memory cell arrays may be stacked on the substrate 1, and the bit lines 30 at the same position in different layers may be spaced apart from each other.

[0099] The word line 40 can extend along the third direction Z, and multiple memory cells stacked in the vertical direction at the same position in different layers share one word line 40; different memory cells in the same layer correspond to different word lines 40, that is, different memory cells in the same layer are connected to different word lines 40.

[0100] The memory cell may be a 1T or 2T memory cell or other multi-transistor memory cell.

[0101] Taking a 1T1C memory cell as an example, the memory cell may include a transistor and a capacitor connected to the transistor. The transistor and capacitor of the same memory cell may be distributed along a first direction X. The transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The gate electrode 26 may be part of a word line 40, and the gate electrodes 26 of transistors at the same location on different layers may also be part of the same word line 40.

[0102] The second electrode 52 may be connected to the bit line 30, or the second electrode 52 may be part of the bit line 30. The second electrodes 52 of the transistors in the same column of memory cells in the same memory cell array and distributed along the second direction Y may be connected to the same bit line 30. That is, the second electrodes 52 of the transistors in the same column and distributed along the second direction Y are connected to form the bit line 30 extending along the second direction Y. The second electrodes 52 of the transistors in adjacent columns of the same memory cell array may be connected to different bit lines 30.

[0103] The capacitor may include a first capacitor electrode 41 and a second capacitor electrode 42. The first electrode 51 may be connected to the first capacitor electrode 41 of the capacitor, or the first electrode 51 and the first capacitor electrode 41 may share the same electrode.

[0104] The following description is made by taking a semiconductor device including a plurality of vertically stacked transistors at the same position as an example, and taking a 1T1C memory cell as an example.

[0105] As shown in FIG. 1A to FIG. 1C , an embodiment of the present disclosure provides a semiconductor device, which may include:

[0106] A substrate 1, and at least one transistor disposed on the substrate 1;

[0107] The transistor may include a gate electrode 26 and a semiconductor layer 23, the gate electrode 26 may extend in a direction perpendicular to the substrate 1; the semiconductor layer 23 may include a first semiconductor sublayer 231 that at least partially surrounds the gate electrode 26 and a second semiconductor sublayer 232 that is arranged on the side of the first semiconductor sublayer 231 away from the gate electrode 26, the doping concentration of the second semiconductor sublayer 232 is greater than the doping concentration of the first semiconductor sublayer 231, and the second semiconductor sublayer 232 may include a first part 2321 and a second part 2322 that are spaced apart on the surface of the first semiconductor sublayer 231 away from the gate electrode 26.

[0108] The above solution sets the high doping concentration sublayer on the outer side wall of the low doping concentration sublayer, which facilitates the early formation of the low doping concentration sublayer and the high doping concentration sublayer, avoids additional and more complicated doping operations during the semiconductor device manufacturing process, and simplifies the process.

[0109] In some embodiments, the semiconductor device may include multiple transistors distributed in different layers and stacked along a direction perpendicular to the substrate 1. Along the direction perpendicular to the substrate 1, multiple gate electrodes 26 of the multiple transistors are interconnected to form a word line 40 perpendicular to the substrate 1, and the multiple semiconductor layers 23 of the multiple transistors are arranged at intervals.

[0110] Among them, the second semiconductor sublayer 232 can be a heavily doped semiconductor film layer, and the first semiconductor sublayer 231 can be a lightly doped or undoped semiconductor film layer, so that the first semiconductor sublayer 231 can be used as the channel region of the transistor, and the two parts of the second semiconductor sublayer 232 can be used as the source contact region and drain contact region of the transistor, respectively contacting the source electrode and drain electrode.

[0111] The gate electrodes 26 of multiple transistors on different layers can be connected to form an integrated structure extending in a direction perpendicular to the substrate 1. This integrated structure is the word line 40. Before and after the word line 40 is formed, there is no need to separately form the gate electrode 26. After the word line 40 is formed, a portion of the word line 40 functions as the gate electrode 26.

[0112] In some embodiments, the cross-sections of the word line 40 at different locations parallel to the substrate 1 may have substantially the same size and shape. However, the present disclosure is not limited thereto, and the word line 40 may extend only in a direction perpendicular to the substrate 1 as a whole, but the morphology of the sidewalls of the word line 40 is not limited.

[0113] In some embodiments, the first semiconductor sublayer 231 may surround the gate electrode 26 partially or completely. That is, in a plane parallel to the substrate 1, the cross-section of the first semiconductor sublayer 231 may be an open loop or a closed loop. The cross-section of the first semiconductor sublayer 231 shown in FIG1C is a closed loop, in which case the transistor has a dual channel. However, the embodiments of the present disclosure are not limited thereto. The cross-section of the first semiconductor sublayer 231 in a plane parallel to the substrate 1 may be an open loop, in which case the transistor has a single channel.

[0114] In some embodiments, the second semiconductor sublayer 232 may extend along a second direction Y parallel to the substrate 1. This solution facilitates stacking semiconductor film layers with high doping concentrations and etching the semiconductor film layers to obtain the second semiconductor sublayer 232, without doping different semiconductor layers.

[0115] In some embodiments, the height of the first portion 2321 of the second semiconductor sublayer 232 along the direction perpendicular to the substrate 1 may be the same as or approximately the same as the height of the second portion 2322 of the second semiconductor sublayer 232 along the direction perpendicular to the substrate 1 .

[0116] In some embodiments, the first portion 2321 and the second portion 2322 of the second semiconductor sublayer 232 may be spaced apart along a first direction X, the first portion 2321 may extend along a second direction Y, and the second portion 2322 may extend along the second direction Y. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0117] In some embodiments, as shown in FIG1C , the second portions 2322 of the second semiconductor sublayers 232 of transistors in the same layer and in the same column along the second direction Y may be connected to form an integrated structure. The integrated structure may extend along the second direction Y. However, the disclosed embodiments are not limited thereto, and the second portions 2322 of the second semiconductor sublayers 232 of transistors in the same layer and in the same column along the second direction Y may be separated from each other.

[0118] 1C , the first portions 2321 of the second semiconductor sublayers 232 of transistors in the same layer and in the same column along the second direction Y may be separated from each other. That is, the first portions 2321 of the second semiconductor sublayers 232 of transistors in the same column may be spaced apart along the second direction Y.

[0119] In some embodiments, the bit line 30 can be a strip electrode parallel to the substrate 1, a portion of the strip electrode can be the second electrode 52 of the transistor, and the side wall of the strip electrode is connected to the second portion 2322 of the second semiconductor sublayer 232, or, the bit line 30 can have a branch of an integral design, and the branch is connected to the second portion 2322 of the second semiconductor sublayer 232, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as approximately perpendicular, and the branch can be the second electrode 52 of the transistor.

[0120] The branches may be a plurality of branches on a sidewall of the bit line 30 , and each branch corresponds to the second portion 2322 of the second semiconductor sublayer 232 connected to a transistor.

[0121] In some embodiments, the transistor may further include a gate insulating layer 24 disposed between the semiconductor layer 23 and the gate electrode 26, the gate insulating layer 24 surrounding the gate electrode 26, the first semiconductor sublayer 231 surrounding the gate insulating layer 24, the gate insulating layer 24 isolating the semiconductor layer 23 and the gate electrode 26, and the gate insulating layers 24 of multiple transistors at the same position on different layers can be connected to form an integrated structure. The solution provided in this embodiment can form the gate insulating layers 24 of multiple transistors at one time, which can simplify the process. However, the embodiments of the present disclosure are not limited to this, and the gate insulating layers 24 of multiple transistors at the same position on different layers can be spaced apart, for example, physically disconnected.

[0122] In some embodiments, the first semiconductor sublayer 231, the gate insulating layer 24, and the gate electrode 26 may be disposed in a hole, that is, the semiconductor device may further include: an insulating layer and a conductive layer alternately distributed in a direction perpendicular to the substrate 1; a first hole K1 penetrating the insulating layer and the conductive layer; the conductive layer including a first electrode 51 and a second electrode 52 of the transistor, the first electrode 51 being connected to the first portion 2321, and the second electrode 52 being connected to the second portion 2322;

[0123] The first hole K1 is sequentially arranged from the outside to the inside with the first semiconductor sublayer 231, the gate insulation layer 24 surrounding the gate electrode 26, and the gate electrode 26. Multiple gate electrodes 26 of multiple transistors at the same position on different layers fill the first hole K1. The first hole K1 contains the first semiconductor sublayers 231 of multiple transistors stacked perpendicular to the substrate.

[0124] In some embodiments, the orthographic projection of the first hole K1 on the substrate 1 may be a square, but the embodiments of the present disclosure are not limited thereto. The orthographic projection of the first hole K1 on the substrate 1 may be other shapes, such as a circle.

[0125] In some embodiments, the first hole K1 may include a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, wherein the orthographic projection of the first sub-hole on the substrate 1 falls within the orthographic projection of the second sub-hole on the substrate 1. The solution provided in this embodiment, by providing first and second sub-holes of different aperture sizes, allows etching to be performed within the first hole, disconnecting the first semiconductor layers 231 of transistors in different layers. However, the disclosed embodiments are not limited thereto; the orthographic projection of the second sub-hole on the substrate 1 may fall within the orthographic projection of the first sub-hole on the substrate 1, thereby enabling etching outside the hole to disconnect the first semiconductor layers 231 of transistors in different layers.

[0126] In some embodiments, when the orthographic projection of the first sub-hole onto the substrate 1 falls within the orthographic projection of the second sub-hole onto the substrate 1, the second sub-hole has a first groove V1 along a direction parallel to the substrate 1 relative to the first sub-hole, and the first semiconductor sub-layer 231 can be disposed within the first groove V1, and the first semiconductor sub-layer 231 can fill the first groove V1. However, the disclosed embodiments are not limited thereto, and the first semiconductor sub-layer 231 may not completely fill the first groove V1. For example, the first semiconductor sub-layer 231 may cover the inner wall of the first groove V1, and the gate insulating layer 24 and the gate electrode 26 may extend into the first groove V1.

[0127] In some embodiments, the first electrode 51 is connected to the first portion 2321 and is disposed on a side of the first portion 2321 facing away from the gate electrode 26. The first electrode 51 can have various shapes. For example, the conductive layer can be formed with a groove having an opening facing away from the gate electrode 26, and the first electrode 51 can cover the inner wall of the groove.

[0128] For another example, the first electrode 51 and the first capacitor electrode 41 can be reused, that is, they have the same structure. In order to increase the capacitance of the capacitor and increase the area of ​​the first capacitor electrode 41, a second hole K2 can be provided through the conductive layer and the insulating layer, and the first capacitor electrode 41 can be provided on the inner wall of the second hole K2. In some embodiments, as shown in Figures 1A, 1B, and 1C, the semiconductor device may further include:

[0129] A second hole K2 passes through the insulating layer and the conductive layer; the second hole K2 includes a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, and the fourth sub-hole has a third groove V3 extending in the horizontal direction relative to the third sub-hole.

[0130] In some embodiments, the semiconductor device may further include: a plurality of capacitors, each capacitor including a first capacitor electrode 41 and a second capacitor electrode 42 , wherein the first electrode 51 and the first capacitor electrode 41 are multiplexed.

[0131] In some embodiments, the second capacitor electrode 42 may include a first sub-electrode 421 ;

[0132] The first capacitor electrode 41 surrounding the first sub-electrode 421 , the first dielectric layer 431 surrounding the first sub-electrode 421 , and the first sub-electrode 421 are sequentially distributed in the second hole K2 from outside to inside.

[0133] In some embodiments, the first capacitor electrode 41 is distributed on the inner wall of the third groove V3 and does not completely fill the third groove V3. The first sub-electrode 421 extends in a direction perpendicular to the substrate 1 and has an extension portion extending into the third groove V3.

[0134] The first electrodes 51 of transistors at the same position in different layers are arranged with intervals therebetween.

[0135] In some embodiments, the second capacitor electrode 42 may further include a second sub-electrode 422. The second sub-electrode 422 may be distributed on the side of the first capacitor electrode 41 facing away from the substrate 1, the side facing the substrate 1, and the side facing away from the second semiconductor sublayer 232. A second dielectric layer 432 is provided between the second sub-electrode 422 and the first capacitor electrode 41. The first dielectric layer 431 and the second dielectric layer 432 together constitute the dielectric layer 43 of the capacitor. The solution provided in this embodiment provides electrodes on both the inside and outside of the first capacitor electrode 41 as the second capacitor electrode 42, which can maximize the plate area of ​​the capacitor and increase the capacitance value, while the plane size occupied by the capacitor remains basically unchanged. The first sub-electrode 421 and the second sub-electrode 422 can be connected on the side of the multiple memory cell arrays away from the substrate 1.

[0136] In some embodiments, the first sub-electrodes 421 of capacitors connected to transistors at the same position in different layers may be connected to form an integrated structure.

[0137] In some embodiments, the second sub-electrodes 422 of capacitors connected to transistors at the same position in different layers may be connected to form an integrated structure.

[0138] In some embodiments, every two columns of memory cells on the same layer can be considered a group, and the second sub-electrodes 422 of the capacitors connected to the transistors in the same group can be connected to form an integrated structure. That is, the second sub-electrodes 422 of the capacitors connected to the transistors in adjacent columns on the same layer (two columns in the same group) can be connected to form an integrated structure.

[0139] The technical solution of this embodiment will be further illustrated below using the manufacturing process of the semiconductor device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can be achieved using known coating processes; and etching can be achieved using known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film of a certain material formed on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, the "thin film" before patterning is referred to as a "thin film" and the "layer" after patterning is referred to as a "layer." The "layer" after patterning or photolithography contains at least one "pattern."

[0140] In some embodiments, the manufacturing process of the semiconductor device may include:

[0141] 101) forming a stacked structure;

[0142] The forming of the stack structure may include: providing a substrate 1, and alternately depositing a first semiconductor thin film and a sacrificial layer thin film on the substrate 1 to form a stack structure including a plurality of alternately arranged second semiconductor structure layers 232a and sacrificial layers 10;

[0143] A hard mask film is deposited to form a hard mask layer 9. At this point, the stacked structure includes a plurality of alternating second semiconductor structure layers 232a and sacrificial layers 10, as well as a hard mask layer 9 disposed on the side of the topmost sacrificial layer 10 facing away from the substrate 1, with the hard mask layer 9 covering the sacrificial layer 10, as shown in Figures 2A and 2B. Figure 2A is a top view of the stacked structure after formation, provided in some embodiments, and Figure 2B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 2A. The AA' direction may be parallel to the first direction X.

[0144] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0145] In some embodiments, the first semiconductor thin film may be a heavily doped semiconductor film layer, and the second semiconductor structure layer 232 a may subsequently form a second semiconductor sub-layer 232 .

[0146] In some embodiments, the sacrificial layer can be made of a semiconductor material, such as SiGe. The use of a semiconductor material facilitates epitaxial growth of the first semiconductor film. The sacrificial layer will subsequently be replaced with an insulating film.

[0147] In some embodiments, the hard mask layer 9 includes but is not limited to at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0148] The stacked structure shown in FIG2B includes three second semiconductor structure layers 232 a and three sacrificial layers 10 , which is only an example. In other embodiments, the stacked structure may include more or fewer second semiconductor structure layers 232 a and sacrificial layers 10 that are alternately arranged.

[0149] 102) forming a first trench T1 and a first insulating layer 11;

[0150] Etching the plurality of stacked structures to form a plurality of first trenches T1 penetrating the plurality of stacked structures; the first trenches T1 extend along a first direction X, the plurality of first trenches T1 are spaced apart along the first direction X and the second direction Y, and a memory cell region is defined between adjacent first trenches T1 along the second direction Y. The memory cell region may include a transistor region and a capacitor region; the transistor region and the capacitor region may be arranged along the first direction X;

[0151] A first insulating film is deposited in each first trench T1 and polished to form a first insulating layer 11 filling the first trench T1. The first insulating layer 11 can be flush with the hard mask layer 9. As shown in Figures 3A and 3B, Figure 3A is a top view of the first trench T1 and the first insulating layer 11 after formation, according to some embodiments, and Figure 3B is a cross-sectional view perpendicular to the substrate 1 along the CC' direction in Figure 3A. The CC' direction can be parallel to the first direction X. The first insulating layer 11 can isolate multiple memory cells formed subsequently.

[0152] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The subsequent second to fourth insulating films are similar and will not be described in detail.

[0153] 103) forming a first hole K1;

[0154] The stacked structure is etched from the top to the bottom using dry etching in the transistor region defined by the adjacent first trenches T1 along the second direction Y (etching stops on the substrate 1), forming a first hole K1. At this time, the second sub-hole K12 of the first hole K1 in the second semiconductor structure layer 232a and the first sub-hole K11 in the sacrificial layer 10 have the same aperture, as shown in Figures 4A and 4B, where Figure 4A is a top view of the first hole K1 after formation provided in some embodiments, and Figure 4B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 4A. The sidewalls of the first hole K1 do not expose the first insulating layer 11.

[0155] 104) forming a second insulating layer 12;

[0156] Etching away the sacrificial layer 10 through the first hole K1;

[0157] A second insulating film is deposited on the substrate 1 having the aforementioned structure, forming a second insulating layer 12 that fills the first hole K1 and the area where the sacrificial layer 10 was originally located, as shown in Figures 5A and 5B. Figure 5A is a top view of the second insulating layer 12 after formation, as provided in some embodiments, and Figure 5B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 5A. The second insulating layer 12 can isolate memory cells on different layers. In this step, the sacrificial layer 10 is replaced with the second insulating layer 12.

[0158] 105) exposing the first hole K1;

[0159] The second insulating layer 12 in the first hole K1 is etched away to expose the first hole K1, as shown in Figures 6A and 6B, wherein Figure 6A is a top view after exposing the first hole K1 provided in some embodiments, and Figure 6B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 6A.

[0160] 106) forming a first groove V1;

[0161] Based on the lateral etching (i.e., in a direction parallel to the substrate 1) of the second semiconductor structure layer 232a by the first hole K1, the aperture of the second sub-hole K12 of the first hole K1 located in the second semiconductor structure layer 232a is enlarged, so that the orthographic projection of the first sub-hole K11 of the first hole K1 located in the second insulating layer 12 on the substrate 1 falls within the orthographic projection of the second sub-hole K12 on the substrate 1. At this time, the second sub-hole K12 has a transverse first groove V1 relative to the first sub-hole K11, as shown in Figures 7A and 7B, wherein Figure 7A is a top view after the first groove V1 is formed provided in some embodiments, and Figure 7B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 7A.

[0162] Referring to the area indicated by the dotted line surrounding the first hole K1 in FIG7A , that is, the area where the second sub-hole K12 is located, of the four side walls of the second sub-hole K12, two side walls are the second semiconductor structure layer 232 a, and the other two side walls are the first insulating layer 11, that is, when transversely etching along the second direction Y, the entire second semiconductor structure layer 232 a in this direction is etched away to expose the first insulating layer 11, and when transversely etching along the first direction X, only part of the second semiconductor structure layer 232 a in this direction is etched away.

[0163] 107) forming a first semiconductor structure layer 231a;

[0164] A second semiconductor film is deposited on the substrate 1 forming the aforementioned structure to form a first semiconductor structure layer 231a filling the first hole K1, as shown in Figures 8A and 8B, wherein Figure 8A is a top view after the first semiconductor structure layer 231a is formed provided in some embodiments, and Figure 8B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 8A.

[0165] The first semiconductor structure layer 231 a may be made of a lightly doped or undoped semiconductor material.

[0166] In some embodiments, depositing the second semiconductor film may be epitaxially growing the second semiconductor film.

[0167] In an exemplary embodiment of the present disclosure, the material of the second semiconductor film may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0168] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0169] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0170] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0171] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0172] 108) forming word lines 40 and gate insulating layer 24;

[0173] The first semiconductor structure layer 231a is removed from the first hole K1 except for the area where the first groove V1 is located. That is, only the first semiconductor structure layer 231a located in the first groove V1 is retained. The retained first semiconductor structure layer 231a is the first semiconductor sub-layer 231 of the multiple transistors. The first semiconductor sub-layer 231 is only located in the first groove V1; the first semiconductor sub-layer 231 fills the first groove V1.

[0174] A gate insulating film and a gate electrode film are sequentially deposited within the first hole K1 to form a gate insulating layer 24 and a word line 40. The word line 40 fills the first hole K1, as shown in Figures 9A and 9B. Figure 9A is a top view of the word line 40 and gate insulating layer 24 after formation, as provided in some embodiments, and Figure 9B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 9A. The first hole K1 in this case refers to the first hole K1 in which the first semiconductor sublayer 231 is formed. That is, the gate insulating layer 24 and the word line 40 are formed in the first hole K1 excluding the first groove V1.

[0175] The gate electrodes 26 of transistors at the same position in different layers are part of the word line 40. The gate insulating layer 24 covers the bottom wall and side walls of the first hole K1.

[0176] In some embodiments, the material of the gate insulating layer 24 may include one or more layers of a high-k dielectric material. In some embodiments, the gate insulating layer 24 may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like. For example, the gate insulating layer 24 may include, but is not limited to, at least one of the following high-k materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like.

[0177] In some embodiments, the gate electrode film may be made of one or more of the following different types of materials:

[0178] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0179] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0180] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0181] 109) forming a second trench T2;

[0182] The stacked structure is etched from the top layer to the bottom layer to form a second trench T2 that penetrates the stacked structure. The second trench T2 extends along the second direction Y. Adjacent second trenches T2 define a group of memory cells, each group of memory cells including two columns of memory cells, as shown in Figures 10A and 10B. Figure 10A is a top view of the second trench T2 after formation, provided in some embodiments, and Figure 10B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 10A. The second trench T2 penetrates the stacked structure in the second direction Y. Figures 10A and 10B only illustrate the structure on one side of the second trench T2, and do not illustrate the structure on the other side of the second trench T2.

[0183] 110) forming a second groove V2;

[0184] The second semiconductor structure layer 232a is laterally etched based on the second trench T2, but the second semiconductor structure layer 232a is not completely etched away, that is, the first semiconductor sublayer 231 is not exposed, forming a second groove V2. The second groove V2 extends along the second direction Y, as shown in Figures 11A and 11B, wherein Figure 11A is a top view after the second groove V2 is formed, provided in some embodiments, and Figure 11B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 11A. At this time, the second semiconductor structure layer 232a located on the side of the first semiconductor sublayer 231 facing the second groove V2 serves as the second portion 2322 of the second semiconductor sublayer 232. The second groove V2 penetrates the stacked structure along the second direction Y.

[0185] 111) forming a bit line layer 30a;

[0186] Performing a silicidation process on the second portion 2322 of the second semiconductor sublayer 232 to form a metal silicide, so as to reduce the contact resistance between the second portion 2322 of the second semiconductor sublayer 232 and the bit line layer 30a to be formed;

[0187] A first conductive film is deposited to form a bit line layer 30a, and the bit line layer 30a fills the second trench T2 and the second groove V2; as shown in Figures 12A and 12B, wherein Figure 12A is a top view after the bit line layer 30a is formed provided in some embodiments, and Figure 12B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 12A.

[0188] In some embodiments, the first conductive film may be made of the following conductive materials:

[0189] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; or it may be a metal alloy containing the aforementioned metals;

[0190] Alternatively, it may be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0191] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0192] The subsequent second conductive film, third conductive film, fourth conductive film and first conductive film are made of similar materials and are not described in detail.

[0193] 112) forming a bit line 30 and a third insulating layer 13;

[0194] Etching and removing the bit line layer 30a in the second trench T2, and retaining the bit line layer 30a in the plurality of second grooves V2. At this time, the bit line layer 30a is divided into a plurality of bit lines 30 located in different layers, and the plurality of bit lines 30 are disconnected from each other;

[0195] A third insulating film is deposited to form a third insulating layer 13 filling the second trench T2. The third insulating layer 13 separates different groups of memory cells, as shown in FIG13A and FIG13B , wherein FIG13A is a top view after forming the bit line 30 and the third insulating layer 13 provided in some embodiments, and FIG13B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in FIG13A .

[0196] 113) forming a second hole K2;

[0197] In the capacitor region defined by the adjacent first trenches T1 along the second direction Y, the stacked structure is etched from the top layer to the bottom layer using dry etching (etching stops on the substrate 1), forming a second hole K2. At this time, the aperture of the fourth sub-hole K22 of the second semiconductor structure layer 232a and the third sub-hole K21 of the second insulating layer 12 of the second hole K2 are consistent, as shown in Figures 14A and 14B, where Figure 14A is a top view of the second hole K2 after formation provided in some embodiments, and Figure 14B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 14A. The second hole K2 and the first hole K1 are spaced apart along the first direction X. The sidewalls of the second hole K2 do not expose the first insulating layer 11.

[0198] 114) forming a third groove V3;

[0199] Based on the transverse etching of the second hole K2, the second semiconductor structure layer 232a is enlarged, and the aperture of the fourth sub-hole K22 of the second hole K2 located in the second semiconductor structure layer 232a is enlarged, so that the orthographic projection of the third sub-hole K21 of the second hole K2 located in the second insulating layer 12 on the substrate 1 falls within the orthographic projection of the fourth sub-hole K22 on the substrate 1. At this time, the fourth sub-hole K22 has a transverse third groove V3 relative to the third sub-hole K21, as shown in Figures 15A and 15B, wherein Figure 15A is a top view after the third groove V3 is formed provided in some embodiments, and Figure 15B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 15A.

[0200] Referring to the area indicated by the dotted line surrounding the second hole K2 in FIG15A , that is, the area where the fourth sub-hole K22 is located, of the four side walls of the fourth sub-hole K22, two side walls are the second semiconductor structure layer 232a, and two side walls are the first insulating layer 11, that is, when horizontally etching along the second direction Y, the entire second semiconductor structure layer 232a in this direction is etched away to expose the first insulating layer 11, and when horizontally etching along the first direction X, part of the second semiconductor structure layer 232a is etched away. At this time, the second semiconductor structure layer 232a connected to the first semiconductor sublayer 231 serves as the first part 2321 of the second semiconductor sublayer 232.

[0201] 115) forming a first electrode layer 51a and a fourth insulating layer 14;

[0202] A second conductive film and a fourth insulating film are sequentially deposited in the second hole K2 to form a first electrode layer 51a and a fourth insulating layer 14; the fourth insulating layer 14 fills the second hole K2 (here the second hole K2 includes a third groove V3), as shown in Figures 16A and 16B, wherein Figure 16A is a top view after the first electrode layer 51a and the fourth insulating layer 14 are formed provided in some embodiments, and Figure 16B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 16A.

[0203] 116) forming a first electrode 51;

[0204] The first electrode layer 51a and the fourth insulating layer 14 are etched away from the second hole K2 except for the area where the third groove V3 is located. That is, only the first electrode layer 51a and the fourth insulating layer 14 located in the multiple third grooves V3 remain. The retained first electrode layer 51a is a plurality of first electrodes 51 disconnected from each other, and the first electrode 51 is located only in the third groove V3. The first electrode 51 covers the inner wall of the third groove V3, including the top wall of the third groove V3 parallel to the substrate 1 (the inner wall of the third groove V3 facing away from the substrate 1) and the bottom wall (the inner wall of the third groove V3 facing the substrate 1), as well as the four sidewalls perpendicular to the substrate 1, as shown in Figures 17A and 17B. Figure 17A is a top view of the first electrode 51 after formation, provided in some embodiments, and Figure 17B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 17A. This first electrode 51 also serves as the first capacitive electrode 41 of the capacitor.

[0205] 117) forming a first sub-electrode 421 and a first dielectric layer 431;

[0206] The fourth insulating layer 14 in the third groove V3 is removed by etching. At this time, the entire fourth insulating layer 14 is removed, and the inner wall of the first electrode 51 facing away from the word line 40 is exposed.

[0207] A first dielectric film and a third conductive film are sequentially deposited in the second hole K2 to form a first dielectric layer 431 and a first sub-electrode 421; the first sub-electrode 421 fills the second hole K2, and the first sub-electrode 421 extends into the third groove V3, as shown in Figures 18A and 18B, wherein Figure 18A is a top view after the first sub-electrode 421 and the first dielectric layer 431 are formed provided in some embodiments, and Figure 18B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 18A.

[0208] In some embodiments, the first dielectric film may be a High-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like. For example, it may include, but is not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like. The subsequent second dielectric film is similar to the first dielectric film and will not be described in detail.

[0209] 118) forming a third trench T3;

[0210] The stack structure is etched from the top layer to the bottom layer to form a third trench T3 penetrating the stack structure. The third trench T3 extends along the second direction Y and is located between two adjacent columns of memory cells in the same group. The third trench T3 penetrating the stack structure along the second direction Y is:

[0211] Based on the third trench T3, the second insulating layer 12 is laterally etched, and the second insulating layer 12 is etched along the first direction X to expose the top wall (the surface facing the substrate 1) and the bottom wall (the surface facing away from the substrate 1) of the first capacitor electrode 41. In addition, the second semiconductor structure layer 232a is etched to expose the side wall of the first capacitor electrode 41 facing the third trench T3, so that the subsequently formed second sub-electrode 422 can surround the top wall, bottom wall, and side wall of the first capacitor electrode 41, thereby maximizing the electrode area of ​​the capacitor. When the second insulating layer 12 is laterally etched, a portion of the second insulating layer 12 is retained, and the gate insulating layer 24 is not exposed; as shown in Figures 19A and 19B, where Figure 19A is a top view after the third trench T3 is formed, provided in some embodiments, and Figure 19B is a cross-sectional view perpendicular to the substrate 1 along the AA' direction in Figure 19A.

[0212] 119) forming a second sub-electrode 422 and a second dielectric layer 432;

[0213] A second dielectric film and a fourth conductive film are sequentially deposited within the third trench T3 to form a second dielectric layer 432 and a second sub-electrode 422. The second sub-electrode 422 fills the third trench T3, as shown in Figures 1A, 1B, and 1C. As can be seen, the second sub-electrodes 422 of two columns of memory cells within the same group are connected to form a single integrated structure. The second sub-electrode 422 and the first sub-electrode 421 constitute the second capacitive electrode 42 of the capacitor.

[0214] In the above embodiments, the transistor includes one gate electrode. In some embodiments, the transistor may include two gate electrodes. Figure 20A is a top view of a semiconductor device provided in some other embodiments, Figure 20B is a cross-sectional view along the A1A1' direction in Figure 20A; Figure 20C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 20A; and Figure 20D is a cross-sectional view parallel to the substrate 1 along the DD' direction in Figure 20C. As shown in Figures 20A, 20B, 20C and 20D, an embodiment of the present disclosure provides a semiconductor device, in which a transistor may include a dual gate electrode, that is, the transistor may include a first gate electrode 26a extending in a direction perpendicular to the substrate 1 and a first gate insulation layer 24a surrounding the first gate electrode 26a, as well as a second gate electrode 26b extending in a direction perpendicular to the substrate 1 and a second gate insulation layer 24b surrounding the second gate electrode 26b, the first gate electrode 26a and the second gate electrode 26b may be spaced apart along the second direction Y, and multiple first gate electrodes 26a of multiple transistors at the same position in different layers are connected to form an integrated structure extending in a direction perpendicular to the substrate 1, that is, forming a first word line 40a, and multiple second gate electrodes 26b of multiple transistors at the same position in different layers are connected to form an integrated structure extending in a direction perpendicular to the substrate 1, that is, forming a second word line 40b. The transistor may further include a first semiconductor sublayer 231 and a second semiconductor sublayer 232. The first semiconductor sublayer 231 partially surrounds the first gate electrode 26a, and the first semiconductor sublayer 231 partially surrounds the second gate electrode 26b. The second semiconductor sublayer 232 includes a first portion 2321 and a second portion 2322 spaced apart on the sidewalls of the first semiconductor sublayer 231 facing away from the first gate electrode 26a and the second gate electrode 26b. A memory array composed of transistors with dual gate electrodes can select a vertical column of memory cells (i.e., a group of memory cells at the same location on different layers) by activating a first word line 40a and a second word line 40b. This eliminates the need for gate transistors for word lines, allowing selection of a vertical column of memory cells. Compared to memory arrays composed of transistors with only a single gate electrode, which require gate transistors, the solution provided by this embodiment eliminates the need for additional process steps for manufacturing gate transistors, reduces the number of word line drivers, and maintains the same number as the number of stacked layers increases. Furthermore, the control logic of the driver circuit is simple.

[0215] In some embodiments, the first semiconductor sublayer 231 may have an H-shaped cross-section on a plane parallel to the substrate 1. The H-shaped structure may include a first strip structure extending along a first direction X and two second strip structures extending along a second direction Y at either end of the first strip structure. The first gate electrode 26 a and the second gate electrode 26 b are located on either side of the first strip structure, respectively. The first portion 2321 may be connected to the sidewall of one of the second strip structures on a side facing away from the first gate electrode 26 a, and the second portion 2322 may be connected to the sidewall of another of the second strip structures on a side facing away from the first gate electrode 26 a.

[0216] In some embodiments, multiple first gate insulation layers 24a of multiple transistors at the same position in different layers can be connected to form an integrated structure extending in a direction perpendicular to the substrate 1, and multiple second gate insulation layers 24b of multiple transistors at the same position in different layers can be connected to form an integrated structure extending in a direction perpendicular to the substrate 1.

[0217] The first gate electrode 26a and the second gate electrode 26b can be disposed in different holes, respectively. In some embodiments, the semiconductor device may further include: an insulating layer and a conductive layer alternately distributed along a direction perpendicular to the substrate 1; a third hole K3 and a fourth hole K4 penetrating the insulating layer and the conductive layer; the conductive layer including the first electrode 51 and the second electrode 52 of the transistor, the first electrode 51 connecting to the first portion 2321, and the second electrode 52 connecting to the second portion 2322; the third hole K3 and the fourth hole K4 communicating with each other in the conductive layer;

[0218] The first semiconductor sublayer 231 , the first gate insulating layer 24 a surrounding the first gate electrode 26 a , and the first gate electrode 26 a are sequentially distributed in the third hole K3 from the outside to the inside;

[0219] The first semiconductor sublayer 231 , the second gate insulating layer 24 b surrounding the second gate electrode 26 b , and the second gate electrode 26 b are sequentially distributed in the fourth hole K4 from the outside to the inside.

[0220] In some embodiments, the third hole K3 may include a fifth sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and the orthographic projection of the fifth sub-hole on the substrate 1 falls within the orthographic projection of the sixth sub-hole on the substrate 1:

[0221] The fourth hole K4 may include a seventh sub-hole located in the insulating layer and the sixth sub-hole located in the conductive layer, wherein the orthographic projection of the seventh sub-hole on the substrate 1 falls within the orthographic projection of the sixth sub-hole on the substrate 1. That is, the third hole K3 and the fourth hole K4 share the sixth sub-hole.

[0222] The structures of the first electrode 51, the second electrode 52, and the connected capacitor of the dual-gate transistor can refer to the contents described in the aforementioned embodiment and the subsequent embodiment of the manufacturing process of the dual-gate semiconductor device, and will not be repeated here.

[0223] In some embodiments, the manufacturing process of the dual-gate semiconductor device may include:

[0224] 201) to 202), same as 101) to 102), forming a stacked structure including a first trench T1 and a first insulating layer 11;

[0225] 203) forming a third hole K3 and a fourth hole K4;

[0226] In the transistor region defined by the adjacent first trench T1, the stacked structure is etched from the top layer to the bottom layer using dry etching (etching stops on the substrate 1), forming a third hole K3 and a third hole K4. At this time, the aperture of the sixth sub-hole K32 of the third hole K3 in the second semiconductor structure layer 232a is consistent with the aperture of the fifth sub-hole K31 in the sacrificial layer 10, and the aperture of the eighth sub-hole of the fourth hole K4 in the second semiconductor structure layer 232a is consistent with the aperture of the seventh sub-hole in the sacrificial layer 10, as shown in Figures 21A and 21B. Figure 21A is a top view of the third hole K3 and the fourth hole K4 after formation, provided in some embodiments, and Figure 21B is a cross-sectional view perpendicular to the substrate 1 along the direction A1A1' in Figure 21A. One sidewall of the third hole K3 is the first insulating layer 11, and one sidewall of the fourth hole K4 is the first insulating layer 11. That is, the third hole K3 and the fourth hole K4 are respectively adjacent to two first insulating layers 11 adjacent to each other along the second direction Y.

[0227] 204) forming a second insulating layer 12;

[0228] The sacrificial layer 10 is removed by etching based on the third hole K3 and the fourth hole K4;

[0229] A second insulating film is deposited on the substrate 1 having the aforementioned structure to form a second insulating layer 12 that fills the third and fourth holes K3 and K4 and the area where the sacrificial layer 10 was originally located, as shown in Figures 22A and 22B. Figure 22A is a top view of the second insulating layer 12 after formation, provided in some embodiments, and Figure 22B is a cross-sectional view perpendicular to the substrate 1 along the direction A1A1' in Figure 22A. The second insulating layer 12 can isolate memory cells on different layers.

[0230] 205) exposing the third hole K3 and the fourth hole K4;

[0231] The second insulating layer 12 in the third hole K3 and the fourth hole K4 is etched away to expose the third hole K3 and the fourth hole K4, as shown in Figures 23A and 23B, wherein Figure 23A is a top view after exposing the third hole K3 and the fourth hole K4 provided in some embodiments, and Figure 23B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 23A.

[0232] 206) forming a fourth groove V4;

[0233] The second semiconductor structure layer 232a is laterally etched in the third hole K3 and the fourth hole K4, and the apertures of the sub-holes of the third hole K3 and the fourth hole K4 located in the second semiconductor structure layer 232a are enlarged, so that the orthographic projection of the fifth sub-hole K31 of the third hole K3 located in the second insulating layer 12 on the substrate 1 falls within the orthographic projection of the sixth sub-hole K32 on the substrate 1, and the orthographic projection of the seventh sub-hole K41 of the fourth hole K4 located in the second insulating layer 12 on the substrate 1 falls within the orthographic projection of the eighth sub-hole K42 on the substrate 1. At this time, the sixth sub-hole K32 and the eighth sub-hole K42 overlap, and the sixth sub-hole K32 has an H-shaped fourth groove V4 relative to the fifth sub-hole K31 and the seventh sub-hole K41, as shown in Figures 24A and 24B, wherein Figure 24A is a top view after the fourth groove V4 is formed provided in some embodiments, and Figure 24B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 24A.

[0234] Referring to the area shown by the dotted line in Figure 24A, that is, the area where the sixth sub-hole K32 or the eighth sub-hole K42 is located, it can be seen that when horizontal etching is performed along the second direction Y, the entire second semiconductor structure layer 232a in this direction is etched away, exposing the first insulating layer 11, and when horizontal etching is performed along the first direction X, part of the second semiconductor structure layer 232a in this direction is etched away, and part of the second semiconductor structure layer 232a is retained.

[0235] 207) forming a first semiconductor structure layer 231a;

[0236] A second semiconductor film is deposited on the substrate 1 having the aforementioned structure to form a first semiconductor structure layer 231a that fills the third hole K3 and the fourth hole K4, as shown in Figures 25A and 25B. Figure 25A is a top view of the first semiconductor structure layer 231a after formation, provided in some embodiments, and Figure 25B is a cross-sectional view perpendicular to the substrate 1 along the direction A1A1' in Figure 25A. Depositing the second semiconductor film here may be epitaxial growth on the second semiconductor structure layer 232a to form the second semiconductor film.

[0237] 208) forming a first word line 40a and a first gate insulating layer 24a, a second word line 40b and a second gate insulating layer 24b;

[0238] The first semiconductor structure layer 231a is removed from the third hole K3 and the fourth hole K4 except for the area where the fourth groove V4 is located. That is, only the first semiconductor structure layer 231a located in the plurality of fourth grooves V4 is retained. The retained first semiconductor structure layer 231a is the first semiconductor sub-layer 231 of the plurality of transistors. The first semiconductor sub-layer 231 is located only in the fourth groove V4; the first semiconductor sub-layer 231 fills the fourth groove V4.

[0239] A gate insulating film and a gate electrode film are sequentially deposited in the third hole K3 to form a first gate insulating layer 24a and a first word line 40a, and the first word line 40a fills the third hole K3; a gate insulating film and a gate electrode film are sequentially deposited in the fourth hole K4 to form a second gate insulating layer 24b and a second word line 40b, and the second word line 40b fills the fourth hole K4, as shown in Figures 26A and 26B, wherein Figure 26A is a top view after the first word line 40a, the first gate insulating layer 24a, the second word line 40b and the second gate insulating layer 24b are formed, provided in some embodiments, and Figure 26B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 26A.

[0240] The first gate electrode 26a of a transistor at the same location on a different layer is part of the first word line 40a. The first gate insulating layer 24a covers the bottom and sidewalls of the third hole K3. The second gate electrode 26b of a transistor at the same location on a different layer is part of the second word line 40b. The second gate insulating layer 24a covers the bottom and sidewalls of the fourth hole K4.

[0241] 209) forming a second trench T2;

[0242] The stacked structure is etched from the top layer to the bottom layer to form second trenches T2 that penetrate the stacked structure. The second trenches T2 extend along the second direction Y. Adjacent second trenches T2 define a group of memory cells, each group of memory cells including two columns of memory cells, as shown in FIG27A and FIG27B . FIG27A is a top view of the second trenches T2 after formation according to some embodiments, and FIG27B is a cross-sectional view perpendicular to the substrate 1 along the direction A1A1′ in FIG27A . The second trenches T2 penetrate the stacked structure in the second direction Y.

[0243] 210) forming a second groove V2;

[0244] The second semiconductor structure layer 232a is laterally etched based on the second trench T2, but the second semiconductor structure layer 232a is not completely etched away, that is, the first semiconductor sublayer 231 is not exposed, forming a second groove V2. The second groove V2 extends along the second direction Y and penetrates the stacked structure along the second direction Y, as shown in Figures 28A and 28B. Figure 28A is a top view of the second groove V2 after formation, provided in some embodiments, and Figure 28B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 28A. At this time, the second semiconductor structure layer 232a located on the side of the first semiconductor sublayer 231 facing the second groove V2 serves as the second portion 2322 of the second semiconductor sublayer 232.

[0245] 211) forming a bit line layer 30a:

[0246] Performing a silicidation process on the second portion 2322 of the second semiconductor sublayer 232 to form a metal silicide, so as to reduce the contact resistance between the second portion 2322 of the second semiconductor sublayer 232 and the bit line layer 30a to be formed;

[0247] A first conductive film is deposited to form a bit line layer 30a, and the bit line layer 30a fills the second trench T2 and the second groove V2; as shown in Figures 29A and 29B, wherein Figure 29A is a top view after the bit line layer 30a is formed provided in some embodiments, and Figure 29B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 29A.

[0248] 212) forming a bit line 30 and a third insulating layer 13;

[0249] Etching and removing the bit line layer 30 in the second trench T2, leaving the bit line layer 30a in the plurality of second grooves V2. At this time, the bit line layer 30a is divided into a plurality of bit lines 30 located in different layers, and the plurality of bit lines 30 are disconnected from each other.

[0250] A third insulating film is deposited to form a third insulating layer 13 filling the second trench T2. The third insulating layer 13 separates different groups of memory cells, as shown in FIG30A and FIG30B , wherein FIG30A is a top view after forming the bit line 30 and the third insulating layer 13 provided in some embodiments, and FIG30B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in FIG30A .

[0251] 213) forming a second hole K2;

[0252] In the capacitor region defined by the adjacent first trenches T1 along the second direction Y, the stacked structure is etched from the top layer to the bottom layer using dry etching (etching stops on the substrate 1), forming a second hole K2. At this time, the aperture of the fourth sub-hole K22 of the second semiconductor structure layer 232a and the third sub-hole K21 of the second insulating layer 12 of the second hole K2 are consistent, as shown in Figures 31A, 31B, and 31C. Figure 31A is a top view of the second hole K2 after formation, provided in some embodiments, Figure 31B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 31A, and Figure 31C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 31A. The second hole K2 and the third holes K3 and K4 are spaced apart along the first direction X.

[0253] 214) forming a third groove V3;

[0254] Based on the second hole K2, the second semiconductor structure layer 232a is laterally etched, and the aperture of the fourth sub-hole K22 of the second hole K2 located in the second semiconductor structure layer 232a is enlarged, so that the third sub-hole K21 of the second hole K2 located in the second insulating layer 12 has an orthographic projection on the substrate 1 that falls within the orthographic projection of the fourth sub-hole K22 on the substrate 1. At this time, the fourth hole K22 has a transverse third groove V3 relative to the third hole K21, as shown in Figures 32A, 32B and 32C, wherein Figure 32A is a top view after the third groove V3 is formed provided in some embodiments, Figure 32B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 32A, and Figure 32C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 32A.

[0255] 215) forming a first electrode layer 51a and a fourth insulating layer 14;

[0256] A second conductive film and a fourth insulating film are sequentially deposited in the second hole K2 to form a first electrode layer 51a and a fourth insulating layer 14; the fourth insulating layer 14 fills the second hole K2, as shown in Figures 33A, 33B and 33C, wherein Figure 33A is a top view after the first electrode layer 51a and the fourth insulating layer 14 are formed, provided in some embodiments, Figure 33B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 33A, and Figure 33C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 33A.

[0257] 216) forming a first electrode 51;

[0258] The first electrode layer 51a and the fourth insulating layer 14 except the area where the third groove V3 is located are etched away in the second hole K2, that is, only the first electrode layer 51a and the fourth insulating layer 14 located in the multiple third grooves V3 are retained, and the retained first electrode layer 51a is a plurality of first electrodes 51 disconnected from each other, and the first electrode 51 is only located in the third groove V3; the first electrode 51 covers the inner wall of the third groove V3, including the top wall of the third groove V3 parallel to the substrate 1 (the inner wall of the third groove V3 facing away from the substrate 1) and the bottom wall (the inner wall of the third groove V3 facing the substrate 1), as well as the four side walls perpendicular to the substrate 1, as shown in Figures 34A, 34B and 34C, wherein Figure 34A is a top view after the first electrode 51 is formed provided in some embodiments, Figure 34B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 34A, and Figure 34C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 34A. The first electrode 51 also serves as the first capacitance electrode 41 of the capacitor.

[0259] 217) forming a first sub-electrode 421 and a first dielectric layer 431;

[0260] The fourth insulating layer 14 in the third groove V3 is removed by etching. At this time, the entire fourth insulating layer 14 is removed, and the inner wall of the first electrode 51 facing away from the second semiconductor sublayer 232 is exposed.

[0261] A first dielectric film and a third conductive film are sequentially deposited in the second hole K2 to form a first dielectric layer 431 and a first sub-electrode 421; the first sub-electrode 421 fills the second hole K2, and the first sub-electrode 421 extends into the third groove V3, as shown in Figures 35A, 35B and 35C, wherein Figure 35A is a top view after the first sub-electrode 421 and the first dielectric layer 431 are formed provided in some embodiments, Figure 35B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 35A, and Figure 35C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 35A.

[0262] 218) forming a third trench T3;

[0263] Etching the stack structure from the top layer to the bottom layer to form a third trench T3 penetrating the stack structure, wherein the third trench T3 extends along the second direction Y and is located between two adjacent columns of memory cells in the same group; the third trench T3 penetrating the stack structure along the second direction Y;

[0264] Based on the third trench T3, the second insulating layer 12 is laterally etched, and the second insulating layer 12 is etched along the first direction X to expose the top wall (the surface facing the substrate 1) and the bottom wall (the surface facing away from the substrate 1) of the first capacitor electrode 41, and the second semiconductor structure layer 232a is etched to expose the side wall of the first capacitor electrode 41 facing the third trench T3, so that the subsequently formed second sub-electrode 422 can surround the top wall, bottom wall and side wall of the first capacitor electrode 41, thereby maximizing the electrode area of ​​the capacitor. When the second insulating layer 12 is laterally etched, a portion of the second insulating layer 12 is retained and the gate insulating layer 24 is not exposed; as shown in Figures 36A, 36B, 36C and 36D, wherein Figure 36A is a top view after the third trench T3 provided in some embodiments, Figure 36B is a cross-sectional view perpendicular to the substrate 1 along the A1A1' direction in Figure 36A, Figure 36C is a cross-sectional view perpendicular to the substrate 1 along the BB' direction in Figure 36A, and Figure 36D is a cross-sectional view parallel to the substrate 1 along the DD' direction in Figure 36C.

[0265] 219) forming a second electrode 422 and a second dielectric layer 432;

[0266] A second dielectric film and a fourth conductive film are sequentially deposited within the third trench T3 to form a second dielectric layer 432 and a second sub-electrode 422. The second sub-electrode 422 fills the third trench T3, as shown in Figures 20A, 20B, 20C, and 20D. It can be seen that the second sub-electrodes 422 of two columns of memory cells within the same group are connected to form an integrated structure.

[0267] The present disclosure also provides an electronic device comprising the semiconductor device of the aforementioned embodiment, or a semiconductor device formed by the semiconductor device manufacturing method of the aforementioned embodiment. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include, for example, computer memory, and is not limited here.

[0268] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, comprising: a substrate, and at least one transistor disposed on the substrate; The transistor comprises a gate electrode and a semiconductor layer; The semiconductor layer includes a first semiconductor sublayer that at least partially surrounds the gate electrode and a second semiconductor sublayer that is arranged on a side of the first semiconductor sublayer away from the gate electrode, the doping concentration of the second semiconductor sublayer is greater than the doping concentration of the first semiconductor sublayer, and the second semiconductor sublayer includes a first part and a second part that are spaced apart on a surface of the first semiconductor sublayer away from the gate electrode.

2. The semiconductor device according to claim 1, wherein Along a direction perpendicular to the substrate, the gate electrodes of the plurality of transistors are connected to each other to form a word line perpendicular to the substrate, and the semiconductor layers of the plurality of transistors are arranged at intervals.

3. The semiconductor device according to claim 1, wherein The second semiconductor sublayer extends in a direction parallel to the substrate.

4. The semiconductor device according to claim 3, wherein: The first portion and the second portion are spaced apart along a first direction, the first portion extends along a second direction, the second portion extends along the second direction, and the first direction and the second direction intersect and are both parallel to the substrate.

5. The semiconductor device according to claim 4, wherein: The transistor includes only one gate electrode; along a plane parallel to the substrate, a cross section of the first semiconductor sublayer is a closed loop.

6. The semiconductor device according to claim 4, wherein: The transistor includes a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode are spaced apart along the second direction, a plurality of first gate electrodes of the transistors are interconnected to form an integrated structure extending along a direction perpendicular to the substrate, a plurality of second gate electrodes of the transistors are interconnected to form an integrated structure extending along a direction perpendicular to the substrate, the first semiconductor sublayer partially surrounds the first gate electrode, and the first semiconductor sublayer partially surrounds the second gate electrode.

7. The semiconductor device according to claim 5, wherein: The semiconductor device further comprises: An insulating layer and a conductive layer are alternately distributed along a direction perpendicular to the substrate; a first hole penetrates the insulating layer and the conductive layer; the conductive layer comprises a first electrode and a second electrode of the transistor, the first electrode is connected to the first part, and the second electrode is connected to the second part.

8. The semiconductor device according to claim 7, wherein: The first hole includes a first sub-hole located in the insulating layer and a second sub-hole located in the conductive layer, and an orthographic projection of the first sub-hole on the substrate falls within an orthographic projection of the second sub-hole on the substrate.

9. The semiconductor device according to claim 6, wherein: The semiconductor device further comprises: Insulating layers and conductive layers are alternately distributed along a direction perpendicular to the substrate; a third hole and a fourth hole penetrate the insulating layer and the conductive layer; and the third hole and the fourth hole are connected in the conductive layer.

10. The semiconductor device according to claim 9, wherein The first semiconductor sublayer, the first gate insulating layer, and the first gate electrode are sequentially distributed in the third hole from outside to inside; The first semiconductor sublayer, the second gate insulating layer, and the second gate electrode are sequentially distributed in the fourth hole from outside to inside.

11. The semiconductor device according to claim 9, wherein: The third hole includes a fifth sub-hole located in the insulating layer and a sixth sub-hole located in the conductive layer, and the orthographic projection of the fifth sub-hole on the substrate falls within the orthographic projection of the sixth sub-hole on the substrate; The fourth hole includes a seventh sub-hole located in the insulating layer and the sixth sub-hole located in the conductive layer, and an orthographic projection of the seventh sub-hole on the substrate falls within an orthographic projection of the sixth sub-hole on the substrate.

12. The semiconductor device according to claim 7 or 8, wherein: The semiconductor device also includes: a multi-layer memory cell array distributed along a direction perpendicular to the substrate, each layer of the memory cell array includes a plurality of rows and columns of memory cells distributed along a first direction and a second direction respectively, the memory cells include the transistors, and the second electrodes of the transistors in the same layer and in the same column distributed along the second direction are interconnected to form a bit line extending along the second direction.

13. The semiconductor device according to claim 12, wherein: The second parts of the transistors in the same column and in the same layer distributed along the second direction are connected to each other to form an integrated structure, and the first parts of the transistors in the same column and in the same layer distributed along the second direction are separated from each other.

14. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises: A second hole passes through the insulating layer and the conductive layer; the second hole includes a third sub-hole located in the insulating layer and a fourth sub-hole located in the conductive layer, and the fourth sub-hole has a groove extending in a horizontal direction relative to the third sub-hole.

15. The semiconductor device according to claim 14, wherein: The semiconductor device further includes: a plurality of capacitors, each capacitor including a first capacitor electrode and a second capacitor electrode, wherein the first electrode and the first capacitor electrode are reused.

16. The semiconductor device according to claim 15, wherein: The second capacitor electrode includes a first sub-electrode; the first capacitor electrode surrounding the first sub-electrode, a first dielectric layer surrounding the first sub-electrode, and the first sub-electrode are sequentially distributed in the second hole from outside to inside.

17. The semiconductor device according to claim 16, wherein: The first capacitor electrode is distributed on the inner wall of the groove, and the first sub-electrode extends in a direction perpendicular to the substrate and has a protruding portion extending to the groove.

18. The semiconductor device according to claim 16, wherein: The second capacitor electrode further includes a second sub-electrode; The second sub-electrode is distributed on a side of the first capacitor electrode facing away from the substrate, a side facing the substrate, and a side of the first capacitor electrode facing away from the second semiconductor sub-layer, and a second dielectric layer is arranged between the second sub-electrode and the first capacitor electrode.

19. A method for manufacturing a semiconductor device, comprising: Providing a substrate, on which a stacked structure including alternately arranged semiconductor structure layers and sacrificial layers is formed; Patterning the stacked structure to form a first groove penetrating each layer, wherein the first groove extends along a first direction; Adjacent first trenches spaced apart and distributed along a second direction include transistor regions; the first direction and the second direction intersect and are both parallel to the substrate; forming a hole penetrating the stacked structure in the transistor region in a direction perpendicular to the substrate, removing the sacrificial layer by etching through the hole, and replacing the sacrificial layer with an insulating layer; Based on the hole, the semiconductor structure layer is etched along a direction parallel to the substrate to form a second semiconductor sublayer, wherein the second semiconductor sublayer includes a first part and a second part disconnected from each other; a plurality of gate electrodes arranged along a direction perpendicular to the substrate and a plurality of first semiconductor sublayers surrounding the gate electrodes are formed in the hole, the plurality of gate electrodes are connected to form an integrated structure, and the plurality of first semiconductor sublayers are separated from each other.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The hole formed in the transistor region and penetrating the stacked structure in a direction perpendicular to the substrate comprises: a third hole and a fourth hole formed in the same transistor region and penetrating the stacked structure in a direction perpendicular to the substrate; The etching of the semiconductor structure layer along a direction parallel to the substrate based on the hole comprises: Etching the semiconductor structure layer in the third hole along a direction parallel to the substrate, so that the orthographic projection of the subhole of the third hole in the insulating layer on the substrate falls within the orthographic projection of the subhole of the semiconductor structure layer on the substrate; etching the semiconductor structure layer laterally in the fourth hole, so that the orthographic projection of the subhole of the fourth hole in the insulating layer on the substrate falls within the orthographic projection of the subhole of the semiconductor structure layer on the substrate, and the third hole and the fourth hole are connected to the subhole of the semiconductor structure layer; Forming a plurality of gate electrodes arranged in a direction perpendicular to the substrate in the hole and a plurality of first semiconductor sublayers surrounding the gate electrodes comprises: A plurality of first gate electrodes extending in a direction perpendicular to the substrate are formed in the third hole, a plurality of second gate electrodes extending in a direction perpendicular to the substrate are formed in the fourth hole, and the first semiconductor sublayer is formed in the sub-holes of the semiconductor structure layer in the third hole and the fourth hole.

21. The method for manufacturing a semiconductor device according to claim 19, wherein: The forming a plurality of first semiconductor sub-layers surrounding the gate electrode in the hole comprises: forming a plurality of first semiconductor sub-layers surrounding the gate electrode in the hole by epitaxial growth.

22. An electronic device comprising the semiconductor device according to any one of claims 1 to 18.

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