Display substrate and display apparatus

Abstract

A display substrate, comprising a base, at least one first display unit located in each display island region, and a plurality of second display units located in a second display region and arranged in an array. The second display region is located on at least one side of the first display region. The first display region comprises a plurality of display island regions and a plurality of light-transmissive regions which are arranged in an array. The first display unit comprises N first light-emitting elements and M first pixel circuits, M and N being both integers greater than 1, and M being less than N. At least one first pixel circuit is connected to at least two first light-emitting elements. A second display unit comprises M second light-emitting elements and M second pixel circuits, the M second pixel circuits being connected on a one-to-one basis to the M second light-emitting elements. The arrangement mode of the N first light-emitting elements of the first display unit is different from the arrangement mode of the M second light-emitting elements of the second display unit.

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 22, 2023, with application number 202311785367.4 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present application provide a display substrate and a display device.

[0006] On the one hand, this embodiment provides a display substrate, comprising: a substrate. The substrate comprises: a first display area and a second display area located on at least one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area comprises: at least one first display unit; the at least one first display unit comprises: N first light-emitting elements and M first pixel circuits, where M and N are both integers greater than 1, and M is less than N; at least one first pixel circuit among the M first pixel circuits is connected to at least two first light-emitting elements and is configured to drive the at least two first light-emitting elements to emit light. The second display area comprises: a plurality of second display units arranged in an array; at least one second display unit among the plurality of second display units comprises: M second light-emitting elements and M second pixel circuits, where the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence. The arrangement of the N first light-emitting elements of the at least one first display unit is different from the arrangement of the M second light-emitting elements of the at least one second display unit.

[0007] In some exemplary embodiments, within the first display area, the display island areas and the light-transmitting areas are alternately arranged and aligned in a first direction, and are alternately arranged and aligned in a second direction; wherein the first direction intersects the second direction.

[0008] In some exemplary embodiments, the M first pixel circuits of the at least one first display unit and the M second pixel circuits of the at least one second display unit are aligned in a first direction or a second direction, wherein the first direction intersects the second direction.

[0009] In some exemplary embodiments, the at least one first display unit includes six first light-emitting elements and four first pixel circuits, the four first pixel circuits being arranged sequentially along a first direction. The six first light-emitting elements include two first light-emitting elements that emit a first color of light, two first light-emitting elements that emit a second color of light, and two first light-emitting elements that emit a third color of light. The two first light-emitting elements that emit the first color of light are connected to the same first pixel circuit, the two first light-emitting elements that emit the third color of light are connected to the same first pixel circuit, and the two first light-emitting elements that emit the second color of light are electrically connected to the two first pixel circuits in a one-to-one correspondence.

[0010] In some exemplary embodiments, the six first light-emitting elements are divided into two groups of first light-emitting elements, the two groups of first light-emitting elements being arranged sequentially along the first direction, each group of first light-emitting elements comprising: a first light-emitting element emitting light of the first color, a first light-emitting element emitting light of the second color, and a first light-emitting element emitting light of the third color. In each group of first light-emitting elements, the first light-emitting elements emitting light of the first color and the first light-emitting elements emitting light of the second color are arranged sequentially along a second direction, and the first light-emitting element emitting light of the third color is located on the same side of the first light-emitting elements emitting light of the first color and the first light-emitting elements emitting light of the second color along the first direction. The second direction intersects the first direction.

[0011] In some exemplary embodiments, the six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged sequentially along the first direction. Each group of first light-emitting elements includes: a first light-emitting element that emits light of the first color, a first light-emitting element that emits light of the second color, and a first light-emitting element that emits light of the third color. In each group of first light-emitting elements, the first light-emitting element that emits light of the first color, the first light-emitting element that emits light of the second color, and the first light-emitting element that emits light of the third color are arranged sequentially along the first direction.

[0012] In some exemplary embodiments, in the first display area, the first pixel circuits of the first display units and the first light-emitting elements in adjacent rows of display island areas are connected in different orders.

[0013] In some exemplary embodiments, within the first display area, the four first pixel circuits located in the display island area of ​​the f-th row may be sequentially connected to two first light-emitting elements emitting light of the first color, one first light-emitting element emitting light of the second color, two first light-emitting elements emitting light of the third color, and another first light-emitting element emitting light of the second color. The four first pixel circuits of the first display unit located in the display island area of ​​the f-1-th row may be sequentially connected to two first light-emitting elements emitting light of the third color, one first light-emitting element emitting light of the second color, two first light-emitting elements emitting light of the first color, and another first light-emitting element emitting light of the second color; where f is an integer greater than 1.

[0014] In some exemplary embodiments, the at least one second display unit includes: four second light-emitting elements and four second pixel circuits; the four second pixel circuits are arranged sequentially along the first direction. The four second light-emitting elements include: one second light-emitting element that emits a first color light, two second light-emitting elements that emit a second color light, and one second light-emitting element that emits a third color light; the second light-emitting element that emits the first color light and the second light-emitting element that emits the third color light are arranged in the same row, and the two second light-emitting elements that emit the second color light are arranged in the same row; along the first direction, the second light-emitting element that emits the first color light, the second light-emitting element that emits the second color light, the second light-emitting element that emits the third color light, and the second light-emitting element that emits the second color light are arranged sequentially.

[0015] In some exemplary embodiments, the first color light is red light, the second color light is green light, and the third color light is blue light.

[0016] In some exemplary embodiments, the M first pixel circuits of the first display unit within the display island region are connected to a first scan transmission segment and a second scan transmission segment extending along a first direction; the first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal. First scan transmission segments within adjacent display island regions located in the same row are connected via a first scan connection segment; second scan transmission segments within adjacent display island regions located in the same row are connected via a second scan connection segment. The second scan connection segment is located on a side of the first scan connection segment away from the substrate, and the orthographic projection of the first scan connection segment on the substrate at least partially overlaps with the orthographic projection of the second scan connection segment on the substrate.

[0017] In some exemplary embodiments, a first pixel circuit of a first display unit located within a display island region in the same row is further connected to a first reset control line and a first initial signal line extending along the first direction, wherein the first initial signal line is located on a side of the first reset control line away from the substrate; and the first scan connection segment is located on a side of the first initial signal line away from the substrate. An orthographic projection of the first scan connection segment on the substrate at least partially overlaps with an orthographic projection of the first initial signal line on the substrate; and an orthographic projection of the first initial signal line on the substrate at least partially overlaps with an orthographic projection of the first reset control line on the substrate.

[0018] In some exemplary embodiments, the M first pixel circuits of the first display unit within the display island region are connected to a light-emission control transmission segment extending along the first direction; the light-emission control transmission segment is configured to transmit a light-emission control signal; and the light-emission control transmission segments within adjacent display island regions located in the same row are connected via a light-emission control connection segment. The light-emission control connection segment and the first scanning connection segment are located on either side of a light-transmitting region between adjacent display island regions in a second direction. The second direction intersects the first direction.

[0019] In some exemplary embodiments, the first pixel circuit of the first display unit located in the same row of display islands is further connected to a second reset control line and a second initial signal line extending along the first direction, the second initial signal line being located on a side of the second reset control line away from the substrate; the light emission control connecting segment being located on a side of the second initial signal line away from the substrate; the orthographic projection of the light emission control connecting segment on the substrate at least partially overlapping with the orthographic projection of the second initial signal line on the substrate; and the orthographic projection of the second initial signal line on the substrate at least partially overlapping with the orthographic projection of the second reset control line on the substrate.

[0020] In some exemplary embodiments, the M first pixel circuits of the first display unit within the display island region are further connected to an initial signal transmission segment extending along the first direction; the initial signal transmission segment is configured to transmit a third initial signal. Initial signal transmission segments within adjacent display island regions located in the same row are connected via an initial signal connection segment. The light emission control connection segment is located on a side of the initial signal connection segment away from the substrate; the orthographic projection of the initial signal connection segment on the substrate partially overlaps the orthographic projection of the light emission control connection segment on the substrate.

[0021] In some exemplary embodiments, a plurality of first pixel circuits located in the k-th row and h-th column display island area and a plurality of first pixel circuits located in the k+1-th row and h+1-th column display island area are centrally symmetric about a connection point between the k-th row and h-th column display island area and the k+1-th row and h+1-th column display island area; wherein k and h are both integers greater than 0.

[0022] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area share a first reset control line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1-th row located in the k+1-th row display island area share a second reset control line, where i is an integer greater than 1, and e is an integer greater than or equal to 0.

[0023] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row located in the k-th display island area and the first pixel circuit of the i-1-th row located in the k-1-th display island area share a first initial signal line, and the first pixel circuit of the i+e-th row located in the k-th display island area and the first pixel circuit of the i+e+1-th row located in the k+1-th display island area share a second initial signal line.

[0024] In some exemplary embodiments, the display island area includes two first display units, and the two first display units are arranged along a first direction or along a second direction, wherein the first direction intersects the second direction.

[0025] On the other hand, this embodiment provides a display device, comprising the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0026] On the other hand, this embodiment provides a display substrate, comprising: a substrate. The substrate comprises: a first display area and a second display area located on at least one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area comprises: at least one group of first pixel circuits and a plurality of first light-emitting elements, each group of first pixel circuits comprising M first pixel circuits, at least one of the M first pixel circuits being connected to at least two first light-emitting elements; M is an integer greater than 1. The second display area comprises: a plurality of groups of second pixel circuits and a plurality of second light-emitting elements, each group of second pixel circuits comprising M second pixel circuits, at least one second pixel circuit being connected to at least one second light-emitting element. The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area. The first pixel circuits and the second pixel circuits in the same column are connected to the same data line.

[0027] In some exemplary embodiments, each group of first pixel circuits includes four first pixel circuits connected to six first light-emitting elements, including two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light. Each group of second pixel circuits includes four second pixel circuits connected to four second light-emitting elements, including one second light-emitting element emitting first color light, two second light-emitting elements emitting second color light, and one second light-emitting element emitting third color light.

[0028] In some exemplary embodiments, an arrangement of the six first light-emitting elements is different from an arrangement of the four second light-emitting elements.

[0029] In some exemplary embodiments, the arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the first direction; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second direction in the second display area.

[0030] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0031] Summary of the Figures

[0032] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0033] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0034] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0035] FIG3 is a timing diagram of the operation of the pixel circuit provided in FIG2 ;

[0036] FIG4 is a partial schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0037] FIG5 is a schematic diagram of the signal correspondence relationship between the first display area and the second display area according to at least one embodiment of the present disclosure;

[0038] FIG6 is a partial top view of the first display area according to at least one embodiment of the present disclosure;

[0039] FIG7 is a schematic diagram of the first display area after the shielding layer is formed in FIG6 ;

[0040] FIG8A is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG6 ;

[0041] FIG8B is a schematic diagram of the first semiconductor layer in FIG8A ;

[0042] FIG9A is a schematic diagram of the first display area after the first conductive layer is formed in FIG6 ;

[0043] FIG9B is a schematic diagram of the first conductive layer and the first semiconductor layer in FIG9A ;

[0044] FIG9C is a schematic diagram of the first conductive layer in FIG9A ;

[0045] FIG10A is a schematic diagram of the first display area after the second conductive layer is formed in FIG6 ;

[0046] FIG10B is a schematic diagram of the second conductive layer in FIG10A ;

[0047] FIG11A is a schematic diagram of the first display region after the second semiconductor layer is formed in FIG6 ;

[0048] FIG11B is a schematic diagram of the second semiconductor layer in FIG11A ;

[0049] FIG12A is a schematic diagram of the first display area after the third conductive layer is formed in FIG6;

[0050] FIG12B is a schematic diagram of the third conductive layer in FIG12A;

[0051] FIG13 is a schematic diagram of the first display area after the fifth insulating layer is formed in FIG6;

[0052] FIG14A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG6 ;

[0053] FIG14B is a schematic diagram of the fourth conductive layer in FIG14A;

[0054] FIG15 is a schematic diagram of the first display area after the seventh insulating layer is formed in FIG6;

[0055] FIG16A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG6 ;

[0056] FIG16B is a schematic diagram of the fifth conductive layer in FIG16A;

[0057] FIG17 is a schematic diagram of the first display area after the eighth insulating layer is formed in FIG6;

[0058] FIG18A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG6 ;

[0059] FIG18B is a schematic diagram of the sixth conductive layer in FIG18A ;

[0060] FIG19 is a schematic diagram of the first display area after the ninth insulating layer is formed in FIG6 ;

[0061] FIG20A is a schematic diagram of the first display area after the anode layer is formed in FIG6 ;

[0062] FIG20B is a schematic diagram of the anode layer in FIG20A;

[0063] FIG21 is a schematic diagram of the light-transmitting area in FIG6 ;

[0064] FIG22 is another partial schematic top view of the first display area according to at least one embodiment of the present disclosure;

[0065] FIG23 is a schematic diagram of the first display area after the shielding layer is formed in FIG22;

[0066] FIG24A is a schematic diagram of the first display region after the first semiconductor layer is formed in FIG22;

[0067] FIG24B is a schematic diagram of the first semiconductor layer in FIG24A ;

[0068] FIG25A is a schematic diagram of the first display area after the first conductive layer is formed in FIG22;

[0069] FIG25B is a schematic diagram of the first conductive layer in FIG25A ;

[0070] FIG26A is a schematic diagram of the first display area after the second conductive layer is formed in FIG22;

[0071] FIG26B is a schematic diagram of the second conductive layer in FIG26A ;

[0072] FIG27A is a schematic diagram of the first display region after the second semiconductor layer is formed in FIG22;

[0073] FIG27B is a schematic diagram of the second semiconductor layer in FIG27A;

[0074] FIG28A is a schematic diagram of the first display area after the third conductive layer is formed in FIG22;

[0075] FIG28B is a schematic diagram of the third conductive layer in FIG28A ;

[0076] FIG29A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG22;

[0077] FIG29B is a schematic diagram of the fourth conductive layer in FIG29A;

[0078] FIG30A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG22;

[0079] FIG30B is a schematic diagram of the fifth conductive layer in FIG30A ;

[0080] FIG31A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG22;

[0081] FIG31B is a schematic diagram of the sixth conductive layer in FIG31A ;

[0082] FIG32 is a schematic diagram of the first display area after the anode layer is formed in FIG22;

[0083] FIG33 is a schematic diagram of the light-transmitting area in FIG22;

[0084] FIG34 is another schematic diagram of the signal correspondence between the first display area and the second display area according to at least one embodiment of the present disclosure;

[0085] FIG35 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0086] FIG36 is a partial top view of the first display area according to at least one embodiment of the present disclosure;

[0087] FIG37A is a schematic diagram of the first display area after the anode layer is formed in FIG36;

[0088] FIG37B is a schematic diagram of the anode layer in FIG37A;

[0089] FIG38 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0090] FIG39 is another partial schematic diagram of the display area according to at least one embodiment of the present disclosure;

[0091] FIG40 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0092] Details

[0093] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. This application describes a plurality of embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope encompassed by the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0094] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0095] In addition, when describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims for the method or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0096] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0097] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features being referred to. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include at least one of the features.

[0098] In the description of the present application, “a plurality of” means at least two, for example, two, three, etc., unless explicitly defined otherwise.

[0099] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can mean mechanical connection or electrical connection; it can mean direct connection or indirect connection through an intermediate medium; it can mean internal communication between two elements or interaction between two elements, unless otherwise specified. For those skilled in the art, the meanings of the above terms in this application can be understood according to the circumstances.

[0100] In this application, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0101] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it can mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it can mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it can mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0102] In this application, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this application, the channel region refers to the region through which current primarily flows.

[0103] In this application, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes interchanged. Therefore, in this application, "source" and "drain" can be interchanged. In addition, the gate can also be called a control electrode.

[0104] In this application, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0105] In this application, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0106] The "light transmittance" in this application refers to the ability of light to pass through a medium, which is the percentage of the luminous flux passing through a transparent or translucent body to its incident luminous flux.

[0107] In this application, the terms "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this application, "same" can include both completely identical and substantially identical conditions, and "substantially identical" means that the values ​​differ by less than 10%.

[0108] In this application, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion is a line, line segment, or strip-shaped body, the main portion extends along direction B, and the length of the main portion extending along direction B is greater than the length of the secondary portion extending along other directions. In this application, "A extends along direction B" means "the main portion of A extends along direction B."

[0109] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and in-screen hole have emerged one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technologies require digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, an external pixel circuit method or a built-in pixel circuit method is usually adopted in the camera area under the screen.

[0110] The external pixel circuit method involves placing the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area. By separating the light-emitting element and the pixel circuit, the light transmittance of the under-screen camera area is improved. Since the under-screen camera area does not have a pixel circuit, there is no other light-shielding layer in this area except for the anode of the light-emitting element, which can achieve a higher light transmittance. However, under this method, the pixel circuit and the light-emitting element need to be electrically connected via conductive connecting wires. Due to the limited arrangement space of the conductive connecting wires, the size (e.g., aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. Increasing the aperture of the under-screen camera area usually requires increasing the masking process for the conductive connecting wires, resulting in increased costs. Moreover, the conductive connecting wires are usually made of transparent conductive materials, such as indium tin oxide (ITO). Due to the large square resistance of ITO, the conductive connecting wires are loaded heavily, which can easily affect the brightness of the light-emitting element in the under-screen camera area, reducing the brightness of the under-screen camera area, thereby causing poor display in the under-screen camera area, such as vertical display defect (mura). Moreover, the use of conductive connecting wires easily introduces more vias, which in turn reduces the aperture ratio of the under-screen camera area, which is not conducive to optimizing the light transmittance of the under-screen camera area.

[0111] The built-in pixel circuit method involves placing a light-emitting element and the pixel circuit connected to it in the under-screen camera area. Compared to the external pixel circuit method, the built-in method eliminates the need for long conductive wires to connect the pixel circuit and light-emitting element in the under-screen camera area, thus avoiding poor display quality in the under-screen camera area caused by these wires. Furthermore, the built-in method places no restrictions on the size of the under-screen camera area and can support large-aperture under-screen camera areas. However, for complex pixel circuits, due to the numerous wiring patterns, it is difficult to improve the light transmittance of the under-screen camera area by compressing the pixel circuit layout, resulting in an inability to meet the light transmittance requirements for functions such as under-screen video or under-screen facial recognition.

[0112] For the pixel circuit integration method, some of the light-emitting elements and pixel circuits in the under-screen camera area can be removed, so that the remaining light-emitting elements and pixel circuits do not need to be compressed, thereby achieving the required light transmittance of the under-screen function. However, removing some of the light-emitting elements and pixel circuits in the under-screen camera area to improve light transmittance can easily affect the display effect.

[0113] This embodiment provides a display substrate and a display device, which can not only improve the light transmittance of the under-screen camera area, but also compensate for the loss of display effect caused by deleting some light-emitting elements and pixel circuits in the under-screen camera area.

[0114] This embodiment provides a display substrate, comprising: a substrate, at least one first display unit located in a display island area, and a plurality of second display units located in a second display area and arranged in an array. The substrate comprises: a first display area and a second display area located on at least one side of the first display area. The first display area comprises a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. At least one first display unit comprises: N first light-emitting elements and M first pixel circuits, where M and N are both integers greater than 1, and M is less than N. At least one first pixel circuit among the M first pixel circuits is connected to at least two first light-emitting elements and is configured to drive the at least two first light-emitting elements to emit light. At least one second display unit comprises: M second light-emitting elements and M second pixel circuits, where the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence. The arrangement of the N first light-emitting elements of the at least one first display unit is different from the arrangement of the M second light-emitting elements of the at least one second display unit.

[0115] In some examples, the shapes and sizes of the multiple display island regions in the first display area can be substantially the same, and the shapes and sizes of the multiple light-transmitting regions can be substantially the same. The light-transmitting regions can be formed by deleting first pixel circuits and first light-emitting elements, and the number of first pixel circuits deleted corresponding to the light-transmitting regions can be less than or equal to the total number of first pixel circuits included in the multiple display island regions.

[0116] In some examples, at least one first pixel circuit in the first display unit can be connected to at least two first light-emitting elements, and at least one first pixel circuit can be connected to at least one first light-emitting element. For example, the first display unit may include four first pixel circuits, two of which can be connected to the first light-emitting element in a one-drive-two manner, and two of which can be connected to the first light-emitting element in a one-drive-one manner. In this example, one-drive-F means that one pixel circuit is connected to F light-emitting elements, and the pixel circuit drives the connected F light-emitting elements to emit light, where F is an integer greater than or equal to 1. For example, one-drive-one means that one pixel circuit is connected to one light-emitting element and drives the connected one light-emitting element to emit light; one-drive-two means that one pixel circuit is connected to two light-emitting elements and drives the connected two light-emitting elements to emit light. However, this embodiment is not limited to this. In other examples, the first pixel circuit in the first display unit can be connected to the first light-emitting element in other one-drive-many manners such as one-drive-three or one-drive-four.

[0117] In some exemplary embodiments, the second pixel circuit in the second display unit can be connected to the second light-emitting element in a one-to-one manner. The arrangement density of the second pixel circuit in the second display area can be greater than or equal to the arrangement density of the first pixel circuit in the first display area. For example, the arrangement density of the first pixel circuit in the first direction in the first display area can be 0.4 to 0.6 of the arrangement density of the second pixel circuit in the second display area in the first direction, such as 0.45 to 0.55, for example, approximately 0.5; or, the arrangement density of the first pixel circuit in the first display area in the column direction can be 0.4 to 0.6 of the arrangement density of the second pixel circuit in the second display area in the column direction, such as 0.45 to 0.55, for example, approximately 0.5. This example can improve the light transmittance of the first display area by deleting the first pixel circuit in the first display area.

[0118] In some examples, the light transmittance of the second display area may be less than the light transmittance of the first display area.

[0119] The display substrate provided in this embodiment adopts a pixel circuit built-in method to delete the first pixel circuit and the first light-emitting element in the first display area to form a light-transmitting area, and sets the arrangement of the first light-emitting elements to be different from the arrangement of the second light-emitting elements. On the basis of improving the light transmittance of the first display area, it can ensure the display effect of the first display area and compensate for the loss of display effect caused by deleting some light-emitting elements and pixel circuits in the first display area.

[0120] In some exemplary embodiments, each display island may include a first display unit. In other examples, at least one display island may include multiple first display units, for example, two first display units. The two first display units within the display island may be arranged along a first direction, or may be arranged along a second direction. The first direction may intersect with the second direction, for example, the first direction may be perpendicular to the second direction. In some examples, the first direction may be parallel to the row direction of the display islands arranged in an array, and the second direction may be parallel to the column direction of the display islands arranged in an array. This embodiment is not limited to this.

[0121] In some exemplary embodiments, within the first display area, multiple display islands and multiple light-transmitting areas are alternately arranged and aligned in a first direction, and multiple display islands and multiple light-transmitting areas are alternately arranged and aligned in a second direction. The first direction may intersect the second direction. However, this embodiment is not limited to this. In other examples, multiple display islands may be arranged continuously and staggered in the second direction. The arrangement of the display islands and light-transmitting areas in the first display area of ​​this example can help improve the light transmittance of the first display area.

[0122] In this example, alternating arrangement of A and B in direction C means that A and B are alternately arranged along direction C, i.e., they are periodically arranged in the order AB along direction C. Aligning arrangement of A and B in direction C means that the edges of A and B roughly coincide with the midline of the direction perpendicular to direction C, and the extended edges of A and B can roughly coincide with each other. Staggered arrangement of A and B in direction C means that the edges of A and B roughly coincide with the midline of the direction perpendicular to direction C and do not coincide with each other.

[0123] In some exemplary embodiments, the M first pixel circuits of at least one first display unit and the M second pixel circuits of at least one second display unit are aligned in the first direction or the second direction. In this example, the first pixel circuits of the first display area and the second pixel circuits of the second display area can share signal lines extending along the first direction (e.g., including first scan lines, second scan lines, light-emitting control lines, etc.), and can share signal lines extending along the second direction (e.g., including data lines, etc.), thereby facilitating line arrangement.

[0124] In some exemplary embodiments, at least one first display unit may include: six first light-emitting elements and four first pixel circuits, and the four first pixel circuits are arranged in sequence along the first direction. The six first light-emitting elements include: two first light-emitting elements that emit first color light, two first light-emitting elements that emit second color light, and two first light-emitting elements that emit third color light. The two first light-emitting elements that emit first color light are connected to the same first pixel circuit, the two first light-emitting elements that emit third color light are connected to the same first pixel circuit, and the two first light-emitting elements that emit second color light are electrically connected to the two first pixel circuits in a one-to-one correspondence. For example, the first color light is red light, the second color light is green light, and the third color light is blue light. The first light-emitting elements of the first display area of ​​this example can adopt an RGB arrangement, which is conducive to improving the display effect of the first display area.

[0125] In some exemplary embodiments, the six first light-emitting elements of the first display unit can be divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction. Each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. In each group of first light-emitting elements, the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light can be arranged in sequence along the second direction, and the first light-emitting element emitting the third color light can be located on the same side of the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light along the first direction. Alternatively, in each group of first light-emitting elements, the first light-emitting element emitting the first color light, the first light-emitting element emitting the second color light, and the first light-emitting element emitting the third color light can be arranged in sequence along the first direction. The arrangement of the first light-emitting elements in the first display area of ​​this example can optimize the display effect of the first display area.

[0126] In some exemplary embodiments, at least one second display unit may include: four second light-emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along the first direction. The four second light-emitting elements may include: a second light-emitting element that emits a first color light, two second light-emitting elements that emit a second color light, and a second light-emitting element that emits a third color light. The second light-emitting element that emits the first color light and the second light-emitting element that emits the third color light are arranged in the same row, and the two second light-emitting elements that emit the second color light are arranged in the same row; along the first direction, the second light-emitting element that emits the first color light, the second light-emitting element that emits the second color light, the second light-emitting element that emits the third color light, and the second light-emitting element that emits the second color light can be arranged in sequence. For example, the first color light is red light, the second color light is green light, and the third color light is blue light. The second display area of ​​this example can adopt an RGBG arrangement to ensure the display effect of the second display area.

[0127] In some exemplary embodiments, within the first display area, the connection order of the first pixel circuits and the first light-emitting elements of the first display units in adjacent rows of display islands may be different. In some examples, the four first pixel circuits of the first display unit located in the display island area of ​​the fth row may be connected in sequence to two first light-emitting elements emitting first color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting third color light, and another first light-emitting element emitting second color light. The four first pixel circuits of the first display unit located in the display island area of ​​the f-1th row may be connected in sequence to two first light-emitting elements emitting third color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting first color light, and another first light-emitting element emitting second color light. Wherein, f is an integer greater than 1. The connection method of the first pixel circuits and the first light-emitting elements in the display island area of ​​this example can be beneficial to optimizing the display uniformity of the first display area.

[0128] In some exemplary embodiments, within the first display area, the M first pixel circuits of the first display unit within the display island area are connected to a first scan transmission segment and a second scan transmission segment extending along the first direction. The first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal. The first scan transmission segments within adjacent display island areas located in the same row can be connected via a first scan connection segment, and the second scan transmission segments within adjacent display island areas located in the same row can be connected via a second scan connection segment. For example, the first scan line may include a first scan transmission segment and a first scan connection segment connected at intervals along the first direction, and the first scan transmission segment and the first scan connection segment are located in different film layers; the second scan line may include a second scan transmission segment and a second scan connection segment connected at intervals along the first direction, and the second scan transmission segment and the second scan connection segment are located in different film layers. The second scan connection segment may be located on a side of the first scan connection segment away from the substrate, and the orthographic projection of the first scan connection segment on the substrate and the orthographic projection of the second scan connection segment on the substrate may at least partially overlap. For example, the first scan transmission segment can be located on the first conductive layer, and the first scan connection segment can be located on the fourth conductive layer; the second scan transmission segment can be located on the third conductive layer, and the second scan connection segment can be located on the fifth conductive layer. In this example, the transmission traces of the first scan signal and the second scan signal are segmented and switched across layers, allowing the first scan connection segment and the second scan connection segment to overlap, thereby increasing the area of ​​the light-transmitting area and thereby improving the light transmittance of the first display area.

[0129] In some exemplary embodiments, the first pixel circuit of the first display unit located in the same row of the display island area can also be connected to the first reset control line and the first initial signal line extending along the first direction, and the first initial signal line can be located on the side of the first reset control line away from the substrate. The first scan connection segment can be located on the side of the first initial signal line away from the substrate. The orthographic projection of the first scan connection segment on the substrate can at least partially overlap with the orthographic projection of the first initial signal line on the substrate, and the orthographic projection of the first initial signal line on the substrate can at least partially overlap with the orthographic projection of the first reset control line on the substrate. For example, the first initial signal line can be located in the third conductive layer, the first reset control line can be located in the first conductive layer, and the first scan connection segment can be located in the fourth conductive layer. In this example, overlapping wiring of the first reset control line, the first initial signal line, and the first scan connection segment can help increase the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0130] In some exemplary embodiments, the M first pixel circuits of the first display unit in the display island area can be connected to a light-emitting control transmission segment extending along the first direction; the light-emitting control transmission segment can be configured to transmit a light-emitting control signal. The light-emitting control transmission segments in the display island areas that are adjacent to each other in the same row can be connected through a light-emitting control connection segment. For example, the light-emitting control line may include a light-emitting control transmission segment and a light-emitting control connection segment that are spaced apart and connected along the first direction, and the light-emitting control transmission segment and the light-emitting control connection segment are located in different film layers. For example, the light-emitting control transmission segment can be located in the first conductive layer, and the light-emitting control connection segment can be located in the fourth conductive layer. The light-emitting control connection segment and the first scanning connection segment can be located on both sides of the light-transmitting area between the adjacent display island areas in the column direction. In this example, the first scanning connection segment and the light-emitting control connection segment are arranged to bypass the light-transmitting area from both sides of the light-transmitting area along the column direction, which can optimize the wiring space and help increase the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0131] In some exemplary embodiments, the first pixel circuit of the first display unit located in the same row of the display island area may also be connected to the second reset control line and the second initial signal line extending along the first direction, and the second initial signal line may be located on the side of the second reset control line away from the substrate; the light-emitting control connection segment may be located on the side of the second initial signal line away from the substrate. The orthographic projection of the light-emitting control connection segment on the substrate may at least partially overlap with the orthographic projection of the second initial signal line on the substrate. The orthographic projection of the second initial signal line on the substrate may at least partially overlap with the orthographic projection of the second reset control line on the substrate. For example, the second reset control line may be located in the first conductive layer, the second initial signal line may be located in the third conductive layer, and the light-emitting control connection segment may be located in the fourth conductive layer. In this example, overlapping wiring of the second reset control line, the second initial signal line, and the light-emitting control connection segment may be beneficial to increasing the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0132] In some exemplary embodiments, the M first pixel circuits of the first display unit in the display island area may also be connected to an initial signal transmission segment extending along the first direction; the initial signal transmission segment may be configured to transmit a third initial signal. The initial signal transmission segments in the display island areas that are adjacent to each other in the same row may be connected through an initial signal connection segment. For example, the third initial signal line may include an initial signal transmission segment and an initial signal connection segment that are spaced apart and connected along the first direction, and the initial signal transmission segment and the initial signal connection segment may be located in different film layers. The light-emitting control connection segment may be located on the side of the initial signal connection segment away from the substrate. The orthographic projection of the initial signal connection segment on the substrate may partially overlap with the orthographic projection of the light-emitting control connection segment on the substrate. For example, the initial signal transmission segment may be located in the third conductive layer, the initial signal connection segment may be located in the second conductive layer, and the light-emitting control connection segment may be located in the fourth conductive layer. In this example, overlapping wiring of the initial signal connection segment and the light-emitting control connection segment may be beneficial to increasing the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0133] In some exemplary embodiments, the plurality of first pixel circuits located in the display island area of ​​row k, column h and the plurality of first pixel circuits located in the display island area of ​​row k+1, column h+1 may be centrally symmetric about the connection point between the display island area of ​​row k, column h and the display island area of ​​row k+1, column h+1. Wherein, k and h are both integers greater than 0. In this example, the first pixel circuits in the display island areas of even rows or odd rows are flipped so that the first pixel circuits in the display island areas of adjacent rows and columns are centrally symmetric. This can help reduce the wiring space within the display island area, increase the area of ​​the light-transmitting area, and thus improve the light transmittance of the first display area.

[0134] In some exemplary embodiments, within the first display area, the first pixel circuits in the i-th row located in the k-th display island area and the first pixel circuits in the i-1-th row located in the k-1-th display island area may share a first reset control line, and the first pixel circuits in the i+e-th row located in the k-th display island area and the first pixel circuits in the i+e+1-th row located in the k+1-th display island area may share a second reset control line, where i is an integer greater than 1, and e is an integer greater than or equal to 0. In some examples, a row of first pixel circuits may be provided for each row of display island areas, and the value of e may be 0; the first pixel circuits in the i-th row located in the k-th display island area and the first pixel circuits in the i-1-th row located in the k-1-th display island area may share a first reset control line, and the first pixel circuits in the i-th row located in the k-th display island area and the first pixel circuits in the i+1-th row located in the k+1-th display island area may share a second reset control line. In other examples, each row of the display island area includes at least two rows of first pixel circuits, and the value of e can be greater than or equal to 1. For example, each row of the display island area can include two rows of first pixel circuits, and e can be 1. The first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area can share a first reset control line, and the first pixel circuit of the i+1-th row located in the k-th row display island area and the first pixel circuit of the i+2-th row located in the k+1-th row display island area can share a second reset control line. This example can help reduce wiring space and increase the area of ​​the light-transmitting area by setting two adjacent rows of first pixel circuits in adjacent rows of display island areas to share the first reset control line or the second reset control line, thereby improving the light transmittance of the first display area.

[0135] In some exemplary embodiments, within the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area may share a first initial signal line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1-th row located in the k+1-th row display island area may share a second initial signal line. In some examples, each row of display island areas may be provided with a row of first pixel circuits, and the value of e may be 0; the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area may share a first initial signal line, and the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i+1-th row located in the k+1-th row display island area may share a second initial signal line. In other examples, each row of display island areas includes at least two rows of first pixel circuits, and the value of e may be greater than or equal to 1. For example, each row of display island areas may include two rows of first pixel circuits, and e may be 1. The first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area may share a first initial signal line, and the first pixel circuit of the i+1-th row located in the k-th row display island area and the first pixel circuit of the i+2-th row located in the k+1-th row display island area may share a second initial signal line. In this example, by setting two adjacent rows of first pixel circuits in adjacent rows of display island areas to share the first initial signal line or the second initial signal line, it is beneficial to reduce wiring space, increase the area of ​​the light-transmitting area, and thus improve the light transmittance of the first display area.

[0136] The solution of this embodiment is illustrated below through some examples.

[0137] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display substrate may include a display area AA and a peripheral area BB located outside the display area AA. The display area AA may include at least a first display area A1 and a second display area A2, wherein the second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this.

[0138] In some examples, as shown in Figure 1, the first display area A1 can be called the under-screen camera (FDC, Full Display With Camera) area. The second display area A2 can also be called the normal display area. The light transmittance of the first display area A1 can be greater than the light transmittance of the second display area A2. For example, the orthographic projection of the sensor (such as hardware such as a camera) on the display substrate can be located in the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 can be circular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the first display area A1. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the sensor on the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1. This embodiment is not limited to this.

[0139] In some examples, as shown in FIG1 , the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other locations, such as the upper left corner, upper right corner, lower left corner, or lower right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0140] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0141] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0142] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0143] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data write transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0144] In some examples, the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0145] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0146] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0147] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0148] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0149] FIG3 is an operating timing diagram of the pixel circuit shown in FIG2. The operating process of the pixel circuit shown in FIG2 will be described below with reference to FIG3. In the pixel circuit, the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0150] In some examples, as shown in FIG. 2 and FIG. 3 , during a frame display period, the operation process of the pixel circuit may include at least: a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 .

[0151] The first stage S1 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0152] The second stage S2 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The first transistor T1 and the second transistor T2 are turned on, causing the first initial signal line provided by the first initial signal line INIT1 to be supplied to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0153] The third stage S3 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0154] In the fourth stage S4, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0155] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata]2 ;

[0156] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0157] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0158] In some examples, as shown in FIG1 , the first display area A1 may include: a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 13; the second display area A2 may include: a plurality of second pixel circuits 12 and a plurality of second light-emitting elements 14. At least one first pixel circuit 11 may be connected to at least one first light-emitting element 13 and configured to drive the at least one first light-emitting element 13 connected thereto to emit light. At least one second pixel circuit 12 may be connected to at least one second light-emitting element 14 and configured to drive the at least one second light-emitting element 14 connected thereto to emit light. This example uses a pixel circuit built-in method in the first display area A1 to drive the first light-emitting elements to emit light.

[0159] Figure 4 is a partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 4 illustrates the arrangement of multiple first light-emitting elements in the first display area and multiple second light-emitting elements in the second display area. Figure 4 uses eight rows and four columns of display islands in the first display area as an example. This example does not limit the number of display islands in the first display area.

[0160] In some examples, as shown in FIG4 , the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. In a first direction X (parallel to the row direction), the display island areas A11 and the light-transmitting areas A12 may be alternately arranged and aligned. In a second direction Y (parallel to the column direction), the display island areas A11 and the light-transmitting areas A12 may be alternately arranged and aligned. However, this embodiment is not limited to this. In other examples, adjacent rows of display island areas may be staggered, for example, at least one first pixel circuit in adjacent rows of display island areas may be aligned.

[0161] In some examples, the display islands A11 may have substantially the same shape and size, and the light-transmitting areas A12 may have substantially the same shape and size. For example, the display islands A11 may be substantially rectangular.

[0162] In some examples, as shown in FIG4 , at least one display island A11 may include a first display unit 21. The first display unit 21 may include six first light-emitting elements and four first pixel circuits. The six first light-emitting elements may include two first light-emitting elements 13a and 13d that emit a first color of light, two first light-emitting elements 13b and 13e that emit a second color of light, and two first light-emitting elements 13c and 13f that emit a third color of light. For example, the first color of light may be red, the second color of light may be green, and the third color of light may be blue. This embodiment is not limited to this.

[0163] In some examples, as shown in FIG4 , the six first light-emitting elements of the first display unit 21 can be divided into two groups of first light-emitting elements, each group of first light-emitting elements including three first light-emitting elements emitting light of different colors. For example, the first group of first light-emitting elements can include three first light-emitting elements 13a, 13b, and 13c; the second group of first light-emitting elements can include three first light-emitting elements 13d, 13e, and 13f. The first group of first light-emitting elements and the second group of first light-emitting elements can be arranged sequentially along a first direction X. In the first group of first light-emitting elements, first light-emitting elements 13a and 13b can be arranged sequentially along a second direction Y, and first light-emitting element 13c can be located on the same side of first light-emitting elements 13a and 13b in the first direction X. For example, first light-emitting element 13a can be located to one side of first light-emitting element 13b in the second direction Y, and first light-emitting element 13c can be located to one side of first light-emitting elements 13a and 13b in the first direction X. In the second group of first light-emitting elements, the first light-emitting elements 13d and 13e may be arranged sequentially along the second direction Y, and the first light-emitting element 13f may be located on the same side of the first light-emitting elements 13d and 13e in the first direction X. For example, the first light-emitting element 13d may be located on one side of the first light-emitting element 13e in the second direction Y, and the first light-emitting element 13f may be located on one side of the first light-emitting elements 13d and 13e in the first direction X. In this example, the three first light-emitting elements emitting light of different colors in each group of first light-emitting elements of the first display unit 21 may be arranged in a Pentile RGB manner.

[0164] In some examples, as shown in FIG4 , the second display area A2 may include: a plurality of second display units 22 arranged in an array. At least one second display unit 22 may include: four second light-emitting elements and four second pixel circuits. The four second light-emitting elements may include: a second light-emitting element 14a emitting a first color light, two second light-emitting elements 14b and 14d emitting a second color light, and a second light-emitting element 14c emitting a third color light. The four second light-emitting elements may be electrically connected to the four second pixel circuits in a one-to-one correspondence. Each second pixel circuit may be configured to drive a corresponding second light-emitting element to emit light. Within a second display unit 22, the second light-emitting elements 14a, 14b, 14c, and 14d may be arranged in different columns in sequence along the first direction X, the second light-emitting elements 14a and 14c may be arranged in the same row, and the second light-emitting elements 14b and 14d may be arranged in the same row. In the second display area A2, the plurality of second light-emitting elements 14a and 14c may be arranged in the same row at intervals, and the plurality of second light-emitting elements 14b and 14d may be arranged in the same row at intervals. The row containing the second light-emitting elements 14a and 14c may be spaced apart from the row containing the second light-emitting elements 14b and 14d along the second direction Y, so that the plurality of second light-emitting elements 14a and 14c may be spaced apart in the same column, and the plurality of second light-emitting elements 14b and 14d may be spaced apart in the same column. In this example, the plurality of second light-emitting elements in the second display area may be arranged in an RGBG pattern.

[0165] Figure 5 is a schematic diagram of the signal correspondence between the first display area and the second display area according to at least one embodiment of the present disclosure. Figure 5 takes a first display unit in the first display area A1 and a second display unit in the second display area A2 as an example for illustration.

[0166] In some examples, as shown in FIG5 , the four first pixel circuits of the first display unit may include: first pixel circuits 11a, 11b, 11c, and 11d arranged sequentially along a first direction X. The first pixel circuit 11a may be connected to two first light-emitting elements 13a and 13d emitting light of a first color, and configured to drive the two first light-emitting elements 13a and 13d to emit light. The first pixel circuit 11b may be connected to one first light-emitting element 13b emitting light of a second color, and configured to drive the first light-emitting element 13b to emit light. The first pixel circuit 11c may be connected to two first light-emitting elements 13c and 13f emitting light of a third color, and configured to drive the two first light-emitting elements 13c and 13f to emit light. The first pixel circuit 11d may be connected to one first light-emitting element 13e emitting light of a second color, and configured to drive the first light-emitting element 13e to emit light. In this example, the first pixel circuits 11a and 11c are connected to the first light-emitting elements in a one-drive-two configuration, and the first pixel circuits 11b and 11d are connected to the first light-emitting element in a one-drive-one configuration.

[0167] In some examples, as shown in FIG5 , the orthographic projection of the first pixel circuit 11a on the substrate may at least partially overlap with the orthographic projection of the first light-emitting elements 13a and 13b on the substrate. The orthographic projection of the first pixel circuit 11b on the substrate may at least partially overlap with the orthographic projection of the first light-emitting element 13c on the substrate. The orthographic projection of the first pixel circuit 11c on the substrate may at least partially overlap with the orthographic projection of the first light-emitting elements 13d and 13e on the substrate. The orthographic projection of the first pixel circuit 11d on the substrate may at least partially overlap with the orthographic projection of the first light-emitting element 13f on the substrate. In this example, the orthographic projections of the first pixel circuit and the first light-emitting element to which it is connected on the substrate may partially overlap, or may not overlap.

[0168] In some examples, as shown in Figure 5, the four second pixel circuits of the second display unit may include: second pixel circuits 12a, 12b, 12c and 12d arranged in sequence along the first direction X. The second pixel circuit 12a can be connected to a second light-emitting element 14a that emits a first color light, and is configured to drive the second light-emitting element 14a to emit light. The second pixel circuit 12b can be connected to a second light-emitting element 14b that emits a second color light, and is configured to drive the second light-emitting element 14b to emit light. The second pixel circuit 12c can be connected to a second light-emitting element 14c that emits a third color light, and is configured to drive the second light-emitting element 14c to emit light. The second pixel circuit 12d can be connected to a second light-emitting element 14d that emits a second color light, and is configured to drive the second light-emitting element 14d to emit light. In this example, the four second pixel circuits can all be connected to the second light-emitting elements in a one-to-one drive manner.

[0169] In some examples, as shown in FIG5 , the orthographic projection of the second pixel circuit 12a on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14a on the substrate. The orthographic projection of the second pixel circuit 12b on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14b on the substrate. The orthographic projection of the second pixel circuit 12c on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14c on the substrate. The orthographic projection of the second pixel circuit 12d on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14d on the substrate. In this example, the orthographic projections of the second pixel circuit and the second light-emitting element to which it is connected on the substrate may at least partially overlap.

[0170] In some examples, as shown in FIG5 , the four first pixel circuits of the first display unit can be aligned with the four second pixel circuits of the second display unit in the second direction Y. For example, the first pixel circuit 11 a and the second pixel circuit 12 a can be aligned in the second direction Y, the first pixel circuit 11 b and the second pixel circuit 12 b can be aligned in the second direction Y, the first pixel circuit 11 c and the second pixel circuit 12 c can be aligned in the second direction Y, and the first pixel circuit 11 d and the second pixel circuit 12 d can be aligned in the second direction Y.

[0171] In some examples, as shown in FIG5 , the first pixel circuit 11 a of the first display unit and the second pixel circuit 12 a of the second display unit can be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (e.g., data line DL(j)). The first pixel circuit 11 b of the first display unit and the second pixel circuit 12 b of the second display unit can be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (e.g., data line DL(j+1)). The first pixel circuit 11 c of the first display unit and the second pixel circuit 12 c of the second display unit can be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (e.g., data line DL(j+2)). The first pixel circuit 11 d of the first display unit and the second pixel circuit 12 d of the second display unit can be located in the same column of pixel circuits and connected to the same data line extending along the second direction Y (e.g., data line DL(j+3)). Wherein, j can be a positive integer.

[0172] In some examples, as shown in FIG5 , the four first pixel circuits of the first display unit may be arranged in the same row of pixel circuits and connected to the same first scan line (e.g., the first scan line GL1(f)) extending along the first direction X. The four second pixel circuits of the second display unit may be arranged in the same row of pixel circuits and connected to the same first scan line (e.g., the first scan line GL1(f+1)) extending along the first direction X. Wherein, f may be a positive integer.

[0173] In some examples, as shown in FIG4 and FIG5, the plurality of second light-emitting elements of the second display area A2 can be arranged in an RGBG manner, and the second pixel circuit and the second light-emitting element can be in a one-to-one correspondence. The plurality of first light-emitting elements of the first display area A1 can be arranged in a Pentile RGB manner, and by reducing the number of first pixel circuits, four first pixel circuits can drive six first light-emitting elements to emit light. With one RGB unit as a first pixel unit and one RGBG unit as a second pixel unit, two first pixel units can be set in the pixel space corresponding to one second pixel unit, so that the resolution (PPI) of the first display area can be equivalent to the resolution of the second display area. Moreover, since the display effect of the RGB arrangement with a resolution (PPI) of a can be equivalent to a PPI of a×[2 ∧ (1 / 2)], therefore, in this example, on the basis of deleting pixel circuits in the first display area to improve the light transmittance of the first display area, by setting the arrangement of the first light-emitting elements to be different from the arrangement of the second light-emitting elements, the display effect of the first display area can be optimized, thereby improving the display uniformity of the first display area and the second display area.

[0174] Figure 6 is a partial top view schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 6 illustrates a partial top view schematic diagram of two rows (e.g., row k and row k+1) and two columns (e.g., column h and column h+1) of display island areas, where k and h are both integers greater than 0. In some examples, as shown in Figure 6, the first display area may include: multiple display island areas and multiple light-transmitting areas A12. A single light-transmitting area A12 may be surrounded by two display island areas in the first direction X and by two display island areas in the second direction Y.

[0175] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, and a circuit structure layer and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer may be located on a side of the circuit structure layer away from the substrate. The circuit structure layer of the first display area may include: a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include: a plurality of first light-emitting elements.

[0176] In some examples, the circuit structure layer may include: a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A buffer layer may be disposed between the shielding layer and the first semiconductor layer. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer may be disposed on the side of the sixth conductive layer away from the substrate. In some examples, the buffer layer, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to ninth insulating layers may be organic insulating layers. This embodiment is not limited to this. In other examples, the shielding layer may be omitted. In other examples, an insulating layer may be disposed between the fourth and fifth conductive layers. In other examples, two insulating layers may be provided on the side of the sixth conductive layer away from the substrate to improve the planarization effect of the anode layer.

[0177] In some examples, the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer, which are sequentially arranged on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light of a corresponding color when driven by the anode layer and the cathode layer.

[0178] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0179] The “A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The “thickness” of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The “shape of A” mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0180] The following describes the film layer of the circuit structure layer using four first pixel circuits (for example, including first pixel circuits 11a, 11b, 11c, and 11d) in a display island area of ​​the first display area (for example, a display island area located in the kth row and hth column) as an example. This example is described using the first pixel circuit as the aforementioned 8T1C structure. The first pixel circuit 11a may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a storage capacitor; the first pixel circuit 11b may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, and a storage capacitor. The connection relationship between the eight transistors and the storage capacitor in each first pixel circuit can be referred to the equivalent circuit diagram shown in FIG2 .

[0181] In some examples, the process of preparing a display substrate may include the following steps.

[0182] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The material of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0183] (2) Forming a shielding layer. In some examples, a shielding film is deposited on a substrate and patterned through a patterning process to form a shielding layer disposed on the substrate. In some examples, the shielding layer may also be referred to as a bottom shielding metal (BSM).

[0184] Figure 7 is a schematic diagram of the first display area after the shielding layer is formed in Figure 6. In some examples, as shown in Figure 7, the shielding layer of the first display area may include at least: shielding blocks 300 located in the display islands. Each display island may be provided with one shielding block 300. The shielding blocks 300 in adjacent rows of display islands in adjacent columns of display islands may be interconnected as a single unit. Multiple shielding blocks 300 in the first display area may be interconnected as a single unit.

[0185] In some examples, as shown in FIG7 , the obstructing block 300 located within the display island area may have two first hollow portions 301, two second hollow portions 302, two third hollow portions 303, and two fourth hollow portions 304. The obstructing block 300 may be substantially symmetrical about the second centerline O2. The two first hollow portions 301 may be substantially symmetrical about the second centerline O2, and the single first hollow portion 301 may be substantially symmetrical about the first centerline O1 or the third centerline O3. The second hollow portion 302, the third hollow portion 303, and the fourth hollow portion 304 may be located on one side of the first hollow portion 301 opposite the second direction Y. The fourth hollow portion 304 may be located between the second hollow portion 302 and the third hollow portion 303 in the first direction X. One second hollow portion 302 and one third hollow portion 303 may be substantially symmetrical about the first centerline O1, and another second hollow portion 302 and another third hollow portion 303 may be substantially symmetrical about the third centerline O3. One fourth hollow portion 304 can be substantially symmetrical about the first center line O1, and another fourth hollow portion 304 can be substantially symmetrical about the third center line O3. In this example, providing a light shielding block in the display island region can provide a light shielding effect for the first type transistor of the first pixel circuit in the display island region. Furthermore, providing a hollow portion in the light shielding block can avoid the use of large areas of metal, which could cause parasitic capacitance between the metal film layers and other metal layers, thereby affecting the display effect.

[0186] In some examples, the shielding layer can extend to the peripheral area and be electrically connected to the first power supply line in the peripheral area to receive the first voltage signal to avoid affecting other signal lines.

[0187] (3) Forming a first semiconductor layer. In some examples, a buffer film and a first semiconductor film are sequentially deposited on the substrate having the aforementioned pattern, and the first semiconductor film is patterned by a patterning process to form a buffer layer and a first semiconductor layer disposed on the buffer layer. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0188] Fig. 8A is a schematic diagram of the first display region after the first semiconductor layer is formed in Fig. 6. Fig. 8B is a schematic diagram of the first semiconductor layer in Fig. 8A. In some examples, as shown in Figures 8A and 8B, the first semiconductor layer of the first display area may include at least: active layers of multiple first-type transistors of multiple first pixel circuits (for example, including: the first active layer 310a of the first transistor of the first pixel circuit 11a, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor; the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor).

[0189] In some examples, as shown in Figures 8A and 8B, the first semiconductor layer patterns of the first pixel circuits 11a and 11b within the display island region can be substantially symmetrical about the first center line O1, the first semiconductor layer patterns of the first pixel circuits 11b and 11c can be substantially symmetrical about the second center line O2, and the first semiconductor layer patterns of the first pixel circuits 11c and 11d can be substantially symmetrical about the third center line O3. The first semiconductor layer patterns of the first pixel circuits 11a and 11b and the first semiconductor layer patterns of the first pixel circuits 11c and 11d can be substantially symmetrical about the second center line O2. The first semiconductor layer patterns of different display island regions can be independent of each other.

[0190] In some examples, as shown in Figures 8A and 8B, the third active layer, fourth active layer, fifth active layer, sixth active layer, and seventh active layer of the four first pixel circuits in the display island region can be interconnected as an integrated structure. Specifically, the seventh active layer 370a of the first pixel circuit 11a can be directly connected to the seventh active layer 370b of the first pixel circuit 11b, the fifth active layer 350b of the first pixel circuit 11b can be directly connected to the fifth active layer of the first pixel circuit 11c, and the seventh active layer of the first pixel circuit 11c can be directly connected to the seventh active layer of the first pixel circuit 11d.

[0191] In some examples, as shown in FIG8A and FIG8B , the first semiconductor layer pattern of the first pixel circuit 11a is used as an example for description. The first active layer 310a and the fourth active layer 340a of the first pixel circuit 11a can be located on one side of the third active layer 330a along the second direction Y, and the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a can be located on a side of the third active layer 330a in the opposite direction of the second direction Y. The first active layer 310a, the sixth active layer 360a, and the seventh active layer 370a can be aligned in the second direction Y.

[0192] In some examples, the third active layer 330a may be approximately U-shaped, the fourth active layer 340a may be approximately I-shaped, and the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a may be approximately L-shaped. However, this embodiment is not limited to this. The arrangement and shape of the first semiconductor layer pattern of the first pixel circuits 11b, 11c, and 11d are similar to those of the first pixel circuit 11a, and are therefore not further described herein.

[0193] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0194] In some examples, as shown in FIG8A , the orthographic projection of the blocking layer of the first display area on the substrate may partially overlap with the orthographic projection of the first semiconductor layer on the substrate. The orthographic projection of the blocking block 300 of the display island area on the substrate may cover the orthographic projections of the third active layer, the fourth active layer, the fifth active layer, the sixth active layer, the seventh active layer and the eighth active layer of the four first pixel circuits on the substrate, and partially overlap with the orthographic projection of the first active layer on the substrate. For example, the orthographic projection of the blocking block 300 on the substrate may cover the orthographic projection of the channel region of the active layer of the first type transistor of the four first pixel circuits on the substrate. In this example, by setting a blocking layer to block the channel region of the active layer of the first type transistor located in the first semiconductor layer, it is possible to prevent external light from affecting the transistor of the pixel circuit, thereby ensuring the performance of the transistor.

[0195] (4) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the first insulating layer may also be referred to as a first gate insulating layer.

[0196] FIG9A is a schematic diagram of the first display area after the first conductive layer is formed in FIG6 . FIG9B is a schematic diagram of the first conductive layer and the first semiconductor layer in FIG9A . FIG9C is a schematic diagram of the first conductive layer in FIG9A . In some examples, as shown in FIG9A to FIG9C , the first conductive layer in the first display area may include at least: first scan transmission segments 251 of a plurality of first scan lines (e.g., including first scan lines GL1(k) and GL1(k+1)), light emission control transmission segments 261 of a plurality of light emission control lines (e.g., including light emission control lines EML(k) and EML(k+1)), a plurality of first reset control lines (e.g., including first reset control lines RST1(k), RST1(k+1), and RST1(k+2)), a plurality of second reset control lines (e.g., including second reset control lines RST2(k-1), RST2(k), and RST2(k+1)), and first electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including first electrodes 391a and 391b).

[0197] In some examples, the first scan transfer segment 251 and the emission control transfer segment 261 can be located in the display island region where the connected first pixel circuit is located. The first scan transfer segment 251 of the first scan line GL1(k) can be located on one side of the first electrode (e.g., first electrodes 391a, 391b) of the storage capacitor of the first pixel circuit in the second direction Y. The first reset control line RST1(k) can be located on one side of the first scan transfer segment 251 of the first scan line GL1(k) in the second direction Y. The emission control transfer segment 261 of the emission control line EML(k) can be located on one side of the first electrode (e.g., first electrodes 391a, 391b) of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y. The second reset control line RST2(k) can be located on one side of the emission control transfer segment 261 of the emission control line EML(k) in the opposite direction of the second direction Y. The first reset control line RST1(k+1) can be located on one side of the second reset control line RST2(k) in the opposite direction of the second direction Y.

[0198] In some examples, the first reset control line RST1(k) can be located on one side of the light-transmitting area A12 in the kth row and h+1th column in the second direction Y. The segment of the first reset control line RST1(k) near the light-transmitting area A12 can be substantially straight and extend along the first direction X. The second reset control line RST2(k) can be located on one side of the light-transmitting area A12 in the kth row and h+1th column in the opposite direction of the second direction Y. The segment of the second reset control line RST2(k) near the light-transmitting area A12 can be substantially straight and extend along the first direction X. The first scan line GL1(k) bypasses the light-transmitting area A12 from one side of the light-transmitting area A12 in the second direction Y using the first scan connection line. The emission control line EML(k) can bypass the light-transmitting area A12 from the opposite side of the second direction Y using the emission control connection line. The routing arrangement of the first conductive layer in this example can help increase the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0199] In some examples, the shape of the line segment of the first reset control line RST1(k) located in the display island region where the connected first pixel circuit is located can be substantially a zigzag line extending along the first direction X. For example, in the display island region at the kth row and hth column, the overlapping region between the first reset control line RST1(k) and the first active layers of the four first pixel circuits can serve as the gates of the first transistors of the four first pixel circuits (e.g., including the gate of the first transistor 31a and the gate of the first transistor 31b).

[0200] In some examples, the shape of the first scan transmission segment 251 of the first scan line GL1(k) can be substantially a zigzag line extending along the first direction X. For example, in the display island region at the kth row and hth column, the overlapping region of the first scan transmission segment 251 of the first scan line GL1(k) and the fourth active layers of the four first pixel circuits can serve as the gates of the fourth transistors of the four first pixel circuits (e.g., including the gates of the fourth transistor 34a and the gates of the fourth transistor 34b).

[0201] In some examples, the shape of the light-emission control transmission segment 261 of the light-emission control line EML(k) can be approximately a zigzag line extending along the first direction X. For example, in the display island area in the kth row and hth column, the overlapping region of the light-emission control transmission segment 261 of the light-emission control line EML(k) and the fifth active layers of the four first pixel circuits can serve as the gates of the fifth transistors of the four first pixel circuits (e.g., including the gates of the fifth transistors 35a and 35b), and the overlapping region of the light-emission control transmission segment 261 of the light-emission control line EML(k) and the sixth active layers of the four first pixel circuits can serve as the gates of the sixth transistors of the four first pixel circuits (e.g., including the gates of the sixth transistors 36a and 36b).

[0202] In some examples, the shape of the line segment of the second reset control line RST2(k) located in the display island region where the connected first pixel circuit is located can be approximately a zigzag line extending along the first direction X. For example, in the display island region at the kth row and hth column, the overlapping region between the second reset control line RST2(k) and the seventh active layer of the four first pixel circuits can serve as the gates of the seventh transistors of the four first pixel circuits (e.g., including the gates of the seventh transistors 37a and 37b), and the overlapping region between the second reset control line RST2(k) and the eighth active layer of the four first pixel circuits can serve as the gates of the eighth transistors of the four first pixel circuits (e.g., including the gates of the eighth transistors 38a and 38b).

[0203] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a can also serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitor of the first pixel circuit 11b can also serve as the gate of the third transistor 33b. The orthographic projections of the first electrodes 391a and 391b on the substrate can be approximately rectangular. This embodiment is not limited to this.

[0204] (5) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0205] FIG10A is a schematic diagram of the first display area after the second conductive layer is formed in FIG6 . FIG10B is a schematic diagram of the second conductive layer in FIG10A . In some examples, as shown in FIG10A and FIG10B , the second conductive layer in the first display area may include at least: second scanning auxiliary transmission segments 271 of a plurality of second scanning auxiliary lines (e.g., including second scanning auxiliary lines GL2b(k), GL2b(k)), second electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including second electrodes 392a, 392b), and initial signal connection segments 292 of a plurality of third initial signal lines (e.g., including third initial signal lines INIT3(k-1), INIT3(k), INIT3(k+1)).

[0206] In some examples, the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) can be located in the display island region where the connected first pixel circuit is located. The shape of the second scanning auxiliary transmission segment 271 can be substantially a zigzag line extending along the first direction X. For example, in the display island region in the kth row and hth column, the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) can be located on one side of the second electrode (e.g., second electrodes 392a and 392b) of the storage capacitor of the first pixel circuit in the second direction Y.

[0207] In some examples, within the display island area, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate can be approximately a rectangular structure with a hollow area, and the orthographic projection of the hollow area on the substrate can be approximately a rectangle, and the rectangle can have rounded corners or chamfered corners. The second electrode 392a of the storage capacitor of the first pixel circuit 11a and the second electrode 392b of the storage capacitor of the first pixel circuit 11b can be electrically connected through a first plate connecting block 392-1, the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c can be electrically connected through a second plate connecting block 392-2, and the second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d can be electrically connected through another first plate connecting block 392-1. The side of the second electrode 392a of the storage capacitor of the first pixel circuit 11a away from the first pixel circuit 11b can be connected to a second plate connecting block 392-2, and the side of the second electrode of the storage capacitor of the first pixel circuit 11d away from the first pixel circuit 11c can be electrically connected to another second plate connecting block 392-2. The length of the first plate connecting block 392-1 along the second direction Y can be less than the length of the second plate connecting block 392-2 along the second direction Y. The second electrode of the storage capacitor can subsequently be electrically connected to the first power line through the second plate connecting block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits in the first display island area can be an integrated structure that is interconnected, which is conducive to ensuring uniform transmission of the first voltage signal along the first direction X.

[0208] In some examples, the initial signal connection segment 292 of the third initial signal line INIT3(k) can be located in an adjacent row and column display island area of ​​the display island area where the connected first pixel circuit is located. For example, the initial signal connection segment 292 of the third initial signal line INIT3(k) connected to the first pixel circuit in the display island area of ​​the kth row and hth column can be located in the display island area of ​​the k+1th row and h+1th column, and can be located on the side of the light-transmitting area A12 of the kth row and h+1th column opposite to the second direction Y. The shape of the initial signal connection segment 292 can be roughly straight and extend along the first direction X. The initial signal connection segment 292 can be configured to connect the initial signal transmission segments in the adjacent display island areas formed subsequently to realize the transmission of the third initial signal along the first direction X within the first display area.

[0209] (6) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may also be referred to as a third gate insulating layer.

[0210] Figure 11A is a schematic diagram of the first display area after the second semiconductor layer is formed in Figure 6. Figure 11B is a schematic diagram of the second semiconductor layer in Figure 11A. In some examples, as shown in Figures 11A and 11B, the second semiconductor layer of the first display area may include at least: active layers of the second type transistors of multiple first pixel circuits (for example, including: second active layer 320a of second transistor 32a of first pixel circuit 11a, second active layer 320b of second transistor 32b of first pixel circuit 11b).

[0211] In some examples, within the display island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be approximately symmetrical about the first center line O1, the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be approximately symmetrical about the second center line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be approximately symmetrical about the third center line O3. The second semiconductor layer patterns of the first pixel circuits 11a and 11b and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be approximately symmetrical about the second center line O2.

[0212] In some examples, the second active layers 320a and 320b can be shaped approximately like an inverted L. The overlapping region between the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) and the second active layer 320a can serve as the bottom gate of the second transistor 32a, and the overlapping region between the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) and the second active layer 320b can serve as the bottom gate of the second transistor 32b.

[0213] In some examples, the orthographic projection of the second semiconductor layer on the substrate may partially overlap with the orthographic projection of the shielding layer on the substrate. The orthographic projection of the channel region of the second active layer on the substrate may not overlap with the orthographic projection of the shielding layer on the substrate. For example, the orthographic projections of the channel regions of the second active layers 320a and 320b on the substrate may be located within the orthographic projection of the first hollow region 301 on the substrate.

[0214] (7) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fourth insulating layer may also be referred to as a fourth gate insulating layer.

[0215] FIG12A is a schematic diagram of the first display area after the third conductive layer is formed in FIG6 . FIG12B is a schematic diagram of the third conductive layer in FIG12A . In some examples, as shown in FIG12A and FIG12B , the third conductive layer in the first display area may include at least: a second scan transmission segment 281 of a plurality of second scan lines (e.g., including second scan lines GL2(k) and GL2(k+1)), an initial signal transmission segment 291 of a plurality of first initial signal lines (e.g., including first initial signal lines INIT1(k), INIT1(k+1), and INIT1(k+2)), a plurality of second initial signal lines (e.g., including second initial signal lines INIT2(k-1), INIT2(k), and INIT2(k+1)), and a plurality of third initial signal lines (e.g., including third initial signal lines INIT3(k) and INIT3(k+1)).

[0216] In some examples, within the display island area, the first initial signal line INIT1(k) and the second scan transmission segment 281 of the second scan line GL2(k) may be located on one side of the storage capacitor along the second direction Y, and the initial signal transmission segments 291 of the second initial signal line INIT2(k) and the third initial signal line INIT3(k) may be located on a side of the storage capacitor in a direction opposite to the second direction Y. The first initial signal line INIT1(k) may be located on one side of the second scan transmission segment 281 of the second scan line GL2(k), the initial signal transmission segment 291 of the third initial signal line INIT3(k) and the second initial signal line INIT2(k) may be located on a side of the second scan transmission segment 281 of the second scan line GL2(k) in a direction opposite to the second direction Y, and the second initial signal line INIT2(k) may be located on a side of the initial signal transmission segment 291 of the third initial signal line INIT3(k) in a direction opposite to the second direction Y.

[0217] In some examples, the first initial signal line INIT1(k) can be located on one side of the light-transmitting area A12 in the kth row and h+1th column in the second direction Y. The second initial signal line INIT2(k) can be located on the side of the light-transmitting area A12 in the kth row and h+1th column in the opposite direction of the second direction Y. The shape of the line segment of the first initial signal line INIT1(k) located within the display island region where the first pixel circuit connected thereto is located can be approximately a zigzag shape extending along the first direction X. The shape of the line segment of the first initial signal line INIT1(k) adjacent to the light-transmitting area A12 can be approximately a straight line extending along the first direction X. The shape of the line segment of the second initial signal line INIT2(k) located within the display island region where the first pixel circuit connected thereto is located can be approximately a zigzag shape extending along the first direction X. The shape of the line segment of the second initial signal line INIT2(k) adjacent to the light-transmitting area A12 can be approximately a straight line extending along the first direction X. The routing arrangement of the third conductive layer in this example can help increase the area of ​​the light-transmitting area and improve the light transmittance of the first display area.

[0218] In some examples, the orthographic projection of the first initial signal line INIT1(k) on the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(k) on the substrate. For example, the orthographic projection of the first initial signal line INIT1(k) on the substrate may include the orthographic projection of the first reset control line RST1(k) on the substrate. The orthographic projection of the second scan transmission segment 281 of the second scan line GL2(k) on the substrate may partially overlap with the orthographic projection of the second scan auxiliary transmission segment 271 of the second scan auxiliary line GL2b(k) on the substrate. The orthographic projection of the initial signal transmission segment 291 of the third initial signal line INIT3(k) on the substrate may partially overlap with the orthographic projection of the emission control transmission segment 261 of the emission control line EML(k) on the substrate. The orthographic projection of the second initial signal line INIT2(k) on the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(k) on the substrate. For example, the orthographic projection of the second initial signal line INIT2(k) on the substrate may include the orthographic projection of the second reset control line RST2(k) on the substrate. This example utilizes a stacked design for routing traces on different conductive layers (e.g., the first conductive layer, the second conductive layer, and the third conductive layer) to avoid excessive routing space, saving wiring space and thereby improving light transmittance in the first display area.

[0219] (8) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate having the aforementioned pattern, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0220] FIG13 is a schematic diagram of the first display area after the fifth insulating layer is formed in FIG6 . In some examples, as shown in FIG13 , the fifth insulating layer of the first display area may be provided with a plurality of vias, such as first-type vias (e.g., first to nineteenth vias V1 to V19 ), second-type vias (e.g., twenty-first via V21 , twenty-second via V22 , thirty-fifth via V35 , and thirty-eighth via V38 ), third-type vias (e.g., twenty-third via V23 , twenty-fourth via V24 , thirty-seventh via V37 , and fortieth via V40 ), a plurality of fourth-type vias (e.g., thirty-first to thirty-fourth vias V31 to V34 ), and a plurality of fifth-type vias (e.g., twenty-fifth to twenty-ninth vias V29 , thirty-sixth via V36 , and thirty-ninth via V39 ).

[0221] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first type via can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second type via can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer within the third type via can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer and the fourth insulating layer within the fourth type via can be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer within the fifth type via can be removed to expose a portion of the surface of the third conductive layer.

[0222] In some examples, the first type via, the second type via, and the third type via can be formed by a same patterning process, and the fourth type via and the fifth type via can be formed by a same patterning process.

[0223] (9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0224] FIG14A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG6 . FIG14B is a schematic diagram of the fourth conductive layer in FIG14A . In some examples, as shown in FIG14A and FIG14B , the fourth conductive layer in the first display area may include at least: a plurality of pixel connection electrodes (e.g., including the first pixel connection electrode 401 to the seventeenth pixel connection electrode 417 ), a plurality of routing transfer electrodes (e.g., including the first routing transfer electrode 283 and the second routing transfer electrode 293 ), a plurality of first scan lines (e.g., including the first scan line GL1(k) and GL1(k+1)), and a plurality of emission control lines (e.g., including the emission control lines EML(k) and EML(k+1)).

[0225] In some examples, the shape of the first pixel connection electrode 401 may be substantially rectangular.The first pixel connection electrode 401 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the third via hole V3.

[0226] In some examples, the second pixel connection electrode 402 can be shaped substantially like a strip extending along the second direction Y. One end of the second pixel connection electrode 402 can be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a through a thirty-first via hole V31, and the other end can be electrically connected to the first electrode 391a of the storage capacitor of the first pixel circuit 11a through a twenty-first via hole V21. The second pixel connection electrode 402 is electrically connected to the gate of the third transistor 33a, the first electrode 391a of the storage capacitor, and the first electrode of the second transistor 32a. The second pixel connection electrode 402 can serve as the first node of the first pixel circuit 11a.

[0227] In some examples, the third pixel connection electrode 403 can be shaped substantially like a strip extending along the second direction Y. One end of the third pixel connection electrode 403 can be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through the second via hole V2, and the other end can be electrically connected to the second active layer 320a of the second transistor 32a through the thirty-second via hole V32. The third pixel connection electrode 403 can also be electrically connected to the third active layer of the third transistor 33a through the sixth via hole V6. The third pixel connection electrode 403 can serve as a third node of the first pixel circuit 11a.

[0228] In some examples, the fourth pixel connection electrode 404 may be shaped substantially like a zigzag line extending along the second direction Y. The fourth pixel connection electrode 404 may be electrically connected to the fourth active layer 340 a of the fourth transistor 34 a of the first pixel circuit 11 a through a fourth via hole V4, and may also be electrically connected to the eighth active layer 380 a of the eighth transistor 38 a through an eighth via hole V8.

[0229] In some examples, the fifth pixel connection electrode 405 may be shaped substantially like a strip extending along the second direction Y. The fifth pixel connection electrode 405 may be electrically connected to the fifth active layer 350a of the fifth transistor 35a of the first pixel circuit 11a through a fifth via hole V5, and may also be electrically connected to the second plate connection block 392-2 connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a through a twenty-third via hole V23, thereby achieving electrical connection with the second electrode 392a of the storage capacitor of the first pixel circuit 11a.

[0230] In some examples, the shape of the sixth pixel connection electrode 406 may be substantially rectangular.The sixth pixel connection electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through a seventh via hole V7.

[0231] In some examples, the shape of the seventh pixel connection electrode 407 can be substantially L-shaped. The seventh pixel connection electrode 407 can be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a through a ninth via hole V9, and can also be electrically connected to the initial signal transmission section 291 of the third initial signal line INIT3(k) through a twenty-sixth via hole V26.

[0232] In some examples, the eighth pixel connection electrode 408 may be shaped substantially like a strip extending along the second direction Y. The eighth pixel connection electrode 408 may be electrically connected to the seventh active layer 370 a of the seventh transistor 37 a of the first pixel circuit 11 a through a tenth via hole V10, and may also be electrically connected to the second initial signal line INIT2 (k) through a twenty-seventh via hole V27.

[0233] In some examples, the ninth pixel connection electrode 409 may be shaped approximately like a flat figure 8. One end of the ninth pixel connection electrode 409 may be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through the first via hole V1, and the other end may be electrically connected to the first initial signal line INIT1(k) through the twenty-fifth via hole V25.

[0234] In some examples, the tenth pixel connection electrode 410 may be shaped approximately like a flat figure 8. One end of the tenth pixel connection electrode 410 may be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b through the eleventh via hole V11, and the other end may be electrically connected to the first initial signal line INIT1(k) through the twenty-eighth via hole V28.

[0235] In some examples, the eleventh pixel connection electrode 411 may be substantially rectangular in shape. The eleventh pixel connection electrode 411 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the thirteenth via hole V13.

[0236] In some examples, the twelfth pixel connection electrode 412 can be shaped substantially like a strip extending along the second direction Y. One end of the twelfth pixel connection electrode 412 can be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via a thirty-third via hole V31, and the other end can be electrically connected to the first electrode 391b of the storage capacitor of the first pixel circuit 11b via a twenty-second via hole V22. The twelfth pixel connection electrode 412 is electrically connected to the gate of the third transistor 33b, the first electrode 391b of the storage capacitor, and the first electrode of the second transistor 32b. The twelfth pixel connection electrode 412 can serve as the first node of the first pixel circuit 11b.

[0237] In some examples, the thirteenth pixel connection electrode 413 may be shaped substantially like a strip extending along the second direction Y. One end of the thirteenth pixel connection electrode 413 may be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b via a twelfth via hole V12, and the other end may be electrically connected to the second active layer 320b of the second transistor 32b via a thirty-fourth via hole V34. The thirteenth pixel connection electrode 413 may also be electrically connected to the third active layer 330b of the third transistor 33b via a sixteenth via hole V16. The thirteenth pixel connection electrode 413 may serve as a third node of the first pixel circuit 11b.

[0238] In some examples, the shape of the fourteenth pixel connection electrode 414 can be substantially a zigzag shape extending along the second direction Y. The fourteenth pixel connection electrode 414 can be electrically connected to the fourth active layer 340 b of the fourth transistor 34 b of the first pixel circuit 11 b through the fourteenth via hole V14, and can also be electrically connected to the eighth active layer 380 b of the eighth transistor 38 b through the eighteenth via hole V18.

[0239] In some examples, the shape of the fifteenth pixel connection electrode 415 can be substantially a strip extending along the second direction Y. The fifteenth pixel connection electrode 415 can be electrically connected to the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b through the fifteenth via hole V15, and can also be electrically connected to the second plate connection block 392-2 connected to the second electrode 392b of the storage capacitor of the first pixel circuit 11b through the twenty-fourth via hole V24, thereby achieving electrical connection with the second electrode 392b of the storage capacitor of the first pixel circuit 11b.

[0240] In some examples, the shape of the sixteenth pixel connection electrode 416 may be substantially rectangular.The sixteenth pixel connection electrode 416 may be electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the seventeenth via hole V17.

[0241] In some examples, the shape of the seventeenth pixel connection electrode 417 can be substantially L-shaped. The seventeenth pixel connection electrode 417 can be electrically connected to the eighth active layer 380b of the eighth transistor 38b of the first pixel circuit 11b through a nineteenth via hole V19, and can also be electrically connected to the initial signal transmission section 291 of the third initial signal line INIT3(k) through a twenty-ninth via hole V29.

[0242] In some examples, within the display island area, the first pixel circuits 11a and 11b can be roughly symmetrical about the second center line O2, the first pixel circuits 11c and 11d can be roughly symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, the first pixel circuits 11c and 11d can be roughly symmetrical about the first center line O1.

[0243] In some examples, the shape of the first routing electrode 283 can be substantially L-shaped. The first routing electrode 283 can be connected to the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) through the thirty-seventh via V37, and can also be connected to the second scanning transmission segment 281 of the second scanning line GL2(k) through the thirty-sixth via V36.

[0244] In some examples, the second routing transition electrode 293 can be roughly rectangular in shape. The second routing transition electrode 293 can be connected to the initial signal transmission segment 291 located in the third conductive layer through the thirty-ninth via V39, and can also be connected to the initial signal connection segment 292 located in the second conductive layer through the fortieth via V40. In this example, the two ends of the initial signal connection segment 292 can be connected to the initial signal transmission segments 291 located in two adjacent display islands in the same row through the second routing transition electrode 293, thereby enabling transmission of the third initial signal along the first direction X.

[0245] In some examples, the shape of the first scan connection segment 252 of the first scan line GL1(k) can be roughly a zigzag extending along the first direction X. The first scan connection segment 252 of the first scan line GL1(k) can be located on one side of the light-transmitting area A12 in the k-th row and h+1 column along the second direction Y. The first scan connection segment 252 can, for example, be located within the display island in the k-1-th row and h+1 column. The orthographic projection of the first scan connection segment 252 on the substrate can partially overlap with the orthographic projections of the first reset control line RST1(k) and the first initial signal line INIT1(k) on the substrate. One end of the first scan connection segment 252 can be connected to the first scan transmission segment 251 located in the first conductive layer in the display island in the k-th row and h column via the thirty-fifth via V35, and the other end can be connected to the first scan transmission segment in the display island in the k-th row and h+1 column. The first scan connection segment 252 can connect the first scan transmission segments in two adjacent display islands along the first direction X, thereby enabling transmission of the first scan signal along the first direction X.

[0246] In some examples, the shape of the light-emitting control connection segment 262 of the light-emitting control line EML(k) can be approximately a zigzag line extending along the first direction X. The light-emitting control connection segment 262 of the light-emitting control line EML(k) can be located on a side of the light-transmitting area A12 in the kth row and h+1 column opposite to the second direction Y. The light-emitting control connection segment 262 can, for example, be located in the display island area in the k+1th row and h+1 column. The orthographic projection of the light-emitting control connection segment 262 on the substrate can partially overlap with the orthographic projections of the second reset control line RST2(k), the second initial signal line INIT2(k), and the initial signal connection segment 292 on the substrate. One end of the light-emitting control connection segment 262 can be connected to the light-emitting control transmission segment 261 located in the first conductive layer in the display island area in the kth row and hth column through the thirty-eighth via V38, and the other end can be connected to the light-emitting control transmission segment in the display island area in the kth row and h+1 column. The light-emitting control connecting segment 262 can connect the light-emitting control transmission segments in two adjacent display islands along the first direction X, thereby realizing the transmission of the light-emitting control signal along the first direction X.

[0247] (10) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a seventh insulating film is coated. The seventh insulating film and the sixth insulating film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0248] Figure 15 is a schematic diagram of the first display area after the seventh insulating layer is formed in Figure 6. In some examples, as shown in Figure 15, the seventh insulating layer in the first display area can be provided with multiple vias, such as vias 41 to 47 (V41 to V47). The seventh and sixth insulating layers within vias 41 to 47 (V41 to V47) can be removed, exposing a portion of the surface of the fourth conductive layer.

[0249] (11) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0250] FIG16A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG6 . FIG16B is a schematic diagram of the fifth conductive layer in FIG16A . In some examples, as shown in FIG16A and FIG16B , the fifth conductive layer in the first display area may include at least: a plurality of data lines (e.g., data lines DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7), and DL(j+8)), a plurality of first anode connection electrodes (e.g., first anode connection electrodes 422a, 422b, 422c, and 422d), a plurality of first power connection electrodes (e.g., first power connection electrodes 423a, 423b, and 423c), a plurality of first shield electrodes (e.g., first shield electrodes 421a and 421b), and second scan connection segments 282 of a plurality of second scan lines (e.g., second scan lines GL2(k) and GL2(k+1)). Where j is an integer greater than 0.

[0251] In some examples, the plurality of data lines may be roughly in the shape of a broken line extending along the second direction Y. The four first pixel circuits in each display island area may be electrically connected to the four data lines in a one-to-one correspondence. The data line DL(j) may be electrically connected to the first pixel connection electrode 401 through the forty-first via V41, thereby being electrically connected to the fourth transistor of the first pixel circuit 11a. The data line DL(j+1) may be electrically connected to the eleventh pixel connection electrode 411 through the forty-fifth via V45, thereby being electrically connected to the fourth transistor of the first pixel circuit 11b. The data line DL(j+2) may be electrically connected to the fourth transistor of the first pixel circuit 11c. The data line DL(j+3) may be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0252] In some examples, the four data lines electrically connected to the four first pixel circuits in the display island area can be divided into two groups to bypass the light-transmitting area A12 adjacent to the display island area in the second direction Y. For example, the data line DL(j) connected to the first pixel circuit 11a and the data line DL(j+1) connected to the first pixel circuit 11b can bypass the light-transmitting area A12 located in the hth column from the side opposite to the first direction X, and the data line DL(j+2) connected to the first pixel circuit 11c and the data line DL(j+3) connected to the first pixel circuit 11d can bypass the light-transmitting area A12 located in the hth column from the side of the first direction X. In this example, by setting the data lines to bend and bypass the light-transmitting area, it is beneficial to reduce the space occupied by the wiring, thereby improving the light transmittance of the first display area.

[0253] In some examples, the shape of the first anode connection electrodes 422a, 422b, 422c, and 422d can be substantially rectangular. The first anode connection electrodes 422a and 422b can be located between the data lines DL(j) and DL(j+1), and the first anode connection electrodes 422c and 422d can be located between the data lines DL(j+2) and DL(j+3).

[0254] In some examples, the first anode connection electrode 422a can be electrically connected to the sixth pixel connection electrode 406 through the forty-third via hole V43, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 422b can be electrically connected to the sixteenth pixel connection electrode 416 through the forty-sixth via hole V46, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 422c can be electrically connected to the sixth transistor of the first pixel circuit 11c. The first anode connection electrode 422d can be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0255] In some examples, the shapes of the first power connection electrodes 423a, 423b, and 423c can be substantially rectangular. The first power connection electrode 423a can be located between the data lines DL(j) and DL(j-1), the first power connection electrode 423b can be located between the data lines DL(j+1) and DL(j+2), and the first power connection electrode 423c can be located between the data lines DL(j+3) and DL(j+4).

[0256] In some examples, the first power connection electrode 423a can be electrically connected to the fifth pixel connection electrode 405 through the forty-second via hole V42, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuit 11a. The second power connection electrode 423b can be electrically connected to the fifteenth pixel connection electrode 415 through the forty-fourth via hole V44, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuits 11b and 11c. The third power connection electrode 423c can be electrically connected to the fifth transistor and storage capacitor of the first pixel circuit 11d.

[0257] In some examples, the shape of the first shielding electrodes 421a and 421b can be roughly n-shaped. The first shielding electrode 421a can be located between the data lines DL(j) and DL(j+1), and the first shielding electrode 421b can be located between the data lines DL(j+2) and DL(j+3). The orthographic projection of the first shielding electrode 421a on the substrate can cover the orthographic projection of the second pixel connection electrode 402 and the twelfth pixel connection electrode 412 on the substrate, which can block the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11a and 11b. The second shielding electrode 421b can block the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11c and 11d.

[0258] In some examples, the second scan connection segment 282 of the second scan line GL2(k) can be shaped approximately like a zigzag line extending along the first direction X. The second scan connection segment 282 of the second scan line GL2(k) can be located on one side of the light-transmitting area A12 at the kth row and the h+1th column along the second direction Y. For example, the second scan connection segment 282 can be located within the display island area at the k-1th row and the h+1th column. The orthographic projection of the second scan connection segment 282 on the substrate can partially overlap with the orthographic projections of the first scan connection segment 252, the first reset control line RST1(k), and the first initial signal line INIT1(k) on the substrate. One end of the second scan connection segment 282 can be connected to the first routing transfer electrode 283 in the display island area of ​​the kth row and hth column through the forty-seventh via V47, thereby connecting to the second scan transmission segment 281 and the second scan auxiliary transmission segment 271 in the display island area of ​​the kth row and hth column. The other end of the second scan connection segment 282 can be connected to the second scan transmission segment 281 and the second scan auxiliary transmission segment 271 in the display island area of ​​the kth row and h+1th column. The second scan connection segment 282 can connect the second scan transmission segments in two adjacent display island areas along the first direction X, and can also connect the second scan auxiliary transmission segments in two adjacent display island areas along the first direction X, thereby enabling transmission of the second scan signal along the first direction X.

[0259] (12) Forming an eighth insulating layer. In some examples, an eighth insulating layer is coated on the substrate having the aforementioned pattern, and the eighth insulating layer is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second planar layer.

[0260] FIG17 is a schematic diagram of the first display area after the eighth insulating layer is formed in FIG6 . In some examples, as shown in FIG17 , the eighth insulating layer in the first display area may be provided with a plurality of vias, such as vias V51 through V59. The eighth insulating layer within vias V51 through V59 may be removed to expose a portion of the surface of the fifth conductive layer.

[0261] (13) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate having the aforementioned pattern, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0262] FIG18A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG6 . FIG18B is a schematic diagram of the sixth conductive layer in FIG18A . In some examples, as shown in FIG18A and FIG18B , the sixth conductive layer in the first display area may include at least: a plurality of second anode connection electrodes (e.g., including second anode connection electrodes 432a, 432b, 432c, and 432d), a plurality of first voltage transmission lines (e.g., including first voltage transmission lines 451a and 451b), a plurality of power connection bars 452, and a plurality of second power connection electrodes (e.g., including second power connection electrodes 453a, 453b, and 453c).

[0263] In some examples, the first voltage transmission lines 451a and 451b may be shaped like a zigzag extending along the second direction Y. The first voltage transmission lines 451a and 451b may be spaced apart along the first direction X. The first voltage transmission line 451a may be electrically connected to the first power connection electrode 423a through the fifty-third via V53, and the first voltage transmission line 451b may be electrically connected to the first power connection electrode 423c through the fifty-fifth via V55. The first voltage transmission lines 451a and 451b may be connected to the first voltage signal. For example, the first voltage transmission lines 451a and 451b may extend to the peripheral area and be electrically connected to the first power supply line in the peripheral area to achieve access to the first voltage signal.

[0264] In some examples, the power connection bar 452 can be shaped approximately as a straight line extending along the first direction X. The power connection bar 452 can connect two adjacent first voltage transmission lines 451a and 451b. The power connection bar 452 within a single display island area can be connected to three second power connection electrodes 453a, 453b, and 453c. The second power connection electrodes 453a, 453b, and 453c can be shaped approximately as a straight line extending along the second direction Y. The second power connection electrode 453a can be connected to the first shielding electrode 421a through the fifty-first via V51, the second power connection electrode 453b can be connected to the first power connection electrode 432b through the fifty-fourth via V54, and the second power connection electrode 453c can be connected to the second shielding electrode 421b through the fifty-second via V52. The power connection bar 452, the first voltage transmission lines 451a and 451b, and the plurality of second power connection electrodes 453a, 453b and 453c can be an integrated structure connected to each other, thereby forming a mesh connection structure for transmitting the first voltage signal in the first display area to ensure the transmission uniformity of the first voltage signal.

[0265] In some examples, the second anode connection electrode 432a can be located between the first voltage transmission line 451a and the second power connection electrode 453a, the second anode connection electrode 432b can be located between the second power connection electrodes 453a and 453b, the second anode connection electrode 432c can be located between the second power connection electrodes 453b and 453c, and the second anode connection electrode 432d can be located between the second power connection electrode 453c and the first voltage transmission line 451b.

[0266] In some examples, the shapes of the second anode connection electrodes 432a, 432b, 432c, and 432d can be substantially strip-shaped extending along the second direction Y. The second anode connection electrode 432a can be electrically connected to the first anode connection electrode 422a through the fifty-sixth via hole V56. The second anode connection electrode 432b can be electrically connected to the first anode connection electrode 422b through the fifty-seventh via hole V57. The second anode connection electrode 432c can be electrically connected to the first anode connection electrode 422c through the fifty-eighth via hole V58. The second anode connection electrode 432d can be electrically connected to the first anode connection electrode 422d through the fifty-ninth via hole V59.

[0267] In this example, the fifth and sixth conductive layers are used to arrange the data lines and first voltage transmission lines. This avoids the possibility of excessive wiring in the conductive layer near the anode layer, which could affect the flatness of the anode layer. Furthermore, placing the first voltage transmission lines in the sixth conductive layer and the data lines in the fifth conductive layer increases the distance between the data lines and the anode layer, preventing signals transmitted by the data lines from affecting the anode layer.

[0268] (14) Forming a ninth insulating layer. In some examples, a ninth insulating layer is coated on the substrate having the aforementioned pattern, and the ninth insulating layer is patterned by a patterning process to form the ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as a third planar layer.

[0269] FIG19 is a schematic diagram of the first display area after the ninth insulating layer is formed in FIG6 . In some examples, as shown in FIG19 , the ninth insulating layer in the first display area may have multiple vias, such as vias V61 through V64. The ninth insulating layer within vias V61 through V64 may be removed to expose a portion of the surface of the sixth conductive layer.

[0270] At this point, the circuit structure layer is complete. The film structure of the circuit structure layer in the second display area is similar to that of the first display area, so it will not be described in detail here. Specifically, the first scan line, second scan line, second scan auxiliary line, light control line, and third initial signal line in the second display area do not need to use a segmented switching design.

[0271] (15) Forming a light-emitting structure layer. In some examples, an anode film is deposited on the substrate having the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer.

[0272] FIG20A is a schematic diagram of the first display area after the anode layer is formed in FIG6 . FIG20B is a schematic diagram of the anode layer in FIG20A . In some examples, as shown in FIG20A and FIG20B , the anode layer of the first display area may include at least: anodes of a plurality of first light-emitting elements (e.g., anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, anode 131d of first light-emitting element 13d, anode 131e of first light-emitting element 13e, and anode 131f of first light-emitting element 13f), a plurality of anode connection blocks (e.g., anode connection blocks 132a, 132b, 132c, and 132d), and a plurality of anode connection bars (e.g., first anode connection bar 133 and second anode connection bar 134).

[0273] In some examples, the shapes of the anodes 131a, 131b, 131c, 131d, 131e, and 131f can be substantially rectangular. Anode 131a can be located on one side of anode 131b in the second direction Y, and anode 131c can be located on one side of anodes 131a and 131b in the first direction X. Anode 131d can be located on one side of anode 131e in the second direction Y, and anode 131f can be located on one side of anodes 131d and 131e in the first direction X.

[0274] In some examples, the anode connection block 132a may be roughly hexagonal in shape. The anode 131a and the anode connection block 132a may be interconnected as an integral structure. The anode connection block 132a may be electrically connected to the second anode connection electrode 432a via a sixty-first via hole V61, thereby achieving electrical connection with the first pixel circuit 11a. The anode connection blocks 132b, 132c, and 132d may be roughly V-shaped in shape. The anode 131b and the anode connection block 132b may be interconnected as an integral structure. The anode connection block 132b may be electrically connected to the second anode connection electrode 432b via a sixty-second via hole V62, thereby achieving electrical connection with the first pixel circuit 11b. The anode 131c and the anode connection block 132c may be interconnected as an integral structure. The anode connection block 132c may be electrically connected to the second anode connection electrode 432c via a sixty-third via hole V63, thereby achieving electrical connection with the first pixel circuit 11c. The anode 131e and the anode connection block 132d may be interconnected as an integral structure. The anode connection block 132d can be electrically connected to the second anode connection electrode 432d through the sixty-fourth via hole V64 to achieve electrical connection with the first pixel circuit 11d.

[0275] In some examples, the shape of the first anode connection bar 133 can be substantially a zigzag line extending along the first direction X. Both ends of the first anode connection bar 133 can be connected to the anodes 131 a and 131 d, respectively. The first anode connection bar 133 can be located on one side of the anode 131 c in the second direction Y. The first anode connection bar 133, the anodes 131 a and 131 d, and the anode connection block 132 a can be an interconnected integral structure.

[0276] In some examples, the second anode connection bar 134 can be shaped substantially as a straight line extending along the first direction X. The two ends of the second anode connection bar 134 can be connected to the anodes 131 c and 131 f, respectively. The second anode connection bar 134 can be located between the anodes 131 d and 131 e. The second anode connection bar 134, the anodes 131 c and 131 f, and the anode connection block 132 c can be an integrated structure connected to each other.

[0277] In some examples, a pixel definition film is coated on a substrate having the aforementioned pattern, and a pixel definition layer is formed by masking, exposure, and development processes. As shown in FIG6 , the pixel definition layer of the first display area can form a plurality of first pixel openings (e.g., including first pixel openings 130a, 130b, 130c, and 130d). The shape of the plurality of first pixel openings can be roughly rectangular. The first pixel opening 130a of the first light-emitting element 13a and the first pixel opening 130d of the first light-emitting element 13d can be roughly the same size, the first pixel opening 130c of the first light-emitting element 13c and the first pixel opening 130f of the first light-emitting element 13f can be roughly the same size, and the first pixel opening 130b of the first light-emitting element 13b and the first pixel opening 130e of the first light-emitting element 13e can be roughly the same size. The first pixel opening 130c of the first light-emitting element 13c can be larger than the first pixel opening 130a of the first light-emitting element 13a, and can be larger than the first pixel opening 130b of the first light-emitting element 13b.

[0278] In some examples, the light-emitting region of a light-emitting element may be the portion of the light-emitting element located within the pixel opening of the pixel definition layer. For example, the light-emitting region of first light-emitting element 13a may be greater than or equal to the light-emitting region of first light-emitting element 13b, and the light-emitting region of first light-emitting element 13c may be greater than both the light-emitting region of first light-emitting element 13a and the light-emitting region of first light-emitting element 13b.

[0279] In some examples, an organic light-emitting layer is formed within the pixel opening formed above, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode film is deposited and patterned through a patterning process to form a cathode layer, which can be connected to the organic light-emitting layer.

[0280] FIG21 is a schematic diagram of the light-transmitting area in FIG6 . In some examples, as shown in FIG21 , the light-transmitting area A12 may include: a first area A121 and a second area A122. The orthographic projections of the first area A121 and the second area A122 on the substrate may not overlap. The light-transmitting area A12 as a whole may be roughly elliptical, and the shapes of the multiple light-transmitting areas A12 are roughly the same, and are roughly wide at the top and narrow at the bottom. The first area A121 may be an irregular shape, and the second area A122 may be located at the edge of the first area A121. The cathode layer in the first area A121 may be removed, and the cathode layer in the second area A122 may be retained.

[0281] In some examples, as shown in FIG21 , the maximum length L11 of the light-transmitting area A12 along the second direction Y can be 30 to 40 microns, such as approximately 35 microns. The maximum length L12 of the first area A121 of the light-transmitting area A12 along the first direction X can be 70 to 90 microns, such as approximately 81 microns. The minimum length L13 of the side of the lower portion of the first area A121 extending along the second direction Y in the first direction X can be 65 to 82 microns, such as approximately 74 microns.

[0282] In some examples, after preparing the light-emitting structure layer, an encapsulation structure layer can be formed on the cathode. In some examples, the encapsulation structure layer can include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer can be arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate can also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0283] In some examples, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The seventh insulating layer, the eighth insulating layer, and the ninth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited to this.

[0284] The structure of the display substrate and its preparation process in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or removed as needed. The preparation process of this exemplary embodiment can be implemented using currently available manufacturing equipment and is well compatible with existing manufacturing processes. The process is simple to implement, easy to implement, and has high production efficiency, low production costs, and a high yield rate.

[0285] In the display substrate of this example, compared with the second display area, the light-transmitting area and the display island area are formed by deleting the first pixel circuit and the first light-emitting element in the first display area, and the first pixel circuit and the first light-emitting element in the display island area are set to a combination of one-drive-one and one-drive-many, and the arrangement of the first light-emitting elements in the display island area is different from the arrangement of the second light-emitting elements in the second display area. This can optimize the display effect of the first display area on the basis of improving the light transmittance of the first display area.

[0286] In some examples, a first scan signal within the first display area can be transmitted via a first scan line formed by a cross-layer connection between a first scan transmission segment and a first scan connection segment, and a second scan signal can be transmitted via a second scan line formed by a cross-layer connection between a second scan transmission segment and a second scan connection segment. The first scan connection segment and the second scan connection segment can be located in different film layers and have overlapping wiring, which can help save wiring space and thereby increase the area of ​​the light-transmitting area. In some examples, the first scan connection segment, the second scan connection segment, the first reset control line, and the first initial signal line can be located in different film layers and have overlapping wiring, which can help save wiring space.

[0287] In some examples, the light control signal within the first display area can be transmitted via a light control line formed by a cross-layer connection between the light control transmission segment and the light control connection segment. The light control connection segment and the first and second scan connection segments can bypass the light-transmitting area from both sides along the second direction, facilitating streamlined wiring. In some examples, the light control connection segment, the second reset control line, and the second initial signal line can be located in different film layers and have overlapping wiring, which can help save wiring space and thereby increase the area of ​​the light-transmitting area.

[0288] In some examples, the third initial signal within the first display area can be transmitted via a third initial signal line formed by a cross-layer connection between the initial signal transmission segment and the initial signal connection segment. The initial signal connection segment and the light-emitting control connection segment can be located in different film layers and have overlapping wiring, which can help save wiring space.

[0289] Figure 22 is another partial top view schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 22 shows a partial top view schematic diagram of two rows (for example, the kth row and the k+1th row) and two columns (for example, the hth column and the h+1th column) of display island areas, where k and h are both integers greater than 0. In some examples, as shown in Figure 22, the first display area may include: a plurality of display island areas and a plurality of light-transmitting areas A12. A single light-transmitting area A12 is surrounded by two display island areas in the first direction X and by two display island areas in the second direction Y. The number of film layers and the stacking order of the circuit structure layer of the display substrate of this example are similar to those of the aforementioned embodiment. The following is an explanation taking the film layer structure of the display island area of ​​the kth row and hth column and the display island area of ​​the k+1th row and h+1 column as an example.

[0290] In some examples, k may be 2d, where d is an integer greater than 0. The kth row may be an odd row, and the k+1th and k-1th rows may be even rows. In other examples, k may be 2d-1, where d is an integer greater than 0. The kth row may be an even row, and the k+1th and k-1th rows may be odd rows. In this example, odd rows refer to rows with odd row numbers, and even rows refer to rows with even row numbers.

[0291] Figure 23 is a schematic diagram of the first display area after the shielding layer is formed in Figure 22. In some examples, as shown in Figure 23, the shielding layer of the first display area may include at least: a plurality of shielding blocks (for example, a shielding block 300a located in the display island area of ​​the kth row and the hth column and a shielding block 300b located in the display island area of ​​the k+1th row and the h+1th column). A shielding block 300a can be provided for each display island area located in the kth row, and a shielding block 300b can be provided for each display island area located in the k+1th row. The shielding block 300a and the connected shielding block 300b can be centrally symmetrical about the connection point between the two. The shielding blocks 300a and 300b of the display island areas of adjacent rows in the display island areas of adjacent columns can be interconnected integral structures. The multiple shielding blocks 300a and 300b of the first display area can be interconnected integral structures. Regarding the shape of the shielding blocks, reference can be made to the description of the aforementioned embodiment, so it will not be repeated here.

[0292] Figure 24A is a schematic diagram of the first display area after the first semiconductor layer is formed in Figure 22. Figure 24B is a schematic diagram of the first semiconductor layer in Figure 24A. In some examples, as shown in Figures 24A and 24B, the first semiconductor layer of the first display area may include at least: an active layer of multiple first-type transistors of multiple first pixel circuits. The first semiconductor layer patterns of the four first pixel circuits located in the display island area of ​​the kth row and hth column and the first semiconductor layer patterns of the four first pixel circuits located in the display island area of ​​the k+1th row and h+1th column may be centrally symmetrical about the connection point between the two. The description of the first semiconductor layer pattern in each display island area can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0293] FIG25A is a schematic diagram of the first display area after the first conductive layer is formed in FIG22 . FIG25B is a schematic diagram of the first conductive layer in FIG25A . In some examples, as shown in FIG25A and FIG25B , the first conductive layer of the first display area may include at least: a plurality of first scan lines (e.g., first scan lines GL1(k-1), GL1(k), GL1(k+1), and GL1(k+2)), a plurality of emission control lines (e.g., emission control lines EML(k) and EML(k+1)), a plurality of first reset control lines (e.g., first reset control lines RST1(k) and RST1(k+2)), a plurality of second reset control lines (e.g., second reset control lines RST2(k) and RST2(k+2)), and first electrodes of storage capacitors of a plurality of first pixel circuits (e.g., first electrodes 391 a and 391 b).

[0294] In some examples, the first scan line GL1(k), the first reset control line RST1(k), and the first scan line GL1(k-1) can be sequentially arranged along the second direction Y and located on one side of the first electrode of the storage capacitor of the first pixel circuit in the display island area of ​​the kth row in the second direction Y. The emission control line EML(k), the second reset control line RST2(k), and the emission control line EML(k+1) can be sequentially arranged along the second direction Y and located on a side opposite to the second direction Y of the first electrode of the storage capacitor of the first pixel circuit in the display island area of ​​the kth row, and located on one side of the first electrode of the storage capacitor of the first pixel circuit in the display island area of ​​the k+1th row in the second direction Y.

[0295] In some examples, the first scan line GL1(k) may be located on one side of the k-th row of light-transmitting areas A12 in the second direction Y, and the emission control line EML(k) may be located on a side of the k-th row of light-transmitting areas A12 in the opposite direction of the second direction Y. The first scan line GL1(k) and the emission control line EML(k) may bypass the light-transmitting areas A12 from opposite sides of the k-th row of light-transmitting areas A12 in the second direction Y.

[0296] In some examples, the first pixel circuits in each display island area are arranged in the same row. The first pixel circuit in the k-th row display island area (for example, the first pixel circuit in the i-th row) and the first pixel circuit in the k-1-th row display island area (for example, the first pixel circuit in the i-1-th row) can share the first reset control line RST1(k). The first pixel circuit in the k+1-th row display island area (for example, the first pixel circuit in the i+1-th row) and the first pixel circuit in the k-th row display island area (for example, the first pixel circuit in the i-th row) can share the second reset control line RST2(k). In this example, by flipping the first pixel circuit in the even-numbered row display island area upside down, the first pixel circuit in the even-numbered row display island area can share the first reset control line or the second reset control line with the first pixel circuit in the adjacent odd-numbered row display island area to save wiring arrangement space.

[0297] Figure 26A is a schematic diagram of the first display area after the second conductive layer is formed in Figure 22. Figure 26B is a schematic diagram of the second conductive layer in Figure 26A. In some examples, as shown in Figures 26A and 26B, the second conductive layer of the first display area may include at least: a second scan auxiliary transmission segment 271 of a plurality of second scan auxiliary lines, and a second electrode of the storage capacitor of a plurality of first pixel circuits (for example, including second electrodes 392a, 392b). The second electrodes of the storage capacitors of the four first pixel circuits in a single display island area may be an integrated structure connected to each other. In the kth row and hth column display island area, the second scan auxiliary transmission segment 271 may be located on one side of the second electrode of the storage capacitor of the first pixel circuit in the second direction Y; in the k+1th row and h+1th column display island area, the second scan auxiliary transmission segment 271 may be located on the side of the second electrode of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y.

[0298] Figure 27A is a schematic diagram of the first display area after the second semiconductor layer is formed in Figure 22. Figure 27B is a schematic diagram of the second semiconductor layer in Figure 27A. In some examples, as shown in Figures 27A and 27B, the second semiconductor layer in the first display area may include at least: an active layer of a plurality of second-type transistors of the first pixel circuit. The second semiconductor layer pattern within the display island region in row k, column h and the second semiconductor layer pattern within the display island region in row k+1, column h+1 may be centrally symmetrical about the connection point between the two display island regions.

[0299] FIG28A is a schematic diagram of the first display area after the third conductive layer is formed in FIG22 . FIG28B is a schematic diagram of the third conductive layer in FIG28A . In some examples, as shown in FIG28A and FIG28B , the third conductive layer in the first display area may include at least: a second scan transmission segment 281 of a plurality of second scan lines (e.g., including second scan lines GL2(k) and GL2(k+1)), a plurality of first initial signal lines (e.g., including first initial signal lines INIT1(k) and INIT1(k+1)), a plurality of second initial signal lines (e.g., including second initial signal line INIT2(k)), and a plurality of third initial signal lines (e.g., including third initial signal lines INIT3(k) and INIT3(k+1)).

[0300] In some examples, the first pixel circuits in each display island area are arranged in the same row. The first pixel circuit in the k-th display island area (e.g., the first pixel circuit in the i-th row) and the first pixel circuit in the k-1-th display island area (e.g., the first pixel circuit in the i-1-th row) can share the first initial signal line INIT1(k). The first pixel circuit in the k+1-th display island area (e.g., the first pixel circuit in the i+1-th row) and the first pixel circuit in the k-th display island area (e.g., the first pixel circuit in the i-th row) can share the second initial signal line INIT2(k). The first pixel circuit in the k+1-th display island area (e.g., the first pixel circuit in the i+1-th row) and the first pixel circuit in the k+2-th display island area (e.g., the first pixel circuit in the i+2-th row) can share the first initial signal line INIT1(k+1). In this example, the first pixel circuit in the even-numbered row display island area is flipped upside down so that the first pixel circuit in the even-numbered row display island area can share the first initial signal line or the second initial signal line with the first pixel circuit in the adjacent odd-numbered row display island area to save wiring layout space.

[0301] FIG29A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG22 . FIG29B is a schematic diagram of the fourth conductive layer in FIG29A . In some examples, as shown in FIG29A and FIG29B , the fourth conductive layer in the first display area may include at least: a plurality of pixel connection electrodes (e.g., including the first pixel connection electrode 401 to the seventeenth pixel connection electrode 417) and a plurality of routing electrodes (e.g., including the first routing electrode 283). The first routing electrode 283 may be substantially L-shaped. The first routing electrode 283 may be connected to the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) and the second scanning transmission segment 281 of the second scanning line GL2(k). The fourth conductive layer pattern in the display island region of the kth row and hth column and the fourth conductive layer pattern in the display island region of the k+1th row and h+1th column may be centrally symmetrical about the connection point between the two display island regions.

[0302] FIG30A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG22 . FIG30B is a schematic diagram of the fifth conductive layer in FIG30A . In some examples, as shown in FIG30A and FIG30B , the fifth conductive layer in the first display area may include at least: a plurality of data lines (e.g., data lines DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7), and DL(j+8)), a plurality of first anode connection electrodes (e.g., first anode connection electrodes 422a, 422b, 422c, 422d, 422e, 422f, 422g, and 422h), a plurality of first power connection electrodes (e.g., first power connection electrodes 423a, 423b, and 423c), a plurality of first shield electrodes (e.g., first shield electrodes 421a and 421b), and a plurality of second scan connection segments 282 of second scan lines. The fifth conductive layer pattern in the display island region of row k, column h and the fifth conductive layer pattern in the display island region of row k+1, column h+1 can be centrally symmetrical about the connection point between the two display island regions. The first anode connection electrode 422e is connected to the first first pixel circuit in the display island region of row k+1, column h+1, the first anode connection electrode 422f is connected to the second first pixel circuit in the display island region of row k+1, column h+1, the first anode connection electrode 422g is connected to the third first pixel circuit in the display island region of row k+1, column h+1, and the first anode connection electrode 422h is connected to the fourth first pixel circuit in the display island region of row k+1, column h+1.

[0303] FIG31A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG22 . FIG31B is a schematic diagram of the sixth conductive layer in FIG31A . In some examples, as shown in FIG31A and FIG31B , the sixth conductive layer in the first display area may include at least: a plurality of second anode connection electrodes (e.g., including second anode connection electrodes 432a, 432b, 432c, 432d, 432e, 432f, 432g, and 432h), a plurality of first voltage transmission lines (e.g., including first voltage transmission lines 451a and 451b), a plurality of power connection bars 452, and a plurality of second power connection electrodes (e.g., including second power connection electrodes 453a, 453b, and 453c). The second anode connection electrodes 432e, 432f, 432g, and 432h may be substantially strip-shaped and extend along the second direction Y. Second anode connection electrode 432e may be connected to first anode connection electrode 422e, second anode connection electrode 432f may be connected to first anode connection electrode 422f, second anode connection electrode 432g may be connected to first anode connection electrode 422g, and second anode connection electrode 432h may be connected to first anode connection electrode 422h.

[0304] FIG32 is a schematic diagram of the first display area after the anode layer is formed in FIG22 . In some examples, as shown in FIG32 , the anode layer of the first display area may include at least: anodes of a plurality of first light-emitting elements (e.g., anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, anode 131d of first light-emitting element 13d, anode 131e of first light-emitting element 13e, and anode 131f of first light-emitting element 13f), a plurality of anode connection blocks (e.g., anode connection blocks 132a, 132b, 132c, and 132d), and a plurality of anode connection bars (e.g., first anode connection bar 133 and second anode connection bar 134). The anode layer pattern in the display island region of row k and column h is substantially the same as the anode layer pattern in the display island region of row k+1 and column h+1. The anodes of the two first light-emitting elements emitting the first color light in the display island region of the k+1th row can be connected to the first first pixel circuit via the second anode connection electrode 432e and the first anode connection electrode 422e, the anode of one first light-emitting element emitting the second color light can be connected to the second first pixel circuit via the second anode connection electrode 432f and the first anode connection electrode 422f, the anodes of the two first light-emitting elements emitting the third color light can be connected to the third first pixel circuit via the second anode connection electrode 432g and the first anode connection electrode 422g, and the anode of another first light-emitting element emitting the second color light can be connected to the fourth first pixel circuit via the second anode connection electrode 432h and the first anode connection electrode 422h. The patterning of the anode layer in this example is similar to that of the anode layer in the aforementioned embodiment, and therefore will not be described in detail here.

[0305] Figure 33 is a schematic diagram of the light-transmitting area in Figure 22. In some examples, the light-transmitting area A12 in the kth row and the h+1th column and the light-transmitting area A12 in the k+1th row and the hth column can be centrally symmetrical about the connection point between the display island area in the kth row and the hth column and the display island area in the k+1th row and the h+1th column. The light-transmitting area A12 as a whole can be roughly elliptical. For example, the light-transmitting area A12 in the k+1th row and the hth column can be narrow at the top and wide at the bottom. The light-transmitting area A12 can include: a first area A121 and a second area A122. The orthographic projections of the first area A121 and the second area A122 on the substrate can have no overlap. The first area A121 can be an irregular shape, and the second area A122 can be located at the edge of the first area A121. The cathode layer in the first area A121 can be removed, and the cathode layer in the second area A122 can be retained.

[0306] In some examples, as shown in FIG33 , the maximum length L21 of the light-transmitting area A12 along the second direction Y can be 34 to 42 microns, such as approximately 38 microns. The maximum length L22 of the first area A121 of the light-transmitting area A12 along the first direction X can be 75 to 95 microns, such as approximately 85 microns. The minimum length L23 of the side of the first area A121 extending along the second direction Y in the first direction X can be 65 to 81 microns, such as approximately 73 microns.

[0307] Compared to the previous embodiment, the display substrate of this example flips the first pixel circuits in the display island areas of even rows (or odd rows) upside down, so that the first pixel circuits in adjacent rows and columns can be centrally symmetrical. Furthermore, the first pixel circuits in adjacent rows can share the first reset control line and the first initial signal line, or can share the second reset control line and the second initial signal line. This helps save wiring space in the display island area, increases the area of ​​the light-transmitting area, and thus improves the light transmittance of the first display area. The remaining description of the display substrate of this embodiment can refer to the description of the previous embodiment, and will not be repeated here.

[0308] FIG34 is another schematic diagram illustrating the signal correspondence between the first display area and the second display area according to at least one embodiment of the present disclosure. FIG5 illustrates a first display unit in the display island area of ​​the first display area A1 in the fth row and hth column and a first display unit in the display island area of ​​the f-1th row and h+1th column, where f is an integer.

[0309] In some examples, as shown in FIG34 , the four first pixel circuits 11 a , 11 b , 11 c , and 11 d in the display island region in the fth row and the hth column may be sequentially arranged along the first direction X. The first pixel circuit 11 a may be connected to two first light-emitting elements 13 a and 13 d emitting first color light, the first pixel circuit 11 b may be connected to one first light-emitting element 13 b emitting second color light, the first pixel circuit 11 c may be connected to two first light-emitting elements 13 c and 13 f emitting third color light, and the first pixel circuit 11 d may be connected to another first light-emitting element 13 e emitting second color light.

[0310] In some examples, as shown in FIG34 , the four first pixel circuits 11 a , 11 b , 11 c , and 11 d in the display island region at the fth row and the h+1th column may be sequentially arranged along the first direction X. The first pixel circuit 11 a may be connected to two first light-emitting elements 13 c and 13 f that emit light of the third color, the first pixel circuit 11 b may be connected to one first light-emitting element 13 b that emits light of the second color, the first pixel circuit 11 c may be connected to two first light-emitting elements 13 a and 13 d that emit light of the first color, and the first pixel circuit 11 d may be connected to another first light-emitting element 13 e that emits light of the second color.

[0311] In this example, the first pixel circuits in two adjacent rows of display islands are connected to the first light-emitting elements in a different order. For example, the first first pixel circuit in the display island in row f is connected to two first light-emitting elements emitting the first color light, and the third first pixel circuit is connected to two first light-emitting elements emitting the third color light. The four first pixel circuits correspond to RGBG in sequence. The first first pixel circuit in the display island in row f-1 is connected to two first light-emitting elements emitting the third color light, and the third first pixel circuit is connected to two first light-emitting elements emitting the first color light. The four first pixel circuits correspond to BGRG in sequence.

[0312] This example improves display uniformity and enhances the display quality of the first display area by setting a different connection sequence between the first pixel circuits and the first light-emitting elements in adjacent rows of display islands. The remaining description of the display substrate of this example can be referred to the description of the previous embodiment and will not be repeated here.

[0313] Figure 35 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 35 illustrates the arrangement of multiple first light-emitting elements in the first display area A1 and multiple second light-emitting elements in the second display area A2. Figure 35 uses eight rows and four columns of display islands in the first display area A1 as an example. This example does not limit the number of display islands in the first display area.

[0314] In some examples, as shown in FIG35 , the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The display island area A11 may include a first display unit 21, and the first display unit 21 may include: six first light-emitting elements and four first pixel circuits. The six first light-emitting elements may include: two first light-emitting elements 13a and 13d emitting a first color light, two first light-emitting elements 13b and 13e emitting a second color light, and two first light-emitting elements 13c and 13f emitting a third color light. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light.

[0315] In some examples, the six first light-emitting elements of the first display unit 21 can be divided into two groups of first light-emitting elements, each group of which can include three first light-emitting elements emitting light of different colors. For example, the first group of first light-emitting elements can include three first light-emitting elements 13a, 13b, and 13c; the second group of first light-emitting elements can include three first light-emitting elements 13d, 13e, and 13f. The first group of first light-emitting elements and the second group of first light-emitting elements can be arranged sequentially along the first direction X. In the first group of first light-emitting elements, the first light-emitting elements 13a, 13b, and 13c can be arranged sequentially along the first direction X. In the second group of first light-emitting elements, the first light-emitting elements 13d, 13e, and 13f can be arranged sequentially along the first direction X. In this example, the three first light-emitting elements emitting light of different colors in each group of first light-emitting elements of the first display unit 21 can be arranged in a Real RGB arrangement. The arrangement of the multiple second light-emitting elements in the second display area A2 can refer to the description of the previous embodiment and will not be repeated here.

[0316] Figure 36 is a partial top view schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 37A is a schematic diagram of the first display area after the anode layer is formed in Figure 36. Figure 37B is a schematic diagram of the anode layer in Figure 37A. Figure 36 shows a partial top view schematic diagram of the display island area with two rows (for example, the kth row and the k+1th row) and two columns (for example, the hth column and the h+1th column). The circuit structure layer of the first display area of ​​this example can be the structure of the embodiment shown in Figure 22, so it will not be repeated here. In other examples, the circuit structure layer of the first display area of ​​this example can be the structure of the embodiment shown in Figure 6. This embodiment is not limited to this.

[0317] In some examples, as shown in Figures 36 to 37B, the anode layer of the first display area may include at least: anodes of multiple first light-emitting elements (for example, including anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, anode 131d of first light-emitting element 13d, anode 131e of first light-emitting element 13e, and anode 131f of first light-emitting element 13f), multiple anode connection blocks (for example, including anode connection blocks 132a, 132b, 132c, and 132d), and multiple anode connection bars (for example, including first anode connection bar 133 and second anode connection bar 134).

[0318] In some examples, the anodes 131a, 131b, 131c, 131d, 131e, and 131f may be substantially rectangular in shape. The anodes 131a, 131b, 131c, 131d, 131e, and 131f may be arranged sequentially along the first direction X.

[0319] In some examples, the shape of the anode connection block 132a can be roughly hexagonal. The anode 131a and the anode connection block 132a can be an integrated structure connected to each other. The anode connection block 132a can be connected to the first first pixel circuit. The shape of the anode connection block 132b can be roughly diagonal. The anode 131b and the anode connection block 132b can be an integrated structure connected to each other. The anode connection block 132b can be connected to the second first pixel circuit. The shape of the anode connection block 132c can be roughly V-shaped. The anode 131c and the anode connection block 132c can be an integrated structure connected to each other. The anode connection block 132c can be connected to the third first pixel circuit. The shape of the anode connection block 132d can be roughly diagonal. The anode 131e and the anode connection block 132d can be an integrated structure connected to each other. The anode connection block 132d can be connected to the fourth first pixel circuit.

[0320] In some examples, the shape of the first anode connection bar 133 can be substantially a zigzag line extending along the first direction X. Both ends of the first anode connection bar 133 can be connected to the anodes 131 a and 131 d, respectively. The first anode connection bar 133 can be located on one side of the anodes 131 b and 131 c in the second direction Y. The first anode connection bar 133, the anodes 131 a and 131 d, and the anode connection block 132 a can be an integrated structure connected to each other.

[0321] In some examples, the second anode connection bar 134 can be shaped substantially like a broken line extending along the first direction X. The two ends of the second anode connection bar 134 can be connected to the anode 131f and the anode connection block 132c, respectively. The second anode connection bar 134 can be located on a side opposite to the anodes 131d and 131e in the second direction Y. The second anode connection bar 134, the anodes 131c and 131f, and the anode connection block 132c can be an integrated structure connected to each other.

[0322] In the display substrate of this example, by setting the first light-emitting elements in the display island area to adopt a Real RGB arrangement, the display effect of the first display area can be optimized.

[0323] Figure 38 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 38 illustrates the arrangement of multiple first light-emitting elements in the first display area A1 and multiple second light-emitting elements in the second display area A2. Figure 38 uses four rows and four columns of display islands in the first display area A1 as an example. This example does not limit the number of display islands in the first display area.

[0324] In some examples, as shown in FIG38 , the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The plurality of display island areas A11 and the plurality of light-transmitting areas A12 may be arranged at intervals along the first direction X and the second direction Y. The display island area A11 may include two first display units 21a and 21b. The two first display units 21a and 21b may be arranged in sequence along the second direction Y. Each first display unit may include six first light-emitting elements and four first pixel circuits. The display island area of ​​this example may be roughly square island-shaped. The arrangement of the first light-emitting element and the first pixel circuit in each first display unit may refer to the description of the aforementioned embodiment, so it will not be repeated here. In other examples, each display island area may be provided with three or more first display units arranged in sequence along the second direction Y.

[0325] Figure 39 is another partial schematic diagram of the display area of ​​at least one embodiment of the present disclosure. Figure 39 illustrates the arrangement of multiple first light-emitting elements in the first display area A1 and multiple second light-emitting elements in the second display area A2. Figure 39 uses four rows and four columns of display islands in the first display area A1 as an example. This example does not limit the number of display islands in the first display area.

[0326] In some examples, as shown in FIG39 , the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The plurality of display island areas A11 and the plurality of light-transmitting areas A12 may be arranged at intervals along the first direction X and the second direction Y. The display island area A11 may include two first display units 21a and 21b. The two first display units 21a and 21b may be arranged in sequence along the first direction X. Each first display unit may include six first light-emitting elements and four first pixel circuits. The display island area of ​​this example may be roughly rectangular island-shaped. The arrangement of the first light-emitting element and the first pixel circuit in each first display unit may refer to the description of the aforementioned embodiment, so it will not be repeated here. In other examples, each display island area may be provided with three or more first display units arranged in sequence along the first direction X.

[0327] In other examples, at least one first pixel circuit in at least one first display unit can be connected to three or four first light-emitting elements to drive the three or four first light-emitting elements to emit light. In other examples, two groups of first light-emitting elements in at least one first display unit can adopt different arrangements, for example, one group of first light-emitting elements adopts a Pentile RGB arrangement, and the other group of first light-emitting elements adopts a Real RGB arrangement. In other examples, the first light-emitting elements in at least one first display unit can adopt a Pentile RGB arrangement, and the first light-emitting elements in at least one first display unit can adopt a Real RGB arrangement. This embodiment is not limited to this.

[0328] This embodiment provides a display substrate, comprising: a substrate. The substrate comprises: a first display area and a second display area located on at least one side of the first display area. The first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area comprises: at least one group of first pixel circuits and a plurality of first light-emitting elements, each group of first pixel circuits comprises M first pixel circuits, at least one of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1. The second display area comprises: a plurality of groups of second pixel circuits and a plurality of second light-emitting elements, each group of second pixel circuits comprises M second pixel circuits, at least one second pixel circuit is connected to at least one second light-emitting element. The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area. The first pixel circuits and the second pixel circuits located in the same column are connected to the same data line.

[0329] The display substrate provided in this embodiment adopts a pixel circuit built-in method to delete the first pixel circuit and the first light-emitting element in the first display area to form a light-transmitting area, and sets the driving relationship of the first pixel circuit to the first light-emitting element to be different from the driving relationship of the second pixel circuit to the second light-emitting element. On the basis of improving the light transmittance of the first display area, it can ensure the display effect of the first display area and compensate for the loss of display effect caused by deleting some light-emitting elements and pixel circuits in the first display area.

[0330] In some exemplary embodiments, each group of first pixel circuits includes four first pixel circuits connected to six first light-emitting elements, including two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light. Each group of second pixel circuits includes four second pixel circuits connected to four second light-emitting elements, including one second light-emitting element emitting first color light, two second light-emitting elements emitting second color light, and one second light-emitting element emitting third color light.

[0331] In some exemplary embodiments, an arrangement of the six first light-emitting elements is different from an arrangement of the four second light-emitting elements.

[0332] In some exemplary embodiments, the arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the first direction, such as 0.45 to 0.55, and for example, may be approximately 0.5; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second direction in the second display area, such as 0.45 to 0.55, and for example, may be approximately 0.5.

[0333] The description of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0334] Figure 40 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 40 , this embodiment provides a display device comprising: a display substrate 91; and a sensor 92 located on a light-emitting side of a light-emitting structure layer, away from the display substrate 91. The sensor 92 can be located on the non-display surface of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 can at least partially overlap with the first display area A1. For example, the orthographic projection of the sensor 92 on the display substrate 91 can be located within the first display area A1.

[0335] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0336] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example" or "some examples" mean that the features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0337] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, comprising: A substrate, comprising: a first display area and a second display area located at at least one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; The display island area includes: at least one first display unit; the at least one first display unit includes: N first light-emitting elements and M first pixel circuits, where M and N are both integers greater than 1, and M is less than N; at least one first pixel circuit among the M first pixel circuits is connected to at least two first light-emitting elements and is configured to drive the at least two first light-emitting elements to emit light; The second display area comprises: a plurality of second display units arranged in an array; at least one second display unit among the plurality of second display units comprises: M second light-emitting elements and M second pixel circuits, and the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence; The arrangement of the N first light-emitting elements of the at least one first display unit is different from the arrangement of the M second light-emitting elements of the at least one second display unit.

2. The display substrate according to claim 1, wherein: In the first display area, the display island areas and the light-transmitting areas are alternately arranged and aligned in a first direction, and are alternately arranged and aligned in a second direction, wherein the first direction intersects the second direction.

3. The display substrate according to claim 1, wherein: The M first pixel circuits of the at least one first display unit and the M second pixel circuits of the at least one second display unit are aligned in a first direction or a second direction, wherein the first direction intersects the second direction.

4. The display substrate according to claim 1, wherein: The at least one first display unit comprises: six first light emitting elements and four first pixel circuits, wherein the four first pixel circuits are arranged in sequence along a first direction; The six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light; The two first light-emitting elements emitting the first color light are connected to the same first pixel circuit, the two first light-emitting elements emitting the third color light are connected to the same first pixel circuit, and the two first light-emitting elements emitting the second color light are connected to two first pixel circuits in a one-to-one correspondence.

5. The display substrate according to claim 4, wherein: The six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction, and each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; In each group of first light-emitting elements, the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light are arranged in sequence along the second direction, and the first light-emitting elements emitting the third color light are located on the same side of the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light along the first direction; the second direction intersects with the first direction.

6. The display substrate according to claim 4, wherein: The six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction, and each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; In each group of first light-emitting elements, the first light-emitting elements emitting first color light, the first light-emitting elements emitting second color light, and the first light-emitting elements emitting third color light are arranged in sequence along the first direction.

7. The display substrate according to claim 4, wherein: In the first display area, the connection order of the first pixel circuits and the first light-emitting elements of the first display units in the display island areas of adjacent rows is different.

8. The display substrate according to claim 7, wherein: In the first display area, four first pixel circuits located in the display island area of ​​the fth row may be connected in sequence to two first light-emitting elements emitting first color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting third color light, and another first light-emitting element emitting second color light; The four first pixel circuits of the first display unit located in the display island area of ​​the f-1th row can be connected in sequence to two first light-emitting elements emitting the third color light, one first light-emitting element emitting the second color light, two first light-emitting elements emitting the first color light, and another first light-emitting element emitting the second color light; wherein f is an integer greater than 1.

9. The display substrate according to any one of claims 4 to 8, wherein: The at least one second display unit comprises: four second light emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along the first direction; The four second light-emitting elements include: a second light-emitting element emitting a first color light, two second light-emitting elements emitting a second color light, and a second light-emitting element emitting a third color light; the second light-emitting element emitting the first color light, the second light-emitting element emitting the second color light, the second light-emitting element emitting the third color light, and the second light-emitting element emitting the second color light are arranged in sequence along the first direction; the second light-emitting element emitting the first color light and the second light-emitting element emitting the third color light are arranged in the same row, and the two second light-emitting elements emitting the second color light are arranged in the same row.

10. The display substrate according to any one of claims 4 to 9, wherein: The first color light is red light, the second color light is green light, and the third color light is blue light.

11. The display substrate according to any one of claims 1 to 10, wherein: The M first pixel circuits of the first display unit in the display island area are connected to a first scan transmission segment and a second scan transmission segment extending along the first direction; the first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal; The first scan transmission segments in the display island regions that are located in the same row and adjacent to each other are connected via the first scan connection segment; the second scan transmission segments in the display island regions that are located in the same row and adjacent to each other are connected via the second scan connection segment; The second scanning connection segment is located at a side of the first scanning connection segment away from the substrate, and an orthographic projection of the first scanning connection segment on the substrate at least partially overlaps with an orthographic projection of the second scanning connection segment on the substrate.

12. The display substrate according to claim 11, wherein: The first pixel circuit of the first display unit located in the display island area of ​​the same row is also connected to a first reset control line and a first initial signal line extending along the first direction, the first initial signal line is located on a side of the first reset control line away from the substrate; the first scan connection section is located on a side of the first initial signal line away from the substrate; The orthographic projection of the first scanning connection segment on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate; An orthographic projection of the first initial signal line on the substrate at least partially overlaps with an orthographic projection of the first reset control line on the substrate.

13. The display substrate according to claim 11, wherein: The M first pixel circuits of the first display unit in the display island area are connected to the light emitting control transmission segment extending along the first direction; the light emitting control transmission segment is configured to transmit a light emitting control signal; the light emitting control transmission segments in the display island areas adjacent to each other in the same row are connected via a light emitting control connection segment; The light-emitting control connection segment and the first scanning connection segment are located on both sides of the light-transmitting area between the adjacent display island areas in a second direction, and the second direction intersects the first direction.

14. The display substrate according to claim 13, wherein: The first pixel circuit of the first display unit located in the display island area of ​​the same row is also connected to a second reset control line and a second initial signal line extending along the first direction, the second initial signal line is located on a side of the second reset control line away from the substrate; the light emitting control connection section is located on a side of the second initial signal line away from the substrate; The orthographic projection of the light-emitting control connection section on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate; the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate.

15. The display substrate according to claim 13, wherein: The M first pixel circuits of the first display unit in the display island area are also connected to an initial signal transmission segment extending along the first direction; the initial signal transmission segment is configured to transmit a third initial signal; The initial signal transmission segments in adjacent display islands located in the same row are connected via the initial signal connection segments; The light-emitting control connection section is located at a side of the initial signal connection section away from the substrate; the orthographic projection of the initial signal connection section on the substrate partially overlaps with the orthographic projection of the light-emitting control connection section on the substrate.

16. The display substrate according to any one of claims 1 to 10, wherein: The multiple first pixel circuits located in the display island area of ​​the kth row and the hth column and the multiple first pixel circuits located in the display island area of ​​the k+1th row and the h+1th column are centrally symmetric about the connection point between the display island area of ​​the kth row and the hth column and the display island area of ​​the k+1th row and the h+1th column; wherein k and h are both integers greater than 0.

17. The display substrate according to claim 16, wherein: In the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1th row located in the k-1-th row display island area share a first reset control line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1th row located in the k+1-th row display island area share a second reset control line, wherein i is an integer greater than 1, and e is an integer greater than or equal to 0.

18. The display substrate according to claim 17, wherein: In the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area share a first initial signal line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1-th row located in the k+1-th row display island area share a second initial signal line.

19. The display substrate according to any one of claims 1 to 18, wherein: The display island area includes two first display units, and the two first display units are arranged along a first direction or along a second direction; the first direction intersects with the second direction.

20. A display device, comprising a display substrate as claimed in any one of claims 1 to 19, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate at least partially overlaps with a first display area of ​​the display substrate.

21. A display substrate, comprising: A substrate, comprising: a first display area and a second display area located at at least one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; The display island area includes: at least one group of first pixel circuits and a plurality of first light-emitting elements, each group of first pixel circuits includes M first pixel circuits, at least one first pixel circuit of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1; The second display area includes: a plurality of groups of second pixel circuits and a plurality of second light-emitting elements, each group of second pixel circuits includes M second pixel circuits, and at least one second pixel circuit is connected to at least one second light-emitting element; The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area; The first pixel circuit and the second pixel circuit located in the same column are connected to the same data line.

22. The display substrate according to claim 21, wherein: Each group of first pixel circuits includes four first pixel circuits, and the four first pixel circuits are connected to six first light-emitting elements, and the six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light; Each group of second pixel circuits includes four second pixel circuits, which are connected to four second light-emitting elements. The four second light-emitting elements include one second light-emitting element emitting first color light, two second light-emitting elements emitting second color light, and one second light-emitting element emitting third color light.

23. The display substrate according to claim 22, wherein: The arrangement of the six first light-emitting elements is different from the arrangement of the four second light-emitting elements.

24. The display substrate according to claim 21, wherein: The arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the first direction; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the second direction; the first direction intersects the second direction.

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