Display method, display apparatus, and electronic device

Abstract

The present invention relates to the technical field of display, and provides a display method, a display apparatus, and an electronic device. The display method in the present invention is applied to the display apparatus. The display apparatus comprises a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array. The sub-pixel array comprises a plurality of gate lines and a plurality of data lines, and a plurality of sub-pixels defined by crossing the gate lines and the data lines. The display method comprises: the main control board receives an initial data frame and divides the initial data frame into a first target data frame and a second target data frame, the first target data frame comprising odd-numbered rows of data of the initial data frame, and the second target data frame comprising even-numbered rows of data of the initial data frame; the timing controller applies a frame start signal and a plurality of clock signals to the gate driving circuit, and applies a source control signal to the source driving circuit; and the gate driving circuit provides a gate driving signal for a plurality of rows of gate lines on the basis of the frame start signal and the plurality of clock signals.

Description

Display methods, display devices, and electronic equipment Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display method, display device, and electronic device. Background Technology

[0002] With technological advancements, display devices are evolving towards larger sizes and higher resolutions. However, as display device sizes increase and resolutions improve, the charging time for each row of pixels becomes shorter, making it impossible to achieve the required pixel charging rate, thus affecting the display. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a display method, display device and electronic device.

[0004] This disclosure provides a display method applied to a display device, the display device including a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array includes multiple gate lines and multiple data lines, and multiple sub-pixels defined by the intersection of the gate lines and data lines; wherein, the display method includes:

[0005] The main control board receives an initial data frame and divides the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered rows of data from the initial data frame, and the second target data frame includes even-numbered rows of data from the initial data frame;

[0006] The timing controller applies a frame start signal and multiple clock signals to the gate drive circuit, and applies a source control signal to the source drive circuit;

[0007] The gate driving circuit provides gate driving signals for the multiple rows of gate lines based on the frame start signal and the multiple clock signals;

[0008] The source drive circuit, based on the source control signal, controls the start time of writing the data signal for each row of sub-pixels. The phase difference between this start time and the end time of the effective level of the gate drive signal written to the gate line connected to that row of sub-pixels is 2H. Here, H is half the phase difference between the start times of the effective levels of the gate drive signals written to the k-th and (k+2)-th gate lines according to the scan order. Here, k is a positive integer.

[0009] Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the first target data frame line by line into the odd-numbered rows of sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of writing the data of the 2kth row of sub-pixels is not later than the end time of writing the data of the 2k-1th row of sub-pixels, and the end time of writing the data of the 2kth row of sub-pixels is not earlier than the start time of writing the data of the 2k+1th row of sub-pixels;

[0010] Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the second target data frame line by line into even-numbered sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of writing the data of the (2k+1)th row of sub-pixels is not later than the end time of writing the data of the (2k+1)th row of sub-pixels, and the end time of writing the data of the (2k+1)th row of sub-pixels is not earlier than the start time of writing the data of the (2k+2)th row of sub-pixels.

[0011] The duration for which the gate drive signals of two adjacent rows of sub-pixels are simultaneously at an effective level is not less than 2H.

[0012] The gate drive circuit includes multiple shift register units; each shift register unit is connected to one gate line, and different shift register units are connected to different gate lines.

[0013] The plurality of clock signals include a first clock signal for controlling the first-stage shift register unit in the gate drive circuit to output a gate drive signal;

[0014] Wherein, the start time of the effective level of the frame start signal output by the timing controller is earlier than the start time of the effective level of the first clock signal; the phase difference between the end time of the effective level of the frame start signal and the end time of the effective level of the first clock signal is greater than or equal to 0.2H and less than or equal to 0.6H.

[0015] The gate drive circuit includes N levels of shift register units; the first to P levels of shift register units are connected to the frame start signal; the plurality of clock signals also includes a P-th clock signal for controlling the output gate drive signal of the P-th shift register unit; the duty cycle of each clock signal is less than or equal to 50%, N is greater than P, and P is an integer greater than 1.

[0016] Wherein, the phase difference between the start times of the effective levels of any two adjacent clock signals in the plurality of clock signals is 1H, the end time of the effective level of the frame start signal is no later than the end time of the effective level of the first clock signal, and the duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%.

[0017] The duty cycle of each clock signal is 40%, the duration of the effective level of the gate drive signal is 3.2H, and the phase difference between the end time of the effective level of the frame start signal and the end time of the effective level of the first clock signal is 0.2H.

[0018] The plurality of clock signals includes 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group including 8 shift register units, and each of the 8 shift register units in the group receives the 8 clock signals respectively;

[0019] The timing controller writes the frame start signal to the first-level shift register unit to the fourth-level shift register unit among the N shift register units.

[0020] Wherein, the end time of the effective level of the frame start signal is later than the end time of the effective level of the first clock signal; the phase difference between the start times of the effective levels of the gate drive signals applied to the gate lines in the k-th row and the (K+1)-th row is 1H; each pair of adjacent clock signals is a group, and for adjacent groups of clock signals, the timing controller controls the phase difference between the start times of the effective levels of one group of clock signals to be less than 1H, and the phase difference between the start times of the effective levels of the other group of clock signals to be greater than 1H.

[0021] The duty cycle of each clock signal is 33%, and the duration of the effective level of the gate drive signal is 2.66H. For adjacent groups of clock signals, the timing controller controls the phase difference of the start time of the effective level of one group of clock signals to be 0.76H, and the phase difference of the start time of the effective level of the other group of clock signals to be 1.24H.

[0022] The plurality of clock signals includes 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group including 8 shift register units, and each of the 8 shift register units in the group receives the 8 clock signals respectively;

[0023] The timing controller writes the frame start signal to the first-level shift register unit to the fourth-level shift register unit among the N shift register units.

[0024] The plurality of clock signals include a first clock signal for controlling the first-stage shift register unit in the gate driving unit to output a gate driving signal;

[0025] The plurality of clock signals include a first clock signal for controlling the first-stage shift register unit in the gate drive circuit to output a gate drive signal;

[0026] Wherein, the start time of the effective level of the frame start signal output by the timing controller is earlier than the start time of the effective level of the first clock signal; the end time of the effective level of the frame start signal is the same as the end time of the effective level of the first clock signal.

[0027] The gate drive circuit includes N levels of shift register units; the first level shift register units to the P level shift register units are connected to the frame start signal; the plurality of clock signals also includes a P-th clock signal for controlling the P-th level shift register unit to output the gate drive signal;

[0028] The first-stage shift register unit to the P-stage shift register unit are connected to the frame start signal; the plurality of clock signals also include a P-th clock signal for controlling the output gate drive signal of the P-stage shift register unit; the duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%, N is greater than P; and P is an integer greater than 1.

[0029] Among the plurality of clock signals, the phase difference between the start times of the effective levels of any two adjacent clock signals is 1H, and the duty cycle of each clock signal is 41.6%.

[0030] The effective level of the gate drive signal has a duration of 5H, and the pre-charge period has a duration of 3H.

[0031] The plurality of clock signals includes 12 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group including 12 shift register units, and each of the 12 shift register units in the group receives the 12 clock signals respectively;

[0032] The timing controller writes the frame start signal to the first to sixth level shift register units among the N shift register units.

[0033] When the sub-pixel is selected by the effective level of the gate drive signal, the time period is divided into a pre-charge period and a charging period; the charging period is the data signal writing period of the sub-pixel, and the duration of the pre-charge period is greater than 1H.

[0034] The display of the k-th initial data frame and the (k+1)-th initial data frame includes:

[0035] The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order:

[0036] The first target data frame of the k-th initial data frame;

[0037] The second target data frame of the k-th initial data frame;

[0038] The first target data frame of the (k+1)th initial data frame;

[0039] The second target data frame of the (k+1)th initial data frame.

[0040] The display of the k-th initial data frame and the (k+1)-th initial data frame includes:

[0041] The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order:

[0042] The second target data frame of the k-th initial data frame;

[0043] The first target data frame of the k-th initial data frame;

[0044] The second target data frame of the (k+1)th initial data frame;

[0045] The first target data frame of the (k+1)th initial data frame.

[0046] This disclosure provides a display device, including a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array includes multiple gate lines and multiple data lines, and multiple sub-pixels defined by the intersection of the gate lines and data lines; wherein,

[0047] The main control board is configured to receive an initial data frame and divide the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered rows of data from the initial data frame, and the second target data frame includes even-numbered rows of data from the initial data frame.

[0048] The timing controller is configured to apply a frame start signal and a plurality of clock signals to the gate drive circuit, and to apply a source control signal to the source drive circuit.

[0049] The gate driving circuit provides gate driving signals for the multiple rows of gate lines based on the frame start signal and the multiple clock signals;

[0050] The source drive circuit, based on the source control signal, controls the start time of writing the data signal for each row of sub-pixels. The phase difference between this start time and the end time of the effective level of the gate drive signal written to the gate line connected to that row of sub-pixels is 2H. Here, H is half the phase difference between the start times of the effective levels of the gate drive signals written to the k-th and (k+2)-th gate lines according to the scan order. Here, k is a positive integer.

[0051] When the source drive circuit writes the data signal of the first target data frame line by line into odd-numbered sub-pixels, the source control signal and the gate drive signal generated by the timing controller satisfy the following: the start time of writing the data of the 2kth row of sub-pixels is not later than the end time of writing the data of the 2k-1th row of sub-pixels, and the end time of writing the data of the 2kth row of sub-pixels is not earlier than the start time of writing the data of the 2k+1th row of sub-pixels.

[0052] The source control signal and the gate drive signal generated by the timing controller are used in the source drive circuit to write the data signal of the second target data frame line by line into even-numbered sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of the data writing of the 2k+1th row of sub-pixels is not later than the end time of the data writing of the 2kth row of sub-pixels, and the end time of the data writing of the 2k+1th row of sub-pixels is not earlier than the start time of the data writing of the 2k+2th row of sub-pixels.

[0053] This disclosure provides an electronic device, including the display device described above. Attached Figure Description

[0054] Figure 1 shows a schematic diagram of a display device provided in an embodiment of the present disclosure.

[0055] Figures 2A and 2B show example structural diagrams of the gate drive circuit provided in embodiments of the present disclosure.

[0056] Figure 3A shows a signal timing diagram of a display method.

[0057] Figure 3B shows a signal timing diagram for another display method.

[0058] Figure 4 shows a flowchart of a display method according to an embodiment of the present disclosure.

[0059] Figure 5 shows a timing diagram of a display method according to an embodiment of the present disclosure.

[0060] Figure 6 shows a timing diagram of the frame start signal and clock signal according to an embodiment of the present disclosure.

[0061] Figure 7 shows a schematic diagram of the frame start signal line and clock signal line according to an embodiment of the present disclosure.

[0062] Figure 8A is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to an embodiment of this disclosure.

[0063] Figure 8B is a schematic diagram of an embodiment of the present disclosure for extracting odd-numbered rows of data from an initial data frame.

[0064] Figure 9 is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to an embodiment of this disclosure.

[0065] Figure 10 shows a signal timing diagram of odd-numbered frames displayed according to an embodiment of the present disclosure.

[0066] Figure 11 shows a signal timing diagram of odd-numbered frames in an embodiment of this disclosure.

[0067] Figure 12 shows a signal timing diagram of a display method according to an embodiment of the present disclosure.

[0068] Figures 13A and 13B show example structural diagrams of another gate drive circuit provided in an embodiment of this disclosure.

[0069] Figure 14 shows a timing diagram of another frame start signal and clock signal according to an embodiment of the present disclosure.

[0070] Figure 15 shows a signal timing diagram of odd-numbered frames according to an embodiment of the present disclosure.

[0071] Figure 16 shows a signal timing diagram of even-numbered frames according to an embodiment of the present disclosure.

[0072] Figure 17 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0073] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0074] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0075] Figure 1 shows a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in Figure 1, the display device 100 includes a subpixel array, which includes a plurality of subpixels P arranged in an N×M array, wherein N and M are both integers greater than 1.

[0076] The display device 100 may further include a gate driving circuit 10, which is connected to a plurality of sub-pixels P. The gate driving circuit 10 can be connected to N rows of sub-pixels respectively through a plurality of gate signal lines extending along a first direction (x direction in FIG1). For example, the first row of sub-pixels can be connected through a first gate signal line to provide a first gate driving signal G1 to the first row of sub-pixels, and the second row of sub-pixels can be connected through a second gate signal line to provide a second gate driving signal G2 to the second row of sub-pixels, and so on. The first row of sub-pixels turns on in response to receiving the first gate driving signal G1, the second row of sub-pixels turns on in response to receiving the second gate driving signal G2, and so on.

[0077] In some embodiments, the gate driving circuit 10 can scan N rows of sub-pixels one or more rows at a time. For example, the gate driving circuit 10 can scan one row of sub-pixels at a time, such as sequentially generating N gate driving signals G1, G2, ... GN to sequentially turn on the first row of sub-pixels, the second row of sub-pixels P, ... the Nth row of sub-pixels P. The gate driving circuit 10 can also scan two or more rows of sub-pixels P at a time. For example, the gate driving circuit 10 can simultaneously generate a first gate driving signal G1 and a second gate driving signal G2 to simultaneously turn on the first row of sub-pixels and the second row of sub-pixels, then the gate driving circuit 10 can simultaneously generate a third gate driving signal G3 and a fourth gate driving signal G4 to simultaneously turn on the third row of sub-pixels and the fourth row of sub-pixels, and so on. In some embodiments, the gate driving circuit 10 can scan the N rows of sub-pixels at least one row interval to sequentially turn on the sub-pixels of some rows. For example, the gate drive circuit 10 can sequentially turn on odd-numbered rows of sub-pixels P (e.g., sequentially turn on the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, and so on), or sequentially turn on even-numbered rows of sub-pixels (e.g., sequentially turn on the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and so on).

[0078] The display device 100 may further include a source driving circuit 20, which is connected to a plurality of sub-pixels P. For example, the source driving circuit 20 may be connected to M columns of sub-pixels P respectively via multiple data lines extending along a second direction (y direction in FIG1). For example, the source driving circuit 20 may be connected to a first column of sub-pixels via a first data line to provide a first data signal D1 to the first column of sub-pixels, and to a second column of sub-pixels via a second data line to provide a second data signal D2 to the second column of sub-pixels, and so on.

[0079] For example, when the first row of sub-pixels is enabled, the source driving circuit 20 can provide M data signals D11, D12, ..., D1M for the M sub-pixels of the first row through M data lines respectively; when the second row of sub-pixels is enabled, the source driving circuit 20 can provide M data signals D21, D22, ..., D2M for the M sub-pixels of the second row through multiple data lines respectively, and so on. Of course, the embodiments of this disclosure are not limited to this, and will be further described in detail below.

[0080] In some embodiments, the display device 100 may further include a main control board 40 and a timing controller 30. The main control board 40 is connected to the timing controller 30 and is used to transmit initial data frames to the timing controller 30. The timing controller 30 is connected to the gate driving circuit 10 and the source driving circuit 20 and can provide relevant control signals to the gate driving circuit 10 and the source driving circuit 20. For example, the timing controller 30 can provide a data control signal TP to the source driving circuit 20, and the source driving circuit 20 can output data signals for each row under the control of the data control signal TP. The timing controller 30 can also provide other control signals to the source driving circuit 20, including but not limited to row data start signals, data synchronization signals, data inversion signals, etc. The timing controller 30 can also provide various control signals to the gate driving circuit 10, including but not limited to frame start signals, clock signals, etc. required by the gate driving circuit 10.

[0081] Figures 2A and 2B illustrate example structural diagrams of the gate driving circuit according to embodiments of the present disclosure. As shown in Figures 2A and 2B, the gate driving circuit includes multiple cascaded shift register units GOA1, GOA2, ..., GOAN. For example, for a 4K2K (resolution 3840×2160) display panel, the horizontal pixel count is 3840 and the vertical pixel count is 2160. If each pixel contains multiple sub-pixels arranged horizontally, the display panel includes 2160 rows of sub-pixels. In the case where the display panel contains 2160 rows of sub-pixels and each shift register unit corresponds to one row of sub-pixels, the gate driving circuit can include 2160 shift register units.

[0082] Figure 2A shows the shift register units GOA1 to GOA9 from the first to the ninth stage. As shown in Figure 2A, STV1 is the frame start signal. When the gate drive circuit is connected to 8 CLKs, the input terminals of the shift register units GOA1 to GOA4 from the first to the fourth stage can be connected to the frame start signal terminal STV1. After the fourth stage shift register unit GOA4, the input terminal of the nth stage shift register unit GOAn is connected to the output terminal of the (n-4)th stage shift register unit GOA(n-4), where 5 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA5, the output of GOA2 is connected to the input of GOA6, the output of G3 is connected to the input of GOA7, the output of G4 is connected to the input of GOA8, the output of G5 is connected to the input of GOA9, and so on. The reset terminal RST of the nth stage shift register unit GOAn is connected to the output terminal OUT of the (n+4)th stage shift register unit GOA(n+4), where 1 ≤ n ≤ N-4. Figure 2B shows the last-stage shift register unit GOA2160 and the dummy shift register unit (Dummy GOA). As shown in Figure 2B, the last four rows of GOA can be reset through four rows of dummy GOA. For example, dummy GOA1 (Dum1) resets GOA2157, dummy GOA2 (Dum2) resets GOA2158, and so on. Each dummy GOA can be reset through STV1. STV0 is the total reset signal, and STV0 is connected to GOA9 and subsequent units. The waveforms of STV0 and STV1 are exactly the same, so they can be connected together externally.

[0083] The gate drive circuits shown in Figures 2A and 2B employ eight clock signals CLK1 to CLK8. The clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1; the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the eighth-stage shift register unit GOA8 is connected to receive the eighth clock signal CLK8. Similarly, the ninth to sixteenth-stage shift register units GOA9 to GOA16 are connected to receive the first to eighth clock signals CLK1 to CLK8, respectively.

[0084] Each shift register unit GOA1, GOA2, ..., GOAN can generate an output signal as a gate drive signal (or gate scan signal) at its output OUT under the control of its clock signal CLK and input signals. For example, the first-stage shift register unit GOA1 generates a first gate drive signal G1, the second-stage shift register unit GOA2 generates a second gate drive signal G2, and so on. By cascading, the gate drive signal generated by one-stage shift register unit can be shifted relative to the gate drive signal generated by another-stage shift register unit.

[0085] The above is merely an illustrative example of a display device according to an embodiment of this disclosure. The structure of the display device according to this disclosure is not limited thereto, and other structures may be used as needed. For example, the display device may be a display device based on liquid crystal display (LCD) technology, or a display device based on organic light-emitting diode (OLED) display technology. The gate driving circuit of the display device may adopt a different cascading method than that shown in Figures 2A and 2B. For example, it may adopt 10 or 12 clock signals cascaded in different ways.

[0086] Figure 3A shows a signal timing diagram of a display method. The signal timing of Figure 3A will be explained below using the display devices of Figures 1, 2A, and 2B as examples. As shown in Figure 3A, during the display of each frame of image, the gate driving circuit 10 sequentially generates a first gate driving signal G1, a second gate driving signal G2, a third gate driving signal G3, and a fourth gate driving signal G4 at preset time intervals, and so on. The phase difference between the start times of the data signals written to two adjacent row sub-pixels is H. In Figure 3A, the effective level duration of each gate driving signal is, for example, 4H.

[0087] For the first row of sub-pixels, during time periods T1 to T4, the first gate drive signal G1 is high, causing the first row of sub-pixels to be in the on state. The length of each time period T1 to T4 is H, meaning the first sub-pixel is on for 4H seconds. During time period T4, the first high-level pulse of the data control signal TP arrives, thereby controlling the source drive circuit 20 to apply the data signal (also called the first row data signal) DATA1 for the first row of sub-pixels to the on-state first row of sub-pixels. The first row data signal DATA1 may include M data signals D11, D12, ..., D1M for the M sub-pixels of the first row, where data signal D11 is provided to the first column of the first row of sub-pixels, data signal D12 is provided to the second column of the first row of sub-pixels, ..., data signal D1M is provided to the Mth column of the first row of sub-pixels.

[0088] Similarly, for the second row of sub-pixels, during time periods T2 to T5, the second gate drive signal G2 is high, causing the second row of sub-pixels to be in the on state. During time period T5, the second high-level pulse of the data control signal TP arrives, thereby controlling the source drive circuit 20 to apply the data signal (also called the second row data signal) DATA2 for the second row of sub-pixels to the on-state second row of sub-pixels. The second row data signal DATA2 may include M data signals D21, D22, ..., D2M for the M sub-pixels of the second row, respectively. Data signal D21 is provided to the first column of the second row of sub-pixels, data signal D22 is provided to the second column of the second row of sub-pixels, ..., data signal D2M is provided to the Mth column of the second row of sub-pixels. This process can be repeated for other rows of sub-pixels.

[0089] Figure 3B shows a signal timing diagram for another display method. As shown in Figure 3B, the effective level duration of each gate drive signal is, for example, 3.2H, so that the time each row of sub-pixels is in the on state is 3.2H, but the time for each row of sub-pixels to be written with data signals is 1H, that is, the actual charging time is 1H. In addition, in this embodiment of the present disclosure, both the frame start signal and the gate drive signal are taken as having an effective level of high level. In this case, the start time of the effective level is the rising edge of the gate drive signal, and the end time of the effective level is the falling edge of the gate drive signal.

[0090] As can be seen from the two examples above, although the activation time of each row of subpixels is several times the unit scan time, the time for writing data signals to each row of subpixels (also known as the actual charging time) is only one unit scan time H, which is the phase difference between the rising edges of the gate drive signals of the two rows of gate lines. Taking an 8K display device with a resolution of 7680×4320 as an example, at a refresh rate of 60Hz, one frame has a scan time of 1 / 60 second, meaning that scanning 4320 rows of subpixels takes 1 / 60 second. Therefore, the time spent scanning each row of subpixels (i.e., the unit scan time) H = 1 / 60 ÷ 4320 ≈ 3.7µs. At a refresh rate of 120Hz, the unit scan time H is 1.85µs, which is too short to allow the subpixels to be fully charged, thus affecting the display.

[0091] Furthermore, in some embodiments, the frame start signal line STV1, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5, and the sixth clock signal line CLK6 are arranged sequentially in a first direction (e.g., horizontally). Due to the relatively long distance between these signal lines, capacitance may form between adjacent signal lines. A capacitance may form between the start pulse signal line STV1 and the first clock signal line CLK1; similarly, a capacitance may form between the first clock signal line CLK1 and the second clock signal line CLK2, and between the second clock signal line CLK2 and the third clock signal line CLK3, and so on. During a pull-up or pull-down process, a CLK signal can disturb adjacent CLK signals. For example, the falling edge of clock signal CLK1 can cause a pull-down disturbance to clock signal CLK2. Consequently, the gate drive signal G2 corresponding to clock signal CLK2 is also pulled down during the charging cycle, affecting the charging time of the second row of sub-pixels.

[0092] When the falling edge of the frame start signal STV1 aligns with the falling edge of the clock signal CLK1, or when the falling edge of the frame start signal STV1 precedes the falling edge of the clock signal CLK1 and the phase difference between their falling edges is significant, the output signal (gate drive signal) corresponding to the first clock signal line CLK1 will not be disturbed by the frame start signal line STV1 or will be disturbed very little during the charging cycle. Furthermore, the falling edges of other clock signals are all later than the falling edge of the clock signal CLK1. Therefore, the output signal corresponding to the first clock signal line CLK1 will not be disturbed by other clock signals during the charging cycle. Since the output signal corresponding to the first clock signal line CLK1 is not disturbed by other signals during the charging cycle, the charging rate of the pixels in the corresponding row is normal. However, the output signals corresponding to the second clock signal line CLK2 to the eighth clock signal line CLK8 are disturbed during the charging cycle, resulting in a lower charging rate for the pixels in the corresponding rows. The waveforms of the gate drive signals corresponding to clock signal CLK1 and those corresponding to clock signals CLK2 to CLK8 differ. Macroscopically, this results in periodic horizontal fine lines appearing on the display panel, with eight rows of sub-pixels forming one cycle, leading to horizontal stripe defects in the displayed image. Therefore, balancing the disturbances experienced by each clock signal is a problem that needs to be solved.

[0093] This disclosure discloses a display method for a display device, comprising: applying a frame start signal and a plurality of clock signals to a gate driving circuit 10, causing the gate driving circuit 10 to output a plurality of gate driving signals to a sub-pixel array based on the frame start signal and the plurality of clock signals, wherein the sub-pixel array includes N rows of gate lines and M columns of data lines, the N rows of gate lines and M columns of data lines being interleaved to define a plurality of sub-pixels in an N×M array; scanning the sub-pixel array row by row using the plurality of gate driving signals to turn on each row of sub-pixels scanned, such that the duration for which two adjacent rows of sub-pixels are simultaneously in the turned-on state is greater than or equal to twice the unit scan time, the unit scan time being the time required to scan one row of sub-pixels, wherein N and M are both integers greater than 1; and applying a frame start signal and a plurality of clock signals to a sub-pixel array simultaneously in the turned-on state. Two rows of sub-pixels are given data signals such that the duration of the data signals applied to at least some rows of sub-pixels is greater than the unit scan time; wherein, the gate driving circuit 10 includes N shift register units respectively connected to the N rows of sub-pixels of the sub-pixel array, and the first shift register unit of the N shift register units is connected to the first row of sub-pixels in the sub-pixel array; multiple clock signals include a first clock signal for driving the first shift register unit to output a gate driving signal; wherein, the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is not later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times H.

[0094] The display method provided in the embodiments of this disclosure applies data signals to at least two rows of sub-pixels that are simultaneously in an on state, such that the duration for which the data signal is applied to each row of sub-pixels is greater than the unit scan time. Furthermore, it can balance the interference experienced by the clock signal CLK1 and subsequent clock signals, improving the phenomenon of poor horizontal stripes and achieving a better display effect.

[0095] The embodiments and some examples of this disclosure will now be described in detail with reference to the accompanying drawings.

[0096] Figure 4 shows a flowchart of a display method of a display device according to an embodiment of the present disclosure. As shown in Figure 4, the display method includes steps S401 to S403.

[0097] Step S401: The timing controller 30 applies a frame start signal and multiple clock signals to the gate drive circuit 10.

[0098] Step S402: The gate driving circuit 10 outputs multiple gate driving signals to the sub-pixel array based on the frame start signal and multiple clock signals. The multiple gate driving signals are used to scan the sub-pixel array row by row to turn on each scanned row of sub-pixels, such that the duration for which two adjacent rows of sub-pixels are simultaneously in the turned-on state is greater than or equal to 2H. The sub-pixel array includes multiple sub-pixels arranged in an N×M array, where N and M are both integers greater than 1.

[0099] Step S403: The source drive circuit 20 applies a data signal to at least two rows of sub-pixels that are simultaneously in the on state, such that the duration for which the data signal is applied to at least some of the rows of sub-pixels is greater than the unit scan time.

[0100] For example, multiple clock signals may include eight clock signals. N shift register units are divided into multiple groups according to their arrangement, with each group comprising eight shift register units, and each group of eight shift register units receiving eight clock signals respectively. For example, the gate drive circuit 10, frame start signal, clock signal, gate drive signal, data signal, etc., can be referred to in Figures 1, 2A, and 2B as described above, and will not be repeated here.

[0101] For example, in the first time period, the nth row of subpixels and the (n+1th row of subpixels) are turned on sequentially, where n is an integer and 1≤n≤N-3; in the second time period, the (n+2th row of subpixels) and the (n+3th row of subpixels) are turned on sequentially, and one of the nth row data signal and the (n+1th row data signal) is applied to the nth row of subpixels and the (n+1th row of subpixels), and the length of the second time period is greater than or equal to twice the unit scan time; in the third time period, the nth row of subpixels is turned off, and one of the (n+2th row of data signal and the (n+3rd row data signal) is applied to the (n+1th row of subpixels), the (n+2th row of subpixels), and the (n+3rd row of subpixels).

[0102] Figure 5 shows a timing diagram of a display method according to an embodiment of the present disclosure.

[0103] As shown in Figure 5, during time period T1 (the first time period), the first row of sub-pixels and the second row of sub-pixels are turned on sequentially. For example, in the first sub-time period T11 of the first time period T1, the first gate drive signal G1 is at a high level, thereby turning on the first row of sub-pixels; in the second sub-time period T12 of the first time period T1, the second gate drive signal G2 is at a high level, thereby turning on the second row of sub-pixels.

[0104] During time period T2 (second time period), the third and fourth rows of sub-pixels are turned on sequentially, and data signals are applied to the first and second rows of sub-pixels. For example, when the first high-level pulse of the data control signal TP arrives, the source drive circuit 20 applies one of the first row data signal DATA1 and the second row data signal DATA2 (in this embodiment, the first row data signal DATA1) to the first and second rows of sub-pixels.

[0105] During time period T3 (the third time period), the first row of subpixels is turned off, and data signals are applied to the second, third, and fourth row of subpixels. For example, when the second high-level pulse of the data control signal TP arrives, one of the third row data signal DATA3 and the fourth row data signal DATA4 is applied to the second, third, and fourth row of subpixels that are in the turned-on state.

[0106] Similarly, for the third and fourth row sub-pixels, the first time period is time period T2 in Figure 5, the second time period is time periods T3 and T4 in Figure 5, and the third time period is time period T5 in Figure 5. During time period T2, the third and fourth row sub-pixels are sequentially activated. For example, in the first sub-time period T21 of time period T2, the third gate drive signal G3 is high, thereby activating the third row sub-pixels; in the second sub-time period T22 of time period T2, the fourth gate drive signal G4 is high, thereby activating the fourth row sub-pixels. During time periods T3 and T4, the fifth and sixth row sub-pixels are sequentially activated, and one of the third row data signals DATA3 and DATA4 is applied to the third and fourth row sub-pixels. During time period T5, the third row sub-pixels are deactivated, and one of the fifth row data signals DATA5 and DATA6 is applied to the fourth, fifth, and sixth row sub-pixels.

[0107] The length of the second time period can be set to be greater than or equal to 2H, such that the duration for which a data signal is applied to each row of sub-pixels is greater than or equal to 2H. For example, in the example in Figure 5, the time period for which a data signal is applied to the first row of sub-pixels is time period T2, and the time periods for which a data signal is applied to the second row of sub-pixels are time periods T2 and T3. The lengths of time periods T1 and T2 can be set to 2H, and the length of time period T3 can be set to H. In this case, the actual charging time of the first row of sub-pixels is 2H (the length of time period T2), and the actual charging time of the second row of sub-pixels is 3H (the sum of the lengths of time periods T2 and T3). Similarly, the actual charging time of the third row of sub-pixels is 2H, and the actual charging time of the fourth row of sub-pixels is 3H.

[0108] The embodiments of this disclosure enable two rows of sub-pixels sequentially and apply data signals to the two rows of sub-pixels that are simultaneously enabled, so that the actual charging time of some sub-pixels (e.g., odd-numbered row sub-pixels) can reach 2 hours or more, while the actual charging time of other sub-pixels (e.g., even-numbered row sub-pixels) can reach 3 hours or more. For example, the data written to the even-numbered row sub-pixels is, for example, the data of the two adjacent odd-numbered row sub-pixels.

[0109] For example, the gate drive circuit 10 includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, including a first-stage shift register unit (such as GOA1) connected to the first row of sub-pixels in the sub-pixel array. Multiple clock signals include a first clock signal (such as CLK1) for driving the first-stage shift register unit to output a gate drive signal. For example, in the disclosed embodiment, the shift register unit connected to the first row of sub-pixels is referred to as the first-stage shift register unit.

[0110] Figure 6 shows a timing diagram of the frame start signal and clock signal according to an embodiment of the present disclosure.

[0111] As shown in Figure 6, the high-level duration of the frame start signal STV does not exceed the number of corresponding clock signals. For example, if the high-level duration of the frame start signal STV does not exceed the number of corresponding clock signals CLK, i.e., 8CLK, then the high-level duration of STV does not exceed 8H, which can be 8H, 7H, or 6H. In this example, the effective level duration of STV is 6H. The rising edge of the frame start signal STV is earlier than the rising edge of the first clock signal CLK1, and the falling edge of the frame start signal STV is no later than the falling edge of the first clock signal CLK1. The phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is greater than or equal to 0.2H and less than or equal to 0.6H. Based on this setting, display defects can be improved, achieving a better display effect. Figure 7 shows a schematic diagram of the frame start signal line and clock signal line according to an embodiment of this disclosure.

[0112] As shown in Figures 6 and 7, if the falling edge of the frame start signal line STV is aligned with the falling edge of the clock signal line CLK1, then the frame start signal line STV will not cause pull-down interference to the clock signal CLK1 when it is pulled down. The width of the frame start signal line STV is greater than the width of the clock signal line CLK, therefore the resistance of the frame start signal line STV is greater than the resistance of the clock signal line CLK. When the falling edge of the frame start signal line STV is earlier than the falling edge of the first clock signal line CLK1, and the phase difference between the falling edge of the frame start signal line STV and the falling edge of the first clock signal line CLK1 is, for example, 1H or greater, the falling edge of the frame start signal STV during pull-down is slower, thus having a smaller impact on the first clock signal line CLK1. This results in a situation where the interference received by the second clock signal CLK2 and subsequent clock signals cannot be balanced. In this embodiment of the present disclosure, the phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is set to 0.2H to 0.6H. This allows the frame start signal STV to have a greater pull-down effect on the first clock signal CLK1, thereby balancing the interference experienced by the first clock signal CLK1 and its subsequent clock signals, improving the phenomenon of poor horizontal stripes, and achieving a better display effect.

[0113] For example, the first-level shift register unit to the Pth-level shift register unit in the N shift register units are connected to the frame start signal; the multiple clock signals CLK also include the Pth clock signal CLK for driving the output gate drive signal of the Pth-level shift register unit; the duty cycle of each clock signal CLK is greater than or equal to 40% and less than or equal to 45%, and the phase difference and duty cycle are configured such that the falling edge of the frame start signal STV is aligned with the rising edge of the Pth clock signal, where P is an integer greater than 1.

[0114] For example, the value of P is related to the number of clock signals connected to the gate drive circuit 10. When the gate drive circuit 10 is connected to 8 CLK signals, P is 4; when the gate drive circuit 10 is connected to 12 CLK signals, P is 6.

[0115] For example, if the frame start signal STV is connected to the shift register units from the first to the fourth stage, then the P-th stage shift register unit is the fourth stage shift register unit. Setting the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 to 0.2H to 0.6H, and setting the duty cycle of the clock signal to 40% to 45%, and coordinating the phase difference and duty cycle to align the falling edge of the frame start signal with the rising edge of the fourth clock signal CLK4, can further improve display defects and achieve better display results.

[0116] For example, in some embodiments, the phase difference between the rising edges of any two adjacent clock signals in the plurality of clock signals is 1H, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%. For example, as shown in Figure 6, the high-level duration t1 of the frame start signal STV is 6H, the high-level duration t3 of each clock signal CLK is 3.2H, and the period time t4 of the clock signal CLK is 8H, then the duty cycle of the clock signal is 3.2 / 8 = 40%. The phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the first clock signal CLK1 is 5H, the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is 0.2H, and the start and end times of each clock signal CLK are sequentially 1H apart by t5. The rising edge of the fourth clock signal CLK4 is aligned with the falling edge of the frame start signal STV. In other words, when the clock signals CLK differ by 1H, and the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is 0.2H and the duty cycle of the clock signal is 40%, the rising edge of the fourth clock signal CLK4 can be aligned with the falling edge of the frame start signal STV.

[0117] For example, in some other embodiments, when the phase difference t6 between the falling edge of the start-of-frame signal STV and the falling edge of the clock signal CLK1 is 0.3H, setting the duty cycle of the clock signal to 3.3 / 8 = 41.25% can align the rising edge of the clock signal CLK4 with the falling edge of the start-of-frame signal STV. As another example, when the phase difference t6 between the falling edge of the start-of-frame signal STV and the falling edge of the clock signal CLK1 is 0.4H, setting the duty cycle of the clock signal to 3.4 / 8 = 42.5% can align the rising edge of the clock signal CLK4 with the falling edge of the start-of-frame signal STV. As yet another example, when the phase difference t6 between the falling edge of the start-of-frame signal STV and the falling edge of the clock signal CLK1 is 0.6H, setting the duty cycle of the clock signal to 3.6 / 8 = 45% can align the rising edge of the clock signal CLK4 with the falling edge of the start-of-frame signal STV.

[0118] For example, when the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV, the clock signal CLK4 immediately starts rising when the frame start signal STV ends, generating a second-order PU, which fully controls the GOA output. This can avoid leakage at the PU point in the shift register unit, allowing each sub-pixel to achieve a better charging effect.

[0119] For example, setting the duty cycle of the clock signal to 40% to 45% can improve display problems in some cases. The duty cycle of the clock signal is usually 50%, but when the duty cycle is 50%, display problems may occur due to in-plane coupling and other reasons. The embodiments of this disclosure set the duty cycle to 40% to 45%, which can solve the display problems in this case.

[0120] This disclosure also provides a display method for a display device. The display device has the same structure as described above, including a main control board 40, a timing controller 30, a source drive circuit 20, a gate drive circuit 10, and a sub-pixel array.

[0121] The display method of this disclosure mainly improves the problem of insufficient sub-pixel charging time caused by high refresh rates by designing the timing of the clock signal CLK and the frame start signal STV. The display method of this disclosure specifically includes the following steps:

[0122] The main control board 40 receives the initial data frame and divides it into a first target data frame and a second target data frame; the first target data frame includes the odd-numbered rows of data from the initial data frame, and the second target data frame includes the even-numbered rows of data from the initial data frame.

[0123] The timing controller 30 applies a frame start signal STV and multiple clock signals CLK to the gate drive circuit 10, and the image source drive circuit 20 applies a source control signal.

[0124] The gate drive circuit 10 provides gate drive signals for multiple rows of gate lines based on the frame start signal and multiple clock signals CLK. For the k-th and (k+2)-th gate lines in the scan order, the phase difference between the start time of the effective level of the gate drive signal written for the (k+2)-th gate line and the start time of the effective level of the gate drive signal written for the k-th gate line is 2H. H is half the phase difference between the rising edges of the gate drive signals written for the k-th and (k+2)-th gate lines in the scan order. k takes a positive integer.

[0125] Based on the source control signal and the gate drive signal, the source drive circuit 20 writes the data signal of the first target data frame line by line into the odd-numbered sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of the data writing of the 2kth row of sub-pixels is not later than the end time of the data writing of the 2k-1th row of sub-pixels, and the end time of the data writing of the 2kth row of sub-pixels is not earlier than the start time of the data writing of the 2k+1th row of sub-pixels.

[0126] Based on the source control signal and the gate drive signal, the source drive circuit 20 writes the data signal of the second target data frame line by line into the even-numbered sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of writing the data of the 2k+1th row of sub-pixels is not later than the end time of writing the data of the 2kth row of sub-pixels, and the end time of writing the data of the 2k+1th row of sub-pixels is not earlier than the start time of writing the data of the 2k+2th row of sub-pixels. In this embodiment of the present disclosure, it is mainly aimed at the display of a display device whose refresh rate is doubled compared to the previous refresh rate (e.g., from 60Hz to 120Hz). First, the main control board 40 splits the received initial data frame into two frames according to the odd-numbered rows of data and the even-numbered rows of data. The two frames of data formed by the split are called the first target frame data and the second target frame data, respectively. The resolution of these two frames of data is halved compared to the initial data frame. In this way, the amount of data remains the same, and the refresh rate is doubled compared to the previous one. In this case, the gate drive circuit 10 provides gate drive signals to multiple rows of gate lines based on the frame start signal and multiple clock signals CLK in the manner described above. The source drive circuit 20 writes the data signals line by line in the manner described above. In this way, when the display device displays the first target data frame, the odd-numbered row sub-pixels are all written with real data, and the even-numbered row sub-pixels are written with the data interpolated from the two odd-numbered rows above and below the even-numbered row. Similarly, when the display device displays the second target data frame, the even-numbered row sub-pixels are all written with real data, and the odd-numbered row sub-pixels are written with the data interpolated from the two even-numbered rows above and below the odd-numbered row. In this way, the charging rate of each sub-pixel is guaranteed when the refresh rate is doubled.

[0127] In some examples, the timing controller 30 may apply a single or multiple frame start signals STV to the gate drive circuit 10, such as 1 / 2 / 3, etc. When there are multiple frame start signals STV, one of them is a global reset signal, which has the same waveform as the first frame start signal STV. The number of clock signals CLK applied by the timing controller 30 to the gate drive circuit 10 is generally a multiple of 4, for example, 4 / 8 / 12 / 16 clock signals CLK. In this embodiment, only 8 and 12 clock signals CLK are used as examples.

[0128] The multiple clock signals CLK include a first clock signal CLK1 used to control the first-stage shift register unit in the gate drive circuit 10 to output the gate drive signal; the start time of the effective level of the frame start signal STV output by the timing controller 30 is earlier than the start time of the effective level of the first clock signal CLK1, and the end time of the effective level of the frame start signal STV is no later than the end time of the effective level of the first clock signal CLK1; the phase difference between the end time of the effective level of the frame start signal STV and the end time of the effective level of the first clock signal CLK1 is greater than or equal to 0.2H and less than or equal to 0.6H.

[0129] When there are multiple frame start signals (STV), the high-level duration of each STV is generally (2n~4n)H. Its falling edge does not exceed the rising edge of the 2nth clock signal (CLK2n) and is generally not later than the falling edge of the first clock signal (CLK1). The period of the clock signal (CLK) is 4nH, and its high-level duration is less than or equal to 2nH. For example, when n is 3 (12CLK), the period is 12H, and the high-level duration of the clock signal (CLK) is 5H. The phase difference between CLK1 to CLK4n is 1H. G1 to Gs are the gate drive signals for progressively opening the display. The total number of lines (s) is related to the display resolution; for example, s is 2160 lines for UHD, 4320 lines for 8K, and so on. The phase difference between G1 to Gs is 1H. Data is the data signal of the source drive circuit, and the duration of each data signal is 2H. When displaying the first target data frame, the end of each data signal can be aligned with the falling edge of the gate drive signal of row 2k-1 (odd row). When displaying the second target data frame, the end of each data signal can be aligned with the falling edge of the gate drive signal of row 2k (even row).

[0130] Figure 8A is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to an embodiment of this disclosure. Figure 8B is a schematic diagram of extracting odd-numbered rows of data from an initial data frame according to an embodiment of this disclosure. As shown in Figures 8A and 8B, the main control board 40 extracts odd-numbered rows of data from an initial data frame to form a first target data frame, and extracts even-numbered rows of data from the initial data frame to form a second target data frame. Alternatively, it can extract odd-numbered rows of data from an initial data frame to form a second target data frame, and extract even-numbered rows of data from the initial data frame to form a first target data frame. By decomposing an initial data frame into odd-numbered and even-numbered frames, and displaying two frames of data using the time originally required to display one frame, the refresh rate of the display panel can be increased, thereby improving the display effect. For ease of description, in some of the following embodiments, odd-numbered frames and even-numbered frames are used to represent the first target data frame and the second target data frame.

[0131] For example, the display of the k-th initial data frame and the (k+1)-th initial data frame includes: the timing controller 30 controls the source driving circuit 20 and the gate driving circuit 10 to control the sub-pixel array to display frame by frame in the following order: the first target data frame of the k-th initial data frame, the second target data frame of the k-th initial data frame, the first target data frame of the (k+1)-th initial data frame; the second target data frame of the (k+1)-th initial data frame; or, the sub-pixel array is controlled to display frame by frame in the following order: the second target data frame of the k-th initial data frame, the first target data frame of the k-th initial data frame, the second target data frame of the (k+1)-th initial data frame, the first target data frame of the (k+1)-th initial data frame. In this manner, the first target data frame and the second target data frame of the initial data frame are displayed alternately. Figure 9 is a schematic diagram of extracting even-numbered rows of data from the initial data frame according to an embodiment of this disclosure. As shown in Figure 9, in mode 1 and mode 2, the first target data frame and the second target data frame are displayed alternately. The first initial data frame consists of an odd frame (b1) and an even frame (c1); the second initial data frame consists of an odd frame (b2) and an even frame (c2); the third initial data frame consists of an odd frame (b3) and an even frame (c3), and so on. In Mode 1, odd frames (b) can be displayed first, followed by even frames (c), for example, in the order of b1~c1~b2~c2~b3~c3… In Mode 2, even frames (c) can be displayed first, followed by odd frames (b), for example, in the order of c1~b1~c2~b2~c3~b3…

[0132] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the subpixel array; in the second frame, data of the second target data frame corresponding to the first initial data frame is applied to the subpixel array; in the third frame, data of the second target data frame corresponding to the second initial data frame is applied to the subpixel array; and in the fourth frame, data of the first target data frame corresponding to the second initial data frame is applied to the subpixel array.

[0133] For example, as shown in Figure 9, in modes 3 and 4, the odd and even frames corresponding to each initial data frame are displayed consecutively, and two adjacent odd frames and two adjacent even frames are displayed consecutively. In mode 3, they are displayed in the order b1~c1~c2~b2~b3~c3… In mode 4, they are displayed in the order c1~b1~b2~c2~c3~b3… The driving method for odd frames can be the same, and the driving method for even frames can be the same. By displaying adjacent odd frames consecutively and adjacent even frames consecutively, repeated switching of driving methods can be avoided, improving efficiency and saving power consumption.

[0134] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; and in the fourth frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0135] For example, as shown in Figure 9, in modes 5 and 6, odd-numbered frames of two adjacent initial data frames are displayed consecutively, as are even-numbered frames of two adjacent initial data frames. Each initial data frame is separated into odd and even frames. In mode 5, the frames are displayed in the order b1~b2~c1~c2~b3~b4… In mode 6, the frames are displayed in the order c1~c2~b1~b2~c3~c4… The driving methods for odd-numbered frames and even-numbered frames can be the same. By displaying adjacent odd-numbered frames consecutively and adjacent even-numbered frames consecutively, repeated switching of driving methods can be avoided, improving efficiency and saving power.

[0136] Next, the display method of applying 8 clock signals (8CLK) and 12 clock signals (10CLK) to the gate drive circuit 10 by the timing controller 30 will be described.

[0137] The cascaded relationship of the 8CLK gate drive circuit 10 is the same as that in Figures 2A and 2B, so it will not be repeated here. Figure 10 is a signal timing diagram for displaying odd-numbered frames in an embodiment of this disclosure; Figure 11 is a signal timing diagram for displaying even-numbered frames in an embodiment of this disclosure. As shown in Figures 10 and 11, 1H = 1.85μs; the high-level time of the frame start signal STV does not exceed the corresponding clock signal CLK number, that is, 8CLK, so the high-level time of STV does not exceed 8H, which can be 8H, 7H, or 6H. In this example, the effective level time of STV is 8H. CLK1 to CLK8 are periodic waveforms, and the period time is fixed to the number of CLK, that is, 8H. The high-level duty cycle is less than or equal to 50%, such as 4H or 3H or a non-integer. In this example, the high level is 3.2H and the duty cycle is 40%. The phase difference of the high level from CLK1 to CLK8 is shifted by 1H time.

[0138] In each frame, the gate driving circuit 10 sequentially generates the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, and the fourth gate driving signal G4 at preset time intervals, and so on up to Gs. The high-level width of G1 to Gs is the same as the width of the clock signal CLK, and is offset by 1H time width, that is, the preset time interval is 1H.

[0139] For each row of sub-pixels, when the gate line is written with a high level, the data line refreshes one row of data signals. Each row of sub-pixels requires 2 hours to write the data signal, during which the corresponding voltage is charged into the sub-pixel capacitor, completing the data refresh.

[0140] Specifically, referring to Figure 10, the writing time for each row of data signal is 2H, and the end time of data signal writing is aligned with the falling edge of the gate drive signal of the 2k-1th row of the sub-pixel array. At this time, the data signal written to the 2k-1th row of sub-pixels in odd-numbered frames is the actual data; the last 2H of the high level of the corresponding gate drive signal of the 2Kth row of sub-pixels, where 1H is the data signal written to the 2k-1th sub-pixel and the other 1H is the data signal written to the 2k+1th sub-pixel. In other words, the data signal actually written to the 2Kth row of sub-pixels is the interpolation of the data signals of the 2k-1th and 2k+1th sub-pixels, which is an intermediate grayscale value.

[0141] Similarly, referring to Figure 11, the writing time of each row of data signal is 2H, and the end time of data signal writing is aligned with the falling edge of the gate drive signal of the 2kth row of the sub-pixel array. At this time, the data signals written to the 2kth row of sub-pixels in even frames are real data; the 2K-1th row of sub-pixels (excluding the first row of sub-pixels) are written with the data signal at the end of the high level of their corresponding gate drive signal for the last 2H, where 1H is the data signal written to the 2k-2th sub-pixel and the other 1H is the data signal written to the 2kth sub-pixel. In other words, the data signal actually written to the 2Kth row of sub-pixels is the interpolation of the data signals of the 2k-2th sub-pixels and the 2kth sub-pixels, which is an intermediate grayscale value.

[0142] In the display method of the display device, the timing shown in Figures 10 and 11 works alternately to realize the inter-frame data inter-interpolation.

[0143] Figure 12 is a signal timing diagram of the display method according to an embodiment of the present disclosure. As shown in Figure 12, this example is the same as the above example and is also applied to the gate drive circuit 10 of 8CLK. The connection method of the shift register is the same as the above example. The difference from the above example is that in this example, the falling edge of the frame start signal STV is not earlier than the falling edge of the first clock signal.

[0144] Specifically, 1H = 3.7μs; the data signal writing time for each row of sub-pixels is 2H; the high level of the frame start signal STV is 4H-5H, and in this example, the high level of the frame start signal STV is 4.5H; CLK1 to CLK8 are periodic waveforms, with a fixed period of CLK, i.e., 8H; the high level duty cycle is less than or equal to 50%, such as 4H, 3H, or a non-integer; in this example, the high level is 2.66H with a duty cycle of 33%. In this example, the first four rows of sub-pixels are not written with data signals, and the fifth row of sub-pixels begins to be written with data signals, with a writing time of 2H.

[0145] The clock signals CLK are grouped into groups of two adjacent CLKs: CLK1 and CLK2, CLK3 and CLK4, CLK5 and CLK6, and CLK7 and CLK8. For any two adjacent groups, the rising edge delay of the two CLKs within one group is less than 1H (0.76H in this embodiment); the rising edge delay of the two CLKs within another group is greater than 1H (1.24H in this embodiment). Similarly, the rising edge delay of the two clock signals in each group can be controlled to be greater than 1H, while the rising edge delay of the two clock signals in the other group can be less than 1H. Alternatively, if the rising edge delay of the two clock signals in each group is 1H, then the rising edge delay of the adjacent CLK groups is also 1H, and the phase relationship of the CLK waveform is the same as in the previous example. In this embodiment, the phase difference between the rising edge of the k-th clock signal and the rising edge of the (k+1)-th clock signal is 2H.

[0146] Specifically, referring to Figure 12, in this example, the duration T1 of the high level of the frame start signal STV is 4.5H, and the durations of the high and low levels of the first clock signal CLK1 within one cycle are T2 and T3, respectively, where T2 = 2.66H and T3 = 5.34H; the phase difference between the rising edge of the frame start signal STV and the rising edge of the first clock signal CLK1 is T4, the phase difference between the rising edge of the frame start signal STV and the rising edge of the second clock signal CLK2 is T5, the phase difference between the rising edge of the frame start signal STV and the rising edge of the third clock signal CLK3 is T6, and the phase difference between the rising edge of the frame start signal STV and the rising edge of the fourth clock signal CLK1 is T6. The phase difference between the rising edge of K4 is T7, the phase difference between the rising edge of the frame start signal STV and the rising edge of the fifth clock signal CLK5 is T8, the phase difference between the rising edge of the frame start signal STV and the rising edge of the sixth clock signal CLK6 is T9, the phase difference between the rising edge of the frame start signal STV and the rising edge of the seventh clock signal CLK7 is T10, and the phase difference between the rising edge of the frame start signal STV and the rising edge of the eighth clock signal CLK8 is T11. T4 = 1.66; T5 = 2.42; T6 = 3.66; T7 = 4.42; T8 = 5.66; T9 = 6.42; T10 = 7.66; T11 = 8.42.

[0147] For writing a frame of data signal: There is no data signal for the first N / 2 rows of subpixels in the subpixel array (N is the total number of CLKs, which is 8 in this example), that is, no data signal is written for the subpixels from the 1st to the 4th row. Data signal is written starting from the 5th row of subpixels, and the writing time of the data signal is 2H (T12). The 1.08H of the first data signal is aligned with the last 1.08H (T13) of the high level of the gate drive signal of the 5th row of subpixels. Therefore, the writing of the data signal of the 5th row of subpixels ends. The 6th row of subpixels is written with 0.76H of the data signal of the 5th row of subpixels, and the data signal of the 6th row of subpixels is pre-charged by 0.16H. This makes the N / 2+2th row mix the first and second data signals, forming an effect similar to data interpolation.

[0148] Similarly, based on the timing design described above, the delay time of the two clock signals of each CLK group, the delay time of the two clock signals of CLK, and the data interpolation effect under other conditions can also be calculated.

[0149] The above embodiments are described with the gate drive circuit 10 connected to 8 CLK signals. In other embodiments, the gate drive circuit 10 may be connected to 12 CLK signals, and this case will be described below.

[0150] Figures 13A and 13B show example structural diagrams of another gate drive circuit 10 according to an embodiment of the present disclosure.

[0151] [Corrected according to Rule 91, 08.02.2025] Figure 13A shows the shift register units GOA1 to GOA13 from the first to the thirteenth level. As shown in Figure 13A, STV1 is the frame start signal. When the gate drive circuit 10 is connected to 12 CLKs, the input terminals of the shift register units GOA1 to GOA6 from the first to the sixth level can be connected to the frame start signal terminal STV1. After the sixth level shift register unit GOA4, the input terminal of the nth level shift register unit GOAn is connected to the output terminal of the (n-6)th level shift register unit GOA(n-4), where 7 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA7, the output of GOA2 is connected to the input of GOA8, the output of G3 is connected to the input of GOA9, the output of G4 is connected to the input of GOA10, the output of G5 is connected to the input of GOA11, and so on. The reset terminal RST of the nth-stage shift register unit GOAn is connected to the output terminal OUT of the (n+6)th-stage shift register unit GOA(n+6), where 1 ≤ n ≤ N-6. Figure 13B shows the last-stage shift register unit GOA4320 and the virtual shift register unit (Dummy GOA). As shown in Figure 13B, the last 6 rows of GOA can be reset through 6 rows of Dummy GOA. For example, Dummy GOA1 (Dum1) resets GOA4315, Dummy GOA2 (Dum2) resets GOA4316, and so on. Each Dummy GOA can be reset through STV1.

[0152] The gate drive circuit 10 shown in Figures 13A and 13B uses 12 clock signals CLK1 to CLK12. The clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on, with the clock signal terminal CLK of the 12th-stage shift register unit GOA12 connected to receive the 12th clock signal CLK12. Similarly, the 13th to 24th-stage shift register units GOA13 to GOA24 are connected to receive the first to 12th clock signals CLK1 to CLK12, respectively.

[0153] Each shift register unit GOA1, GOA2, ..., GOAN can generate an output signal as a gate drive signal (or gate scan signal) at its output OUT under the control of its clock signal CLK and input signals. For example, the first-stage shift register unit GOA1 generates a first gate drive signal G1, the second-stage shift register unit GOA2 generates a second gate drive signal G2, and so on. By cascading, the gate drive signal generated by one-stage shift register unit can be shifted relative to the gate drive signal generated by another-stage shift register unit.

[0154] For example, a GOA cascading relationship with a period of 12CLK can be applied to 8K4K products, or simply 8K.

[0155] Figure 14 is a signal timing diagram showing odd-numbered frames in an embodiment of this disclosure; Figure 15 is a signal timing diagram showing even-numbered frames in an embodiment of this disclosure. As shown in Figures 14 and 15, 1H = 1.85μs; the high-level duration of the frame start signal STV does not exceed the corresponding clock signal CLK number, i.e., 12CLK, so the high-level duration of the frame start signal STV does not exceed 12H, and can be 6H to 12H. In this example, the duration of the high-level duration of STV is 9H. CLK1 to CLK12 are periodic waveforms, with a fixed period of CLK number, i.e., 12H. The high-level duty cycle is less than or equal to 50%, such as 6H or 5H or a non-integer. In this example, the high level is 5H with a duty cycle of 40%. The phase difference of the high levels of CLK1 to CLK12 is shifted by 1H time sequentially. The falling edge of the frame start signal STV is aligned with the falling edge of the first clock signal CLK1.

[0156] In each frame, the gate driving circuit 10 sequentially generates the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, and the fourth gate driving signal G4 at preset time intervals, and so on up to Gs. The high-level width of G1 to Gs is the same as the width of the clock signal CLK, and is offset by 1H time width, that is, the preset time interval is 1H.

[0157] For each row of sub-pixels, when the gate line is written with a high level, the data line refreshes one row of data signals. Each row of sub-pixels requires 2 hours to write the data signal, during which the corresponding voltage is charged into the sub-pixel capacitor, completing the data refresh.

[0158] Specifically, referring to Figure 14, the writing time for each row of data signal is 2H, and the end time of data signal writing is aligned with the falling edge of the gate drive signal of the 2k-1th row of the sub-pixel array. At this time, the data signal written to the 2k-1th row of sub-pixels in odd-numbered frames is the actual data; the last 2H of the high level of the corresponding gate drive signal of the 2Kth row of sub-pixels, where 1H is the data signal written to the 2k-1th sub-pixel and the other 1H is the data signal written to the 2k+1th sub-pixel. In other words, the data signal actually written to the 2Kth row of sub-pixels is the interpolation of the data signals of the 2k-1th and 2k+1th sub-pixels, which is an intermediate grayscale value.

[0159] Similarly, referring to Figure 15, the writing time of each row of data signal is 2H, and the end time of data signal writing is aligned with the falling edge of the gate drive signal of the 2kth row of the sub-pixel array. At this time, the data signals written to the 2kth row of sub-pixels in even frames are real data; the 2K-1th row of sub-pixels (excluding the first row of sub-pixels) are written with the data signal at the end of the high level of their corresponding gate drive signal for the last 2H, where 1H is the data signal written to the 2k-2th sub-pixel and the other 1H is the data signal written to the 2kth sub-pixel. In other words, the data signal actually written to the 2Kth row of sub-pixels is the interpolation of the data signals of the 2k-2th sub-pixels and the 2kth sub-pixels, which is an intermediate grayscale value.

[0160] In the display method of the display device, the timing sequence shown in Figures 14 and 15 works alternately to realize the inter-frame data inter-interpolation.

[0161] Referring again to FIG1, this embodiment of the present disclosure provides a display device, including a main control board 40, a timing controller 30, a gate driving circuit 10, a source driving circuit 20, and a sub-pixel array; the sub-pixel array includes multiple gate lines and multiple data lines, and multiple sub-pixels defined by the intersection of the gate lines and data lines; wherein, the main control board 40 is configured to receive an initial data frame and divide the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered rows of data from the initial data frame, and the second target data frame includes even-numbered rows of data from the initial data frame. The timing controller 30 is configured to apply a frame start signal STV and multiple clock signals CLK to the gate drive circuit 10, and to apply a source control signal TP to the source drive circuit 20. The gate drive circuit 10 provides gate drive signals for multiple rows of gate lines based on the frame start signal STV and multiple clock signals CLK. The source drive circuit 20 controls the start time of writing the data signal for each row of sub-pixels based on the source control signal TP, with a phase difference between the start time and the end time of the effective level of the gate drive signal for writing to the gate line connected to that row of sub-pixels. 2H; H is half the start time phase difference of the effective level of the gate drive signal written to the k-th and (k+2)-th gate lines according to the scanning order; k is a positive integer; wherein, the source control signal and gate drive signal generated by the timing controller 30 satisfy the following when the source drive circuit 20 writes the data signal of the first target data frame to the odd-numbered sub-pixels: the start time of the data writing of the 2k-th row sub-pixels is not later than the end time of the data writing of the (2k-1)-th row sub-pixels, and the number of sub-pixels in the 2k-th row... The end time of data writing is not earlier than the start time of data writing of the 2k+1th row of sub-pixels; the source control signal and gate drive signal generated by the timing controller 30 write the data signal of the second target data frame line by line into the even-numbered rows of sub-pixels in the source drive circuit 20; and the source control signal and gate drive signal satisfy: the start time of data writing of the 2k+1th row of sub-pixels is not later than the end time of data writing of the 2kth row of sub-pixels, and the end time of data writing of the 2k+1th row of sub-pixels is not earlier than the start time of data writing of the 2k+2th row of sub-pixels.

[0162] This disclosure also provides an electronic device. FIG17 shows a schematic diagram of an electronic device according to an embodiment of this disclosure. As shown in FIG17, the electronic device 1 may include a display device 100. In addition, the electronic device 1 may also include devices such as a processor. The display device 100 can be referred to the display device in the above embodiments, and will not be described again here.

[0163] For example, the electronic device 1 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, or navigator, or any combination of electronic devices and hardware. The embodiments disclosed herein do not limit this.

[0164] It should be noted that, for clarity and brevity, this disclosure does not show all the constituent units of the electronic device 1. To achieve the necessary functions of the electronic device, those skilled in the art can provide and set other constituent units (not shown) according to specific needs, and this disclosure does not limit this.

[0165] For a description of the electronic device 1 and its technical effects, please refer to the description of the frequency divider provided in the embodiments of this disclosure, which will not be repeated here.

[0166] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display method applied to a display device, the display device comprising a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; The sub-pixel array includes multiple gate lines and multiple data lines, as well as multiple sub-pixels defined by the intersection of the gate lines and data lines; wherein, The display method includes: The main control board receives an initial data frame and divides the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered rows of data from the initial data frame, and the second target data frame includes even-numbered rows of data from the initial data frame; The timing controller applies a frame start signal and multiple clock signals to the gate drive circuit, and applies a source control signal to the source drive circuit; The gate driving circuit provides gate driving signals for the multiple rows of gate lines based on the frame start signal and the multiple clock signals; The source drive circuit, based on the source control signal, controls the start time of writing the data signal for each row of sub-pixels. The phase difference between this start time and the end time of the effective level of the gate drive signal written to the gate line connected to that row of sub-pixels is 2H. Here, H is half the phase difference between the start times of the effective levels of the gate drive signals written to the k-th and (k+2)-th gate lines according to the scan order. Here, k is a positive integer. Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the first target data frame line by line into the odd-numbered rows of sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of writing the data of the 2kth row of sub-pixels is not later than the end time of writing the data of the 2k-1th row of sub-pixels, and the end time of writing the data of the 2kth row of sub-pixels is not earlier than the start time of writing the data of the 2k+1th row of sub-pixels; Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the second target data frame line by line into even-numbered sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of writing the data of the (2k+1)th row of sub-pixels is not later than the end time of writing the data of the (2k+1)th row of sub-pixels, and the end time of writing the data of the (2k+1)th row of sub-pixels is not earlier than the start time of writing the data of the (2k+2)th row of sub-pixels.

2. The display method according to claim 1, wherein, The duration for which the gate drive signals of two adjacent rows of sub-pixels are simultaneously active is not less than 2H.

3. The display method according to claim 1, wherein, The gate drive circuit includes multiple shift register units; one shift register unit is connected to one gate line, and different shift register units are connected to different gate lines; The plurality of clock signals include a first clock signal for controlling the first-stage shift register unit in the gate drive circuit to output a gate drive signal; Wherein, the start time of the effective level of the frame start signal output by the timing controller is earlier than the start time of the effective level of the first clock signal; the phase difference between the end time of the effective level of the frame start signal and the end time of the effective level of the first clock signal is greater than or equal to 0.2H and less than or equal to 0.6H.

4. The display method according to claim 3, wherein, The gate drive circuit includes N levels of shift register units; the first level to the P level shift register units are connected to the frame start signal; the plurality of clock signals also includes a P-th clock signal for controlling the output gate drive signal of the P-th level shift register unit; the duty cycle of each clock signal is less than or equal to 50%, and N is greater than P; And P is an integer greater than 1.

5. The display method according to claim 4, wherein, The phase difference between the start times of the effective levels of any two adjacent clock signals in the plurality of clock signals is 1H, the end time of the effective level of the frame start signal is no later than the end time of the effective level of the first clock signal, and the duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%.

6. The display method according to claim 5, wherein, The duty cycle of each clock signal is 40%, and the duration of the effective level of the gate drive signal is 3.2H; the phase difference between the end time of the effective level of the frame start signal and the end time of the effective level of the first clock signal is 0.2H. The plurality of clock signals includes 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group including 8 shift register units, and each of the 8 shift register units in the group receives the 8 clock signals respectively; The timing controller writes the frame start signal to the first-level shift register unit to the fourth-level shift register unit among the N shift register units.

7. The display method according to claim 4, wherein, The end time of the effective level of the frame start signal is later than the end time of the effective level of the first clock signal; the phase difference between the start times of the effective levels of the gate drive signals applied to the gate lines in the kth row and the (K+1)th row is 1H; each pair of adjacent clock signals is a group, and for adjacent groups of clock signals, the timing controller controls the phase difference between the start times of the effective levels of one group of clock signals to be less than 1H, and the phase difference between the start times of the effective levels of the other group of clock signals to be greater than 1H.

8. The display method according to claim 7, wherein, The duty cycle of each clock signal is 33%, and the duration of the effective level of the gate drive signal is 2.66H; for adjacent groups of clock signals, the timing controller controls the phase difference of the start time of the effective level of one group of clock signals to be 0.76H, and the phase difference of the start time of the effective level of the other group of clock signals to be 1.24H. The plurality of clock signals includes 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group including 8 shift register units, and each of the 8 shift register units in the group receives the 8 clock signals respectively; The timing controller writes the frame start signal to the first-level shift register unit to the fourth-level shift register unit among the N shift register units.

9. The display method according to claim 1, wherein, The plurality of clock signals includes a first clock signal for controlling the first-stage shift register unit in the gate driving unit to output a gate driving signal; The plurality of clock signals include a first clock signal for controlling the first-stage shift register unit in the gate drive circuit to output a gate drive signal; Wherein, the start time of the effective level of the frame start signal output by the timing controller is earlier than the start time of the effective level of the first clock signal; the end time of the effective level of the frame start signal is the same as the end time of the effective level of the first clock signal.

10. The display method according to claim 9, wherein, The gate drive circuit includes N levels of shift register units; the first level shift register units to the P level shift register units are connected to the frame start signal; the plurality of clock signals also includes a P-th clock signal for controlling the P-th level shift register unit to output the gate drive signal; The first-stage shift register unit to the P-stage shift register unit are connected to the frame start signal; The plurality of clock signals also includes a P-th clock signal for controlling the output gate drive signal of the P-th stage shift register unit; the duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%, and N is greater than P; And P is an integer greater than 1.

11. The display method according to claim 10, wherein, The phase difference between the start times of the effective levels of any two adjacent clock signals in the plurality of clock signals is 1H, and the duty cycle of each clock signal is 41.6%.

12. The display method according to claim 11, wherein, The effective level of the gate drive signal lasts for 5 hours, and the pre-charge period lasts for 3 hours. The plurality of clock signals includes 12 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group including 12 shift register units, and each of the 12 shift register units in the group receives the 12 clock signals respectively; The timing controller writes the frame start signal to the first to sixth level shift register units among the N shift register units.

13. The display method according to any one of claims 1-12, wherein, When the sub-pixel is selected by the effective level of the gate drive signal, the time period is divided into a pre-charging time period and a charging time period. The charging period is the data signal writing period of the sub-pixel, and the duration of the pre-charging period is greater than 1 hour.

14. The display method according to any one of claims 1-12, wherein, The display of the k-th initial data frame and the (k+1)-th initial data frame includes: The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order: The first target data frame of the k-th initial data frame; The second target data frame of the k-th initial data frame; The first target data frame of the (k+1)th initial data frame; The second target data frame of the (k+1)th initial data frame.

15. The display method according to any one of claims 1-12, wherein, The display of the k-th initial data frame and the (k+1)-th initial data frame includes: The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order: The second target data frame of the k-th initial data frame; The first target data frame of the k-th initial data frame; The second target data frame of the (k+1)th initial data frame; The first target data frame of the (k+1)th initial data frame.

16. A display device comprising a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array comprising multiple gate lines and multiple data lines, and multiple sub-pixels defined by the intersection of the gate lines and data lines; wherein, The main control board is configured to receive an initial data frame and divide the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered rows of data from the initial data frame, and the second target data frame includes even-numbered rows of data from the initial data frame. The timing controller is configured to apply a frame start signal and a plurality of clock signals to the gate drive circuit, and to apply a source control signal to the source drive circuit. The gate driving circuit provides gate driving signals for the multiple rows of gate lines based on the frame start signal and the multiple clock signals; The source drive circuit, based on the source control signal, controls the start time of writing the data signal for each row of sub-pixels. The phase difference between this start time and the end time of the effective level of the gate drive signal written to the gate line connected to that row of sub-pixels is 2H. Here, H is half the phase difference between the start times of the effective levels of the gate drive signals written to the k-th and (k+2)-th gate lines according to the scan order. Here, k is a positive integer. When the source drive circuit writes the data signal of the first target data frame line by line into odd-numbered sub-pixels, the source control signal and the gate drive signal generated by the timing controller satisfy the following: the start time of writing the data of the 2kth row of sub-pixels is not later than the end time of writing the data of the 2k-1th row of sub-pixels, and the end time of writing the data of the 2kth row of sub-pixels is not earlier than the start time of writing the data of the 2k+1th row of sub-pixels. The source control signal and the gate drive signal generated by the timing controller are used in the source drive circuit to write the data signal of the second target data frame line by line into even-numbered sub-pixels; and the source control signal and the gate drive signal satisfy the following: the start time of the data writing of the 2k+1th row of sub-pixels is not later than the end time of the data writing of the 2kth row of sub-pixels, and the end time of the data writing of the 2k+1th row of sub-pixels is not earlier than the start time of the data writing of the 2k+2th row of sub-pixels.

17. An electronic device comprising the display device as claimed in claim 16.

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