Image sensor and preparation method therefor

Abstract

Disclosed in the present invention is an image sensor. By means of setting the same function for at least two transistors in adjacent pixel sub-arrays and configuring at least one type of transistors having the same function to share one gate electrode, the requirements for the shape and size of an opening of an isolation trench are avoided, and the process difficulty of a flow for the isolation trench is greatly reduced. Therefore, isolation distances from a functional tube to a vertical transfer transistor, a floating diffusion region, etc., in the surrounding can be made greater, and the number of required metal connecting lines is greatly reduced, thereby simplifying the arrangement of a metal layer layout, narrowing the area of a chip of the image sensor and reducing the production costs; the symmetry and compactness of the entire layout of an image sensor array are improved, thereby reducing a yield loss caused by asymmetry and reducing the production costs; and the compatibility in the aspects of the structural design, manufacturing process, etc., of pixels shared by different numbers of photodiodes is improved.

Description

Image sensor and preparation method thereof This application claims priority to the Chinese patent application filed with the China Patent Office on December 20, 2023, with application number 2023117662412 and invention name “An image sensor and its preparation method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0001] The present invention relates to the field of sensors, and in particular to an image sensor and a preparation method thereof. Background Art

[0002] With the rapid development and widespread application of image sensors, performance requirements are increasing. To meet the high-pixel requirements of image sensors, the size of sensor pixels is becoming smaller and smaller, and the process requirements are becoming increasingly stringent. Based on current process design, the pixel layout design of existing image sensors typically designs transistors with corresponding functions for each pixel. Since multiple transistors are arranged in the pixel spacing area to meet different functions, this makes the process difficult to manufacture, and the resulting image sensors lack advantages in terms of size and quality. The current pixel layout design has become a bottleneck in improving sensor quality and reducing costs.

[0003] For example, as shown in Figures 1a-1b, Figure 1a is an equivalent circuit diagram of a conventional 3T4shared (3T: having a source follower transistor (SF), a gain conversion transistor (DCG), an RST (reset transistor), and no select transistor (SEL); 4shared: four photodiodes share the 3T). Figure 1b is a partial schematic diagram of a conventional 3T4shared image sensor array layout design, Figure 1c is a schematic diagram of the different transistors corresponding to the two sides of the isolation trench, and Figure 1d is a simplified schematic based on Figure 1b (Note: Figure 1d is only a schematic diagram; the boundary lines do not represent actual boundaries). A pixel unit p is defined, and a pixel subarray s-pa includes four shared pixel units p. Multiple pixel subarrays s-pa are arranged in an array along the horizontal and vertical directions to form the photosensitive array of the image sensor. Among them, a pixel unit p can include a photodiode, and the pixel unit p can also include a transfer transistor Tx. It can be seen that in the layout of the existing pixel sub-array s-pa, the source follower transistor (SF) is placed on one side of the floating diffusion area in the column direction, the gate is connected to the floating diffusion area, the drain end is connected to the high voltage, and the source end serves as the output signal end PXD; the gain conversion transistor (DCG) and the reset transistor (RST) are placed on one side of the floating diffusion area in the row direction, the source end of the gain conversion transistor (DCG) is connected to the floating diffusion area, the drain end of the gain conversion transistor (DCG) is connected to the source end of the reset transistor (RST), and the drain end of the reset transistor (RST) is connected to the high voltage end. Among them, as shown in Figures 1c-1d, DCG (gain conversion transistor) and RST (reset transistor) are respectively arranged on both sides of the same trench PBT (isolation trench structure (PB Trench, PBT), PBT can be a deep trench or a shallow trench), and the gates G1 and G2 of each other are separated by a distance L through the trench PBT, and the sources S1, S2 and drains D1, D2 are also separated by the trench PBT. Corresponding to adjacent pixel sub-arrays, transistors with different functions are respectively on both sides of the trench, and the gates of transistors with the same function in the same row are led out through a row selection line, and the gates of transistors with the same function in different rows are respectively led out through their respective row selection lines. Taking the DCG and RST shown in Figures 1c-1d as an example, since the two transistors DCG (gain conversion transistor) and RST (reset transistor) have different functions, they need to have different working timings. For transistors with a certain function, a separate row selection line is required for each row.Under these layout requirements, the gates of these two transistors must be separated during fabrication using an etching process. Due to the resolution limitations of photolithography and etching, a sufficient distance L must be reserved between the gates of these two adjacent transistors to ensure that the two gates can be completely etched apart during the process. However, due to density limitations, existing designs can only design the trench width to be larger than the isolation limit of the surrounding pixel cells, requiring the pixel isolation spacing to be further increased to meet the required distance L. This significantly affects the layout utilization of components in the photosensor array, hindering the increase in image sensor pixel density and further reducing the size of the image sensor. Furthermore, the large trench opening line width also creates difficulties in the polysilicon filling step. Because the trench filling growth process cannot ensure a consistent growth rate at different depths throughout the trench, the large opening can easily cause some areas within the trench to remain unfilled, leaving cavities of uncontrollable size. These cavities have a serious impact on the cleanliness and consistency of subsequent processes.

[0004] Furthermore, to balance device quality and production costs, different numbers of pixel units are typically designed for sharing. The aforementioned problems with the 3T 4shared image sensor also exist in image sensors with an increased number of shared pixel units. Furthermore, existing technologies typically design dedicated circuit layouts and manufacturing processes for each pixel unit sharing configuration, making them incompatible with each other. This exponentially increases both the circuit layout design costs and the subsequent device manufacturing process costs, making it extremely difficult for companies to reduce costs and achieve mass production.

[0005] Therefore, it is becoming increasingly urgent to rethink the pixel layout design to solve the aforementioned series of problems in order to improve the quality of image sensors and reduce costs. Summary of the Invention

[0006] To solve the above problems, the present disclosure provides an image sensor, which includes an image sensor photosensitive array composed of multiple pixel sub-arrays, wherein the pixel sub-arrays include a number of pixel units and transistors with different functions, and the pixel units include photodiodes. At least one transistor with the same function in adjacent pixel sub-arrays shares a gate to optimize the process and wiring of the image sensor; wherein the transistors include one or more of a source follower transistor, a reset transistor, a gain conversion transistor, and a select transistor.

[0007] In a preferred embodiment, the transistors with the same function that share a gate include at least two transistors, and the at least two transistors with the same function are channel-isolated by an isolation trench.

[0008] In a preferred embodiment, the channels of the two transistors with the same function that share a gate are parallel to each other.

[0009] In a preferred embodiment, the source and drain of the two transistors with the same function that share a gate are isolated by an isolation trench.

[0010] In a preferred embodiment, the common gate extends along the row direction, or along the column direction, or along a direction forming an angle of 45° with the row direction or the column direction.

[0011] In a preferred embodiment, the source follower transistor is exclusively used by the corresponding pixel sub-array.

[0012] In a preferred embodiment, at least one of the reset transistor, the gain conversion transistor, and the selection transistor has the same function as the other transistors and shares a gate electrode for adjacent pixel sub-arrays.

[0013] In a preferred embodiment, the transistors having the same function share a gate for use in adjacent pixel sub-arrays include:

[0014] Two transistors with the same function that share a gate are exclusively used by different adjacent pixel sub-arrays;

[0015] Alternatively, two transistors with the same function and sharing a gate are shared by adjacent different pixel sub-arrays.

[0016] In a preferred embodiment, the adjacent includes adjacent in a row direction and / or adjacent in a column direction.

[0017] In a preferred embodiment, each of the pixel sub-arrays includes one reset transistor, one gain conversion transistor, one or two source follower transistors, and four shared pixel units.

[0018] In a preferred embodiment, in the first direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, and the gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate.

[0019] In a preferred embodiment, there are adjacent first pixel subarrays and second pixel subarrays with different transistor function arrangement positions, the first pixel subarrays and the second pixel subarrays constitute a pixel module, and the image sensor photosensitive array is formed by repeatedly arranging the pixel modules in a first direction and a second direction, and the first direction and the second direction are orthogonal.

[0020] In a preferred embodiment, in the first pixel subarray, the reset transistor is located on the first side of the first pixel subarray in the first direction, and the gain conversion transistor is located on the second side of the first direction of the first pixel subarray; in the second pixel subarray, the reset transistor is located on the second side of the first direction of the second pixel subarray, and the gain conversion transistor is located on the first side of the first direction of the second pixel subarray; and the reset transistor and the gain conversion transistor are located in the same row.

[0021] In a preferred embodiment, the source follower transistor is located on one of two sides of the pixel sub-array in the second direction.

[0022] In a preferred embodiment, each of the pixel sub-arrays includes a number of reset transistors, a number of gain conversion transistors, a number of source follower transistors, a number of selection transistors, and 8, 9, or 16 shared pixel units.

[0023] In a preferred embodiment, the plurality of gain conversion transistors of each pixel subarray include a plurality of first gain conversion transistors and a plurality of second gain conversion transistors;

[0024] When the pixel subarray includes 8 shared pixel units, each of the pixel subarrays includes a reset transistor, a first gain conversion transistor, a reset transistor, and a second gain conversion transistor;

[0025] When the pixel subarray includes 9 shared pixel units, each of the pixel subarrays includes a reset transistor and a first gain conversion transistor, and the plurality of second gain conversion transistors include a plurality of first sub-gain conversion transistors and a plurality of second sub-gain conversion transistors;

[0026] When the pixel subarray includes 16 shared pixel units, the plurality of gain conversion transistors further include two third gain conversion transistors, and each of the pixel subarrays includes two reset transistors, two first gain conversion transistors, two second gain conversion transistors, and two third gain conversion transistors.

[0027] In a preferred embodiment, when the pixel subarray includes 9 shared pixel units, the pixel subarrays adjacent in the first direction share the plurality of second sub-gain conversion transistors, and the pixel subarrays adjacent in the second direction share the plurality of first sub-gain conversion transistors;

[0028] When the pixel sub-array includes 16 shared pixel units, the third gain conversion transistors of adjacent pixel sub-arrays in the second direction are shared, and / or the second gain conversion transistors of adjacent pixel sub-arrays in the first direction are shared.

[0029] In a preferred embodiment, when the pixel subarray includes eight shared pixel units, the reset transistor and the first gain conversion transistor are respectively located on both sides of the pixel subarray in a first direction and in the same row, and the second gain conversion transistor is located on one side of the pixel subarray in a second direction and in a different row or column from the reset transistor and the first gain conversion transistor.

[0030] When the pixel subarray includes 9 shared pixel units, the reset transistor and the first sub-gain conversion transistor are respectively located on both sides of the pixel subarray in the second direction and are located in different rows or columns, and the first gain conversion transistor and a plurality of second sub-gain conversion transistors are respectively located on both sides of the pixel subarray in the first direction and are located in different rows or columns;

[0031] When the pixel subarray includes 16 shared pixel units, the two reset transistors are located in the same row and on one side of the pixel subarray in the second direction, the two first gain conversion transistors are located in the same row and on both sides of the pixel subarray in the first direction, the two second gain conversion transistors are located in the same row and on both sides of the pixel subarray in the first direction, and the two third gain conversion transistors are located in the same row and on the other side of the pixel subarray in the second direction; wherein the reset transistor, the first gain conversion transistor, the second gain conversion transistor, and the third gain conversion transistor are respectively located in different rows.

[0032] In a preferred embodiment, when the pixel subarray includes eight shared pixel units, in a first direction, the reset transistors in adjacent pixel subarrays share a gate, and the first gain conversion transistors in adjacent pixel subarrays share a gate; and in a second direction, the second gain conversion transistors in adjacent pixel subarrays share a gate.

[0033] When the pixel subarray includes 9 shared pixel units, in a first direction, the first gain conversion transistors located in adjacent pixel subarrays share a gate, and every two of the shared second sub-gain conversion transistors share a gate; in a second direction, the reset transistors located in adjacent pixel subarrays share a gate, and every two of the shared first sub-gain conversion transistors share a gate;

[0034] When the pixel subarray includes 16 shared pixel units, in a first direction, the first gain conversion transistors respectively located in adjacent pixel subarrays share a gate, and the second gain conversion transistors respectively located in adjacent pixel subarrays share a gate; in a second direction, the reset transistors respectively located in adjacent pixel subarrays share a gate, and the third gain conversion transistors respectively located in adjacent pixel subarrays share a gate.

[0035] In a preferred embodiment, when the pixel subarray includes eight shared pixel units, the pixel subarray includes two source follower transistors and two select transistors exclusively used by the pixel subarray, the two source follower transistors share a gate, and the two select transistors share a gate, and the select transistor is in a different row from the source follower transistor, the reset transistor, the first gain conversion transistor, and the second gain conversion transistor;

[0036] When the pixel subarray includes 9 shared pixel units, the pixel subarray includes two source follower transistors and two select transistors exclusively shared by the pixel subarray, the two source follower transistors share a gate, and the two select transistors share a gate, the source follower transistor is in the same row as the first gain conversion transistor, and the select transistor is in the same column as the reset transistor;

[0037] When the pixel subarray includes 16 shared pixel units, the pixel subarray includes six source follower transistors and two selection transistors that are exclusively shared by the pixel subarray, and every two source follower transistors share a gate to form a group, and the two selection transistors share a gate. The source follower transistor is either in the same row as the first gain conversion transistor, or in the same row as the second gain conversion transistor, or in the same column as the reset transistor and the third gain conversion transistor, and the selection transistor is in the same column as the reset transistor and the third gain conversion transistor that are not in the same column as the source follower transistor; or, the pixel subarray includes four source follower transistors and four selection transistors that are exclusively shared by the pixel subarray, and every two source follower transistors share a gate to form a group, and every two selection transistors share a gate. The source follower transistor is either in the same row as the first gain conversion transistor, or in the same row as the second gain conversion transistor, and the selection transistor is in the same column as the reset transistor and the third gain conversion transistor.

[0038] In a preferred embodiment, when the pixel subarray includes 8 shared pixel units, the source follower transistor is located inside the pixel subarray, and the selection transistor is located on one side of the pixel subarray in the first direction; when the pixel subarray includes 9 or 16 shared pixel units, the source follower transistor and the selection transistor are both located inside the pixel subarray.

[0039] In a preferred embodiment, a gate terminal of the first sub-gain conversion transistor is connected to a control signal; and a gate terminal of the second sub-gain conversion transistor is grounded.

[0040] In a preferred embodiment, when the pixel subarray includes eight shared pixel units, each pixel subarray further includes a reserved function transistor. In the second direction, the second gain conversion transistor and the reserved function transistor are respectively located on both sides of the pixel subarray, wherein the gate, source, and drain terminals of the reserved function transistor are all connected to a high level to control interface leakage.

[0041] In a preferred embodiment, there are a first pixel subarray, a second pixel subarray, a third pixel subarray, and a fourth pixel subarray with different transistor function arrangement positions, the first pixel subarray, the second pixel subarray, the third pixel subarray, and the fourth pixel subarray constitute a pixel module, and the image sensor photosensitive array is formed by repeatedly arranging the pixel modules in the first direction and the second direction.

[0042] In a preferred embodiment, in a first direction, the first pixel subarray and the second pixel subarray are adjacent, and the third pixel subarray and the fourth pixel subarray are adjacent; in a second direction, the first pixel subarray and the third pixel subarray are adjacent, and the second pixel subarray and the fourth pixel subarray are adjacent; the first direction is orthogonal to the second direction; and the pixel module is symmetrical about a boundary adjacent line of any two of the first pixel subarray, the second pixel subarray, the third pixel subarray, and the fourth pixel subarray.

[0043] In a preferred embodiment, when 8 shared pixel units are shared, the 8 shared pixel units are arranged into 4 rows and 2 columns; when 9 shared pixel units are shared, the 9 shared pixel units are arranged into 3 rows and 3 columns; when 16 shared pixel units are shared, the 16 shared pixel units are arranged into 4 rows and 4 columns.

[0044] In addition, a method for preparing an image sensor is provided, which is used to prepare the image sensor described in any of the aforementioned embodiments, wherein at least one transistor with the same function in adjacent pixel subarrays is arranged on both sides of the trench, and a common gate of the transistors with the same function is fabricated to optimize the process and wiring of the image sensor.

[0045] The image sensor provided by the present disclosure has the following beneficial effects by setting the functions of at least two adjacent transistors to be the same, and setting at least one transistor with the same function in adjacent pixel subarrays to share a gate:

[0046] (1) It avoids separating the gates of two adjacent transistors to avoid the requirements on the opening shape of the isolation trench when manufacturing the transistors, greatly reducing the process difficulty of the isolation trench process.

[0047] (2) The layout size is reduced, so that the isolation distance between the functional transistor and the surrounding vertical transfer transistors, floating diffusion areas, etc. can be made larger, which can improve the manufacturing density of the device.

[0048] (3) Due to the merging of the gates of transistors with the same function, the number of control lines required can be greatly reduced, the metal layer layout can be simplified, and the production cost can be reduced.

[0049] (4) Setting at least one transistor with the same function to share a gate can make the functional transistors arranged uniformly and symmetrically, thereby improving the symmetry and compactness of the entire layout of the image sensor array, reducing the yield loss caused by asymmetric differences, reducing the image sensor chip area, and reducing the production cost of the image sensor.

[0050] (5) By setting the functions of at least two transistors in adjacent pixel sub-arrays to be the same and sharing a gate, the structural design and manufacturing process shared by different numbers of pixel units can be made compatible to a great extent, which can greatly promote cost reduction and mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The present invention will be further described in the form of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, like numbers represent like structures, wherein:

[0052] FIG1a is a schematic diagram of an equivalent circuit of a sensor in the prior art.

[0053] FIG1 b is a schematic diagram of a sensor layout in the prior art.

[0054] FIG1c is a simplified schematic diagram of transistors on both sides of an isolation trench in the prior art.

[0055] FIG. 1 d is a simplified schematic diagram of a pixel arrangement of a sensor in the prior art.

[0056] FIG. 2 a is a simplified schematic diagram of the pixel arrangement of the sensor of the present disclosure.

[0057] FIG. 2 b is a schematic diagram showing transistors with the same function sharing a gate according to the present disclosure.

[0058] FIG3 a is a schematic diagram of an equivalent circuit of multiple pixel sub-arrays of a sensor according to the first embodiment of the present disclosure.

[0059] FIG3 b is a schematic diagram of a circuit layout of the sensor according to the first embodiment of the present disclosure.

[0060] FIG. 3 c is a simplified schematic diagram of the pixel arrangement of the sensor according to the first embodiment of the present disclosure.

[0061] FIG3 d is a schematic diagram of a circuit layout of the first embodiment of the present disclosure.

[0062] FIG4a is a schematic diagram of the basic equivalent circuit of 4T8shared.

[0063] FIG4 b is a schematic diagram of an equivalent circuit of a pixel subarray according to the second embodiment of the present disclosure.

[0064] FIG4 c is a schematic diagram of an equivalent circuit of multiple pixel sub-arrays of a sensor according to the second embodiment of the present disclosure.

[0065] FIG4 d is a simplified schematic diagram of pixel arrangement according to the second embodiment of the present disclosure.

[0066] FIG4e is a schematic diagram of a circuit layout of the second embodiment of the present disclosure.

[0067] FIG5a is a schematic diagram of the basic equivalent circuit of 4T9shared.

[0068] FIG5 b is a schematic diagram of an equivalent circuit of a pixel subarray according to the third embodiment of the present disclosure.

[0069] FIG5 c is a schematic diagram of an equivalent circuit of multiple pixel sub-arrays of a sensor according to the third embodiment of the present disclosure.

[0070] FIG5 d is a simplified schematic diagram of pixel arrangement according to the third embodiment of the present disclosure.

[0071] FIG5e is a schematic diagram of a circuit layout of the third embodiment of the present disclosure.

[0072] FIG. 6 a - 1 is a schematic diagram of an equivalent circuit of a pixel sub-array according to the fourth embodiment of the present disclosure.

[0073] FIG6 a - 2 is another schematic diagram of an equivalent circuit of a pixel sub-array according to the fourth embodiment of the present disclosure.

[0074] FIG. 6 b - 1 is a schematic diagram of an equivalent circuit of multiple pixel sub-arrays of a sensor according to the fourth embodiment of the present disclosure.

[0075] FIG6 b - 2 is another schematic diagram of an equivalent circuit of multiple pixel sub-arrays of a sensor according to the fourth embodiment of the present disclosure.

[0076] FIG6 c - 1 is a simplified schematic diagram of a pixel arrangement according to the fourth embodiment of the present disclosure.

[0077] FIG6 c - 2 is another simplified schematic diagram of pixel arrangement according to the fourth embodiment of the present disclosure.

[0078] FIG6 d is an example of a circuit layout diagram of the fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0079] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly describes the drawings required for describing the embodiments. Obviously, the drawings described below are merely examples or embodiments of the present invention. Those skilled in the art can apply the present invention to other similar scenarios based on these drawings without inventive effort. Unless otherwise apparent from the context or otherwise noted, the same reference numerals in the figures represent the same structure or operation.

[0080] The problems mentioned in the background technology are described below with reference to specific embodiments.

[0081] The present disclosure provides an image sensor, as shown in FIG2a (Note: This figure is merely a schematic diagram, used to indicate the existence of various structures. The lines do not represent actual boundary alignment, nor do the spacing distances represent actual conditions). This is a simplified schematic diagram of the pixel arrangement of the sensor of the present disclosure. Tr represents a module in which at least two transistors with the same function share a common gate, correspondingly forming a group of transistors Tr. In FIG2a, the direction in which the long side of the module illustrated in the transistor group Tr extends represents the arrangement direction of the two or more transistors with the same function sharing a common gate, and also represents the direction in which the common gate of the transistor group Tr extends. The common gate can extend in the row direction, in the column direction, or in a direction at a 45° angle to the row or column direction. The specific design can be appropriately determined based on the specific conditions of the spacing area between pixel units p. p represents a pixel unit. A pixel subarray can include multiple pixel units p and multiple transistors with different functions. Multiple pixel subarrays can constitute an image sensor photosensitive array, which is used to form an image sensor. The pixel unit p can include a photodiode and a transfer transistor Tx. Among them, at least one transistor with the same function in adjacent pixel sub-arrays shares a gate, and a group of transistors Tr sharing a gate is used to provide one or more functions including but not limited to a source follower transistor, a reset transistor, a gain conversion transistor, and a selection transistor, so as to optimize the process and wiring of the image sensor.

[0082] Furthermore, as shown in FIG2a , pixel cells p are repeatedly arranged along a first direction (row direction, or X direction) and a second direction (column direction, or Y direction) to form an array, with pixel gaps formed between adjacent pixel cells p. A first transistor group Tr-x, formed by two or more transistors with the same function arranged along the first direction (i.e., with a shared gate extending along the row direction), is arranged in columns in the second direction with two rows of pixel cells p spaced apart, and in rows with two columns of pixel cells p spaced apart in the first direction. A second transistor group Tr-y, formed by two or more transistors with the same function arranged along the second direction (i.e., with a shared gate extending along the column direction), is arranged in columns in the second direction with two rows of pixel cells p spaced apart, and in rows with two columns of pixel cells p spaced apart in the first direction. Furthermore, the first transistor group Tr-x and the second transistor group Tr-y are not in the same row or column, and the first transistor group Tr-x and the second transistor group Tr-y form a pixel gap region between adjacent pixel cells p. By setting the functions of adjacent transistors on either side of the trench to be the same, the gates of the two adjacent transistors are not separated, thereby avoiding the requirements for the isolation trench opening shape during transistor fabrication, and significantly reducing the process difficulties of the isolation trench process. According to the arrangement shown in FIG. 2a , the symmetry and compactness of the entire layout of the image sensor array can be significantly improved, the yield loss caused by asymmetric differences can be reduced, the image sensor chip area can be reduced, and the production cost of the image sensor can be reduced. Moreover, this arrangement can be adapted to the design and production of image sensors that share different numbers of pixel units p. During the layout design stage, it is only necessary to rationally design the functions of the transistor group Tr surrounding the pixel unit p based on the circuit required by the actual number of pixel units p shared. This process only requires changing the metal layer routing. During the process manufacturing process, it is also possible to focus only on the metal layer routing. In other words, except for the routing metal layer, other structural designs and manufacturing processes required to realize image sensors that share different numbers of pixel units are compatible, which can greatly promote the cost reduction and mass production of image sensors. Moreover, due to the merging of the gates of the transistors with the same function in the transistor group Tr, the number of control lines required can be greatly reduced, and the metal layer routing can be greatly simplified, which can further reduce the device size and reduce production costs. (Note: The number of rows of spacing is only for the simplified schematic. In actual layouts, the rows and columns of different components often have curved contours and fit together. Therefore, the spacing mentioned throughout this article is not limited to absolute spacing. For example, the two adjacent Tr-x in the first row are not actually separated by two columns, but are formed in the gap between two columns of pixel units p.)

[0083] Figure 2b shows a schematic diagram of a transistor group Tr, formed by two transistors with the same function sharing a common gate. The two transistors with the same function include source and drain electrodes S1 and D1, and S2 and D2, respectively, and share a common gate G. A transistor group Tr simply represents the group of transistors with the same function sharing a common gate, and does not represent a specific function. That is, a transistor group Tr can have the same or different functions as another transistor group Tr. Figure 2a illustrates that each transistor group Tr is sequentially arranged between each pixel unit p, which is the most preferred configuration. However, in other embodiments, the number of rows or columns spaced in each direction may not be limited to the aforementioned two rows or two columns. For example, in the first direction, each transistor group Tr is spaced at least two columns of pixel units p apart, and in the second direction, each transistor group Tr is spaced at least two columns apart. Furthermore, the column positions of each transistor group Tr in the first direction are spaced at least one column apart from the column positions of each transistor group Tr in the second direction. For ease of understanding, as shown in Figure 2a, the first transistor group Tr-x and the second transistor group Tr-y, which are closest in position, are spaced at least one column apart. Moreover, the arrangement is not limited to the global arrangement of the sensor array as shown in FIG2a. In other embodiments, the arrangement may be performed only on a portion of the sensor array according to actual needs. For example, the arrangement may be performed only on the periphery or a portion of the corners of the sensor array, or only on the center of the sensor array.

[0084] Preferably, transistors with the same function share a gate. For example, one or more of the following may be used: two source follower transistors share a gate; two reset transistors share a gate; two gain conversion transistors share a gate; and two select transistors share a gate. Other transistors with the same function may also share a gate. Preferably, the number of transistors with the same function sharing a gate is not limited to two, but may be more than two, for example, three, four, etc.

[0085] Preferably, the group of transistors Tr with the same function sharing a gate includes at least two, and the channels of at least two transistors with the same function are isolated by an isolation trench. The channels of the two transistors with the same function sharing a gate are parallel to each other. Optionally, the channels of the two transistors with the same function sharing a gate can also be formed at a certain angle on both sides of the isolation trench. For example, the channels of the transistors extend at a certain angle to the direction in which the isolation trench extends, for example, at a 45° angle. Preferably, the channels of the two transistors with the same function sharing a gate are symmetrical about the isolation trench.

[0086] Preferably, the source and drain of two transistors with the same function that share a gate are also isolated by an isolation trench. Among them, the two transistors with the same function that share a gate are respectively located on both sides of the isolation trench. Preferably, the two transistors with the same function that share a gate are roughly symmetrical with each other about the isolation trench. For example, roughly symmetric may include: at least one of the source, channel, and drain of the two transistors with the same function is roughly symmetrical about the isolation trench, and / or the one gate shared by the two transistors with the same function is also roughly symmetrical about the isolation trench. The symmetric arrangement can improve the symmetry of the photosensitive array, improve the area utilization, and reduce the defects caused by the symmetry differences of the device.

[0087] Preferably, the common gate of two transistors with the same function that share a gate extends along the row direction, or along the column direction, or along a direction that forms a certain angle with the row or column direction. For example, it extends in a direction that forms an angle of 45° with the row or column direction. The extension direction of the isolation trench may also extend roughly along the row direction, or along the column direction, or along a direction that forms a certain angle with the row or column direction. For example, it extends in a direction that forms an angle of 45° with the row or column direction. Preferably, the common gate of two transistors with the same function that share a gate is orthogonal to the extension direction of the isolation trench; optionally, the common gate of two transistors with the same function that share a gate forms a certain angle with the extension direction of the isolation trench, for example, an angle of 30°, 45°, 60°, etc., so as to better utilize the spacing area between the pixel units p and improve area utilization.

[0088] Preferably, the pixel subarray includes a source follower transistor SF, and the source follower transistor SF is exclusively used by the corresponding pixel subarray. The source follower transistor SF exclusively used by the corresponding pixel subarray can be a single transistor or multiple transistors. Preferably, each pixel subarray exclusively uses at least two source follower transistors SF, and each two source follower transistors SF are located on both sides of the isolation trench and share a gate, so that the symmetry of the photosensitive array is ensured.

[0089] Preferably, the pixel subarray includes a reset transistor (RST), a gain conversion transistor (DCG / TCG / QCG), a selection transistor (SEL), and there is at least one transistor with the same function sharing a gate to form a transistor group Tr to be shared by adjacent pixel subarrays.

[0090] Preferably, the transistor group Tr formed by transistors with the same function sharing a gate and used for adjacent pixel sub-arrays may include the following sharing methods: The first method: two transistors with the same function sharing a gate are exclusively used by different adjacent pixel sub-arrays. That is, the two transistors in the transistor group Tr only share a gate, but the two transistors are used for different adjacent pixel sub-arrays. The second method: multiple transistors with the same function sharing a gate are shared by different adjacent pixel sub-arrays. That is, the multiple transistors in the transistor group Tr not only share a gate, but the multiple transistors in the transistor group Tr are also used for corresponding pixel sub-arrays at the same time, that is, the adjacent different pixel sub-arrays also share the transistor group Tr.

[0091] Preferably, the adjacent pixel subarrays include adjacent pixel subarrays in the row direction and / or adjacent pixel subarrays in the column direction. The aforementioned adjacent different pixel subarrays sharing transistor groups Tr may occur in adjacent pixel subarrays in the row direction and / or adjacent pixel subarrays in the column direction.

[0092] Preferably, the number of shared pixel units p included in the pixel subarray of the present disclosure can be 4, 8, 9, 16, etc., and the sensors formed by different numbers of shared pixel units p are compatible in terms of design and process except for the metal leads. Referring to the example of Figure 2a, it is only necessary to select and set the functions corresponding to the transistor group Tr to meet the functional transistors required by the pixel subarray formed by 4, 8, 9, 16, etc. shared pixel units p, and different image sensors can be realized. Each pixel subarray includes a number of reset transistors, a number of gain conversion transistors, a number of source follower transistors, and a number of selection transistors. Based on this, these pixel designs will be further described in detail below. Example 1

[0093] As shown in Figure 3a, it is a schematic diagram of the equivalent circuit of multiple pixel subarrays of the sensor of the first embodiment of the present disclosure (only three pixel subarrays are shown due to limited layout). Involving multiple pixel subarrays of the 3T4shared image sensor, Figure 3b is a schematic diagram of the circuit layout of the sensor of the first embodiment of the present disclosure (not all layers are shown). As shown in Figure 3c, it is a simplified schematic diagram of the pixel arrangement of the image sensor of the first embodiment of the present disclosure. In this embodiment, all transistors across the isolation trench are transistors with the same function, and a common gate (e.g., made of polysilicon) is formed directly across the trench. Two parallel transistors function as source-follower transistors (SF) and are placed on either side of the floating diffusion in the column direction. The gate of the source-follower transistors (SF) is connected to the floating diffusion, the drain is connected to a high voltage, and the source serves as the output signal terminal (PXD). A DCG (gain converter) and a reset transistor (RST) are placed at the boundaries of the pixel subarrays. The DCG of this pixel subarray shares a gate with the DCG of the pixel subarray in the adjacent column on one side, as shown in Figure 3b as DCG*2-G. The RST of this pixel subarray shares a gate with the RST of the pixel subarray in the adjacent column on the other side, as shown in Figure 3b as RST*2-G. Since all functional transistors are placed at the boundaries of the pixel subarrays, a mirrored subarray arrangement allows identical functional transistors in different pixel subarrays to be located adjacent to each other. The two parallel functional transistors (including the DCG / RST of the left and right columns) share a gate, which is connected via a row select line, enabling normal subarray timing. This significantly reduces the number of metal contacts and metal leads within the image sensor array.

[0094] For a 3T4shared image sensor, its pixel subarray s-pa includes a reset transistor RST, a gain conversion transistor DCG, a source follower transistor SF, and four shared pixel units p. According to the principles of the present disclosure, the gates of transistors with the same function are integrated across isolation trenches for sharing. To form a 3T4shared image sensor, transistor groups located on both sides of the pixel subarray s-pa in a first direction (row direction) can be selected to form reset transistors and gain conversion transistors, respectively, such as RST*2-G and DCG*2-G as shown in FIG3c . In a second direction (column direction) orthogonal to the first direction, a transistor group Tr located on one side of the pixel subarray can be selected to serve as a source follower transistor, such as SF*2-G as shown in FIG3c . Furthermore, the source follower transistor SF*2-G is exclusive to the corresponding pixel subarray. The reset transistor RST*2-G includes two set transistors RST, and the gain conversion transistor DCG*2-G includes two gain conversion transistors DCG. However, only one of RST*2-G and DCG*2-G is used for the corresponding pixel subarray, and the other is used for the pixel subarray adjacent to the pixel subarray. Specifically, as shown in FIG3c , in the pixel subarray s-pa, one of the two transistors in the gain conversion transistor DCG*2-G is used for the pixel subarray s-pa in the dotted line, and the other is used for the pixel subarray adjacent to the left of the pixel subarray s-pa in the dotted line. The reset transistor RST*2-G includes one of the two transistors in the reset transistor RST*2-G for the pixel subarray s-pa in the dotted line, and the other is used for the pixel subarray adjacent to the right of the pixel subarray s-pa in the dotted line. Optionally, the aforementioned reset transistor RST*2-G and gain conversion transistor DCG*2-G may also be located on both sides of the pixel subarray in the column direction. In this case, the source follower transistor SF*2-G may be located on one side of the pixel subarray in the row direction.

[0095] Preferably, as shown in FIG3c , there are adjacent first and second pixel subarrays 01 and 02 with different transistor functional arrangement positions. The first and second pixel subarrays 01 and 02 constitute a pixel module 1. The image sensor photosensitive array is formed by repeatedly arranging the pixel modules 1 in a first direction X and a second direction Y, with the first and second directions being orthogonal. In the first pixel subarray 01, the reset transistor RST is located on the first side of the first pixel subarray 01 in the first direction X, and the gain conversion transistor DCG is located on the second side of the first direction of the first pixel subarray 01. In the second pixel subarray 02, the reset transistor RST is located on the second side of the first direction of the second pixel subarray 02, and the gain conversion transistor DCG is located on the first side of the first direction of the second pixel subarray 02. The reset transistors and gain conversion transistors are located in the same row. The source follower transistor SF is located on one of the two sides of the pixel subarray in the second direction.

[0096] FIG3 d is a schematic diagram of the circuit layout of the first embodiment of the present disclosure. It can be seen that the metal wires (ML) are arranged in an orderly manner, with short threads and a small number, and there is sufficient space between the metal wires to avoid parasitic capacitance.

[0097] In summary, for the 3T4shared image sensor, the arrangement of the aforementioned RST, DCG, and SF transistors can avoid process bottlenecks such as trenches and small-sized transistors, reduce the number of leads used, and greatly improve the symmetry of pixels. The resulting image sensor is conducive to reducing imaging quality defects caused by pixel asymmetry differences, and can also increase pixel density, reduce image sensor layout area, and reduce costs. Example 2

[0098] As shown in Figure 4a, it is a basic equivalent circuit diagram of 4T8shared (4T: having a source follower transistor (SF), a gain conversion transistor (DCG), an RST (reset transistor), and a selection transistor (SEL); 8shared: 8 pixel units share the 4T). To be compatible with the arrangement of the example in Figure 2a, as shown in Figure 4b, it is a specific equivalent circuit diagram of a pixel subarray according to the second embodiment of the present disclosure. Each pixel subarray s-pa includes a first gain conversion transistor DCG, a second gain conversion transistor TCG, a reset transistor RST, two source follower transistors SF, two selection transistors SEL, and a reserved transistor. The function of the reserved transistor can be selected according to actual needs. Preferably, the gate, source, and drain terminals of the reserved function transistor are all connected to a high level, which is used to control interface leakage while taking into account the compatibility of the array arrangement.

[0099] Figure 4c is a schematic diagram of the equivalent circuit of multiple pixel subarrays of a sensor according to the second embodiment of the present disclosure. To simplify the drawing, portions of the circuit diagram in Figure 4b, such as cell, Res, have been simplified. Figure 4d is a simplified schematic diagram of the pixel arrangement according to the second embodiment of the present disclosure, showing eight shared pixel cells p arranged in four rows and two columns.

[0100] As shown in Figure 4e, which is a schematic diagram of the circuit layout of the second embodiment of the present disclosure, it can be seen that two parallel transistors serve as source follower transistors SF*2-G and are placed on one side of the floating diffusion area in the column direction. Two parallel transistors serve as select transistors SEL*2-G and are placed in adjacent columns of the source follower transistor SF*2-G. The gate of the source follower transistor SF*2-G is connected to the floating diffusion area, the drain is connected to the high voltage, and the source is connected to the drain of the select transistor SEL. The source of the select transistor SEL*2-G serves as the output signal terminal PXD. The first gain converter DCG, the reset transistor RST, and the second gain converter TCG are placed at the boundary of the pixel sub-array S-PA, and the source follower transistor SF*2-G is placed inside the pixel sub-array. Since all DCG / RST / TCG are placed at the boundaries of the pixel subarrays, the DCG / RST / TCG of adjacent pixel subarrays can share a common gate, as shown in Figure 4d (DCG*2-G, TCG*2-G, and RST*2-G). By mirroring the subarray S-PA, transistors with the same function in different pixel subarrays can be placed in adjacent positions. In this case, two parallel functional transistors (including DCG / RST in the left and right columns, and TCG in the upper and lower rows) share a common gate, which is led out through a row select line to achieve normal timing function of the subarray, significantly reducing the number of metal contacts and metal leads within the image sensor.

[0101] As shown in FIG4 d , the reset transistor RST and the first gain conversion transistor DCG are respectively located on both sides of the pixel sub-array s-PA in a first direction and in the same row, and the second gain conversion transistor TCG is located on one side of the pixel sub-array s-PA in a second direction and in a different row or column from the reset transistor RST and the first gain conversion transistor DCG.

[0102] In the first direction, the reset transistors RST located in adjacent pixel sub-arrays share a gate, and the first gain conversion transistors DCG located in adjacent pixel sub-arrays share a gate; in the second direction, the second gain conversion transistors TCG located in adjacent pixel sub-arrays share a gate.

[0103] Two source follower transistors SF share a gate, and two selection transistors SEL share a gate that is exclusively used by the pixel sub-array s-pa. The selection transistor SEL is not in the same row as the source follower transistor SF, the reset transistor RST, the first gain conversion transistor DCG, and the second gain conversion transistor TCG. The source follower transistor SF is located inside the pixel sub-array, and the selection transistor SEL is located on one side of the two sides of the pixel sub-array in the first direction.

[0104] As shown in Figures 4c-4d, each pixel subarray (S-PA) also includes a reserved function transistor (Res). In the second direction, the second gain conversion transistor (TCG) and the reserved function transistor (Res) are located on either side of the pixel subarray. The gate, source, and drain of the reserved function transistor (Res) are all connected to a high level to control interface leakage. Furthermore, the reserved function transistors (Res) included in the upper and lower rows of pixel subarrays (S-PA) share a common gate and are located in the region separating the upper and lower rows of pixel subarrays (S-PA), further improving the quality of the 4T8shared image sensor array.

[0105] Preferably, further referring to FIG4d, there is a first pixel subarray 01, a second pixel subarray 02, a third pixel subarray 03, and a fourth pixel subarray 04 with different transistor function arrangement positions. The first pixel subarray 01, the second pixel subarray 02, the third pixel subarray 03, and the fourth pixel subarray 04 constitute a pixel module 1, and the image sensor photosensitive array is formed by repeatedly arranging the pixel module 1 in the first direction and the second direction.

[0106] In a first direction, the first pixel subarray 01 and the second pixel subarray 02 are adjacent, and the third pixel subarray 03 and the fourth pixel subarray 04 are adjacent. In a second direction, the first pixel subarray 01 and the third pixel subarray 03 are adjacent, and the second pixel subarray 02 and the fourth pixel subarray 04 are adjacent. The first direction is orthogonal to the second direction. The pixel module is symmetrical about a boundary line between any two of the first pixel subarray 01, the second pixel subarray 02, the third pixel subarray 03, and the fourth pixel subarray 04.

[0107] FIG4e is a schematic diagram of the circuit layout of the second embodiment of the present disclosure. It can be seen that the metal leads ML are arranged in an orderly manner, with short threads and a small number, and there is sufficient space between the metal leads to avoid parasitic capacitance.

[0108] In summary, for the 4T8shared image sensor, the arrangement of the aforementioned RST, DCG, TCG, SF, and SEL transistors can avoid process bottlenecks such as trenches and small-size transistors, reduce the number of leads used, and greatly improve the symmetry of pixels. The image sensor formed thereby is conducive to reducing imaging quality defects caused by pixel asymmetry differences, and can also improve pixel density, reduce image sensor layout area, and reduce costs. Example 3

[0109] As shown in Figure 5a, it is a basic equivalent circuit diagram of a 4T9shared (4T: having a source follower transistor (SF), a gain conversion transistor (DCG), an RST (reset transistor), and a selection transistor (SEL); 9shared: 9 pixel units share the 4T). As shown in Figure 5b, it is an equivalent circuit diagram of a pixel subarray s-pa according to the third embodiment of the present disclosure. According to the concept of the present disclosure, each pixel subarray s-pa is designed to include two exclusive source follower transistors SF, two selection transistors SEL, and 9 shared pixel units p. In addition, the pixel subarray s-pa also includes at least one reset transistor RST, one first gain conversion transistor DCG, and several second gain conversion transistors TCG. Multiple pixel subarrays are used to form the photosensitive array of the image sensor. As shown in Figure 5c, it is an equivalent circuit diagram of multiple pixel subarrays of the sensor according to the third embodiment of the present disclosure. The several gain conversion transistors included in each pixel subarray include a first gain conversion transistor DCG and several second gain conversion transistors TCG. The plurality of second gain conversion transistors TCG include first sub-gain conversion transistors whose gate terminals are connected to the TCG control signal and second sub-gain conversion transistors whose gate terminals are grounded. The upper and lower pixel sub-arrays S-PA share three first sub-gain conversion transistors in the second manner described above, and the left and right pixel sub-arrays S-PA share three second sub-gain conversion transistors in the second manner described above.

[0110] As shown in Figures 5d-5e, the reset transistor RST and the first sub-gain conversion transistor DCG are located on either side of the pixel subarray in the second direction, and are located in different rows or columns. The first gain conversion transistor DCG and several second sub-gain conversion transistors TCG are located on either side of the pixel subarray in the first direction, and are located in different rows or columns. Two parallel transistors function as source follower transistors SF, placed on one side of the floating diffusion in the column direction. Two parallel transistors function as select transistors SEL, placed in adjacent columns to the source follower transistor SF. The gate of the source follower transistor SF is connected to the floating diffusion, the drain is connected to a high voltage, and the source is connected to the drain of the select transistor. The source of the select transistor SEL serves as the output signal terminal PXD. The first gain conversion transistor DCG, the reset transistor RST, and the second gain conversion transistor TCG are placed at the boundary of the pixel subarray S-PA. Since the DCG / RST / TCG transistors are all placed at the pixel subarray boundary, a mirrored pixel subarray arrangement allows transistors with the same function to be located adjacently in different subarrays. At this time, the two parallel functional transistors (including DCG in the left and right columns and RST / TCG in the upper and lower rows) share a gate and are led out through a row select line, which can realize the normal timing function of the sub-array and significantly reduce the number of metal contacts and metal leads inside the image sensor.

[0111] As shown in FIG5d , in the first direction, the first gain-converting transistors DCG located in adjacent pixel sub-arrays share a common gate, forming transistor groups such as 01-DCG, 02-DCG, 03-DCG, and 04-DCG shown in FIG5d . Each pair of the shared second sub-gain-converting transistors share a common gate, such as transistor groups 21 to 24 shown in FIG5d . In the second direction, the reset transistors located in adjacent pixel sub-arrays share a common gate, such as 31 to 34 shown in FIG5d . Each pair of the shared first sub-gain-converting transistors share a common gate, such as 31 to 34 shown in FIG5d .

[0112] As shown in FIG5 d , taking the first pixel sub-array O1 as an example, it includes two parallel source follower transistors SF, namely O1-SF, which share a common gate exclusively with the first pixel sub-array, and two parallel select transistors SEL, namely O1-SEL, which share a common gate exclusively with the first pixel sub-array. The source follower transistor SF is in the same row as the first gain conversion transistor DCG, and the select transistor SEL is in the same column as the reset transistor RST.

[0113] Preferably, the photosensitive array of the image sensor includes a first pixel subarray 01, a second pixel subarray 02, a third pixel subarray 03, and a fourth pixel subarray 04 in which transistor functions are arranged in different positions. As shown in FIG5d , the first pixel subarray 01, the second pixel subarray 02, the third pixel subarray 03, and the fourth pixel subarray 04 are used to form a pixel module 1, and the photosensitive array of the image sensor is formed by repeatedly arranging the pixel module 1 in the first direction and the second direction.

[0114] In the first direction, the first pixel subarray 01 and the second pixel subarray 02 are adjacent, and the third pixel subarray 03 and the fourth pixel subarray 04 are adjacent; in the second direction, the first pixel subarray 01 and the third pixel subarray are adjacent, and the second pixel subarray 02 and the fourth pixel subarray 04 are adjacent; the first direction is orthogonal to the second direction; and the pixel module 1 is symmetrical about the boundary adjacent line of any two of the first pixel subarray 01, the second pixel subarray 02, the third pixel subarray 03, and the fourth pixel subarray 04.

[0115] As shown in FIG5 d , the source follower transistors SF and select transistors SEL corresponding to the first pixel subarray 01, the second pixel subarray 02, the third pixel subarray 03, and the fourth pixel subarray 04 are all located within their corresponding pixel subarrays and are exclusively used by the corresponding pixel subarrays. For example, the source follower transistor 01-SF and the select transistor 01-SEL are exclusively used by the first pixel subarray 01; the source follower transistor 02-SF and the select transistor 02-SEL are exclusively used by the second pixel subarray 02; the source follower transistor 03-SF and the select transistor 03-SEL are exclusively used by the third pixel subarray 03; and the source follower transistor 04-SF and the select transistor 04-SEL are exclusively used by the fourth pixel subarray 04.

[0116] Preferably, the 9 shared pixel units p included in the pixel subarray are arranged in an array of 3 rows and 3 columns, and the first pixel subarray 01, the second pixel subarray 02, the third pixel subarray 03, and the fourth pixel subarray 04 constitute a pixel module 1 including an array of 6 rows and 6 columns of pixel units p.

[0117] Preferably, in pixel module 1, second gain conversion transistors TCG are located in any adjacent region of the first, second, third, and fourth pixel subarrays of pixel module 1. That is, in the pixel module, second gain conversion transistors TCG (11-14, 21-24) are arranged in the "cross" region of pixel module 1, as shown in FIG5d. First gain conversion transistors DCG are respectively arranged corresponding to the first, second, third, and fourth pixel subarrays, namely, the 01-DCG group, the 02-DCG group, the 03-DCG group, and the 04-DCG group. The 01-DCG group and the 03-DCG group are located on the left side of pixel module 1, while the 02-DCG group and the 04-DCG group are located on the right side of pixel module 1. In pixel module 1, the first group of first gain conversion transistors 01-DCG and the second group of first gain conversion transistors 02-DCG are located in the area between the first and second rows of pixel units p; the third group of first gain conversion transistors 03-DCG and the fourth group of first gain conversion transistors 04-DCG are located in the area between the fifth and sixth rows of pixel units p; and the first group of first gain conversion transistors 01-DCG, the second group of first gain conversion transistors 02-DCG, the third group of first gain conversion transistors 03-DCG, and the fourth group of first gain conversion transistors 04-DCG each include two transistors sharing a gate, and the first gain conversion transistor of the two first gain conversion transistors that is farther away from pixel module 1 is used for a pixel subarray in an adjacent pixel module and adjacent to the corresponding pixel subarray. Specifically, one of the transistors in the 01-DCG group is used for the first pixel subarray 01, and another transistor is used for the pixel subarray of the first quadrant of the pixel module adjacent to the left side of the pixel module 1; one of the transistors in the 02-DCG group is used for the second pixel subarray 02, and another transistor is used for the pixel subarray of the second quadrant of the pixel module adjacent to the right side of the pixel module 1; one of the transistors in the 03-DCG group is used for the third pixel subarray 03, and another transistor is used for the pixel subarray of the fourth quadrant of the pixel module adjacent to the left side of the pixel module 1; one of the transistors in the 04-DCG group is used for the fourth pixel subarray 04, and another transistor is used for the pixel subarray of the third quadrant of the pixel module adjacent to the right side of the pixel module 1.

[0118] Preferably, in the pixel module 1, as shown in FIG5d, the second gain conversion transistor TCG is arranged on the “cross” region of the pixel module 1, and the second gain conversion transistor TCG includes first sub-gain conversion transistors 11 to 14 and second sub-gain conversion transistors 21 to 24. All the first sub-gain conversion transistors 11 to 14 are arranged along the row direction (first direction) of the “cross” region; and all the second sub-gain conversion transistors are arranged along the column direction (second direction) of the “cross” region.

[0119] Preferably, in the pixel module 1, the first sub-gain conversion transistors involve the first group 11, the second group 12, the third group 13, and the fourth group 14; wherein the first TCG gain conversion transistors of the first to fourth groups are located in adjacent areas of the upper and lower rows of adjacent pixel sub-arrays of the pixel module, and are located in the area between every two columns of pixel units p.

[0120] Preferably, each group of second gain conversion transistors TCG includes two transistors with a shared gate. In each of the first and fourth groups of first sub-gain conversion transistors 11 and 14, one of the two TCG gain conversion transistors is used for the corresponding pixel subarray in pixel module 1, and the other is used for the adjacent pixel subarray of the adjacent pixel module in the first direction of the corresponding pixel subarray. Furthermore, in each of the second and third groups of first sub-gain conversion transistors 12 and 13, the two transistors are shared by adjacent pixel subarrays in the second direction of the corresponding pixel module. Specifically, as shown in FIG5d , the first group 11 includes two transistors, and the second group 12 also includes two transistors. The first pixel subarray 01 and the third pixel subarray 03 share the two transistors in the second group 12 and one transistor in the first group 11 in the second manner. The other transistor in the first group 11 is shared by the pixel subarrays in the first and fourth quadrants of the pixel module adjacent to the left of pixel module 1. Similarly, the third group 13 includes two transistors, and the fourth group 14 also includes two transistors. The second pixel subarray 02 and the fourth pixel subarray 04 share the two transistors in the third group 13 and one transistor in the fourth group 14. The other transistor in the fourth group 14 is shared by the pixel subarrays in the second and third quadrants of the pixel module adjacent to the right side of the pixel module 1. Preferably, the gate terminal of the first sub-gain conversion transistor TCG is connected to the TCG control signal.

[0121] Preferably, the second sub-gain conversion transistors involve a first group 21, a second group 22, a third group 23, and a fourth group 24, wherein the first to fourth groups are located in adjacent areas of the left and right columns of pixel sub-arrays of the pixel module, and are located in the inter-row areas of every two rows of pixel units p.

[0122] Preferably, each group of second sub-gain conversion transistors includes two transistors with a shared gate. One of the two transistors in each of the first and fourth groups is used for the corresponding pixel subarray, and the other is used for the adjacent pixel subarray of the adjacent pixel module in the second direction of the corresponding pixel subarray. The two TCG gain conversion transistors in the second and third groups are shared by their corresponding adjacent pixel subarrays. Similarly, the first group 21 includes two transistors, and the second group 22 also includes two transistors. The first pixel subarray 01 and the second pixel subarray 02 share the two transistors in the second group 22 and one transistor in the first group 21. The other transistor in the first group 21 is shared by the pixel subarrays in the third and fourth quadrants of the pixel module adjacent to the upper side of pixel module 1. Similarly, the third group 23 includes two transistors, and the fourth group 24 also includes two transistors. The third pixel subarray 03 and the fourth pixel subarray 04 share the two transistors in the third group 23 and one transistor in the fourth group 24. The other transistor in the fourth group 24 is shared by the pixel subarrays in the first and second quadrants of the pixel module adjacent to the lower side of pixel module 1. Preferably, the gate of the second sub-gain conversion transistor TCG is grounded.

[0123] Preferably, multiple reset transistors RST are located adjacent to adjacent pixel modules in the column direction (second direction) of pixel module 1 and are shared by adjacent pixel subarrays located in adjacent pixel modules. In pixel module 1, reset transistor RST groups are arranged along the second direction and include a first group 31, a second group 32, a third group 33, and a fourth group 34. The first, second, third, and fourth groups each include two transistors sharing a gate, one of which is used for the corresponding pixel subarray, and the other is used for the adjacent pixel subarray of the corresponding adjacent module of the corresponding pixel subarray. As shown in Figure 5d, one of the two transistors included in reset transistor RST group 31 is used for pixel subarray 01, and the other is used for the pixel subarray in the third quadrant of the adjacent pixel module above it. One of the two transistors included in reset transistor RST group 32 is used for pixel subarray 02, and the other is used for the pixel subarray in the fourth quadrant of the adjacent pixel module above it. One of the two transistors included in reset transistor RST group 33 is used for pixel subarray 03, and the other is used for the pixel subarray in the second quadrant of the adjacent pixel module below it. One of the two transistors included in the reset transistor RST group 34 is used for the pixel sub-array 04 , and the other is used for the pixel sub-array of the first quadrant of the lower adjacent pixel module.

[0124] Preferably, the first and third groups of reset transistors are located in the region between the first and second columns of pixel units p of the pixel module; the second and fourth groups of reset transistors are located in the region between the fifth and sixth columns of pixel units p.

[0125] Preferably, two source follower transistors SF are arranged along the first direction and share a gate, and are located inside the pixel subarray, wherein, in the pixel module 1: the first group of source follower transistors 01-SF of the first pixel subarray 01 is located between the pixel unit p areas of the 1st row and the 2nd row, and in the area between the pixel units p of the 2nd column and the 3rd column; the second group of source follower transistors 02-SF of the second pixel subarray 02 is located in the area between the pixel units p of the 1st row and the 2nd row, and in the area between the pixel units p of the 4th column and the 5th column; the third group of source follower transistors 03-SF of the third pixel subarray 03 is located in the area between the pixel units p of the 5th row and the 6th row, and in the area between the pixel units of the 2nd column and the 3rd column; the fourth group of source follower transistors 04-SF of the fourth pixel subarray 04 is located in the area between the pixel units p of the 5th row and the 6th row, and in the area between the pixel units p of the 4th column and the 5th column.

[0126] Preferably, the two selection transistors SEL are arranged along the second direction and share a gate, and are located inside the pixel subarray, wherein, in the pixel module 1, the first group of selection transistors 01-SEL of the first pixel subarray 01 is located between the pixel cells p in the 1st column and the 2nd column, and in the area between the pixel cells p in the 2nd row and the 3rd row; the second group of selection transistors 02-SEL of the second pixel subarray 02 is located between the pixel cells p in the 5th column and the 6th column, and in the area between the pixel cells p in the 2nd row and the 3rd row; the third group of selection transistors 03-SEL of the third pixel subarray 03 is located between the pixel cells p in the 1st column and the 2nd column, and in the area between the pixel cells p in the 4th row and the 5th row; the fourth group of selection transistors 04-SEL of the fourth pixel subarray 04 is located between the pixel cells p in the 5th column and the 6th column, and arranged along the second direction in the area between the pixel cells p in the 4th row and the 5th row.

[0127] Figure 5e is a schematic diagram of the circuit layout of the third embodiment of the present disclosure. It can be seen that the metal leads ML are arranged in an orderly manner, with most of the metal leads ML having short threads and a small number of long threads. This allows for ample space between the metal leads for layout, avoids parasitic capacitance, and facilitates device size reduction.

[0128] In summary, for the 4T9shared image sensor, the arrangement of the aforementioned RST, DCG, TCG, SF, and SEL transistors can avoid process bottlenecks such as trenches and small-sized transistors, reduce the number of leads used, and greatly improve the symmetry of pixels. The image sensor formed thereby is conducive to reducing imaging quality defects caused by pixel asymmetry differences, and can also improve pixel density, reduce image sensor layout area, and reduce costs. Example 4

[0129] As shown in Figure 6a-1, it is an equivalent circuit diagram of a pixel subarray of the fourth embodiment of the present disclosure. Figure 6a-2 is another equivalent circuit diagram of a pixel subarray of the fourth embodiment of the present disclosure. This embodiment relates to two equivalent circuit diagrams of a pixel subarray of a 4T16shared (4T: having a source follower transistor (SF), a gain conversion transistor (DCG), RST (reset transistor), and a select transistor (SEL); 16shared: 16 pixel units share 4T) image sensor. The pixel subarray in the sensor includes a reset transistor RST, gain conversion transistors DCG / TCG / QCG (i.e., first / second / third), a source follower transistor SF, a select transistor SEL, and 16 shared pixel units p. Multiple pixel subarrays are used to form a photosensitive array of an image sensor.

[0130] FIG6b-1 shows an equivalent circuit diagram of multiple pixel subarrays of a sensor according to the fourth embodiment of the present disclosure. FIG6b-2 shows another equivalent circuit diagram of multiple pixel subarrays of a sensor according to the fourth embodiment of the present disclosure. The difference between the two is that in FIG6b-1, the pixel subarrays in the upper and lower rows share the third gain conversion transistor QCG in the second manner described above; in FIG6b-2, the pixel subarrays in the upper and lower rows share the third gain conversion transistor QCG in the second manner described above, and the pixel subarrays in the left and right columns share the second gain conversion transistor TCG in the second manner described above. In other embodiments, the pixel subarrays in the upper and lower rows may not share the third gain conversion transistor QCG in the second manner described above, but the pixel subarrays in the left and right columns may share the second gain conversion transistor TCG in the second manner described above. However, the embodiments shown in FIG6b-1 and FIG6b-2 described above are preferred.

[0131] As shown in Figures 6c-1 and 6c-2, there are simplified schematic diagrams of the pixel arrangement of the fourth embodiment of the present disclosure, in which the gain conversion tubes DCG / TCG / QCG (i.e., the first / second / third) and the reset transistor RST are placed at the boundary of the pixel subarray. Since the DCG / RST / TCG / QCG transistors are all placed at the boundary of the pixel subarray, the mirrored pixel subarray arrangement can ensure that the same functional transistors in different subarrays are located in adjacent positions. At this time, the two parallel functional transistors (including the DCG / TCG in the left and right columns and the RST / QCG in the upper and lower rows) share a gate and are led out through a row select line, which can realize the normal timing function of the subarray, and can significantly reduce the number of metal contacts and metal leads inside the image sensor.

[0132] Each pixel subarray s-pa (e.g., pixel subarrays 01, 02, 03, 04) includes 16 shared pixel units p arranged in 4 rows and 4 columns. Each pixel subarray s-pa includes 2 reset transistors RST, several gain conversion transistors (DCG / TCG / QCG), at least 2 source follower transistors, and at least 2 select transistors. Preferably, in order to improve the symmetry of the sensor array pixels, each pixel subarray s-pa includes 6 source follower transistors SF and 2 select transistors SEL, as shown in Figure 6c-1; more preferably, each pixel subarray s-pa includes 4 source follower transistors SF and 4 select transistors SEL, as shown in Figure 6c-2, which can further improve the symmetry of the sensor array pixels.

[0133] The several gain conversion transistors of each pixel subarray s-pa may include several first gain conversion transistors DCG, several second gain conversion transistors TCG; and several third gain conversion transistors QCG. Specifically, each pixel subarray s-pa may include 2 first gain conversion transistors DCG, 2 second gain conversion transistors TCG, and 2 third gain conversion transistors QCG.

[0134] As further shown in Figures 6c-1 and 6c-2, the two reset transistors RST are located in the same row and on one side of the second direction of the pixel subarray s-pa, and the two third gain conversion transistors QCG are located in the same row and on the other side of the second direction of the pixel subarray; the two first gain conversion transistors DCG are located in the same row and are respectively located on both sides of the first direction of the pixel subarray s-pa, and the two second gain conversion transistors TCG are located in the same row and are respectively located on both sides of the first direction of the pixel subarray s-pa; wherein the reset transistor RST, the first gain conversion transistor DCG, the second gain conversion transistor TCG, and the third gain conversion transistor QCG are respectively located in different rows.

[0135] In the first direction, the first gain conversion transistors DCG respectively located in adjacent pixel sub-arrays s-pa share a gate, and the second gain conversion transistors TCG respectively located in adjacent pixel sub-arrays s-pa share a gate; in the second direction, the reset transistors RST respectively located in adjacent pixel sub-arrays s-pa share a gate, and the third gain conversion transistors QCG respectively located in adjacent pixel sub-arrays share a gate.

[0136] As shown in FIG6c-1, the pixel sub-array s-pa includes 6 source follower transistors SF and 2 selection transistors SEL that are exclusively used by the pixel sub-array s-pa. Every two source follower transistors SF share a gate to form a group, and the two selection transistors SEL share a gate. The source follower transistor SF is either in the same column as the first gain conversion transistor DCG, or in the same column as the second gain conversion transistor TCG, or in the same column as the reset transistor RST and the third gain conversion transistor QCG. The selection transistor SEL is in the same column as the reset transistor RST and the third gain conversion transistor QCG that are not in the same column as the source follower transistor SF.

[0137] Preferably, as shown in FIG6c-2, the pixel subarray s-pa may include four source follower transistors SF and four select transistors SEL, each of which is exclusively used by the pixel subarray. Every two source follower transistors SF share a gate to form a group, and every two select transistors SEL share a gate. The source follower transistor SF is either in the same column as the first gain conversion transistor DCG or the second gain conversion transistor TCG, and the select transistor SEL is in the same column as the reset transistor RST and the third gain conversion transistor QCG. By providing four source follower transistors SF and four select transistors SEL, the symmetry of the photosensitive array can be further improved.

[0138] As shown in Figures 6c-1 and 6c-2, there are a first pixel sub-array 01, a second pixel sub-array 02, a third pixel sub-array 03, and a fourth pixel sub-array 04 with different transistor function arrangement positions, which are used to constitute a pixel module 1. The image sensor photosensitive array is formed by repeatedly arranging the pixel module 1 in the first direction and the second direction.

[0139] In a first direction, the first pixel subarray 01 and the second pixel subarray 02 are adjacent, and the third pixel subarray 03 and the fourth pixel subarray 04 are adjacent. In a second direction, the first pixel subarray 01 and the third pixel subarray 03 are adjacent, and the second pixel subarray 02 and the fourth pixel subarray 04 are adjacent. The first direction is orthogonal to the second direction. The pixel module 1 is symmetrical about a boundary adjacent line between any two of the first pixel subarray 01, the second pixel subarray 02, the third pixel subarray 03, and the fourth pixel subarray 04.

[0140] The fourth embodiment of the present disclosure also involves layouts of multiple specific embodiments. As an example, FIG6d is a schematic diagram of a circuit layout of the fourth embodiment of the present disclosure. It is a metal line design based on the sharing format shown in FIG6b-1 and the pixel subarray circuit shown in FIG6a-1. It can be seen that the metal leads ML are arranged in an orderly manner, with most ML leads having short threads and a small number of long metal leads ML. This allows for sufficient space between the metal leads, which helps to avoid parasitic capacitance.

[0141] In summary, for the 4T16shared image sensor, the arrangement of the aforementioned RST, DCG, TCG, QCG, SF, and SEL transistors can avoid process bottlenecks such as trenches and small-size transistors, reduce the number of leads used, and greatly improve the symmetry of pixels. The resulting image sensor is conducive to reducing imaging quality defects caused by pixel asymmetry differences, and can also increase pixel density, reduce image sensor layout area, and reduce costs.

[0142] In addition, the present disclosure also provides a method for preparing an image sensor, which is used to prepare the image sensor involved in any of the aforementioned embodiments, wherein the method includes arranging at least one transistor with the same function in adjacent pixel sub-arrays on both sides of a trench, and manufacturing a common gate of the transistor with the same function to optimize the process and wiring of the image sensor.

[0143] In the embodiment of the present disclosure, by changing the idea of ​​transistor arrangement in the layout, at least one transistor with the same function is set to share a gate, or even only transistors with a common gate exist in the pixel sub-array, thereby greatly reducing the number of row selection lines with the help of gate connection, simplifying the layout; avoiding the requirements for the shape and size of the isolation groove opening, greatly reducing the process difficulty of the isolation groove process; and the difference in the implementation of pixel layouts with different shared numbers is only the difference in the layout of the metal lead layer, and the rest can be compatible, which significantly reduces the cost. At the same time, the pixel layout of the present disclosure is also conducive to improving pixel symmetry, eliminating difference defects, and helping to reduce pixel density and reduce the area of ​​the image sensor, which can greatly improve the quality of the image sensor and reduce production costs. The solution of the present disclosure is of great significance for the production of small-pixel large-array image sensors.

[0144] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still fall within the spirit and scope of the exemplary embodiments of the present invention. It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as an example and not a limitation, the alternative configurations of the embodiments of the present invention may be considered to be consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. An image sensor, comprising an image sensor photosensitive array composed of a plurality of pixel subarrays, wherein the pixel subarrays include a plurality of pixel units and transistors with different functions, wherein the pixel unit includes a photodiode, characterized in that: At least one transistor with the same function in adjacent pixel sub-arrays shares a gate, so as to optimize the process and wiring of the image sensor; The transistor includes one or more of a source follower transistor, a reset transistor, a gain conversion transistor, and a selection transistor.

2. An image sensor according to claim 1, characterized in that: The transistors with the same function that share a gate include at least two transistors, and the at least two transistors with the same function are channel-isolated by an isolation trench.

3. An image sensor according to claim 1 or 2, characterized in that: The channels of the two transistors with the same function sharing a gate are parallel to each other.

4. An image sensor according to claim 1 or 2, characterized in that: The source and drain of the two transistors with the same function sharing a gate are isolated through an isolation trench.

5. The image sensor according to claim 1, characterized in that: The common gate extends along the row direction, or along the column direction, or along a direction forming an angle of 45° with the row direction or the column direction.

6. An image sensor according to claim 1 or 2, characterized in that: The source follower transistor is exclusively used by the pixel sub-array corresponding to the source follower transistor.

7. An image sensor according to claim 1 or 2, characterized in that: At least one of the reset transistor, the gain conversion transistor, and the selection transistor has the same function as the transistor and shares a gate for use in adjacent pixel sub-arrays.

8. The image sensor according to claim 7, characterized in that: The method in which transistors with the same function share a gate for adjacent pixel sub-arrays includes: Two transistors with the same function sharing a gate are exclusively used by different adjacent pixel sub-arrays; Alternatively, two transistors with the same function sharing a gate are shared by adjacent different pixel sub-arrays.

9. The image sensor according to claim 8, characterized in that: The adjacent includes adjacent in a row direction and / or adjacent in a column direction.

10. An image sensor according to any one of claims 1 to 9, characterized in that: Each of the pixel sub-arrays includes one reset transistor, one gain conversion transistor, one or two source follower transistors, and four shared pixel units.

11. An image sensor according to claim 10, characterized in that: In the first direction, the reset transistors respectively located in adjacent pixel sub-arrays share a gate, and the gain conversion transistors respectively located in adjacent pixel sub-arrays share a gate.

12. An image sensor according to any one of claims 10 to 11, characterized in that: There are adjacent first pixel subarray and second pixel subarray with different transistor function arrangement positions, the first pixel subarray and the second pixel subarray constitute a pixel module, and the image sensor photosensitive array is formed by repeatedly arranging the pixel module in a first direction and a second direction, and the first direction and the second direction are orthogonal.

13. An image sensor according to claim 12, characterized in that: In the first pixel subarray, the reset transistor is located on a first side of a first direction of the first pixel subarray, and the gain conversion transistor is located on a second side of the first direction of the first pixel subarray; in the second pixel subarray, the reset transistor is located on the second side of the first direction of the second pixel subarray, and the gain conversion transistor is located on the first side of the first direction of the second pixel subarray; and the reset transistor and the gain conversion transistor are located in the same row.

14. An image sensor according to claim 13, characterized in that: The source follower transistor is located on one of two sides of the pixel sub-array in the second direction.

15. An image sensor according to any one of claims 1 to 9, characterized in that: Each of the pixel sub-arrays includes a number of reset transistors, a number of gain conversion transistors, a number of source follower transistors, a number of selection transistors, and 8, 9, or 16 shared pixel units.

16. An image sensor according to claim 15, characterized in that: The plurality of gain conversion transistors of each of the pixel sub-arrays include a plurality of first gain conversion transistors and a plurality of second gain conversion transistors; When the pixel subarray includes 8 shared pixel units, each of the pixel subarrays includes a reset transistor, a first gain conversion transistor, a reset transistor, and a second gain conversion transistor; When the pixel subarray includes 9 shared pixel units, each of the pixel subarrays includes a reset transistor, a first gain conversion transistor, and the plurality of second gain conversion transistors include a plurality of first sub-gain conversion transistors and a plurality of second sub-gain conversion transistors; When the pixel subarray includes 16 shared pixel units, the plurality of gain conversion transistors further include two third gain conversion transistors, and each of the pixel subarrays includes two reset transistors, two first gain conversion transistors, two second gain conversion transistors, and two third gain conversion transistors.

17. An image sensor according to claim 16, characterized in that: When the pixel sub-array includes 9 shared pixel units, the pixel sub-arrays adjacent to each other in the first direction share the plurality of second sub-gain conversion transistors, and the pixel sub-arrays adjacent to each other in the second direction share the plurality of first sub-gain conversion transistors; When the pixel sub-array includes 16 shared pixel units, the third gain conversion transistors of adjacent pixel sub-arrays are shared in the second direction, and / or the second gain conversion transistors of adjacent pixel sub-arrays are shared in the first direction.

18. An image sensor according to claim 16 or 17, characterized in that: When the pixel subarray includes 8 shared pixel units, the reset transistor and the first gain conversion transistor are respectively located on both sides of the pixel subarray in a first direction and in the same row, and the second gain conversion transistor is located on one side of the pixel subarray in a second direction and in a different row or column from the reset transistor and the first gain conversion transistor; When the pixel subarray includes 9 shared pixel units, the reset transistor and the first sub-gain conversion transistor are respectively located on both sides of the second direction of the pixel subarray and are located in different rows or columns, and the first gain conversion transistor and a plurality of second sub-gain conversion transistors are respectively located on both sides of the first direction of the pixel subarray and are located in different rows or columns; When the pixel subarray includes 16 shared pixel units, the two reset transistors are located in the same row and on one side of the second direction of the pixel subarray, the two first gain conversion transistors are located in the same row and are respectively located on both sides of the first direction of the pixel subarray, the two second gain conversion transistors are located in the same row and are respectively located on both sides of the first direction of the pixel subarray, and the two third gain conversion transistors are located in the same row and are located on the other side of the second direction of the pixel subarray; wherein the reset transistor, the first gain conversion transistor, the second gain conversion transistor, and the third gain conversion transistor are respectively located in different rows.

19. An image sensor according to claim 18, characterized in that: When the pixel subarray includes 8 shared pixel units, in a first direction, the reset transistors respectively located in adjacent pixel subarrays share a gate, and the first gain conversion transistors respectively located in adjacent pixel subarrays share a gate; in a second direction, the second gain conversion transistors respectively located in adjacent pixel subarrays share a gate; When the pixel subarray includes 9 shared pixel units, in the first direction, the first gain conversion transistors respectively located in adjacent pixel subarrays share a gate, and the shared plurality of second sub-gain conversion transistors share a gate every two; in the second direction, the reset transistors respectively located in adjacent pixel subarrays share a gate, and the shared plurality of first sub-gain conversion transistors share a gate every two; When the pixel subarray includes 16 shared pixel units, in the first direction, the first gain conversion transistors respectively located in adjacent pixel subarrays share a gate, and the second gain conversion transistors respectively located in adjacent pixel subarrays share a gate; in the second direction, the reset transistors respectively located in adjacent pixel subarrays share a gate, and the third gain conversion transistors respectively located in adjacent pixel subarrays share a gate.

20. An image sensor according to any one of claims 15 to 19, characterized in that: When the pixel subarray includes 8 shared pixel units, the pixel subarray includes two source follower transistors and two selection transistors exclusively used by the pixel subarray, the two source follower transistors share a gate, and the two selection transistors share a gate, and the selection transistor is in a different row from the source follower transistor, the reset transistor, the first gain conversion transistor, and the second gain conversion transistor; When the pixel subarray includes 9 shared pixel units, the pixel subarray includes two source follower transistors and two selection transistors exclusively used by the pixel subarray, the two source follower transistors share a gate, and the two selection transistors share a gate, the source follower transistor is in the same row as the first gain conversion transistor, and the selection transistor is in the same column as the reset transistor; When the pixel subarray includes 16 shared pixel units, the pixel subarray includes six source follower transistors and two selection transistors that are exclusively used by the pixel subarray, and every two of the source follower transistors share a gate to form a group, and the two selection transistors share a gate, and the source follower transistor is either in the same row as the first gain conversion transistor, or in the same row as the second gain conversion transistor, or in the same column as the reset transistor and the third gain conversion transistor, and the selection transistor is in the same column as the reset transistor and the third gain conversion transistor that are not in the same column as the source follower transistor; or, the pixel subarray includes four source follower transistors and four selection transistors that are exclusively used by the pixel subarray, and every two of the source follower transistors share a gate to form a group, and every two of the selection transistors share a gate, and the source follower transistor is either in the same row as the first gain conversion transistor, or in the same row as the second gain conversion transistor, and the selection transistor is in the same column as the reset transistor and the third gain conversion transistor.

21. An image sensor according to any one of claims 15 to 20, characterized in that: When the pixel subarray includes 8 shared pixel units, the source follower transistor is located inside the pixel subarray, and the selection transistor is located on one side of the pixel subarray in the first direction; when the pixel subarray includes 9 or 16 shared pixel units, the source follower transistor and the selection transistor are both located inside the pixel subarray.

22. The image sensor according to claim 16, characterized in that: The gate terminal of the first sub-gain conversion transistor is connected to a control signal; the gate terminal of the second sub-gain conversion transistor is grounded.

23. The image sensor according to claim 16, characterized in that: When the pixel subarray includes 8 shared pixel units, each of the pixel subarrays further includes a reserved function transistor, and in the second direction, the second gain conversion transistor and the reserved function transistor are respectively located on both sides of the pixel subarray, wherein the gate, source, and drain terminals of the reserved function transistor are all connected to a high level for controlling interface leakage.

24. An image sensor according to any one of claims 15 to 23, characterized in that: There are a first pixel subarray, a second pixel subarray, a third pixel subarray, and a fourth pixel subarray with different transistor function arrangement positions, the first pixel subarray, the second pixel subarray, the third pixel subarray, and the fourth pixel subarray constitute a pixel module, and the image sensor photosensitive array is formed by repeatedly arranging the pixel module in a first direction and a second direction.

25. An image sensor according to claim 24, characterized in that: In a first direction, the first pixel subarray and the second pixel subarray are adjacent, and the third pixel subarray and the fourth pixel subarray are adjacent; in a second direction, the first pixel subarray and the third pixel subarray are adjacent, and the second pixel subarray and the fourth pixel subarray are adjacent; the first direction is orthogonal to the second direction; the pixel module is symmetrical about a boundary adjacent line of any two of the first pixel subarray, the second pixel subarray, the third pixel subarray, and the fourth pixel subarray.

26. An image sensor according to claim 24, characterized in that: When 8 shared pixel units are shared, the 8 shared pixel units are arranged into 4 rows and 2 columns; when 9 shared pixel units are shared, the 9 shared pixel units are arranged into 3 rows and 3 columns; when 16 shared pixel units are shared, the 16 shared pixel units are arranged into 4 rows and 4 columns.

27. A method for preparing an image sensor, used for preparing the image sensor according to any one of claims 1 to 26, characterized in that: At least one transistor with the same function in adjacent pixel sub-arrays is arranged on both sides of the trench, and a common gate of the transistor with the same function is manufactured to optimize the process and wiring of the image sensor.

Images