Display panel and display apparatus

Abstract

A display panel (PNL) and a display apparatus, which belong to the technical field of display. The display panel (PNL) comprises a base substrate (SBT), a driving layer (DRL) and a pixel layer (PIXL), which are sequentially stacked, wherein the driving layer (DRL) comprises pixel driving circuits (PDCs) which are arranged in an array and configured to drive the pixel layer (PIXL); each pixel driving circuit (PDC) comprises a first transistor (T1), a second transistor (T2), a third transistor (T3) and a storage capacitor (CST); the display panel (PNL) comprises scanning signal lines (GL) and sensing signal lines (SL); a gate electrode of the third transistor (T3) is electrically connected to the scanning signal line (GL), and a first electrode (T3S) of the third transistor (T3) is electrically connected to the sensing signal line (SL); a second electrode (T3D) of the third transistor (T3) is electrically connected to a pixel electrode (PE); the first electrode (T3S) of the third transistor (T3) in the at least one pixel driving circuit (PDC) is multiplexed as the first electrode (T3S) of the third transistor (T3) of an adjacent pixel driving circuit (PDC) in a row direction. A source electrode and a drain electrode are shared between adjacent thin-film transistors (TFTs) in the display panel (PNL), and the thin film-transistors (TFTs) are arranged in a two-in-one and one-in-one mode, thereby improving the aperture ratio.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311786876.9, filed on December 22, 2023, and entitled “Display Panel and Display Device.” The entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] With the continuous development of display technology, the application range of display panels is becoming increasingly wider, and people's requirements for display panels are also becoming higher and higher. Display panels with a high pixel count per inch have high image density and better image quality. However, with a display panel with a higher pixel count per inch, the pixel size is smaller and the layout space is smaller. Within the limited space, it is necessary to rationally arrange the components and signal lines, while also considering the pixel aperture ratio design. Therefore, for bottom-emitting OLED devices with a high pixel count per inch, it is even more necessary to rationally arrange the layout to maximize space utilization, increase the aperture ratio, and increase the life of the OLED device. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device with reasonable layout and pattern to improve the aperture ratio.

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a base substrate, a driving layer, and a pixel layer stacked in sequence, wherein the driving layer comprises a first metal layer, a semiconductor layer, a gate insulating layer, a second metal layer, and a planarization layer stacked in sequence on the base substrate;

[0007] The driving layer includes a pixel driving circuit arranged in an array for driving the pixel layer; wherein the pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, wherein the transistor includes a gate, a first electrode and a second electrode;

[0008] The display panel includes a scanning signal line and a sensing signal line; the gate of the third transistor is electrically connected to the scanning signal line, the first electrode of the third transistor is electrically connected to the sensing signal line; and the second electrode of the third transistor is electrically connected to the pixel electrode;

[0009] The first electrode of the third transistor in at least one of the pixel driving circuits is multiplexed as the first electrode of the third transistor of the adjacent pixel driving circuit in the row direction.

[0010] According to one embodiment of the present disclosure, the third transistor includes a third transistor channel region located in the semiconductor layer, and a length direction of the third transistor channel region is a row direction; the third transistor channel region, the first electrode and the second electrode of the third transistor are all located on the same side of the scan signal line;

[0011] The scanning signal line extends along the row direction and has a scanning signal line branch portion protruding along the column direction; the scanning signal line branch portion includes the gate of the third transistor, and the third transistor channel region is arranged to overlap with the gate of the third transistor.

[0012] According to an embodiment of the present disclosure, the display panel is provided with a switching structure, and the switching structure is electrically connected to the first electrode of the third transistor and is electrically connected to the sensing signal line.

[0013] According to an embodiment of the present disclosure, the second metal layer is provided with a metal structure, and the metal structure is electrically connected to the second electrode of the third transistor through a second via hole; the length direction of the second via hole is the column direction.

[0014] According to one embodiment of the present disclosure, the display panel includes a pixel driving circuit group arranged in an array, each pixel driving circuit group includes four pixel driving circuits arranged in a row, and the four pixel driving circuits are connected to the same sensing signal line; wherein two pixel driving circuits are located on one side of the sensing signal line, and the other two pixel driving circuits are located on the other side of the sensing signal line;

[0015] The semiconductor layer is provided with multiplexing structures on both sides of the sensing signal line. The multiplexing structures serve as first electrodes of two adjacent third transistors and are connected to channel regions of the two adjacent third transistors.

[0016] According to one embodiment of the present disclosure, the display panel is further provided with a switching structure corresponding to the pixel driving circuit group, the two multiplexing structures of the pixel driving circuit group are electrically connected to the switching structure respectively, and the switching structure is electrically connected to the sensing signal line.

[0017] According to an embodiment of the present disclosure, the display panel is further provided with data signal lines respectively driving the four pixel driving circuits of the pixel driving circuit group;

[0018] Wherein, two data signal lines are respectively arranged on both sides of the sensing signal line; and the two data signal lines located on the same side of the sensing signal line overlap with the multiplexing structure.

[0019] According to one embodiment of the present disclosure, the display panel is provided with a transfer structure, which includes a first transfer line, which is arranged on the same layer as the scanning signal line; the first transfer line is electrically connected to the multiplexing structure through a first via, and the first via is located between adjacent data signal lines.

[0020] According to an embodiment of the present disclosure, the first patch line includes a first patch line first section extending in a row direction, and two first patch line second sections respectively connected to both ends of the first patch line first section, and the first patch line second section extends in a column direction;

[0021] The first section of the first patch cord is electrically connected to the sensing signal line; the second section of the first patch cord is electrically connected to the multiplexing structure;

[0022] The second section of the first adapter wire is located between two adjacent data signal lines.

[0023] According to one embodiment of the present disclosure, the display panel is provided with a transfer structure; the transfer structure includes a second transfer line, which is arranged in the same layer as the third transistor channel region and is conductorized; the second transfer line is connected to the multiplexing structure and is electrically connected to the sensing signal line.

[0024] According to an embodiment of the present disclosure, the transfer structure further includes a third transfer line, and the third transfer line is provided on the same layer as the scan signal line;

[0025] The third transfer line is electrically connected to the second transfer line through a fourth via hole, and is electrically connected to the sensing signal line through a seventh via hole.

[0026] According to one embodiment of the present disclosure, the first electrode of the first transistor is electrically connected to a driving power supply voltage line for loading a driving power supply voltage, the first electrode of the second transistor is electrically connected to a data signal line for loading a data voltage, and the first electrode of the third transistor is electrically connected to the sensing signal line for loading a reference power supply voltage; the second electrode of the second transistor, the first electrode plate of the storage capacitor, and the gate of the first transistor are electrically connected to the first node, respectively, and the second electrode of the third transistor, the second electrode of the first transistor, the pixel electrode, and the second electrode plate of the storage capacitor are electrically connected to the second node, respectively.

[0027] According to an embodiment of the present disclosure, a pixel electrode via hole is provided on the planarization layer, and the pixel electrode is electrically connected to the first metal structure located on the second metal layer through the pixel electrode via hole;

[0028] The first metal structure is electrically connected to the second electrode of the third transistor through a second via;

[0029] The orthographic projection of the pixel electrode via hole on the base substrate partially overlaps with the orthographic projection of the second via hole on the base substrate.

[0030] According to an embodiment of the present disclosure, a pixel electrode via hole is provided on the planarization layer, and the pixel electrode is electrically connected to the first metal structure located on the second metal layer through the pixel electrode via hole;

[0031] The pixel electrode via hole, the first electrode of the third transistor, and the second electrode of the third transistor are located on the same side of the scanning signal line.

[0032] According to a second aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0033] Adjacent thin film transistors in the display panel disclosed herein share a source and drain electrode, and the thin film transistors are arranged in a two-in-one and then-one manner to improve the aperture ratio.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0036] FIG1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0037] FIG2 is a schematic diagram of a film layer structure of a display panel in one embodiment of the present disclosure.

[0038] FIG3 is an equivalent circuit diagram of a 3T1C pixel driving circuit in one embodiment of the present disclosure.

[0039] FIG4 is a schematic diagram of a four-in-one thin film transistor layout design of a display panel in one embodiment of the present disclosure.

[0040] FIG5 is a schematic diagram of a layout design in which adjacent thin film transistors of a display panel share source and drain electrodes in one embodiment of the present disclosure.

[0041] FIG6 is a partial enlarged schematic diagram of FIG5 .

[0042] FIG7 is a schematic structural diagram of a third transistor in one embodiment of the present disclosure.

[0043] FIG8 is a schematic diagram of a layout design in which a thin film transistor is connected using a conductive second adapter wire in one embodiment of the present disclosure.

[0044] FIG9 is a partially enlarged schematic diagram of FIG8 .

[0045] FIG. 10 is a schematic diagram illustrating the positional relationship between the second metal layer and the pixel electrode via hole in FIG. 5 .

[0046] FIG11 is a schematic diagram of a partial cross-sectional structure of the pixel electrode via hole in FIG5 .

[0047] FIG. 12 is a structural schematic diagram showing the positional relationship between the second metal layer and the pixel electrode via hole in FIG. 8 .

[0048] FIG13 is a schematic diagram of a partial cross-sectional structure of the pixel electrode via hole in FIG8 .

[0049] FIG14 is a schematic diagram of a film layer layout design of a display panel in one embodiment of the present disclosure.

[0050] FIG15 is a schematic diagram of a film layer layout design of a display panel in the first embodiment of the present disclosure.

[0051] FIG16 is a schematic diagram of the connection structure of the pixel driving circuit in the first embodiment of the present disclosure.

[0052] FIG17 is a schematic diagram showing a first embodiment of the present disclosure in which a pixel opening and a third transistor are located on both sides of a scanning signal line.

[0053] FIG18 is a schematic diagram showing the connection between the first metal structure and the second electrode of the third transistor in the first embodiment of the present disclosure.

[0054] FIG19 is a schematic diagram showing the positional relationship between the scan signal line and the third transistor in the first embodiment of the present disclosure.

[0055] FIG20 is a schematic diagram showing the positional relationship between the scanning signal line and the second transistor in the first embodiment of the present disclosure.

[0056] FIG21 is a schematic diagram showing the connection between the second metal structure and the first electrode of the second transistor in the first embodiment of the present disclosure.

[0057] FIG22 is a schematic diagram showing the positional relationship between the first electrode of the second transistor and the pixel opening in the first embodiment of the present disclosure.

[0058] FIG23 is a schematic diagram showing the positional relationship between the second scan signal line branch portion and the second metal structure in the first embodiment of the present disclosure.

[0059] FIG24 is a schematic diagram of a film layer layout design of a display panel in a second embodiment of the present disclosure.

[0060] FIG25 is a schematic diagram of the connection structure of the pixel driving circuit in the second embodiment of the present disclosure.

[0061] FIG. 26 is a schematic diagram showing the positional relationship between the first scan signal line branch portion and the second scan signal line branch portion in the second embodiment of the present disclosure.

[0062] FIG27 is a schematic diagram showing the positional relationship between the first electrode of the second transistor and the pixel opening in the second embodiment of the present disclosure.

[0063] FIG28 is a schematic diagram showing the positional relationship between the second scan signal line branch portion and the second metal structure in the second embodiment of the present disclosure.

[0064] FIG29 is a schematic diagram of a transparent conductive layer in the second embodiment of the present disclosure.

[0065] FIG30 is a schematic diagram of the first metal layer in the second embodiment of the present disclosure.

[0066] FIG31 is a schematic diagram of a semiconductor layer in the second embodiment of the present disclosure.

[0067] FIG32 is a schematic diagram of the second metal layer in the second embodiment of the present disclosure.

[0068] FIG33 is a schematic diagram of the positional relationship between some vias and the second metal layer in the second embodiment of the present disclosure.

[0069] FIG34 is a schematic diagram of the positional relationship between the pixel electrode via hole and the second metal layer in the second embodiment of the present disclosure.

[0070] FIG35 is a schematic diagram of a pixel electrode in a pixel electrode layer in the second embodiment of the present disclosure.

[0071] FIG36 is a schematic diagram of a pixel opening on a pixel electrode in the second embodiment of the present disclosure.

[0072] FIG37 is a schematic diagram of the film layer layout design of the display panel in the third embodiment of the present disclosure.

[0073] FIG38 is a connection diagram of a pixel driving circuit in the third embodiment of the present disclosure.

[0074] FIG39 is a schematic diagram showing the positional relationship between the branch portion of the second scanning signal line and the channel region of the second transistor in the third embodiment of the present disclosure.

[0075] FIG40 is a schematic diagram showing the positional relationship between the second transistor channel region and the third transistor channel region in the third embodiment of the present disclosure.

[0076] FIG41 is a schematic diagram showing the connection between the third metal structure and the second electrode of the first transistor in the third embodiment of the present disclosure.

[0077] FIG42 is a schematic diagram showing the connection between the first electrode of the third transistor and the sensing signal line in the third embodiment of the present disclosure.

[0078] Explanation of the accompanying symbols: AA, display area; BB, peripheral area; BUF, inorganic buffer layer; COML, common electrode layer; CR, channel region; CS, conductive structure; CST, storage capacitor; CST1, first electrode plate of storage capacitor; CST2, second electrode plate of storage capacitor; DH, row direction; DL, data signal line; DRL, drive layer; DV, column direction; EFL, light-emitting functional layer; GL, scan signal line; GLA, scan signal line branch; GLA1, first scan signal line branch; GLA2, second scan signal line branch; GI, gate Gate insulating layer; GS, scan signal; GT, second metal layer; GX1, first metal structure; GX1H, pixel electrode via; GX2, second metal structure; GX3, third metal structure; GX4, fourth metal structure; HA, first via; HB, second via; HC, third via; HD, fourth via; HE, fifth via; HF, sixth via; HG, seventh via; HL, horizontal transfer line; ITO1, transparent conductive layer; NG, first node; NS, second node; PDC, pixel driving circuit; PDCS , pixel driving circuit group; PDL, pixel definition layer; PEL, pixel electrode layer; PE, pixel electrode; PIXL, pixel layer; PIX, sub-pixel; PLN, planarization layer; PNL, display panel; PO, pixel opening; PVX, passivation layer; SBT, substrate; SCL, semiconductor layer; SHL, first metal layer; SL, sensing signal line; SX, light shielding portion; T1, first transistor; T1G, first transistor gate; T2, second transistor; T2A, second transistor channel region; T2S, second transistor second region A pole; T3, a third transistor; T3A, a channel region of a third transistor; T3L, a transfer structure; T3LA, a first transfer line; T3LA1, a first section of a first transfer line; T3LA2, a second section of a first transfer line; T3LB, a second transfer line; T3LC, a third transfer line; T3S, a first pole of a third transistor; T3D, a second pole of a third transistor; TFT, a thin film transistor; TX, a multiplexing structure; VDD, a driving power supply voltage; VDDL, a driving power supply voltage signal line; VSS, a reference power supply voltage; UU, a display unit. DETAILED DESCRIPTION

[0079] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0080] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0081] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0082] In an embodiment of the present disclosure, a thin film transistor has an active layer. The active layer is located in the semiconductor layer and includes a channel region and a source and a drain located on both sides of the channel region. The channel region maintains semiconductor properties, and the source and the drain are partially or fully conductive. In an embodiment of the present disclosure, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In an embodiment of the present disclosure, for any transistor, one of the "first electrode" and the "second electrode" is referred to as the source of the transistor, and the other is referred to as the drain of the transistor.

[0083] In the disclosed embodiments, the channel region of the transistor has a length direction and a width direction. The length direction of the channel region of the transistor refers to the direction in which current primarily flows, and the width direction of the channel region of the transistor is perpendicular to the direction in which current flows. Along the length direction of the channel region of the transistor, the active layer of the transistor sequentially includes the first electrode of the transistor, the channel region, and the second electrode.

[0084] An embodiment of the present disclosure provides a display panel PNL. Referring to FIG. 1 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. Within the display area AA, the display panel PNL is provided with an array of display units UU. The display units UU include sub-pixels PIX and pixel driver circuits PDC that drive the sub-pixels PIX. The display panel PNL does not include display units UU in the peripheral area BB, or the display units UU that are provided are not used for displaying images. Referring to FIG. 1 , the display panel PNL is provided with a plurality of scan signal lines GL extending along a row direction DH in the display area AA. Each scan signal line GL is provided in a one-to-one correspondence with each display unit row. The pixel driver circuit PDC of each display unit UU in a display unit row is electrically connected to the corresponding scan signal line GL. The display panel PNL is also provided with a plurality of data signal lines DL extending along a column direction DV in the display area AA. Each data signal line DL is provided in a one-to-one correspondence with each display unit column. The pixel driver circuit PDC of each display unit UU in a display unit column is electrically connected to the corresponding data signal line DL. In this way, the pixel driving circuit PDC of each display unit UU is connected to a scanning signal line GL and a data signal line DL. When a scanning signal is applied to the scanning signal line GL, the driving voltage applied to the data signal line DL can be written into the pixel driving circuit PDC, thereby allowing the pixel driving circuit PDC to control the brightness of the sub-pixel PIX according to the written driving voltage.

[0085] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor and a storage capacitor CST, and the gate of the driving transistor can be electrically connected to an electrode plate of the storage capacitor CST. The source of the data writing transistor can be electrically connected to the data signal line DL, and the gate of the data writing transistor can be electrically connected to the scanning signal line GL. The pixel driving circuit PDC is configured so that when the scanning signal GS is loaded on the scanning signal line GL, the data writing transistor is turned on, thereby causing the driving voltage on the data signal line DL to be written into the gate of the driving transistor and the storage capacitor CST. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor CST. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It can be understood that the pixel driving circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors so that the pixel driving circuit PDC has better driving performance. For example, the pixel driving circuit PDC may be a 7T1C (seven thin film transistors TFT and one storage capacitor CST), an 8T1C (eight thin film transistors TFT and one storage capacitor CST) or a pixel driving circuit PDC of other architectures.

[0086] In an embodiment of the present disclosure, the sub-pixels PIX in the display panel PNL are current-driven self-luminous elements, such as thin-film self-luminous light-emitting elements. For example, the sub-pixels PIX are OLED, PLED, QLED, etc. Further, the sub-pixels PIX located in the display area AA include sub-pixels PIX of multiple different colors. For example, the sub-pixels PIX include red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It is understandable that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA may also be sub-pixels PIX of only one color, or may also have sub-pixels PIX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0087] In one embodiment of the present disclosure, referring to FIG2 , a display panel PNL may include a base substrate SBT, a drive layer DRL, and a pixel layer PIXL, which are stacked in sequence. The pixel layer PIXL includes subpixels PIX, and the drive layer DRL includes a pixel drive circuit PDC for driving the subpixels PIX. Each subpixel PIX can emit light to display an image under the drive of the pixel drive circuit PDC.

[0088] Optionally, the base substrate SBT can be a base substrate of an inorganic material, or a base substrate of an organic material; of course, it can also be a composite substrate formed by stacking a base substrate of an inorganic material and a base substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the base substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the base substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the base substrate SBT can also be a flexible base substrate, for example, the material of the base substrate SBT can include polyimide.

[0089] Optionally, referring to FIG2 , in the driving layer DRL, at least one pixel driving circuit PDC may include a thin film transistor TFT and a storage capacitor CST. Furthermore, the thin film transistor TFT may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the active layer of the thin film transistor TFT may be made of an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; and the thin film transistor TFT may be an N-type thin film transistor or a P-type thin film transistor.

[0090] In one example, the transistors in the driving layer DRL are top-gate thin film transistors.

[0091] In one example, the transistors in the driving layer DRL are metal oxide thin film transistors.

[0092] As an example, referring to FIG2 , the drive layer DRL may include a first metal layer SHL, an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a second metal layer GT, and a planarization layer PLN, which are stacked in sequence. In this manner, the thin-film transistor TFT formed is a top-gate thin-film transistor. In this example, the source and drain metal layers may not be provided, thereby reducing the thickness of the display panel PNL. This also reduces the patterning process, thereby reducing the cost of the display panel.

[0093] In this embodiment, at least a portion of the first metal layer SHL can function as a light-shielding structure, shielding the channel region CR of the transistor to prevent light from the substrate from reaching the channel region CR and altering transistor characteristics. For example, the orthographic projection of the transistor channel region CR on the substrate SBT is within the orthographic projection of the first metal layer SHL on the substrate SBT.

[0094] Furthermore, referring to FIG. 2 , the first metal layer SHL is connected to the second metal layer GT through vias.

[0095] Furthermore, referring to FIG. 2 , the driving layer DRL further includes a passivation layer PVX located on a side of the second metal layer GT away from the substrate SBT, and a planarization layer PLN is located on a side of the passivation layer PVX away from the substrate SBT.

[0096] In one embodiment of the present disclosure, referring to FIG2 , the driving layer DRL is further provided with a transparent conductive layer ITO1, and the transparent conductive layer ITO1 is used to form an electrode plate of the storage capacitor CST, and the semiconductor layer SCL is used to form another electrode plate of the storage capacitor CST. In this way, the storage capacitor CST is a transparent storage capacitor. Furthermore, the light emitted by the sub-pixel PIX can be emitted through the transparent storage capacitor, so that the display panel PNL is a bottom-emitting display panel PNL. Furthermore, the transparent conductive layer ITO1 is located between the first metal layer SHL and the base substrate SBT. Specifically, when preparing the display panel PNL, the transparent conductive layer ITO1 can be formed first, and then the first metal layer SHL can be formed.

[0097] Optionally, the material of the transparent conductive layer ITO1 may be a transparent conductive metal oxide, such as indium tin oxide.

[0098] Optionally, the material of the first metal layer SHL may be metal. For example, the first metal layer SHL includes one metal layer or multiple stacked metal layers.

[0099] Optionally, when the transparent conductive layer ITO1 is electrically connected to the first metal layer SHL, a portion of the structure of the first metal layer SHL is directly overlapped on the transparent conductive layer ITO1.

[0100] In the example of Figure 2 , the pixel layer PIXL includes light-emitting elements corresponding to the sub-pixels PIX. The pixel layer PIXL can include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML, which are stacked in sequence. The pixel electrode layer PEL has multiple pixel electrodes PE in the display area of ​​the display panel. The pixel electrodes PE are electrically connected to the pixel driving circuit PDC through vias.

[0101] Furthermore, referring to FIG2 , the pixel layer PIXL may further include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has a plurality of through-going pixel openings PO (as shown in FIG5 ) arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, with each pixel opening PO exposing at least a portion of the corresponding pixel electrode PE.

[0102] In one example, the pixel electrode PE serves as an anode of the sub-pixel PIX, and the common electrode layer COML serves as a cathode of the sub-pixel PIX.

[0103] Optionally, the common electrode layer COML is a reflective electrode rather than a transparent electrode, such as a metal electrode or a metal oxide electrode. The pixel electrode PE is a transparent electrode, such as a material of a transparent conductive metal oxide (such as indium tin oxide). In this way, the sub-pixel PIX is a bottom-emitting sub-pixel.

[0104] In one example, the common electrode layer COML may be a metal electrode layer, such as a silver metal layer, an aluminum metal layer, a titanium metal layer, or other metal layer with high reflectivity. Of course, when necessary, the surface of the metal electrode layer may also be modified with an alloy, a metal oxide, a metal nitride, or other materials to adjust the carrier injection characteristics (e.g., electron injection characteristics) of the metal electrode layer. For example, the common electrode layer COML is made of aluminum and has a thickness of 100 nanometers.

[0105] In one embodiment of the present disclosure, referring to FIG3 , the pixel driving circuit PDC in the driving layer DRL is a 3T1C circuit, i.e., it includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor CST. The first electrode of the first transistor T1 is electrically connected to a driving power supply voltage signal line VDDL for loading a driving power supply voltage VDD; the first electrode of the second transistor T2 (labeled as T2S in some drawings) is electrically connected to a data signal line DL for loading a data voltage; the first electrode of the third transistor T3 (labeled as T3S in some drawings) is electrically connected to a sensing signal line SL; the gate of the first transistor T1 is electrically connected to the second electrode of the second transistor T2 and the first electrode plate CST1 of the storage capacitor; the second electrode of the first transistor T1 is electrically connected to the second electrode of the third transistor T3 (labeled as T3D in some drawings), the pixel electrode PE of the sub-pixel PIX, and the second electrode plate CST2 of the storage capacitor.

[0106] Optionally, the second electrode of the second transistor T2, the first electrode plate CST1 of the storage capacitor, and the gate T1G of the first transistor are electrically connected to the first node NG, respectively, and the second electrode T3D of the third transistor, the second electrode of the first transistor T1, the pixel electrode PE, and the second electrode plate CST2 of the storage capacitor are electrically connected to the second node NS, respectively.

[0107] Optionally, the driving power supply voltage signal line VDDL is provided on the first metal layer SHL. Optionally, the driving power supply voltage signal line VDDL extends along the column direction DV.

[0108] Optionally, the drive power supply voltage signal line VDDL is connected to the first electrode of the first transistor T1 via a horizontal transfer line HL (see, for example, FIG. 5 ). In one example, the horizontal transfer line HL is disposed on the second metal layer GT and extends in the row direction DH. The drive power supply voltage signal line VDDL is disposed on the first metal layer SHL and extends in the column direction DV. The horizontal transfer line HL intersects the first metal layer SHL and is electrically connected at the intersection via a via. The horizontal transfer line HL is also electrically connected to the first electrode of the first transistor T1 via a via.

[0109] In one example, adjacent horizontal transfer lines HL in a row are interconnected to form a single horizontal transfer line; this single horizontal transfer line is electrically connected to the intersecting drive power supply voltage signal line VDDL through vias. This allows the drive power supply voltage signal to be distributed in a grid pattern, improving the uniformity of the drive power supply voltage signal.

[0110] Optionally, the data signal line DL is provided on the first metal layer SHL. Optionally, the data signal line DL extends along a column direction DV.

[0111] In one example, the gate of the second transistor T2 and the gate of the third transistor T3 are electrically connected to the scanning signal line GL for applying the scanning signal GS, thereby reducing the number of scanning signal lines, saving layout space, and improving the resolution of the display panel PNL.

[0112] It is understood that in each example of the present disclosure, the gate of the second transistor T2 and the gate of the third transistor T3 are connected to the same scan signal line. In other embodiments of the present disclosure, the display panel may also be provided with two scan signal lines to drive the second transistor and the third transistor respectively. For example, the display panel may be provided with a first scan signal line extending along the row direction and a second scan signal line extending along the row direction; the first scan signal line is used to load a first scan signal, and the second scan signal line is used to load a second scan signal; the gate of the second transistor is electrically connected to the first scan signal line, and the gate of the third transistor is electrically connected to the second scan signal line.

[0113] Optionally, the scan signal line GL is located in the second metal layer GT. Optionally, the scan signal line GL extends along the row direction DH. Meanwhile, the second metal layer GT also includes the gate of each transistor.

[0114] In one example, the sensing signal line SL is located in the first metal layer SHL, and the sensing signal line SL is configured to provide a sensing signal to the pixel driving circuit PDC. Optionally, the sensing signal line SL extends along the column direction DV.

[0115] In an exemplary embodiment, the sensing signal line SL can simultaneously provide sensing signals to the pixel drive circuits PDC in four adjacent sub-pixels PIX, i.e., the sensing signal line SL forms a one-to-four structure. By designing the sensing signal line SL as a one-to-four structure, the display panel PNL of the present disclosure reduces the number of signal lines and occupies less space. This results in a simple structure and a rational layout, fully utilizing the layout space, improving space efficiency, and facilitating higher resolution.

[0116] In one example, the second electrode plate CST2 of the storage capacitor is located on the transparent conductive layer ITO1.

[0117] In one example, the storage capacitor first electrode plate CST1 is located on the semiconductor layer SCL.

[0118] In a related technology, referring to FIG4 , in the display panel PNL, the first electrode and the second electrode of the third transistor T3 are respectively located on both sides of the scanning signal line GL. In addition, the first electrode of each transistor is electrically connected to the switching trace located on the second metal layer GT through a via, and is electrically connected to the sensing signal line SL through the switching trace. This results in the need to set a large number of vias on the display panel PNL to ensure the normal transmission of electrical signals. In addition, the length direction of the vias on the first electrode and the second electrode of the third transistor T3 are both in the column direction DV, which results in the size of the third transistor T3 in the column direction DV being too large. These factors will compress the pixel opening PO, resulting in a lower aperture ratio or a lower resolution. In order to optimize the backplane layout and improve the pixel aperture ratio or the resolution of the display panel, the present application optimizes the backplane structure.

[0119] In some embodiments of the present disclosure, referring to FIG5 , the pixel driving circuit PDC in the driving layer DRL is arranged in an array. The first electrode T3S of the third transistor in at least one pixel driving circuit PDC is reused as the first electrode T3S of the third transistor of the adjacent pixel driving circuit PDC in the row direction DH. In this way, two adjacent third transistors T3 share the same first electrode, reducing the layout area of ​​the third transistor T3, thereby facilitating the compression of the layout area of ​​the pixel driving circuit PDC, and providing conditions for improving the aperture ratio or improving the resolution. In one example, the display panel PNL includes a circuit pair arranged in an array, and the circuit pair includes two pixel driving circuits PDC adjacent to each other in the same row; in the same circuit pair, the first electrode of the third transistor T3 of one pixel driving circuit PDC is reused as the first electrode of the third transistor T3 of another pixel driving circuit PDC.

[0120] In one example, when designing a layout for a high-PPI bottom-emitting OLED device, utilizing a shared connection method for the first electrodes of two adjacent third transistors T3 can reduce the number of connection holes, thereby saving layout space. In other words, by multiplexing the first electrode T3S of the third transistor of at least one pixel driver circuit PDC with the first electrode T3S of the third transistor of an adjacent pixel driver circuit PDC, the display panel PNL can improve space utilization and reduce the layout area of ​​the pixel driver circuit PDC, thereby improving the PPI of the display panel.

[0121] In some embodiments of the present disclosure, referring to Figures 5 and 6 , the first electrode T3S and the second electrode T3D of the third transistor are both disposed on the same side of the scan signal line GL. For example, in the examples of Figures 5 and 6 , the first electrode T3S, the channel region T3A, and the second electrode T3D are all disposed on the side of the scan signal line GL away from the pixel opening. This saves layout space, improves layout space utilization, and increases the aperture ratio, making the layout design of the OLED device more rational and prolonging the life of the OLED device.

[0122] In some embodiments of the present disclosure, the transistor is a thin film transistor (TFT), which includes a channel region CR located in a semiconductor layer SCL and two conductive structures CS located on either side of the channel region CR. It will be understood that the thin film transistor TFT further includes a gate located in the second metal layer GT and a gate insulating structure (located in the gate insulating layer) between the gate and the channel region.

[0123] In the disclosed embodiment, referring to FIG2 , the conductive structure CS of the thin film transistor can be selected from any one of three types: a first conductive structure, a second conductive structure, and a third conductive structure, as needed. The two conductive structures CS of the thin film transistor TFT can be of the same type or different types.

[0124] The first conductive structure includes an electrical contact structure located in the semiconductor layer SCL, an overlapping insulating structure located in the gate insulating layer GI, and an overlapping structure located in the second metal layer GT. The overlapping insulating structure has overlapping vias, and the overlapping structure is electrically connected to the electrical contact structure through the overlapping vias. In this first conductive structure CS, the electrical contact structure and the channel region CR are both located in the semiconductor layer SCL and are arranged adjacent to each other. The electrical contact structure and the channel region CR together serve as part of the active layer of the thin-film transistor TFT. The electrical contact structure can serve as the source or drain of the thin-film transistor. The overlapping structure is electrically connected to the electrical contact structure through the overlapping vias, so that the source or drain of the transistor is electrically connected to the second metal layer.

[0125] The second conductive structure includes an electrical contact structure located on the semiconductor layer SCL, an overlapping insulating structure located on the gate insulating layer GI, and an overlapping structure located on the second metal layer GT. Furthermore, the second conductive structure CS overlaps the inorganic buffer layer BUF and the first metal layer SHL. The overlapping insulating structure includes overlapping vias, which include a main via that exposes the semiconductor layer SCL and a first auxiliary via that exposes the first metal layer SHL, outside the region where the semiconductor layer SCL is located. The main via and the first auxiliary via are adjacent to each other. The inorganic buffer layer BUF includes a second auxiliary via aligned with the first auxiliary via; the first and second auxiliary vias expose at least a portion of the first metal layer SHL. The overlapping structure is electrically connected to the electrical contact structure via the main via of the overlapping via; the overlapping structure is electrically connected to the first metal layer SHL via the first and second auxiliary vias of the overlapping via. In this second conductive structure CS, the electrical contact structure and the channel region CR are both located on the semiconductor layer SCL and adjacent to each other. The electrical contact structure and the channel region CR together serve as part of the active layer of the thin-film transistor TFT. The electrical contact structure can serve as the source or drain of the thin film transistor; the overlapping structure is electrically connected to the electrical contact structure through a via and is electrically connected to the first metal layer SHL, so that the source or drain of the transistor is electrically connected to the first metal layer SHL.

[0126] The third conductive structure includes an electrical contact structure located in the semiconductor layer SCL. The electrical contact structure is electrically connected to the second metal layer or the first metal layer without vias. The electrical contact structure and the channel region CR are both located in the semiconductor layer SCL and are adjacent to each other. The electrical contact structure and the channel region CR together serve as part of the active layer of the thin film transistor TFT.

[0127] In one embodiment of the present disclosure, when preparing the display panel PNL, a patterned semiconductor layer SCL can be prepared first, and then a gate insulating layer GI can be prepared. When preparing the gate insulating layer GI, a whole layer of the gate insulating layer GI can be deposited first, and then vias can be opened on the whole layer of the gate insulating layer GI. At least part of the vias expose at least part of the area of ​​the semiconductor layer SCL. After the vias are opened on the whole layer of the gate insulating layer GI, the exposed semiconductor layer SCL is conductively made by ion implantation, so that the exposed areas of the semiconductor layer SCL are all conductively made, and the part of the semiconductor layer SCL covered by the gate insulating layer GI is not conductively made. Then a second metal layer GT is prepared. For example, a whole layer of the second metal layer GT is formed on the side of the gate insulating layer GI away from the semiconductor layer SCL, and then the whole layer of the second metal layer GT is patterned by a photolithography process. When forming the second metal layer GT, in the vias formed by the whole layer of the gate insulating layer GI, the second metal layer GT covers a part of the exposed semiconductor layer SCL. The gate insulating layer GI having vias is patterned using the second metal layer GT as a mask (or using a photoresist layer defining the pattern of the second metal layer GT as a mask). For example, the gate insulating layer GI not covered by the mask (the second metal layer GT or the photoresist layer) is removed by etching. This exposes the semiconductor layer SCL that does not overlap with the mask. Ion implantation is then used to make the exposed semiconductor layer SCL conductive, forming a conductive channel. During this process, the channel region CR of the transistor is protected by the transistor's gate, thereby maintaining its semiconductor properties.

[0128] During the patterning of the gate insulating layer GI using the second metal layer GT as a mask, portions of the exposed semiconductor layer SCL not covered by the gate insulating layer GI may be damaged during etching. For example, the portion of the semiconductor layer SCL not covered by the gate insulating layer GI may be thinned or even partially etched through. As a result, the thickness of the semiconductor layer SCL in the region not covered by the gate insulating layer GI may be thinner than the thickness of the semiconductor layer SCL in the channel region CR.

[0129] In one example, because the gate insulating layer GI is patterned using the second metal layer GT as a mask, the orthographic projection of the gate insulating layer GI on the substrate SBT does not exceed the orthographic projection of the second metal layer GT on the substrate SBT. The second metal layer GT protects the covered gate insulating layer GI, preventing the covered gate insulating layer GI from being etched.

[0130] The pixel driving circuit PDC of the display panel PNL provided by the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings:

[0131] In one embodiment of the present disclosure, referring to Figures 5 and 6 , the third transistor T3 includes a third transistor first electrode T3S, a third transistor channel region T3A, and a third transistor second electrode T3D located in the semiconductor layer SCL. The length direction of the third transistor channel region T3A is the row direction DH. The third transistor first electrode T3S, the third transistor channel region T3A, and the third transistor second electrode T3D are all arranged on the same side of the scan signal line GL. Furthermore, the scan signal line GL has a scan signal line branch portion GLA protruding along the column direction DV. The scan signal line branch portion GLA is arranged to overlap with the third transistor channel region T3A. In other words, the scan signal line branch portion GLA includes the gate of the third transistor T3, and the third transistor channel region T3A is arranged to overlap with the gate of the third transistor T3.

[0132] In an example, the length direction of the third transistor channel region T3A is parallel to the scan signal line GL, for example, arranged along the row direction DH.

[0133] Optionally, as shown in FIG6 , a first via HA is provided on the first electrode T3S of the third transistor. The first electrode T3S of the third transistor is electrically connected to the second metal layer GT through the first via HA. ​​The length of the first via HA is oriented in the column direction DV. Thus, the length of the first via HA is perpendicular to the length of the channel region T3A of the third transistor. This prevents the third transistor T3 from being too large in the row direction DH, thereby reducing the layout area of ​​the pixel driver circuit PDC and facilitating an increase in aperture ratio or resolution.

[0134] In one example, the first via hole HA is open; specifically, the first via hole HA is a notch opened at the edge of the gate insulating layer GI, and the opening of the notch is the opening of the first via hole HA. Furthermore, the opening direction of the first via hole HA (the direction of the notch) is the column direction DV, and in particular, can be toward the pixel opening PO.

[0135] Optionally, as shown in FIG6 , a second via HB is provided on the second electrode T3D of the third transistor. The second electrode T3D of the third transistor is electrically connected to the second metal layer GT through the second via HB. The length of the second via HB is oriented in the column direction DV. Thus, the length of the second via HB is perpendicular to the length of the channel region T3A of the third transistor. This prevents the third transistor T3 from being too large in the row direction DH, thereby reducing the layout area of ​​the pixel driver circuit PDC and facilitating an increase in aperture ratio or resolution.

[0136] In one example, the second via HB is open; specifically, the second via HB is a notch opened at the edge of the gate insulating layer GI, and the opening of the notch is the opening of the second via HB. Furthermore, the opening direction of the second via HB (the direction of the notch) is the column direction DV, and in particular, can be toward the pixel opening PO.

[0137] In one embodiment of the present disclosure, referring to Figures 5 and 6 , the display panel PNL is provided with a transfer structure T3L. The transfer structure T3L is electrically connected to the first electrode T3S of the third transistor and to the sensing signal line SL. Thus, the first electrode T3S of the third transistor is electrically connected to the sensing signal line SL via the transfer structure T3L.

[0138] In the example of FIG6 , both the first via HA and the second via HB are open along the column direction DV, i.e., the opening directions of both the first via HA and the second via HB are perpendicular to the length direction of the third transistor channel region T3A. It is understood that in other embodiments of the present disclosure, one of the first via HA and the second via HB may not be open, or the opening direction may be in the row direction DH.

[0139] In one embodiment of the present disclosure, as shown in FIG6 , both the first via HA and the second via HB are rectangular. The opening direction of the first via HA is parallel to the length direction of the first via HA. ​​The opening direction of the second via HB is parallel to the length direction of the second via HB. This ensures electrical connection between the second metal layer GT and the first and second electrodes T3S and T3D of the third transistor, reducing contact resistance.

[0140] In one embodiment of the present disclosure, referring to Figures 5 to 7, the display panel PNL includes a pixel driving circuit group PDCS arranged in an array, each pixel driving circuit group PDCS includes four pixel driving circuits PDC arranged in the same row, and the four pixel driving circuits PDC are connected to the same sensing signal line SL. Two pixel driving circuits PDC are located on one side of the sensing signal line SL, and the other two pixel driving circuits PDC are located on the other side of the sensing signal line SL. The display panel PNL is also provided with data signal lines DL that respectively drive the four pixel driving circuits PDC of the pixel driving circuit group PDCS; two data signal lines DL are respectively provided on both sides of the sensing signal line SL. In this way, the design layout of the pixel driving circuit PDC in the display panel PNL is realized, making the layout design of the OLED device more reasonable.

[0141] In the embodiment of the present disclosure, if the third transistor first electrode T3S of one pixel driving circuit PDC is multiplexed as the third transistor first electrode T3S of an adjacent pixel driving circuit PDC, the multiplexed third transistor first electrode T3S is referred to as a multiplexing structure TX.

[0142] In the disclosed embodiment, the pixel drive circuit group PDCS is provided with two multiplexing structures TX, and the two multiplexing structures TX are arranged on both sides of the sensing signal line SL. The multiplexing structures TX are located in the semiconductor layer SCL. The multiplexing structures TX serve as the third transistor first electrodes T3S of two adjacent third transistors T3 and are respectively connected to the third transistor channel regions T3A of the two adjacent third transistors T3. In this way, a two-in-one and then re-integrated thin-film transistor (TFT) arrangement can be implemented, and adjacent thin-film transistors TFT share a source and drain, thereby improving space utilization and increasing the aperture ratio.

[0143] Optionally, two data signal lines DL on the same side of the sensing signal line SL overlap with the multiplexing structure TX, so as to achieve one-to-one driving of the pixel driving circuit PDC, thereby reducing the distance between two adjacent data signal lines DL and improving space utilization.

[0144] In one embodiment of the present disclosure, the pixel drive circuit group PDCS drives four different sub-pixels PIX of the same pixel. For example, a pixel includes four different sub-pixels PIX, such as a red sub-pixel, a white sub-pixel, a green sub-pixel, and a blue sub-pixel; the four pixel drive circuits PDC in the pixel drive circuit group PDCS drive the four different sub-pixels PIX, respectively. In one example, along the row direction DH, the four different sub-pixels PIX corresponding to the pixel drive circuit group PDCS are arranged in the order of red sub-pixel, white sub-pixel, green sub-pixel, and blue sub-pixel.

[0145] In one embodiment of the present disclosure, referring to Figures 5 to 9 , a transfer structure T3L corresponds to a pixel drive circuit group PDCS, and the two multiplexing structures TX of the pixel drive circuit group PDCS are electrically connected to the transfer structure T3L, and the transfer structure T3L is electrically connected to the sensing signal line SL. In this way, the two-in-one thin-film transistor TFT can be electrically connected to the sensing signal line SL in a re-integrated manner, thereby reducing the number of connection holes and the number of horizontal scanning signal lines GL, thereby saving space.

[0146] In one embodiment of the present disclosure, referring to Figures 5 to 9, a switching structure T3L is used to electrically connect two multiplexing structures TX with the sensing signal line SL, that is, four third transistors T3 in four pixel driving circuits PDC are connected to the sensing signal line SL after being combined into one, thereby realizing a two-in-one and then-one layout design of thin film transistors TFT.

[0147] In the embodiment of the present disclosure, the transfer structure T3L of the display panel PNL may adopt different forms as needed.

[0148] In one strategy, as shown in Figures 5 and 6 , the transfer structure T3L utilizes a first transfer line T3LA, which is disposed on the same layer as the scan signal lines GL. The first transfer line T3LA is electrically connected to the multiplexing structure TX via a first via HA. ​​Thus, the first electrodes of the four third transistors of the pixel drive circuit group PDCS are electrically connected to each other via the first transfer line T3LA. Furthermore, the first via HA is located between adjacent data signal lines DL.

[0149] Optionally, referring to Figure 6 , the first adapter line T3LA includes a first adapter line segment T3LA1 extending along the row direction DH, and two first adapter line segments T3LA2 connected to the ends of the first adapter line segment T3LA1. The first adapter line segment T3LA2 extends along the column direction DV; the first adapter line segment T3LA1 is electrically connected to the sensing signal line SL; and the first adapter line segment T3LA2 is electrically connected to the multiplexing structure TX. Furthermore, the first adapter line segment T3LA2 is entirely or partially located between two adjacent data signal lines DL.

[0150] Optionally, when etching the portion of the gate insulating layer GI not covered by the second metal layer GT and performing a second conductorization on the underlying semiconductor layer SCL, there is a risk of etching damage to the portion of the semiconductor layer SCL not covered by the second metal layer GT, resulting in an erroneous connection between the scanning signal line GL and the first metal layer SHL.

[0151] In one example, to prevent the second metal layer GT from being mistakenly connected to the first metal layer SHL, the first via HA cannot overlap the data signal line DL. By aligning the length of the first via HA in the column direction DV, the size of the first via HA in the row direction DH can be reduced, thereby shortening the distance between the two data signal lines DL on the same side of the sensing signal line SL. This improves space utilization.

[0152] In another strategy, referring to Figures 8 and 9, the transfer structure T3L includes a second transfer line T3LB, which is arranged in the same layer as the third transistor channel region T3A and is conductive. The second transfer line T3LB is connected to the multiplexing structure TX and is electrically connected to the sensing signal line SL. In this way, the display panel PNL can avoid setting the first via HA, and the two adjacent data signal lines DL do not need to avoid the first via HA, so the distance between the two adjacent data signal lines DL can be further compressed, which is conducive to improving the aperture ratio or resolution. In this strategy, the length of the second transfer line T3LB is not too long, so its use of conductive semiconductor material will not cause serious voltage drop or power loss.

[0153] Moreover, since the second transfer line T3LB is not provided on the second metal layer GT, other structures on the second metal layer GT have a larger layout space. For example, the second metal layer GT is provided with a first metal structure GX1, and the first metal structure GX1 is electrically connected to the second electrode T3D of the third transistor through a second via HB, and is electrically connected to the pixel electrode PE through a pixel electrode via GX1H. Among them, the second via HB is a via opened on the planarization layer PLN. It can be understood that when the display panel PNL is provided with a passivation layer PVX, the second via HB also penetrates the passivation layer PVX and exposes the first metal structure GX1.

[0154] When the first strategy is adopted, the first metal structure GX1 needs to avoid other structures arranged on the same layer, and its size is limited. In one example, referring to Figures 10 and 11, the first metal structure GX1 covers the pixel electrode via GX1H; along the row direction DH, the first metal structure GX1 extends beyond the edge of the pixel electrode via GX1H by a first dimension a1 and a second dimension a2, respectively. Here, a1 is 1 to 2 microns, for example, 1 micron, 1.2 microns, 1.4 microns, 1.6 microns, 1.8 microns, or 2 microns; a2 is 1 to 1.5 microns, for example, 1 micron, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns, or 1.5 microns.

[0155] When the second strategy is adopted, the transfer structure T3L does not squeeze the first metal structure GX1, so the size of the first metal structure GX1 can be increased. In one example, referring to Figures 12 and 13, the first metal structure GX1 covers the pixel electrode via GX1H; along the row direction DH, the first metal structure GX1 extends beyond the edge of the pixel electrode via GX1H by a first dimension a1 and a second dimension a2, respectively. The first dimension a1 and the second dimension a2 are both 2 to 3.5 microns. For example, the first dimension a1 is 2 microns, 2.5 microns, 3 microns, or 3.5 microns. For another example, the second dimension a2 is 2 microns, 2.5 microns, 3 microns, or 3.5 microns. Compared to the first strategy, the second strategy provides space for increasing the size of the first metal structure GX1, thereby improving the reliability of the electrical connection between the pixel electrode PE and the first metal structure GX1.

[0156] In one example, referring to FIG9 , the length direction of the second via HB is the column direction DV. In this way, the size of the second via HB in the row direction DH can be reduced, thereby facilitating the compression of the layout size of the pixel driving circuit PDC in the row direction DH, improving space utilization to increase the aperture ratio or increase the resolution. Furthermore, the second via HB is an open structure, that is, the second via HB extends to an edge of the gate insulating layer GI under the first metal structure GX1; in other words, the gate insulating layer GI under the first metal structure GX1 is provided with a gap serving as the second via HB. Optionally, the opening direction of the second via HB is toward the direction of the pixel opening PO, which can make the pixel electrode via GX1H as far away from the scanning signal line GL as possible, thereby facilitating increasing the size of the pixel opening PO.

[0157] In one example, referring to Figures 8 and 9, in the second strategy, the transfer structure T3L may further include a third transfer line T3LC. The third transfer line T3LC is arranged on the same layer as the scan signal line GL, that is, located in the second metal layer GT. The third transfer line T3LC is electrically connected to the second transfer line T3LB through the fourth via HD, and is electrically connected to the sensing signal line SL through the seventh via HG. Specifically, the fourth via HD spans an edge of the second transfer line T3LB, and its first part exposes the second transfer line T3LB and the second part exposes the sensing signal line SL located in the first metal layer SHL. It can be understood that, in addition to penetrating the gate insulating layer GI, the second part of the fourth via HD also penetrates the inorganic buffer layer BUF. In this way, the number of vias can be reduced and space utilization can be improved.

[0158] It is understood that in some other embodiments of the present disclosure, the first electrode and the second electrode of the third transistor T3 can also be respectively arranged on both sides of the scanning signal line GL, rather than on the same side. For example, in the embodiment illustrated in FIG14 , in the two adjacent third transistors T3 on the same side of the sensing signal line SL, the first electrodes of the two third transistors T3 are reused; however, the first electrode and the second electrode of the third transistor T3 are respectively located on both sides of the scanning signal line GL. In this embodiment, the pixel electrode via GX1H and the pixel opening PO are located on the same side of the scanning signal line GL; due to the large depth of the pixel electrode via GX1H, it is difficult for the pixel definition layer PDL to fully flatten the pixel electrode via GX1H area, and therefore there is a risk of light leakage; compared to the embodiment in which the pixel electrode via GX1H and the pixel opening PO are respectively arranged on both sides of the scanning signal line GL, this embodiment will compress the size of the pixel opening.

[0159] In some embodiments of the present disclosure, referring to Figures 15, 24, and 37, the third transistor T3 is disposed on one side of the scan signal line GL. For example, the channel region, first electrode, and second electrode of the third transistor T3 are all disposed on the side of the scan signal line GL away from the pixel opening PO. In two adjacent pixel driving circuits PDC located on the same side of the sensing signal line SL, the two third transistors T3 share the same first electrode. Furthermore, the two third transistors T3 sharing the same first electrode are staggered, i.e., the two third transistor channel regions T3A are located on either side of the first electrode in the row direction DH. This reduces the space occupied by the third transistor T3.

[0160] In one example, the display panel PNL is a high-PPI bottom-emission OLED display panel. In this display panel PNL, the second transistor T2 and the third transistor T3 are both arranged horizontally (the length direction of the channel region CR is the row direction DH), and the second transistor T2 and the third transistor T3 are respectively located on either side of the scan signal line GL. This can reduce the space occupied by the thin-film transistors, improve the utilization of the layout space, increase the aperture ratio, and increase the lifespan of the OLED device. In other words, the display panel PNL of this example can improve space utilization and reduce the layout area of ​​the pixel drive circuit PDC while meeting the layout space and process requirements by arranging the two third transistors T3 sharing the first electrode horizontally on either side of the scan signal line GL, thereby increasing the aperture ratio of the display panel PNL.

[0161] In the first embodiment of the present disclosure, referring to Figures 15 to 17 , the pixel opening PO of a sub-pixel PIX driven by at least one pixel driving circuit PDC and the third transistor T3 of the pixel driving circuit PDC are located on either side of the scanning signal line GL. This ensures a large distance between the pixel opening PO and the pixel electrode via GX1H in the pixel driving circuit PDC, preventing the pixel electrode via GX1H from squeezing the pixel opening PO and improving the aperture ratio.

[0162] In the first embodiment of the present disclosure, referring to Figures 15, 16, and 18, the second metal layer GT has a first metal structure GX1. The first metal structure GX1 is electrically connected to the second electrode plate CST2 of the storage capacitor (located in the transparent conductive layer ITO1) through a fifth via HE (see Figure 15). The first metal structure GX1 is also electrically connected to the second electrode T3D of the third transistor through a second via HB. The planarization layer PLN has a pixel electrode via GX1H that exposes at least a portion of the first metal structure GX1. The pixel electrode via GX1H and the pixel opening PO are respectively located on either side of the scanning signal line GL. In this way, a sufficiently large distance is ensured between the pixel electrode via GX1H and the pixel opening PO, which is conducive to increasing the aperture ratio.

[0163] In an example, the second via hole HB passes through the gate insulating layer GI; the fifth via hole HE passes through the gate insulating layer GI and the inorganic buffer layer BUF in sequence, and the fifth via hole HE is adjacent to and connected to the second via hole HB.

[0164] In the first embodiment of the present disclosure, referring to Figures 15, 16, and 19, the length direction of the third transistor channel region T3A is in the row direction DH; the first electrode T3S of the third transistor is electrically connected to the second metal layer GT via a first via HA, and the second electrode T3D of the third transistor is electrically connected to the second metal layer GT via a second via HB. The length directions of the first via HA and the second via HB are both in the column direction DV. The scan signal line GL has a first scan signal line branch portion GLA1 that protrudes along the column direction DV toward the side away from the pixel opening PO; the first scan signal line branch portion GLA1 includes the gate of the third transistor T3, and the channel region of the third transistor T3 is arranged overlapping with the gate of the third transistor. This arrangement allows the third transistors T3 to be arranged horizontally (along the row direction DH), facilitating the sharing of the first electrode between two adjacent third transistors T3 and improving space utilization. Furthermore, the connection between the third transistor T3 and the scan signal line GL is achieved, saving layout space.

[0165] Optionally, referring to Figures 15, 16, and 20, a second transistor T2 and a third transistor T3 are respectively disposed on either side of the scan signal line GL. The second transistor T2 includes an active layer located in the semiconductor layer SCL; the active layer of the second transistor T2 includes a first electrode, a channel region, and a second electrode connected in sequence. The second transistor channel region T2A extends longitudinally along the row direction DH. The scan signal line GL includes a second scan signal line branch portion GLA2 protruding along the column direction DV. The second scan signal line branch portion GLA2 includes the gate of the second transistor T2, and the gate of the second transistor T2 is arranged overlapping with the second transistor channel region T2A. This allows the second transistor T2 to be connected to the scan signal line GL and helps save layout space.

[0166] In the first embodiment of the present disclosure, referring to Figures 15, 16, and 21, the second metal layer GT includes a second metal structure GX2. The second metal structure GX2 is electrically connected to the data signal line DL via a third via HC and to the first electrode T2S of the second transistor via a sixth via HF. Furthermore, the third via HC and the sixth via HF are connected to form a single integral via. This allows for electrical connection between the data signal line DL and the second transistor T2.

[0167] Optionally, the third via HC passes through the gate insulating layer GI and the inorganic buffer layer BUF in sequence and is electrically connected to the data signal line DL (located on the first metal layer SHL), the sixth via HF passes through the gate insulating layer GI and is electrically connected to the first electrode T2S of the second transistor, and the third via HC and the sixth via HF are connected at one end close to each other.

[0168] Furthermore, the second electrode T3D of the third transistor is electrically connected to the second electrode of the first transistor via the transparent conductive layer ITO1.

[0169] In the first embodiment of the present disclosure, referring to Figures 15, 16, and 22, the first electrode T2S of the second transistor extends along the column direction DV; the orthographic projection of the first electrode T2S of the second transistor in the column direction DV partially overlaps with the orthographic projection of the pixel opening PO in the column direction DV. The end of the first electrode T2S of the second transistor, distal from the second transistor channel region T2A, is electrically connected to the data signal line DL via the second metal structure GX2. This allows the second transistor channel region T2A to be closer to the scan signal line GL, improving space utilization and further increasing the aperture ratio.

[0170] In this embodiment, referring to FIG. 22 , the end of the first electrode T2S of the second transistor is away from the scanning signal line GL, which makes the distance between the second transistor channel region T2A and the second metal structure GX2 longer, that is, the first electrode T2S of the second transistor is longer and performs a routing function.

[0171] In the first embodiment of the present disclosure, optionally referring to FIG. 15 , FIG. 16 , and FIG. 23 , the scan signal line GL includes a second scan signal line branch portion GLA2 protruding along the column direction DV. A gap exists between the orthographic projection of the second scan signal line branch portion GLA2 in the column direction DV and the orthographic projection of the second metal structure GX2 in the column direction DV. This prevents interference between the second scan signal line branch portion GLA2 and the second metal structure GX2.

[0172] In this embodiment, optionally, as shown in FIG16 , a first, inwardly recessed relief notch is provided at one end of the pixel opening PO proximate to the second metal structure GX2. This first relief notch avoids the second metal structure GX2, and in particular, avoids the various vias connected to the second metal structure GX2. It will be appreciated that if the display panel PNL is a top-emitting display panel, the pixel opening PO may not be provided with the first relief notch.

[0173] In this embodiment, referring to FIG. 17 , a second avoidance notch recessed inward is provided at one end of the pixel opening PO close to the first transistor T1 . The second avoidance notch is used to avoid the via hole, prevent light leakage, and improve the display quality of the display panel.

[0174] It is understood that the display panel of the embodiment of the present disclosure is not limited to the description of the above embodiments, and the structure and features of the embodiment of the present disclosure can also be adjusted to achieve similar or better effects.

[0175] Figures 24 to 26 illustrate a second embodiment of the present disclosure. In this second embodiment, the scan signal line GL includes a first scan signal line branch portion GLA1 and a second scan signal line branch portion GLA2 that protrude along the column direction DV. The first scan signal line branch portion GLA1 and the second scan signal line branch portion GLA2 are located on either side of the scan signal line GL. Along the row direction DH, the first scan signal line branch portion GLA1 is located between the second scan signal line branch portion GLA2 and the data signal line DL. Thus, the first scan signal line branch portion GLA1 and the second scan signal line branch portion GLA2 are staggered, allowing the second transistor T2 and the third transistor T3 to be staggered on either side of the scan signal line GL, thereby reducing the space occupied by the thin-film transistors TFT and increasing the opening.

[0176] Compared with the first embodiment, the distance between the second transistor channel region T2A and the data signal line DL in the second embodiment is increased, so that the second metal structure GX2 can be set close to the scanning signal line GL, thereby avoiding the second metal structure GX2 being far away from the scanning signal line GL and occupying a large amount of space.

[0177] In one example, referring to Figures 24, 25, and 27, the orthographic projection of the first electrode T2S of the second transistor in the column direction DV does not overlap with the orthographic projection of the pixel opening PO in the column direction DV. This reduces the length of the first electrode T2S of the second transistor between the second transistor channel region T2A and the second metal structure GX2, thereby reducing the distance between the semiconductor layer SCL connecting the data signal line DL and the second transistor channel region T2A and reducing impedance. Furthermore, the end of the first electrode T2S of the second transistor is closer to the scan signal line GL, which helps reduce the area of ​​the second transistor T2 and allows for a more concentrated arrangement of the thin-film transistors TFT, thereby improving the aperture ratio.

[0178] In an example, referring to FIG. 24 , FIG. 25 and FIG. 28 , the orthographic projection of the second scan signal line branch portion GLA2 in the column direction DV partially overlaps with the orthographic projection of the second metal structure GX2 in the column direction DV.

[0179] In one example, referring to FIG. 24 , a third, inwardly recessed relief notch is provided at one end of the pixel opening PO near the second metal structure GX2. This third relief notch avoids the via connected to the second metal structure GX2. Compared to the first embodiment, the second metal structure GX2 in this example is closer to the scan signal line GL, and therefore the via connected to the second metal structure GX2 is closer to the scan signal line GL. This allows the third relief notch to be smaller than the first relief notch, thereby increasing the size of the pixel opening.

[0180] Figure 29 illustrates a schematic structural diagram of the transparent conductive layer ITO1 in this second embodiment. A second electrode plate CST2 for a storage capacitor is formed on the transparent conductive layer ITO1. One end of the second electrode plate CST2 is electrically connected to the first metal structure GX1 via a fifth via HE, and the other end is electrically connected to the second electrode of the first transistor.

[0181] Figure 30 illustrates a schematic structural diagram of the first metal layer SHL in this second embodiment. The first metal layer SHL is formed with data signal lines DL, drive power supply voltage signal lines VDDL, and sensing signal lines SL. As such, the display panel PNL does not require a source / drain metal layer, thereby reducing the thickness and manufacturing cost of the display panel PNL. Furthermore, the first metal layer SHL also includes a light shielding portion SX, which can overlap with the channel region of the first transistor T1 to shield light from the channel region of the first transistor T1. Furthermore, the orthographic projection of the channel region of the first transistor T1 on the substrate SBT is completely within the orthographic projection of the light shielding portion SX on the substrate SBT. Furthermore, the orthographic projection of the active layer of the first transistor T1 on the substrate SBT is completely within the orthographic projection of the light shielding portion SX on the substrate SBT.

[0182] Figure 31 illustrates a schematic structural diagram of the semiconductor layer SCL in this second embodiment. The semiconductor layer SCL forms the active layer of each thin-film transistor (TFT). The active layer of each thin-film transistor (TFT) includes a first electrode, a channel region, and a second electrode that are sequentially connected. Furthermore, the semiconductor layer SCL also forms a first electrode plate CST1 of a storage capacitor, which is directly connected to the second electrode of the second transistor T2.

[0183] Figure 32 illustrates a schematic diagram of the structure of the second metal layer GT in this second embodiment. Figure 33 illustrates a schematic diagram of the positional relationship between the second metal layer GT and the via it covers in this second embodiment. Figure 34 illustrates a schematic diagram of the positional relationship between the via exposing the second metal layer GT and the second metal layer GT in this second embodiment. Referring to Figure 32 , the second metal layer GT includes a scan signal line GL, a first metal structure GX1, a second metal structure GX2, and a first adapter line T3LA that electrically connects the first electrode T3S of the third transistor to the sensing signal line SL.

[0184] The second metal layer GT is further provided with a horizontal transfer line HL extending along the row direction DH. The horizontal transfer line HL is electrically connected to the drive power supply voltage signal line VDDL through a via, and is also electrically connected to the first electrode of at least one first transistor T1. Furthermore, two pixel drive circuits PDC are provided on either side of each drive power supply voltage signal line VDDL, and these four pixel drive circuits PDC are arranged in a row; each horizontal transfer line HL is also electrically connected to the first electrode T3S of the third transistor of each of the four pixel drive circuits PDC.

[0185] The second metal layer GT is further provided with a first transistor gate T1G, which overlaps with the channel region of the first transistor T1. The gate of the first transistor T1 is also electrically connected to the first electrode plate CST1 of the storage capacitor through a via.

[0186] The second metal layer GT is further provided with a fourth metal structure GX4 , which is electrically connected to the second electrode of the first transistor T1 through a via, and is also electrically connected to the second electrode plate CST2 of the storage capacitor through a via.

[0187] 33 , vias (eg, first vias HA, second vias HB, etc.) are provided on the gate insulating layer GI and the inorganic buffer layer BUF, and the second metal layer GT covers these vias so that the second metal layer GT is electrically connected to the semiconductor layer SCL, the first metal layer SHL, etc.

[0188] 34 , the passivation layer PVX and the planarization layer PLN are both provided with a pixel electrode via hole GX1H, and the pixel electrode via hole GX1H is used for electrically connecting the pixel electrode PE and the first metal structure GX1.

[0189] Figure 35 illustrates a schematic structural diagram of the pixel electrode layer PEL in the second embodiment. Referring to Figure 35 , the pixel electrode layer PEL is provided with the pixel electrode PE of the display panel PNL, and the pixel electrode PE is electrically connected to the first metal structure GX1 through the pixel electrode via GX1H.

[0190] Figure 36 illustrates a schematic structural diagram of the pixel opening PO in the second embodiment. The pixel opening PO is opened in the pixel definition layer PDL, exposing a partial area of ​​the pixel electrode PE. In the first embodiment of the present disclosure (as shown in Figure 15) and the second embodiment (as shown in Figure 24), each pixel driving circuit group PDCS includes four pixel driving circuits PDC arranged in the same row; the four pixel driving circuits PDC are connected to the same sensing signal line SL; wherein, two pixel driving circuits PDC are located on one side of the sensing signal line SL, and the other two pixel driving circuits PDC are located on the other side of the sensing signal line SL. The pixel openings PO of the four sub-pixels PIX corresponding to the pixel driving circuit group PDCS are all located on the same side of the scanning signal line GL.

[0191] It will be appreciated that, in the embodiments of the present disclosure, the arrangement of the pixel drive circuits PDC is not limited to this. For example, in the third embodiment of the present disclosure, referring to Figures 37 to 42, each pixel drive circuit group PDCS includes four pixel drive circuits PDC connected to the same sensing signal line SL; wherein two pixel drive circuits PDC are located on one side of the sensing signal line SL, and the other two pixel drive circuits PDC are located on the other side of the sensing signal line SL; two pixel drive circuits PDC are located on one side of the scanning signal line GL, and the other two pixel drive circuits PDC are located on the other side of the scanning signal line GL. Thus, in the embodiments of the present disclosure, the four sub-pixels PIX are arranged in two rows and two columns; each scanning signal line GL can simultaneously drive two rows of pixel drive circuits PDC, thereby reducing the number of scanning signal lines GL, facilitating the size compression of the pixel drive circuit PDC in the column direction DV, and reducing the height (column direction) to width (row direction) ratio of the pixel drive circuit PDC, thereby overcoming the reduced space utilization caused by the overly narrow and long layout area of ​​the pixel drive circuit PDC, thereby facilitating the increase in pixel aperture size and resolution.

[0192] In an example of the third embodiment of the present disclosure, referring to Figures 37 to 39 , the second transistor T2 and the third transistor T3 of the same pixel driver circuit PDC are respectively arranged on the same side of the scan signal line GL. The scan signal line GL has a first scan signal line branch portion GLA1 and a second scan signal line branch portion GLA2 protruding along the column direction DV. The first scan signal line branch portion GLA1 is provided with the gate of the third transistor T3 and is arranged to overlap with the third transistor channel region T3A; the second scan signal line branch portion GLA2 is provided with the gate of the second transistor T2 and is arranged to overlap with the second transistor channel region T2A. In the region where the pixel driver circuit PDC is located, the protruding direction of the first scan signal line branch portion GLA1 and the protruding direction of the second scan signal line branch portion GLA2 are both toward the pixel opening PO. In other words, in this embodiment, the second transistor T2 and the third transistor T3 are both arranged between the scan signal line GL and the pixel opening PO.

[0193] In a third embodiment of the present disclosure, referring to Figures 37 and 38 , the first transistor T1 is disposed on a side of the second transistor T2 away from the scanning signal line GL. Two first transistors T1 adjacent to each other along the column direction DV share a first electrode. In other words, the first electrode of one of the two first transistors T1 adjacent to each other along the column direction DV serves as the first electrode of the adjacent first transistor T1. This further reduces the space occupied by the thin-film transistors (TFTs) and increases the aperture ratio.

[0194] In an example of the third embodiment of the present disclosure, referring to Figures 37, 38, and 40, the second transistor channel region T2A and the third transistor channel region T3A are arranged along the row direction DH; the second transistor channel region T2A is located on the side of the third transistor channel region T3A away from the sensing signal line SL. In this way, two adjacent third transistors T3 in the same row on either side of the sensing signal line SL can share a first electrode. This shared first electrode can be electrically connected to the sensing signal line SL located on the first metal layer SHL via a transfer structure T3L provided on the second metal layer GT. This helps reduce the number of vias and, in turn, helps improve the aperture ratio. For example, referring to Figure 42, third transfer lines T3LC (located on the second metal layer GT) corresponding to the sensing signal line SL are provided on both sides of the scanning signal line GL. The first electrodes T3S of the two third transistors located on the same side of the scanning signal line GL are both electrically connected to the sensing signal line SL via the third transfer line T3LC on the same side. In this way, two thin-film transistors TFT can be connected to the sensing signal line SL through a single via, reducing the number of connection holes and improving space utilization.

[0195] In an example of the third embodiment of the present disclosure, referring to Figures 37, 38 and 41, the second metal layer GT has a third metal structure GX3, which is electrically connected to the second electrode plate CST2 of the storage capacitor through a via, and the third metal structure GX3 is electrically connected to the second electrode of the first transistor T1 through a via; the planarization layer PLN has a pixel electrode via GX1H that exposes at least a portion of the third metal structure GX3, and the pixel electrode via GX1H and the pixel opening PO are located on the same side of the scanning signal line GL. Furthermore, the pixel electrode via GX1H is arranged in the same row as the channel region of the first transistor T1, and both are arranged on the side of the pixel opening PO away from the scanning signal line GL. In this way, the pixel electrode via GX1H is prevented from being arranged between the transistor and the pixel opening PO and affecting the aperture ratio.

[0196] In one example of the third embodiment of the present disclosure, as shown in FIG37 , a fourth, inwardly recessed clearance notch is provided on the side of the pixel opening proximate to the second electrode of the second transistor T2; and a fifth, inwardly recessed clearance notch is provided on the side of the pixel opening proximate to the second electrode of the third transistor T3D. The fourth and fifth clearance notches are used to avoid the via hole, reducing the risk of light leakage caused by the via hole and improving the display quality of the display panel PNL. Because the second transistor T2 and the third transistor T3 are arranged in the same row, the fourth and fifth clearance notches are both relatively small, which facilitates increasing the size of the pixel opening.

[0197] The inventors also tested the aperture ratios of the display panels PNL of different examples. The test results show that the average aperture ratio of the display panel PNL shown in FIG14 is 15.8%, the average aperture ratio of the display panel PNL of the first embodiment is 24.8%, the average aperture ratio of the display panel PNL of the second embodiment is 26.6%, and the average aperture ratio of the display panel PNL of the third embodiment is 28%. The test results further confirm that the third embodiment has the highest average aperture ratio.

[0198] The present disclosure also provides a display device comprising any of the display panels described in the display panel embodiments above. The display device may be a smartphone screen, a smartwatch screen, or another type of display device. Because the display device comprises any of the display panels described in the display panel embodiments above, it exhibits the same beneficial effects, and the present disclosure will not elaborate further here.

[0199] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: The display panel comprises a base substrate, a driving layer and a pixel layer which are sequentially stacked, wherein the driving layer comprises a first metal layer, a semiconductor layer, a gate insulating layer, a second metal layer and a planarization layer which are sequentially stacked on the base substrate; The driving layer includes a pixel driving circuit arranged in an array for driving the pixel layer; wherein the pixel driving circuit includes a first transistor, a second transistor, a third transistor and a storage capacitor, wherein the transistor includes a gate, a first electrode and a second electrode; The display panel includes a scanning signal line and a sensing signal line; the gate of the third transistor is electrically connected to the scanning signal line, the first electrode of the third transistor is electrically connected to the sensing signal line; the second electrode of the third transistor is electrically connected to the pixel electrode; Among them, the first electrode of the third transistor in at least one of the pixel driving circuits is multiplexed as the first electrode of the third transistor of the adjacent pixel driving circuit in the row direction.

2. The display panel according to claim 1, characterized in that: The third transistor comprises a third transistor channel region located in the semiconductor layer, the length direction of the third transistor channel region is the row direction; the third transistor channel region, the first electrode and the second electrode of the third transistor are all located on the same side of the scanning signal line; The scan signal line extends along the row direction and has a scan signal line branch protruding along the column direction; the scan signal line branch includes a gate of the third transistor, and the third transistor channel region overlaps with the gate of the third transistor.

3. The display panel according to claim 1, characterized in that: The display panel is provided with a switching structure, and the switching structure is electrically connected to the first electrode of the third transistor and is electrically connected to the sensing signal line.

4. The display panel according to claim 1, characterized in that: The second metal layer is provided with a metal structure, and the metal structure is electrically connected to the second electrode of the third transistor through a second via hole; the length direction of the second via hole is the column direction.

5. The display panel according to claim 1, characterized in that: The display panel includes a pixel driving circuit group arranged in an array, each of the pixel driving circuit groups includes four pixel driving circuits arranged in a row, and the four pixel driving circuits are connected to the same sensing signal line; wherein two of the pixel driving circuits are located on one side of the sensing signal line, and the other two of the pixel driving circuits are located on the other side of the sensing signal line; The semiconductor layer is provided with multiplexing structures on both sides of the sensing signal line, respectively. The multiplexing structures serve as first electrodes of two adjacent third transistors and are respectively connected to channel regions of two adjacent third transistors.

6. The display panel according to claim 5, characterized in that: The display panel is further provided with a switching structure corresponding to the pixel driving circuit group, the two multiplexing structures of the pixel driving circuit group are electrically connected to the switching structure respectively, and the switching structure is electrically connected to the sensing signal line.

7. The display panel according to claim 5, characterized in that: The display panel is also provided with data signal lines respectively driving the four pixel driving circuits of the pixel driving circuit group; Wherein, two data signal lines are respectively arranged on both sides of the sensing signal line; and the two data signal lines located on the same side of the sensing signal line overlap with the multiplexing structure.

8. The display panel according to claim 7, characterized in that: The display panel is provided with a switching structure, which includes a first switching line, which is arranged in the same layer as the scanning signal line; the first switching line is electrically connected to the multiplexing structure through a first via hole, and the first via hole is located between adjacent data signal lines.

9. The display panel according to claim 8, characterized in that: The first adapter wire comprises a first adapter wire first section extending in a row direction, and two first adapter wire second sections respectively connected to two ends of the first adapter wire first section, and the first adapter wire second section extends in a column direction; The first section of the first patch cord is electrically connected to the sensing signal line; the second section of the first patch cord is electrically connected to the multiplexing structure; The second section of the first adapter wire is located between two adjacent data signal lines.

10. The display panel according to claim 7, characterized in that: The display panel is provided with a switching structure; the switching structure includes a second switching line, the second switching line is provided in the same layer as the third transistor channel region and is conductorized; the second switching line is connected to the multiplexing structure and is electrically connected to the sensing signal line.

11. The display panel according to claim 10, characterized in that: The transfer structure further includes a third transfer line, and the third transfer line is arranged on the same layer as the scanning signal line; The third adapter line is electrically connected to the second adapter line through a fourth via hole, and is electrically connected to the sensing signal line through a seventh via hole.

12. The display panel according to claim 1, characterized in that: The first electrode of the first transistor is electrically connected to a driving power supply voltage line for loading a driving power supply voltage, the first electrode of the second transistor is electrically connected to a data signal line for loading a data voltage, and the first electrode of the third transistor is electrically connected to the sensing signal line for loading a reference power supply voltage; the second electrode of the second transistor, the first electrode plate of the storage capacitor, and the gate of the first transistor are electrically connected to the first node, respectively, and the second electrode of the third transistor, the second electrode of the first transistor, the pixel electrode, and the second electrode plate of the storage capacitor are electrically connected to the second node, respectively.

13. The display panel according to claim 1, characterized in that: A pixel electrode via hole is provided on the planarization layer, and the pixel electrode is electrically connected to the first metal structure located on the second metal layer through the pixel electrode via hole; The first metal structure is electrically connected to the second electrode of the third transistor through a second via; The orthographic projection of the pixel electrode via hole on the base substrate partially overlaps with the orthographic projection of the second via hole on the base substrate.

14. The display panel according to claim 1, characterized in that: A pixel electrode via hole is provided on the planarization layer, and the pixel electrode is electrically connected to the first metal structure located on the second metal layer through the pixel electrode via hole; The pixel electrode via hole, the first electrode of the third transistor, and the second electrode of the third transistor are located on the same side of the scanning signal line.

15. A display device, comprising the display panel according to any one of claims 1 to 14.

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