Display panel and display apparatus

Abstract

A display panel (PNL) and a display apparatus, which relate to the technical field of display. The display panel (PNL) comprises a base substrate (SBT), a driving layer (DRL) and a pixel layer (PIXL), which are sequentially stacked, wherein the driving layer (DRL) has transistors (TFTs) for driving sub-pixels (PIX); at least one transistor (TFT) comprises a channel region (CR) located on a semiconductor layer (SCL), and comprises two conductive structures (CSs) located on two sides of the channel region (CR); at least one conductive structure (CS) comprises an electrical contact structure (ECS) located on the semiconductor layer (SCL), an overlapping insulation structure (GIS) located on a gate insulation layer (GI), and an overlapping structure (OS) located on a second metal layer (GT); the overlapping insulation structure (GIS) has an overlapping via hole (GIH), and the overlapping structure (OS) is electrically connected to the electrical contact structure (ECS) by means of the overlapping via hole (GIH); and the length direction (ED) of at least one overlapping via hole (GIH) of the at least one transistor (TFT) is not parallel to the length direction (LE) of the channel region (CR) of the transistor (TFT). The display panel (PNL) can improve the space utilization rate to the greatest extent, improve the aperture ratio of a display device, and prolong the service life of an OLED device.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311786394.3, filed on December 22, 2023, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] With the continuous development of display technology, the application range of display panels is becoming increasingly wider, and people's requirements for display panels are also becoming higher and higher. Display panels with a high pixel count per inch have higher image density and better image quality. However, the higher the pixel count per inch of the display panel, the smaller the pixel size and the smaller the layout space. For bottom-emitting OLED devices with high pixel count per inch, it is even more important to optimize the layout to maximize space utilization, increase the aperture ratio, and increase the life of the OLED device. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device to increase the number of pixels per inch and improve the aperture ratio.

[0006] According to a first aspect of the present disclosure, a display panel is provided, comprising a base substrate, a driving layer, and a pixel layer stacked in sequence, wherein the driving layer comprises a transistor for driving sub-pixels; the driving layer comprises a first metal layer, a semiconductor layer, a gate insulating layer, a second metal layer, and a planarization layer stacked in sequence on the base substrate;

[0007] At least one of the transistors includes a channel region located in the semiconductor layer and two conductive structures located on both sides of the channel region; at least one of the conductive structures includes an electrical contact structure located in the semiconductor layer, a strapping insulating structure located in the gate insulating layer, and a strapping structure located in the second metal layer;

[0008] The overlapping insulating structure has an overlapping via, and the overlapping structure is electrically connected to the electrical contact structure through the overlapping via;

[0009] Wherein, a length direction of at least one overlapping via of at least one transistor is not parallel to a length direction of a channel region of the transistor.

[0010] According to one embodiment of the present disclosure, a length direction of a bridging via of the at least one transistor is perpendicular to a length direction of a channel region of the transistor.

[0011] According to an embodiment of the present disclosure, the length directions of the two overlapping vias of the at least one transistor are both perpendicular to the length direction of the channel region of the transistor.

[0012] According to an embodiment of the present disclosure, the overlapping via extends to the edge of the overlapping insulation structure and presents an open structure; the length direction of the overlapping via is the open direction of the overlapping via.

[0013] According to one embodiment of the present disclosure, the orthographic projection of the gate insulating layer on the base substrate does not exceed the orthographic projection of the second metal layer on the base substrate.

[0014] According to one embodiment of the present disclosure, at least one of the electrical contact structures has an adjacent area exposed by the gate insulation layer and the second metal layer and adjacent to the overlapping via, and the thickness of the semiconductor layer in the adjacent area is less than the thickness of the semiconductor layer in the channel area.

[0015] According to an embodiment of the present disclosure, along the length direction of the overlapping via, the size of the adjacent area is smaller than the size of the overlapping via.

[0016] According to one embodiment of the present disclosure, the electrical contact structure includes a first conductive region, a second conductive region, and a third conductive region connected in sequence;

[0017] The first conductive region is located between the channel region of the transistor and the adjacent region; the second conductive region is located on a side of the adjacent region away from the overlapping via; and the third conductive region is located on a side of the adjacent region away from the channel region.

[0018] According to one embodiment of the present disclosure, the driving layer also includes a first metal layer and an inorganic buffer layer located between the base substrate and the semiconductor layer; the inorganic buffer layer is located between the first metal layer and the semiconductor layer; the first metal layer and the second metal layer are connected through vias.

[0019] According to one embodiment of the present disclosure, at least one of the overlapping vias further includes a first auxiliary hole covered by the overlapping structure and extending beyond the electrical contact structure; the inorganic buffer layer has a second auxiliary hole aligned with the first auxiliary hole; the first auxiliary hole and the second auxiliary hole expose at least a portion of the first metal layer;

[0020] The overlapping structure is electrically connected to the first metal layer through the first auxiliary hole and the second auxiliary hole.

[0021] According to one embodiment of the present disclosure, the driving layer has a pixel driving circuit for driving the pixel layer, the pixel driving circuit includes a storage capacitor, a first transistor, a second transistor, and a third transistor, wherein the transistor includes a gate, a first electrode, and a second electrode;

[0022] The first electrode of the first transistor is used to apply a driving power supply voltage, the gate of the first transistor is electrically connected to the second electrode of the second transistor and the first electrode plate of the storage capacitor, the second electrode of the first transistor is electrically connected to the second electrode of the third transistor, the pixel electrode of the sub-pixel, and the second electrode plate of the storage capacitor, and the first electrode of the third transistor is electrically connected to the sensing signal line; the first electrode of the second transistor is used to apply a data voltage;

[0023] The gate of the second transistor and the gate of the third transistor are used to load a scan signal;

[0024] The inorganic buffer layer and the gate insulating layer have sensing vias, and the sensing signal line is electrically connected to the second metal layer through the sensing vias;

[0025] The first transistor has a first conductive structure adjacent to the sensing via, and a length direction of the first conductive structure connecting the via is perpendicular to a channel region of the first transistor.

[0026] According to an embodiment of the present disclosure, the length direction of the overlapping vias of the first conductive structure is a row direction;

[0027] The length direction of the first transistor channel region is the column direction.

[0028] According to one embodiment of the present disclosure, the driving layer has a pixel driving circuit for driving the pixel layer, the pixel driving circuit includes a storage capacitor, a first transistor, a second transistor, and a third transistor, wherein the transistor includes a gate, a first electrode, and a second electrode;

[0029] The first electrode of the first transistor is used to apply a driving power supply voltage, the gate of the first transistor is electrically connected to the second electrode of the second transistor and the first electrode plate of the storage capacitor, the second electrode of the first transistor is electrically connected to the second electrode of the third transistor, the pixel electrode of the sub-pixel, and the second electrode plate of the storage capacitor, and the first electrode of the third transistor is electrically connected to the sensing signal line; the first electrode of the second transistor is used to apply a data voltage;

[0030] The gate of the second transistor and the gate of the third transistor are used to load a scan signal;

[0031] The inorganic buffer layer and the gate insulating layer have sensing vias, and the sensing signal line is electrically connected to the second metal layer through the sensing vias;

[0032] The third transistor has a second conductive structure adjacent to the sensing via hole, and a length direction of the overlapping via hole of the second conductive structure is perpendicular to the channel region of the third transistor.

[0033] According to an embodiment of the present disclosure, the length directions of the overlapping vias of the two conductive structures of the third transistor are both in the column direction;

[0034] The length direction of the channel region of the third transistor is the row direction.

[0035] According to a second aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0036] The display panel disclosed herein can maximize space utilization, increase the aperture ratio of the display device, and increase the life of the OLED device.

[0037] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0039] FIG1 is a schematic diagram of a planar structure of a display panel in one embodiment of the present disclosure.

[0040] FIG2 is a schematic diagram of a film layer structure of a display panel in one embodiment of the present disclosure.

[0041] FIG3 is an equivalent circuit diagram of a 3T1C pixel driving circuit in one embodiment of the present disclosure.

[0042] FIG4 is a schematic structural diagram of a first conductive structure in one embodiment of the present disclosure.

[0043] FIG5 is a schematic structural diagram of an overlapping insulating structure of a first conductive structure in one embodiment of the present disclosure.

[0044] FIG6 is a schematic diagram of a partial cross-sectional structure of a first conductive structure in one embodiment of the present disclosure.

[0045] FIG7 is a schematic structural diagram of a second conductive structure in one embodiment of the present disclosure.

[0046] FIG8 is a schematic structural diagram of an overlapping insulating structure of a second conductive structure in one embodiment of the present disclosure.

[0047] FIG9 is a schematic diagram of a partial cross-sectional structure of a second conductive structure in one embodiment of the present disclosure.

[0048] FIG10 is a schematic structural diagram of a third conductive structure in one embodiment of the present disclosure.

[0049] FIG. 11 is a schematic structural diagram of forming a lapped via on a gate insulating layer in one embodiment of the present disclosure.

[0050] FIG12 is a schematic structural diagram of forming a second metal layer by a photolithography process in one embodiment of the present disclosure.

[0051] FIG13 is a schematic structural diagram of a gate insulating layer patterned using the second metal layer as a mask in one embodiment of the present disclosure.

[0052] FIG14 is a schematic diagram of a conductive channel of a first conductive structure in one embodiment of the present disclosure.

[0053] FIG15 is a schematic diagram of a conductive channel of a second conductive structure in one embodiment of the present disclosure.

[0054] FIG16 is a schematic diagram of via connections of an I-type transistor in one embodiment of the present disclosure.

[0055] FIG17 is a schematic diagram of via connections of an L-type transistor in one embodiment of the present disclosure.

[0056] FIG18 is a schematic diagram of a film layer structure of a display panel in one embodiment of the present disclosure.

[0057] FIG19 is a schematic diagram of the partial structure of the first metal layer, the second metal layer and the semiconductor layer in FIG18 .

[0058] FIG20 is a schematic diagram of the partial structure of the first metal layer, the second metal layer and the semiconductor layer of an I-type transistor in one embodiment of the present disclosure.

[0059] FIG21 is a schematic diagram of via connections of a single-sided L-type transistor in one embodiment of the present disclosure.

[0060] FIG22 is a schematic diagram of the partial structure of the first metal layer, the second metal layer and the semiconductor layer of a single-sided L-type transistor in one embodiment of the present disclosure.

[0061] FIG23 is a schematic diagram of via connections of a double-sided L-type transistor in one embodiment of the present disclosure.

[0062] FIG24 is a schematic diagram of the partial structure of the first metal layer, the second metal layer and the semiconductor layer of a double-sided L-type transistor in one embodiment of the present disclosure.

[0063] FIG25 is a schematic diagram of an offset via connection of an L-type transistor in one embodiment of the present disclosure.

[0064] FIG26 is a schematic diagram of via connections of an L-type transistor with a compensation region in one embodiment of the present disclosure.

[0065] FIG27 is a schematic diagram of the partial structure of the first metal layer, the second metal layer, and the semiconductor layer of an L-type transistor with a compensation region in one embodiment of the present disclosure.

[0066] Explanation of the accompanying drawings: AA, display area; AB, adjacent area; AH1, first auxiliary hole; AH2, second auxiliary hole; BB, peripheral area; BUF, inorganic buffer layer; COML, common electrode layer; CR, channel region; CS, conductive structure; CST, storage capacitor; CST1, storage capacitor first electrode plate; CST2, storage capacitor second electrode plate; CZ, compensation area; DH, row direction; DL, data signal line; DRL, drive layer; DV, column direction; ECS, electrical contact structure; ECS1, first conductive area; ECS2, second conductive area; ECS3, third conductive area; ED, length direction; EFL, light-emitting functional layer; GL, scan signal line; GI, gate insulating layer; GIS, overlapping insulating structure; GIH, overlapping via; GIV, sensing via; GS, scan signal; GT, first Two metal layers; ITO1, transparent conductive layer; LE, length direction; OE, open edge; OS, overlap structure; PDC, pixel driving circuit; PDL, pixel definition layer; PEL, pixel electrode layer; PE, pixel electrode; PIXL, pixel layer; PIX, sub-pixel; PLN, planarization layer; PNL, display panel; PVX, passivation layer; PR, photoresist layer; SBT, substrate; SCL, semiconductor layer; SHL, first metal layer; SL, sensing signal line; T1, first transistor; T1CR, first transistor channel region; T2, second transistor; T3, third transistor; T3CR, third transistor channel region; TFT, transistor; VDD, driving power supply voltage; VDDL, driving power supply voltage signal line; VSS, reference power supply voltage; UU, display unit. DETAILED DESCRIPTION

[0067] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0068] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0069] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0070] In an embodiment of the present disclosure, a transistor has an active layer. The active layer is located in a semiconductor layer and includes a channel region and a source and a drain located on both sides of the channel region. The channel region maintains semiconductor properties, and the source and the drain are partially or fully conductive. In an embodiment of the present disclosure, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In an embodiment of the present disclosure, for any transistor, one of the "first pole" and the "second pole" is referred to as the source of the transistor, and the other is referred to as the drain of the transistor.

[0071] In the disclosed embodiments, the channel region of the transistor has a length direction and a width direction. The length direction of the channel region of the transistor refers to the direction in which current primarily flows, and the width direction of the channel region of the transistor is perpendicular to the direction in which current flows. Along the length direction of the channel region of the transistor, the active layer of the transistor sequentially includes the first electrode of the transistor, the channel region, and the second electrode.

[0072] An embodiment of the present disclosure provides a display panel PNL. Referring to FIG. 1 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. Within the display area AA, the display panel PNL is provided with an array of display units UU. The display units UU include sub-pixels PIX and pixel driver circuits PDC that drive the sub-pixels PIX. The display panel PNL does not include display units UU in the peripheral area BB, or the display units UU that are provided are not used for displaying images. Referring to FIG. 1 , the display panel PNL is provided with a plurality of scan signal lines GL extending along a row direction DH in the display area AA. Each scan signal line GL is provided in a one-to-one correspondence with each display unit row. The pixel driver circuit PDC of each display unit UU in a display unit row is electrically connected to the corresponding scan signal line GL. The display panel PNL is also provided with a plurality of data signal lines DL extending along a column direction DV in the display area AA. Each data signal line DL is provided in a one-to-one correspondence with each display unit column. The pixel driver circuit PDC of each display unit UU in a display unit column is electrically connected to the corresponding data signal line DL. In this way, the pixel driving circuit PDC of each display unit UU is connected to a scanning signal line GL and a data signal line DL. When a scanning signal is applied to the scanning signal line GL, the driving voltage applied to the data signal line DL can be written into the pixel driving circuit PDC, thereby allowing the pixel driving circuit PDC to control the brightness of the sub-pixel PIX according to the written driving voltage.

[0073] Optionally, the pixel driving circuit PDC includes at least a data writing transistor, a driving transistor and a storage capacitor CST, and the gate of the driving transistor can be electrically connected to an electrode plate of the storage capacitor CST. The source of the data writing transistor can be electrically connected to the data signal line DL, and the gate of the data writing transistor can be electrically connected to the scanning signal line GL. The pixel driving circuit PDC is configured so that when the scanning signal GS is loaded on the scanning signal line GL, the data writing transistor is turned on, thereby causing the driving voltage on the data signal line DL to be written into the gate of the driving transistor and the storage capacitor CST. When the data writing transistor is turned off, the driving voltage can be maintained by the storage capacitor CST. The driving transistor can output a driving current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It can be understood that the pixel driving circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors so that the pixel driving circuit PDC has better driving performance. For example, the pixel driving circuit PDC may be a 7T1C (seven transistors TFT and one storage capacitor CST), an 8T1C (eight transistors TFT and one storage capacitor CST) or a pixel driving circuit PDC of other architectures.

[0074] In an embodiment of the present disclosure, the sub-pixels PIX in the display panel PNL are current-driven self-luminous elements, such as thin-film self-luminous light-emitting elements. For example, the sub-pixels PIX are OLED, PLED, QLED, etc. Further, the sub-pixels PIX located in the display area AA include sub-pixels PIX of multiple different colors. For example, the sub-pixels PIX include red sub-pixels for emitting red light, green sub-pixels for emitting green light, and blue sub-pixels for emitting blue light. It is understandable that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA may also be sub-pixels PIX of only one color, or may also have sub-pixels PIX of other colors (for example, yellow sub-pixels for emitting yellow light, cyan sub-pixels for emitting cyan light, white sub-pixels for emitting white light, etc.).

[0075] In one embodiment of the present disclosure, referring to FIG2 , a display panel PNL may include a base substrate SBT, a drive layer DRL, and a pixel layer PIXL, which are stacked in sequence. The pixel layer PIXL includes subpixels PIX, and the drive layer DRL includes a pixel drive circuit PDC for driving the subpixels PIX. Each subpixel PIX can emit light to display an image under the drive of the pixel drive circuit PDC.

[0076] Optionally, the base substrate SBT can be a base substrate of an inorganic material, or a base substrate of an organic material; of course, it can also be a composite substrate formed by stacking a base substrate of an inorganic material and a base substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the base substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the base substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the base substrate SBT can also be a flexible base substrate, for example, the material of the base substrate SBT can include polyimide.

[0077] Optionally, in the drive layer DRL, any pixel drive circuit PDC may include a transistor TFT and a storage capacitor CST. Furthermore, the transistor TFT may be selected from a top-gate transistor, a bottom-gate transistor, or a dual-gate transistor; the active layer of the transistor TFT may be made of an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; and the transistor TFT may be an N-type transistor or a P-type transistor.

[0078] In one example, the transistors in the driving layer DRL are top-gate transistors.

[0079] In one example, the transistors in the driving layer DRL are metal oxide transistors.

[0080] As an example, referring to FIG2 , the driving layer DRL may include a first metal layer SHL, an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a second metal layer GT and a planarization layer PLN stacked in sequence, and the transistor TFT formed in this way is a top-gate transistor.

[0081] In this embodiment, at least a portion of the first metal layer SHL can function as a light-shielding structure, shielding the channel region CR of the transistor to prevent light from the substrate from reaching the channel region CR and altering transistor characteristics. For example, the orthographic projection of the transistor channel region CR on the substrate SBT is within the orthographic projection of the first metal layer SHL on the substrate SBT.

[0082] Furthermore, referring to FIG. 2 , the first metal layer SHL is connected to the second metal layer GT through vias.

[0083] Furthermore, referring to FIG. 2 , the driving layer DRL further includes a passivation layer PVX located on a side of the second metal layer GT away from the substrate SBT, and a planarization layer PLN is located on a side of the passivation layer PVX away from the substrate SBT.

[0084] In one embodiment of the present disclosure, referring to FIG2 , the driving layer DRL is further provided with a transparent conductive layer ITO1, and the transparent conductive layer ITO1 is used to form an electrode plate of the storage capacitor CST (for example, the second electrode plate CST2 of the storage capacitor), and the semiconductor layer SCL is used to form another electrode plate of the storage capacitor CST (for example, the first electrode plate CST1 of the storage capacitor). In this way, the storage capacitor CST is a transparent storage capacitor. Furthermore, the light emitted by the sub-pixel PIX can be emitted through the transparent storage capacitor, so that the display panel PNL is a bottom-emitting display panel PNL. Furthermore, the transparent conductive layer ITO1 is located between the first metal layer SHL and the base substrate SBT. Specifically, when preparing the display panel PNL, the transparent conductive layer ITO1 can be formed first, and then the first metal layer SHL can be formed.

[0085] Optionally, the material of the transparent conductive layer ITO1 may be a transparent conductive metal oxide, such as indium tin oxide.

[0086] Optionally, the material of the first metal layer SHL may be metal. For example, the first metal layer SHL includes one metal layer or multiple stacked metal layers.

[0087] Optionally, when the transparent conductive layer ITO1 is electrically connected to the first metal layer SHL, a portion of the structure of the first metal layer SHL is directly overlapped on the transparent conductive layer ITO1.

[0088] In the example of Figure 2 , the subpixels PIX in the pixel layer PIXL are thin-film light-emitting elements. The pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML stacked in sequence. The pixel electrode layer PEL includes multiple pixel electrodes PE in the display area of ​​the display panel. The pixel electrodes PE are electrically connected to the pixel driving circuit PDC through vias.

[0089] Furthermore, the pixel layer PIXL may further include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, and any pixel opening exposes at least a portion of the corresponding pixel electrode PE.

[0090] In one example, the pixel electrode serves as an anode of the sub-pixel PIX, and the common electrode layer COML serves as a cathode of the sub-pixel PIX.

[0091] Optionally, the common electrode layer COML is a reflective electrode rather than a transparent electrode, such as a metal electrode or a metal oxide electrode. The pixel electrode PE is a transparent electrode, such as a material of a transparent conductive metal oxide (such as indium tin oxide). In this way, the sub-pixel PIX is a bottom-emitting sub-pixel.

[0092] In one example, the common electrode layer COML may be a metal electrode layer, such as a silver metal layer, an aluminum metal layer, a titanium metal layer, or other metal layer with high reflectivity. Of course, when necessary, the surface of the metal electrode layer may also be modified with an alloy, a metal oxide, a metal nitride, or other materials to adjust the carrier injection characteristics (e.g., electron injection characteristics) of the metal electrode layer. For example, the common electrode layer COML is made of aluminum and has a thickness of 100 nanometers.

[0093] In one embodiment of the present disclosure, referring to FIG3 , the pixel driving circuit PDC in the driving layer DRL is a 3T1C circuit, i.e., it includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor CST. The first electrode of the first transistor T1 is electrically connected to a driving power supply voltage signal line VDDL for loading a driving power supply voltage VDD; the gate of the first transistor T1 is electrically connected to a second electrode of the second transistor T2 and a first electrode plate CST1 of the storage capacitor; the second electrode of the first transistor T1 is electrically connected to a second electrode of the third transistor T3, a pixel electrode PE of a sub-pixel PIX, and a second electrode plate CST2 of the storage capacitor; the first electrode of the third transistor T3 is electrically connected to a sensing signal line SL for loading a reference power supply voltage VSS; the first electrode of the second transistor T2 is electrically connected to a data signal line DL for loading a data voltage; and the gates of the second transistor T2 and the third transistor T3 are used to load a scan signal GS.

[0094] Optionally, the driving power supply voltage signal line VDDL is provided on the first metal layer SHL. Optionally, the driving power supply voltage signal line VDDL extends along the column direction DV.

[0095] Optionally, the data signal line DL is provided on the first metal layer SHL. Optionally, the data signal line DL extends along a column direction DV.

[0096] In one example, the gate of the second transistor T2 and the gate of the third transistor T3 are electrically connected to the scanning signal line GL for applying the scanning signal GS, thereby reducing the number of scanning signal lines, saving layout space, and improving the resolution of the display panel PNL.

[0097] It is understood that in each example of the present disclosure, the gate of the second transistor T2 and the gate of the third transistor T3 are connected to the same scan signal line. In other embodiments of the present disclosure, the display panel may also be provided with two scan signal lines to drive the second transistor and the third transistor respectively. For example, the display panel may be provided with a first scan signal line extending along the row direction and a second scan signal line extending along the row direction; the first scan signal line is used to load a first scan signal, and the second scan signal line is used to load a second scan signal; the gate of the second transistor is electrically connected to the first scan signal line, and the gate of the third transistor is electrically connected to the second scan signal line.

[0098] Optionally, the scan signal line GL is located in the second metal layer GT. Optionally, the scan signal line GL extends along the row direction DH. Meanwhile, the second metal layer GT also includes the gate of each transistor.

[0099] In one example, the sensing signal line SL is located in the first metal layer SHL, and the sensing signal line SL is configured to provide a sensing signal to the pixel driving circuit PDC. Optionally, the sensing signal line SL extends along the column direction DV.

[0100] In one example, the second electrode plate CST2 of the storage capacitor is located on the transparent conductive layer ITO1.

[0101] In one example, the storage capacitor first electrode plate CST1 is located on the semiconductor layer SCL.

[0102] In an embodiment of the present disclosure, referring to FIG2 , at least one transistor TFT includes a channel region CR located in a semiconductor layer SCL and two conductive structures CS located on either side of the channel region CR. It will be appreciated that the transistor TFT further includes a gate located in a second metal layer GT and a gate insulating structure (located in a gate insulating layer GI) between the gate and the channel region CR.

[0103] In the embodiment of the present disclosure, the conductive structure CS of the transistor TFT can be selected from any one of three types: a first conductive structure, a second conductive structure, and a third conductive structure, as needed. The two conductive structures CS of the transistor TFT can be of the same type or different types.

[0104] FIG4 is a schematic structural diagram of the first conductive structure, FIG5 is a schematic structural diagram of the overlapping insulation structure GIS of the first conductive structure, and FIG6 is a schematic structural diagram of a partial cross-section of the first conductive structure.

[0105] 4 to 6 , the first conductive structure includes an electrical contact structure ECS located in the semiconductor layer SCL, an overlapping insulating structure GIS located in the gate insulating layer GI, and an overlapping structure OS located in the second metal layer GT. The overlapping insulating structure GIS has an overlapping via GIH, and the overlapping structure OS is electrically connected to the electrical contact structure ECS through the overlapping via GIH. In the first conductive structure, the electrical contact structure ECS and the channel region CR are both located in the semiconductor layer SCL and are adjacent to each other. The electrical contact structure ECS and the channel region CR together serve as part of the active layer of the transistor TFT. The electrical contact structure ECS can serve as the source or drain of the transistor TFT, and the overlapping structure OS is electrically connected to the electrical contact structure ECS through the overlapping via GIH, so that the source or drain of the transistor is electrically connected to the second metal layer GT.

[0106] FIG7 is a schematic structural diagram of the second conductive structure, FIG8 is a schematic structural diagram of the overlapping insulation structure GIS of the second conductive structure, and FIG9 is a schematic structural diagram of a partial cross-section of the second conductive structure.

[0107] Referring to Figures 7 to 9, the second conductive structure includes an electrical contact structure ECS located in the semiconductor layer SCL, an overlapping insulation structure GIS located in the gate insulation layer GI, and an overlapping structure OS located in the second metal layer GT. In addition, the second conductive structure overlaps with the inorganic buffer layer BUF and the first metal layer SHL. The overlapping insulation structure GIS has an overlapping via GIH, which includes a main via that exposes the semiconductor layer SCL and a first auxiliary hole AH1 outside the area where the semiconductor layer SCL is located that can expose the first metal layer SHL. The main via and the first auxiliary hole AH1 are arranged adjacent to each other. The inorganic buffer layer BUF has a second auxiliary hole AH2 aligned with the first auxiliary hole AH1; the first auxiliary hole AH1 and the second auxiliary hole AH2 expose at least a portion of the first metal layer SHL. The overlapping structure OS is electrically connected to the electrical contact structure ECS through the main via of the overlapping via GIH. The overlapping structure OS is also electrically connected to the first metal layer SHL through the first auxiliary via AH1 and the second auxiliary via AH2 of the overlapping via GIH. In this second conductive structure, the electrical contact structure ECS and the channel region CR are both located adjacent to each other in the semiconductor layer SCL. Together, the electrical contact structure ECS and the channel region CR serve as part of the active layer of the transistor TFT. The electrical contact structure ECS can serve as the source or drain of the transistor TFT. The overlapping structure OS is electrically connected to the electrical contact structure ECS and to the first metal layer SHL through the vias, thereby electrically connecting the source or drain of the transistor to the first metal layer SHL.

[0108] Figure 10 is a schematic diagram of a third conductive structure. Referring to Figure 10 , this third conductive structure includes an electrical contact structure ECS located on the semiconductor layer SCL. This electrical contact structure ECS is electrically connected to the second metal layer GT or the first metal layer SHL without requiring vias. This electrical contact structure ECS and the channel region CR are both located adjacent to each other on the semiconductor layer SCL and together serve as part of the active layer of the transistor TFT.

[0109] In an embodiment of the present disclosure, at least one conductive structure CS is selected from the first conductive structure or the second conductive structure, so that the source or drain of the transistor is electrically connected to other conductive film layers (eg, the second metal layer GT or the first metal layer SHL).

[0110] 11 to 13 take the first conductive structure as an example to exemplarily introduce the preparation process of some film layers of the display panel PNL.

[0111] Referring to FIG. 11 , when preparing the display panel PNL, a patterned semiconductor layer SCL can be first prepared, followed by the gate insulating layer GI. When preparing the gate insulating layer GI, a full layer of the gate insulating layer GI can be deposited first, and then a via can be formed in the full layer of the gate insulating layer GI. In the example via shown in FIG. 11 , the via includes an overlapping via GIH and an adjacent via adjacent to the overlapping via GIH. The overlapping via GIH and the adjacent via are two parts of a single via. The via exposes at least a portion of the semiconductor layer SCL. The area of ​​the semiconductor layer SCL exposed by the overlapping via GIH is the overlapping area, and the area of ​​the semiconductor layer SCL exposed by the adjacent via is the adjacent area AB. After the via is formed in the full layer of the gate insulating layer GI, the exposed semiconductor layer SCL is conductively conductively formed using ion implantation. This results in conductively conductively forming both the overlapping area and the adjacent area AB of the semiconductor layer SCL, while the portion of the semiconductor layer SCL covered by the gate insulating layer GI remains unconductively conductive. Referring to FIG. 12 , a second metal layer GT is then formed. For example, a whole second metal layer GT is formed on the side of the second metal layer GT away from the semiconductor layer SCL, and then the whole second metal layer GT is patterned using a photolithography process. For example, in the example of FIG12 , a photoresist layer PR serving as a mask is still retained on the second metal layer GT. Referring to FIG12 , when the second metal layer GT is formed, the second metal layer GT covers the overlapping area and exposes the adjacent area AB. In other words, in the via formed by the whole gate insulating layer GI, the portion that exposes the semiconductor layer SCL and is covered by the second metal layer GT is the overlapping via GIH, and the portion that exposes the semiconductor layer SCL and is not covered by the second metal layer GT is the adjacent via. Referring to FIG13 , the gate insulating layer GI having the via is patterned using the second metal layer GT as a mask (or using the photoresist layer PR that defines the pattern of the second metal layer GT as a mask). For example, the gate insulating layer GI not covered by the mask (the second metal layer GT or the photoresist layer PR) is removed by etching. This allows the semiconductor layer SCL that does not overlap with the mask to be exposed; the exposed semiconductor layer SCL is then conductively implanted by ion implantation. During this process, the channel region CR of the transistor is protected by the gate of the transistor, thus maintaining semiconductor characteristics.

[0112] In this first conductive structure, the overlapping structure OS located on the second metal layer GT only partially overlaps with the electrical contact structure ECS located on the semiconductor layer SCL. The overlapping area and the adjacent area AB of the electrical contact structure ECS are conductorized during the first conductorization process, and the portion of the electrical contact structure ECS not covered by the overlapping structure OS is conductorized during the second conductorization process. Therefore, referring to Figure 14, the electrical contact structure ECS has a conductorized conductive path, which includes the overlapping area, the adjacent area AB, and the remaining portion not covered by the second metal layer GT (as shown by the arrow). The edge of the overlapping structure OS defines the boundary between the overlapping area and the adjacent area AB, which enables the overlapping area to maintain electrical communication with the remaining conductive path through the adjacent area AB.

[0113] Therefore, referring to Figures 5 and 14 , the overlapping via GIH of the overlapping insulating structure GIS of the first conductive structure extends to the edge of the overlapping insulating structure, forming an open structure (a non-enclosed via), and the open edge OE of the overlapping via GIH is flush with at least one edge of the overlapping structure OS. Furthermore, referring to Figure 13 , during the patterning of the gate insulating layer GI using the second metal layer GT as a mask, the semiconductor layer SCL in the adjacent region AB may be damaged during etching because it is not covered by the gate insulating layer GI. For example, the portion of the semiconductor layer SCL located in the adjacent region AB may be thinned or even partially etched through. Therefore, in the first conductive structure CS, the thickness of the semiconductor layer SCL in the adjacent region AB may be less than the thickness of the semiconductor layer SCL in the channel region CR.

[0114] In one example, in at least one first conductive structure, the thickness of the semiconductor layer SCL in the adjacent area AB is smaller than the thickness of the semiconductor layer SCL in the channel region CR.

[0115] The preparation process for the second conductive structure is similar to that for the first. During the preparation of the display panel PNL, a first metal layer SHL and an inorganic buffer layer BUF are prepared before the semiconductor layer SCL. During the preparation of the semiconductor layer SCL, the semiconductor layer SCL is partially overlapped with the first metal layer SHL. For example, the electrical contact structure ECS of the second conductive structure CS is partially overlapped with the first metal layer SHL to be connected. The first metal layer SHL is required to partially protrude beyond the electrical contact structure ECS. The portion that is spatially adjacent to but does not overlap with the electrical contact structure ECS can be referred to as the protrusion of the first metal layer SHL. After the entire gate insulation layer GI is prepared, a via is formed. In the region where the second conductive structure is located, the via of the gate insulation layer GI includes two sequentially connected portions: an adjacent via and an overlapping via GIH. Unlike the first conductive structure, the overlapping via GIH of the second conductive structure includes a main via that exposes the semiconductor layer SCL and a first auxiliary via AH1 that is located outside the region where the semiconductor layer SCL is located and exposes the first metal layer SHL. Furthermore, during the via formation process, overetching can be performed so that the inorganic buffer layer BUF continues to be etched downward in the area where the first auxiliary hole AH1 is located to form a second auxiliary hole AH2 that exposes the protrusion of the first metal layer SHL. Therefore, in the second conductive structure, the boundary between the main via of the overlapping via GIH and the first auxiliary hole AH1 is essentially an edge of the electrical contact structure ECS. When forming the second metal layer GT, the overlapping structure OS of the second conductive structure CS is electrically connected to the electrical contact structure ECS through the main via, and electrically connected to the first metal layer SHL through the first auxiliary hole AH1 and the second auxiliary hole AH2. Similar to the first conductive structure, the overlapping via GIH of the second conductive structure is an open structure, and the open edge OE of the overlapping via GIH is flush with at least one edge of the overlapping structure OS. Referring to FIG. 15 , similar to the first conductive structure, the electrical contact structure ECS of the second conductive structure is also formed with a conductive conductive channel.

[0116] In one example, the via formed in the gate insulation layer GI before the first conductorization is an elongated hole, such as a rectangular hole; the length direction of the elongated hole corresponds to the direction of the opening of the overlapping via GIH. Furthermore, the overlapping via GIH is rectangular, and the length direction of the overlapping via GIH corresponds to the length direction ED of the overlapping via GIH. This ensures the size of the overlapping area to reduce contact resistance, and ensures the presence of the adjacent area AB to ensure the stability of the conductive path.

[0117] In an example, since the gate insulating layer GI is patterned using the second metal layer GT as a mask, the orthographic projection of the gate insulating layer GI on the base substrate SBT does not exceed the orthographic projection of the second metal layer GT on the base substrate SBT.

[0118] In one example, at least one electrical contact structure ECS has an adjacent region AB exposed by the gate insulation layer GI and the second metal layer GT and adjacent to the overlapping via GIH. The thickness of the semiconductor layer SCL in the adjacent region AB is less than the thickness of the semiconductor layer SCL in the channel region CR. For example, the adjacent region AB of a portion of the electrical contact structure ECS may be overetched and thinned during the etching process of the gate insulation layer, or even partially etched through.

[0119] In the related art, referring to Figures 16 and 20, the conductive structure CS of the transistor adopts the first conductive structure or the second conductive structure, and the length direction ED of the two overlapping vias GIH of the transistor TFT is parallel to the length direction LE of the channel region CR. In the embodiment of the present disclosure, this type of transistor TFT is referred to as an I-type transistor TFT. The via connection method of the I-type transistor TFT will make the size of the transistor TFT in the length direction LE of the channel region CR too large, which will cause the overlapping structure OS to squeeze the space of other structures located in the second metal layer GT; in order to avoid excessive proximity between different structures of the second metal layer GT, the total space occupied by the second metal layer GT is relatively large, which will compress the pixel opening, resulting in a reduced aperture ratio or a reduced resolution.

[0120] In an embodiment of the present disclosure, referring to Figures 17 to 19, at least one transistor TFT is optimized; in the optimized transistor TFT, the length direction ED of at least one overlapping via GIH is not parallel to the length direction LE of the channel region CR. In one example, the length direction ED of the overlapping via GIH is the opening direction of the overlapping via GIH, and the opening direction refers to the direction of the gap of the via on the gate insulating layer GI. In an embodiment of the present disclosure, if the length direction ED of the overlapping via GIH of a conductive structure CS (the first conductive structure or the second conductive structure) is not parallel to the length direction LE of the channel region CR, then the conductive structure CS is called an L-type conductive structure.

[0121] In the disclosed embodiments, when designing a layout for a high-PPI bottom-emitting OLED device, utilizing a via connection method in which the length direction ED of the overlapping via GIH is non-parallel to the length direction LE of the channel region CR can save layout space. In particular, the size of the transistor along the length direction LE of the channel region CR can be reduced, thereby making the layout design of the OLED device more rational, improving the utilization of the layout space, and enhancing the display quality of the OLED device. In other words, by employing an L-shaped conductive structure for at least one transistor TFT of the pixel driver circuit PDC in the display panel PNL of the disclosed embodiments, space utilization can be improved and the layout area of ​​the pixel driver circuit PDC can be reduced, thereby improving the PPI of the display panel.

[0122] The transistor TFT of the display panel PNL provided by the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings:

[0123] In one embodiment of the present disclosure, referring to Figures 21 and 22, the length direction ED of a bridging via GIH of at least one transistor TFT is perpendicular to the length direction LE of the channel region CR of the transistor TFT. Thus, only one conductive structure CS of the transistor TFT is an L-shaped conductive structure, and the transistor is a single-sided L-shaped transistor TFT, which can achieve increased space utilization. The other conductive structure CS of the transistor TFT can be the third conductive structure, or the first conductive structure, or the second conductive structure, and the length direction ED of the bridging via GIH can be parallel to the length direction LE of the channel region CR of the transistor TFT.

[0124] In another embodiment of the present disclosure, referring to Figures 23 and 24, the length direction ED of the two overlapping via holes GIH of at least one transistor TFT is perpendicular to the length direction LE of the channel region CR of the transistor TFT. In this way, the two conductive structures CS of the transistor TFT are both L-shaped conductive structures, and the transistor TFT is a double-sided L-shaped transistor TFT, which can further save space, maximize space utilization, and increase the aperture ratio. Furthermore, the transistor TFT is U-shaped.

[0125] In one embodiment of the present disclosure, referring to FIG17 , the overlapping via GIH is rectangular, and the length direction ED of the overlapping via GIH is the length direction of the overlapping via GIH. In an L-shaped conductive structure, this can reduce the size of the conductive structure CS of the transistor TFT in the length direction LE of the channel region CR and increase the size of the conductive structure CS of the transistor TFT in the width direction of the channel region CR, thereby improving space utilization.

[0126] Alternatively, as shown in FIG17 , along the length direction ED of the overlapping via GIH, the size of the adjacent area AB is smaller than the size of the overlapping via GIH. This can increase the size of the overlapping via GIH, increase the contact area between the overlapping structure OS and the electrical contact structure ECS, and reduce the contact resistance.

[0127] Alternatively, referring to Figure 17 , in an L-shaped conductive structure, the electrical contact structure ECS includes a first conductive region ECS1, a second conductive region ECS2, and a third conductive region ECS3, which are sequentially connected. The first conductive region ECS1 is located between the channel region CR and the adjacent region AB of the transistor TFT; the second conductive region ECS2 is located on the side of the adjacent region AB away from the bridging via GIH; and the third conductive region ECS3 is located on the side of the adjacent region AB away from the channel region CR. In this way, the first conductive region ECS1, the second conductive region ECS2, and the third conductive region ECS3 are sequentially connected to form a conductive channel, ensuring smooth signal transmission.

[0128] In one example, during the fabrication of the conductive structure CS, due to interlayer overlap between film layers, the initially created via in the gate insulating layer GI may shift overall in the length direction ED of the overlapping via GIH. Referring to FIG. 25 , when this via shift occurs, the adjacent region AB compresses or even isolates the second conductive region ECS2, reducing or even severing the electrical connectivity between the first conductive region ECS1 and the third conductive region ECS3. This results in a smaller conductive path, increased impedance, and impacted transistor (TFT) characteristics.

[0129] In one example, referring to Figures 26 and 27, in an L-shaped conductive structure, the electrical contact structure ECS may further include a compensation zone CZ, which is located on the side of the adjacent area AB away from the overlapping via GIH and protrudes toward the side away from the overlapping via GIH to increase the size of the second conductive area ECS2. For example, referring to Figure 26, along the length direction ED of the overlapping via GIH, the distance between the outer edge of the compensation zone CZ and the edge of the overlapping structure OS is greater than the distance between the outer edge of the first conductive area ECS1 and the edge of the overlapping structure OS. The outer edge of the compensation zone CZ refers to the edge of the compensation zone CZ that is farthest from the edge of the overlapping structure OS among the various edges. The outer edge of the first conductive area ECS1 refers to the edge of the first conductive area ECS1 that is farthest from the edge of the overlapping structure OS among the various edges. In this way, the conductive channel can be increased, avoiding poor contact caused by via offset due to interlayer overlap between film layers.

[0130] FIG26 illustrates an L-shaped conductive structure when the first via hole created in the gate insulating layer GI is offset. Referring to FIG26 , by providing a compensation zone CZ, even if the first via hole created in the gate insulating layer GI is offset, the second conductive region ECS2 is not completely isolated. FIG27 illustrates an L-shaped conductive structure in which the first via hole created in the gate insulating layer GI is not offset. Referring to FIG27 , providing a compensation zone CZ increases the width of the second conductive region ECS2, improving the process window for the second conductive region ECS2.

[0131] In one embodiment of the present disclosure, referring to Figures 3 and 19, the inorganic buffer layer BUF and the gate insulation layer GI have a sensing via GIV, and the sensing signal line SL is electrically connected to the second metal layer GT through the sensing via GIV; the first transistor T1 has a first conductive structure adjacent to the sensing via GIV, and the length direction ED of the overlapping via GIH of the first conductive structure is perpendicular to the first transistor channel region T1CR.

[0132] The first transistor T1 has a first conductive structure, and the length direction ED of the overlapping via GIH of the first conductive structure of the first transistor T1 is perpendicular to the first transistor channel region T1CR. The first transistor T1 is L-shaped, thereby improving space utilization and realizing device layout. Each transistor TFT can emit light under the drive of the pixel driving circuit PDC.

[0133] Optionally, referring to FIG. 19 , the length direction ED of the overlapping via hole GIH of the first conductive structure is the row direction DH; and the length direction LE of the first transistor channel region T1CR is the column direction DV.

[0134] In another embodiment of the present disclosure, referring to Figures 3 and 18, the inorganic buffer layer BUF and the gate insulation layer GI have a sensing via GIV, and the sensing signal line SL is electrically connected to the second metal layer GT through the sensing via GIV; the third transistor T3 has a second conductive structure adjacent to the sensing via GIV, and the length direction ED of the overlapping via GIH of the second conductive structure is arranged perpendicular to the channel region T3CR of the third transistor.

[0135] The third transistor T3 has a second conductive structure, and the length direction ED of the overlapping via GIH of the second conductive structure of the third transistor T3 is perpendicular to the third transistor channel region T3CR. The third transistor T3 is L-shaped, thereby improving space utilization and realizing device layout. Each transistor TFT can emit light under the drive of the pixel driving circuit PDC.

[0136] Optionally, referring to FIG. 18 , the length directions ED of the overlapping vias GIH of the two conductive structures CS of the third transistor T3 are both in the column direction DV; and the length direction LE of the channel region T3CR of the third transistor is in the row direction DH.

[0137] The present disclosure also provides a display device comprising any of the display panels described in the display panel embodiments above. The display device may be a smartphone screen, a smartwatch screen, or another type of display device. Because the display device comprises any of the display panels described in the display panel embodiments above, it exhibits the same beneficial effects, and the present disclosure will not elaborate further here.

[0138] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: The display panel comprises a base substrate, a driving layer and a pixel layer which are sequentially stacked, wherein the driving layer has a transistor for driving a sub-pixel; the driving layer comprises a first metal layer, a semiconductor layer, a gate insulating layer, a second metal layer and a planarization layer which are sequentially stacked on the base substrate; At least one of the transistors includes a channel region located in the semiconductor layer, and two conductive structures located on both sides of the channel region; at least one of the conductive structures includes an electrical contact structure located in the semiconductor layer, a lapped insulating structure located in the gate insulating layer, and a lapped structure located in the second metal layer; The overlapping insulating structure has an overlapping via, and the overlapping structure is electrically connected to the electrical contact structure through the overlapping via; Wherein, a length direction of at least one overlapping via of at least one transistor is not parallel to a length direction of a channel region of the transistor.

2. The display panel according to claim 1, characterized in that: A length direction of a bridging via hole of the at least one transistor is perpendicular to a length direction of a channel region of the transistor.

3. The display panel according to claim 1, characterized in that: The length directions of the two overlapping vias of the at least one transistor are both perpendicular to the length direction of the channel region of the transistor.

4. The display panel according to claim 1, characterized in that: The overlapping via hole extends to the edge of the overlapping insulating structure and is an open structure; the length direction of the overlapping via hole is the open direction of the overlapping via hole.

5. The display panel according to claim 1, characterized in that: The orthographic projection of the gate insulating layer on the base substrate does not exceed the orthographic projection of the second metal layer on the base substrate.

6. The display panel according to claim 5, characterized in that: At least one of the electrical contact structures has an adjacent region exposed by the gate insulating layer and the second metal layer and adjacent to the overlapping via, and a thickness of the semiconductor layer in the adjacent region is smaller than a thickness of the semiconductor layer in the channel region.

7. The display panel according to claim 6, characterized in that: Along the length direction of the overlapping via hole, the size of the adjacent area is smaller than the size of the overlapping via hole.

8. The display panel according to claim 6, characterized in that: The electrical contact structure comprises a first conductive region, a second conductive region and a third conductive region connected in sequence; The first conductive region is located between the channel region of the transistor and the adjacent region; the second conductive region is located on a side of the adjacent region away from the overlapping via; and the third conductive region is located on a side of the adjacent region away from the channel region.

9. The display panel according to claim 1, characterized in that: The driving layer further includes a first metal layer and an inorganic buffer layer located between the base substrate and the semiconductor layer; the inorganic buffer layer is located between the first metal layer and the semiconductor layer; the first metal layer and the second metal layer are connected through vias.

10. The display panel according to claim 9, characterized in that: At least one of the overlapping vias further comprises a first auxiliary hole covered by the overlapping structure and extending beyond the electrical contact structure; the inorganic buffer layer has a second auxiliary hole aligned with the first auxiliary hole; The first auxiliary hole and the second auxiliary hole expose at least a portion of the first metal layer; The overlapping structure is electrically connected to the first metal layer through the first auxiliary hole and the second auxiliary hole.

11. The display panel according to claim 9, characterized in that: The driving layer has a pixel driving circuit for driving the pixel layer, the pixel driving circuit includes a storage capacitor, a first transistor, a second transistor and a third transistor, wherein the transistor includes a gate, a first electrode and a second electrode; The first electrode of the first transistor is used to load the driving power supply voltage, the gate of the first transistor is electrically connected to the second electrode of the second transistor and the first electrode plate of the storage capacitor, the second electrode of the first transistor is electrically connected to the second electrode of the third transistor, the pixel electrode of the sub-pixel, and the second electrode plate of the storage capacitor, and the first electrode of the third transistor is electrically connected to the sensing signal line; the first electrode of the second transistor is used to load the data voltage; The gate of the second transistor and the gate of the third transistor are used to load a scan signal; The inorganic buffer layer and the gate insulating layer have sensing vias, and the sensing signal line is electrically connected to the second metal layer through the sensing vias; The first transistor has a first conductive structure adjacent to the sensing via, and a length direction of the lapped via of the first conductive structure is perpendicular to a channel region of the first transistor.

12. The display panel according to claim 11, characterized in that: The length direction of the overlapping vias of the first conductive structure is the row direction; The length direction of the first transistor channel region is the column direction.

13. The display panel according to claim 9, characterized in that: The driving layer has a pixel driving circuit for driving the pixel layer, the pixel driving circuit includes a storage capacitor, a first transistor, a second transistor and a third transistor, wherein the transistor includes a gate, a first electrode and a second electrode; The first electrode of the first transistor is used to load the driving power supply voltage, the gate of the first transistor is electrically connected to the second electrode of the second transistor and the first electrode plate of the storage capacitor, the second electrode of the first transistor is electrically connected to the second electrode of the third transistor, the pixel electrode of the sub-pixel, and the second electrode plate of the storage capacitor, and the first electrode of the third transistor is electrically connected to the sensing signal line; the first electrode of the second transistor is used to load the data voltage; The gate of the second transistor and the gate of the third transistor are used to load a scan signal; The inorganic buffer layer and the gate insulating layer have sensing vias, and the sensing signal line is electrically connected to the second metal layer through the sensing vias; The third transistor has a second conductive structure adjacent to the sensing via, and a length direction of the overlapping via of the second conductive structure is arranged perpendicular to a channel region of the third transistor.

14. The display panel according to claim 13, characterized in that: The length directions of the overlapping vias of the two conductive structures of the third transistor are both in the column direction; The length direction of the channel region of the third transistor is the row direction.

15. A display device, comprising the display panel according to any one of claims 1 to 14.

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