Field effect transistor

Abstract

Disclosed in the present invention is a field effect transistor, comprising: a drain electrode, located on a bottom layer; a base substrate, located on the drain electrode; a first conductive semiconductor layer, located on the base substrate; a gate electrode structure, comprising a gate electrode and a gate insulating film, the gate electrode extending downwards from a first region of an upper surface of the first conductive semiconductor layer, and the gate insulating film wrapping around the entire outer surface of the gate electrode; a Schottky source electrode, located in a second region of the upper surface of the first conductive semiconductor layer; a field plate structure, comprising a field plate electrode and a dielectric layer, the field plate electrode being in contact with a lower surface of the Schottky source electrode and extending downwards, the dielectric layer wrapping around the remaining outer surface of the field plate electrode, and a work function of the material of the field plate electrode being greater than that of the material of the first conductive semiconductor layer; and an ohmic source electrode, located in a third region of the upper surface of the first conductive semiconductor layer, wherein the first region and the second region on the upper surface of the first conductive semiconductor layer are not connected. According to the present invention, the conduction loss of field effect transistors can be reduced.

Description

A field-effect transistor Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a field effect transistor. Background Art

[0002] The Schottky source-drain MOSFET structure, first proposed in the 1960s, replaces the semiconductor-doped source and drain of traditional pn-junction MOSFETs with metal sources and drains, forming a Schottky contact barrier between the metal source and drain and the semiconductor. When a positive voltage is applied between the drain and source, the Schottky barrier formed between the source and the semiconductor material is reverse-biased, widening the depletion layer and achieving shutdown. Consequently, the Schottky source-drain MOSFET is a normally-off device. Turning on a Schottky source-drain MOSFET occurs when a positive gate bias forms a conductive channel, allowing carriers at the source to tunnel directly through the barrier and into the channel.

[0003] Compared with traditional pn junction MOSFET, Schottky source-drain MOSFET has four advantages: First, the metal Schottky contact has the characteristics of ultra-shallow junction, which can effectively suppress the short channel effect and source-drain punch-through problems that plague conventional MOSFETs when the device size is greatly reduced, providing the possibility for MOSFET to continue to reduce in size; Second, the high conductivity of the metal-semiconductor contact can further reduce the drain-source resistance; Third, there is no parasitic triode effect in Schottky source-drain MOSFET, the response speed is faster, and it can be more high-frequency; Fourth, ion implantation is not required to form the n+ or P+ source and drain regions, and high-temperature annealing is eliminated, which simplifies the process and avoids the lattice damage problem caused by ion implantation and annealing, which helps to obtain high interface quality, thereby obtaining a high-quality dielectric layer, and better voltage resistance and reliability.

[0004] However, since the birth of Schottky source-drain MOSFET, there have been two significant disadvantages: first, the on-state current is small. The on-state current of a conventional pn junction MOSFET can reach tens to hundreds of amperes, while the on-state current of a Schottky source-drain MOSFET under the same conditions can only reach milliamperes or even lower; second, the off-state leakage is large. The leakage current includes the thermal electron emission current transmitted from the source junction through the substrate and the tunneling current from the source junction.

[0005] The same problem also exists in other Schottky source-drain field-effect transistors, including but not limited to MOSFET, IGBT, various types of semiconductor thyristors, etc. Summary of the Invention

[0006] In view of this, the technical problem to be solved by the present invention is to provide a field effect transistor that can reduce the off-state leakage current of the Schottky source-drain field effect transistor at least to a certain extent.

[0007] To solve the above technical problems, the present invention provides a field effect transistor embodiment and technical solution as follows:

[0008] A field effect transistor, comprising:

[0009] a drain electrode, located at the bottom layer of the field effect transistor;

[0010] a substrate, located on the drain electrode;

[0011] A first conductive semiconductor layer is located on the substrate;

[0012] a gate electrode structure comprising a gate electrode and a gate insulating film, wherein the gate electrode extends downward from a first region on the upper surface of the first conductive type semiconductor layer, and the gate insulating film wraps around the entire outer surface of the gate electrode;

[0013] a Schottky source electrode, located in the second region of the upper surface of the first conductive type semiconductor layer and forming a Schottky contact with the first conductive type semiconductor layer;

[0014] a field plate structure comprising a field plate electrode and a dielectric layer, wherein the field plate electrode contacts the lower surface of the Schottky source electrode and extends downward, the dielectric layer wraps around the remaining outer surface of the field plate electrode, and the work function of the field plate electrode material is greater than the work function of the first conductive type semiconductor layer material;

[0015] an ohmic source electrode, located on the third region of the upper surface of the first conductive type semiconductor layer and forming an ohmic contact with the first conductive type semiconductor layer;

[0016] The first region and the second region on the upper surface of the first conductive type semiconductor layer are not connected.

[0017] Preferably, the material of the first conductive semiconductor layer is n-type.

[0018] Preferably, the width of the first conductive semiconductor layer between the Schottky source electrode and the gate electrode is in the range of 3 nm to 200 nm.

[0019] Preferably, the Schottky source electrode and the ohmic source electrode correspond to different metals or alloys.

[0020] Preferably, the gate electrode includes: a shielding gate electrode located at a lower portion and a groove gate electrode located at an upper portion, and a dielectric layer is provided between the groove gate electrode and the shielding gate electrode.

[0021] Preferably, the depth to which the field plate structure extends into the first conductive type semiconductor layer does not exceed the depth to which the gate electrode structure extends into the first conductive type semiconductor layer.

[0022] Preferably, the field effect transistor is composed of field effect transistor units configured in strip cells; or the field effect transistor is composed of field effect transistor units configured in closed cells.

[0023] Preferably, the field plate electrode material is metal, alloy or a second conductivity type electrode material, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, and the second conductivity type is different from the first conductivity type.

[0024] Preferably, the conductivity type of the first conductive type semiconductor layer is the first conductive type, the conductivity type of the base substrate is also the first conductive type, and the field effect transistor is a MSOFET.

[0025] Preferably, the conductivity type of the first conductive semiconductor layer is a first conductive type, the conductivity type of the base substrate is a second conductive type, the first conductive type is opposite to the second conductive type, and the field effect transistor is an IGBT.

[0026] In view of the above invention contents, the present invention has the following beneficial effects:

[0027] (1) The field effect transistor of the embodiment of the present invention adjusts the pure Schottky source to a combination of an ohmic source and a Schottky source. While maintaining the normally-off design of the device, the problem of low on-state current of the Schottky source-drain field effect transistor can be solved, the current carrying capacity of the Schottky source-drain field effect transistor can be improved, and the on-resistance of the channel region can be reduced, thereby reducing the conduction loss of the device.

[0028] (2) The field effect transistor of the embodiment of the present invention is provided with a field plate structure connected to the first portion of the source electrode below. The introduction of the field plate structure can increase the lateral depletion effect on the carriers in the drift region. Thus, when the carrier concentration in the drift region is increased, the voltage withstand capability of the device can be maintained unchanged due to the lateral depletion effect of the field plate structure. Increasing the carrier concentration in the drift region can reduce the on-resistance of the drift region, thereby further reducing the conduction loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a vertical cross-sectional view of an embodiment of a conventional Schottky source-drain MOSFET;

[0030] FIG2 is a vertical cross-sectional view of an embodiment of a MOSFET proposed by the present applicant in Chinese patent application No. 202310325051.0;

[0031] FIG. 3 is a vertical cross-sectional view of a specific embodiment of a field effect transistor of the present invention.

[0032] The technical features corresponding to the marks in the figure are:

[0033] 11 Drain electrode

[0034] 12a Ohmic source electrode

[0035] 12b Schottky source electrode

[0036] 12c Surface source electrode

[0037] 13 Gate electrode

[0038] 13a Recessed gate electrode

[0039] 13b Shielding gate electrode

[0040] 14 p-type polysilicon electrode

[0041] 21a n+ type semiconductor layer

[0042] 21b n-type semiconductor layer

[0043] 51a Gate insulating film

[0044] 51b dielectric layer DETAILED DESCRIPTION

[0045] To more clearly illustrate the technical solution of the present invention, the following will be briefly introduced through embodiments or descriptions of the prior art. Obviously, the following drawings are only illustrative of some embodiments of the present invention, and the scope of protection claimed by the present invention is not limited to the embodiments. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0046] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0047] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0049] In the present invention, unless otherwise specified, directional words such as "up, down, left, right" etc. are usually used with reference to the directions shown in the drawings, or with reference to the vertical, perpendicular or gravity directions of the components themselves; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above directional words are not used to limit the present invention.

[0050] It should be noted that the field-effect transistor structure of the present invention is universal, including MOSFETs, IGBTs, and various types of semiconductor thyristors. The technical solutions provided below in describing the development background of the field-effect transistor of the present invention are described using MOSFETs as a representative example. It should be understood that these solutions can also be expanded and applied to other types of field-effect transistors, such as IGBTs and various types of semiconductor thyristors.

[0051] Figure 1 is a vertical cross-sectional view of an embodiment of a conventional Schottky source-drain MOSFET. This MOSFET comprises: a drain electrode 11; an n+-type semiconductor layer 21a; an n-type semiconductor layer 21b; a gate trench extending into the n-type semiconductor layer 21b; a gate electrode 13 located in the trench and surrounded by a gate insulating film 51a; a Schottky source electrode 12b forming a Schottky contact with the n-type semiconductor layer 21b; and a surface source electrode 12c.

[0052] In the conventional Schottky source-drain MOSFET shown in FIG1 , due to the presence of the Schottky junction formed between the Schottky source electrode 12b and the n-type semiconductor layer 21b, when only a forward voltage is applied between the drain electrode 11 and the surface source electrode 12c, the Schottky junction is reverse biased, causing the depletion region to widen, so that a complete electron conduction channel cannot be formed between the drain electrode 11 and the surface source electrode 12c, and no current flows between the drain and the source. Based on this principle, the Schottky junction MOSFET shown in FIG2 is a normally-off device; when a positive voltage is applied between the gate electrode 13 and the source electrode 12c, due to the presence of the Schottky junction between the Schottky source electrode 12b and the n-type semiconductor layer 21b ... and the depletion region to widen, and the depletion region to widen. The existence of the Schottky barrier prevents the formation of a complete and high-concentration electron conductive channel between the drain electrode 11 and the surface source electrode 12c. At this time, even when a positive voltage is applied between the drain electrode 11 and the surface source electrode 12c, the reverse-biased depletion layer of the Schottky barrier formed between the Schottky source electrode 12b and the n-type semiconductor layer 21b widens, which inhibits the transport of electron carriers. As a result, only a small number of electron carriers form current through the tunneling effect between the drain electrode 11 and the Schottky source electrode 12b, which results in the poor on-state current conduction capability of the traditional Schottky junction MOSFET, which cannot meet the application requirements of currents above the ampere level.

[0053] To this end, the applicant of this application conducted research and development, and proposed a shielded gate MOSFET with large on-state current capability in the patent application document with Chinese application number 202310325051.0. Figure 2 is a vertical cross-sectional view of an embodiment of the MOSFET in the patent application document 202310325051.0. This MOSFET has: a drain electrode 11, located at the bottom layer of the field effect transistor; an n+ type semiconductor layer 21a, located above the drain electrode 11; an n- type semiconductor layer 21b, located above the n+ type semiconductor layer 21a; a gate electrode, extending downward from the upper surface of the n- type semiconductor layer 21b, further, the gate electrode includes a shielded gate electrode 13a located at the bottom and a recessed gate electrode 13b located at the top, with a dielectric between the recessed gate electrode and the shielded gate electrode; a gate insulating film 51a, wrapped around the outer surface of the gate electrode; a Schottky source electrode 12b, recessed in the n- type semiconductor layer 21b, and forming a Schottky contact with the n- type semiconductor layer 21b; an ohmic source electrode 12a, located above the n- type semiconductor layer 21b, and forming an ohmic contact with the n- type semiconductor layer 21b; a surface source electrode 12c, located at the top layer of the field effect transistor, and having the same potential as the shielded gate electrode 13a.

[0054] It should be noted that when the priority 202311768008.8 of this application was submitted, the patent application document with Chinese application number 202310325051.0 had not yet been disclosed. The contents disclosed in the patent document and the contents introduced in this application to the patent application document cannot be used to evaluate the novelty and creativity of this application.

[0055] The MOSFET shown in Figure 2 has optimized the source electrode design. The pure Schottky source electrode 12b in the traditional Schottky source-drain MOSFET is adjusted to a combined design of an ohmic source electrode 12a and a Schottky source electrode 12b. When the voltage V GS Greater than the threshold voltage V GS（th） When the gate insulating film 51a is adjacent to the drain electrode 11, electron carriers gather in the n-type semiconductor layer 21b to form a high-concentration electron channel. Since there is no potential barrier between the ohmic source electrode 12a and the n-type semiconductor layer 21b, when a positive voltage is applied between the drain electrode 11 and the surface source electrode 12c, a complete and high-concentration electron channel is formed between the drain electrode 11 and the surface source electrode 12c, and current flows between the drain electrode 11 and the surface source electrode 12c. When the voltage V GS= 0, the Schottky barrier formed by the Schottky source electrode 12b and the n-type semiconductor layer 21b will produce a vertical and horizontal depletion effect on electron carriers. In addition, when there is a work function difference between the material of the gate electrode 13 and the material of the n-type semiconductor layer 21b (i.e., the work function of the material of the gate electrode 13 is greater than the work function of the material of the n-type semiconductor layer 21b), the gate electrode 13 will also produce a horizontal depletion effect on the electron carriers in the n-type semiconductor layer 21b. In this way, under the combined action of the Schottky source electrode 12b and the gate electrode 13, the electron carriers in the n-type semiconductor layer 21b located between the Schottky source electrode 12b and the gate electrode 13 can be completely depleted, thereby blocking the electron conduction channel between the drain electrode 11 and the surface source electrode 12c. Therefore, the MOSFET shown in Figure 2 can be a normally-off device, and can also be a normally-off device with a large on-state current capability. Compared with FIG1 , FIG2 optimizes the gate electrode 13 into a combination of a shielded gate electrode 13a at the bottom and a grooved gate electrode 13b at the top. The purpose is to introduce the shielded gate electrode 13a. When the device is in the off state, the shielded gate electrode 13a produces a lateral depletion effect on the carriers in the n-type semiconductor layer 21b. In this way, the off-state leakage of the device can be reduced and the breakdown voltage of the device can be improved.

[0056] In summary, the patent application with application number 202310325051.0 adjusts the pure Schottky source in the Schottky source-drain MOSFET to a combination design of an ohmic source and a Schottky source. While maintaining the normally-off design of the device, it can solve the problem of low on-state current of the Schottky source-drain MOSFET, improve the current-carrying capacity of the Schottky source-drain MOSFET, and reduce the on-resistance. However, in this patent application, the on-resistance is reduced by reducing the resistance of the channel region, and there is no mention of optimizing the on-resistance of the drift region. In power devices with high voltage requirements, the on-resistance of the drift region has a greater impact on the conduction loss. Therefore, seeking to reduce the on-resistance of the drift region is the key to further reducing the conduction loss of the device.

[0057] The applicant of the present application has proposed, through further research, an embodiment of the field effect transistor structure of the present application, including:

[0058] The drain electrode is located at the bottom layer of the field effect transistor;

[0059] a substrate, located on the drain electrode;

[0060] A first conductive semiconductor layer is located on the substrate;

[0061] a gate electrode structure comprising a gate electrode and a gate insulating film, wherein the gate electrode extends downward from a first region on the upper surface of the first conductive type semiconductor layer, and the gate insulating film wraps around the entire outer surface of the gate electrode;

[0062] a Schottky source electrode, located on the second region of the upper surface of the first conductive type semiconductor layer and forming a Schottky contact with the first conductive type semiconductor layer;

[0063] A field plate structure comprising a field plate electrode and a dielectric layer, wherein the field plate electrode contacts the lower surface of the Schottky source electrode and extends downward, the dielectric layer wraps around the remaining outer surface of the field plate electrode, and the work function of the field plate electrode material is greater than the work function of the first conductive type semiconductor layer material;

[0064] an ohmic source electrode, located on the third region of the upper surface of the first conductive type semiconductor layer and forming an ohmic contact with the first conductive type semiconductor layer;

[0065] The first region and the second region of the upper surface of the first conductive type semiconductor layer are not connected.

[0066] The above field effect transistor structure has the following beneficial effects:

[0067] (1) Adjusting the pure Schottky source to a combination of an ohmic source and a Schottky source can solve the problem of low on-state current of the Schottky source-drain field effect transistor while maintaining the normally-off design of the device, improve the current-carrying capacity of the Schottky source-drain field effect transistor, reduce the on-resistance of the channel region, and thus reduce the conduction loss of the device;

[0068] (2) A field plate structure connected to the first portion of the source electrode is added below the first portion. The introduction of the field plate structure can increase the lateral depletion effect on the carriers in the drift region. In this way, when the carrier concentration in the drift region is increased, the voltage withstand capability of the device can be maintained unchanged due to the lateral depletion effect of the field plate structure. Increasing the carrier concentration in the drift region can reduce the on-resistance of the drift region, thereby further reducing the conduction loss of the device.

[0069] The material of the first conductive type semiconductor layer is n-type.

[0070] Preferably, the width of the first conductive semiconductor layer between the Schottky source electrode and the gate electrode is in the range of 3 nm to 200 nm, so that the device can achieve a normally-off function and have a small off-state leakage.

[0071] Preferably, the Schottky source electrode and the ohmic source electrode correspond to different metals or alloys. For example, when the first conductive semiconductor layer is a lightly doped silicon single crystal layer, the material of the Schottky source electrode is Pt, thereby forming a higher Schottky barrier contact with the silicon single crystal layer, which can reduce the off-state leakage of the device; the material of the ohmic source electrode can be Ti or TiN, thereby forming a good ohmic contact with the silicon single crystal layer, which can reduce the on-state loss of the device.

[0072] Preferably, the gate electrode includes a shielded gate electrode located at the bottom and a recessed gate electrode located at the top, with a dielectric layer disposed between the recessed gate electrode and the shielded gate electrode. This is intended to ensure that when the field-effect transistor device is in the off state, the Schottky barrier formed by the Schottky source electrode and the first-conductivity-type semiconductor layer is reverse biased, thereby vertically depleting the carriers in the first-conductivity-type semiconductor layer. The introduction of the shielded gate electrode also creates a lateral depletion effect on the carriers in the first-conductivity-type semiconductor layer. This reduces off-state leakage and improves the device's breakdown voltage.

[0073] Preferably, the depth to which the field plate structure extends into the first conductive semiconductor layer does not exceed the depth to which the gate electrode structure extends into the first conductive semiconductor layer. This is because the field plate structure and the Schottky source electrode are at the same potential. When the device is in the off state, both the Schottky source electrode and the field plate structure will laterally deplete carriers in the first n-type conductive semiconductor layer. If the depth to which the field plate structure extends into the first conductive semiconductor layer does not exceed the depth to which the gate electrode structure extends into the first conductive semiconductor layer, then under the action of a positive gate bias, the depth of the accumulation channel formed in the first conductive semiconductor layer by the gate electrode will be insufficient to cover the depth to which the field plate structure extends into the first conductive semiconductor layer. Consequently, the device may not be properly turned on.

[0074] Preferably, the field effect transistor is composed of field effect transistor units configured in strip cells; or the field effect transistor is composed of field effect transistor units configured in closed cells.

[0075] Preferably, the field plate electrode material is a metal, an alloy or an electrode material of the second conductivity type, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, and the second conductivity type is different from the first conductivity type. For example, when the conductivity type of the first conductivity type semiconductor layer is n-type conductivity, the electrode material of the second conductivity type is p-type conductivity. When the device is in the off state, the lateral depletion effect of the p-type field plate electrode on the carriers in the first conductivity type semiconductor layer can reduce the off-state leakage.

[0076] Preferably, the conductivity type of the first conductive type semiconductor layer is the first conductive type, the conductivity type of the base substrate is also the first conductive type, and the field effect transistor is a MSOFET.

[0077] Preferably, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, the conductivity type of the base substrate is the second conductivity type, the first conductivity type is opposite to the second conductivity type, and the field effect transistor is an IGBT.

[0078] FIG3 is a vertical cross-sectional view of a specific embodiment of a field effect transistor of the present invention. FIG3 also shows a shielded gate MOSFET, which includes:

[0079] A drain electrode 11 is located at the bottom layer of the field effect transistor;

[0080] A substrate, located on the drain electrode, namely the n+ type semiconductor layer 21a in FIG3 ;

[0081] A first conductive semiconductor layer, located on the base substrate 21 a , namely, the n-type semiconductor layer 21 b in FIG. 3 ;

[0082] A gate electrode structure includes a gate electrode and a gate insulating film. The gate electrode extends downward from the first region of the upper surface of the first-conductivity-type semiconductor layer, and the gate insulating film 51a wraps around the entire outer surface of the gate electrode. Referring to FIG3 , the gate electrode specifically includes a shielded gate electrode 13b located at the bottom and a recessed gate electrode 13a located at the top, with a dielectric layer disposed between the recessed gate electrode 13a and the shielded gate electrode 13b.

[0083] The Schottky source electrode 12b is located on the second region of the upper surface of the first conductive type semiconductor layer and forms a Schottky contact with the first conductive type semiconductor layer;

[0084] A field plate structure includes a field plate electrode and a dielectric layer 51b. The field plate electrode is the p-type polysilicon electrode 14 in FIG. 3 . The field plate electrode contacts the lower surface of the Schottky source electrode and extends downward. The dielectric layer 51b wraps around the remaining outer surface of the field plate electrode. The work function of the field plate electrode material is greater than the work function of the first conductive type semiconductor layer material.

[0085] an ohmic source electrode 12a, located on the third region of the upper surface of the first conductive type semiconductor layer and forming an ohmic contact with the first conductive type semiconductor layer;

[0086] The first region and the second region of the upper surface of the first conductive type semiconductor layer are not connected.

[0087] The MOSFET field-effect transistor in FIG3 is further improved on the basis of the structure shown in FIG2 . Specifically, a field plate structure connected to the Schottky source electrode 12 b is added below the Schottky source electrode 12 b. The field plate structure includes a p-type polysilicon electrode 14 and a dielectric layer 51 b surrounding the p-type polysilicon electrode 14 . The work function of the p-type polysilicon electrode 14 is greater than the work function of the semiconductor layer corresponding material of the n-type semiconductor layer 21 b.

[0088] In FIG3 , the p-type polysilicon electrode 14, the dielectric layer 51b, and the n-type semiconductor layer 21b in contact with the dielectric layer 51b form a MIS junction (i.e., an electrode-insulator-semiconductor junction). Because the work function of the p-type polysilicon electrode 14 is greater than that of the n-type semiconductor layer 21b, it causes a lateral depletion of electron carriers in the region of the n-type semiconductor layer 21b adjacent to the dielectric layer 51b. Compared to the MSOFET shown in FIG2 , the MOSFET shown in FIG3 enhances the lateral depletion of carriers in the n-type semiconductor layer 21b due to the introduction of a field plate structure connected to the Schottky source electrode 12b below it. Thus, while achieving the same withstand voltage, the doping concentration of the n-type semiconductor layer 21b in the MOSFET shown in FIG3 can be relatively higher. This higher doping concentration helps reduce the on-resistance of the drift region, thereby reducing the conduction loss of the device.

[0089] For the MOSFET field effect transistor in FIG. 3 , further, in order to reduce off-state leakage current, the width of the n-type semiconductor layer 21 b between the Schottky source electrode 12 b and the gate insulating film 51 a is set in the range of 30 nm to 120 nm.

[0090] For the MOSFET field effect transistor in FIG3 , further, the electrode material of the field plate structure may also be metal or alloy, and the work function of the metal or alloy is greater than the work function of the n-type semiconductor layer 21 b .

[0091] 3, when a positive voltage V is applied between the gate electrode 13 and the surface source electrode 12c GS When the voltage applied to the gate electrode 13 is greater than the threshold voltage, a high-concentration electron accumulation channel will be formed in the region of the n-type semiconductor layer 21b adjacent to the gate insulating film 51a. Because this channel is formed in the n-type semiconductor layer 21b, it is equivalent to gathering electrons to form an accumulation-type electron channel. Therefore, the MOSFET of the present invention is an accumulation-type channel field-effect transistor.

[0092] In the embodiment shown in FIG3 , the substrate corresponds to the n+ type semiconductor layer 21 a , and the device formed is an accumulation-type MOSFET; when the substrate uses a p-type conductive semiconductor layer, that is, when the n+ type semiconductor layer 21 a is replaced with a p-type conductive semiconductor layer, an accumulation-type IGBT can be formed.

[0093] It should be understood that the above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above-described embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A field effect transistor, characterized in that: include: A drain electrode, located at the bottom layer of the field effect transistor; A substrate, located on the drain electrode; A first conductive semiconductor layer is located on the substrate; a gate electrode structure, comprising a gate electrode and a gate insulating film, wherein the gate electrode extends downward from a first region on the upper surface of the first conductive type semiconductor layer, and the gate insulating film wraps around the entire outer surface of the gate electrode; A Schottky source electrode is located in a second region of the upper surface of the first conductive semiconductor layer and forms a Schottky contact with the first conductive semiconductor layer; A field plate structure, comprising a field plate electrode and a dielectric layer, wherein the field plate electrode contacts the lower surface of the Schottky source electrode and extends downward, the dielectric layer wraps around the remaining outer surface of the field plate electrode, and the work function of the field plate electrode material is greater than the work function of the first conductive type semiconductor layer material; an ohmic source electrode, located on a third region of the upper surface of the first conductive type semiconductor layer and forming an ohmic contact with the first conductive type semiconductor layer; The first region and the second region on the upper surface of the first conductive type semiconductor layer are not connected.

2. The field effect transistor according to claim 1, characterized in that: The material of the first conductive type semiconductor layer is n-type.

3. The field effect transistor according to claim 1, characterized in that: The width of the first conductive semiconductor layer between the Schottky source electrode and the gate electrode is in the range of 3 nm to 200 nm.

4. The field effect transistor according to claim 1, characterized in that: The Schottky source electrode and the ohmic source electrode correspond to different metals or alloys.

5. The field effect transistor according to claim 1, characterized in that: The gate electrode comprises: a shielding gate electrode located at a lower portion and a groove gate electrode located at an upper portion, and a dielectric layer is provided between the groove gate electrode and the shielding gate electrode.

6. The field effect transistor according to claim 1, characterized in that: The depth to which the field plate structure extends into the first conductive type semiconductor layer does not exceed the depth to which the gate electrode structure extends into the first conductive type semiconductor layer.

7. The field effect transistor according to claim 1, characterized in that: The field effect transistor is composed of field effect transistor units configured in strip cells; or the field effect transistor is composed of field effect transistor units configured in closed cells.

8. The field effect transistor according to claim 1, characterized in that: The field plate electrode material is metal, alloy or a second conductivity type electrode material, the conductivity type of the first conductivity type semiconductor layer is the first conductivity type, and the second conductivity type is different from the first conductivity type.

9. The field effect transistor according to claim 1, characterized in that: The conductivity type of the first conductivity type semiconductor layer is the first conductivity type, the conductivity type of the base substrate is also the first conductivity type, and the field effect transistor is a MSOFET.

10. The field effect transistor according to claim 1, characterized in that: The conductivity type of the first conductivity type semiconductor layer is a first conductivity type, the conductivity type of the base substrate is a second conductivity type, the first conductivity type is opposite to the second conductivity type, and the field effect transistor is an IGBT.

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