Ultra-thin tunnel oxide passivated contact solar cell and manufacturing method therefor

Abstract

An ultra-thin tunnel oxide passivated contact solar cell and a manufacturing method therefor. An ultrathin tunnel oxide layer and a doped polycrystalline silicon layer are arranged on the back face of a semiconductor substrate, so as to achieve ultra-thin tunnel oxide passivated contact on the back face. A bottom electrode contact layer is arranged between a bottom electrode and the doped polycrystalline silicon layer. The bottom electrode contact layer comprises: an ultra-thin oxide layer and a doped polycrystalline silicon carbide layer. The doped polycrystalline silicon carbide layer can control the metallization depth of the bottom electrode in the bottom electrode sintering process, so that the bottom electrode and the doped polycrystalline silicon layer form an ohmic contact, and the metallization range does not exceed the doped polycrystalline silicon layer, so as to prevent the metal material of the sintered bottom electrode from burning the ultra-thin tunnel oxide layer, prevent causing a problem of poor ultra-thin tunnel oxide passivated contact effect, improve the ultra-thin tunnel oxide passivated contact effect, prevent the metal material of the bottom electrode from being in direct contact with the semiconductor substrate, reduce metal contact compounding, reduce parasitic absorption, and improve the photoelectric conversion efficiency.

Description

Ultra-thin tunneling oxide passivation contact solar cell and manufacturing method thereof

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on December 22, 2023, with application number 202311783183.4, and invention name “A Ultra-thin Tunneling Oxide Passivated Contact Solar Cell and Its Manufacturing Method”, and claims priority to the Chinese patent application filed with the Patent Office of China on April 22, 2024, with application number 202410488553.X, and invention name “A TopCon Cell and TopCon Cell Preparation Method”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of solar cells, and more specifically, to an ultra-thin tunneling oxide passivated contact (TOPCon) solar cell and a manufacturing method thereof. Background Art

[0003] The increasing shortage of fossil energy has had a serious impact on the sustainable development of the economy and human environmental health. In addition, the ecological environment has been damaged and traditional energy is facing depletion. As a result, people are in urgent need of a clean, pollution-free, and sustainable green energy. Solar energy, as the most promising clean energy for sustainable development, is particularly important.

[0004] Solar cells are currently the primary way people utilize solar energy. The backside of TOPCon solar cells utilizes an ultra-thin oxide layer and polysilicon layer to achieve an ultra-thin tunneling oxide passivation contact. This not only achieves excellent backside passivation, but also utilizes the quantum tunneling effect to allow majority carriers to tunnel while blocking minority carriers, achieving selective carrier collection and improving photoelectric conversion efficiency. It also exhibits good compatibility with existing Passivated Emitter and Rear Cell (PERC) cell processes.

[0005] Existing TOPCon solar cells have the problem of poor ultra-thin tunneling oxide passivation contact effect and large parasitic absorption problem, which affects the photoelectric conversion efficiency.

[0006] Traditional TopCon (Tunnel Oxide Passivated Contact) cells employ a tunneling layer and a doped polysilicon layer as passivation layers, sequentially arranged across the entire surface of the substrate. However, due to the material structure and doping concentration of the doped polysilicon layer, the doped polysilicon layer in traditional TopCon cells has a relatively high light absorption coefficient, leading to a serious parasitic absorption problem. This problem affects the cell's short-circuit current and bifaciality. Therefore, it is necessary to provide a TopCon cell and a TopCon cell preparation method to address the parasitic absorption problem in the prior art. Summary of the Invention

[0007] In view of this, the present application provides an ultra-thin tunneling oxide passivation contact solar cell and a method for manufacturing the same, the scheme is as follows:

[0008] A TOPCon solar cell, comprising:

[0009] The semiconductor substrate has a front surface and a back surface that are opposite to each other; the back surface has a metal gate line region and non-metal gate line regions on both sides of the metal gate line region;

[0010] An ultra-thin tunnel oxide layer covering the back side;

[0011] a doped polysilicon layer covering an ultra-thin tunnel oxide layer;

[0012] A patterned bottom electrode contact layer is located on a surface of the doped polysilicon layer facing away from the ultra-thin tunneling oxide layer and is located in the metal gate line region;

[0013] a bottom electrode located on a surface of the bottom electrode contact layer facing away from the doped polysilicon layer;

[0014] Among them, the bottom electrode contact layer includes: an ultra-thin oxide layer located on the surface of the doped polycrystalline silicon layer and a doped polycrystalline silicon carbide layer located on the surface of the ultra-thin oxide layer. The doped polycrystalline silicon carbide layer is used to control the metallization depth of the bottom electrode during the bottom electrode sintering process, so that the bottom electrode forms an ohmic contact with the doped polycrystalline silicon layer, and the metallization range does not exceed the doped polycrystalline silicon layer.

[0015] Preferably, in the above TOPCon solar cell, the thickness of the doped polysilicon layer is in the range of 10 nm to 40 nm.

[0016] Preferably, in the above TOPCon solar cell, the thickness of the doped polycrystalline silicon carbide layer is in the range of 40 nm to 140 nm.

[0017] Preferably, in the above TOPCon solar cell, the distance between two adjacent bottom electrodes ranges from 0.85 mm to 0.95 mm.

[0018] Preferably, the above-mentioned TOPCon solar cell further comprises:

[0019] A silicon nitride passivation layer is located on the surface of the doped polysilicon layer on a side away from the ultra-thin tunneling oxide layer. The silicon nitride passivation layer is located in the non-metallic gate line area and exposes the bottom electrode contact layer.

[0020] Preferably, in the above TOPCon solar cell, the thickness of the silicon nitride passivation layer is 70 nm to 150 nm, including both ends.

[0021] Preferably, in the above-mentioned TOPCon solar cell, the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than the light absorption coefficient of the doped polycrystalline silicon layer.

[0022] Preferably, in the above TOPCon solar cell, the activation impurity concentration of the doped polysilicon layer is 1×10 20 cm -3 -1×10 21 cm -3 , including the values ​​at both ends.

[0023] Preferably, in the above TOPCon solar cell, the activation impurity concentration of the doped polycrystalline silicon carbide layer is 1×10 20 cm -3 -1×10 21 cm -3 , including the values ​​at both ends.

[0024] Preferably, in the above TOPCon solar cell, the width of the metal gridline region is 80 μm-200 μm, inclusive; the width of the non-metal gridline region is 1000 μm-2000 μm, inclusive.

[0025] The present application also provides a method for manufacturing any of the above-mentioned TOPCon solar cells, comprising:

[0026] A semiconductor substrate is provided, which has a front surface and a back surface arranged opposite to each other; the back surface has a metal gate line region and non-metal gate line regions located on both sides of the metal gate line region;

[0027] forming an ultra-thin tunneling oxide layer covering the back surface;

[0028] forming a doped polysilicon layer and a bottom electrode contact layer, wherein the doped polysilicon layer covers the polysilicon layer of the ultra-thin tunneling oxide layer; forming a patterned bottom electrode contact layer on a surface of the doped polysilicon layer facing away from the ultra-thin tunneling oxide layer, wherein the bottom electrode contact layer is located in the metal gate line region;

[0029] forming a bottom electrode on a surface of the bottom electrode contact layer facing away from the doped polysilicon layer;

[0030] Among them, the bottom electrode contact layer includes: an ultra-thin oxide layer located on the surface of the doped polycrystalline silicon layer and a doped polycrystalline silicon carbide layer located on the surface of the ultra-thin oxide layer. The doped polycrystalline silicon carbide layer is used to control the metallization depth of the bottom electrode during the bottom electrode sintering process, so that the bottom electrode forms an ohmic contact with the doped polycrystalline silicon layer, and the metallization range does not exceed the doped polycrystalline silicon layer.

[0031] Preferably, in the above-mentioned manufacturing method, an ultra-thin tunneling oxide layer, a doped amorphous silicon layer, an unpatterned bottom electrode contact layer, and an unpatterned mask layer are sequentially formed on the back side using the same PECVD equipment;

[0032] The doped amorphous silicon layer is used to form a doped polysilicon layer based on an annealing process; after the bottom electrode contact layer is patterned based on the mask layer, the mask layer is removed.

[0033] Preferably, in the above manufacturing method, the thickness of the doped polysilicon layer is in the range of 10 nm to 40 nm.

[0034] Preferably, in the above-mentioned manufacturing method, the thickness of the doped polycrystalline silicon carbide layer is in the range of 40 nm to 140 nm;

[0035] And / or, the distance between two adjacent bottom electrodes ranges from 0.85 mm to 0.95 mm.

[0036] Preferably, in the above manufacturing method, the method of forming the doped polysilicon layer and the bottom electrode contact layer includes:

[0037] forming a doped amorphous silicon layer on the surface of the ultra-thin tunneling oxide layer;

[0038] forming an unpatterned ultrathin oxide layer and a doped amorphous silicon carbide layer in sequence on the surface of the doped amorphous silicon layer;

[0039] After forming a mask layer on the surface of the doped amorphous silicon carbide layer on the side facing away from the ultra-thin oxide layer, annealing is performed to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer, and the doped amorphous silicon carbide layer into a doped polycrystalline silicon carbide layer;

[0040] Patterning the mask layer, wherein the patterned mask layer covers the doped polycrystalline silicon carbide layer located at the metal gate line and exposes the doped polycrystalline silicon carbide layer located at the non-metal gate line area;

[0041] Based on the patterned mask layer, etching and removing the doped polycrystalline silicon carbide layer located in the non-metallic gate line area;

[0042] The ultra-thin oxide layer and the mask layer located in the non-metal gate line area are removed simultaneously; wherein the ultra-thin oxide layer and the mask layer are made of the same material.

[0043] From the above description, it can be seen that in the ultra-thin tunneling oxide passivation contact solar cell and its manufacturing method provided by the technical solution of the present application, an ultra-thin tunneling oxide layer and a doped polycrystalline silicon layer are arranged on the back side of the semiconductor substrate, which can realize ultra-thin tunneling oxide passivation contact on the back side, and a bottom electrode contact layer is arranged between the bottom electrode and the doped polycrystalline silicon layer. The bottom electrode contact layer includes: an ultra-thin oxide layer and a doped polycrystalline silicon carbide layer. The doped polycrystalline silicon carbide layer can control the metallization depth of the bottom electrode during the bottom electrode sintering process, so that the bottom electrode forms an ohmic contact with the doped polycrystalline silicon layer, and the metallization range does not exceed the doped polycrystalline silicon layer, thereby avoiding the metal material of the bottom electrode from burning through the ultra-thin tunneling oxide layer after sintering, avoiding the problem of poor ultra-thin tunneling oxide passivation contact effect caused by this, improving the ultra-thin tunneling oxide passivation contact effect, avoiding the metal material of the bottom electrode from directly contacting the semiconductor substrate, reducing metal contact recombination, thereby reducing parasitic absorption and improving photoelectric conversion efficiency.

[0044] This application also provides a TopCon battery and a TopCon battery preparation method, the scheme is as follows:

[0045] A TopCon battery comprises: a substrate; a surface of one side of the substrate having a metal contact area and a non-metal contact area;

[0046] The metal contact region is provided with a first tunneling layer, a doped polysilicon layer and an electrode in sequence along a direction away from the substrate; the electrode is in ohmic contact with the doped polysilicon layer;

[0047] The non-metallic contact region is sequentially provided with a second tunneling layer and a doped polycrystalline silicon carbide layer in a direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than the light absorption coefficient of the doped polycrystalline silicon layer.

[0048] Optionally, the second tunneling layer covers the doped polysilicon layer and the non-metallic contact region; the doped polycrystalline silicon carbide layer covers the second tunneling layer;

[0049] The electrode penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer and makes ohmic contact with the doped polycrystalline silicon layer.

[0050] Optionally, the TopCon cell further comprises: a passivation anti-reflection layer; the passivation anti-reflection layer covers the surface of the doped polycrystalline silicon carbide layer facing away from the substrate;

[0051] The electrode penetrates the passivation anti-reflection layer, the doped polycrystalline silicon carbide layer and the second tunneling layer, and is in ohmic contact with the doped polycrystalline silicon layer.

[0052] Optionally, the passivation anti-reflection layer includes any one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, and a magnesium fluoride layer.

[0053] Optionally, the thickness of the passivation anti-reflection layer is 70 nm to 150 nm, including both ends.

[0054] Optionally, the activated impurity concentration of the doped polysilicon layer is 1×10 20 cm -3 -1×10 21 cm -3 , and include the values ​​at both ends;

[0055] The thickness of the doped polysilicon layer is 20 nm to 100 nm, inclusive.

[0056] Optionally, the activation impurity concentration of the doped polycrystalline silicon carbide layer is 1×10 20 cm -3 -1×10 21 cm -3 , and include the values ​​at both ends;

[0057] The doped polycrystalline silicon carbide layer has a thickness of 20 nm to 50 nm, inclusive.

[0058] Optionally, the width of the metal contact area is 80 μm-200 μm, including both ends; the width of the non-metal contact area is 1000 μm-2000 μm, including both ends.

[0059] Optionally, the doped polycrystalline silicon carbide layer located in the metal contact area is used to control the metallization depth of the electrode during the electrode sintering process, so that the electrode forms an ohmic contact with the doped polycrystalline silicon layer located in the metal contact area, and the metallization range does not exceed the metal contact area.

[0060] Optionally, the spacing between two adjacent electrodes is in the range of 0.85 mm to 0.95 mm. To achieve the above object, the present application also provides a TopCon battery preparation method, comprising:

[0061] A first tunneling layer and a doped polysilicon layer are sequentially formed in a metal contact region on a surface of one side of the substrate in a direction away from the substrate;

[0062] A second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially formed in a non-metallic contact region on a surface of one side of the substrate in a direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than the light absorption coefficient of the doped polycrystalline silicon layer;

[0063] After the doped polysilicon layer and the doped polycrystalline silicon carbide layer are prepared, an electrode is prepared in the metal contact region so that the electrode is in ohmic contact with the doped polysilicon layer.

[0064] Optionally, forming a second tunneling layer and a doped polycrystalline silicon carbide layer in sequence in a direction away from the substrate in a non-metallic contact region on a surface of one side of the substrate includes:

[0065] After the doped polysilicon layer is prepared, the second tunneling layer and the doped polycrystalline silicon carbide layer are sequentially formed on the doped polysilicon layer and the non-metallic contact region in a direction away from the substrate;

[0066] Accordingly, an electrode is prepared in the metal contact region so that the electrode is in ohmic contact with the doped polysilicon layer, comprising:

[0067] The electrode is prepared so that the electrode penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer and is in ohmic contact with the doped polycrystalline silicon layer.

[0068] Obviously, the TopCon cell provided by the present application optimizes the passivation layer structure, retains the doped polysilicon layer in the metal contact area, and the doped polysilicon layer forms a high-low junction with the substrate to provide field passivation and forms an ohmic contact with the electrode; a doped polycrystalline silicon carbide layer is provided in the non-metallic contact area, and the doped polycrystalline silicon carbide layer forms a heterojunction with the substrate to provide field passivation and serve as a lateral carrier transport layer. On the one hand, by removing the doped polysilicon layer in the non-metallic contact area, the parasitic absorption of the passivation layer is reduced. At the same time, since the light absorption coefficient of the doped polycrystalline silicon carbide layer is low and thin, the parasitic absorption can also be reduced; on the other hand, by retaining the doped polysilicon layer in the metal contact area to form an ohmic contact with the electrode, it can ensure low recombination loss when contacting the metal grid line; in addition, field passivation is formed in both the metal contact area and the non-metallic area, ensuring the passivation effect of the entire surface of the substrate. The present application also provides a TopCon cell preparation method, and the TopCon cell prepared by this preparation method also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0070] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size, without affecting the efficacy and objectives that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0071] FIG1 is a cross-sectional view of a TOPCon solar cell provided in an embodiment of the present application;

[0072] FIG2 is a cross-sectional view of another TOPCon solar cell provided in an embodiment of the present application;

[0073] FIG3 is a cross-sectional view of another TOPCon solar cell provided in an embodiment of the present application;

[0074] 4 to 13 are schematic structural diagrams of different process steps of a TOPCon solar cell manufacturing method provided in an embodiment of the present application.

[0075] Description of the drawings: 10-semiconductor substrate; 11-ultra-thin tunneling oxide layer; 12-doped polycrystalline silicon layer; 13-bottom electrode contact layer; 14-bottom electrode; 131-ultra-thin oxide layer; 132-doped polycrystalline silicon carbide layer; 15-silicon nitride passivation layer; 21-diffusion layer; 22-front passivation structure; 23-top electrode; 12'-doped amorphous silicon layer; 132'-doped amorphous silicon carbide layer; 16-mask layer.

[0076] FIG14 is a schematic structural diagram of a TopCon battery provided in an embodiment of the present application;

[0077] FIG15 is a flow chart of a TopCon battery preparation method provided in an embodiment of the present application.

[0078] The reference numerals are as follows: 1 - substrate; 2 - first tunneling layer; 3 - doped polysilicon layer; 4 - second tunneling layer; 5 - doped polycrystalline silicon carbide layer; 6 - passivation anti-reflection layer; 7 - electrode. DETAILED DESCRIPTION

[0079] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0080] It will be apparent to those skilled in the art that various modifications and variations can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application can be combined with each other without contradiction.

[0081] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0082] Referring to FIG. 1 , FIG. 1 is a cross-sectional view of a TOPCon solar cell provided in an embodiment of the present application. The TOPCon solar cell includes:

[0083] The semiconductor substrate 10 has a front surface and a back surface that are opposite to each other; the back surface has a metal gate line region and non-metal gate line regions on both sides of the metal gate line region.

[0084] An ultra-thin tunneling oxide layer 11 covering the back side;

[0085] a doped polysilicon layer 12 covering the ultra-thin tunneling oxide layer 11;

[0086] A patterned bottom electrode contact layer 13, the bottom electrode contact layer 13 is located on a surface of the doped polysilicon layer 12 facing away from the ultra-thin tunneling oxide layer 11 and is located in the metal gate line region;

[0087] A bottom electrode 14 is located on a surface of the bottom electrode contact layer 13 that is away from the doped polysilicon layer 12;

[0088] Among them, the bottom electrode contact layer 13 includes: an ultra-thin oxide layer 131 located on the surface of the doped polysilicon layer 12 and a doped polycrystalline silicon carbide layer 132 located on the surface of the ultra-thin oxide layer 131. The doped polycrystalline silicon carbide layer 132 is used to control the metallization depth of the bottom electrode 14 during the sintering process of the bottom electrode 14, so that the bottom electrode 14 forms an ohmic contact with the doped polysilicon layer 12, and the metallization range does not exceed the doped polysilicon layer 12, avoiding damage to the ultra-thin tunneling oxide layer 11 between the doped polysilicon layer 12 and the semiconductor substrate 10, so as to ensure good ultra-thin tunneling oxide passivation contact.

[0089] On the back side of the semiconductor substrate 10 , an ultra-thin tunneling oxide layer 11 and a doped polysilicon layer 12 can realize a TOPCon passivation structure, thereby improving the battery passivation effect.

[0090] In the TOPCon solar cell provided in the embodiment of the present application, the bottom electrode contact layer 13 is provided with a doped polycrystalline silicon carbide layer 132. The doped polycrystalline silicon carbide layer 132 can control the metallization depth of the bottom electrode 14 during the sintering process of the bottom electrode 14, so that the bottom electrode 14 forms an ohmic contact with the doped polycrystalline silicon layer 12, and the metallization range does not exceed the doped polycrystalline silicon layer 12, thereby avoiding the metal material of the bottom electrode 14 from burning through the ultra-thin tunneling oxide layer 11 after sintering, avoiding the resulting poor ultra-thin tunneling oxide passivation contact effect, improving the ultra-thin tunneling oxide passivation contact effect, avoiding the metal material of the bottom electrode 14 from directly contacting the semiconductor substrate 10, reducing metal contact recombination, thereby reducing parasitic absorption and improving photoelectric conversion efficiency.

[0091] Optionally, the semiconductor substrate 10 is an N-type doped silicon substrate. The ultra-thin tunneling oxide layer 11 is a silicon oxide layer. The doped polysilicon layer 12 can be phosphorus-doped polysilicon. The ultra-thin oxide layer 131 is a silicon oxide layer. The doped polycrystalline silicon carbide layer 132 is a phosphorus-doped polycrystalline silicon carbide layer.

[0092] In conventional TOPCon solar cells, the thickness of the doped polysilicon layer 12 is generally around 120 nm, which is relatively thick, and the short-circuit current density gain of the cell is about 0.2-0.4 mA / cm 2 , the battery short-circuit current density gain is small. Although the battery short-circuit current density gain can be improved by reducing the thickness of the doped polysilicon layer 12, it will cause the lateral carrier transport performance in the doped polysilicon layer 12 to weaken. Moreover, after the electrode is sintered, due to the reduction in the thickness of the doped polysilicon layer 12, it is more likely that the metal material in the bottom electrode 14 will burn through the ultra-thin tunneling oxide layer 11, affecting the photoelectric conversion efficiency.

[0093] In the TOPCon solar cell provided in the embodiment of the present application, a thinner doped polysilicon layer 12 can be used. Although the thickness of the doped polysilicon layer 12 is thinner, the problem of metal material burning through the ultra-thin tunneling oxide layer 11 due to the reduced thickness of the doped polysilicon layer 12 can be solved by doping the polycrystalline silicon carbide layer 132. The problem of weakened lateral carrier transport performance in the doped polysilicon layer 12 due to the reduced thickness of the doped polysilicon layer 12 can be overcome by reducing the distance between the bottom electrodes 14. In this way, while improving the short-circuit current density gain of the battery, the loss of fill factor can be reduced to within an absolute value of less than 0.3%, thereby ensuring that the final photoelectric conversion efficiency of the battery has an absolute gain of more than 0.1%.

[0094] Based on the above description, it can be seen that compared to conventional TOPCon solar cells, in the embodiments of the present application, the thickness of the doped polysilicon layer 12 can be reduced from 120nm to no more than 40nm. For example, the thickness of the doped polysilicon layer 12 can be set to a range of 10nm to 40nm. Due to the significant reduction in the thickness of the doped polysilicon layer 12, the short-circuit current density gain of the cell can be effectively improved.

[0095] Optionally, the thickness of the doped polycrystalline silicon carbide layer 132 is set to be in the range of 40 nm to 140 nm. When the thickness of the doped polycrystalline silicon carbide layer 132 is in the range of 40 nm to 140 nm, the thickness of the doped polycrystalline silicon layer 12 can be made not to exceed 40 nm, and the problem of metal material burning through the ultra-thin tunneling oxide layer 11 due to the reduced thickness of the doped polycrystalline silicon layer 12 can be effectively solved.

[0096] Optionally, based on a certain thickness of the doped polycrystalline silicon carbide layer 132, the electrode contact portion formed by the bottom electrode 14 after sintering can be located on the side of the ultra-thin oxide layer 131 away from the back surface of the semiconductor substrate 10, that is, the bottom electrode 14 does not pass through the ultra-thin oxide layer 131. This is because a heterojunction structure is formed between the doped polycrystalline silicon layer 12 and the doped polycrystalline silicon carbide layer 132, which can promote the separation and migration of photogenerated carriers. However, good surface passivation is required between different semiconductors to reduce interface defects. The ultra-thin oxide layer 131 can effectively passivate the surfaces of the doped polycrystalline silicon layer 12 and the doped polycrystalline silicon carbide layer 132. Moreover, due to its extremely thin thickness, it can cause electron tunneling, further separating the carriers and reducing recombination.

[0097] In some implementations of the embodiments of the present application, the spacing between two adjacent bottom electrodes 14 is set to a range of 0.85mm to 0.95mm. When the spacing between two adjacent bottom electrodes 14 is in the range of 0.85mm to 0.95mm, the thickness of the doped polysilicon layer 12 can be made not to exceed 40nm, and the problem of weakening the lateral carrier transport performance in the doped polysilicon layer 12 due to the reduction in the thickness of the doped polysilicon layer 12 can be effectively overcome. In the embodiments of the present application, the thickness of the doped polycrystalline silicon carbide layer 132 is set to a range of 40nm to 140nm, and the spacing between two adjacent bottom electrodes 14 is set to a range of 0.85mm to 0.95mm, which can greatly reduce the thickness of the doped polysilicon layer 12 and make the doped polysilicon layer 12 not exceed 30nm. A doped polysilicon layer 12 with a thickness ranging from 20nm to 30nm can be used. While effectively solving the problem of metal material burning through the ultra-thin tunneling oxide layer 11 due to the reduction in the thickness of the doped polysilicon layer 12, it also overcomes the problem of weakening the lateral carrier transport performance in the doped polysilicon layer 12 due to the reduction in the thickness of the doped polysilicon layer 12.

[0098] Referring to Figure 2, Figure 2 is a cross-sectional view of another TOPCon solar cell provided in an embodiment of the present application. Based on the above embodiment, the TOPCon solar cell shown in Figure 2 further includes: a silicon nitride passivation layer 15 located on the surface of the doped polysilicon layer 12 facing away from the ultra-thin tunneling oxide layer 11, the silicon nitride passivation layer 15 is located in the non-metallic gate line area, and the bottom electrode contact layer 13 is exposed.

[0099] In the embodiment shown in Figure 5, the back of the cell not only has a TOPCon passivation structure formed by an ultra-thin tunneling oxide layer 11 and a doped polysilicon layer 12, but also a silicon nitride passivation layer 15, enhancing the backside passivation of the cell. Silicon nitride passivation layer 15 has good chemical stability and prevents the metal material of bottom electrode 14 from damaging other film layers in the non-metallic gateline area during subsequent electrode sintering. Furthermore, silicon nitride passivation layer 15 enhances anti-reflection properties.

[0100] Referring to Figure 3, Figure 3 is a cross-sectional view of another TOPCon solar cell provided in an embodiment of the present application. Based on the above embodiment, in the TOPCon solar cell shown in Figure 3, a diffusion layer 21 is provided on the front side of the semiconductor substrate 10, the surface of the diffusion layer 21 is covered with a front passivation structure 22, and a top electrode 23 is provided on the surface of the front passivation structure 22.

[0101] When an N-type doped silicon substrate is used, the diffusion layer 21 may be a P-type doped diffusion layer.

[0102] After forming the top electrode 23 and bottom electrode 14 using a conductive paste through a screen printing process, a sintering process is performed to achieve good ohmic contact between the top electrode 23 and the diffusion layer 21, and good ohmic contact between the bottom electrode 14 and the doped polysilicon layer 12. Through the sintering process, the metal material in the electrode and the silicon material in the underlying film layer can reach the eutectic temperature of the materials under the action of heat, forming an alloy system. When the temperature drops to a certain range, the silicon atoms in the alloy system will recrystallize, forming a good ohmic contact.

[0103] In this embodiment, the light absorption coefficient of the doped polycrystalline silicon carbide layer 132 is less than the light absorption coefficient of the doped polycrystalline silicon layer 12. Although the doped polycrystalline silicon carbide layer 132 is patterned, its width is generally greater than the width of the bottom electrode 14 after sintering. This means that a portion of the doped polycrystalline silicon carbide layer 132, not blocked by the bottom electrode 14, is still exposed on the back side of the solar cell. By setting the light absorption coefficient of the doped polycrystalline silicon carbide layer 132 to be less than that of the doped polycrystalline silicon layer 12, parasitic absorption can be reduced.

[0104] Specifically, in this embodiment, the thickness of the silicon nitride passivation layer 15 is generally 70 nm to 150 nm, including both ends. The activated impurity concentration of the doped polysilicon layer 12 is generally 1×10 20 cm -3 -1×10 21 cm -3 The activation impurity concentration of the doped polycrystalline silicon carbide layer 132 is generally 1×10 20 cm -3 -1×10 21 cm -3 , including the values ​​at both ends.

[0105] Specifically, in this embodiment, the width of the metal gate line region is generally 80 μm-200 μm, including both ends; the width of the non-metal gate line region is generally 1000 μm-2000 μm, including both ends.

[0106] Based on the TOPCon solar cell provided in the above embodiment, another embodiment of the present application further provides a method for manufacturing the above TOPCon solar cell.

[0107] 4 to 12 , which are schematic diagrams of the structure of a TOPCon solar cell manufacturing method according to an embodiment of the present application at different process steps, the manufacturing method includes:

[0108] Step S11: As shown in FIG4 , a semiconductor substrate 10 is provided.

[0109] The semiconductor substrate 10 has a front surface and a back surface that are opposite to each other. The back surface has a metal gate line region and non-metal gate line regions on both sides of the metal gate line region.

[0110] Step S12: As shown in FIG5 , an ultra-thin tunneling oxide layer 11 is formed to cover the back surface.

[0111] A PECVD process may be used to form an ultra-thin tunneling oxide layer 11 on the back side of the semiconductor substrate 10 by utilizing N2O ionization. Optionally, the thickness of the ultra-thin tunneling oxide layer 11 may be in the range of 0.8 nm to 2 nm.

[0112] Step S13: As shown in FIG. 6 to FIG. 13 , a doped polysilicon layer 12 and a bottom electrode contact layer 13 are formed.

[0113] The doped polysilicon layer 12 covers the ultra-thin tunneling oxide layer 11 . A patterned bottom electrode contact layer 13 is formed on the surface of the doped polysilicon layer 12 facing away from the ultra-thin tunneling oxide layer 11 . The bottom electrode contact layer 13 is located in the metal gate line region.

[0114] In this step, the method for forming the doped polysilicon layer 12 and the bottom electrode contact layer 13 includes: as shown in FIG6, forming a doped amorphous silicon layer 12' on the surface of the ultra-thin tunneling oxide layer 11; as shown in FIG7 and FIG8, sequentially forming an unpatterned ultra-thin oxide layer 131 and a doped amorphous silicon carbide layer 132' on the surface of the doped amorphous silicon layer 12'; as shown in FIG9, forming a mask layer 16 on the surface of the doped amorphous silicon carbide layer 132' away from the ultra-thin oxide layer 131, and then performing annealing as shown in FIG10 to convert the doped amorphous silicon layer 12' into a doped polysilicon layer 12, and converting the doped amorphous silicon carbide layer 132' into a doped polysilicon layer 12. The silicon carbide layer 132' is converted into a doped polycrystalline silicon carbide layer 12; as shown in FIG11 , the mask layer 16 is patterned, and the patterned mask layer 16 covers the doped polycrystalline silicon carbide layer 132 located in the metal gate line and exposes the doped polycrystalline silicon carbide layer 132 located in the non-metal gate line area; as shown in FIG12 , based on the patterned mask layer 16, the doped polycrystalline silicon carbide layer 132 located in the non-metal gate line area is etched away; as shown in FIG13 , the ultra-thin oxide layer 131 and the mask layer 16 located in the non-metal gate line area are simultaneously removed; wherein, the ultra-thin oxide layer 131 and the mask layer 16 are made of the same material.

[0115] A PECVD process can be used to deposit a phosphorus-doped amorphous silicon layer 12' using SiH4 and PH3 ionization, so as to facilitate subsequent annealing to form a doped polysilicon layer 12. Optionally, the thickness of the doped amorphous silicon layer 12' can range from 10 nm to 40 nm, and the corresponding thickness of the doped polysilicon layer 12 can range from 10 nm to 40 nm.

[0116] Step S14: forming a bottom electrode 14 on the surface of the bottom electrode contact layer 13 facing away from the polysilicon layer 12 to form the battery structure shown in FIG1 .

[0117] The manufacturing method shown in Figures 4 to 13 is described using the battery structure shown in Figure 1 as an example. For the entire surface structure of the battery, reference can be made to the manufacturing method of the front structure of a conventional TOPCon solar cell, which will not be described in detail in the embodiments of this application.

[0118] Among them, the bottom electrode contact layer 13 includes: an ultra-thin oxide layer 131 located on the surface of the doped polysilicon layer 12 and a doped polycrystalline silicon carbide layer 132 located on the surface of the ultra-thin oxide layer 131. The doped polycrystalline silicon carbide layer 132 is used to control the metallization depth of the bottom electrode 14 during the sintering process of the bottom electrode 14, so that the bottom electrode 14 forms an ohmic contact with the doped polysilicon layer 12, and the metallization range does not exceed the doped polysilicon layer 12.

[0119] In step S13, the method for forming the bottom electrode contact layer 13 includes:

[0120] Step S141: As shown in FIG7 , an unpatterned ultrathin oxide layer 131 is formed. PECVD can be used to form the ultrathin oxide layer 131 on the surface of the doped amorphous silicon layer 12 ′ using N 2 O ionization. Optionally, the thickness of the ultrathin oxide layer 131 ranges from 0.8 nm to 2 nm.

[0121] Step S142: As shown in FIG8 , an unpatterned doped amorphous silicon carbide layer 132' is formed. A PECVD process can be used to form a phosphorus-containing amorphous silicon carbide layer on the surface of the ultra-thin oxide layer 131 using SiH4, CO2, and PH3 ionization. The doped amorphous silicon carbide layer 132' can optionally have a thickness ranging from 40 nm to 140 nm.

[0122] Step S143: As shown in FIG9 , a mask layer 16 is formed covering the doped amorphous silicon carbide layer 132 ′. A PECVD process can be used to ionize SiH 4 and N 2 O to form a layer of silicon oxide on the surface of the doped amorphous silicon carbide layer 132 ′ as the mask layer 16. Optionally, the thickness of the mask layer 16 ranges from 10 nm to 30 nm.

[0123] As shown in FIG11 , after forming the mask layer 16 and before patterning the mask layer 16, an annealing process is performed to crystallize the polysilicon layer 12 and the doped amorphous silicon carbide layer 132' and activate doping to ensure uniform doping of internal dopant ions. Performing the annealing process before patterning the mask layer 16 allows for a uniform annealing temperature across the entire mask layer 16, ensuring crystallization of the doped amorphous silicon layer 12' and the doped amorphous silicon carbide layer 132' and improving the uniformity of internal dopant ion distribution, thereby forming high-quality doped polysilicon layer 12 and doped polycrystalline silicon carbide layer 132 after annealing.

[0124] In addition, compared with the method of etching the doped amorphous silicon carbide layer 132' to form a patterned doped amorphous silicon carbide layer 132', and then annealing to form a doped polycrystalline silicon carbide layer 132, the embodiment of the present application first performs annealing and then forms a patterned doped polycrystalline silicon carbide layer 132, which can make the doping ion distribution in the doped polycrystalline silicon carbide layer 132 more uniform. This is because the lateral size of the patterned doped amorphous silicon carbide layer 132' is relatively small. If annealing is performed after patterning, the edge effect will cause a large difference in the uniformity of doped ions in the edge regions and the central region of the formed doped polycrystalline silicon carbide layer 132. In the present application, the patterned doped polycrystalline silicon carbide layer 132 is formed after annealing. Even if the uniformity of doped ions in the edge regions and the central region of the doped polycrystalline silicon carbide layer 132 is significantly different after annealing, the edge regions can be removed after etching the doped polycrystalline silicon carbide layer 132, thereby making the distribution of doped ions in the doped polycrystalline silicon carbide layer 132 more uniform.

[0125] Step S144: As shown in FIG11 , the mask layer 16 is etched to form a desired pattern structure to facilitate subsequent etching of the doped polycrystalline silicon carbide layer 132. In this step, laser etching can be used to remove the mask layer 16 in the non-metal gate region, exposing the doped polycrystalline silicon carbide layer 132 in the non-metal gate region, while retaining the mask layer 16 in the metal gate region to protect the doped polycrystalline silicon carbide layer 132 in the metal gate region.

[0126] Step S145: As shown in FIG12 , the doped polycrystalline silicon carbide layer 132 is etched based on the etched mask layer 16 to form a patterned doped polycrystalline silicon carbide layer 132. Wet etching can be used to remove the doped polycrystalline silicon carbide layer 132 not covered by the mask layer 16, while retaining the doped polycrystalline silicon carbide layer 132 covered by the mask layer 16, thereby forming a patterned doped polycrystalline silicon carbide layer 132.

[0127] Step S146: As shown in FIG13 , the ultra-thin oxide layer 131 in the non-metal gate region and the mask layer 16 on the surface of the doped polycrystalline silicon carbide layer 132 are simultaneously etched away. This step not only etches the ultra-thin oxide layer 131 to form a patterned ultra-thin oxide layer 131, but also simultaneously removes the mask layer 16 on the surface of the doped polycrystalline silicon carbide layer 132.

[0128] The mask layer 16 and the ultra-thin oxide layer 131 are made of the same material so that they can be etched and removed simultaneously. For example, both can be silicon oxide layers.

[0129] In an embodiment of the present application, the thickness of the mask layer 16 is greater than the thickness of the ultra-thin oxide layer 131. Thus, when the doped polycrystalline silicon carbide layer 132 is etched based on the mask layer 16, a portion of the thickness of the mask layer 16 is consumed. At this time, the mask layer 16 and the ultra-thin oxide layer 131 have the same or similar thickness, so that the two can be better etched and removed synchronously.

[0130] The same PECVD equipment can be used to sequentially form an ultra-thin tunneling oxide layer 11, a doped amorphous silicon layer 12', an unpatterned bottom electrode contact layer 13, and an unpatterned mask layer 16 on the back side of the semiconductor substrate 10; as described above, after the bottom electrode contact layer 13 is patterned based on the mask layer 16, the mask layer 16 is removed.

[0131] In the embodiment of the present application, the ultra-thin tunneling oxide layer 11, the doped amorphous silicon layer 12', the unpatterned bottom electrode contact layer 13 and the unpatterned mask layer 16 can be formed in sequence in the same PECVD equipment without replacing other process machines. The manufacturing process is simple and the manufacturing cost is reduced.

[0132] As mentioned above, the thickness of the doped polysilicon layer 12 ranges from 10 nm to 40 nm. The thickness of the doped polycrystalline silicon carbide layer 132 ranges from 40 nm to 140 nm; and / or, the spacing between two adjacent bottom electrodes 14 ranges from 0.85 mm to 0.95 mm. This not only significantly reduces the thickness of the doped polysilicon layer 12, but also effectively solves the problem of metal material burning through the ultra-thin tunneling oxide layer 11 due to the reduced thickness of the doped polysilicon layer 12, and overcomes the problem of weakened lateral carrier transport performance in the doped polysilicon layer 12 due to the reduced thickness of the doped polysilicon layer 12.

[0133] In the embodiment of the present application, the thickness of the doped polysilicon layer 12 is uniform, and there is no need to design a differentiated thickness of the doped polysilicon layer 12 in the metal gate line area and the non-metal gate line area. By doping the polycrystalline silicon carbide layer 132, the metal material in the bottom electrode 14 can be prevented from burning through the doped polysilicon layer 12.

[0134] Please refer to FIG14 , which is a schematic diagram of the structure of a TopCon battery provided in an embodiment of the present application. The structure may include: a substrate 1; a metal contact area and a non-metallic contact area are provided on one side surface of the substrate 1;

[0135] The metal contact region is provided with a first tunneling layer 2, a doped polysilicon layer 3 and an electrode 7 in sequence along a direction away from the substrate 1; the electrode 7 is in ohmic contact with the doped polysilicon layer 3;

[0136] The non-metallic contact region is sequentially provided with a second tunneling layer 4 and a doped polycrystalline silicon carbide layer 5 in a direction away from the substrate 1 ; the light absorption coefficient of the doped polycrystalline silicon carbide layer 5 is smaller than that of the doped polycrystalline silicon layer 3 .

[0137] This embodiment does not limit the specific type of the substrate 1. For example, the substrate 1 may be doped single crystal silicon, including but not limited to phosphorus-doped N-type single crystal silicon, boron-doped or gallium-doped P-type single crystal silicon.

[0138] This embodiment does not limit the specific location of the passivation structure formed by the first tunneling layer 2, the doped polysilicon layer 3, the second tunneling layer 4 and the doped polycrystalline silicon carbide layer 5. For example, it can be located on the front side of the substrate 1; it can also be located on the back side of the substrate 1; it can also be located on both the front side and the back side of the substrate 1.

[0139] This embodiment does not limit the specific type of the first tunneling layer 2. For example, the first tunneling layer 2 may be a tunneling oxide layer, including but not limited to a phosphorus- or boron-containing silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer. This embodiment does not limit the specific thickness of the first tunneling layer 2. For example, the thickness of the first tunneling layer 2 may be 0.5 nm to 2 nm, inclusive.

[0140] This embodiment does not limit the specific type of the second tunneling layer 4. For example, the second tunneling layer 4 may be a tunneling oxide layer, including but not limited to a phosphorus- or boron-containing silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer. This embodiment does not limit the specific thickness of the second tunneling layer 4. For example, the thickness of the second tunneling layer 4 may be 0.5 nm to 2 nm, inclusive.

[0141] This embodiment does not limit the specific type of the doped polysilicon layer 3. For example, the doped polysilicon layer 3 may be a phosphorus-doped or boron-doped polysilicon layer. This embodiment does not limit the specific activation impurity concentration of the doped polysilicon layer 3. For example, the activation impurity concentration of the doped polysilicon layer 3 may be 1×10 20 cm -3 -1×10 21 cm -3 This embodiment does not limit the specific thickness of the doped polysilicon layer 3 . For example, the thickness of the doped polysilicon layer 3 may be 20 nm to 100 nm, including both ends of the thickness.

[0142] This embodiment does not limit the specific type of the doped polycrystalline silicon carbide layer 5. For example, the doped polycrystalline silicon carbide layer 5 can be a phosphorus-doped or boron-doped polycrystalline silicon carbide layer. This embodiment does not limit the specific activation impurity concentration of the doped polycrystalline silicon carbide layer 5. For example, the activation impurity concentration of the doped polycrystalline silicon carbide layer 5 can be 1×10 20 cm -3 -1×10 21 cm -3, including both ends. This embodiment does not limit the specific thickness of the doped polycrystalline silicon carbide layer 5. For example, the thickness of the doped polycrystalline silicon carbide layer 5 can be 20nm-50nm, including both ends. It should be noted that when the doped polycrystalline silicon carbide layer 5 covers both the non-metallic contact area and the metal contact area, the thinner the thickness of the doped polycrystalline silicon carbide layer 5, the more conducive it is for the electrode 7 slurry to burn through the second tunneling layer 4 and contact the doped polycrystalline silicon layer 3.

[0143] When the doped polycrystalline silicon carbide layer 5 covers the metal contact area, the doped polycrystalline silicon carbide layer 5 located in the metal contact area can also be used to control the metallization depth of the electrode 7 during the sintering process of the electrode 7, so that the electrode 7 forms an ohmic contact with the doped polycrystalline silicon layer 3 located in the metal contact area, and the metallization range does not exceed the metal contact area. At this time, this structure can prevent the metal material of the electrode 7 from burning through the first tunneling layer 2 after sintering, avoid the resulting poor passivation contact effect of the first tunneling layer 2, improve the passivation contact effect of the first tunneling layer 2, prevent the metal material of the electrode 7 from directly contacting the substrate 1, reduce metal contact recombination, thereby reducing parasitic absorption and improving photoelectric conversion efficiency.

[0144] Specifically, in this embodiment, the distance between two adjacent electrodes 7 ranges from 0.85 mm to 0.95 mm.

[0145] This embodiment does not limit the specific widths of the metal contact region and the non-metal contact region. For example, the width of the metal contact region can be 80 μm-200 μm, inclusive; the width of the non-metal contact region can be 1000 μm-2000 μm, inclusive. It should be noted that in this embodiment, the pattern of the metal contact region corresponds to the pattern of the metal electrode 7 and is distributed in a grid-like pattern.

[0146] This embodiment does not limit the specific type of material used for the electrode 7. For example, the material of the electrode 7 may include but is not limited to silver, aluminum, copper, and alloys thereof.

[0147] Furthermore, in this embodiment, the second tunneling layer 4 can cover the doped polysilicon layer 3 and the non-metallic contact area; the doped polycrystalline silicon carbide layer 5 can cover the second tunneling layer 4; and the electrode 7 penetrates the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4, establishing ohmic contact with the doped polycrystalline silicon layer 3. It should be noted that the different materials are spatially distributed according to the metal contact area and the non-metallic contact area. In this embodiment, the metal contact area is a stack of the first tunneling layer 2, the doped polycrystalline silicon layer 3, the second tunneling layer 4, and the doped polycrystalline silicon carbide layer 5, while the non-metallic contact area is the second tunneling layer 4 and the doped polycrystalline silicon carbide layer 5. In preparing this structure in this embodiment, the step of patterning the second tunneling layer 4 and the doped polycrystalline silicon carbide layer 5 can be omitted, simplifying the preparation process.

[0148] Furthermore, in order to achieve anti-reflection and passivation functions, this embodiment may also include: a passivation anti-reflection layer 6; the passivation anti-reflection layer 6 covers the surface of the doped polycrystalline silicon carbide layer 5 facing away from the substrate 1; the electrode 7 penetrates the passivation anti-reflection layer 6, the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4, and is in ohmic contact with the doped polycrystalline silicon layer 3.

[0149] This embodiment does not limit the specific type of the passivation anti-reflection layer 6. For example, the passivation anti-reflection layer 6 may include any one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, and a magnesium fluoride layer. This embodiment does not limit the specific thickness of the passivation anti-reflection layer 6. For example, the thickness of the passivation anti-reflection layer 6 may be 70 nm to 150 nm, inclusive.

[0150] Based on the above embodiments, the present application optimizes the passivation layer structure, retaining a doped polysilicon layer in the metal contact region. The doped polysilicon layer forms a high-low junction with the substrate to provide field passivation and forms an ohmic contact with the electrode. A doped polycrystalline silicon carbide layer is provided in the non-metallic contact region. The doped polycrystalline silicon carbide layer forms a heterojunction with the substrate to provide field passivation and serve as a lateral carrier transport layer. On the one hand, by removing the doped polysilicon layer in the non-metallic contact region, the parasitic absorption of the passivation layer is reduced. At the same time, since the doped polycrystalline silicon carbide layer has a low light absorption coefficient and is thinner, parasitic absorption is also reduced. On the other hand, by retaining the doped polysilicon layer in the metal contact region to form an ohmic contact with the electrode, low recombination loss can be ensured when contacting the metal gate line. In addition, field passivation is formed in both the metal contact region and the non-metallic region, ensuring a passivation effect on the entire surface of the substrate.

[0151] Please refer to FIG15 , which is a flow chart of a TopCon battery preparation method provided in an embodiment of the present application. The method may include:

[0152] S101: a first tunneling layer and a doped polysilicon layer are sequentially formed in a metal contact region on a surface of one side of a substrate in a direction away from the substrate.

[0153] Furthermore, in order to remove dirt and mechanical damage on the surface of the substrate 1 and form a polished or pyramid-like suede morphology, the substrate 1 may be cleaned and dried before step S101. This embodiment does not limit the specific cleaning method, as long as it can ensure that dirt and mechanical damage on the surface of the substrate 1 are removed and a polished or pyramid-like suede morphology is formed. For example, the substrate 1 may be cleaned and dried using a wet chemical method.

[0154] This embodiment does not limit the specific method of preparing the first tunneling layer 2 and the doped polysilicon layer 3, as long as it is ensured that the first tunneling layer 2 and the doped polysilicon layer 3 can be formed in the metal contact area. For example, the first tunneling layer 2 can be prepared on the surface of one side of the substrate 1; after the first tunneling layer 2 is formed, the doped polysilicon layer 3 is prepared on the surface of the first tunneling layer 2 facing away from the substrate 1; after the doped polysilicon layer 3 is formed, the doped polysilicon layer 3 and the first tunneling layer 2 in the non-metal contact area are patterned.

[0155] This embodiment does not limit the specific method for preparing the first tunneling layer 2. The corresponding preparation method can be selected according to the specific type of the first tunneling layer 2. For example, when the first tunneling layer 2 is a tunneling oxide layer, high-temperature thermal oxidation with oxygen or plasma-enhanced oxidation can be performed by introducing nitrous oxide into a PECVD (Plasma Enhanced Chemical Vapor Deposition) device to oxidize the surface of one side of the substrate 1 to form the first tunneling layer 2 on the surface of one side of the substrate 1.

[0156] This embodiment does not limit the specific method for preparing the doped polycrystalline silicon layer 3. For example, a PECVD device may be used to deposit a doped amorphous silicon layer on the surface of the first tunneling layer 2 facing away from the substrate 1. The reaction gas source may include, but is not limited to, silane, phosphine, diborane, or hydrogen. After the doped amorphous silicon layer is formed, the doped amorphous silicon layer is crystallized in an annealing device to form the doped polycrystalline silicon layer 3. This preparation method is an in-situ doping method. Alternatively, the doped amorphous silicon layer may be formed by impurity diffusion.

[0157] This embodiment does not limit the specific timing of crystallization. The doped amorphous silicon layer can be crystallized directly after the doped amorphous silicon layer is formed; or the doped amorphous silicon layer and the doped amorphous silicon carbide layer can be crystallized simultaneously after the doped amorphous silicon carbide layer is prepared. This embodiment does not limit the specific value of the annealing temperature. For example, the annealing temperature can be 850°C-1100°C, including both ends. This embodiment does not limit the specific type of annealing atmosphere. For example, the annealing atmosphere can be an inert gas such as nitrogen, argon, or a hydrogen-nitrogen mixture.

[0158] This embodiment does not limit the specific method of graphical processing. For example, an oxidation mask may be prepared on the surface of the doped amorphous silicon layer facing away from the substrate 1; after forming the oxidation mask, the oxidation mask, the doped amorphous silicon layer and the first tunneling oxide layer in the non-metal contact area are removed; after removing the first tunneling oxide layer, the oxidation mask in the metal contact area is removed.

[0159] This embodiment does not limit the specific type of the oxidation mask. For example, the oxidation mask may include a silicon oxide mask or a silicon oxynitride mask. This embodiment does not limit the specific method for preparing the oxidation mask. A corresponding preparation method can be selected according to the specific type of the oxidation mask. For example, the oxidation mask can be deposited on the surface of the doped amorphous silicon layer facing away from the substrate 1 using a PECVD device. The reaction gas source includes but is not limited to silane, nitrous oxide, or ammonia.

[0160] This embodiment does not limit the specific method for removing the oxide mask in the non-metallic contact area. For example, a laser can be used to open holes in the oxide mask in the non-metallic contact area. Alternatively, a barrier paste can be printed on the surface of the oxide mask in the metal contact area. After printing the barrier paste, the oxide mask in the non-metallic contact area can be removed using hydrofluoric acid etching. It should be noted that the oxide mask in the metal contact area can be directly removed using hydrofluoric acid etching.

[0161] This embodiment does not limit the specific method of removing the doped amorphous silicon layer in the non-metallic contact area. For example, the doped amorphous silicon layer in the non-metallic contact area can be removed by etching with an alkaline solution, but is not limited to the method. It should be noted that during the removal of the doped amorphous silicon layer, the first tunneling layer 2 will also be removed.

[0162] Furthermore, in this embodiment, after removing the oxide mask of the metal contact area, the surface of the substrate 1 may be cleaned; cleaning methods include but are not limited to water cleaning or RCA cleaning, wherein RCA cleaning is a wet chemical cleaning method.

[0163] S102: a second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially formed in a non-metallic contact area on a surface of one side of the substrate in a direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than the light absorption coefficient of the doped polycrystalline silicon layer.

[0164] Furthermore, in order to simplify the process flow, in this embodiment, after the doped polysilicon layer 3 is prepared, a second tunneling layer 4 and a doped polycrystalline silicon carbide layer 5 can be prepared in sequence in the direction away from the substrate 1 in the doped polysilicon layer 3 and the non-metallic contact area; accordingly, an electrode 7 is prepared so that the electrode 7 penetrates the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4, and is in ohmic contact with the doped polysilicon layer 3.

[0165] This embodiment does not limit the specific method of preparing the second tunneling layer 4. The corresponding preparation method can be selected according to the specific type of the second tunneling layer 4. For example, when the second tunneling layer 4 is a tunneling oxide layer, high-temperature thermal oxidation with oxygen or plasma-enhanced oxidation by introducing nitrous oxide into a PECVD device can be used to oxidize the surface of the doped polysilicon layer 3 facing away from the substrate 1 and the non-metallic contact area, thereby forming the second tunneling layer 4 on the surface of the doped polysilicon layer 3 facing away from the substrate 1 and the non-metallic contact area.

[0166] This embodiment does not limit the specific method for preparing the doped polycrystalline silicon carbide layer 5. For example, a PECVD device may be used to deposit a doped amorphous silicon carbide layer on the surface of the second tunneling layer 4 facing away from the substrate 1. The reaction gas source may include, but is not limited to, silane, phosphine, diborane, or hydrogen. After the doped amorphous silicon carbide layer is formed, it is crystallized in an annealing device to form the doped polycrystalline silicon carbide layer 5. This preparation method is an in-situ doping method. Alternatively, the doped amorphous silicon carbide layer may be formed by impurity diffusion.

[0167] Furthermore, in order to achieve anti-reflection and passivation functions, after step S102, this embodiment can also prepare a passivation anti-reflection layer 6 on the surface of the doped polycrystalline silicon carbide layer 5 facing away from the substrate 1; accordingly, an electrode 7 is prepared so that the electrode 7 penetrates the passivation anti-reflection layer 6, the doped polycrystalline silicon carbide layer 5 and the second tunneling layer 4, and is in ohmic contact with the doped polycrystalline silicon layer 3.

[0168] This embodiment does not limit the specific type of the passivation anti-reflection layer 6. For example, the passivation anti-reflection layer 6 may include any one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, and a magnesium fluoride layer. This embodiment does not limit the specific method for preparing the passivation anti-reflection layer 6. A corresponding preparation method can be selected according to the specific type of the passivation anti-reflection layer 6. For example, the passivation anti-reflection layer 6 can be deposited on the surface of the doped polycrystalline silicon carbide layer 5 facing away from the substrate 1 using a PECVD device or an ALD (Atomic Layer Deposition) device. The reaction gas source includes but is not limited to silane, ammonia, trimethylaluminum, or laughing gas.

[0169] S103: After the doped polysilicon layer and the doped polycrystalline silicon carbide layer are prepared, an electrode is prepared in the metal contact area so that the electrode is in ohmic contact with the doped polysilicon layer.

[0170] This embodiment does not limit the specific method for preparing the electrode 7. For example, the electrode 7 can be formed in the metal contact area by screen printing or electroplating. The screen printing method requires a high-temperature sintering annealing process to volatilize the organic solvent in the metal slurry, burn through the surface passivation anti-reflection layer 6, and form a metal-semiconductor contact between the metal particles and the doped polycrystalline silicon layer 3. The electroplating method requires laser pretreatment to remove the surface passivation anti-reflection layer 6 and the doped polycrystalline silicon carbide layer 5 in the electroplated area, so that the electroplated metal forms a metal-semiconductor contact with the doped polycrystalline silicon layer 3.

[0171] The TopCon cell prepared based on the above-described embodiment has an optimized passivation layer structure. A doped polysilicon layer is retained in the metal contact region. The doped polysilicon layer forms a high-low junction with the substrate, providing field passivation, and forms an ohmic contact with the electrode. A doped polycrystalline silicon carbide layer is provided in the non-metallic contact region. The doped polycrystalline silicon carbide layer forms a heterojunction with the substrate, providing field passivation and serving as a lateral carrier transport layer. On the one hand, by removing the doped polysilicon layer from the non-metallic contact region, parasitic absorption of the passivation layer is reduced. Furthermore, since the doped polysilicon carbide layer has a low light absorption coefficient and is thinner, parasitic absorption is also reduced. On the other hand, by retaining the doped polysilicon layer in the metal contact region to form an ohmic contact with the electrode, low recombination losses are ensured when in contact with the metal gate line. Furthermore, field passivation is formed in both the metal contact region and the non-metallic region, ensuring a passivation effect across the entire substrate surface.

[0172] The following is a specific example to illustrate the preparation process of the TopCon battery. The process is as follows:

[0173] Step 1: Cleaning: The silicon wafer is cleaned and dried using a wet chemical method to remove dirt and mechanical damage on the surface of the silicon wafer and form a polished or pyramid-like suede surface. The cleaning process is not restricted here.

[0174] Step 2, primary oxidation: The cleaned silicon wafer is subjected to surface oxidation treatment, using oxygen high-temperature thermal oxidation or plasma-enhanced oxidation by introducing nitrous oxide in a PECVD device to form a tunneling oxide layer on the surface of the silicon wafer;

[0175] Step 3, doped amorphous silicon deposition: PECVD equipment is used to deposit on the coated surface of the silicon wafer to form a doped amorphous silicon film. The reaction gas source is silane, phosphine, diborane or hydrogen;

[0176] Step 4: Oxide mask deposition: Deposit a silicon oxide or silicon oxynitride mask on the surface of the doped amorphous silicon film using PECVD equipment, with the reaction gas source being silane, nitrous oxide, or ammonia.

[0177] Step 5: Patterning: Patterning the oxide mask and the doped amorphous silicon film. The specific process includes: patterning the oxide mask, patterning the doped amorphous silicon film, hydrofluoric acid etching, and post-cleaning.

[0178] The patterned oxide mask preparation may include laser film opening, or resist slurry printing and hydrofluoric acid etching, etc., to remove the oxide mask in the non-metal contact area and retain the oxide mask in the metal contact area;

[0179] The patterned doped amorphous silicon film can be prepared by etching with an alkaline solution to remove the doped amorphous silicon film in the non-metallic contact area; in the process of removing the doped amorphous silicon film, the tunneling oxide layer formed in step 2 will also be removed;

[0180] Remove the remaining oxide mask in the metal contact area by hydrofluoric acid etching, and clean the silicon wafer surface by water washing or RCA cleaning;

[0181] Step 6, secondary oxidation: The cleaned silicon wafer is subjected to surface oxidation treatment, using oxygen high-temperature thermal oxidation or plasma-enhanced oxidation by introducing nitrous oxide in a PECVD device to form a tunneling oxide layer on the surface of the silicon wafer and the patterned doped amorphous silicon film;

[0182] Step 7: Deposition of doped amorphous silicon carbide: PECVD equipment is used to deposit a doped amorphous silicon carbide film on the coated surface of the silicon wafer. The reaction gas source is silane, methane, phosphine, diborane or hydrogen.

[0183] Step 8: High-temperature annealing and crystallization: The silicon wafer is placed in a high-temperature annealing device at 850 to 1100°C to crystallize the doped amorphous silicon film and doped amorphous silicon carbide film prepared in steps 3 and 7 to form a doped polycrystalline silicon film and a doped polycrystalline silicon carbide film. The annealing atmosphere is an inert gas such as nitrogen, argon, or a hydrogen-nitrogen mixture.

[0184] Step 9: Deposition of surface passivation anti-reflection film: Deposition is performed on the coated surface of the silicon wafer using equipment such as PECVD and ALD to form a surface passivation anti-reflection film on the outside of the doped polysilicon film. The reaction gas source is silane, ammonia, trimethylaluminum or laughing gas.

[0185] Step 10, Metallization: Metal electrodes with the same pattern as the metal contact areas are prepared by screen printing or electroplating. The screen printing method requires high-temperature sintering and annealing to volatilize the organic solvent in the metal slurry, burn through the surface passivation anti-reflection film, and form a metal-semiconductor contact between the metal particles and the doped polycrystalline silicon film. The electroplating method requires laser pretreatment to remove the surface passivation anti-reflection film and the doped polycrystalline silicon carbide film in the electroplated area, so that the electroplated metal and the doped polycrystalline silicon film form a metal-semiconductor contact.

[0186] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0187] It should be noted that in the description of this application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure numbers throughout the embodiments of the specification identify the same structure. In addition, for the purpose of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity.

[0188] The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like, indicating positions or locations, are based on the positions or locations shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this application. They are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally located component.

[0189] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0190] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An ultra-thin tunneling oxide passivation contact solar cell, characterized in that: include: A semiconductor substrate having a front side and a back side arranged opposite to each other; The back surface has a metal gate line region and non-metal gate line regions located on both sides of the metal gate line region; an ultra-thin tunneling oxide layer covering the back surface; a doped polysilicon layer covering the ultra-thin tunneling oxide layer; A patterned bottom electrode contact layer is located on a surface of the doped polysilicon layer that is away from the ultra-thin tunneling oxide layer and is located in the metal gate line region; A bottom electrode located on a surface of the bottom electrode contact layer facing away from the doped polysilicon layer; Among them, the bottom electrode contact layer includes: an ultra-thin oxide layer located on the surface of the doped polysilicon layer and a doped polycrystalline silicon carbide layer located on the surface of the ultra-thin oxide layer, and the doped polycrystalline silicon carbide layer is used to control the metallization depth of the bottom electrode during the bottom electrode sintering process, so that the bottom electrode forms an ohmic contact with the doped polysilicon layer, and the metallization range does not exceed the doped polysilicon layer.

2. The ultra-thin tunneling oxide passivation contact solar cell according to claim 1, characterized in that: The thickness of the doped polysilicon layer is in the range of 10 nm to 40 nm.

3. The ultra-thin tunneling oxide passivation contact solar cell according to claim 2, characterized in that: The thickness of the doped polycrystalline silicon carbide is in the range of 40 nm to 140 nm.

4. The ultra-thin tunneling oxide passivation contact solar cell according to claim 2, characterized in that: The distance between two adjacent bottom electrodes ranges from 0.85 mm to 0.95 mm.

5. The ultra-thin tunneling oxide passivated contact solar cell according to any one of claims 1 to 4, characterized in that: Also includes: A silicon nitride passivation layer is located on the surface of the doped polysilicon layer on a side away from the ultra-thin tunneling oxide layer, and the silicon nitride passivation layer is located in the non-metallic gate line region and exposes the bottom electrode contact layer.

6. The ultra-thin tunneling oxide passivation contact solar cell according to claim 5, characterized in that: The thickness of the silicon nitride passivation layer is 70 nm to 150 nm, including both ends.

7. The ultra-thin tunneling oxide passivation contact solar cell according to claim 1, characterized in that: The light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than the light absorption coefficient of the doped polycrystalline silicon layer.

8. The ultra-thin tunneling oxide passivation contact solar cell according to claim 1, characterized in that: The activation impurity concentration of the doped polysilicon layer is 1×10 20 cm -3 -1×10 21 cm -3 , including the values ​​at both ends.

9. The ultra-thin tunneling oxide passivation contact solar cell according to claim 1, characterized in that: The activation impurity concentration of the doped polycrystalline silicon carbide layer is 1×10 20 cm -3 -1×10 21 cm -3 , including the values ​​at both ends.

10. The ultra-thin tunneling oxide passivation contact solar cell according to claim 1, characterized in that: The width of the metal gate line region is 80 μm-200 μm, including both ends; the width of the non-metal gate line region is 1000 μm-2000 μm, including both ends.

11. A method for manufacturing an ultra-thin tunneling oxide passivation contact solar cell according to any one of claims 1 to 5, characterized in that: include: Providing a semiconductor substrate having a front side and a back side disposed opposite to each other; The back surface has a metal gate line region and non-metal gate line regions located on both sides of the metal gate line region; forming an ultra-thin tunneling oxide layer covering the back surface; A doped polysilicon layer and a bottom electrode contact layer are formed, wherein the doped polysilicon layer covers the ultra-thin tunneling oxide layer; a patterned bottom electrode contact layer is formed on a surface of the doped polysilicon layer facing away from the ultra-thin tunneling oxide layer, and the bottom electrode contact layer is located in the metal gate line region; forming a bottom electrode on a surface of the bottom electrode contact layer on a side away from the doped polysilicon layer; Among them, the bottom electrode contact layer includes: an ultra-thin oxide layer located on the surface of the doped polysilicon layer and a doped polycrystalline silicon carbide layer located on the surface of the ultra-thin oxide layer, and the doped polycrystalline silicon carbide layer is used to control the metallization depth of the bottom electrode during the bottom electrode sintering process, so that the bottom electrode forms an ohmic contact with the doped polysilicon layer, and the metallization range does not exceed the doped polysilicon layer.

12. The manufacturing method according to claim 11, characterized in that: Using the same PECVD equipment to sequentially form the ultra-thin tunneling oxide layer, the doped amorphous silicon layer, the unpatterned bottom electrode contact layer and the unpatterned mask layer on the back side; Wherein, the doped amorphous silicon layer is used to form the doped polysilicon layer based on an annealing process; after the bottom electrode contact layer is patterned based on the mask layer, the mask layer is removed.

13. The manufacturing method according to claim 11, characterized in that: The thickness of the doped polysilicon layer is in the range of 10 nm to 40 nm.

14. The manufacturing method according to claim 13, characterized in that: The thickness of the doped polycrystalline silicon carbide is in the range of 40 nm to 140 nm; And / or, the distance between two adjacent bottom electrodes is in the range of 0.85 mm to 0.95 mm.

15. The manufacturing method according to claim 11, characterized in that: The method of forming the doped polysilicon layer and the bottom electrode contact layer comprises: forming a doped amorphous silicon layer on the surface of the ultra-thin tunneling oxide layer; forming an unpatterned ultra-thin oxide layer and a doped amorphous silicon carbide layer in sequence on the surface of the doped amorphous silicon layer; After forming a mask layer on the surface of the doped amorphous silicon carbide layer on one side away from the ultra-thin oxide layer, annealing is performed to convert the doped amorphous silicon layer into a doped polycrystalline silicon layer, and to convert the doped amorphous silicon carbide layer into a doped polycrystalline silicon carbide layer; Patterning the mask layer, wherein the patterned mask layer covers the doped polycrystalline silicon carbide layer located at the metal gate line and exposes the doped polycrystalline silicon carbide layer located at the non-metal gate line area; Based on the patterned mask layer, etching and removing the doped polycrystalline silicon carbide layer located in the non-metallic gate line region; The ultra-thin oxide layer and the mask layer located in the non-metallic gate line region are removed simultaneously; wherein the ultra-thin oxide layer and the mask layer are made of the same material.

16. A TopCon battery, characterized in that: include: A substrate; a surface of one side of the substrate having a metal contact area and a non-metal contact area; The metal contact region is provided with a first tunneling layer, a doped polysilicon layer and an electrode in sequence along a direction away from the substrate; the electrode is in ohmic contact with the doped polysilicon layer; The non-metallic contact region is sequentially provided with a second tunneling layer and a doped polycrystalline silicon carbide layer along a direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than the light absorption coefficient of the doped polycrystalline silicon layer.

17. The TopCon battery according to claim 16, characterized in that The second tunneling layer covers the doped polysilicon layer and the non-metallic contact region; the doped polycrystalline silicon carbide layer covers the second tunneling layer; The electrode penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer and makes ohmic contact with the doped polycrystalline silicon layer.

18. The TopCon battery according to claim 17, characterized in that Also includes: A passivation anti-reflection layer; the passivation anti-reflection layer covers the surface of the doped polycrystalline silicon carbide layer away from the substrate; The electrode penetrates the passivation anti-reflection layer, the doped polycrystalline silicon carbide layer and the second tunneling layer, and is in ohmic contact with the doped polycrystalline silicon layer.

19. The TopCon battery according to claim 18, characterized in that The passivation anti-reflection layer includes any one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, and a magnesium fluoride layer.

20. The TopCon battery according to claim 18, characterized in that The thickness of the passivation anti-reflection layer is 70 nm to 150 nm, including both ends.

21. The TopCon battery according to claim 16, characterized in that The activation impurity concentration of the doped polysilicon layer is 1×10 20 cm -3 -1×10 21 cm -3 , and includes the values ​​at both ends; The thickness of the doped polysilicon layer is 20 nm to 100 nm, including both ends.

22. The TopCon battery according to claim 16, characterized in that The activation impurity concentration of the doped polycrystalline silicon carbide layer is 1×10 20 cm -3 -1×10 21 cm -3 , and includes the values ​​at both ends; The doped polycrystalline silicon carbide layer has a thickness of 20 nm to 50 nm, including both ends.

23. The TopCon battery according to claim 16, characterized in that The width of the metal contact area is 80 μm-200 μm, including both ends; the width of the non-metal contact area is 1000 μm-2000 μm, including both ends.

24. The TopCon battery according to claim 17, characterized in that The doped polycrystalline silicon carbide layer located in the metal contact area is used to control the metallization depth of the electrode during the electrode sintering process, so that the electrode forms an ohmic contact with the doped polycrystalline silicon layer located in the metal contact area, and the metallization range does not exceed the metal contact area.

25. The TopCon battery according to claim 16, characterized in that The distance between two adjacent electrodes ranges from 0.85 mm to 0.95 mm.

26. A method for preparing a TopCon battery, characterized in that: include: In a metal contact region on a surface of one side of the substrate, a first tunneling layer and a doped polysilicon layer are sequentially formed in a direction away from the substrate; A second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially formed in a non-metallic contact region on a surface of one side of the substrate in a direction away from the substrate; the light absorption coefficient of the doped polycrystalline silicon carbide layer is smaller than the light absorption coefficient of the doped polycrystalline silicon layer; After the doped polysilicon layer and the doped polycrystalline silicon carbide layer are prepared, an electrode is prepared in the metal contact region so that the electrode is in ohmic contact with the doped polysilicon layer.

27. The method for preparing a TopCon battery according to claim 26, characterized in that: A second tunneling layer and a doped polycrystalline silicon carbide layer are sequentially prepared in a non-metallic contact region on a surface of one side of the substrate in a direction away from the substrate, comprising: After the doped polysilicon layer is prepared, the second tunneling layer and the doped polycrystalline silicon carbide layer are sequentially prepared on the doped polysilicon layer and the non-metallic contact region in a direction away from the substrate; Accordingly, preparing an electrode in the metal contact region so that the electrode is in ohmic contact with the doped polysilicon layer comprises: The electrode is prepared so that the electrode penetrates the doped polycrystalline silicon carbide layer and the second tunneling layer and is in ohmic contact with the doped polycrystalline silicon layer.

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