Method for fabricating a device comprising a plurality of pixels

Abstract

One aspect of the invention relates to a method for fabricating a device comprising a plurality of pixels, the method comprising a step of forming a first group of pixels (40) on the substrate (11) comprising the following sub-steps: - depositing, on lower electrodes (41) of the pixels deposited on the substrate, a first stack (421) of organic layers and a first conductive layer (16) on the first stack (421) of organic layers; - etching at least a portion of the first conductive layer to form cavities (30) having a depth strictly less than the thickness of the first conductive layer, the cavities being located in line with spaces extending between lower electrodes of the pixels of the first group; - anisotropic etching of the first conductive layer and of the first stack of organic layers so as to extend the cavities through the first conductive layer and the first stack of organic layers, with residual portions (431) of the first conductive layer remaining between the cavities.

Description

DESCRIPTION TITLE: METHOD FOR MANUFACTURING A DEVICE COMPRISING A PLURALITY OF PIXELS TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of optoelectronic devices and components and more particularly that of organic semiconductor devices.

[0002] The present invention relates to a method of manufacturing a device comprising a plurality of OLED (Organic Light-Emitting Diodes) or OPD (Organic Photo-Diodes) pixels.

[0003] The present invention finds an advantageous application for the production of display screens for electronic objects, and in particular for the production of high-resolution color display screens. The expression "high resolution" designates pixels with a size of less than 15 pm. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0004] Generally speaking, an important parameter for matrix displays is to have the brightest and smallest possible emissive surfaces (i.e., pixels).

[0005] In the field of enhanced resolution OLED display devices, OLED-type matrix displays are known which have pixels smaller than 15 pm, typically between 5 pm and 12 pm.

[0006] When this type of matrix display is in color, each pixel is subdivided into subpixels of different colors (typically three, with the colors red, green and blue) which cooperate to make the pixel emit the desired color. Each subpixel is an elementary light source and has a size of less than 10 pm, for example 3 pm or 6 pm.

[0007] Each sub-pixel is generally formed of several superimposed elements, including a lower electrode (the anode) deposited on a common substrate, several organic layers (at least one of which is emissive) forming an OLED stack on each lower electrode, and an upper electrode (the cathode).

[0008] To improve the luminous flux of OLED pixels, OLED display devices are known with multi-stack structure OLED pixels, also called "multistack" structure pixels according to the commonly used English terminology. In such devices, the OLED stack comprises several OLED diodes stacked on top of each other and separated from each other by a conductive interconnection layer (also called CGL for "Charge Generation Layer" in English), generally also of organic nature. The use of several stacked OLED diodes, instead of just one, makes it possible to increase the luminance of the pixel since the luminous fluxes of the OLED diodes add up.

[0009] Due to the complexity of structuring the organic layers with the desired resolution (typically a resolution corresponding to pixels with lateral dimensions of less than 15 pm), it is generally preferred to separate only the lower electrodes from each other to form a multistack OLED pixel matrix. The other elements (OLED stack, conductive interconnection layer, upper electrode) are thus left as layers common to all pixels.

[0010] This arrangement, however, leads to the appearance of crosstalk phenomena between neighboring pixels, also called "crosstalk" in English, which degrade the performance of the display device (essentially, they lead to a distortion of the colors and a blurring of the image displayed by the OLED display device).

[0011] These crosstalk effects are due to capacitive effects between neighboring pixels, or to parasitic currents flowing between neighboring pixels through the common conductive layers of OLED stacks and the interconnect layer. They are exacerbated in the case of multistack structures due to the presence of the conductive interconnect layer(s), which facilitates the flow of currents. They are also exacerbated when the pixel size decreases.

[0012] To reduce crosstalk phenomena, one approach is to discretize all the layers of materials (including organic layers) forming the pixels.

[0013] Documents FR3079909A1 and US2023 / 0041252A1 thus describe separation structures between pixels which allow organic layers to be discretized smoothly.

[0014] The expression "gently" here means without implementing masking and removal steps which generally require environments (humidity, temperature above 90°C, solvents, ultraviolet, etc.) which are harmful to organic materials.

[0015] Document FR3079909 A1 thus describes a first OLED display device in which the lower electrodes of each sub-pixel are separated from each other by an insulating wall rising vertically from the substrate. Each wall acts as a separator between two neighboring sub-pixels.

[0016] This same document FR3079909 describes a second device in which the insulating walls are replaced by trenches in which an insulating layer is deposited.

[0017] The insulating walls and trenches are formed before the organic layers are deposited by thermal evaporation and play the same role. Since the evaporation deposition technique is predominantly directive, the organic layers are preferentially deposited on the horizontal walls of the device, and not on the side walls of the insulating walls or trenches. Each organic layer is thus broken (or discretized) at the level of the insulating walls or trenches.

[0018] However, the directivity of the OLED stack deposition is never complete in practice. Organic particles can also be deposited on the side walls of insulating walls or trenches. However, these particles are undesirable because they degrade the insulation (electrical, optical) between the sub-pixels and contribute to creating the crosstalk phenomena described above.

[0019] Document US2023 / 0041252A1 provides a solution to this problem by describing sub-pixel separators that are arranged on a substrate and have a mushroom-shaped structure (or "hang-over" according to the English terminology used in this document). More specifically, this mushroom structure comprises a lower part having oblique sides, forming the foot of the mushroom. It also comprises an upper part, of width higher than the lower part, which hides a region of the substrate. This upper part forms the cap of the mushroom.

[0020] The subpixels are formed once the mushroom structures are in place. The OLED stack is then deposited on these structures and broken at the upper parts. The breaking of the OLED stack is achieved with satisfactory reliability since no organic particles can be deposited on the region of the substrate hidden by the upper part or on the side walls of the mushroom structure (the lower part is not accessible from the top because it is hidden by the upper part). Thus, the degree of directionality of the OLED stack deposition is of little importance.

[0021] These mushroom structures are, however, particularly complex to produce and not very compact (vertically, they have a height of the order of 1 pm or more). In addition, the production of the common cathode requires the use of deposition equipment specially designed for the manufacture of the device. This involves depositing a metal layer under the upper part of the mushroom structures, at a very specific angle determined by the inclination of the sides of the lower parts. It is therefore not easy, nor economically advantageous, to deploy such a manufacturing process.

[0022] Therefore, there is still a need for a manufacturing process for OLED display devices with high resolution and improved efficiency that is less expensive and simpler to implement. SUMMARY OF THE INVENTION

[0023] The invention offers a solution to the problems mentioned above, by making it possible to discretize all the layers of materials forming each pixel without using separation structures.

[0024] The term "pixel" refers to a subpixel, that is, the smallest element making up a pixel of the organic semiconductor device.

[0025] A first aspect of the invention thus relates to a method of manufacturing a device comprising a plurality of pixels arranged on a substrate, each pixel comprising a lower electrode, an upper electrode, and an active element arranged between the lower and upper electrodes, said method comprising the following steps: Providing a structure comprising the substrate and the lower electrodes of the pixels, the lower electrodes being spaced from each other and arranged on a first surface of the substrate, called the active surface, Formation of a first group of pixels on the substrate, by performing the following sub-steps: Deposition, on the active surface of the substrate, of a first stack of organic layers configured to generate or absorb a first radiation, Deposition of a first conductive layer on the first stack of organic layers, Etching at least part of the first conductive layer to form cavities having a depth strictly less than the thickness of the first conductive layer, the cavities being located at right angles to spaces extending between lower electrodes of the pixels of the first group, Anisotropic etching of the first conductive layer and anisotropic etching of the first stack of organic layers so as to extend the cavities through the first conductive layer and the first stack of organic layers, residual portions of the first conductive layer remaining between the cavities, resulting in the pixels of the first group separated from each other by the cavities.

[0026] Radiation is here understood as light radiation which comprises at least one wavelength in the visible and infrared spectrum, i.e. in the wavelength range extending between 400 nm and 2500 nm.

[0027] Thus, the use, as an etching mask for the stack of organic layers, of a conductive layer (here called the first conductive layer) intended to be partly preserved in the device (the residual portions of this layer are part of the pixels), in other words which partly remains at the end of the manufacturing process, makes it possible to avoid a mask removal step (or "stripping" in English). A mask removal step like those used during the manufacturing of non-organic semiconductor devices is incompatible with OLED (for “Organic Light-Emitting Diodes” in English) or OPD (for “Organic Photo-Diodes” in English) technology.

[0028] Indeed, this mask removal step requires the application, on the substrate, of particularly aggressive environments, and therefore destructive, for the organic layers. This can involve solvents (in the case of a resin mask), exposure to plasma (in the case of a hard mask) and / or the use of high temperatures, above 100°C.

[0029] The manufacturing method according to the invention therefore does not include any step of removing an etching mask which would be in contact with the organic materials constituting the active element of each pixel (because this step is no longer necessary). Thus, the organic materials are preserved. In addition, the method is simpler to implement than the methods of the prior art, based on separation structures between the pixels, and suitable for forming pixels of a size of up to 1 pm (i.e. to achieve the desired high resolution).

[0030] In addition, thanks to the anisotropic etchings of the first conductive layer and the first stack of organic layers, pixels are obtained that are physically separated from each other over their entire height. This avoids electrical crosstalk phenomena since currents can no longer flow between the pixels. This also reduces optical crosstalk phenomena between pixels. Indeed, the cavities that separate the pixels create an index break between the pixels and their external environment, which leads to the confinement of light fluxes in the pixel area.

[0031] Thus, thanks to the invention, an organic semiconductor device with high resolution and better performance is manufactured in a simple manner.

[0032] In addition to the characteristics which have just been mentioned in the preceding paragraph, the manufacturing method according to the first aspect of the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations: The anisotropic etching sub-step is carried out in an oxygen-free atmosphere. The provided structure comprises an electrically insulating layer disposed on the active surface of the substrate and laterally coating the lower electrode of each pixel, the electrically insulating layer serving as a barrier layer during the anisotropic etching of the first stack of organic layers. The step of forming the first group of pixels on the substrate further comprises: between the deposition of the first stack of organic layers and the deposition of the first conductive layer, the deposition of a second conductive layer formed of a metal, between the anisotropic etching of the first conductive layer and the anisotropic etching of the first stack of organic layers, an anisotropic etching of the second conductive layer. The first stack of organic layers is configured to generate the first radiation and the step of forming the first group of pixels on the substrate further comprises: Between the deposition of the first stack of organic layers and the deposition of the second conductive layer, the following operations: Depositing a conductive interconnection layer on the first stack of organic layers, the conductive interconnection layer being adapted to connect the first stack of organic layers to a second stack of organic layers, Deposition of the second stack of organic layers on the conductive interconnection layer, Between the anisotropic etching of the second conductive layer and the anisotropic etching of the first stack of organic layers, an anisotropic etching of the interconnecting conductive layer and an anisotropic etching of the second stacking of organic layers, resulting in pixels separated from each other and having a tandem structure. The conductive interconnection layer is formed of a metallic or organic conductive material. The first conductive layer is formed from a metal and has an initial thickness determined so that the thickness of the residual portions of the first conductive layer is less than 20 nm, preferably between 10 nm and 20 nm. The first conductive layer is formed of a conductive and transparent material such as a transparent conducting oxide (TCO). The manufacturing method may comprise, after the step of forming the pixels on the substrate, a step of depositing a passivation layer on the edges of the pixels and on the surface of the substrate. The deposition of the passivation layer is carried out in a compliant manner. The manufacturing method may comprise, after the step of depositing the passivation layer, a step of forming a common electrode comprising the following sub-steps: Opening the passivation layer so as to create access to the upper electrode of each pixel, Formation of a third continuous conductive layer on the pixels and on the substrate between the pixels and on an electrical contact track arranged on a second surface of the substrate peripheral to the active surface, resulting in the common electrode connecting the upper electrode of each pixel to the electrical contact track. The third conductive layer can be transparent. Alternatively, the third conductive layer is reflective and the substrate is transparent. When the conductive layer is reflective, the third conductive layer has a thickness greater than 50 nm. The manufacturing method may comprise, after the step of depositing the passivation layer, a step of forming a second group of pixels on another part of the lower electrodes, comprising the following sub-steps: Opening the passivation layer so as to create access to each lower electrode of the pixels of the second group, Deposition, on the active surface of the substrate, of a third stack of organic layers configured to generate radiation distinct from the first radiation, Deposition of a fourth conductive layer on the third stack of organic layers, Etching at least a portion of the fourth conductive layer to form cavities having a depth less than or equal to the thickness of the fourth conductive layer, the cavities being located in line with spaces extending between lower electrodes of the pixels of the second group, Anisotropic etching of the fourth conductive layer and anisotropic etching of the third stack of organic layers so as to extend the cavities through the fourth conductive layer and the third stack of organic layers, residual portions of the fourth conductive layer remaining between the cavities, resulting in, in addition to the pixels of the first group, the pixels of the second group separated from each other by the cavities.

[0033] A second aspect of the invention relates to a method of manufacturing a device comprising a plurality of pixels arranged on a substrate, each pixel comprising a lower electrode, an upper electrode, and an active element arranged between the lower and upper electrodes, said method comprising the following steps: Providing a structure comprising the substrate and the lower electrodes of the pixels, the lower electrodes being spaced from each other and arranged on a first surface of the substrate, called the active surface, Formation of a first group of pixels on the substrate, by performing the following sub-steps: Deposition, on the active surface of the substrate, of a first stack of organic layers configured to generate or absorb a first radiation, Deposition of a second conductive layer formed of a metal on the first stack of organic layers, Deposition of a first conductive layer on the first stack of organic layers, Etching at least a portion of the first conductive layer to form cavities having a depth less than or equal to the thickness of the first conductive layer, the cavities being located in line with spaces extending between lower electrodes of the pixels of the first group, Anisotropic etching of the first conductive layer and anisotropic etching of the first stack of organic layers so as to extend the cavities through the first conductive layer, the second conductive layer and the first stack of organic layers, residual portions of the first conductive layer remaining between the cavities, resulting in the pixels of the first group separated from each other by the cavities.

[0034] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0035] The figures are presented for information purposes only and in no way limit the invention. Figure 1 shows, in schematic form, a sectional view of an example pixel of an electroluminescent display device, Figures 2 to 14 represent a first embodiment of a method for manufacturing an electroluminescent display device according to the invention, Figures 15 to 19 represent a second embodiment of the method for manufacturing an electroluminescent display device according to the invention, Figure 20 represents a third embodiment of the method for manufacturing an electroluminescent display device according to the invention, Figure 21 represents a fourth embodiment of the method for manufacturing an electroluminescent display device according to the invention. DETAILED DESCRIPTION

[0036] The present invention aims to improve the manufacturing methods of devices comprising an array of organic pixels (i.e. pixels made partly of organic materials). The present invention relates in particular to a manufacturing method which aims to improve the pixel separation phase. More particularly still, the present invention aims to physically separate the pixels from each other in a simpler manner than the state-of-the-art solutions based on separation elements between the pixels.

[0037] The present invention finds, for example, an advantageous application for the manufacture of devices comprising an OLED (Organic Light Emitting Diode) pixel matrix with improved resolution, also called OLED electroluminescent display devices or OLED micro-displays. The present invention in fact makes it possible to obtain display devices that are convenient to manufacture and of better quality, since the crosstalk phenomena between OLED pixels are reduced.

[0038] Naturally, the present invention can also be applied to the manufacture of other OLED type display devices, such as OLED screens for television applications or any other light source based on OLED pixels. The present invention can furthermore be applied to the manufacture of devices comprising an OPD (for "Organic Photo-Diode") pixel matrix.

[0039] Figures 2 to 11 illustrate a first mode of implementation of a manufacturing method in accordance with the invention, preferably used to produce an electroluminescent display device.

[0040] Figure 7 shows, in schematic form, a first embodiment of an OLED electroluminescent display device 1 (also referred to as “display device 1” hereinafter) obtained at the end of a step E2 of forming a first group of pixels on a substrate, according to the first embodiment of the manufacturing method.

[0041] As shown in FIG. 7, the first embodiment of the display device 1 comprises a plurality of pixels 40 arranged on a substrate 11.

[0042] The substrate 11 has an upper surface 11a (also referred to as the “surface of the substrate 11” hereinafter) which extends in a plane {X,Y}. This plane defines the plane of the substrate. The directions and dimensions will subsequently be designated according to this plane {X,Y} of the substrate. Thus, the term “lateral” designates a direction included in the plane of the substrate 11 or in a plane parallel to the plane of the substrate 10, while the term “vertical” designates a direction along a Z axis perpendicular to the plane {X,Y} of the substrate. The terms “height”, “thickness” and “depth” refer to dimensions measured perpendicular to the plane {X,Y} of the substrate, i.e. along the Z axis. The term “length” refers to a dimension measured in a plane parallel to the plane of the substrate 11.

[0043] The substrate 11 is advantageously a specialized circuit or ASIC (for “Application Specific Integrated Circuit”) of CMOS type (for “Complementary Metal Oxide Semiconductor”) formed from a silicon wafer. This type of circuit is in fact well suited to addressing pixels 40 with lateral dimensions of less than 15 pm. Note that such a substrate 11 is opaque and that the display device 1 is then of the top emission type (or “TOP emission” according to the terminology commonly used). In the remainder of the description, the terms "transparent" and "opaque" refer to an element which, for at least one wavelength in the 400-800 nm spectral band, has an optical transmission coefficient of respectively greater than 60% and less than or equal to 60%.

[0044] Alternatively, the substrate 11 may comprise thin film transistors or TFTs (for “Thin Film Transistor” in English) made with amorphous silicon, polycrystalline silicon and / or deposited on a glass plate. The substrate 11 may thus be transparent. The display device 1 may then be of the bottom emission type (or “BOTTOM emission” according to the terminology commonly used).

[0045] The substrate 11 comprises an addressing circuit and a plurality of contact pads 1 13 of the pixels (for greater readability, the addressing circuit is not shown in Figure 7 or in the other figures, and the contact pads 1 13 are only shown in Figures 2 and 9).

[0046] The addressing circuit is configured to address 40 pixels.

[0047] The contact pads 1 13 are formed from a conductive material. They are spaced from each other and are flush with the surface 1 1 a of the substrate 1 1 . The contact pads 1 13 make it possible to make an electrical connection between each pixel 40 and the addressing circuit.

[0048] For a display device with improved resolution, the pixels 40 preferably have lateral dimensions of less than 15 μm, preferably between 15 μm and 3 μm, for example equal to 4 μm. In top view, they advantageously have a square shape. The size of the pixels will hereinafter designate the side of the square.

[0049] As shown in the boxed portion of Figure 7, each pixel 40 comprises a lower electrode 41 disposed on the substrate 11, an upper electrode 43 and an active element 42 disposed between the lower electrode 41 and the upper electrode 43.

[0050] The lower electrode 41 of the pixel is preferably formed from one or more metals, advantageously chosen from the following metals: silver (Ag), chromium (Cr), Aluminum (Al), Titanium (Ti).

[0051] The lower electrode 41 is preferably reflective for a top-emitting device. In this case, its thickness is greater than 15 nm. The reflective lower electrode 41 is preferably used when the substrate 11 is opaque.

[0052] Alternatively, the lower electrode 41 is transparent for a bottom-emitting device. In this case, its thickness is less than 15 nm. The transparent lower electrode 41 is preferably used when the substrate 11 is transparent.

[0053] The lower electrodes 41 of the pixels are preferably formed by structuring a conductive layer or several conductive layers stacked and formed from different conductive materials.

[0054] Referring to Figure 7, the lower electrode 41 has a lower face 41a connected to the surface 11a of the substrate and an opposite upper face 41b connected by a peripheral lateral surface. The lower electrode 41 also has a height e4i.

[0055] The lower electrode 41 finally has, in a plane parallel to the plane {X,Y} of the substrate, a surface, or section, which can take different shapes (square, circular, rectangular, etc.).

[0056] In Figure 7, the section of the lower electrode 41 is here square in shape. The peripheral lateral surface 41 d is then made up of four facets corresponding to the four lateral faces (also called peripheral edges hereinafter) 41 c of the lower electrode 41 . In the sectional view of Figure 7, two of these side walls 41 c are visible.

[0057] The section of the lower electrode 41 corresponds to the emission surface of the pixel 40. For high-resolution display devices, this emission surface is advantageously less than 15x15 pm 2 , preferably between 3x3 pm 2 and 12x12 pm 2 , and for example equal to 4x4 pm 2 .

[0058] The lower electrode 41 is electrically connected to one of the contact pads of the substrate 11.

[0059] The active element 42 of the pixel is arranged on the upper face 41a of the lower electrode 41. It has a height e42.

[0060] In the example shown in Figure 7, the active element 42 is of tandem structure, that is to say that it successively comprises, starting from the lower electrode 41 and in the vertical direction, the following sub-elements: a first electroluminescent sub-element formed from a first OLED stack 421, a conductive charge generation layer CGL (for “Charge Generation Layer” in English), and a second electroluminescent element formed from a second OLED stack 422.

[0061] This tandem structure is described in more detail below in relation to Figure 1.

[0062] The first and second OLED stacks 421, 422 both comprise organic layers, at least one of which is emissive (denoted EM421 and EM422 in FIG. 1).

[0063] Preferably, each OLED stack 421, 422 successively comprises the following organic layers: a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emissive layer EM421, EM422, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL.

[0064] The injection, transport and blocking layers are conductive.

[0065] The term "organic emissive layer" EM421, EM422 refers to an organic layer which has the property of generating radiation when a voltage is applied between the lower and upper electrodes of the pixel.

[0066] Radiation is here understood as light radiation which comprises at least one wavelength in the visible and infrared spectrum, i.e. in the wavelength range extending between 400 nm and 2500 nm.

[0067] Hereinafter, "white light radiation" will be used to refer to radiation whose spectrum extends between 400 nm and 800 nm, while a color radiation will designate a light radiation whose spectrum is centered around the wavelength corresponding to the color. Thus: radiation in the blue has a wavelength spectrum centered on a blue, for example a spectrum located mainly between 430 nm and 490 nanometers radiation in the green has a spectrum centered on a green, for example a spectrum located mainly between 490 nm and 590 nm, and radiation in the red has a spectrum centered on a red, for example a spectrum located mainly between 590 nm and 700 nm.

[0068] The emissive layer EM421 of the first OLED stack 421 and the emissive layer EM422 of the second OLED stack can be configured to generate radiation of different colors, so that the active element 42 emits white light radiation.

[0069] The charge generation layer CGL separating the two OLED stacks may be an organic conductive layer whose conductivity has been modulated using a doping technique. Alternatively, the charge generation layer CGL separating the two OLED stacks 421, 422 may be an undoped organic semiconductor layer.

[0070] Alternatively, the CGL layer may be a metallic conductive layer. The use of a metal rather than an organic semiconductor layer makes it possible to improve the injection of charge carriers into the OLED diodes arranged on either side of this CGL layer. Thus, the use of the two electroluminescent sub-elements 421 and 422 is optimized (each electroluminescent sub-element 421, 422 is crossed by a greater current density). In other words, by increasing the conductivity of the charge transfer GGL layer, a doubled luminance, compared to the use of a single electroluminescent element, is obtained with an identical current density. The pixel 40 is thus brighter and has an extended operational lifetime.

[0071] The upper electrode 43 of the pixel is a conductive element which covers the active element 42 (on its upper face) and terminates (from the top) the pixel 40. It has a thickness noted e43 in figure 7.

[0072] The pixel 40 then has a height h4o which is equal to the sum of the thickness e4i of the lower electrode 41, the thickness e42 of the active element 42 and the thickness e43 of the upper electrode 43 (see FIG. 7). This height h4o of the pixel is preferably between 100 nm and 200 nm, for example equal to 150 nm.

[0073] The upper electrode 43 comprises, in this first embodiment, two superimposed conductive portions 431, 432, the second portion 432 being arranged on the active element 42 and the first portion 431 being arranged on the second portion 432. The thickness e43 of the upper electrode 43 is then equal to the sum of the thickness 6431 of the first portion 431 and the thickness 6432 of the second portion 432.

[0074] The second portion 432 of the upper electrode 43 makes it possible to create an optical microcavity effect in the pixel 40 (the microcavity being delimited between the lower electrode 41 and the first portion 431 of the upper electrode).

[0075] Depending on the configuration chosen for the active element 42 of the pixel 40 (including its height h42 or the optical index of the organic layers forming this active element 42), this microcavity effect makes it possible to select radiation of a given color from the white light radiation obtained at the output of the active element 42.

[0076] The configuration of the active element 42 can thus be chosen so that the pixel 40 produces light radiation in blue, green or red.

[0077] The upper electrode 43 is transparent when the substrate 11 is opaque.

[0078] The upper electrode 43 is preferentially reflective when the substrate 11 is transparent.

[0079] Now that each pixel 40 has been described, the arrangement of the pixels relative to each other is described in more detail.

[0080] The pixels 40 occupy a surface of the substrate 11 called the active surface SACT (see figure 7). This active surface SACT of the substrate 11 extends for example between 10 mm 2 and 5 cm 2 for OLED micro-displays.

[0081] On this active surface SACT, the pixels 40 are preferably arranged in rows and columns. In other words, they are arranged with a first repetition pitch in a first direction included in the plane of the substrate (for example the X direction) and with a second repetition pitch in a second direction (for example the X direction). example Y) secant to the first direction. Thus, the pixels 40 form a matrix of electroluminescent elements.

[0082] Advantageously, the 40 pixels all have an identical shape (within manufacturing tolerances).

[0083] As shown in Figure 7, the pixels 40 are physically separated from each other, over their entire height h4o. In other words, a trench 30 free of organic layers and conductive layers is arranged between two neighboring pixels 40 (or separates, or even spaces, two neighboring pixels 40).

[0084] This trench 30 extends over a length, defined as the distance d4o between a side wall of a lower electrode 41 and the side wall opposite the neighboring lower electrode 41, which is preferably less than or equal to 1 pm, preferably between 500 nm and 1 pm, for example equal to 800 nm.

[0085] Since no layer (organic, conductive) is common to all the pixels, no current can flow between the pixels 40. This avoids the appearance of electrical crosstalk phenomena between neighboring pixels 40. This makes it possible to obtain a display device 1 that is both brighter (thanks to the tandem structure of the active elements 42) and better display resolution (thanks to the trenches 30 between the pixels 40).

[0086] Another advantage of physically separating the pixels 40 from each other is to limit the phenomena of optical crosstalk between the pixels 40. The presence, between the pixels 40, of an area free of organic layers and conductive layers in fact makes it possible to achieve a break in optical index at the outer limits of each pixel 40. This break in optical index is favorable to the confinement of the radiation emitted by each pixel in the area of ​​the pixel 40. The reduction of the phenomena of optical crosstalk contributes to improving the display resolution of the display device 1.

[0087] Note that, in the display device shown in Figure 7, all the pixels 40 have a height h4o and lateral dimensions that are identical (within manufacturing tolerances) and their elements 41, 42, 43 are all of identical nature (i.e. formed from the same materials). The display device is then monochrome (all the pixels 40 produce the same radiation).

[0088] Figure 19 represents a second embodiment of the display device 1.

[0089] This second embodiment differs from the first embodiment (illustrated in FIG. 7) only in that the pixels 40 do not all produce the same light radiation.

[0090] According to this second embodiment, the display device 1 thus comprises three groups of pixels 40I, B, 402, V and 40a, R configured to produce three radiations having distinct colors, for example a red R, a green V and a blue B. The pixels of the three groups are advantageously arranged alternately: a pixel 402, v of green radiation arranged between a pixel 40I, B of blue radiation and a pixel of red radiation 40a, R. The overall radiation emitted by these three pixels 40I, B, 402, v, 40a, , which corresponds to the combination of these three radiations, can be adjustable according to the light intensities of the three pixels. The display device is then a color display device.

[0091] Figure 20 shows a third embodiment of the display device 1.

[0092] This third embodiment differs from the first embodiment illustrated in FIG. 19 in that the active element 42 of each pixel comprises a single electroluminescent sub-element (or first OLED stack 421). This makes it possible to obtain a display device which is certainly less bright than the first and second embodiments, but simpler to produce.

[0093] It is noted that the presence of the trenches 30 between the pixels 40 makes it possible, as for the first and second embodiments, to reduce, or even eliminate, the phenomena of electrical and optical crosstalk between the pixels 40. These phenomena also exist (although to a lesser extent compared to tandem pixel devices) in single OLED display devices.

[0094] The third embodiment is further distinguished from the first and second embodiments in that the upper electrode 43 of the pixels 40 is preferably formed from a single conductive portion 431 (instead of two conductive portions 431, 432). This single conductive portion 431 is then formed from a metal (silver, aluminum, titanium, etc.). It can also have a thin thickness e43i, less than 15 nm so as to be transparent. This configuration is preferred when the substrate 11 is opaque.

[0095] The use of a single conductive portion 431 instead of two makes it possible to reduce the number of manufacturing steps and therefore to simplify the manufacture of the display device 1.

[0096] Note that this third embodiment makes it possible to produce a monochrome display device. Indeed, the active elements 42 of the pixels 40 can all be configured identically, like the pixels 40 of the first embodiment illustrated in FIG. 7.

[0097] According to a variant, the active element of each pixel 40 of the device shown in FIG. 20 may, alternatively, be formed from a stack of organic layers configured to absorb (and not generate) visible or infrared radiation. In this case, the pixels are OPD pixels (for “organic Photo-Diode” in English).

[0098] Figure 21 shows a fourth embodiment of the display device 1.

[0099] According to this fourth embodiment, the device 1 comprises, like the third embodiment, pixels of simple OLED structure.

[0100] Thus, the active elements 42I, B 422, V 423, R of the pixels are formed only from a stack of organic layers 4211, 4212, 421 a.

[0101] Like the third embodiment, the fourth embodiment of the device 1 comprises three groups of pixels 40I,B, 402,V and 40a,R.

[0102] Preferably, the color of the radiation produced by each group of pixels is obtained directly by the configuration of the OLED stack 421, 4212, 4213 of the pixels 40. In other words, the active element 42I,B of each pixel 40I,B of the first group is formed of a first stack configured to produce radiation in the blue, while the active element 422,v of each pixel 402,v of the second group is formed of a second stack configured to produce radiation in the green, and the active element 423,R of each pixel 403,R of the third group is formed of a third stack configured to produce radiation in the red.

[0103] Obtaining the color radiation directly at the level of the active elements 42 of the pixels makes it possible to do without a color filter and to obtain brighter color pixels.

[0104] The method of manufacturing the display device 1 according to the first embodiment will now be described in relation to FIGS. 2 to 7.

[0105] As shown in Figure 2, the method 1 begins with a step E1 consisting of providing a structure 10 comprising the substrate 11 and the lower electrodes 41 of the pixels, these being spaced from each other (and therefore electrically insulated from each other).

[0106] The surface of the substrate 11 which is occupied by the lower electrodes 41 corresponds to an active surface SACT of the substrate 11.

[0107] These lower electrodes 41 can be formed by well-known operations of deposition, lithography, etching and mask removal (or “stripping” in English).

[0108] The structure 10 may also comprise an electrically insulating layer 12 which extends over the active surface SACT of the substrate 11 and laterally coats each lower electrode 41 (i.e. which covers the lateral peripheral surface of each lower electrode 41).

[0109] In addition to providing effective electrical insulation between the lower electrodes 41, the insulating layer 12 also serves, as will be described later, as an etch stop layer.

[0110] The insulating layer 12 may be formed from silicon dioxide (SiC).

[0111] The structure 10 further comprises an electrical track 13 arranged on a surface of the substrate 11 (also referred to as the “peripheral surface SPERI” hereinafter) located at the periphery of the active surface SACT. This electrical track 13 is electrically connected to the contact pads 113 of the substrate 11 via conductive connections 111. In FIG. 2, the contact pads 113 which are shown allow, as will be explained hereinafter, the creation of an electrical connection between the upper electrode 43 of each pixel 40 and the electrical track 13.

[0112] The multiplicity of these contact pads allows for better current distribution across the upper electrodes of the pixels, compared to a single contact point.

[0113] Figures 3 to 7 illustrate a step E2 of forming a first group of pixels 40 on the substrate 11.

[0114] The number of pixels of the first group may correspond, as illustrated in FIG. 7, to the number of lower electrodes 41 arranged on the substrate 11. Thus, all the pixels 40 of the display device 1 are formed during step E2.

[0115] Step E2 includes a sub-step E21 of depositing layers of materials and two etching sub-steps E22 and E23.

[0116] With reference to figure 3, step E2 begins with sub-step E21 which consists of successively depositing, on the active surface SACT of the substrate 11, the materials forming the active element 42 (see figure 7) and the upper electrode 43 of the pixels 40.

[0117] More specifically, sub-step E21 includes the following operations: Deposition E21 1 of the first stack 421 of organic layers on the active surface SACT of the substrate 1 1 (in this case on the insulating layer 12), Deposition E212 of the CGL layer on the first stack 421 of organic layers, Deposition E213 of the second stack 422 of organic layers on the CGL layer, Deposition E214 of a second conductive layer 17 on the second stack 422 of organic layers, and Deposition E215 of a first conductive layer 16 on the second conductive layer 17.

[0118] It is specified that the deposits E21 1 to E215 are preferably made using a stencil which exposes the active surface SACT of the substrate 1 1 and protects the peripheral surface SPERI of the substrate 1 1 .

[0119] In addition, the deposits of the materials are preferably carried out according to a directional process (in a direction perpendicular to the plane {X,Y} of the substrate 1 1 ), preferably by a physical vapor deposition process such as evaporation.

[0120] The first conductive layer 16 is intended to form the first conductive portions 431 of the upper electrodes 43 of the pixels 40 (see figure 7). The initial thickness e-æ (see figure 4) of this first conductive layer 16 is to be adjusted according to the thickness e43 (see figure 7) desired for the upper electrode 43 of each pixel 40. The initial thickness e-ie of the first conductive layer 16 is thus, for example, between 30 nm and 100 nm.

[0121] The first conductive layer 16 may be formed from a metal such as aluminum (Al), silver (Ag), or chromium (Cr) for a “bottom emitting” type display device 1.

[0122] Alternatively, the first conductive layer 16 may be formed from a conductive and transparent material chosen (but not limited to) from the following materials: Poly(3,4-ethylenedioxythiophene) (or PEDOT), indium-tin oxide (or ITO for “Indium Tin Oxide” in English), tin dioxide (SnO2), zinc oxide (ZnO) or aluminum-doped zinc oxide (or AZO).

[0123] The second conductive layer 17 is intended to form the second conductive portions 432 of the upper electrodes 43 of the pixels 40.

[0124] The second conductive layer 17 is preferably formed from a metal, for example silver (Ag).

[0125] To obtain second transparent conductive portions 432, the second conductive layer 17 has a thickness of less than 20 nm, for example between 10 nm and 20 nm.

[0126] At the end of sub-step E21, all of the materials intended to form the pixels 40 have been deposited on the active surface SACT of the substrate 11. The layers obtained 421, CGL, 422, 17, and 16 form a stack denoted E p in Figure 3.

[0127] Figures 4 to 6 illustrate operations implemented during sub-step E22.

[0128] With reference to figure 5 or with reference to figure 6, this sub-step E22 consists of etching at least a portion of the first conductive layer 16 to form cavities 30 having a depth eso less than or equal to the thickness e-ie of the first conductive layer 16. These cavities 30 are located in line with the spaces 40B extending between lower electrodes 41 of the pixels 40. These spaces 40B correspond to the spaces provided between the pixels 40.

[0129] The etching sub-step E22 is described in detail below.

[0130] With reference to figure 4, sub-step E22 begins with an operation E221 of forming an etching mask 20, for example in photosensitive resin, on the first conductive layer 16. Photo-lithographic methods known to those skilled in the art are implemented for this.

[0131] In Figure 4, the spacing 20B between two neighboring portions 20A of the etching mask 20 corresponds here to the spacing 40B between two neighboring lower electrodes 41. Furthermore, each portion of the etching mask 20 corresponds to a zone 40A of one of the lower electrodes 41.

[0132] Then, as illustrated in FIG. 5, a first etching operation E222 of the first conductive layer 16 is carried out through the etching mask 20 to form the cavities 30.

[0133] This first etching operation E222 may be partial, as shown in Figure 5: in fact, the cavities 30 do not pass through the first conductive layer 16. There therefore remains a residual layer of the first conductive layer 16 on the second conductive layer 17.

[0134] Each cavity 30 preferably has a depth eso of between 10 nm and 300 nm. The thickness e-ie' of the first conductive layer arranged under the cavities 30 (also referred to as "first residual conductive layer") is for example 100 nm.

[0135] Alternatively, the first etching operation E222 may be configured to reach the second conductive layer 17. In this configuration, not shown in the figures, the cavities 30 pass through the first conductive layer 16 and their bottom consists of the upper surface of the second conductive layer 17.

[0136] The first etching operation E222 is preferably a dry etching type etching, such as reactive ion etching (RIE), induced-coupled plasma etching (ICP), or ion beam etching (IBE).

[0137] As shown in Figure 5, when the etching operation E222 is partial, the first etching operation E222 makes it possible to obtain a first conductive layer 16 that is thicker at the lower electrodes 41 of the pixels 40 than at the regions 40B between the lower electrodes 41 of the pixels 40.

[0138] Finally, a removal E223 of the etching mask 20 is implemented. We thus obtain the structure illustrated in figure 6.

[0139] The fact that the cavities 30 obtained (after the first etching operation E222) in the first conductive layer 16 are not through (in the configuration shown in FIG. 5) produces a double effect: on the one hand, the first residual conductive layer protects the organic layers of the stack Ep during the removal E223 of the etching mask 20 and, on the other hand, it makes it possible to leave, after the sub-step E23 described below, portions 431 of this first conductive layer 16 on either side of the cavities 30.

[0140] In the configuration where the second conductive layer 17 is present and the etching E222 continues up to this second conductive layer 17), it is the second conductive layer 17 which protects the underlying organic layers (of the stack E p ) when removing E223 from the etching mask. In addition, portions of the first conductive layer 16 remain on either side of the cavities 30.

[0141] In the following sub-step E23, the following operations are carried out to extend the cavities 30 to the substrate (in this case, to the insulating layer 12): anisotropic etching E231 of the first conductive layer 16 so that the cavities pass through the first conductive layer 16 still present, anisotropic etching E232 of the second conductive layer 17 so that the cavities 30 pass through the second conductive layer 17, anisotropic etching E233 of the second stack 422 of organic layers so that the cavities 30 pass through this second stack of organic layers, anisotropic etching E234 of the CGL layer so that the cavities pass through the CGL layer, and anisotropic etching E235 of the first stack 421 of organic layers so that the cavities 30 pass through the first stack 421 of organic layers.

[0142] Anisotropic etching means etching carried out in a preferential etching direction perpendicular to the plane {X,Y} of the substrate 1 1 . The anisotropic etching makes it possible to preserve the topology (i.e. the profile of the cavities 30) of the first conductive layer 16 as obtained after the etching sub-step E22.

[0143] The anisotropic etching is preferably performed using a ballistic physical etching process. Thus, etching is prevented on either side of the cavities. The ballistic etching makes it possible to extend the cavities 30 while reducing the risk of damaging the organic layers of the stacks 421, 422 between the cavities 30.

[0144] Anisotropic etchings are preferably carried out in an oxygen-free atmosphere. The absence of oxygen allows the performance of organic layers to be best preserved since they are particularly sensitive to this element.

[0145] For example, anisotropic etchings are performed in a vacuum using a physical ballistic etching process, preferably by exposure to argon plasma.

[0146] As shown in Figure 7, the pixels 40 are formed at the end of sub-step E23 and are separated from each other by the cavities 30.

[0147] Thus, initially, the anisotropic etching of the first conductive layer 16 makes it possible to uniformly reduce (i.e. in the same way over the entire surface of the first conductive layer 16) the thickness of the first conductive layer 16.

[0148] Since the anisotropic etching of the first conductive layer 16 is carried out until the cavities 30 open onto the second conductive layer 17, the remaining first conductive layer 16 is made up of conductive portions 431 spaced apart from each other (see FIG. 7).

[0149] The remaining portions 431 of the first conductive layer 16 are illustrated in FIG. 7. These conductive portions 431 remain on either side of the cavities 30, where the thickness of the first conductive layer (after the etching sub-step E22 and before the etching sub-step E23) was the thickest. Each portion 431 of the first conductive layer 16 corresponds to, or constitutes, one of the first conductive portions 431 of the upper electrodes 43 of the pixels 40. Tl

[0150] Thus, the depth eso of the cavities 30 is less than 20 nm, preferably between 10 nm and 20 nm to obtain transparent first conductive portions 431. This configuration is chosen when the substrate 11 is opaque and the second conductive layer 17 is transparent. This makes it possible to obtain a top-emitting type device.

[0151] Alternatively, the depth eso of the cavities 30 is strictly greater than 15 nm to obtain first reflective conductive portions 431. This configuration is preferentially chosen when the substrate 11 is transparent. This makes it possible to obtain a top-emitting type device.

[0152] In a second step, the underlying layers 17, 422, CGL, 422 to the first conductive layer 16 are anisotropically etched through the remaining first conductive layer 16 which serves as an etching mask. Thus, the first conductive portions 431 are not removed.

[0153] Anisotropic etchings E232, E233, E234 and E235 can be performed with the same etching chemistry or with different etching chemistries, implemented in the same etching chamber or in different chambers of the same equipment.

[0154] Preferably, the underlying layers 17, 422, CGL, 422 to the first conductive layer 16 are further selectively etched relative to the first conductive layer 16.

[0155] Note that pixel formation step E3 is analogous to the steps used for manufacturing inorganic semiconductor devices, but does not include any mask removal operation (since this operation is not necessary).

[0156] This allows the OLED pixels to be physically separated without damaging the organic layers. Indeed, it avoids applying solvents (in the case of a resin mask), plasmas (in the case of a hard mask) and / or high temperatures, above 100°C, to the substrate and therefore to the environment of organic layers, which are particularly aggressive, and therefore destructive, for organic layers.

[0157] Furthermore, because the manufacturing process includes technological steps commonly used for the manufacture of devices inorganic semiconductors, it is simpler than prior art methods based on separation structures between pixels. The method also makes it possible to form pixels down to 1 pm or even smaller (i.e. to achieve the desired high resolution).

[0158] Now that the pixels 40 have been formed, the manufacturing process can advantageously continue with steps E3, E4 and E5.

[0159] Step E3, illustrated in FIG. 8, consists of depositing, in a conformal manner, a passivation layer 50 on the substrate 11 and on the periphery of the pixels 40. A conformal deposition technique is preferably implemented. For example, an atomic thin layer deposition technique (or pure ALD) is implemented.

[0160] The passivation layer 50 is formed from a material that acts as a barrier to oxygen. For example, it is formed from alumina or SiO. The passivation layer 50 thus makes it possible to protect the active elements 43 from the external environment. In particular, it prevents the organic layers of these active elements from coming into contact with oxygen (they are particularly sensitive to this element).

[0161] The encapsulation layer 50 is also electrically insulating. This therefore makes it possible to reinforce the electrical insulation of the pixels.

[0162] Step E4, illustrated in Figures 9 and 10, consists of forming a common electrode 60 electrically connecting the upper electrode of each pixel to the electrical track 13 arranged on the peripheral surface of the substrate 11.

[0163] This common electrode 60 makes it possible to bring the current to the upper electrodes of the pixels 40.

[0164] Step E4 therefore comprises a sub-step E41, illustrated in FIG. 9, which consists of opening the passivation layer 50 on the upper face of the pixels 40. By thus releasing a part of the passivation layer 50 on the pixels, an access 43a to the upper electrode 43 of each pixel 40 is created.

[0165] Masking operations using an etching mask (for example using a photosensitive resin), then etching and removing the etching mask are for example carried out during this step E41. Like the passivation layer 50 remains on the sides of the pixels 40, it protects the organic layers of the stacks 421, 422 from the external environment.

[0166] Since the height h4o of the pixels 40 is preferably between 100 nm and 200 nm, and the distance d4o between the pixels 40 is preferably between 500 nm and 1 pm, the ratio between the height h4o of the pixels and their spacing d4o is preferably between 0.1 and 0.4. This ratio is favorable to efficient spreading of the photosensitive resin between the pixels 40.

[0167] Preferably, openings 113a are also created at this sub-step through the insulating layer 12 between the pixels 40, so as to free access to the contact points 113 of the substrate 11 (see FIG. 2).

[0168] With reference to figure 10, a sub-step E42 is then implemented to form a third conductive layer 60 of continuous thickness which extends over the edges of the pixels 40, over the first passivation layer 50 between the pixels 40 and up to the electrical contact track 13.

[0169] As openings 43a have been created in the passivation layer 50 at the level of the upper electrodes 43 of the pixels 40 (see Fig. 9), the third conductive layer is also deposited in contact with these upper electrodes 43. The common electrode 60 is thus formed at least in part by the third conductive layer 60.

[0170] When openings 1 13a are also created through the insulating layer 12, the third conductive layer 60, and therefore the common electrode 60, connects each contact pad 1 13 of the substrate 1 1 . Thus, the distribution of the current through each pixel 40 is carried out from a contact pad 1 13 located near the pixel 40. This proximity of distribution makes it possible to reduce the contact resistance and to standardize the distribution of the current through the pixels 40 of the display device 1 .

[0171] The third conductive layer 60 is preferably formed using a directional deposition method (along a direction perpendicular to the plane {X,Y} of the substrate 11), preferably using a physical vapor deposition method such as evaporation. It is noted that, since the height h4o of the pixels is small compared to the distance between the pixels (for example, there is a factor of 0.1 between this height and this distance), such a directional deposition method makes it possible to deposit conductive material also on the lateral peripheral surface of the pixels 40 (in addition to the surfaces horizontal). This eliminates the need to implement a more complex and costly compliant filing process.

[0172] This third conductive layer 60 may be formed from a metal, for example silver, aluminum, or chromium.

[0173] It can then have a thickness of less than 15 nm to be transparent. Such a thickness is preferred in the case where the substrate 11 is opaque and the lower electrodes are reflective. This makes it possible to obtain a top-emitting display device.

[0174] Alternatively, it may have a significant thickness, for example greater than 300 nm, to be reflective, in the case where the substrate 11 is transparent and where the lower electrodes and / or the upper electrodes are also transparent. This makes it possible to obtain a bottom emission type display device.

[0175] Alternatively, the third conductive layer 60 may be formed from a transparent conductive oxide or TCO.

[0176] With reference to figure 11, step E5 consists of forming a second conformal passivation layer 70 on the third conductive layer 60. The second passivation layer 70 can be formed from the same material as the first passivation layer 50. It makes it possible to encapsulate and therefore protect and electrically insulate the display device.

[0177] Figures 12 to 18 illustrate a second embodiment of the manufacturing method for manufacturing the electroluminescent display device 1 illustrated in Figure 19 (i.e., the second embodiment of the electroluminescent display device 1).

[0178] Mainly, this second mode of implementation differs from the first mode of implementation in that the pixels 40 are formed group by group. In other words, they are not all formed during step E2.

[0179] According to this second mode of implementation, the manufacturing process begins with a step identical to step E1, illustrated in figure 2, of the first embodiment.

[0180] The manufacturing method continues with a step E2', illustrated in Figures 12 and 13. This step E2' differs from step E2 illustrated in Figures 3 to 5 in that a first group of pixels 40I, B (see Figure 13) is formed on only a portion (typically a third) of the lower electrodes 41 (it is recalled that, according to the first embodiment, there are as many pixels 40 as there are lower electrodes 41). Typically, on three adjacent lower electrodes, a single lower electrode is used to form the pixels 401, B of the first group (the other lower electrodes are denoted 40NR in Figure 13).

[0181] The 40i,e pixels of this first group are then configured to produce a first color radiation, for example a blue color radiation.

[0182] Step E2' begins with a step identical to step E21 illustrated in Figure 3, therefore consisting of: Deposit the first stack 421 of organic layers on the active surface SACT of the substrate 11 (in this case on the insulating layer 12), Deposit the CGL layer on the first stack 421 of organic layers, Deposit the second stack 422 of organic layers on the CGL layer, Depositing the second conductive layer 17 on the second stack 422 of organic layers, and Deposit the first conductive layer 16 on the second conductive layer 17.

[0183] The first and second stack 421, 422 as well as the second conductive layer 17 are here configured to produce the first color radiation (in the example chosen, blue color, noted “B” in the figures).

[0184] With reference to figure 12, step E2' continues with a sub-step E22' of partial etching of the first conductive layer 16. As indicated previously, sub-step E22' can alternatively be an etching configured to reach the second conductive layer 17.

[0185] This sub-step E22' comprises, like the sub-step E22 illustrated in figures 4 to 6, an operation of forming an etching mask, then a partial etching operation of the first conductive layer 16 through the etching mask, then an operation of removing the etching mask.

[0186] The operation of forming the etching mask according to this second embodiment is illustrated in Figure 12.

[0187] As shown in Figure 12, the portions 20A' of the etching mask 20 no longer correspond to each lower electrode 41 (as illustrated in Figure 4) but to one lower electrode out of three, noted 411,B in Figure 12.

[0188] Step E2' continues by implementing sub-steps E22' and E23' which are respectively identical to the sub-steps E22 and E23 previously described.

[0189] Figure 13 shows the structure obtained at the end of this alternative step E2'. It comprises pixels 40I,B (here blue in color) formed on the substrate 11 and spaced two by two by two adjacent lower electrodes (not covered with materials, noted 41NR in figure 13).

[0190] The manufacturing process according to the second manufacturing method can continue, optionally, with a step E3', illustrated in figure 14. This step E3' is analogous to step E3 illustrated in figure 8. It thus consists of depositing a passivation layer 50 on the edges of the pixels 40I, B and between the pixels 40I, B.

[0191] Then, the second group of pixels is formed during a step E6, illustrated in Figures 15 to 18.

[0192] The pixels of the second group are configured to produce a second radiation of a different color from the color of the first radiation. For example, the second radiation is green. The pixels of the second group are denoted 402, v in Figures 17 and 18.

[0193] When step E3' of depositing the passivation layer 50 is implemented, step E6 begins with a sub-step E61, illustrated in FIG. 15. Otherwise, step E6 begins with sub-step E62.

[0194] Sub-step E61 consists of opening the passivation layer 50 at the right of the lower electrodes 412,v of the pixels of the second group, to form accesses 80 to these lower electrodes 412,v.

[0195] Substep E62 is analogous to substep E21 illustrated in Figure 3. Thus, with reference to figure 16, the following are carried out: a deposition, on the active surface SACT of the substrate, of a third stack 4212 of organic layers, a deposition, on the third stack of organic layers of a second layer CGL2 deposited during step E2', a deposition, on the second layer CGL2, of a fourth stack 4222 of organic layers, a deposition, on the fourth stack 4222 of organic layers, of a fifth conductive layer 172, and a deposition of a fourth conductive layer 162 on the fifth conductive layer 172.

[0196] The second layer CGL2 is similar to the layer CGL, in the sense that it fulfills the same role, namely interconnecting two stacks of organic layers, here the third and fourth stack 4212, 4222 of organic layers. In addition, the second layer CGL2 is preferentially formed from the same material as the layer CGL deposited during sub-step E21.

[0197] The third and fourth stacks of organic layers 4212, 4222 are configured to produce the second color radiation (in the chosen example, this second radiation is green in color, denoted “V” in the figures). These stacks 4212, 4222 of organic layers are intended to form the active elements 422, v of the pixels of the second group.

[0198] The fourth conductive layer 162 is similar to the first conductive layer 16, in the sense that it is intended to form the first 4312 portions of the upper electrodes 432, v, of the pixels 402, v of the second group (see figure 17).

[0199] The fifth conductive layer 172 is similar to the second conductive layer 17 in the sense that it is intended to form the second conductive portions 4322 of the upper electrodes 43 of the pixels 402,v of the second group.

[0200] Sub-step E63 aims, like sub-step E22 of the first embodiment or like sub-step E22' of this second embodiment, to partially etch the upper conductive layer (which is here the fourth layer conductive 162) to form non-through cavities therein. In this sub-step E63, the cavities extend between the pixels 40I, B of the first group and on either side of the lower electrodes of the pixels of the second group (denoted 412, v in figure 16).

[0201] To do this, the procedure is the same as for sub-step E22. Thus, an operation E631 of forming an etching mask on the fourth conductive layer 162 is implemented. This operation E631 is illustrated in FIG. 16. The portions 20A” of the etching mask are here arranged in line with the lower electrodes 412, v of the pixels of the second group.

[0202] Then, an operation (not shown in the figures) of partial etching of the fourth conductive layer 162 is carried out through the etching mask 20 to form the cavities having a depth strictly less than the thickness of the fourth conductive layer 162. The etching configurations (chemistry, duration, etc.) are then similar to those used during the operation E222. Alternatively, the etching operation is not partial but configured to reach the fifth conductive layer 172. The cavities 30 then have the fifth conductive layer 172 as their bottom.

[0203] Finally, the etching mask is removed using a process similar to the process implemented during operation E223.

[0204] In a sub-step E64 illustrated in FIG. 17, the cavities formed in the previous sub-step E63 are extended. The cavities are thus extended through the fourth conductive layer 162, then through the fifth conductive layer 172, the fourth stack of organic layers 4222, the second layer CGL2 and the third stack of organic layers 4212. The resulting cavities, denoted 302 in FIG. 17, open onto the insulating layer 12. This results in the pixels 402,v of the second group and the pixels 401,B of the first group separated from each other.

[0205] Specifically, during this sub-step E64, the following anisotropic etching operations are carried out: anisotropic etching of the fourth conductive layer 162 until it reaches the fifth conductive layer 172, anisotropic etching of the fifth conductive layer 172 until it reaches the fourth stack of organic layers 4222, anisotropic etching of the fourth stack of organic layers 4222 until it reaches the second layer CGL2, anisotropic etching of the second layer CGL2 until it reaches the third stack of organic layers 4212 and anisotropic etching of the third stack of organic layers 4212 until it reaches the insulating layer 12.

[0206] The configurations of the anisotropic etchings of the layers underlying the fourth conductive layer 162 are similar to the etching configurations of the layers underlying the first conductive layer 16, in the sense that they are preferably ballistic type etchings, and / or preferably selective etchings with respect to the fourth conductive layer 162.

[0207] In an optional sub-step E65, similar to step E3, a third passivation layer 50' can be formed conformally on the edges of the pixels and between the pixels. At the end of sub-step E65, the structure illustrated in FIG. 18 is obtained. This structure comprises, in addition to the pixels 40I,B of the first group, the pixels 402,v of the second group separated from each other by the cavities 302. These pixels 40I,B, 40i,v are covered with the passivation layer 50'.

[0208] Then, the third group of pixels 40a, R is formed during a step E7, illustrated in figure 19.

[0209] The pixels in the third group are configured to produce a third radiation of a different color from the color of the first and second radiations. For example, the third radiation is red. The pixels in the third group are denoted 403, R in Figure 19.

[0210] In this step E7, the procedure is the same as in step E6, as described below.

[0211] When step E6 comprises the sub-step of depositing the passivation layer 50', step E7 begins, like step E6, with a sub-step (not shown in the figures) of opening the passivation layer 50' so as to create access to each lower electrode 413 of the pixels of the third group.

[0212] Step E7 continues with the operations described below. It is noted that when step E6 does not include the sub-step of depositing the passivation layer 50', these operations are carried out at the start of step E7.

[0213] Step E7 then continues with the following operations: Deposition, on the active SACT surface of the substrate, of a fifth stack 4213 of organic layers, Deposition of a third CGL3 layer on the fifth 4213 of organic layers, Deposition of a sixth stack 4223 of organic layers on the third CGL3 layer, Deposition of a seventh conductive layer 173 on the sixth stack 4223, Deposition of a sixth conductive layer 163 on the third stack of organic layers.

[0214] The third layer CGL3 is similar to the layer CGL and the second layer CGL2, in the sense that it fulfills the same role, namely interconnecting stacks of organic layers (here the fifth and sixth stacks 4213, 4223 of organic layers). In addition, the third layer CGL3 is preferentially formed from the same material as the layer CGL deposited during sub-step E21.

[0215] The third and fourth stacks of organic layers 4213, 4223 are configured to produce the third color radiation (in the chosen example, this second radiation is red in color, denoted “R” in the figures). These stacks 4213, 4223 of organic layers are intended to form the active elements 423, R of the pixels of the third group.

[0216] The sixth conductive layer 163 is similar to the first conductive layer 16, in the sense that it is intended to form the first 4313 portions of the upper electrodes 43s, of the pixels 403, of the third group (see figure 19).

[0217] The seventh conductive layer 173 is similar to the second conductive layer 17 in the sense that it is intended to form the second conductive portions 432s of the upper electrodes 43 of the pixels 403, of the third group.

[0218] Once the deposits of the materials intended to form the pixels of the third group have been deposited, step E7 continues, like step E6, with a sub-step of partial etching of the sixth conductive layer 163 to obtain non-through cavities between the pixels 40I, B, 412, V already formed and at the right of the spaces between the lower electrodes 413, R of the pixels of the third group. Alternatively, the etching operation is not partial but configured to reach the seventh conductive layer 173. The cavities 30 then have the seventh conductive layer 173 as their bottom.

[0219] To do this, proceed in the same way as for sub-step E22.

[0220] The etching configurations (chemistry, duration, etc.) are then similar to those used during operation E222.

[0221] Once the non-through cavities have been obtained, a sub-step illustrated in FIG. 19 is implemented, as in step E6, which consists of extending the non-through cavities through the sixth conductive layer 163, then through the seventh conductive layer 173, the sixth stack of organic layers 4223, the third layer CGL3 and the fifth stack of organic layers 4213. The resulting cavities, denoted 30s in FIG. 19, open onto the insulating layer 12. This results in the pixels 403, R of the second group, the pixels of the second group 402,v and the pixels 40I,B of the first group separated from each other.

[0222] As in sub-step E64, anisotropic etchings are performed through the sixth conductive layer 163, then through the layers underlying the sixth conductive layer 163. The anisotropic etching configurations are similar to the etching configurations described in relation to sub-step E64, or in relation to sub-step E23.

[0223] Finally, a fourth passivation layer 50” (see figure 19) is formed in a conformal manner on the edges of the pixels and between the formed pixels. At the end of step E7, the structure illustrated in figure 19 is obtained. This structure comprises, in addition to the pixels 40I,B of the first group and the pixels 402,v of the second group, the pixels 403, of the third group separated from each other by the cavities 30s.

[0224] Preferably, steps E4 and E5 are implemented on the display device illustrated in Figure 19.

[0225] According to a third embodiment, the manufacturing method makes it possible to form the display device 1 according to the third embodiment (illustrated in figure 20).

[0226] The manufacturing method according to the third embodiment differs from the first embodiment (described in relation to FIGS. 2 to 7) in that during the sub-step E21 consisting of depositing the materials intended to form the pixels, the operations E212, E213 and E214 are not carried out. In other words, the manufacturing method does not comprise, during a step E2' of forming the pixels 40, the following operations: Deposition of the CGL layer on the first stack 421 of organic layers, Deposition of the second stack 422 of organic layers on the CGL layer, Deposition of the second conductive layer 17 on the second stack 422 of organic layers.

[0227] Since the CGL layer and the second stack 422 of organic layers are not deposited, the manufacturing method according to this third embodiment does not further comprise the following operations: anisotropic etching E232 of the second conductive layer 17, anisotropic etching E233 of the second stack 422 of organic layers, anisotropic etching E234 of the CGL layer.

[0228] It should be noted that the charge transport layers CGL, the second stack 422 of organic layers, as well as the second conductive layer 17 are therefore not essential.

[0229] Furthermore, the manufacturing method according to the third embodiment differs from the first embodiment (described in relation to FIGS. 2 to 7) in that the step E222 of etching at least a portion of the first conductive layer 16 is configured so that the cavities 30 have a depth eso strictly less than (and not less than or equal to) the thickness ei6 of the first conductive layer 16. Indeed, in the absence of the second conductive layer 17, the residual thickness of the first conductive layer 16 protects the first stack of organic layers when the etching mask is removed.

[0230] According to an alternative embodiment, the second conductive layer 17 can be deposited on the first stack 421 of organic layers, before the deposition of the first conductive layer 16. In this case, an anisotropic etching operation of the second conductive layer 17 deposited on the first stack 421 of organic layers is implemented between the anisotropic etching of the first conductive layer 16 and the anisotropic etching of the first stack of organic layers 421. In addition, the etching of at least a portion of the first conductive layer 16 is configured so that the cavities 30 have a depth less than or equal to the thickness of the first conductive layer 16.

[0231] According to a fourth embodiment, the manufacturing method makes it possible to form the 1-color display device according to the fourth embodiment (illustrated in figure 21).

[0232] This fourth embodiment differs from the third embodiment in that all the pixels are not formed in a single step E2', but in three stages, with organic layers configured to produce radiation of different color (here, in the example chosen, of respective blue, green and red color).

[0233] To do this, we proceed in much the same way as for the second implementation method, described in relation to figures 12 to 19.

[0234] Specifically, the fourth mode of implementation differs from the second mode of implementation only during the steps of deposition and anisotropic etching of the materials intended to form, or forming, the pixels.

[0235] Thus, compared to the second mode of implementation, the manufacturing method according to the fourth mode of implementation does not include, during a step E2” of forming the pixels of the first group, the following operations: Deposition of the CGL layer on the first stack 421 of organic layers, Deposition of the second stack 422 of organic layers on the CGL layer, Deposition of the second conductive layer 17 on the second stack 422 of organic layers, Anisotropic etching of the second conductive layer 17, Anisotropic etching of the second stack 422 of organic layers, Anisotropic etching of the CGL layer

[0236] Furthermore, the manufacturing method according to the fourth embodiment does not include, during a step E6' of forming the pixels of the second group, the following operations: Deposition of the second CGL2 layer on the third stack 4212 of organic layers, Deposition of the fourth stack 4222 of organic layers on the second CGL2 layer, Deposition of the fifth conductive layer 172 on the fourth stack 4222 organic layers, Anisotropic etching of the fifth conductive layer 172, Anisotropic etching of the fourth stack 4222 of organic layers, Anisotropic etching of the second CGL2 layer.

[0237] Finally, the manufacturing method according to the fourth embodiment does not include, during a step E7' of forming the pixels of the third group, the following operations: Deposition of the third CGL3 layer on the fifth stack 4213 of organic layers, Deposition of the sixth stack 4223 of organic layers on the third CGL3 layer, Deposition of the seventh conductive layer 173 on the sixth stack 4223 organic layers, Anisotropic etching of the seventh conductive layer 173, Anisotropic etching of the sixth stack 4223 of organic layers, Anisotropic etching of the third CGL3 layer.

Claims

CLAIMS

1. A method of manufacturing a device (1) comprising a plurality of pixels (40) arranged on a substrate (11), each pixel (40) comprising a lower electrode (41), an upper electrode (43), and an active element (42) arranged between the lower (41) and upper (43) electrodes, said method comprising the following steps: - Provision (E1) of a structure (10) comprising the substrate (11) and the lower electrodes (41) of the pixels (40), the lower electrodes (41) being spaced from each other and arranged on a first surface (SACT) of the substrate (11), called the active surface (SACT), - Formation (E2) of a first group of pixels (40) on the substrate (1 1 ), by performing the following sub-steps: o Deposition (E21 , E21 1 ), on the active surface (SACT) of the substrate, of a first stack (421 ) of organic layers configured to generate or absorb a first radiation, o Deposition (E21 , E215) of a first conductive layer (16) on the first stack (421 ) of organic layers, o Etching (E22) of at least a portion of the first conductive layer (16) to form cavities (30) having a depth strictly less than the thickness (e-ie) of the first conductive layer (16), the cavities (30) being located at right angles to spaces (40B) extending between lower electrodes (41 ) of the pixels (40) of the first group,o Anisotropic etching (E23) of the first conductive layer (16) and anisotropic etching (E23) of the first stack (421) of organic layers so as to extend the cavities (30) through the first conductive layer (16) and the first stack (421) of organic layers, residual portions (431) of the first conductive layer (16) remaining between the cavities (30), resulting in the pixels (40) of the first group separated from each other by the cavities (30).,

2. Manufacturing method according to claim 1, in which the anisotropic etching sub-step (E23) is carried out in an oxygen-free atmosphere.

3. Manufacturing method according to one of claims 1 to 2, in which the provided structure (10) comprises an electrically insulating layer (12) arranged on the active surface (SACT) of the substrate (11) and laterally coating the lower electrode (41) of each pixel (40), the electrically insulating layer (12) serving as a stop layer during the anisotropic etching (E23) of the first stack (421) of organic layers.

4. Manufacturing method according to one of claims 1 to 3, in which the step (E2) of forming the first group of pixels (40) on the substrate (11) further comprises: - between the deposition (E21 1) of the first stack of organic layers and the deposition (E215) of the first conductive layer, the deposition (E214) of a second conductive layer (17) formed of a metal, - between the anisotropic etching (E23) of the first conductive layer (16) and the anisotropic etching (E23) of the first stack (421) of organic layers, an anisotropic etching (E23) of the second conductive layer (17).

5. A manufacturing method according to claim 4, wherein the first stack (421) of organic layers is configured to generate the first radiation and wherein the step (E2) of forming the first group of pixels on the substrate further comprises: - Between the deposition (E21 1) of the first stack of conductive layers and the deposition (E214) of the second conductive layer, the following operations: - Deposition (E212) of a conductive interconnection layer (CGL) on the first stack (421) of organic layers, the conductive interconnection layer (CGL) being adapted to connect the first stack (421) of organic layers to a second stack (422) of organic layers, - Deposition (E213) of the second stack (422) of organic layers on the conductive interconnection layer (CGL), - Between the anisotropic etching (E23) of the second conductive layer (17) and the anisotropic etching (E23) of the first stack (421) of organic layers, an anisotropic etching (E23) of the conductive interconnection layer (CGL) and an anisotropic etching of the second stack (422) of organic layers, resulting in the pixels (40) separated from each other and having a multi-stack structure also called tandem structure.

6. A manufacturing method according to claim 5, wherein the conductive interconnection layer (CGL) is formed of a metallic or organic conductive material.

7. Manufacturing method according to one of claims 1 to 4, in which the first conductive layer (16) is formed of a metal and has an initial thickness (e-ie) determined so that the thickness (e43i) of the residual portions of the first conductive layer (16) is less than 20 nm, preferably between 10 nm and 20 nm.

8. Manufacturing method according to one of claims 1 to 7, comprising, after the step (E2) of forming the pixels on the substrate, a step (E3) of depositing a passivation layer (50) on the edges of the pixels (40) and on the surface of the substrate (11).

9. Manufacturing method according to claim 8, in which the deposition (E3) of the passivation layer (50) is carried out in a conformal manner.

10. Manufacturing method according to one of claims 8 to 9, comprising, after step (E3) of depositing the passivation layer, a step (E4) of forming a common electrode (60) comprising the following sub-steps: - Opening of the passivation layer (50) so as to create access to the upper electrode (41) of each pixel (40), - Formation of a third continuous conductive layer (60) on the pixels (40) and on the substrate between the pixels and on an electrical contact track (13) arranged on a second surface (SPERI) of the substrate peripheral to the active surface, from which results the common electrode (70) connecting the upper electrode (43) of each pixel (40) to the electrical contact track (13). [Claim 1 1 ] A manufacturing method according to claim 10, wherein the third conductive layer (60) is transparent.

12. A manufacturing method according to claim 10, wherein the third conductive layer (60) is reflective and the substrate (11) is transparent.

13. The manufacturing method of claim 12, wherein the third conductive layer (60) has a thickness greater than 50 nm.

14. Manufacturing method according to one of claims 8 to 13, comprising, after the step (E3) of depositing the passivation layer, a step of forming (E6) a second group of pixels on another part of the lower electrodes, comprising the following sub-steps: - Opening of the passivation layer so as to create access to each lower electrode of the pixels of the second group, - Deposition, on the active surface of the substrate, of a third stack of organic layers configured to generate or receive a second radiation distinct from the first radiation, - Deposition of a fourth conductive layer on the third stack of organic layers, - Etching at least a portion of the fourth conductive layer to form cavities having a depth less than or equal to the thickness of the fourth conductive layer, the cavities being located in line with spaces extending between lower electrodes of the pixels of the second group, - Anisotropic etching of the fourth conductive layer and anisotropic etching of the third stack of organic layers so as to extend the cavities through the fourth conductive layer and the third stack of organic layers, residual portions of the fourth conductive layer remaining between the cavities, hence it results, in addition to the pixels of the first group, the pixels of the second group separated from each other by the cavities.

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