Resistive random access memory for performing forming-free resistive switching, and method of manufacturing the memory

Abstract

The disclosure relates to a Resistive Random Access Memory (1), ReRAM, for performing forming-free resistive switching, and methods of manufacturing the memory. The ReRAM comprises a bottom electrode (20) disposed on a substrate layer (10), an oxide layer (30) disposed on the bottom electrode, a reactive-metal layer (40) disposed on the oxide layer, and a top electrode (50) disposed on the reactive-metal layer; wherein: the bottom electrode comprises a first inert metal selected from Pd, Rh, Ru, Re, and / or combinations thereof; the oxide layer has a thickness between 3 nm and 9 nm; the reactive-metal layer comprises Ti; and the top electrode comprises a second inert metal selected from Pd, Rh, Ru, Re, and / or combinations thereof. The ReRAM exhibits multi-level resistance states and can be implemented in a computer-architecture, such as a chip.

Description

[0001] Resistive Random Access Memory for performing forming-free resistive switching, and method of manufacturing the memory

[0002] Field of the invention

[0003] The invention relates to a Resistive Random Access Memory, ReRAM, for performing forming-free resistive switching, and method of manufacturing the memory.

[0004] Background art

[0005] A ReRAM is a well-known non-volatile type of memory for storing data as resistance by exhibiting resistive states that can be controlled via applying suitable voltages to the ReRAM. For example, applying a set voltage may switch on the ReRAM from a high- resistance-state (HRS) to a low-resistance-state (LRS), while applying a re-set voltage may switch off the ReRAM from the LRS to the HRS. Resistive switching refers to performing switching between different resistive states of the ReRAM.

[0006] Various known ReRAMs typically require an electro-forming step for performing the resistive switching, in which a relatively-high voltage is applied to the ReRAM to generate an electrically conductive path in an oxide layer of the ReRAM so as to realize a LRS. But such electro-forming steps are undesirable as they increase the power consumption of the ReRAM and moreover degrade its functionality by reducing its endurance due to the relatively-high voltage required for the electro-forming steps.

[0007] Therefore, there is a vast interest in developing forming-free ReRAMs that can be operated without electro-forming steps. Forming-free ReRAMs offer technical advantages including simplified manufacturing, improved reliability, reduced energy consumption, and / or enhanced scalability.

[0008] However, only few ReRAMs intended for performing forming-free resistive switching that require relatively-low operating voltages have been reported at all. There is thus still a need to provide ReRAMs for performing forming-free resistive switching.

[0009] Summary of the invention

[0010] A general object of the invention is to provide ReRAMs for performing forming-free resistive switching.

[0011] Therefore, according to a first aspect of the invention, a ReRAM for performing forming-free resistive switching as defined in appended claim 1 is provided. The ReRAM comprises a bottom electrode disposed on a substrate layer, an oxide layer disposed on the bottom electrode, a reactive-metal layer disposed on the oxide layer, and a top electrode disposed on the reactive-metal layer; wherein: the bottom electrode comprises a first inert metal selected from Pd, Rh, Ru, Os, Re, Ir, Au, and / or combinations thereof; the oxide layer has a thickness between 3nm and 9nm; the reactive-metal layer comprises a first reactive metal selected from Cd, Ag, Ta, Nb, Ti, Ta, W, Zr, Al, and / or combinations thereof; and the top electrode comprises a second inert metal selected from Pt, Pd, Rh, Ru, Os, Re, Ir, Au, and / or combinations thereof.

[0012] The inventors have identified that the combination of an oxide layer having a thickness between 3nm and 15nm with a reactive-metal layer and bottom and top electrodes with elements selected as specified according to the above-recited first aspect of the invention, has the surprising synergetic technical effect of providing a ReRAM capable of efficiently performing forming-free resistive switching. The surprising synergetic technical advantages associated with the ReRAM include one or more of the following:

[0013] Forming-free electrical behaviour: operating voltages of the ReRAM are surprisingly low and the ReRAM does not require an electro-forming step, thereby increasing its endurance and reducing power consumption;

[0014] Simplified manufacturing: manufacturing the ReRAM does not require relatively invasive treatments as for known ReRAMs, such as thermal annealing treatments, oxygen plasma treatments, proton injection, hydrogen plasma treatment, exotic element doping such as Ge or Sm or Dy doping, X-Ray irradiation. The ReRAM exhibits sufficient amount of oxygen defects by the specific combination of materials and oxide layer thickness.

[0015] Compatibility: the ReRAM design can easily be integrated in existing CMOS technologies due to providing a compact and easy-to-manufacture stack structure avoiding invasive treatments, such as recited above, and thereby reducing unwanted negative side-effects on components surrounding the ReRAM when implemented in a computing-architecture, for example negatively impacting the performance of transistors on a chip.

[0016] Thermal stability: the ReRAM is thermally stable and exhibits extended durability. Multi-level resistance: the ReRAM exhibits multi-level resistance states that can increase memory-efficiency and realize a more power-efficient memory.

[0017] In particular, that the ReRAM according to the invention can exhibit multiple resistance states means going beyond standard binary switching characteristics. The emergence of multilevel resistance states is a surprising synergetic technical effect and may be put to use for example to increase the energy-efficiency and memory-efficiency provided by the ReRAM and to perform neuromorphic computing. The ReRAM according to the invention can be implemented in a computingarchitecture that accordingly can be controlled in an energy-efficient manner due to the ReRAM providing forming-free resistive switching capabilities.

[0018] Furthermore, a method of manufacturing the ReRAM according to the invention is provided.

[0019] Particularly advantageous and preferred aspects of the invention as well as further advantages are discussed further below in the detailed description.

[0020] Brief description of the drawings

[0021] The present invention is discussed in more detail below, with reference to the attached drawings, in which:

[0022] Fig- 1 illustrates the ReRAM according to the invention.

[0023] Fig- 2 illustrates a preferred version of the ReRAM in which the oxide layer thereof comprises HfCh.

[0024] Figs. 3a-3d illustrate preferred versions of the ReRAM in which the oxide layer comprises HfCh, the reactive-metal layer comprises Ti, and the bottom and top electrodes comprise inert metals selected from Pd, Rh.

[0025] Figs. 4a and 4b illustrate methods of manufacturing the ReRAM.

[0026] Fig. 5 shows a table illustratively comparing properties of an example of the ReRAM according to the present invention with known ReRAMs.

[0027] Figs. 6a and 6b show I-V curves of examples of ReRAMs showcasing the relevance of the bottom electrode material.

[0028] Fig. 6c shows an operation table with various illustrating voltage operations that can be performed on the ReRAM of the present invention.

[0029] Figs. 6d-6e show I-V curves of further examples of ReRAMs showcasing the relevance of the thickness of the oxide layer.

[0030] Figs. 6f shows I-V curves of a further example of the forming-free ReRAM according to the invention, in which the bottom and top electrode metals are selected from Ru.

[0031] Fig. 6g showcases that Pd-based ReRAMs exhibit an activation energy that is significantly lower than Pt-based ReRAMs, which means that a lower voltage is required for oxygen vacancies to start migrating to the oxide layer for the first cycle.

[0032] Figs. 7a-7d illustrate multi-resistance states exhibited by the ReRAM of the present invention.

[0033] Figs. 8 and 9 show an endurance test and retention test for an example of the ReRAM of the present invention. Fig. 10 illustrates schematically compares an example of the ReRAM of the present invention with another ReRAM.

[0034] Detailed description

[0035] Embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. However, the embodiments of the present disclosure are not limited to the specific embodiments and should be construed as including all modifications, changes, equivalent devices and methods, and / or alternative embodiments of the present disclosure.

[0036] The terms “have,” “may have,” “include,” and “may include” as used herein indicate the presence of corresponding features (for example, elements such as numerical values, functions, operations, or parts), and do not preclude the presence of additional features.

[0037] The terms “A or B,” “at least one of A or / and B,” or “one or more of A or / and B” as used herein include all possible combinations of items enumerated with them. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” means (1) including at least one A, (2) including at least one B, or (3) including both at least one A and at least one B.

[0038] The terms such as “first” and “second” as used herein may modify various elements regardless of an order and / or importance of the corresponding elements, and do not limit the corresponding elements. These terms may be used for the purpose of distinguishing one element from another element. For example, a first element may be referred to as a second element without departing from the scope the present invention, and similarly, a second element may be referred to as a first element.

[0039] It will be understood that, when an element (for example, a first element) is “(operatively or communicatively) coupled with / to” or “connected to” another element (for example, a second element), the element may be directly coupled with / to another element, and there may be an intervening element (for example, a third element) between the element and another element. To the contrary, it will be understood that, when an element (for example, a first element) is “directly coupled with / to” or “directly connected to” another element (for example, a second element), there is no intervening element (for example, a third element) between the element and another element.

[0040] The expression “configured to (or set to)” as used herein may be used interchangeably with “suitable for” “having the capacity to” “designed to” “adapted to” “made to,” or “capable of’ according to a context. The term “configured to (set to)” does not necessarily mean “specifically designed to” in a hardware level. Instead, the expression “apparatus configured to...” may mean that the apparatus is “capable of...” along with other devices or parts in a certain context.

[0041] The terms used in describing the various embodiments of the present disclosure are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. All of the terms used herein including technical or scientific terms have the same meanings as those generally understood by an ordinary skilled person in the related art unless they are defined otherwise. The terms defined in a generally used dictionary should be interpreted as having the same or similar meanings as the contextual meanings of the relevant technology and should not be interpreted as having ideal or exaggerated meanings unless they are clearly defined herein. According to circumstances, even the terms defined in this disclosure should not be interpreted as excluding the embodiments of the present disclosure.

[0042] The person skilled in the art will understand that the features described above and / or below may be combined in any way deemed useful. The drawings of the present disclosure show examples / embodiments of the invention, which will be described in detail hereinafter. It is to be understood that one or more of elements / components shown and / or described in one or more of these examples / embodiments and not in others may be used in those others too unless mechanical or other limitations prevent such an implementation. Moreover, describing features of different examples / embodiments in a single passage does not automatically mean that those features are inextricably linked. They may be applied separately from one another.

[0043] Fig- 1 illustrates the ReRAM 1 according to the invention. The ReRAM 1 is for performing forming-free resistive switching and comprises: a bottom electrode 20 disposed on a substrate 10; an oxide layer 30 disposed on the bottom electrode 20; a reactive-metal layer 40 disposed on the oxide layer 30; and a top electrode 50 disposed on the reactive-metal layer 40; wherein: the bottom electrode 20 comprises a first inert metal selected from Pd, Rh, Ru, Os, Re, Ir, Au, and / or combinations thereof, the oxide layer 30 has a thickness between 3nm and 9nm, the reactive-metal layer 40 comprises a first reactive metal selected from Cd, Ag, Ta, Nb, Ti, Ta, W, Zr, Al, and / or combinations thereof, and the top electrode 50 comprises a second inert metal selected from Pt, Pd, Rh, Ru, Os, Re, Ir, Au, and / or combinations thereof.

[0044] The inventors have identified that the specific combination of providing the bottom electrode 20 with inert metals selected from Pd, Rh, Ru, Os, Re, Ir, Au, and / or combinations thereof, the top electrode 50 with inert metals selected from Pt, Pd, Rh, Ru, Os, Re, Ir, Au, and / or combinations thereof, while providing a reactive-metal layer 40 with a reactive metal selected from Cd, Ag, Ta, Nb, Ti, Ta, W, Zr, Al, and / or combinations thereof, and moreover at the same time limiting the oxide layer 30 to having a thickness between 3nm and 9nm, reveals a surprising synergetic technical effect in that the ReRAM shows one or more of the technical advantages as recited above under Summary of the invention.

[0045] The bottom electrode, oxide layer and reactive-metal layer are together also referred to as a switching layer, which has the functionality of enabling the ReRAM to exhibit multiple resistive states that can be controlled by applying voltages between the top and bottom electrodes or by compliance current through the top and bottom electrodes. In particular, the inclusion of the reactive-metal layer 40 deposited on the oxide layer 30 is crucial for the switching behaviour. The reactive-metal layer 40 is preferably tightly bonded with the oxide layer 30 to form a relatively-large amount of Mreactive-0 bonds, thereby creating large amounts of oxygen-vacancies in the oxide layer 30.

[0046] Preferably, the oxide layer 30 comprises a layer of HfCh directly contacting the bottom electrode 20. More preferably, the layer of HfCh makes up 80% of the oxide layer 30, even more preferably 90% of the oxide layer 30, even more preferably 95% of the oxide layer 30. Most preferably, the oxide layer 30 is made of HfCh.

[0047] Fig- 2 illustrates the preferred version of the ReRAM 1 in which the oxide layer 30 thereof comprises HfCh. The inventors found that the ReRAM 1 shows the surprising synergetic technical effect most pronounced when basing the oxide layer 30 on HfCh.

[0048] In particular, the inventors specifically identified that in the context of the ReRAM 1, providing the oxide layer 30 based on HfCh is preferred over other metal oxides such as TiCh, Ta2Os, Nb20s, ZrCh, WO3, MoOs, due to advantages of HfCh regarding the dielectric constant, excellent compatibility with silicon, relatively-high thermal stability, a relatively -high band gap as well as breakdown voltage, when compared to the other metal oxides.

[0049] Furthermore, as compared to other existing HfCh-based ReRAMs, the inventors found that the ReRAM 1 according to the present invention, in which the oxide layer 30 comprises the layer of HfCh directly contacting the bottom electrode 20, is the only electro-forming free ReRAM that is HfCh-based while not requiring thermal annealing or other special processes such as X-ray irradiation, plasma treatment, etc. Instead, the ReRAM 1 can be manufactured by conventional integrated circuit, IC, manufacturing processes while still being forming-free with low operating voltage and exhibiting multi-level resistance states. A comparison of the ReRAM 1 according to the present invention with known ReRAMs is shown in Fig. 4 in the context of a more specific example for illustrative purposes.

[0050] Preferably, the first reactive metal is selected from Cd, Ag, Ti, W, Zr, Al, and / or combinations thereof. Even more preferably, the first reactive metal is Ti.

[0051] The inventors found that when further specifically selecting the first reactive metal from the sub-group of Cd, Ag, Ti, W, Zr, Al, and / or combinations thereof, then the surprising synergetic effect is even more pronounced.

[0052] In particular, providing the ReRAM 1 with the combination of including a HfCE layer directly contacting the bottom electrode 20 and selecting Ti as the first reactive metal is a preferred way of achieving the surprising synergetic effect.

[0053] The most preferred option of Ti combines particularly well with HfCE as the oxide layer 30 and Pd for both bottom and top electrodes. Such more preferred combinations of materials are discussed further below.

[0054] Next, more preferred options of thicknesses are discussed.

[0055] Preferably, the reactive-metal layer 40 has a thickness between 5nm and lOOnm, more preferably between 5nm and 50nm, even more preferably between 5nm and 15nm, even more preferably between 5nm and 12nm, most preferably between 5nm and lOnm.

[0056] In particular, the inventors found that combining the oxide layer 30 thickness of 3-9nm with a relatively-small reactive-metal layer 40 thickness in between 5nm and 20 nm is advantageous as efficiently enabling the forming-free electric behaviour of the ReRAM 1. Furthermore, the ability of achieving the forming-free electric behaviour with the relatively- small thicknesses provides the additional advantages of compactness of the ReRAM, thereby supporting small-scale computer chips, as well as economic usage of involved materials for manufacturing.

[0057] Furthermore, combining the relatively-small thicknesses with the material choices of HfCh and Ti was found to be a particularly advantageous way of enabling the forming-free behaviour and providing low operating voltages.

[0058] In one variant of the ReRAM 1, the thickness of the oxide layer 30 is preferably between 3nm and 8nm, even more preferably between 3nm and 7nm, even more preferably between 3nm and 6nm, yet even more preferably between 4nm and 6nm. An example of the ReRAM 1 with thickness of 5nm of the oxide layer 30 is discussed further below as Example lb. Examples of ReRAMs with thicknesses of the oxide layer 30 higher than 9nm are discussed further below under Examples 2 and 3, showcasing that the forming-free behaviour arises as a surprising synergetic effect for the ReRAM 1 of the present invention only when choosing the oxide layer thickness between 3nm and 9nm .

[0059] Preferably, the thickness of the oxide layer 30 is between 3nm and 9nm, and the reactive-metal layer 40 has a thickness between 5nm and 15nm, preferably between 5nm and lOnm.

[0060] As mentioned above, specifically the combination of relatively-small thicknesses of both the oxide layer 30 and the reactive-metal layer 40 in the context of the present ReRAM 1 is a particularly advantageous way of enabling the forming-free behaviour and providing low operating voltages.

[0061] Preferably, the thickness ratio of the oxide layer 30 and the reactive-metal layer 40 is smaller than or equal to 2, more preferably smaller than or equal to 1.

[0062] Preferably, the thickness of the oxide layer 30 is between 4nm and 6nm, and the reactive-metal layer 40 has a thickness between 5nm and lOnm.

[0063] Such particularly advantageous combinations are showcased in the context of Examples 1-3, which further illustrate specific material and thickness choices.

[0064] Preferably, the bottom electrode 20 comprises the first inert material selected from Pd, Rh, Ru, Re, and / or combinations thereof, the top electrode 50 comprises the second inert metal selected from Pd, Rh, Ru, Re, and / or combinations thereof, and the reactive-metal layer 40 comprises Ti. In particular, the combining of these choices with the previously-discussed thicknesses and with the choice of HfCE as the oxide layer material is a particularly advantageous way of enabling the forming-free behaviour and providing low operating voltages.

[0065] Figs. 3a-3d illustrate even more preferred examples of the ReRAM 1. In these even more preferred example, the bottom electrode 20 comprises the first inert material selected from Pd, Rh, and / or combinations thereof; the top electrode 50 comprises the second inert metal selected from Pd, Rh, and / or combinations thereof; and the reactive-metal layer 40 comprises Ti. I.e., Figs. 3a-3d illustrate preferred versions of the ReRAM 1 in which the oxide layer 30 comprises HfCE, the reactive-metal layer 40 comprises Ti, and the bottom and top electrodes 20, 50 comprise inert metals selected from Pd, Rh. The invention is however not limited to the even more preferred examples.

[0066] As shown in Fig. 3a, preferably, the bottom electrode 20 comprises Pd, the top electrode 50 comprises Pd, and the reactive-metal layer 40 comprises Ti. As shown in Fig. 3b, preferably, the bottom electrode 20 comprises Pd, the top electrode 50 comprises Rh, and the reactive-metal layer 40 comprises Ti.

[0067] As shown in Fig. 3c, preferably, the bottom electrode 20 comprises Rh, the top electrode 50 comprises Pd, and the reactive-metal layer 40 comprises Ti.

[0068] As shown in Fig. 3d, preferably, the bottom electrode 20 comprises Rh, the top electrode 50 comprises Rh, and the reactive-metal layer 40 comprises Ti.

[0069] Preferably, the bottom electrode 20 has a thickness between 0.3nm and 500nm, and / or the top electrode 50 has a thickness between 0.3nm and 500nm. More preferably, the bottom electrode 20 has a thickness between 5nm and 50nm, and the top electrode 50 has a thickness between 5nm and 50nm as well. Even more preferably, the bottom and top electrodes 20, 50 both have a thickness between lOnm and 30nm. Yet even more preferably, the bottom and top electrodes 20, 50 both have a thickness between 20nm and 30nm. Such smaller thicknesses combined with the above-disclosed thicknesses for the oxide and reactive-metal layers were found to particularly well achieve the synergetic technical effect and are therefore preferred. Examples are further discussed below.

[0070] The bottom electrode 20 and top electrode 50 may be multi-layer electrodes. For example, the bottom electrode 20 may further comprise a layer of Pt on which the first inert material is deposed. For example, the top electrode 50 may further comprise a layer of Pt deposed on top of the second inert material.

[0071] The layer of the bottom electrode 20 directly contacting the oxide layer 30 is preferably a metal layer whose work function is lower than the work function of Pt, so that the metal layer can bond with sufficient oxygen from the oxide layer spontaneously. Furthermore, this lower- work-function metal layer preferably has a thickness of at least 0.3nm so that it can guarantee sufficient chemical bond of Metal-Oxygen on the interface between the lower- work-function metal layer and the oxide layer.

[0072] Preferably, the substrate 10 comprises a SiCE layer (not illustrated), such as a thermal oxidized SiCE layer, and preferably the SiCE layer has a thickness between lOnm and 5000nm. A SiCE layer in the context of the present ReRAM 1 combines particularly well suited when choosing the oxide layer 30 to be based on HfCE.

[0073] The substrate 10 is not limited thereto. The substrate 10 may for example further comprise an adhesive layer (not illustrated), preferably positioned between the SiCE layer and the bottom electrode. Such aspects are however well-known and therefore not discussed here.

[0074] The ReRAM 1 may be incorporated in a computer-architecture such as a chip. The computer-architecture can comprise one or more instances of the ReRAM 1 including one or more or all of the aspects as disclosed herein. Since the ReRAM 1 according to the present invention is easily manufactured by standard IC manufacturing techniques and not relying on thermal annealing and other special processes as discussed above, and moreover exhibits forming-free behaviour and low operating voltages, the ReRAM 1 is particularly suitable for being incorporated into a computing-architecture involving computing based on ReRAMs.

[0075] Fig. 4a illustrates a method 4 of manufacturing the ReRAM 1 according to the present invention. The method 4 of manufacturing comprises: providing (step 402a) the substrate 10; disposing (step 404a) the bottom electrode 20 on the substrate 10; disposing (step 406a) the oxide layer 30 on the bottom electrode 20; disposing (step 408a) the reactive-metal layer 40 on the oxide layer 30; and disposing (step 410a) the top electrode 50 on the reactive-metal layer 40.

[0076] The method of manufacturing the ReRAM 1 can thus be performed relying on known IC manufacturing techniques but avoiding relatively invasive treatments as for known ReRAMs, such as thermal annealing treatments, oxygen plasma treatments, proton injection, hydrogen plasma treatment, exotic element doping such as Ge or Sm or Dy doping, X-Ray irradiation.

[0077] Fig. 4b illustrates the method 4 of manufacturing with more detailed manufacturing steps that may be included:

[0078] Step 402b: Surface cleaning

[0079] Step 404b: SiCh layer formation

[0080] Step 406b: Patterning & bottom electrode formation

[0081] Step 408b: Liftoff & Form oxide layer

[0082] Step 410b: Patterning & form reactive-metal layer and top electrodes

[0083] Step 412b: Liftoff & patterning

[0084] Step 414b: Contact features formation

[0085] For example, steps 402b, 404b may be part of step 402a; step 406b may be part of steps 404a and 406a; step 410b may be part of steps 408a and 410a.

[0086] In more detail, the steps may contain the following manufacturing aspects each of which taken alone is a well-known technique in the field of IC manufacturing.

[0087] Step 402b: Surface cleaning.

[0088] The surface may be cleaned by various organics and acid. Organics for cleaning include for example Acetone, ethanol, Isopropyl alcohol (IP A), and / or combinations thereof. Acids for clearing include fuming nitric acid or diluted acid. Furthermore, RCA clean may be performed, i.e. standard set of wafer cleaning steps. Such surface cleaning is well-known and is therefore not detailed here.

[0089] Step 404b: SiCh layer formation.

[0090] A silicon wafer can be oxidized by a chemical vapor deposition (CVD) system, wherein the oxygen source may include at least one of air or H2O to form the surface SiCh layer or SiCh may be formed by deposition by a CVD system (such as (ICP / )PECVD and LPCVD) or Sputter system.

[0091] Step 406b: Patterning & bottom electrode formation.

[0092] Resists such as electron-beam-lithography resists and photo-lithography resists can be applied in patterning, including negative resists as well as positive resists, each with single layer or multi-layer.

[0093] After spin-coating the resists on the wafers by a spin-coater with rounds-per-minute (rpm) ranging from 500 to 8000, a physical vapor deposition (PVD) system may be applied to form an adhesion layer, such as Ti as an example, and the bottom electrode. The applying of the PVD system is preferably performed in the same vacuum chamber and the layers are preferably deposited consecutively without breaking the vacuum. Thereby, one can avoid reactive-metals oxidation in case of the vacuum being broken and / or exposing the reactive metals to oxidative molecules like O2 or H2O.

[0094] Step 408b: Liftoff & Form oxide layer.

[0095] This step may comprise immersing the wafers with both metal films and resist(s) into removers for positive or negative resists and with / without ultrasonication and washed by ethanol or IPA. Then, preferably after cleaning the surface, one may deposit the oxide layer by Sputter or by Atomic layer deposition (ALD) which are equipped with corresponding precursors.

[0096] The thickness of oxide layer is ranging from 3nm to 15nm. The inventors found that an aspect relating to the surprising synergetic technical effect of the ReRAM may further relate to the observation that for relatively-thin oxide layers, quantum tunnelling effects may surprisingly become a dominant factor that causes uncontrollable conductance, thereby causing an on state for the ReRAM that can not be switched off; and in case of relatively-thick oxide layers, it may be more difficult to form conductive paths / filaments and no forming-free behaviour may be observed.

[0097] Step 410b: Patterning & form reactive-metal layer and top electrodes. For patterning, similar as mentioned above for step 406b, resists such as electron-beam lithography resists or photo-lithography resists may be applied, including negative resists as well as positive resists, each with single layer or multi-layer.

[0098] After spin-coating the resists on the wafers by a spin-coater with rpm ranging from 500 to 8000, a PVD system may be applied to form the reactive-metal layer, such as Ti as an example, and the top electrode. The applying of the PVD system is preferably performed in the same vacuum chamber and the layers are preferably deposited consecutively without breaking the vacuum.

[0099] Step 412b: Liftoff & patterning.

[0100] As in step 408b, this step may comprise immersing the wafers with both metal films and resist(s) into removers for positive or negative resists and with / without ultrasonication and washed by ethanol or IPA.

[0101] Step 414b: Contact features formation.

[0102] One may employ for example dry etching techniques ((deep) reactive ion etching) with etching gases selected from SF4, SHF3, CHF3, CF4, Ar, 02, and / or C12. Furthermore, conductive metals for device measurements and / or for establishing further connections to other circuits may be deposited.

[0103] Next, measurement results are presented for the following examples:

[0104] Example la: Pd-30nm / Ti-5nm / HfO2-5nm / Pt-30nm.

[0105] Example lb: Pd-30nm / Ti-5nm / HfO2-5nm / Pd-30nm.

[0106] Example 2: Pd-30nm / Ti-5nm / HfO2-10nm / Pd-30nm.

[0107] Example 3: Pd-30nm / Ti-lOnm / HfO2-10nm / Pd-30nm.

[0108] From left to right, top electrode / reactive-metal layer / oxide layer / bottom electrode.

[0109] Fig- 5 shows a table illustratively comparing properties of Example lb according to the present invention with known ReRAMs. Example lb exhibits operating voltages VSET / VRESET that are comparatively low, while at the same time being manufactured without requiring thermal annealing and / or other special processes such as plasma treatment, and being materialefficient as functioning based on a relatively thin oxide layer of HfCE. Moreover, Example lb shows an endurance of more than 10A4 sec. The references Ref. 1-12 in Fig. 5 are indicated in the “List of references” further below in the present document. As evident by the table, Example lb is the only example among HfCE-based ReRAMs that shows both low operating voltages while at the same time not requiring thermal annealing and / or other special processes. Figs. 6a and 6b show I-V curves of Examples la and lb, in which Example la has Pt as bottom electrode (Fig. 6a) and Example lb has Pd as bottom electrode (Fig. 6b). The horizonal axis “Applied Voltage (V) ” represents a voltage applied to the respective ReRAM, in units of Volt (V), while the vertical axis represents a current through the ReRAM, in units of Ampere (A).

[0110] Depicted are each 1 first cycle followed by 10 cycles of I-V characteristics. The first cycle gives insight into whether an electro-forming process is required or not. Comparing Figs. 6a and 6b shows that choosing Pt leads to the necessity of an electro-forming step (Fig. 6a) but choosing Pd instead does lead to forming-free behaviour (Fig. 6b), as can be recognized by the first cycle. The following 10 cycles confirm that the cycle-to-cycle variation is small enough and that the ReRAMs can continuously work i.e. can continuously be switched on and off. The I-V curves show a hysteric and asymmetric behaviour of the ReRAMs. The current through the oxide layer at high-resistance-state (HRS) and low-resistance-state (LRS) is relatively low, less than the compliance current of about 0,1mA. The low-current and forming-free behaviour exemplifies the ultra-low power consumption of the ReRAM.

[0111] In the I-V curve, the hysteric loop has both HRS and LRS, showcasing that the oxide layer is able to function as data storage / memory. For example, the LRS may represent “on” or ‘T’and the HRS may represent “off’ or “0”, or vice versa.

[0112] The I-V curves include a first voltage range ranging from 0V to 1.5V and a second voltage range from -1.5V to 0V. For example, the operations “set” and “read” can be performed in the first voltage range, the operation “reset” can be performed in the second voltage range. These operations exemplify a bipolar mode. In the present example, the SET switching voltage 604 is around 0.65V and the RESET switching voltage 608 is around -0.7V. Then one can set the sweeping voltage to a value in 0 to 0.65V or 0 to 1.3 V for the SET operation (less than twice the switching voltage is preferred) while for the RESET operation one can set the sweeping voltage at a value from 0 to -0.7V or from 0V to -1.4V. A more negative bias voltage of for example -2V or -3V is undesirable in this example, as the ReRAM would be switched on reversely. The illustrated voltage ranges are by means of example, but are not limited to the given example. For example, one may choose the voltage ranges to have a higher or lower absolute maximum than |+ / - 1.5V|.

[0113] Fig. 6c shows an operation table with various illustrating voltage operations that can be performed on the ReRAM of the present invention. The illustrations are given below by means of example but the invention is not limited to the illustration. For example, other choices for associating SET and RESET with different voltage ranges may be chosen. The SET operation, for setting the oxide layer and thereby the ReRAM into the LRS, is illustrated in the first row of the operation table. In the SET operation, the top electrode is biased to a high voltage in the first voltage range while the bottom electrode is biased to a low voltage such as grounding (“GND”). The difference between the applied high and low voltages provides a SET voltage. The SET voltage is within the first voltage range, thus starts from OV and increases to VSTOP that is equal to or greater than VSET. In an example, VSTOP is around 1.5 V.

[0114] The RESET operation, for resetting the oxide layer and thereby the ReRAM into the HRS, is illustrated in the second row of the operation table. In the RESET operation, a RESET voltage is applied to the top electrode of the ReRAM, the RESET voltage being in the second voltage range from -1.5V to OV. For the RESET operation, one can sweep the applied voltage from OV to -VSTOP. In the example, while VSTOP is around 1.5V, VRESET is approximately -0.7V, so that preferably one chooses VSTOP for RESET more negative than -0.7V, for example -1.5V. In the RESET operation, the top electrode is biased to the second voltage range while the bottom electrode is biased to a low voltage such as grounding ("GND”). The difference between the high and low voltages provides a RESET voltage.

[0115] The SET voltage may refer to the magnitude of the voltage difference and therefore is positive. Similarly for the RESET volage. To completely reset to LRS, the RESET voltage preferably reaches a certain maximum value, such as -1.5V. For Example 1, VSET is around 0.75 V and VRESET is about -0.6 V, as also indicated in the table of Fig. 5.

[0116] In a read operation, the associated read voltage may be any voltage in the first voltage range. Preferably, the reading voltage amplitude is less than 0.6V. The difference between the applied high and low voltages then provides the read voltage. In the present example, the read voltage can be at around 0.1V.

[0117] The “electro-forming” operation shown in the operation table of Fig. 6c is not required for the ReRAM of the present invention. Thus, a higher operating voltage of Vforming may be avoided, thereby reducing power consumption of the ReRAM and enhancing durability.

[0118] For multilevel resistance operations, one can tune the VSTOP for the RESET operation which effectively tunes to what extend filaments / conductive paths can be broken, thereby tuning the resistance of the ReRAM. In an example, the voltages of -1.5 V, -1.4V, -1.3 V, ..., - 0.7V were used as VSTOP for the RESET operation.

[0119] Furthermore, instead of applying sweeping voltages as illustrated above, one could also apply voltage pulses in which the amplitude is equal to VSTOP for all operations of SET, RESET and multilevel resistance operations. The pulse width may depend on the amplitude of pulse bias, but preferably ranges from 5ns to 10s, more preferably 5ns to 1000ns, even more preferably from 5ns to 100ns.

[0120] Figs. 6d and 6e show further I-V characterizations for Example 2 (Fig. 6d) and Example 3 (Fig. 6e), respectively, in which the thicknesses of the Ti layer as reactive-metal is varied and the thickness of the oxide layer is chosen higher than 9nm, in the examples lOnm. Both Fig. 6d and Fig. 6e show the need of an electro-forming step when choosing the oxide-layer thickness higher than 9nm. The surprising synergetic effect of forming-free behaviour is achieved by the ReRAM 1 of the present invention as showcased by Example lb.

[0121] Figs. 6f shows I-V curves of a further example of the forming-free ReRAM according to the present invention, in which the bottom and top electrode metals are selected from Ru. The further example corresponds to Ru-30nm / Ti-5nm / HfO2-5nm / Ru-30nm.

[0122] Fig- 6g showcases that Pd-based ReRAMs exhibit an activation energy that is significantly lower than Pt-based ReRAMs, which means that a lower voltage is required for oxygen vacancies to start migrating to the oxide layer for the first cycle.

[0123] Figs. 7a-7d show the aspect of multilevel resistance of the ReRAM.

[0124] Fig. 7a shows a I-V characterization of Example lb under various compliance currents ranging from 0.1mA to 1.0 mA. The I-V characterization indicates the existence of multi-level resistance states in the ReRAM. The I-V curves for showing multilevel resistance states were achieved by tunning compliance currents (cc); the SET operation in this case related to sweeping the voltage from 0V to 1.5V while the RESET operation in this case related to sweeping the voltage from 0V to -1.5V. The compliance current varies from cycle to cycle (from 0.1mA for the first cycle, 0.1mA for the second cycle, etc., with the final cycle ending at 1.0mA cc).

[0125] Fig 7b shows R-V curves obtained from Fig. 7a, which demonstrates multilevel resistance states.

[0126] Fig 7c shows I-V curves showing multilevel resistance states achieved by tunning VSTOP for RESET operation: the SET operation in this case related to sweeping the voltage from 0V to 1.0V while the RESET operation in this case related to sweeping the voltage from 0V to - VSTOP (VSTOP varies from cycle to cycle: from 1.5 V for the initial cycle, followed by 1.4V for the second cycle, and ending with 0.6V for the final cycle); the compliance current is fixed at 0.3mA for all cycles in this example.

[0127] Fig. 7d shows R-read# curves (# of reads, i.e., number of reads) for showing multilevel resistance states by reading different resistance state from Fig. 7c. The horizonal axis relates to reading times for each resistance state. Fig.7d showcases that different resistance state are very stable, as also with many reading operations, they still remains their initial resistance states respectively without noticeable change.

[0128] Figs. 8 and 9 show an endurance test and retention test for Example lb, respectively.

[0129] For the endurance test of Fig. 8, a reading voltage of VREAD= 0.1V was applied and voltage sweeping over 2600 cycles was performed.

[0130] For the retention test of Fig. 9, a reading voltage of 0.1V was applied on top electrodes with interval measurements being performed every 60s, up to 113k seconds. Similarly, after SET operation applying first voltage range, a reading voltage of 0.1 V was applied on top electrodes with interval measurements being performed every 60s, up to 113k seconds. The data shows an on / off ration of about 17 for the ration of HRS / LRS.

[0131] Fig- 8 shows resistance-number of cycles (#cycles): the upper grey-color dots represent high resistance values and the lower black dots represent low resistance values depending on different number of cycles. From Fig. 8, one can conclude that the ReRAM can endure more than 2600 cycles without on / off ratio degradation. The data in this example is read at 0.1V after SET operation followed by RESET. The SET -RESET combination represents one cycle. After one cycle, repeat operations as read(HRS values)-SET-read(LRS values) so that one can plot them as shown in Fig 8. One can also read the HRS and LRS at -0. IV, but in this example they were read at positive bias.

[0132] Fig. 9 shows R-t curves which characterize the memory retention of the ReRAM: the grey-color dots on top represent the values of HRS, reading at 0.1V once every 60 seconds. After 113000 seconds, the ReRAM was switched (SET operation) and one started to read the LRS values at 0. IV once every 60 seconds, again with a test duration of 113000 seconds.

[0133] Fig. 9 showcases that within 113000 seconds, the resistance state can be retained at least 113000 seconds at room temperature without any noticeable degradation.

[0134] Fig. 10 illustrates schematically compares an example of the ReRAM of the present invention with another ReRAM, which may illuminate the forming-free behaviour of the ReRAM of the present invention. The left illustration corresponds to an example of the ReRAM of the present invention, while the right illustration corresponds to a fully Pt-based ReRAM. The employing of lower work function metals such as Pd may potentially bind oxygen ions from the interface between Pd and HfCE so that larger amount of oxygen vacancies are created in HfCE than compared to the Pt-based ReRAM. Area 1108 illustrates oxygen-Pd bonds and oxygen vacancies above thereof, which can result in the LRS. In comparison, area 1106 illustrates that the bonding of Pt-0 may be comparatively neglectable so that there is no substantial oxygen vacancies in HfCh, thereby incurring the mandatory operation of electroforming step to activate the Pt-based ReRAM.

[0135] Aspects of the present document can be understood from the following clauses.

[0136] 1. Resistive random-access memory, ReRAM, (1) for performing forming-free resistive switching, the ReRAM (1) comprising: a bottom electrode (20) disposed on a substrate (10); an oxide layer (30) disposed on the bottom electrode (20); a reactive-metal layer (40) disposed on the oxide layer (30); and a top electrode (50) disposed on the reactive-metal layer (40); wherein: the bottom electrode (20) comprises a first inert metal selected from Pd, Rh, Ru,

[0137] Os, Re, Ir, Au, and / or combinations thereof, the oxide layer (30) has a thickness between 3nm and 9nm, the reactive-metal layer (40) comprises a first reactive metal selected from Cd,

[0138] Ag, Ta, Nb, Ti, Ta, W, Zr, Al, and / or combinations thereof, and the top electrode (50) comprises a second inert metal selected from Pt, Pd, Rh, Ru, Os, Re, Ir, Au, and / or combinations thereof.

[0139] 2. The ReRAM (1) of any one of the preceding clauses, wherein: the oxide layer (30) comprises a layer of HfO? directly contacting the bottom electrode (20), and preferably the oxide layer (30) is made of HfCh.

[0140] 3. The ReRAM (1) of any one of the preceding clauses, wherein: the first reactive metal is selected from Cd, Ag, Ti, W, Zr, Al, and / or combinations thereof, and preferably the first reactive metal is Ti.

[0141] 4. The ReRAM (1) of any one of the preceding clauses, wherein: the reactive-metal layer (40) has a thickness between 5nm and lOOnm, preferably between 5nm and 50nm, more preferably between 5nm and 15nm, even more preferably between 5nm and 12nm, most preferably between 5nm and lOnm.

[0142] 5. The ReRAM (1) of any one of the preceding clauses, wherein: the thickness of the oxide layer (30) is between 3nm and 8nm, more preferably between 3nm and 7nm, even more preferably between 3nm and 6nm, most preferably between 4nm and 6nm.

[0143] 6. The ReRAM (1) of any one of clauses 1-5, wherein: the reactive-metal layer (40) has a thickness between 5nm and 15nm, preferably between 5nm and lOnm. 7. The ReRAM (1) of any one of clauses 1-4, wherein: the thickness of the oxide layer (30) is between 4nm and 6nm, and the reactive-metal layer (40) has a thickness between 5nm and lOnm.

[0144] 8. The ReRAM (1) of any one of the preceding clauses, wherein: the bottom electrode (20) comprises the first inert material selected from Pd, Rh, Ru, Re, and / or combinations thereof, the top electrode (50) comprises the second inert metal selected from Pd, Rh, Ru, Re, and / or combinations thereof, and the reactive-metal layer (40) comprises Ti.

[0145] 9. The ReRAM (1) of any one of clauses 1-7, wherein: the bottom electrode (20) comprises the first inert material selected from Pd, Rh, and / or combinations thereof, the top electrode (50) comprises the second inert metal selected from Pd, Rh, and / or combinations thereof, and the reactive-metal layer (40) comprises Ti.

[0146] 10. The ReRAM (1) of any one of clauses 1-7, wherein: the bottom electrode (20) comprises Pd, the top electrode (50) comprises Pd, and the reactive-metal layer (40) comprises Ti.

[0147] 11. The ReRAM (1) of any one of the preceding clauses, wherein: the bottom electrode (20) has a thickness between 0.3nm and 500nm, and / or the top electrode (50) has a thickness between 0.3nm and 500nm.

[0148] 12. The ReRAM (1) of any one of the preceding clauses, wherein the substrate (10) comprises a SiCh layer, and preferably the SiCh layer has a thickness between lOnm and 5000nm.

[0149] 13. The ReRAM (1) of any one of the preceding clauses, wherein the first reactive metal is selected from Ti, Zr, Hf, and Nb. The metals Zr and Hf have similar reactive properties as Ti and may therefore also be used as the first reactive metal.

[0150] 14. A computer-architecture, such as a chip, comprising one or more instances of the ReRAM (1) of any one of the preceding clauses.

[0151] 15. Method (4) of manufacturing the ReRAM (1) of any one of clauses 1-12, the method comprising: providing (402a) the substrate; disposing (404a) the bottom electrode (20) on the substrate (10); disposing (406a) the oxide layer (30) on the bottom electrode (20); disposing (408a) the reactive-metal layer (40) on the oxide layer (30); and disposing (410a) the top electrode (50) on the reactive-metal layer (40).

[0152] The following list of references is referred to in the present document and is incorporated herein by way of reference. List of references

[0153] Ref l: 10.1109 / TED.2022.3215932 / 10.1038 / srep28525

[0154] Ref 2: 10.1109 / LED.2010.2081658

[0155] Ref 3: 10.1002 / aelm.201901290.

[0156] Ref 4: 10.1002 / pssa.201900756 Ref 5: 10.1088 / 1361-6528 / ab2507

[0157] Ref 6: 10.1088 / 1361-6528 / aab9el

[0158] Ref 7: 10.1109 / LED.2018.2821162

[0159] Ref 8: 10.1186 / 1556-276X-9-45

[0160] Ref 9: 10.1587 / elex. l7.20200343 Ref 10: 10.1109 / TED.2023.3247369

[0161] Ref 11: 10.1109 / LED.2013.2262917

[0162] Ref 12: 10.1109 / ESSDERC.2016.7599612

Claims

What is claimed is:

1. Resistive random-access memory, ReRAM, (1) for performing forming-free resistive switching, the ReRAM (1) comprising: a bottom electrode (20) disposed on a substrate (10); an oxide layer (30) disposed on the bottom electrode (20); a reactive-metal layer (40) disposed on the oxide layer (30); and a top electrode (50) disposed on the reactive-metal layer (40); wherein: the bottom electrode (20) comprises a first inert metal selected from Pd, Rh, Ru, Re, and / or combinations thereof, the oxide layer (30) has a thickness between 3nm and 9nm, the reactive-metal layer (40) comprises Ti, and the top electrode (50) comprises a second inert metal selected from Pd, Rh, Ru, Re, and / or combinations thereof.

2. The ReRAM (1) of any one of the preceding claims, wherein: the oxide layer (30) comprises a layer of HfCh directly contacting the bottom electrode (20), and preferably the oxide layer (30) is made of HfCh.

3. The ReRAM (1) of any one of the preceding claims, wherein: the reactive-metal layer (40) has a thickness between 5nm and lOOnm, preferably between 5nm and 50nm, more preferably between 5nm and 15nm, even more preferably between 5nm and 12nm, most preferably between 5nm and lOnm.

4. The ReRAM (1) of any one of the preceding claims, wherein: the thickness of the oxide layer (30) is between 3nm and 8nm, more preferably between 3nm and 7nm, even more preferably between 3nm and 6nm, most preferably between 4nm and 6nm.

5. The ReRAM (1) of any one of claims 1-4, wherein: the reactive-metal layer (40) has a thickness between 5nm and 15nm, preferably between 5nm and lOnm.

6. The ReRAM (1) of any one of claims 1-3, wherein: the thickness of the oxide layer (30) is between 4nm and 6nm, and the reactive-metal layer (40) has a thickness between 5nm and lOnm.

7. The ReRAM (1) of any one of claims 1-6, wherein: the bottom electrode (20) comprises the first inert material selected from Pd, Rh, and / or combinations thereof, the top electrode (50) comprises the second inert metal selected from Pd, Rh, and / or combinations thereof, and the reactive-metal layer (40) comprises Ti.

8. The ReRAM (1) of any one of claims 1-6, wherein: the bottom electrode (20) comprises Pd, the top electrode (50) comprises Pd, and the reactive-metal layer (40) comprises Ti.

9. The ReRAM (1) of any one of the preceding claims, wherein: the bottom electrode (20) has a thickness between 0.3nm and 500nm, and / or the top electrode (50) has a thickness between 0.3nm and 500nm.

10. The ReRAM (1) of any one of the preceding claims, wherein the substrate (10) comprises a SiCh layer, and preferably the SiCh layer has a thickness between lOnm and 5000nm.

11. A computer-architecture, such as a chip, comprising one or more instances of the ReRAM (1) of any one of the preceding claims.

12. Method (4) of manufacturing the ReRAM (1) of any one of claims 1-10, the method comprising: providing (402a) the substrate; disposing (404a) the bottom electrode (20) on the substrate (10); disposing (406a) the oxide layer (30) on the bottom electrode (20); disposing (408a) the reactive-metal layer (40) on the oxide layer (30); and disposing (410a) the top electrode (50) on the reactive-metal layer (40).

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