Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device having micro-sized transistors. The semiconductor device includes: first to fourth conductive layers; a semiconductor layer; and first to third insulative layers. The first conductive layer, the first insulative layer, the second conductive layer, the second insulative layer, and the third conductive layer overlap in the given order. The first insulative layer, the second conductive layer, the second insulative layer, and the third conductive layer have an opening reaching the first conductive layer. In the opening, the semiconductor layer contacts an upper surface of the first conductive layer, a lateral surface of the first insulative layer, a lateral surface of the second conductive layer, a lateral surface of the second insulative layer, and a lateral surface of the third conductive layer. The third insulative layer contacts an upper surface of the semiconductor layer. The fourth conductive layer overlaps the opening and contacts an upper surface of the third insulative layer.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a transistor, a method for manufacturing a semiconductor device, and a method for manufacturing a display device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), an electronic device including any of these devices, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for semiconductor devices with higher integration and faster speeds. For example, when semiconductor devices are applied to high-resolution display devices, semiconductor devices with higher integration levels are required. As one means for increasing the integration level of transistors, development of fine-sized transistors is underway.

[0005] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) devices, and light-emitting devices including light-emitting devices (also referred to as light-emitting elements) such as light-emitting diodes (LEDs).

[0006] Patent Document 1 discloses a display device for VR that uses an organic EL device (also called an organic EL element).

[0007] International Publication No. 2018 / 087625

[0008] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a small-sized semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0010] In order to further increase the integration density of semiconductor devices, it is effective to miniaturize the transistors included in the semiconductor device and to devise a layout for the transistors. For example, it is effective to arrange multiple transistors included in a semiconductor device in a stacked manner perpendicular to the substrate surface, rather than arranging them on the same plane. This allows for increased integration density of semiconductor devices without increasing the area occupied by the transistors on the substrate surface.

[0011] Furthermore, by using vertical transistors (transistors in which the source electrode and the drain electrode are provided at different heights relative to the substrate surface and the drain current flows in the height direction (vertical direction)) as the multiple transistors arranged in a stack, the area occupied by the semiconductor device in a planar view can be reduced compared to when using planar transistors (transistors in which the source electrode and the drain electrode are provided on the same plane and the drain current flows in a direction parallel to the plane (horizontal direction)).

[0012] Furthermore, for example, when two vertical transistors are stacked, rather than simply stacking them, a configuration in which the components of each transistor are shared can be realized, achieving a configuration equivalent to stacking the two. For example, one of the source electrode or drain electrode (the electrode located on the upper side as viewed from the substrate surface) of a first vertical transistor can be shared with one of the source electrode or drain electrode (the electrode located on the lower side as viewed from the substrate surface) of a second vertical transistor located on the first vertical transistor. Furthermore, the semiconductor layer, gate insulating layer, and gate electrode can also be shared between the two vertical transistors. When planar transistors are stacked, it is difficult to achieve the above due to the transistor structure.

[0013] Therefore, by stacking multiple vertical transistors, the area occupied by the semiconductor device in plan view can be reduced compared to when multiple planar transistors are stacked. Furthermore, when stacking multiple vertical transistors, the transistors can share some of their components as described above, so the number of steps required to manufacture the semiconductor device can be reduced compared to when multiple planar transistors are stacked.

[0014] In view of the above, one embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer, in which the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are stacked in this order, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have an opening reaching the first conductive layer, and in the opening, the semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer, the third insulating layer is in contact with a top surface of the semiconductor layer, and the fourth conductive layer overlaps with the opening and is in contact with a top surface of the third insulating layer.

[0015] In the above, it is preferable that the semiconductor layer contains a metal oxide, and at least one of the first insulating layer and the second insulating layer contains silicon oxide or silicon oxynitride.

[0016] In the above, it is preferable that the metal oxide contains two or three elements selected from indium, an element M, and zinc, and that the element M contains one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium.

[0017] Furthermore, in the above, it is preferable that the first insulating layer has a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, the second insulating layer has a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer, and that the fourth insulating layer, the sixth insulating layer, the seventh insulating layer, and the ninth insulating layer each have silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and that the fifth insulating layer and the eighth insulating layer each have silicon oxide or silicon oxynitride.

[0018] In the above, it is preferable that a tenth insulating layer is provided on the fourth conductive layer so as to have an area overlapping with the opening, and that the tenth insulating layer has one or both of an organic insulating material and an inorganic insulating material.

[0019] In addition, in the above, it is preferable that the tenth insulating layer contains one or more selected from acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins.

[0020] In the above, the upper surface of the fourth conductive layer is preferably located above the upper end of the side surface of the second conductive layer facing the opening.

[0021] Another embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer, in which the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, the fourth insulating layer, and the fifth conductive layer are stacked in this order, and the fifth conductive layer has an opening reaching the first conductive layer, and within the opening, the fifth insulating layer is in contact with a part of the upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, a side surface of the third conductive layer, a side surface of the third insulating layer, a side surface of the fourth conductive layer, a side surface of the fourth insulating layer, and a side surface of the fifth conductive layer, and within the opening, the semiconductor layer is in contact with another part of the upper surface of the first conductive layer and the side surface of the fifth insulating layer, the sixth insulating layer is in contact with the upper surface of the semiconductor layer, and the sixth conductive layer overlaps the opening and is in contact with the upper surface of the sixth insulating layer.

[0022] In the above, it is preferable that the semiconductor layer contains a metal oxide, and at least one of the first insulating layer and the second insulating layer contains silicon oxide or silicon oxynitride.

[0023] In the above, it is preferable that the metal oxide contains two or three elements selected from indium, an element M, and zinc, and that the element M contains one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium.

[0024] In the above, the first insulating layer includes a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer, the second insulating layer includes a tenth insulating layer, an eleventh insulating layer on the tenth insulating layer, and a twelfth insulating layer on the eleventh insulating layer, the third insulating layer includes a thirteenth insulating layer, a fourteenth insulating layer on the thirteenth insulating layer, and a fifteenth insulating layer on the fourteenth insulating layer, and the fourth insulating layer includes a sixteenth insulating layer and a seventeenth insulating layer on the sixteenth insulating layer. and an 18th insulating layer on the 17th insulating layer, wherein the seventh insulating layer, the ninth insulating layer, the tenth insulating layer, the twelfth insulating layer, the thirteenth insulating layer, the fifteenth insulating layer, the sixteenth insulating layer, and the eighth insulating layer each preferably comprise silicon nitride, silicon nitride oxide, hafnium oxide, or aluminum oxide, and the eighth insulating layer, the eleventh insulating layer, the fourteenth insulating layer, and the seventeenth insulating layer each preferably comprise silicon oxide or silicon oxynitride.

[0025] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a first conductive layer, a first insulating film, a second conductive layer, a second insulating film, and a third conductive layer in this order; removing parts of the first insulating film, the second conductive layer, the second insulating film, and the third conductive layer to form an opening reaching the first conductive layer; forming the first insulating layer, a fourth conductive layer, the second insulating layer, and a fifth conductive layer; forming a semiconductor layer in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the fourth conductive layer, a side surface of the second insulating layer, and a side surface of the fifth conductive layer in the opening; forming a third insulating layer in contact with a top surface of the semiconductor layer; and forming a sixth conductive layer over the third insulating layer to overlap with the opening.

[0026] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a small-sized semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is a cross-sectional view showing an example of a semiconductor device. FIG. 2A is a cross-sectional view showing an example of a semiconductor device. FIG. 2B is a circuit diagram illustrating the semiconductor device. FIGS. 3A to 3D are circuit diagrams illustrating an operation example of the semiconductor device. FIG. 4A is a circuit diagram illustrating an operation example of the semiconductor device. FIG. 4B is a circuit diagram illustrating the semiconductor device. FIG. 5A is a plan view showing an example of a semiconductor device. FIG. 5B is a cross-sectional view showing an example of a semiconductor device. FIG. 6A is a cross-sectional view showing an example of a semiconductor device. FIG. 6B is a circuit diagram illustrating the semiconductor device. FIGS. 7A and 7B are circuit diagrams illustrating an operation example of the semiconductor device. FIG. 8A is a plan view showing an example of a semiconductor device. FIG. 8B is a cross-sectional view showing an example of a semiconductor device. FIG. 9 is a cross-sectional view showing an example of a semiconductor device. FIG. 10 is a circuit diagram illustrating the semiconductor device. FIGS. 11A and 11B are circuit diagrams illustrating an operation example of the semiconductor device. FIGS. 12A and 12B are circuit diagrams illustrating an operation example of the semiconductor device. FIGS. 13A and 13B are circuit diagrams illustrating an operation example of the semiconductor device. 14A and 14B are circuit diagrams illustrating an example of operation of a semiconductor device. FIG. 15 is a circuit diagram illustrating an example of operation of a semiconductor device. FIG. 16 is a circuit diagram illustrating a semiconductor device. FIG. 17A is a plan view illustrating an example of a semiconductor device. FIG. 17B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 19 is a circuit diagram illustrating a semiconductor device. FIGS. 20A and 20B are circuit diagrams illustrating an example of operation of a semiconductor device. FIGS. 21A and 21B are cross-sectional views illustrating an example of a semiconductor device. FIG. 22 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 23B and 23C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 24A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 24B and 24C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 25A is a plan view illustrating an example of a method for manufacturing a semiconductor device.25B and 25C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 26A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 26B and 26C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 27B and 27C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 28B and 28C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 29A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 29B and 29C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 30A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 30B and 30C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 31A is a diagram illustrating an example of a configuration of a sequential circuit. FIG. 31B is a circuit diagram of a shift register. FIG. 31C is a timing chart. FIGS. 32A and 32B are diagrams illustrating an example of a configuration of a sequential circuit. 33A and 33B are diagrams showing an example of the configuration of a sequential circuit. FIGS. 34A to 34D are diagrams showing an example of an electronic device. FIGS. 35A to 35F are diagrams showing an example of an electronic device. FIGS. 36A to 36F are diagrams showing an example of an electronic device.

[0029] The following description of the preferred embodiments will be given in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the preferred embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0033] A transistor is a type of semiconductor element that can realize functions such as amplifying current or voltage, and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed to the source terminal and drain terminal, or the source electrode and drain electrode, etc., depending on the situation.

[0035] The terms "gate" and "back gate" can be interchanged. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0036] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0037] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no exchange of an electric signal or an interaction of electric potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an exchange of an electric signal or an interaction of electric potential occurs between A and B.

[0038] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0039] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0040] In this specification and the like, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).

[0041] In this specification, the phrase "top surface shapes generally match" means that at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0042] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0043] Furthermore, in this specification and the like, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are approximately the same in a cross-sectional view. For example, when a planarization process (typically, a chemical mechanical polishing (CMP) process) is performed, the heights of the processed surfaces are approximately the same. However, even when a planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification and the like, this case is also considered to be "approximately the same height."

[0044] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention, a manufacturing method of the semiconductor device, and the like will be described.

[0045] One embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer.

[0046] Among these, the first conductive layer, the second conductive layer, the fourth conductive layer, the semiconductor layer, and the third insulating layer can function as components of a first transistor, and the second conductive layer, the third conductive layer, the fourth conductive layer, the semiconductor layer, and the third insulating layer can function as components of a second transistor.

[0047] Therefore, it can also be said that the semiconductor device has a first transistor and a second transistor. Both the first transistor and the second transistor are vertical transistors. The second transistor is stacked on the first transistor. Therefore, it can be said that the semiconductor device has a configuration in which two vertical transistors are stacked.

[0048] The first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are stacked in this order so as to have overlapping regions.

[0049] The first conductive layer functions as one of a source electrode and a drain electrode of the first transistor. The second conductive layer functions as the other of the source electrode and the drain electrode of the first transistor and also functions as one of the source electrode and the drain electrode of the second transistor. The third conductive layer functions as the other of the source electrode and the drain electrode of the second transistor. The first insulating layer is provided between the first conductive layer and the second conductive layer and functions as a spacer between the source electrode and the drain electrode of the first transistor. The second insulating layer is provided between the second conductive layer and the third conductive layer and functions as a spacer between the source electrode and the drain electrode of the second transistor.

[0050] The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have an opening that reaches the first conductive layer. A semiconductor layer is provided in the opening and in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer. A third insulating layer is provided in contact with a top surface of the semiconductor layer. Furthermore, a fourth conductive layer is provided in contact with a top surface of the third insulating layer so as to have a region overlapping the opening.

[0051] A part of the semiconductor layer functions as a channel formation region of the first transistor, and another part of the semiconductor layer functions as a channel formation region of the second transistor. A part of the third insulating layer functions as a gate insulating layer of the first transistor, and another part of the third insulating layer functions as a gate insulating layer of the second transistor. A part of the fourth conductive layer functions as a gate electrode of the first transistor, and another part of the fourth conductive layer functions as a gate electrode of the second transistor.

[0052] That is, in the semiconductor device of one embodiment of the present invention, the first transistor and the second transistor share one of a source electrode or a drain electrode, a semiconductor layer, a gate insulating layer, and a gate electrode.

[0053] The semiconductor device according to one embodiment of the present invention has the above-described structure, which enables miniaturization and higher integration of the semiconductor device compared to a structure in which two planar transistors are stacked. Furthermore, since the two transistors can share some of their components, the number of steps required for manufacturing the semiconductor device can be reduced compared to a structure in which two transistors are simply stacked.

[0054] For example, when the semiconductor device of one embodiment of the present invention is used in a scan line driver circuit (also referred to as a gate line driver circuit or a gate driver) of a display device, vertical transistors can be used as each of a plurality of transistors included in the scan line driver circuit, and the transistors whose source electrodes or drain electrodes are connected to each other can be stacked. This can reduce the area occupied by the scan line driver circuit and narrow the frame of the display device.

[0055] Furthermore, depending on the location of the scanning line driving circuit, for example, a high voltage applied from a power supply may place a heavy load on some transistors. For example, in the case of a transistor connected in a manner that allows a high voltage to be applied to its source electrode or drain electrode, the transistor is required to have sufficient resistance to the applied voltage (source-drain breakdown voltage). One solution to this problem is, for example, connecting multiple transistors in series to divide the source-drain voltage applied to each transistor. Furthermore, depending on the location of the scanning line driving circuit, for example, a transistor with a large on-state current may be required to supply an amplified signal to a circuit connected in a subsequent stage. One solution to this problem is, for example, connecting multiple transistors in parallel to increase the total output current of all transistors. Although the above is just one example, in either case, the need to connect multiple transistors in series or in parallel poses the problem of significantly increasing the area occupied by the transistors in the scanning line driving circuit.

[0056] In contrast, the semiconductor device of one embodiment of the present invention has a structure in which multiple vertical transistors are stacked so as to share some components, as described above. Therefore, even if the number of stacked transistors is increased, the area occupied by the transistors can be suppressed from increasing. Furthermore, by applying different voltages to the source and drain electrodes of multiple stacked vertical transistors, the transistors can be appropriately switched between being connected in series or in parallel. Therefore, it is not necessary to create different transistor configurations (sizes, number of connections, etc.) for each region of the scan line driver circuit. Simply by varying the magnitude of the voltage applied to each electrode in the stacked structure of the vertical transistors described above, a highly high-performance scan line driver circuit can be realized without increasing the area occupied. Therefore, the number of steps required to manufacture the entire scan line driver circuit can be reduced compared to when different transistor configurations are used for each region.

[0057] Below, specific structural examples of the semiconductor device of one embodiment of the present invention will be described with reference to the drawings.

[0058] <Configuration Example 1 of Semiconductor Device> Fig. 1A shows a plan view (also referred to as a top view) of a semiconductor device 100A. Fig. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 1A, and Fig. 2A shows a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 1A. Fig. 2B shows a circuit diagram illustrating the configuration of the semiconductor device 100A. Note that Fig. 1A omits some of the components of the semiconductor device 100A (insulating layers, etc.). As with Fig. 1A, some of the components will also be omitted in plan views of semiconductor devices and the like in the following drawings.

[0059] The semiconductor device 100A is provided over a substrate 102. Although not shown in FIG. 1B and other drawings, an insulating layer functioning as a base film may be provided between the substrate 102 and the semiconductor device 100A. The semiconductor device 100A includes a transistor 10A_1, a transistor 10A_2, an insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1), and an insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2). The transistor 10A_1 and the transistor 10A_2 share some components and are provided overlapping in this order.

[0060] The transistor 10A_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. A part of the conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode. The conductive layer 112b functions as the other of the source electrode and the drain electrode. A region of the semiconductor layer 108 that faces the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region of the semiconductor layer 108 that is in contact with the drain electrode functions as a drain region.

[0061] The transistor 10A_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112b, and a conductive layer 112c. Another part of the conductive layer 104 functions as a gate electrode. Another part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112b functions as one of a source electrode and a drain electrode. The conductive layer 112c functions as the other of the source electrode and the drain electrode. A region of the semiconductor layer 108 that faces the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region of the semiconductor layer 108 that is in contact with the drain electrode functions as a drain region.

[0062] That is, in the semiconductor device 100A, the conductive layer 104 functions as a gate electrode of the transistor 10A_1 and also functions as a gate electrode of the transistor 10A_2. The insulating layer 106 functions as a gate insulating layer of the transistor 10A_1 and also functions as a gate insulating layer of the transistor 10A_2. The semiconductor layer 108 functions as a semiconductor layer of the transistor 10A_1 and also functions as a semiconductor layer of the transistor 10A_2. The conductive layer 112b functions as the other of the source and drain electrodes of the transistor 10A_1 and also functions as one of the source and drain electrodes of the transistor 10A_2.

[0063] In this manner, in the semiconductor device 100A, the transistors 10A_1 and 10A_2 are stacked and share some of their components. In addition, the semiconductor device 100A can be said to have a configuration in which some of the electrodes (one (or the other) of the source electrode or the drain electrode and the gate electrode) of the transistors 10A_1 and 10A_2 are connected to each other.

[0064] The detailed configuration of the semiconductor device 100A will be described below.

[0065] A conductive layer 112a is provided on the substrate 102. FIGS. 1A and 1B show a configuration in which the conductive layer 112a extends toward the A2 side of the dashed-dotted line A1-A2. An insulating layer 110a1 is provided on the conductive layer 112a and the substrate 102. An insulating layer 110b1 is provided on the insulating layer 110a1. An insulating layer 110c1 is provided on the insulating layer 110b1. A conductive layer 112b is provided on the insulating layer 110c1. FIGS. 1A and 1B show a configuration in which the conductive layer 112b extends toward the A1 side of the dashed-dotted line A1-A2. Note that the insulating layers 110a1, 110b1, and 110c1 may be collectively referred to as insulating layer 110_1.

[0066] The conductive layer 112a, the insulating layer 110_1, and the conductive layer 112b overlap with each other in a region where the insulating layer 110_1 is sandwiched between the conductive layer 112a and the conductive layer 112b.

[0067] An insulating layer 110a2 is provided on the conductive layer 112b and the insulating layer 110c1. An insulating layer 110b2 is provided on the insulating layer 110a2. An insulating layer 110c2 is provided on the insulating layer 110b2. A conductive layer 112c is provided on the insulating layer 110c2. In FIGS. 1A and 1B, the conductive layer 112c extends to the A2 side of the dashed dotted line A1-A2. Note that the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2 may be collectively referred to as the insulating layer 110_2.

[0068] The conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c have a region where they overlap with each other. In this region, the insulating layer 110_2 is sandwiched between the conductive layer 112b and the conductive layer 112c.

[0069] The conductive layer 112a, the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c have overlapping regions.

[0070] The insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c have an opening 143 that reaches the conductive layer 112a.

[0071] The top surface shape of the opening 143 can be, for example, circular or elliptical. The top surface shape of the opening 143 may be a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), or a pentagon, or a polygon with rounded corners. As shown in FIG. 1A , the top surface shape of the opening 143 is preferably circular. By making the top surface shape of the opening 143 circular, the processing accuracy when forming the opening 143 can be improved, and the opening 143 can be formed with a fine size. Note that in this specification and the like, a circle is not limited to a perfect circle.

[0072] 1B and 2A show a configuration in which the thickness of the conductive layer 112a in the region overlapping with the opening 143 is approximately equal to the thickness of the region not overlapping with the opening 143, but this is not limited thereto. The thickness of the conductive layer 112a in the region overlapping with the opening 143 may be thinner than the thickness of the region not overlapping with the opening 143. In this case, the electric field from the conductive layer 104 can be applied to the channel formation region of the transistor 10A_1 near the conductive layer 112a. Therefore, the effect of the gate electric field on carriers in the channel formation region of the transistor 10A_1 can be strengthened in some cases compared to when the conductive layer 112a has a uniform thickness.

[0073] The semiconductor layer 108 is provided in contact with the top surface of the conductive layer 112a in the opening 143, the side surface of the insulating layer 110_1 in the opening 143, the side surface of the conductive layer 112b in the opening 143, the side surface of the insulating layer 110_2 in the opening 143, the side surface of the conductive layer 112c in the opening 143, and the top surface of the conductive layer 112c.

[0074] 1B and 2A show a configuration in which the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112c, but this is not limiting. The semiconductor layer 108 only needs to have a region in contact with the side surface of the conductive layer 112c in at least the opening 143.

[0075] For example, by configuring the entire semiconductor layer 108 to be located within the opening 143 and the end of the semiconductor layer 108 to be in contact only with the side surface of the conductive layer 112c within the opening 143, it is possible to prevent the end of the semiconductor layer 108 from causing a step on the conductive layer 112c. This can improve the coverage of a film on the top surface of the conductive layer 112c as a formation surface.

[0076] 1B and 2A , by configuring the semiconductor layer 108 so that the end portion thereof extends to the outside of the opening 143 and the semiconductor layer 108 is in contact with not only the side surface of the conductive layer 112c in the opening 143 but also the top surface of the conductive layer 112c, the contact area between the semiconductor layer 108 and the conductive layer 112c can be increased. This can prevent the semiconductor layer 108 from peeling off. Furthermore, the contact resistance between the semiconductor layer 108 and the conductive layer 112c can be reduced, which can increase the on-state current of the transistor 10A_2 in some cases.

[0077] Here, the insulating layer 110b1 of the insulating layer 110_1 is preferably an insulating layer containing oxygen. Furthermore, it is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layer 110b1 can be supplied to the metal oxide. This can repair oxygen vacancies in the metal oxide, thereby improving the electrical characteristics and reliability of the transistor 10A_1.

[0078] On the other hand, the insulating layer 110a1 and the insulating layer 110c1 of the insulating layer 110_1 preferably have a blocking property against gases such as oxygen and hydrogen. This can prevent oxygen contained in the insulating layer 110b1 from being released to the outside through the insulating layer 110a1 or the insulating layer 110c1. Furthermore, it can prevent hydrogen from diffusing from the outside of the insulating layer 110_1 into the insulating layer 110b1 through the insulating layer 110a1 or the insulating layer 110c1 and then diffusing into the semiconductor layer 108. For example, when a metal oxide is used for the semiconductor layer 108, hydrogen in the semiconductor layer 108 can cause deterioration of the electrical characteristics and reliability of the transistor 10A_1.

[0079] Note that the description of transistor 10A_1 above can also be applied to transistor 10A_2 by replacing insulating layer 110_1, insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1 with insulating layer 110_2, insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2, respectively.

[0080] An insulating layer 106 is provided over the semiconductor layer 108. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112c, and the top surface of the insulating layer 110c2.

[0081] A conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 is provided in contact with the upper surface of the insulating layer 106 so as to have a region overlapping with the opening 143 in a plan view. FIGS. 1A and 2A show a configuration in which the conductive layer 104 extends to the B2 side of the dashed dotted line B1-B2. The conductive layer 104 has a shape that conforms to the shapes of the semiconductor layer 108 and the insulating layer 106 within the opening 143. That is, the conductive layer 104 has a recess on its upper surface that corresponds to the shape of the opening 143. The conductive layer 104 has a region within the opening 143 that faces the semiconductor layer 108 with the insulating layer 106 interposed therebetween.

[0082] The conductive layer 104 can also be formed so as to fill the opening 143. For example, depending on the size of the diameter of the opening 143 in a plan view, the conductive layer 104 may be formed so as to fill the opening 143. In this case, the step or unevenness formed on the upper surface of the conductive layer 104 in the region overlapping with the opening 143 is reduced, which is preferable because the coverage of the layer formed thereon can be improved.

[0083] In the transistor 10A_1, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. Similarly, in the transistor 10A_2, the source electrode and the drain electrode are located at different heights with respect to the surface of the insulating layer 110_1, which is a surface where the transistor is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the substantially flat surface of the insulating layer 110_1. That is, in the transistors 10A_1 and 10A_2, the drain current flows in the vertical direction or approximately vertically. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0084] Since the source electrode and the drain electrode of each of the transistors 10A_1 and 10A_2 can be overlapped, the transistors can be made smaller than a so-called planar transistor in which the source electrode and the drain electrode are arranged on the same plane, and the area occupied by the transistor within the substrate surface can be significantly reduced.

[0085] Furthermore, in the semiconductor device 100A of one embodiment of the present invention, the transistor 10A_2 is provided overlapping the transistor 10A_1, sharing some of the components. Therefore, the area occupied by the transistors in the substrate surface can be significantly reduced compared to a configuration in which the two transistors are arranged on the same plane, thereby enabling miniaturization and high integration of the semiconductor device. For example, when the semiconductor device of one embodiment of the present invention is used in a scan line driver circuit of a display device, vertical transistors can be used for each of the multiple transistors constituting the scan line driver circuit, and transistors that share some of the components, such as the transistors 10A_1 and 10A_2, or transistors whose electrodes are connected to each other can be stacked on each other. This reduces the area occupied by the scan line driver circuit, thereby realizing a display device with an extremely narrow frame. Furthermore, since the transistors 10A_1 and 10A_2 share some of the components, the number of steps required to manufacture the entire semiconductor device can be reduced compared to a configuration in which the transistors are provided separately.

[0086] The channel lengths and channel widths of the transistors 10A_1 and 10A_2 will be described.

[0087] In the transistor 10A_1, a region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of a source region and a drain region, a region of the semiconductor layer 108 in contact with the conductive layer 112b functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region. In the transistor 10A_2, a region of the semiconductor layer 108 in contact with the conductive layer 112b functions as one of the source region and the drain region, a region of the semiconductor layer 108 in contact with the conductive layer 112c functions as the other of the source region and the drain region, and a region between the source region and the drain region functions as a channel formation region.

[0088] The channel lengths of the transistors 10A_1 and 10A_2 are the distances between the source and drain regions of the transistors 10A_1 and 10A_2, respectively. In FIG. 1B, the channel length L1 of the transistor 10A_1 and the channel length L2 of the transistor 10A_2 are indicated by dashed double-headed arrows. In FIG. 1B, the distance along the semiconductor layer 108 in the region between the conductive layers 112a and 112b is indicated as the channel length L1 of the transistor 10A_1. The distance along the semiconductor layer 108 in the region between the conductive layers 112b and 112c is indicated as the channel length L2 of the transistor 10A_2.

[0089] Note that the channel length L1 of the transistor 10A_1 may be the thickness of the insulating layer 110_1 in a region sandwiched between the top surface of the conductive layer 112a and the bottom surface of the conductive layer 112b (in the case of the channel length L2 of the transistor 10A_2, the thickness of the insulating layer 110_2 in a region sandwiched between the top surface of the conductive layer 112b and the bottom surface of the conductive layer 112c). Alternatively, the channel length L1 of the transistor 10A_1 may be the thickness of the insulating layer 110b1 (in the case of the channel length L2 of the transistor 10A_2, the thickness of the insulating layer 110b2). Alternatively, the channel length L1 of the transistor 10A_1 may be the sum of the thicknesses of the insulating layer 110_1 and the conductive layer 112b (in the case of the channel length L2 of the transistor 10A_2, the sum of the thicknesses of the insulating layer 110_2 and the conductive layer 112c).

[0090] Here, the channel length L1 of the transistor 10A_1 is determined by the thickness of the insulating layer 110_1, the thickness of the conductive layer 112b, the angle (angle θ143) between the surface where the semiconductor layer 108 is to be formed in the opening 143 (here, the side surface of the insulating layer 110_1) and the surface where the insulating layer 110_1 is to be formed (here, the top surface of the conductive layer 112a), and the like, and is not affected by the performance of an exposure apparatus used to manufacture the transistor. Therefore, the channel length L1 can be set to a value smaller than the resolution limit of the exposure apparatus, thereby enabling a transistor with a micro-sized structure to be realized. The channel length L2 of the transistor 10A_2 can also be determined by replacing the insulating layer 110_1, the conductive layer 112b, and the conductive layer 112a with the insulating layer 110_2, the conductive layer 112c, and the conductive layer 112b, respectively, and the same description of the channel length L1 of the transistor 10A_1 can be applied.

[0091] The channel lengths L1 and L2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm. For example, the channel lengths L1 and L2 can be, for example, 100 nm or more and less than 1 μm. By shortening the channel length L1, the on-current of the transistor 10A_1 can be increased. By shortening the channel length L2, the on-current of the transistor 10A_2 can be increased.

[0092] The thickness of the insulating layer 110_1 and the thickness of the insulating layer 110_2 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.

[0093] The angle θ143 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less. The smaller the angle θ143, the better the coverage of the layer (such as the semiconductor layer 108) formed along the sidewall of the opening 143 can be. On the other hand, the closer the angle θ143 is to 90 degrees, the better the area occupied by the transistor on the substrate surface can be reduced.

[0094] The channel widths of the transistors 10A_1 and 10A_2 are the lengths of their source and drain regions in a plan view ( FIG. 1A ). That is, the channel width of the transistor 10A_1 is the length of the region where the semiconductor layer 108 and the conductive layer 112 a contact each other or the length of the region where the semiconductor layer 108 and the conductive layer 112 b contact each other in a plan view (in the case of the channel width of the transistor 10A_2, it is the length of the region where the semiconductor layer 108 and the conductive layer 112 b contact each other or the length of the region where the semiconductor layer 108 and the conductive layer 112 c contact each other in a plan view). Alternatively, the channel width of transistor 10A_1 may be an intermediate value between the length of the region where the semiconductor layer 108 and the conductive layer 112a are in contact in a planar view and the length of the region where the semiconductor layer 108 and the conductive layer 112b are in contact in a planar view (in the case of the channel width of transistor 10A_2, an intermediate value between the length of the region where the semiconductor layer 108 and the conductive layer 112b are in contact in a planar view and the length of the region where the semiconductor layer 108 and the conductive layer 112c are in contact in a planar view).

[0095] Here, the channel width of the transistor 10A_1 is described as the perimeter of a region where the semiconductor layer 108 and the side surface of the conductive layer 112b on the opening 143 side are in contact with each other. The channel width of the transistor 10A_2 is described as the perimeter of a region where the semiconductor layer 108 and the side surface of the conductive layer 112c on the opening 143 side are in contact with each other. In FIGS. 1A and 1B , the channel width W1 of the transistor 10A_1 and the channel width W2 of the transistor 10A_2 are each indicated by a dashed double-headed arrow. Of these, the channel width W2 of the transistor 10A_2 located in the uppermost layer can also be considered to be the perimeter of the opening 143 in a plan view. Note that when the angle θ143 is 90 degrees, the channel width W1 of the transistor 10A_1 located in the lower layer can also be considered to be the perimeter of the opening 143 in a plan view.

[0096] The channel widths W1 and W2 are determined by the top surface shape of the opening 143, etc. In FIGS. 1A and 1B, the width D143 of the opening 143 is indicated by a two-dot chain line with a double arrow. The width D143 refers to the short side of the smallest rectangle circumscribing the opening 143 in a plan view. When the opening 143 is formed using photolithography, the width D143 of the opening 143 is equal to or greater than the resolution limit of the exposure device. The width D143 is, for example, 0.20 μm or greater and less than 5.0 μm. Note that when the top surface shape of the opening 143 is circular, the width D143 corresponds to the diameter of the opening 143, and the channel width W2 (and the channel width W1 when the angle θ143 is 90 degrees) can be calculated as "D143 × π."

[0097] [Semiconductor Layer 108] The semiconductor material that can be used for the semiconductor layer 108 is not particularly limited. For example, an elemental semiconductor or a compound semiconductor can be used. As the elemental semiconductor, for example, silicon or germanium can be used. As the compound semiconductor, for example, gallium arsenide and silicon germanium can be used. As the compound semiconductor, an organic substance having semiconductor properties or a metal oxide (also referred to as an oxide semiconductor) having semiconductor properties can be used. Note that these semiconductor materials may contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0098] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0099] Silicon can be used for the semiconductor layer 108. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS).

[0100] A transistor using amorphous silicon for the semiconductor layer 108 can be formed over a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon for the semiconductor layer 108 has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for the semiconductor layer 108 has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0101] The semiconductor layer 108 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the semiconductor layer 108 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin. The element M is more preferably gallium.

[0102] The semiconductor layer 108 can be formed using, for example, indium oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO), or the like. Alternatively, indium tin oxide containing silicon can be used.

[0103] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When forming a metal oxide by sputtering, the atomic ratio of the target may differ from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc in the metal oxide may be approximately 40% to 90% of the atomic ratio of zinc contained in the target.

[0104] When the semiconductor layer 108 is formed by the ALD method, it is preferable to use a film formation method such as a thermal ALD method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it not only exhibits high step coverage but also allows low-temperature film formation.

[0105] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistors 10A_1 and 10A_2.

[0106] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized. Furthermore, by using a metal oxide that does not contain gallium or has a low content of gallium in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by using a metal oxide with a low content of element M in the semiconductor layer 108, a transistor with high reliability against application of a positive bias can be realized. Furthermore, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be realized.

[0107] The composition of the metal oxide contained in the semiconductor layer 108 will be described in detail later.

[0108] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 108. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 108, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized. Note that the CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane. In the CAAC structure, crystal grain boundaries (grains) are less clearly visible in the a-b plane than in the polycrystalline structure, and therefore a highly reliable transistor can be realized.

[0109] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 108, the more the density of defect states in the semiconductor layer 108 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0110] The semiconductor layer 108 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, the semiconductor layer 108 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, where the second metal oxide layer has a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the two or more metal oxide layers included in the semiconductor layer 108 may have different compositions.

[0111] The thickness of the semiconductor layer 108 (film thickness relative to the surface on which it is formed) is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, even more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, even more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, even more preferably 20 nm to 50 nm, even more preferably 20 nm to 40 nm, even more preferably 25 nm to 40 nm.

[0112] Here, oxygen vacancies that can be formed in the semiconductor layer 108 will be described.

[0113] When an oxide semiconductor is used for the semiconductor layer 108, hydrogen contained in the oxide semiconductor reacts with oxygen that is bonded to a metal atom to form water, and oxygen vacancies (V Ｏ Furthermore, defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V ＯH.) functions as a donor and generates electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0114] V Ｏ H can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in an oxide semiconductor, evaluation is sometimes performed using the carrier concentration rather than the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration."

[0115] From the above, when an oxide semiconductor is used for the semiconductor layer 108, V in the semiconductor layer 108 Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, impurities such as water and hydrogen are removed from the oxide semiconductor (this may be referred to as dehydration or dehydrogenation treatment), and oxygen vacancies (V Ｏ It is important to repair the Ｏ By using an oxide semiconductor in which defects such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0116] In the case where an oxide semiconductor is used for the semiconductor layer 108, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less.１７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably 1×10 −９ cm −３ It can be said that:

[0117] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, by using an OS transistor in a semiconductor device, the power consumption of the semiconductor device can be reduced.

[0118] OS transistors can be applied to display devices. To increase the light-emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since OS transistors have a higher source-drain breakdown voltage than transistors using silicon (hereinafter referred to as Si transistors), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as a driving transistor in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the light-emission luminance of the light-emitting device.

[0119] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a greater number of gray levels to be displayed in the pixel circuit.

[0120] In terms of saturation characteristics of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed through a light-emitting device, even when the current-voltage characteristics of the light-emitting device vary. In other words, when an OS transistor operates in a saturation region, the source-drain current of the OS transistor remains almost unchanged even when the source-drain voltage increases, thereby stabilizing the light-emitting luminance of the light-emitting device.

[0121] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of variations in light-emitting devices," and the like.

[0122] Furthermore, OS transistors can also be applied to, for example, a scan line driver circuit of a display device. As described above, OS transistors have significantly higher field-effect mobility than transistors using amorphous silicon. Therefore, by applying OS transistors to the scan line driver circuit of a display device, a scan line driver circuit that can operate at high speed can be realized.

[0123] Furthermore, OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0124] In the transistor of one embodiment of the present invention, and in a semiconductor device, a display device, or the like to which the transistor of one embodiment of the present invention is applied, an inorganic insulating material or an organic insulating material can be used for the insulating layer (the insulating layer 110_1, the insulating layer 110_2, and the insulating layer 106). Alternatively, the insulating layer may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0125] As the inorganic insulating material, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride can be used.

[0126] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0127] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS) can be used to analyze the oxygen and nitrogen contents. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the element contents, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0128] Furthermore, for evaluating the film density of an insulating layer or the like, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR) can be used. Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a pale (bright) transmission electron (TE) image. Even when the same material is used for the insulating layer, if the film densities are different, the boundary between these may be observed as a difference in contrast in a cross-sectional TEM image.

[0129] The nitrogen content of the insulating layer can be confirmed, for example, by energy dispersive X-ray spectrometry (EDX). For example, when silicon nitride, silicon oxynitride, or the like is used for the insulating layer, the nitrogen content can be evaluated using the ratio of the nitrogen peak height to the silicon peak height. In EDX, the peak of a certain element refers to the point at which the count number of the element reaches a maximum in a spectrum where the horizontal axis shows the energy of characteristic X-rays and the vertical axis shows the count number (detection value) of characteristic X-rays. Alternatively, the count number at the energy of characteristic X-rays specific to the element may be used to confirm the difference in nitrogen content by the ratio of the nitrogen count number to the silicon count number. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0130] The hydrogen concentration of the insulating layer can be evaluated by, for example, SIMS.

[0131] When hydrogen diffuses into the semiconductor layer 108, it reacts with oxygen atoms contained in the oxide semiconductor to form water, and oxygen vacancies (V Ｏ ) may be formed in the semiconductor layer 108. Ｏ H may be formed, which may increase the carrier concentration in the semiconductor layer 108. By using a blocking film that suppresses hydrogen diffusion as an insulating layer in contact with the semiconductor layer 108 or an insulating layer located around the semiconductor layer 108, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0132] Oxygen vacancies (V Ｏ ) and V Ｏ In particular, when the channel length is short, oxygen vacancies (V Ｏ ) and V ＯFor example, when VH flows from the source region or drain region to the channel formation region, the influence of VH on the electrical characteristics and reliability of the transistors 10A_1 and 10A_2 increases. Ｏ The diffusion of H increases the carrier concentration in the channel formation region, which may cause fluctuations in the threshold voltages of the transistors 10A_1 and 10A_2 or reduce the reliability. Ｏ The influence of the diffusion of H on the electrical characteristics and reliability of the transistors 10A_1 and 10A_2 increases as the channel length decreases. Ｏ ) and V Ｏ By reducing H, it is possible to realize a transistor with a short channel length, which has good electrical characteristics and high reliability.

[0133] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108 (for example, the insulating layer 106, the insulating layer 110b1, and the insulating layer 110b2), oxygen can be supplied from the insulating layer to the semiconductor layer 108. By supplying oxygen to the channel formation region of the semiconductor layer 108, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H can be reduced, and a highly reliable transistor can be obtained, which has favorable electrical characteristics. Note that other treatments for supplying oxygen to the semiconductor layer 108 include heat treatment in an atmosphere containing oxygen, plasma treatment in an atmosphere containing oxygen, and the like.

[0134] It is preferable that the insulating layer in contact with the semiconductor layer 108 or the insulating layer located around the semiconductor layer 108 emits less impurities (for example, water and hydrogen) from itself. Note that the impurities referred to here are impurities that diffuse into the semiconductor layer 108 and cause oxygen deficiency (V Ｏ ) and V Ｏ Impurities refer to substances that can adversely affect the electrical characteristics of a transistor by, for example, generating H. Reducing the release of impurities can suppress the diffusion of the impurities into the semiconductor layer 108, thereby enabling a transistor to exhibit favorable electrical characteristics and high reliability.

[0135] Oxygen may be desorbed from the semiconductor layer 108 due to heat applied in a process after the formation of the semiconductor layer 108. However, oxygen is supplied to the semiconductor layer 108 from an insulating layer in contact with the semiconductor layer 108, and oxygen vacancies (V Ｏ ) and V Ｏ It is possible to suppress an increase in H. Furthermore, it is possible to increase the degree of freedom in the process temperature in the steps after the formation of the semiconductor layer 108. Specifically, it is possible to increase the process temperature in the steps after the formation of the semiconductor layer 108. Therefore, it is possible to form a transistor that exhibits good electrical characteristics and is highly reliable.

[0136] [Insulating Layer 110_1 and Insulating Layer 110_2] The insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) and the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) can be formed using an inorganic insulating material or an organic insulating material. The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of an inorganic insulating material and an organic insulating material.

[0137] An inorganic insulating material can be suitably used for the insulating layer 110_1 and the insulating layer 110_2. Examples of the inorganic insulating material that can be used include one or more of oxide, oxynitride, nitride oxide, and nitride. Examples of the insulating layer 110_1 and the insulating layer 110_2 that can be used include one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride.

[0138] The insulating layer 110_1 and the insulating layer 110_2 may have a stacked structure of two or more layers. In FIG. 1B and other drawings, the insulating layer 110_1 has a stacked structure of an insulating layer 110a1, an insulating layer 110b1 on the insulating layer 110a1, and an insulating layer 110c1 on the insulating layer 110b1, and the insulating layer 110_2 has a stacked structure of an insulating layer 110a2, an insulating layer 110b2 on the insulating layer 110a2, and an insulating layer 110c2 on the insulating layer 110b2. The insulating layers 110a1, 110b1, 110c1, 110a2, 110b2, and 110c2 may be made of the same material or different materials.

[0139] The insulating layers 110_1 and 110_2 preferably release little impurities (for example, water and hydrogen) from themselves.

[0140] The insulating layers 110b1 and 110b2 can be thicker than the insulating layers 110a1 and 110a2 and the insulating layers 110c1 and 110c2. As described above, the insulating layers 110b1 and 110b2 are both insulating layers containing oxygen to be supplied to the semiconductor layer 108. Therefore, by making the insulating layers 110b1 and 110b2 thickest among the three insulating layers constituting the insulating layer 110_1 (the insulating layer 110a1, the insulating layer 110b1, and the insulating layer 110c1) and the three insulating layers constituting the insulating layer 110_2 (the insulating layer 110a2, the insulating layer 110b2, and the insulating layer 110c2), respectively, the amount of oxygen that can be contained in the entire insulating layer 110_1 and the entire insulating layer 110_2 can be increased. The deposition rate of the insulating layers 110b1 and 110b2 is preferably faster than the deposition rate of the insulating layers 110a1 and 110a2 and the deposition rate of the insulating layers 110c1 and 110c2. By increasing the deposition rate of a thick film, productivity can be improved.

[0141] The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, function as blocking films that suppress gas desorption from the insulating layers 110b1 and 110b2, respectively. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, are preferably made of materials that are difficult for gas to diffuse through. The insulating layers 110a1 and 110c1, as well as the insulating layers 110a2 and 110c2, preferably have regions with higher film density than the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layers can improve their blocking properties against gas. Slowing the film formation rate of the insulating layers increases the film density, thereby improving their blocking properties against gas.

[0142] The insulating layers 110b1 and 110b2 are preferably formed using an oxide or an oxynitride. The insulating layers 110b1 and 110b2 are preferably formed using a film that releases oxygen when heated. The insulating layers 110b1 and 110b2 are preferably formed using, for example, silicon oxide or silicon oxynitride.

[0143] The insulating layers 110b1 and 110b2 release oxygen, which allows oxygen to be supplied to the semiconductor layer 108 from the insulating layers 110b1 and 110b2. The insulating layers 110b1 and 110b2 preferably have a high oxygen diffusion coefficient. A high oxygen diffusion coefficient facilitates oxygen diffusion in the insulating layers 110b1 and 110b2, allowing oxygen to be efficiently supplied to the semiconductor layer 108. Furthermore, as described above, by configuring the insulating layers 110b1 and 110b2 to be thicker than the insulating layers 110a1 and 110c1 and the insulating layers 110a2 and 110c2, respectively, more oxygen can be supplied to the semiconductor layer 108.

[0144] The insulating layers 110_1 and 110_2 are preferably formed by a film formation method such as a sputtering method, an ALD method, or a plasma CVD method.

[0145] In particular, by using a sputtering method without using a gas containing hydrogen in the deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen supply to the semiconductor layer 108 can be suppressed, and the electrical characteristics of the transistors 10A_1 and 10A_2 can be stabilized. When silicon oxide is deposited by sputtering, it can be deposited using a silicon target in an atmosphere containing an oxygen gas, for example. When silicon nitride is deposited by sputtering, it can be deposited using a silicon target in an atmosphere containing nitrogen gas, for example. When aluminum oxide is deposited by sputtering, it can be deposited using an aluminum target in an atmosphere containing an oxidizing gas, for example.

[0146] Silicon oxide and silicon nitride can be formed by, for example, the PEALD method. Aluminum oxide and hafnium oxide can be formed by, for example, the thermal ALD method. By forming an insulating layer by the PEALD method and the thermal ALD method, a dense insulating film can be formed, and thus the blocking property against oxygen and hydrogen can be improved.

[0147] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 can be made of a material having a higher nitrogen content than the insulating layers 110b1 and 110b2, respectively. Increasing the nitrogen content of the insulating layers can improve the blocking properties against oxygen and hydrogen.

[0148] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 may each have a region with a lower hydrogen concentration than the insulating layers 110b1 and 110b2.

[0149] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to oxygen. Furthermore, the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably impermeable to hydrogen. The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 function as blocking films that suppress diffusion of hydrogen from outside the transistor to the semiconductor layer 108 via the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, respectively. The film densities of the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 are preferably higher than those of the insulating layers 110b1 and 110b2, respectively. Increasing the film density of the insulating layer can improve the blocking properties of oxygen and hydrogen. When silicon oxide or silicon oxynitride is used for the insulating layer 110b1 and the insulating layer 110b2, silicon nitride or silicon nitride oxide can be used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2, respectively. Furthermore, hafnium oxide or aluminum oxide can be suitably used for the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2.

[0150] Furthermore, the insulating layer 110a1, the insulating layer 110c1, the insulating layer 110a2, and the insulating layer 110c2 can each have a structure in which two or more materials selected from silicon nitride, silicon nitride oxide, hafnium oxide, and aluminum oxide are stacked.

[0151] If oxygen contained in the insulating layers 110b1 and 110b2 diffuses downward (toward the substrate 102) from the insulating layers 110b1 and 110b2, the amount of oxygen supplied from the insulating layers 110b1 and 110b2 to the semiconductor layer 108 may decrease. By providing the insulating layers 110a1 and 110a2 below the insulating layers 110b1 and 110b2, respectively, it is possible to prevent the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing downward from the insulating layers 110b1 and 110b2. Furthermore, by providing the insulating layers 110c1 and 110c2 above the insulating layers 110b1 and 110b2, it is possible to prevent the oxygen contained in the insulating layers 110b1 and 110b2 from diffusing upward from the insulating layers 110b1 and 110b2. Therefore, the amount of oxygen supplied from the insulating layer 110b1 and the insulating layer 110b2 to the semiconductor layer 108 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0152] Furthermore, by providing the insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2, the diffusion of hydrogen into the semiconductor layer 108 is suppressed, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0153] The insulating layers 110a1 and 110c1, and the insulating layers 110a2 and 110c2 preferably have a thickness that functions as a blocking film for oxygen and hydrogen. If the insulating layers are too thin, their function as a blocking film may be reduced. On the other hand, if the insulating layers are too thick, the region of the semiconductor layer 108 in contact with the insulating layers 110b1 and 110b2 may be narrowed, and the amount of oxygen supplied to the semiconductor layer 108 may be reduced. The thicknesses (film thicknesses with respect to the surface on which the insulating layers 110a1, 110c1, 110a2, and 110c2) are preferably 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm, respectively.

[0154] [Insulating Layer 106] The insulating layer 106, which functions as a gate insulating layer, preferably has a low defect density. A low defect density in the insulating layer 106 enables a transistor to exhibit favorable electrical characteristics. Furthermore, the insulating layer 106 preferably has a high withstand voltage. A high withstand voltage of the insulating layer 106 enables a highly reliable transistor.

[0155] The insulating layer 106 is preferably an insulating layer containing oxygen. Furthermore, the insulating layer 106 is preferably an insulating layer that releases oxygen by heating. Thus, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layer 106 can be supplied to the metal oxide. Thus, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistors 10A_1 and 10A_2.

[0156] The insulating layer 106 can be formed using, for example, one or more of an oxide, an oxynitride, a nitride oxide, and a nitride having insulating properties. The insulating layer 106 can be formed using, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide. The insulating layer 106 can be formed as a single layer or a stacked layer. The insulating layer 106 can be formed as, for example, a stacked layer structure of an oxide and a nitride.

[0157] In a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0158] The insulating layer 106 preferably releases little impurities (for example, water and hydrogen) from itself. When the insulating layer 106 releases little impurities, the impurities are prevented from diffusing into the semiconductor layer 108, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0159] Because the insulating layer 106 is formed over the semiconductor layer 108, it is preferable that the insulating layer 106 be formed under conditions that cause little damage to the semiconductor layer 108. For example, it is preferable that the insulating layer 106 be formed under conditions that cause a sufficiently slow film formation rate. For example, when the insulating layer 106 is formed by a plasma CVD method, damage to the semiconductor layer 108 can be reduced by forming the insulating layer 106 under low power conditions.

[0160] Here, the insulating layer 106 will be specifically described using an example in which the semiconductor layer 108 is made of a metal oxide.

[0161] In order to improve the interface characteristics with the semiconductor layer 108, it is preferable to use one or more of oxide and oxynitride at least on the side of the insulating layer 106 that is in contact with the semiconductor layer 108. For example, one or more of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 106. It is more preferable to use a film that releases oxygen by heating for the insulating layer 106.

[0162] Note that the insulating layer 106 may have a stacked structure. The insulating layer 106 can have a stacked structure of an oxide film or an oxynitride film on the side in contact with the semiconductor layer 108 and a nitride film on the side in contact with the conductive layer 104. As the oxide film or the oxynitride film, for example, one or more of silicon oxide and silicon oxynitride can be preferably used. As the nitride film, silicon nitride can be preferably used.

[0163] The thickness of the insulating layer 106 (thickness relative to the surface where the insulating layer 106 is formed) is preferably 1 nm to 100 nm. At least a part of the insulating layer 106 may have a region with the above thickness.

[0164] [Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 112c] The conductive layers 112a, 112b, and 112c, which function as a source electrode and a drain electrode, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above metals. For the conductive layers 112a, 112b, and 112c, a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be preferably used. Copper and aluminum are particularly preferred because of their excellent mass productivity.

[0165] The conductive layer 112a, the conductive layer 112b, and the conductive layer 112c can each be formed using a metal oxide film (also referred to as an oxide conductor). Examples of the oxide conductor (OC) include In—Sn oxide (ITO), In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Zn oxide, In—Sn—Si oxide (ITSO), and In—Ga—Zn oxide.

[0166] Here, oxide conductors (OC) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes more conductive and becomes an electric conductor. A metal oxide that has become an electric conductor can be called an oxide conductor.

[0167] The conductive layers 112a, 112b, and 112c may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0168] The conductive layer 112 a, the conductive layer 112 b, and the conductive layer 112 c may each be a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu—X alloy film, it is possible to process the film by wet etching, thereby reducing manufacturing costs.

[0169] Note that the conductive layers 112a, 112b, and 112c may be formed using the same material or different materials.

[0170] Here, the conductive layers 112a, 112b, and 112c will be specifically described using an example in which the semiconductor layer 108 is formed using a metal oxide.

[0171] When an oxide semiconductor is used for the semiconductor layer 108, the conductive layers 112a, 112b, and 112c are oxidized by oxygen contained in the semiconductor layer 108, which may increase the resistance. The conductive layers 112a, 112b, and 112c are oxidized by oxygen contained in the insulating layers 110_1 and 110_2, which may increase the resistance. Furthermore, the conductive layers 112a, 112b, and 112c are oxidized by oxygen contained in the semiconductor layer 108, which may increase the oxygen vacancy (V Ｏ When the conductive layers 112a, 112b, and 112c are oxidized by oxygen contained in the insulating layers 110_1 and 110_2, the amount of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layer 108 may decrease.

[0172] The conductive layers 112a, 112b, and 112c are preferably made of a material that is resistant to oxidation. The conductive layers 112a, 112b, and 112c are preferably made of an oxide conductor. For example, In—Sn oxide (ITO) or In—Sn—Si oxide (ITSO) can be suitably used. The conductive layers 112a, 112b, and 112c may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 112a, 112b, and 112c may each have a stacked structure of the above-mentioned materials.

[0173] By using a material that is not easily oxidized for the conductive layer 112a, the conductive layer 112b, and the conductive layer 112c, it is possible to prevent the conductive layer 112a from being oxidized by oxygen contained in the semiconductor layer 108 or oxygen contained in the insulating layer 110_1 or 110_2, which can prevent the resistance from increasing. Ｏ ) can be suppressed, and the amount of oxygen supplied from the insulating layers 110_1 and 110_2 to the semiconductor layer 108 can be increased.

[0174] [Conductive Layer 104] The conductive layer 104 functioning as a gate electrode can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above-mentioned metals. Alternatively, the conductive layer 104 may be formed using any of the materials that can be used for the conductive layers 112a, 112b, and 112c.

[0175] 1B and other drawings, the conductive layer 104 is shown as having a single-layer structure, but this is not limited thereto. For example, the conductive layer 104 may have a stacked structure of two or more layers. For example, when the conductive layer 104 has a two-layer stacked structure, a nitride or an oxide can be used as the first conductive layer (the conductive layer on the insulating layer 106 side), and a second conductive layer can be made of one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy containing one or more of the above-mentioned metals. Furthermore, for example, when the conductive layer 104 has a three-layer stacked structure, the first conductive layer (the conductive layer on the insulating layer 106 side) can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy; the second conductive layer can be an alloy containing one or more of the above-mentioned metals as components; and the third conductive layer can be an alloy containing one or more of the above-mentioned metals as components, or a nitride of the metal or the alloy.

[0176] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102. Furthermore, any of these substrates on which semiconductor elements are provided may also be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0177] A flexible substrate may be used as the substrate 102, and the semiconductor device 100A or the like may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device 100A or the like. The release layer can be used to separate a semiconductor device, after a part or all of the semiconductor device is completed thereon, from the substrate 102 and transfer it to another substrate. In this case, the semiconductor device 100A or the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0178] [Composition of Metal Oxide in Semiconductor Layer 108] The composition of the metal oxide in the semiconductor layer 108 will be described below.

[0179] The composition of the metal oxide in the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 10A_1 and the transistor 10A_2.

[0180] For example, by increasing the content of indium in the metal oxide, a transistor with a large on-state current can be realized.

[0181] When an In—Zn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or a ratio close to these, can be used.

[0182] When an In—Sn oxide is used for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, or In:Sn=10:1, or a ratio close to these values, can be used.

[0183] When an In-M-Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the semiconductor layer 108 may be formed using metal oxides in which the atomic ratios of metal elements are In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1. :6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, or metal oxides thereof having a similar structure can be used.

[0184] In addition, when the element M has a plurality of metal elements, the sum of the atomic ratios of the metal elements can be taken as the atomic ratio of the element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as the element M, the sum of the atomic ratio of gallium and the atomic ratio of tin can be taken as the atomic ratio of the element M. Furthermore, it is preferable that the atomic ratios of indium, the element M, and zinc are within the above-mentioned range.

[0185] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the number of atoms of metal elements contained in the metal oxide is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, and more preferably 70 atomic % or more and 80 atomic % or less. For example, when an In—Ga—Zn oxide is used for the semiconductor layer 108, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms be in the above-mentioned range.

[0186] In this specification and the like, the ratio of the number of indium atoms to the number of atoms of the contained metal element may be referred to as the indium content. The same applies to other metal elements.

[0187] By increasing the indium content of the metal oxide, a transistor with a large on-state current can be obtained. By applying the transistor to a transistor that requires a large on-state current, a semiconductor device with excellent electrical characteristics can be obtained.

[0188] The composition of a metal oxide can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, or quantification may be difficult, or element M may not be detected.

[0189] In this specification, a "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when an atomic ratio is described as In:M:Zn = 4:2:3 or a composition near there, this includes a case where, when the atomic ratio of indium is 4, the atomic ratio of M is 1 to 3 and the atomic ratio of zinc is 2 to 4. Furthermore, when an atomic ratio is described as In:M:Zn = 5:1:6 or a composition near there, this includes a case where, when the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 5 and less than 7. Furthermore, when an atomic ratio is described as In:M:Zn = 1:1:1 or a composition near there, this includes a case where, when the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and less than 2 and the atomic ratio of zinc is greater than 0.1 and less than 2.

[0190] Here, the reliability of a transistor will be described. One of the indicators for evaluating the reliability of a transistor is a Gate Bias Temperature (GBT) stress test, in which a transistor is held at a high temperature while an electric field is applied to the gate. Among these, a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential while the transistor is held at a high temperature is called a Positive Bias Temperature (PBTS) test, and a test in which a negative potential (negative bias) is applied to the gate while the transistor is held at a high temperature is called a Negative Bias Temperature (NBTS) test. The PBTS test and the NBTS test performed under light irradiation are called a PBTIS (Positive Bias Temperature Illumination Stress) test and an NBTIS (Negative Bias Temperature Illumination Stress) test, respectively.

[0191] In an n-channel transistor, a positive potential is applied to the gate when the transistor is turned on (a state in which current flows). Therefore, the amount of change in threshold voltage in the PBTS test is one of the important items to be noted as an index of the reliability of the transistor.

[0192] By using a metal oxide that does not contain gallium or has a low gallium content for the semiconductor layer 108, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of fluctuation in threshold voltage in a PBTS test can be obtained. Furthermore, when a metal oxide containing gallium is used, it is preferable to make the gallium content lower than the indium content. This makes it possible to realize a highly reliable transistor.

[0193] One factor that causes the threshold voltage to fluctuate in the PBTS test is carrier trapping into defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect level density, the greater the number of carriers trapped in the defect levels, resulting in significant degradation in the PBTS test. By reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer, the generation of the defect levels can be suppressed.

[0194] The following is a possible reason why using a metal oxide containing no gallium or with a low gallium content for the semiconductor layer can suppress fluctuations in threshold voltage in the PBTS test. Gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that gallium combines with excess oxygen in the gate insulating layer at the interface between the gallium-rich metal oxide and the gate insulating layer, making it easier to generate carrier (here, electron) trap sites. Therefore, when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, which is thought to cause fluctuations in threshold voltage.

[0195] More specifically, when an In—Ga—Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer 108. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, it is preferable to use a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga for the semiconductor layer 108.

[0196] For the semiconductor layer 108, a metal oxide is preferably used in which the ratio of the number of gallium atoms to the number of atoms of the contained metal element is greater than 0 atomic % and less than 50 atomic %, preferably 0.1 atomic % to 40 atomic %, more preferably 0.1 atomic % to 35 atomic %, more preferably 0.1 atomic % to 30 atomic %, more preferably 0.1 atomic % to 25 atomic %, more preferably 0.1 atomic % to 20 atomic %, more preferably 0.1 atomic % to 15 atomic %, and more preferably 0.1 atomic % to 10 atomic %. By reducing the gallium content in the semiconductor layer, a transistor with high resistance to the PBTS test can be obtained. Note that by including gallium in the metal oxide, oxygen deficiency (V) in the metal oxide can be prevented. Ｏ ) is less likely to occur.

[0197] A metal oxide that does not contain gallium may be used for the semiconductor layer 108. For example, In—Zn oxide may be used for the semiconductor layer 108. In this case, increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide can increase the field-effect mobility of the transistor. On the other hand, increasing the atomic ratio of zinc to the atomic number of metal elements contained in the metal oxide can result in a metal oxide with high crystallinity, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving reliability. Alternatively, a metal oxide that does not contain gallium or zinc, such as indium oxide, may be used for the semiconductor layer 108. Using a metal oxide that does not contain gallium can significantly reduce fluctuations in threshold voltage, particularly in a PBTS test.

[0198] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3 or a ratio close thereto can be used.

[0199] Although gallium has been described as a representative example, the present invention can also be applied to a case where the element M is used instead of gallium. For the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of the element M. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M.

[0200] A transistor having high reliability when a positive bias is applied can be obtained by using a metal oxide having a low content of the element M for the semiconductor layer 108. When the transistor is used as a transistor that is required to have high reliability when a positive bias is applied, a highly reliable semiconductor device can be obtained.

[0201] Next, the reliability of the transistor against light will be described.

[0202] Light incident on a transistor may cause fluctuations in the electrical characteristics of the transistor. In particular, it is preferable that a transistor applied to a region where light may be incident exhibits small fluctuations in electrical characteristics under light irradiation and has high reliability against light. The reliability against light can be evaluated, for example, by the amount of fluctuation in threshold voltage in an NBTIS test.

[0203] Increasing the content of the element M in the metal oxide can provide a transistor with high reliability against light. That is, a transistor with a small variation in threshold voltage in an NBTIS test can be provided. Specifically, a metal oxide in which the atomic ratio of the element M is equal to or greater than the atomic ratio of indium has a larger band gap, and can reduce the variation in threshold voltage of the transistor in an NBTIS test. The band gap of the metal oxide in the semiconductor layer 108 is preferably 2.0 eV or more, more preferably 2.5 eV or more, even more preferably 3.0 eV or more, still more preferably 3.2 eV or more, even more preferably 3.3 eV or more, still more preferably 3.4 eV or more, and even more preferably 3.5 eV or more.

[0204] For example, the semiconductor layer 108 can be made of metal oxides having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or similar ratios.

[0205] For the semiconductor layer 108, a metal oxide in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0206] When an In—Ga—Zn oxide is used for the semiconductor layer 108, a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is equal to or less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, or a ratio close to these can be used.

[0207] For the semiconductor layer 108, a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less can be suitably used.

[0208] A transistor with high reliability to light can be obtained by using a metal oxide having a high content of element M for the semiconductor layer 108. By using the transistor as a transistor that is required to have high reliability to light, a highly reliable semiconductor device can be obtained.

[0209] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0210] The semiconductor layer 108 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs.

[0211] The two or more metal oxide layers included in the semiconductor layer 108 may have different compositions. For example, a stacked structure of a first metal oxide layer having an atomic ratio of In:M:Zn=1:3:4 or a composition similar thereto and a second metal oxide layer having an atomic ratio of In:M:Zn=1:1:1 or a composition similar thereto, provided on the first metal oxide layer, can be preferably used. Furthermore, it is particularly preferable to use gallium or aluminum as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.

[0212] As described above, the semiconductor device 100A includes two transistors (transistor 10A_1 and transistor 10A_2), which share some components with each other. Specifically, the conductive layer 112b, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are shared between the two transistors. FIG. 2B is a circuit diagram illustrating the connection between the two transistors.

[0213] 2B , the other of the source or the drain of the transistor 10A_1 provided in the first layer and the other of the source or the drain of the transistor 10A_2 provided in the second layer are connected to each other and led to the outside as a single wiring (here, a conductive layer 112b). The gate of the transistor 10A_1 and the gate of the transistor 10A_2 are connected to each other and led to the outside as a single wiring (here, a conductive layer 104). The other of the source or the drain of the transistor 10A_1 is led to the outside by a wiring represented as a conductive layer 112a, and the other of the source or the drain of the transistor 10A_2 is led to the outside by a wiring represented as a conductive layer 112c.

[0214] That is, the semiconductor device 100A can be said to have a transistor 10A_1 and a transistor 10A_2 connected in series to each other.

[0215] The semiconductor device 100A can control the current path through the semiconductor device in various ways depending on the magnitude of the potential applied to four terminals of the semiconductor device (here, the conductive layer 104, the conductive layer 112a, the conductive layer 112b, and the conductive layer 112c). An example of the operation of the semiconductor device 100A will be described below.

[0216] Note that the terms "high potential" and "low potential" used in the operation examples of a semiconductor device described below refer to a relative comparison of potentials applied to the source and drain of a transistor, with the higher potential being referred to as a "high potential" and the lower potential being referred to as a "low potential." For example, when different potentials are applied to the source and drain of a transistor, the higher potential is referred to as a "high potential" and the lower potential is referred to as a "low potential." Furthermore, a "high potential" potential applied to the gate of a transistor refers to a potential that is equal to or greater than the threshold voltage and that turns the transistor on.

[0217] Note that the following description will be given using an example in which all the transistors included in the semiconductor device are n-channel transistors. However, when a p-channel transistor is used as the target, the following description can be applied by appropriately changing the magnitude of the potential applied to each electrode of the transistor (for example, by switching between "high potential" and "low potential").

[0218] 3A shows an example of current paths in the semiconductor device 100A when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, and a low potential (potential L1) is applied to the conductive layer 112b, and the conductive layer 112c is set to a floating state (potential F). In FIG. 3A, the main current paths in the semiconductor device 100A are indicated by solid arrows.

[0219] In this case, for the transistor 10A_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or drain, and a low potential (potential L1) is applied to the other of the source or drain. For the transistor 10A_2, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a low potential (potential L1) is applied to the other of the source or drain.

[0220] Here, when the potential H0 is equal to or higher than the threshold voltage of the transistor 10A_1, the transistor 10A_1 is turned on, and a current corresponding to the source-drain potential difference (potential H1-potential L1) flows between the source and drain. On the other hand, when the potential H0 is equal to or higher than the threshold voltage of the transistor 10A_2, the transistor 10A_2 is also turned on. However, since the source-drain potential difference (potential F-potential L1) is much smaller than the same potential difference (potential H1-potential L1) of the transistor 10A_1, almost no current flows between the source and drain of the transistor 10A_2. Therefore, in the semiconductor device 100A, a state equivalent to operating only the transistor 10A_1 can be achieved.

[0221] 3B shows an example of current paths in the semiconductor device 100A when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H2) is applied to the conductive layer 112c, and a low potential (potential L2) is applied to the conductive layer 112b, and the conductive layer 112a is set to a floating state (potential F). In FIG. 3B, the main current paths in the semiconductor device 100A are indicated by solid arrows.

[0222] In this case, for the transistor 10A_2, a high potential (potential H0) is applied to the gate, a low potential (potential L2) is applied to one of the source or drain, and a high potential (potential H2) is applied to the other of the source or drain. For the transistor 10A_1, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a low potential (potential L2) is applied to the other of the source or drain.

[0223] In this case, a current corresponding to the source-drain potential difference (potential H2-potential L2) flows between the source and drain of transistor 10A_2. Meanwhile, transistor 10A_1 is also turned on, but the source-drain potential difference (potential F-potential L2) is much smaller than the source-drain potential difference (potential H2-potential L2) of transistor 10A_2, so almost no current flows between the source and drain of transistor 10A_1. Therefore, in the semiconductor device 100A, a state equivalent to operating only transistor 10A_2 can be achieved.

[0224] 3C shows an example of current paths in the semiconductor device 100A when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, and a low potential (potential L2) is applied to the conductive layer 112c, and the conductive layer 112b is set to a floating state (potential F). In FIG. 3C, the main current paths in the semiconductor device 100A are indicated by solid arrows.

[0225] In this case, for the transistor 10A_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or drain, and the other of the source or drain is floating (potential F). For the transistor 10A_2, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a low potential (potential L2) is applied to the other of the source or drain.

[0226] In this case, no potential difference occurs between the other of the source or drain of transistor 10A_1 and the other of the source or drain of transistor 10A_2. Meanwhile, a potential difference of potential H1 - potential L2 occurs between the other of the source or drain of transistor 10A_1 and the other of the source or drain of transistor 10A_2. Therefore, a current corresponding to a potential of potential H1 - potential L2 flows through both transistor 10A_1 and transistor 10A_2 in the semiconductor device 100A. In other words, a state equivalent to connecting transistors 10A_1 and 10A_2 in series can be achieved.

[0227] 3D shows an example of current paths in the semiconductor device 100A when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H2) is applied to the conductive layer 112c, and a low potential (potential L1) is applied to the conductive layer 112a, and the conductive layer 112b is set to a floating state (potential F). In FIG. 3D, the main current paths in the semiconductor device 100A are indicated by solid arrows.

[0228] In this case, for the transistor 10A_1, a high potential (potential H0) is applied to the gate, a low potential (potential L1) is applied to one of the source or drain, and the other of the source or drain is floating (potential F). For the transistor 10A_2, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a high potential (potential H2) is applied to the other of the source or drain.

[0229] In this case, as in FIG. 3C , no potential difference occurs between the other of the source or drain of transistor 10A_1 and the other of the source or drain of transistor 10A_2. Meanwhile, a potential difference of potential H2 minus potential L1 occurs between the other of the source or drain of transistor 10A_1 and the other of the source or drain of transistor 10A_2. Therefore, a current corresponding to a potential of potential H2 minus potential L1 flows through both transistors 10A_1 and 10A_2 in the semiconductor device 100A. That is, as in FIG. 3C , a state equivalent to connecting transistors 10A_1 and 10A_2 in series can be achieved. However, while in FIG. 3C , current flows from transistor 10A_1 to transistor 10A_2, in FIG. 3D , current flows from transistor 10A_2 to transistor 10A_1.

[0230] 4A shows an example of a current path in the semiconductor device 100A when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, a high potential (potential H2) is applied to the conductive layer 112c, and a low potential (potential L12) is applied to the conductive layer 112b. In FIG. 4A, the current paths in the semiconductor device 100A are indicated by solid arrows.

[0231] In this case, for the transistor 10A_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or the drain, and a low potential (potential L12) is applied to the other of the source or the drain. For the transistor 10A_2, a high potential (potential H0) is applied to the gate, a low potential (potential L12) is applied to one of the source or the drain, and a high potential (potential H2) is applied to the other of the source or the drain.

[0232] In this case, a current corresponding to the source-drain potential difference (potential H1-potential L12) flows between the source and drain of transistor 10A_1, and a current corresponding to the source-drain potential difference (potential H2-potential L12) flows between the source and drain of transistor 10A_2. That is, a current having a magnitude equal to the sum of the current flowing through transistor 10A_1 and the current flowing through transistor 10A_2 is output to conductive layer 112b in semiconductor device 100A.

[0233] Here, when the potential H1 applied to one of the source or drain of transistor 10A_1 and the potential H2 applied to the other of the source or drain of transistor 10A_2 are the same potential, as shown in FIG. 4B, the two transistors can be operated with their gates, sources, and drains connected to each other, that is, the state is equivalent to operating transistor 10A_1 and transistor 10A_2 in a parallel connection.

[0234] 1A to 2A , various operation methods as described above can be realized by varying the magnitude of potentials applied to conductive layers (the conductive layers 112a, 112b, 112c, and 104) that function as source electrodes, drain electrodes, and gate electrodes of two transistors included in the semiconductor device. For example, when the semiconductor device is used in a scan line driver circuit of a display device, it is not necessary to fabricate different semiconductor devices depending on the location of the scan line driver circuit. A plurality of semiconductor devices having the same structure are provided within a plane, and by varying the operation methods of the semiconductor devices, the semiconductor device as a whole can perform the same function as the scan line driver circuit.

[0235] For example, in a portion of the scan line driver circuit where a small off-state current or an increased source-drain breakdown voltage is desired, a configuration equivalent to two transistors connected in series can be used, as shown in FIGS. 3C and 3D . Furthermore, in a portion of the scan line driver circuit where a large on-state current is desired, a configuration equivalent to two transistors connected in parallel can be used, as shown in FIGS. 4A and 4B . Furthermore, as shown in FIGS. 3A and 3B , only one of the two transistors can be operated. This allows the effective channel lengths of the transistors included in the semiconductor device to be freely switched within the same semiconductor device. For example, when a transistor with a short channel length is desired to be operated, only transistor 10A_1 or transistor 10A_2 can be operated. Furthermore, operating the transistors in a state equivalent to the aforementioned two transistors connected in series can be effectively equivalent to operating a transistor with a long channel length.

[0236] Furthermore, when the semiconductor device is used in the scanning line driver circuit of a display device, there is no need to manufacture different semiconductor devices depending on the location of the scanning line driver circuit. Therefore, the number of masks required for manufacturing and the number of manufacturing steps can be significantly reduced compared to the case where different semiconductor devices are manufactured.

[0237] <Configuration Example 2 of Semiconductor Device> Figures 5A to 6B show a configuration example of a semiconductor device 100B having a different configuration from the semiconductor device 100A shown in Figures 1A to 2B. Figure 5A is a plan view of the semiconductor device 100B. Figure 5B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100B shown in Figure 5A. Figure 6A is a cross-sectional view corresponding to the dashed dotted line B1-B2 in the plan view of the semiconductor device 100B shown in Figure 5A. Figure 6B is a circuit diagram illustrating the configuration of the semiconductor device 100B.

[0238] In the following, differences from the semiconductor device 100A described above will be mainly described, and descriptions of parts that overlap with the semiconductor device 100A may be omitted.

[0239] The semiconductor device 100B includes a transistor 10B_1, a transistor 10B_2, and insulating layers 110_1 and 110_2. The transistor 10B_1 corresponds to the transistor 10A_1 in the semiconductor device 100A. The transistor 10B_2 corresponds to the transistor 10A_2 in the semiconductor device 100A. The semiconductor device 100B differs from the semiconductor device 100A in the configuration of the conductive layer 112b.

[0240] Specifically, in the semiconductor device 100A, as shown in FIGS. 1A and 1B, the conductive layer 112b extends toward the A1 side of the dashed-dotted line A1-A2. In contrast, in the semiconductor device 100B, as shown in FIGS. 5A to 6A, the conductive layer 112b does not extend in either the A1 or A2 direction of the dashed-dotted line A1-A2 or the B1 or B2 direction of the dashed-dotted line B1-B2, but is provided in an island shape. That is, in the semiconductor device 100B, unlike the conductive layers 112a, 112c, and 104, the conductive layer 112b does not function as a wiring for connecting to an external terminal (not shown). That is, in the semiconductor device 100B, the conductive layer 112b is always in a floating state, and unlike the semiconductor device 100A, a potential cannot be applied to the conductive layer 112b from the outside.

[0241] FIG. 6B is a circuit diagram illustrating the connection relationship between the transistor 10B_1 and the transistor 10B_2 included in the semiconductor device 100B.

[0242] 6B , in the semiconductor device 100B, unlike the semiconductor device 100A, the conductive layer 112b is not extended to the outside, and the other of the source or the drain of the transistor 10B_1 is connected to the one of the source or the drain of the transistor 10B_2 via the conductive layer 112b. The semiconductor device 100B has the same configuration as the semiconductor device 100A except for the above. Therefore, it can be said that the semiconductor device 100B has the transistor 10B_1 and the transistor 10B_2 connected in series.

[0243] As shown in Figures 3C and 3D, the semiconductor device 100A can also achieve a state equivalent to two transistors connected in series by applying potentials to the electrodes of the two transistors constituting the semiconductor device. However, because the conductive layer 112b, which is externally connected, is in an unstable floating state, there is a concern that a small amount of current may flow toward the conductive layer 112b in some cases. In contrast, in the semiconductor device 100B, because the conductive layer 112b is not externally connected, the path of current flowing through the semiconductor device 100B is limited to between the conductive layer 112a and the conductive layer 112c. Therefore, the configuration of the semiconductor device 100A can achieve more stable operation than when operating equivalent to two transistors connected in series.

[0244] An example of the operation of the semiconductor device 100B will be described with reference to FIGS. 7A and 7B.

[0245] 7A shows an example of a current path in the semiconductor device 100B when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, and a low potential (potential L2) is applied to the conductive layer 112c. In FIG. 7A, the current path in the semiconductor device 100B is indicated by solid arrows.

[0246] In this case, a high potential (potential H0) is applied to the gate of the transistor 10B_1, and a high potential (potential H1) is applied to one of the source and the drain of the transistor 10B_1. A high potential (potential H0) is applied to the gate of the transistor 10B_2, and a low potential (potential L2) is applied to the other of the source and the drain of the transistor 10B_1. The other of the source and the drain of the transistor 10B_2 is connected to the other of the source and the drain of the transistor 10B_2 via a conductive layer 112b.

[0247] In this case, both the transistor 10B_1 and the transistor 10B_2 are turned on, and a potential difference of H1-L2 occurs between the source or drain of the transistor 10B_1 and the source or drain of the transistor 10B_2. Therefore, a current corresponding to a potential of H1-L2 flows through both the transistor 10B_1 and the transistor 10B_2 in the semiconductor device 100B.

[0248] 7B shows an example of a current path in the semiconductor device 100B when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H2) is applied to the conductive layer 112c, and a low potential (potential L1) is applied to the conductive layer 112a. In FIG. 7B, the current paths in the semiconductor device 100B are indicated by solid arrows.

[0249] In this case, a high potential (potential H0) is applied to the gate of the transistor 10B_1, and a low potential (potential L1) is applied to one of the source and drain of the transistor 10B_1. A high potential (potential H0) is applied to the gate of the transistor 10B_2, and a high potential (potential H2) is applied to the other of the source and drain of the transistor 10B_1. The other of the source and drain of the transistor 10B_1 is connected to the other of the source and drain of the transistor 10B_2 via a conductive layer 112b.

[0250] In this case, a current corresponding to a potential of potential H2-potential L1 flows through both transistors 10B_1 and 10B_2 in the semiconductor device 100B, as in Fig. 7A. However, while the current flows from transistor 10B_1 to transistor 10B_2 in Fig. 7A, the current flows from transistor 10B_2 to transistor 10B_1 in Fig. 7B.

[0251] With respect to the semiconductor device 100B, the contents described for the semiconductor device 100A can be referred to for other aspects than those described above.

[0252] <Configuration Example 3 of Semiconductor Device> Figures 8A to 10 show a configuration example of a semiconductor device 100C having a different configuration from the semiconductor device 100A shown in Figures 1A to 2B. Figure 8A is a plan view of the semiconductor device 100C. Figure 8B is a cross-sectional view corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100C shown in Figure 8A. Figure 9 is a cross-sectional view corresponding to the dashed dotted line B1-B2 in the plan view of the semiconductor device 100C shown in Figure 8A. Figure 10 is a circuit diagram illustrating the configuration of the semiconductor device 100C.

[0253] The semiconductor device 100C includes a transistor 10C_1, a transistor 10C_2, a transistor 10C_3, a transistor 10C_4, an insulating layer 110_1, an insulating layer 110_2, an insulating layer 110_3 (insulating layer 110a3, insulating layer 110b3, and insulating layer 110c3), and an insulating layer 110_4 (insulating layer 110a4, insulating layer 110b4, and insulating layer 110c4). The semiconductor device 100C differs from the semiconductor device 100A in that the number of stacked vertical transistors that share some components is four.

[0254] In the semiconductor device 100C, a transistor 10C_1, a transistor 10C_2, a transistor 10C_3, and a transistor 10C_4 share some components and are provided overlapping in this order.

[0255] The transistor 10C_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The transistor 10C_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112b, and a conductive layer 112c. The transistor 10C_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112c, and a conductive layer 112d. The transistor 10C_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112d, and a conductive layer 112e.

[0256] In the transistor 10C_1, part of the conductive layer 104 functions as a gate electrode. Part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode. The conductive layer 112b functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108, the entire region that faces the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, in the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0257] In the transistor 10C_2, part of the conductive layer 104 (part other than that of the transistor 10C_1) functions as a gate electrode. Part of the insulating layer 106 (part other than that of the transistor 10C_1) functions as a gate insulating layer. The conductive layer 112b functions as one of a source electrode and a drain electrode. The conductive layer 112c functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108, the entire region that faces the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, in the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0258] In the transistor 10C_3, part of the conductive layer 104 (part other than the transistors 10C_1 and 10C_2) functions as a gate electrode. Part of the insulating layer 106 (part other than the transistors 10C_1 and 10C_2) functions as a gate insulating layer. The conductive layer 112c functions as one of a source electrode and a drain electrode. The conductive layer 112d functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108, the entire region that faces the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, in the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0259] In the transistor 10C_4, part of the conductive layer 104 (part other than the transistors 10C_1, 10C_2, and 10C_3) functions as a gate electrode. Part of the insulating layer 106 (part other than the transistors 10C_1, 10C_2, and 10C_3) functions as a gate insulating layer. The conductive layer 112d functions as one of a source electrode and a drain electrode. The conductive layer 112e functions as the other of the source electrode and the drain electrode. In the semiconductor layer 108, the entire region that faces the gate electrode with the gate insulating layer interposed therebetween functions as a channel formation region. In addition, in the semiconductor layer 108, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region.

[0260] That is, in the semiconductor device 100C, the conductive layer 112b functions as the other of the source and drain electrodes of the transistor 10C_1 and also functions as one of the source and drain electrodes of the transistor 10C_2. The conductive layer 112c functions as the other of the source and drain electrodes of the transistor 10C_2 and also functions as one of the source and drain electrodes of the transistor 10C_3. The conductive layer 112d functions as the other of the source and drain electrodes of the transistor 10C_3 and also functions as one of the source and drain electrodes of the transistor 10C_4. The semiconductor layer 108 functions as a semiconductor layer having channel formation regions of the transistors 10C_1 to 10C_4. The insulating layer 106 functions as a gate insulating layer of the transistors 10C_1 to 10C_4. The conductive layer 104 functions as a gate electrode of the transistors 10C_1 to 10C_4.

[0261] The insulating layer 110_1 is provided to have a region sandwiched between the source electrode and drain electrode of the transistor 10C_1. The insulating layer 110_2 is provided to have a region sandwiched between the source electrode and drain electrode of the transistor 10C_2. The insulating layer 110_3 is provided to have a region sandwiched between the source electrode and drain electrode of the transistor 10C_3. The insulating layer 110_4 is provided to have a region sandwiched between the source electrode and drain electrode of the transistor 10C_4.

[0262] Of the insulating layers constituting the insulating layer 110_3 and the insulating layer 110_4, the insulating layer 110a3, the insulating layer 110a4, the insulating layer 110c3, and the insulating layer 110c4 can refer to the descriptions of the insulating layer 110a1, the insulating layer 110a2, the insulating layer 110c1, and the insulating layer 110c2. Of the insulating layers constituting the insulating layer 110_3 and the insulating layer 110_4, the insulating layer 110b3 and the insulating layer 110b4 can refer to the descriptions of the insulating layer 110b1 and the insulating layer 110b2.

[0263] The conductive layer 112a, the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, the conductive layer 112c, the insulating layer 110_3, the conductive layer 112d, the insulating layer 110_4, and the conductive layer 112e have overlapping regions. In FIGS. 8A and 8B , the conductive layer 112a extends to the A2 side of the dashed-dotted line A1-A2. The conductive layer 112b extends to the A1 side of the dashed-dotted line A1-A2. The conductive layer 112c extends to the A2 side of the dashed-dotted line A1-A2. The conductive layer 112d extends to the A1 side of the dashed-dotted line A1-A2. The conductive layer 112e extends to the A2 side of the dashed-dotted line A1-A2.

[0264] The insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, the conductive layer 112c, the insulating layer 110_3, the conductive layer 112d, the insulating layer 110_4, and the conductive layer 112e have openings 144 that reach the conductive layer 112a.

[0265] The semiconductor layer 108 is provided in contact with the top surface of the conductive layer 112a in the opening 144, the side surface of the insulating layer 110_1 in the opening 144, the side surface of the conductive layer 112b in the opening 144, the side surface of the insulating layer 110_2 in the opening 144, the side surface of the conductive layer 112c in the opening 144, the side surface of the insulating layer 110_3 in the opening 144, the side surface of the conductive layer 112d in the opening 144, the side surface of the insulating layer 110_4 in the opening 144, the side surface of the conductive layer 112e in the opening 144, and the top surface of the conductive layer 112e.

[0266] The insulating layer 106 is provided over the semiconductor layer 108. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112e, and the top surface of the insulating layer 110c4.

[0267] A conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 is provided so as to have a region that overlaps with the opening 144 in a plan view. 8A and 9 show a configuration in which the conductive layer 104 extends to the B2 side of the dashed dotted line B1-B2. The conductive layer 104 has a shape that conforms to the shapes of the semiconductor layer 108 and the insulating layer 106 within the opening 144. That is, the conductive layer 104 has a recess on its upper surface that corresponds to the shape of the opening 144. The conductive layer 104 has a region that faces the semiconductor layer 108 within the opening 144, with the insulating layer 106 interposed therebetween.

[0268] The channel lengths and channel widths of the transistors 10C_1 to 10C_4 can be referred to in the descriptions of the transistors 10A_1 and 10A_2. In Figure 8B, the channel length L1 of the transistor 10C_1, the channel length L2 of the transistor 10C_2, the channel length L3 of the transistor 10C_3, and the channel length L4 of the transistor 10C_4 are indicated by double-headed dashed arrows. In Figures 8A and 8B, the channel width W1 of the transistor 10C_1, the channel width W2 of the transistor 10C_2, the channel width W3 of the transistor 10C_3, and the channel width W4 of the transistor 10C_4 are indicated by double-headed dashed arrows. In Figures 8A and 8B, the width D144 of the opening 144 is indicated by a double-headed dashed arrow. In addition, in Figure 8B, the angle between the formation surface of the semiconductor layer 108 within the opening 144 (here, the side surface of the insulating layer 110_1) and the formation surface of the insulating layer 110_1 (here, the top surface of the conductive layer 112a) is shown as angle θ144.

[0269] As described above, the semiconductor device 100C includes four transistors (transistors 10C_1 to 10C_4), which share some components with one another. Specifically, the conductive layer 112b, the conductive layer 112c, and the conductive layer 112d are each shared by two of the four transistors, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are shared by the four transistors. FIG. 10 is a circuit diagram illustrating the connections between the four transistors.

[0270] 10 , the other of the source or drain of the transistor 10C_1 provided in the first layer and one of the source or drain of the transistor 10C_2 provided in the second layer are connected to each other and led to the outside as a single wiring (here, a conductive layer 112b). The other of the source or drain of the transistor 10C_2 provided in the second layer and one of the source or drain of the transistor 10C_3 provided in the third layer are connected to each other and led to the outside as a single wiring (here, a conductive layer 112c). The other of the source or drain of the transistor 10C_3 provided in the third layer are connected to each other and led to the outside as a single wiring (here, a conductive layer 112d). The gates of the transistors 10C_1 to 10C_4 are connected to each other and led to the outside as a single wiring (here, a conductive layer 104). One of the source and the drain of the transistor 10C_1 is led to the outside by a wiring represented as a conductive layer 112a, and the other of the source and the drain of the transistor 10C_4 is led to the outside by a wiring represented as a conductive layer 112e.

[0271] That is, the semiconductor device 100C includes transistors 10C_1 to 10C_4 connected in series.

[0272] The semiconductor device 100C can control the current path through the semiconductor device in various ways depending on the magnitude of the potential applied to six terminals of the semiconductor device (here, the conductive layer 104, the conductive layer 112a, the conductive layer 112b, the conductive layer 112c, the conductive layer 112d, and the conductive layer 112e). An example of the operation of the semiconductor device 100C will be described below.

[0273] 11A shows an example of current paths in a semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, and a low potential (potential L1) is applied to the conductive layer 112b, and the conductive layers 112c, 112d, and 112e are floating (potential F). In FIG. 11A, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0274] In this case, for the transistor 10C_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or the drain, and a low potential (potential L1) is applied to the other of the source or the drain. For the transistor 10C_2, a high potential (potential H0) is applied to the gate, a low potential (potential L1) is applied to one of the source or the drain, and the other of the source or the drain is floating (potential F). For the transistor 10C_3, a high potential (potential H0) is applied to the gate, and both the source and the drain are floating (potential F). For the transistor 10C_4, a high potential (potential H0) is applied to the gate, and both the source and the drain are floating (potential F).

[0275] In this case, the transistor 10C_1 is turned on, and a current corresponding to the source-drain potential difference (potential H1-potential L1) flows between the source and drain. Meanwhile, the transistors 10C_2, 10C_3, and 10C_4 are also turned on. However, since the source-drain potential difference of each transistor is much smaller than the same potential difference of the transistor 10C_1 (potential H1-potential L1), almost no current flows between the source and drain of the three transistors. Therefore, the semiconductor device 100C can be brought into a state substantially equivalent to operating only the transistor 10C_1.

[0276] 11B shows an example of current paths in the semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H2) is applied to the conductive layer 112c, and a low potential (potential L2) is applied to the conductive layer 112b, and the conductive layers 112a, 112d, and 112e are set to a floating state (potential F). In FIG. 11B, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0277] In this case, for the transistor 10C_2, a high potential (potential H0) is applied to the gate, a low potential (potential L2) is applied to one of the source or drain, and a high potential (potential H2) is applied to the other of the source or drain. For the transistor 10C_1, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a low potential (potential L2) is applied to the other of the source or drain. For the transistor 10C_3, a high potential (potential H0) is applied to the gate, one of the source or drain is high potential (potential H2), and the other of the source or drain is floating (potential F). For the transistor 10C_4, a high potential (potential H0) is applied to the gate, and both the source and drain are floating (potential F).

[0278] In this case, a current corresponding to the source-drain potential difference (potential H2-potential L2) flows between the source and drain of the transistor 10C_2. Meanwhile, the transistors 10C_1, 10C_3, and 10C_4 are also turned on, but because the source-drain potential difference of each transistor is much smaller than the same potential difference (potential H2-potential L2) of the transistor 10C_2, almost no current flows between the source and drain of the three transistors. Therefore, the semiconductor device 100C can be brought into a state substantially equivalent to operating only the transistor 10C_2.

[0279] 12A shows an example of current paths in the semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H3) is applied to the conductive layer 112c, and a low potential (potential L3) is applied to the conductive layer 112d, and the conductive layers 112a, 112b, and 112e are floating (potential F). In FIG. 12A, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0280] In this case, for the transistor 10C_3, a high potential (potential H0) is applied to the gate, a high potential (potential H3) is applied to one of the source or drain, and a low potential (potential L3) is applied to the other of the source or drain. For the transistor 10C_1, a high potential (potential H0) is applied to the gate, and both the source and the drain are floating (potential F). For the transistor 10C_2, a high potential (potential H0) is applied to the gate, one of the source or the drain is floating (potential F), and a high potential (potential H3) is applied to the other of the source or the drain. For the transistor 10C_4, a high potential (potential H0) is applied to the gate, a low potential (potential L3) is applied to one of the source or the drain, and the other of the source or the drain is floating (potential F).

[0281] In this case, a current corresponding to the source-drain potential difference (potential H3-potential L3) flows between the source and drain of transistor 10C_3. Meanwhile, transistors 10C_1, 10C_2, and 10C_4 are also turned on, but because the source-drain potential difference of each transistor is much smaller than the same potential difference (potential H3-potential L3) of transistor 10C_3, almost no current flows between the source and drain of these three transistors. Therefore, in the semiconductor device 100C, a state equivalent to operating only transistor 10C_3 can be achieved.

[0282] 12B shows an example of current paths in the semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H4) is applied to the conductive layer 112e, and a low potential (potential L4) is applied to the conductive layer 112d, and the conductive layers 112a, 112b, and 112c are set to a floating state (potential F). In FIG. 12B, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0283] In this case, for the transistor 10C_4, a high potential (potential H0) is applied to the gate, a low potential (potential L4) is applied to one of the source or drain, and a high potential (potential H4) is applied to the other of the source or drain. For the transistors 10C_1 and 10C_2, a high potential (potential H0) is applied to the gate, and both the source and the drain are floating (potential F). For the transistor 10C_3, a high potential (potential H0) is applied to the gate, one of the source or the drain is floating (potential F), and a low potential (potential L4) is applied to the other of the source or the drain.

[0284] In this case, a current corresponding to the source-drain potential difference (potential H4-potential L4) flows between the source and drain of transistor 10C_4. Meanwhile, transistors 10C_1, 10C_2, and 10C_3 are also turned on, but because the source-drain potential difference of each transistor is much smaller than the same potential difference (potential H4-potential L4) of transistor 10C_4, almost no current flows between the source and drain of these three transistors. Therefore, in the semiconductor device 100C, a state equivalent to operating only transistor 10C_4 can be achieved.

[0285] 13A shows an example of current paths in the semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, and a low potential (potential L2) is applied to the conductive layer 112c, and the conductive layers 112b, 112d, and 112e are floating (potential F). In FIG. 13A, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0286] In this case, for the transistor 10C_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or drain, and the other of the source or drain is floating (potential F). For the transistor 10C_2, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a low potential (potential L2) is applied to the other of the source or drain. For the transistor 10C_3, a high potential (potential H0) is applied to the gate, a low potential (potential L2) is applied to one of the source or drain, and the other of the source or drain is floating (potential F). For the transistor 10C_4, a high potential (potential H0) is applied to the gate, and both the source and drain are floating (potential F).

[0287] In this case, no potential difference occurs between the other of the source or drain of transistor 10C_1 and the one of the source or drain of transistor 10C_2. Meanwhile, a potential difference of potential H1 - potential L2 occurs between the one of the source or drain of transistor 10C_1 and the other of the source or drain of transistor 10C_2. The potential differences between the other of the source or drain of transistor 10C_2 and the source and drain of transistor 10C_3 and the source and drain of transistor 10C_4 are much smaller than the potential difference of potential H1 - potential L2. Therefore, a current corresponding to a potential of potential H1 - potential L2 flows through both transistor 10C_1 and transistor 10C_2 in the semiconductor device 100C. That is, a state equivalent to connecting transistors 10C_1 and 10C_2 in series can be achieved.

[0288] 13B shows an example of current paths in the semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, and a low potential (potential L3) is applied to the conductive layer 112d, and the conductive layers 112b, 112c, and 112e are floating (potential F). In FIG. 13B, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0289] In this case, for the transistor 10C_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or drain, and the other of the source or drain is floating (potential F). For the transistor 10C_2, a high potential (potential H0) is applied to the gate, and both the source and the drain are floating (potential F). For the transistor 10C_3, a high potential (potential H0) is applied to the gate, one of the source or the drain is floating (potential F), and a low potential (potential L3) is applied to the other of the source or the drain. For the transistor 10C_4, a high potential (potential H0) is applied to the gate, a low potential (potential L3) is applied to one of the source or the drain, and the other of the source or the drain is floating (potential F).

[0290] In this case, no potential difference occurs between the other of the source or drain of transistor 10C_1 and one of the source or drain of transistor 10C_2. Also, no potential difference occurs between the other of the source or drain of transistor 10C_2 and one of the source or drain of transistor 10C_3. Meanwhile, a potential difference of potential H1 minus potential L3 occurs between the one of the source or drain of transistor 10C_1 and the other of the source or drain of transistor 10C_3. The potential difference between the other of the source or drain of transistor 10C_3 and the other of the source or drain of transistor 10C_4 is much smaller than the potential difference of potential H1 minus potential L3. Therefore, a current corresponding to a potential of potential H1 minus potential L3 flows through transistors 10C_1, 10C_2, and 10C_3 in the semiconductor device 100C. That is, a state equivalent to connecting the transistors 10C_1 to 10C_3 in series can be achieved.

[0291] 14A shows an example of current paths in the semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H1) is applied to the conductive layer 112a, and a low potential (potential L4) is applied to the conductive layer 112e, and the conductive layers 112b, 112c, and 112d are set to a floating state (potential F). In FIG. 14A, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0292] In this case, for the transistor 10C_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or drain, and the other of the source or drain is floating (potential F). For the transistors 10C_2 and 10C_3, a high potential (potential H0) is applied to the gate, and both the source and the drain are floating (potential F). For the transistor 10C_4, a high potential (potential H0) is applied to the gate, one of the source or the drain is floating (potential F), and a low potential (potential L4) is applied to the other of the source or the drain.

[0293] In this case, no potential difference occurs between the other of the source or drain of transistor 10C_1 and one of the source or drain of transistor 10C_2. Furthermore, no potential difference occurs between the other of the source or drain of transistor 10C_2 and one of the source or drain of transistor 10C_3. Furthermore, no potential difference occurs between the other of the source or drain of transistor 10C_3 and one of the source or drain of transistor 10C_4. Meanwhile, a potential difference of potential H1 minus potential L4 occurs between one of the source or drain of transistor 10C_1 and the other of the source or drain of transistor 10C_4. Therefore, a current corresponding to a potential of potential H1 minus potential L4 flows through the semiconductor device 100C via the transistors 10C_1 to 10C_4. That is, a state equivalent to connecting the transistors 10C_1 to 10C_4 in series can be achieved.

[0294] 14B shows an example of current paths in the semiconductor device 100C when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H2) is applied to the conductive layer 112b, and a low potential (potential L3) is applied to the conductive layer 112d, and the conductive layers 112a, 112c, and 112e are set to a floating state (potential F). In FIG. 14B, the main current paths in the semiconductor device 100C are indicated by solid arrows.

[0295] In this case, for the transistor 10C_2, a high potential (potential H0) is applied to the gate, a high potential (potential H2) is applied to one of the source or drain, and the other of the source or drain is floating (potential F). For the transistor 10C_3, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a low potential (potential L3) is applied to the other of the source or drain. For the transistor 10C_1, a high potential (potential H0) is applied to the gate, one of the source or drain is floating (potential F), and a high potential (potential H2) is applied to the other of the source or drain. For the transistor 10C_4, a high potential (potential H0) is applied to the gate, a low potential (potential L3) is applied to one of the source or drain, and the other of the source or drain is floating (potential F).

[0296] In this case, no potential difference occurs between the other of the source or drain of transistor 10C_2 and the other of the source or drain of transistor 10C_3. Meanwhile, a potential difference of potential H2 minus potential L3 occurs between the other of the source or drain of transistor 10C_2 and the other of the source or drain of transistor 10C_3. The potential difference between the one of the source or drain of transistor 10C_1 and the one of the source or drain of transistor 10C_2, and the potential difference between the other of the source or drain of transistor 10C_3 and the other of the source or drain of transistor 10C_4 are significantly smaller than the potential difference of potential H2 minus potential L3. Therefore, a current corresponding to a potential of potential H2 minus potential L3 flows through both transistors 10C_2 and 10C_3 in the semiconductor device 100C. That is, a state equivalent to connecting transistors 10C_2 and 10C_3 in series can be achieved.

[0297] 15 shows an example of current paths in semiconductor device 100C when a high potential (potential H0) is applied to conductive layer 104, a high potential (potential H1) to conductive layer 112a, a high potential (potential H23) to conductive layer 112c, and a high potential (potential H4) to conductive layer 112e, and a low potential (potential L12) to conductive layer 112b and a low potential (potential L34) to conductive layer 112d. In FIG. 15, the current paths in semiconductor device 100C are indicated by solid arrows.

[0298] In this case, for the transistor 10C_1, a high potential (potential H0) is applied to the gate, a high potential (potential H1) is applied to one of the source or the drain, and a low potential (potential L12) is applied to the other of the source or the drain. For the transistor 10C_2, a high potential (potential H0) is applied to the gate, a low potential (potential L12) is applied to one of the source or the drain, and a high potential (potential H23) is applied to the other of the source or the drain. For the transistor 10C_3, a high potential (potential H0) is applied to the gate, a high potential (potential H23) is applied to one of the source or the drain, and a low potential (potential L34) is applied to the other of the source or the drain. For the transistor 10C_4, a high potential (potential H0) is applied to the gate, a low potential (potential L34) is applied to one of the source or the drain, and a high potential (potential H4) is applied to the other of the source or the drain.

[0299] In this case, a current corresponding to the source-drain potential difference (potential H1 - potential L12) flows between the source and drain of transistor 10C_1, and a current corresponding to the source-drain potential difference (potential H23 - potential L12) flows between the source and drain of transistor 10C_2. Therefore, a current having a magnitude equal to the sum of the currents flowing through transistors 10C_1 and 10C_2 is output to conductive layer 112b. Furthermore, a current corresponding to the source-drain potential difference (potential H23 - potential L34) flows between the source and drain of transistor 10C_3, and a current corresponding to the source-drain potential difference (potential H4 - potential L34) flows between the source and drain of transistor 10C_4. Therefore, a current having a magnitude equal to the sum of the currents flowing through transistors 10C_3 and 10C_4 is output to conductive layer 112d. Therefore, the semiconductor device 100C as a whole outputs a current equal to the sum of the current output to the conductive layer 112b and the current output to the conductive layer 112d.

[0300] Here, when the potentials H1, H23, and H4 are the same in magnitude and the potentials L12 and L34 are the same in magnitude, the four transistors can be operated with their gates, sources, and drains connected to each other, as shown in Figure 16, which is equivalent to operating transistors 10C_1 to 10C_4 in a parallel connection.

[0301] 8A to 10 , various operation methods as described above can be realized by varying the magnitude of potentials applied to conductive layers (the conductive layers 112a, 112b, 112c, 112d, 112e, and 104) that function as source electrodes, drain electrodes, and gate electrodes of four transistors included in the semiconductor device. For example, when the semiconductor device is used in a scan line driver circuit of a display device, it is not necessary to fabricate different semiconductor devices depending on the location of the scan line driver circuit. A plurality of semiconductor devices having the same structure are provided within a plane, and the semiconductor devices can be operated in different ways to achieve the same function as the scan line driver circuit as a whole.

[0302] By increasing the number of stacked vertical transistors that share some components to four, as in the semiconductor device 100C, the number of types of operation of the semiconductor device can be increased compared to the semiconductor device 100A. Furthermore, the number of series-connected or parallel-connected transistors in the semiconductor device 100C can be increased compared to the semiconductor device 100A. Therefore, the semiconductor device 100C can have a larger on-current than the semiconductor device 100A. Furthermore, the semiconductor device 100C can have a smaller off-current than the semiconductor device 100A.

[0303] Although the semiconductor device 100A has two vertical transistors and the semiconductor device 100C has four vertical transistors, the present invention is not limited to these. The semiconductor device of one embodiment of the present invention may have three vertical transistors or may have five or more vertical transistors. As described above, the semiconductor device of one embodiment of the present invention has a structure in which multiple vertical transistors are stacked. Therefore, even if the number of vertical transistors increases, the area occupied by the transistors in a plan view does not increase, which is preferable.

[0304] With respect to the semiconductor device 100C, the contents described for the semiconductor device 100A can be referred to for other aspects than those described above.

[0305] <Configuration Example 4 of Semiconductor Device> Figures 17A to 19 show a configuration example of a semiconductor device 100D having a different configuration from the semiconductor device 100C shown in Figures 8A to 10. Figure 17A is a plan view of the semiconductor device 100D. Figure 17B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in the plan view of the semiconductor device 100D shown in Figure 17A. Figure 18 is a cross-sectional view corresponding to the dashed-dotted line B1-B2 in the plan view of the semiconductor device 100D shown in Figure 17A. Figure 19 is a circuit diagram illustrating the configuration of the semiconductor device 100D.

[0306] In the following, differences from the semiconductor device 100C described above will be mainly described, and descriptions of parts that overlap with the semiconductor device 100C may be omitted.

[0307] The semiconductor device 100D includes transistors 10D_1, 10D_2, 10D_3, and 10D_4, and insulating layers 110_1, 110_2, 110_3, and 110_4. The transistor 10D_1 corresponds to the transistor 10C_1 in the semiconductor device 100C. The transistor 10D_2 corresponds to the transistor 10C_2 in the semiconductor device 100C. The transistor 10D_3 corresponds to the transistor 10C_3 in the semiconductor device 100C. The transistor 10D_4 corresponds to the transistor 10C_4 in the semiconductor device 100C. The semiconductor device 100D differs from the semiconductor device 100C in the configurations of the conductive layers 112b, 112c, and 112d.

[0308] Specifically, in the semiconductor device 100C, as shown in FIGS. 8A and 8B , the conductive layers 112b and 112d extend toward the A1 side of the dashed-dotted line A1-A2. The conductive layer 112c extends toward the A2 side of the dashed-dotted line A1-A2. In contrast, in the semiconductor device 100D, as shown in FIGS. 17A to 18 , the conductive layers 112b, 112c, and 112d do not extend in either the A1 or A2 direction of the dashed-dotted line A1-A2 or the B1 or B2 direction of the dashed-dotted line B1-B2, but are arranged in an island shape. That is, in the semiconductor device 100D, unlike the conductive layers 112a, 112e, and 104, the conductive layers 112b, 112c, and 112d do not function as wiring for connecting to an external terminal (not shown). That is, in the semiconductor device 100D, the conductive layers 112b, 112c, and 112d are always in a floating state, and a potential cannot be applied from the outside, as in the semiconductor device 100C.

[0309] FIG. 19 is a circuit diagram illustrating the connections of the transistors 10D_1 to 10D_4 included in the semiconductor device 100D.

[0310] 19 , in the semiconductor device 100D, the conductive layers 112b, 112c, and 112d are not led out, unlike in the semiconductor device 100C. The other of the source or the drain of the transistor 10D_1 is connected to one of the source or the drain of the transistor 10D_2 through the conductive layer 112b. The other of the source or the drain of the transistor 10D_2 is connected to one of the source or the drain of the transistor 10D_3 through the conductive layer 112c. The other of the source or the drain of the transistor 10D_3 is connected to one of the source or the drain of the transistor 10D_4 through the conductive layer 112d. The semiconductor device 100D has the same configuration as the semiconductor device 100C except for the above. Therefore, it can be said that the semiconductor device 100D has the transistors 10D_1 to 10D_4 connected in series.

[0311] As shown in FIG. 14A , the semiconductor device 100C can also achieve a state equivalent to a state in which four transistors are connected in series by applying potentials to the electrodes of the four transistors constituting the semiconductor device. However, because the conductive layers 112b, 112c, and 112d, which are externally connected, are in an unstable floating state, there is a concern that a small amount of current may flow to the conductive layers 112b, 112c, and 112d. In contrast, in the semiconductor device 100D, the conductive layers 112b, 112c, and 112d are not externally connected, so the path of current flowing through the semiconductor device 100D is limited to between the conductive layers 112a and 112e. Therefore, the configuration of the semiconductor device 100C can achieve more stable operation than when operating equivalent to four transistors connected in series.

[0312] An example of the operation of the semiconductor device 100D will be described with reference to FIGS. 20A and 20B.

[0313] 20A shows an example of current paths in semiconductor device 100D when a high potential (potential H0) is applied to conductive layer 104, a high potential (potential H1) is applied to conductive layer 112a, and a low potential (potential L4) is applied to conductive layer 112e. In FIG. 20A, the current paths in semiconductor device 100D are indicated by solid arrows.

[0314] In this case, a high potential (potential H0) is applied to the gate of the transistor 10D_1, and a high potential (potential H1) is applied to either the source or the drain of the transistor 10D_1. A high potential (potential H0) is applied to the gate of the transistor 10D_4, and a low potential (potential L4) is applied to the other of the source or the drain of the transistor 10D_1. The other of the source or the drain of the transistor 10D_1 is connected to the other of the source or the drain of the transistor 10D_4 via the transistors 10D_2 and 10D_3.

[0315] In this case, the transistors 10D_1 to 10D_4 are turned on, and a potential difference of H1 minus L4 occurs between the source or drain of the transistor 10D_1 and the source or drain of the transistor 10D_4. Therefore, a current corresponding to a potential of H1 minus L4 flows through the semiconductor device 100D via the transistors 10D_1 to 10D_4.

[0316] 20B shows an example of current paths in the semiconductor device 100D when a high potential (potential H0) is applied to the conductive layer 104, a high potential (potential H4) is applied to the conductive layer 112e, and a low potential (potential L1) is applied to the conductive layer 112a. In FIG. 20B, the current paths in the semiconductor device 100D are indicated by solid arrows.

[0317] In this case, a high potential (potential H0) is applied to the gate of the transistor 10D_1, and a low potential (potential L1) is applied to one of the source and drain of the transistor 10D_1. A high potential (potential H0) is applied to the gate of the transistor 10D_4, and a high potential (potential H4) is applied to the other of the source and drain of the transistor 10D_1. The other of the source and drain of the transistor 10D_1 is connected to the other of the source and drain of the transistor 10D_4 via the transistors 10D_2 and 10D_3.

[0318] In this case, a current corresponding to a potential of potential H4 minus potential L1 flows through the semiconductor device 100D via the transistors 10D_1 to 10D_4, as in Fig. 20A. However, while the current flows from the transistor 10D_1 to the transistor 10D_4 in Fig. 20A, the current flows from the transistor 10D_4 to the transistor 10D_1 in Fig. 20B.

[0319] With respect to the semiconductor device 100D, the contents described in the semiconductor device 100C can be referred to for other aspects.

[0320] 21A shows a configuration example of a semiconductor device 100E having a different configuration from the semiconductor device 100A shown in FIGS. 1A to 2B. FIG. 21A is a cross-sectional view of the semiconductor device 100E corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100A shown in FIG.

[0321] In the following, differences from the semiconductor device 100A described above will be mainly described, and descriptions of parts that overlap with the semiconductor device 100A may be omitted.

[0322] The semiconductor device 100E includes a transistor 10E_1, a transistor 10E_2, and insulating layers 110_1 and 110_2. The transistor 10E_1 corresponds to the transistor 10A_1 in the semiconductor device 100A. The transistor 10E_2 corresponds to the transistor 10A_2 in the semiconductor device 100A. The semiconductor device 100E differs from the semiconductor device 100A in that an insulating layer 195 is provided to fill recesses formed on the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 in the opening 143.

[0323] The insulating layer 195 is provided on the conductive layer 104 so as to have a region overlapping with the opening 143. The upper surface of the insulating layer 195 preferably has a substantially flat shape. This reduces large steps, such as the recesses described above, that the semiconductor device 100E has. FIG. 21A illustrates a configuration in which the height of the upper surface of the insulating layer 195 and the height of the highest region of the conductive layer 104 as viewed from the substrate surface are substantially equal. By providing the insulating layer 195, the surface on which a layer to be provided on the semiconductor device 100E is to be formed can be substantially flat, thereby improving the coverage of the layer. Note that while FIG. 21A illustrates an example in which the upper surface of the insulating layer 195 has a substantially flat shape, this is not a limitation. The upper surface of the insulating layer 195 may also have an uneven shape. The height of the upper surface of the insulating layer 195 may be higher or lower than the height of the highest region of the conductive layer 104 as viewed from the substrate surface. Even in this case, it is preferable to have the insulating layer 195 because it can reduce the effects of recesses formed on the conductive layer 104 (such as the coverage of a layer formed on the conductive layer 104) compared to when the insulating layer 195 is not present.

[0324] Note that the insulating layer 195 may be provided not only inside the opening 143 but also outside the opening 143. For example, the insulating layer 195 may also be provided on the insulating layer 106 outside the opening 143. In this case, it is preferable that the height of the upper surface of the insulating layer 195 located inside the opening 143 is approximately the same as the height of the upper surface of the insulating layer 195 located outside the opening 143. Alternatively, the entire upper surface of the semiconductor device 100E may be covered with the insulating layer 195, and the height of the upper surface of the insulating layer 195 may be approximately flat.

[0325] An organic insulating material or an inorganic insulating material, or both, can be used for the insulating layer 195. An organic insulating material is preferably used for the insulating layer 195. For example, by using an organic insulating material for the insulating layer 195, a film with excellent flatness can be easily formed at a relatively low temperature on a formation surface having steps.

[0326] Specific examples of organic insulating materials that can be used for the insulating layer 195 include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimideamide resins, siloxane resins, benzocyclobutene-based resins, phenolic resins, and precursors of these resins. Photosensitive materials may also be used as the organic insulating material. Here, photosensitivity refers to the property of being sensitive to ultraviolet light, far ultraviolet light, electron beams, X-rays, and the like. This property is utilized to form a resist pattern by exposure. For exposure of silicon-containing resists, ultraviolet light, and more preferably far ultraviolet light, is primarily used. The raw material monomer used here is preferably aromatic, but to increase sensitivity, it is more desirable for it to have a structure that does not contain an aromatic ring. For example, polyimide resin is preferably used for the insulating layer 195.

[0327] An inorganic insulating material can also be used for the insulating layer 195. Specific examples of the inorganic insulating material that can be used for the insulating layer 195 include the inorganic insulating materials that can be used for the insulating layer 110_1 and the insulating layer 110_2. For example, the insulating layer 195 is preferably made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

[0328] With respect to the semiconductor device 100E, the contents described for the semiconductor device 100A can be referred to for other aspects than those described above.

[0329] 21B shows a configuration example of a semiconductor device 100F having a different configuration from the semiconductor device 100A shown in FIGS. 1A to 2B. FIG. 21B is a cross-sectional view of the semiconductor device 100F corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100A shown in FIG.

[0330] The semiconductor device 100F includes a transistor 10F_1, a transistor 10F_2, and insulating layers 110_1 and 110_2. The transistor 10F_1 corresponds to the transistor 10A_1 in the semiconductor device 100A. The transistor 10F_2 corresponds to the transistor 10A_2 in the semiconductor device 100A. The semiconductor device 100F differs from the semiconductor device 100A in the shape of the conductive layer 104.

[0331] Specifically, in the semiconductor device 100A, the conductive layer 104 has a shape that reflects the shape of the opening 143, whereas in the semiconductor device 100F, a portion of the conductive layer 104 is provided to fill the opening 143, and another portion of the conductive layer 104 is located outside the opening 143. The height of the upper surface of the conductive layer 104 is higher than the height of the upper surface of the semiconductor layer 108. In addition, the upper surface of the conductive layer 104 has a substantially flat shape. This allows recesses generated on the semiconductor layer 108 and the insulating layer 106 formed in the opening 143 to be filled. Therefore, the surface on which a layer to be provided on the semiconductor device 100F is to be formed can be made substantially flat, thereby improving the coverage of the layer.

[0332] It is preferable that the upper surface of the conductive layer 104 in the opening 143 be located at a height at least half the depth of the opening 143 when viewed from the upper surface of the conductive layer 112a. For example, it is preferable that the upper surface of the conductive layer 104 in the opening 143 be located higher than the upper end of the side surface of the conductive layer 112b facing the opening 143. Even in this case, the depth of the recess formed on the conductive layer 104 in the opening 143 can be reduced compared to the semiconductor device 100A shown in FIG. 1B. Therefore, the coverage of the layer provided on the conductive layer 104 can be improved compared to the semiconductor device 100A.

[0333] Furthermore, compared to the semiconductor device 100E shown in FIG. 21A, the step of forming the insulating layer 195 is not necessary, so the number of steps involved in the manufacture can be reduced compared to the semiconductor device 100E.

[0334] With respect to the semiconductor device 100F, the contents described in the semiconductor device 100A can be referred to for other aspects than those described above.

[0335] 22 shows a configuration example of a semiconductor device 100G having a different configuration from the semiconductor device 100A shown in FIGS. 1A to 2B. FIG. 22 is a cross-sectional view of the semiconductor device 100G corresponding to the dashed dotted line A1-A2 in the plan view of the semiconductor device 100A shown in FIG.

[0336] The semiconductor device 100G includes a transistor 10G_1, a transistor 10G_2, and insulating layers 110_1 and 110_2. The transistor 10G_1 corresponds to the transistor 10A_1 in the semiconductor device 100A. The transistor 10G_2 corresponds to the transistor 10A_2 in the semiconductor device 100A. The semiconductor device 100G differs from the semiconductor device 100A in that the transistor 10G_1 and the transistor 10G_2 each include a second gate electrode (also referred to as a back gate electrode) and a second gate insulating layer (also referred to as a back gate insulating layer) and in the configurations of the insulating layer 110_1 and the insulating layer 110_2.

[0337] The transistor 10G_1 includes a conductive layer 114_1 and an insulating layer 110s in addition to the structure of the transistor 10A_1 included in the semiconductor device 100A. In the transistor 10G_1, the conductive layer 114_1 functions as a second gate electrode. The insulating layer 110s functions as a second gate insulating layer.

[0338] The transistor 10G_2 includes a conductive layer 114_2 and an insulating layer 110s in addition to the structure of the transistor 10A_2 included in the semiconductor device 100A. In the transistor 10G_2, the conductive layer 114_2 functions as a second gate electrode. The insulating layer 110s functions as a second gate insulating layer.

[0339] The insulating layer 110_1 includes an insulating layer 110d1, an insulating layer 110e1 on the insulating layer 110d1, an insulating layer 110f1 on the insulating layer 110e1, an insulating layer 110g1 on the insulating layer 110f1, an insulating layer 110h1 on the insulating layer 110g1, and an insulating layer 110i1 on the insulating layer 110h1.

[0340] The insulating layer 110_2 includes an insulating layer 110d2, an insulating layer 110e2 on the insulating layer 110d2, an insulating layer 110f2 on the insulating layer 110e2, an insulating layer 110g2 on the insulating layer 110f2, an insulating layer 110h2 on the insulating layer 110g2, and an insulating layer 110i2 on the insulating layer 110h2.

[0341] The conductive layer 114_1 is provided between the insulating layer 110f1 and the insulating layer 110g1. The conductive layer 112a, the insulating layer 110d1, the insulating layer 110e1, the insulating layer 110f1, the conductive layer 114_1, the insulating layer 110g1, the insulating layer 110h1, the insulating layer 110i1, and the conductive layer 112b have regions that overlap with one another.

[0342] The conductive layer 114_2 is provided between the insulating layer 110f2 and the insulating layer 110g2. The conductive layer 112b, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the conductive layer 112c have regions that overlap with one another.

[0343] The conductive layer 112a, the insulating layer 110d1, the insulating layer 110e1, the insulating layer 110f1, the conductive layer 114_1, the insulating layer 110g1, the insulating layer 110h1, the insulating layer 110i1, the conductive layer 112b, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the conductive layer 112c have regions that overlap with each other.

[0344] Openings 145 reaching the conductive layer 112a are provided in the insulating layer 110d1, the insulating layer 110e1, the insulating layer 110f1, the conductive layer 114_1, the insulating layer 110g1, the insulating layer 110h1, the insulating layer 110i1, the conductive layer 112b, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the conductive layer 112c.

[0345] In the opening 145, an insulating layer 110s is provided in contact with a portion of the upper surface of the conductive layer 112a, the side surfaces of the insulating layers 110d1, 110e1, 110f1, the conductive layer 114_1, 110g1, 110h1, 110i1, the conductive layer 112b, the insulating layer 110d2, the insulating layer 110e2, the insulating layer 110f2, the conductive layer 114_2, the insulating layer 110g2, the insulating layer 110h2, the insulating layer 110i2, and the conductive layer 112c. The upper end of the insulating layer 110s has a curved shape.

[0346] The semiconductor layer 108 is provided in contact with another part of the upper surface of the conductive layer 112a in the opening 145, the side surface of the insulating layer 110s in the opening 145, the curved portion of the insulating layer 110s, and the upper surface of the conductive layer 112c.

[0347] In the transistor 10G_1 included in the semiconductor device 100G, one surface of the semiconductor layer 108 in the opening 145 faces the conductive layer 104 with the insulating layer 106 interposed therebetween, and the other surface of the semiconductor layer 108 in the opening 145 faces the conductive layer 114_1 with the insulating layer 110s interposed therebetween. As described above, the conductive layer 114_1 functions as the second gate electrode of the transistor 10G_1. The insulating layer 110s functions as the second gate insulating layer of the transistor 10G_1.

[0348] Similarly, in the transistor 10G_2 included in the semiconductor device 100G, one surface of the semiconductor layer 108 in the opening 145 faces the conductive layer 104 with the insulating layer 106 interposed therebetween, and the other surface of the semiconductor layer 108 in the opening 145 faces the conductive layer 114_2 with the insulating layer 110s interposed therebetween. As described above, the conductive layer 114_2 functions as the second gate electrode of the transistor 10G_2. The insulating layer 110s functions as the second gate insulating layer of the transistor 10G_2.

[0349] That is, in the semiconductor device 100G, the insulating layer 110s functions as a second gate insulating layer of the transistor 10G_1 and also functions as a second gate insulating layer of the transistor 10G_2.

[0350] The transistors 10G_1 and 10G_2 included in the semiconductor device 100G each have two gate electrodes sandwiching the semiconductor layer 108, allowing a gate electric field to be applied to carriers in the channel formation region from both sides of the semiconductor layer 108. Therefore, the transistors 10G_1 and 10G_2 can achieve a larger on-state current and a smaller off-state current than the transistors 10A_1 and 10A_2 included in the semiconductor device 100A, which have only one gate electrode (conductive layer 104). Furthermore, the threshold voltage can be shifted toward the normally-off state. Furthermore, the saturation characteristics of the current flowing when operating in the saturation region can be improved (i.e., the magnitude of the drain current hardly changes with an increase in the drain voltage).

[0351] The insulating layer 110s, which functions as the second gate insulating layer of the transistor 10G_1 and the transistor 10G_2, is preferably formed using a material that contains oxygen and releases oxygen by heat treatment or the like. For example, the insulating layer 110s can be formed using the material that can be used for the insulating layers 110b1 and 110b2. As a result, when a metal oxide is used for the semiconductor layer 108, for example, oxygen contained in the insulating layer 110s can be supplied to the metal oxide. As a result, oxygen vacancies in the metal oxide can be repaired, thereby improving the electrical characteristics and reliability of the transistor 10G_1 and the transistor 10G_2.

[0352] The conductive layer 114_1 functioning as the second gate electrode of the transistor 10G_1 and the conductive layer 114_2 functioning as the second gate electrode of the transistor 10G_2 can each be made of the material that can be used for the conductive layer 104 described above.

[0353] Among the six insulating layers constituting the insulating layer 110_1, insulating layer 110d1, insulating layer 110f1, insulating layer 110g1, and insulating layer 110i1, and among the six insulating layers constituting the insulating layer 110_2, insulating layer 110d2, insulating layer 110f2, insulating layer 110g2, and insulating layer 110i2, the materials that can be used for the insulating layers 110a1, 110c1, 110a2, and 110c2 described above can be used. Furthermore, the materials that can be used for the insulating layers 110b1 and 110b2 described above can be used for the insulating layers 110e1, 110h1, 110e2, and 110h2.

[0354] As a result, for example, when a metal oxide is used for the semiconductor layer 108, oxygen contained in the insulating layers 110e1, 110h1, 110e2, and 110h2 can be supplied to the semiconductor layer 108 through the insulating layer 110s. This allows oxygen vacancies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of the transistors 10G_1 and 10G_2.

[0355] Furthermore, it is possible to prevent oxygen contained in the insulating layer 110e1 from diffusing to the conductive layer 112a through the insulating layer 110d1 and to the conductive layer 114_1 through the insulating layer 110f1. It is also possible to prevent oxygen contained in the insulating layer 110h1 from diffusing to the conductive layer 114_1 through the insulating layer 110g1 and to the conductive layer 112b through the insulating layer 110i1.

[0356] Similarly, oxygen contained in the insulating layer 110e2 can be prevented from diffusing to the conductive layer 112b through the insulating layer 110d2 and to the conductive layer 114_2 through the insulating layer 110f2. Furthermore, oxygen contained in the insulating layer 110h2 can be prevented from diffusing to the conductive layer 114_2 through the insulating layer 110g2 and to the conductive layer 112c through the insulating layer 110i2.

[0357] With respect to the semiconductor device 100G, the contents described for the semiconductor device 100A can be referred to for other aspects than those described above.

[0358] Although the semiconductor device 100G has a configuration in which both the transistor 10G_1 and the transistor 10G_2 have two gate electrodes, this is not a limitation. For example, the transistor 10G_1 may have two gate electrodes and the transistor 10G_2 may have only one gate electrode. Alternatively, the transistor 10G_1 may have only one gate electrode and the transistor 10G_2 may have two gate electrodes.

[0359] <Example of Manufacturing Method of Semiconductor Device> A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described below with reference to the drawings. Here, the semiconductor device 100A shown in FIGS. 1A to 2B is used as an example.

[0360] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0361] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when film formation is performed using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0362] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, photo-CVD (photo-CVD) methods that utilize light, etc. Furthermore, CVD methods can be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0363] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0364] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0365] The CVD and ALD methods differ from sputtering methods in that particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0366] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film whose composition changes continuously by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0367] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0368] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0369] When processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0370] There are two typical photolithography methods: one is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed; the other is a method in which a photosensitive thin film is formed, and then the thin film is exposed to light and developed to be processed into a desired shape.

[0371] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0372] For etching the thin film, for example, dry etching, wet etching, or sandblasting can be used.

[0373] Typically, a polishing method such as CMP can be suitably used as the planarization treatment of the thin film. Alternatively, a reflow method, in which the conductive layer is subjected to a heat treatment to fluidize it, can be suitably used. Alternatively, a combination of the reflow method and CMP can be used.

[0374] Alternatively, a process may be used in which a planarizing film is formed on an uneven film surface and then highly anisotropically etched (e.g., dry etching) on ​​the planarizing film to form a film with a flat upper surface, or a process may be used in which a planarizing film and a photoresist are formed in that order on the uneven film surface and then highly anisotropically etched on the planarizing film and the photoresist to fill the recesses with only the planarizing film and flatten the entire upper surface (these processes are sometimes referred to as etch-back processes). The etch-back process does not require a high-temperature (e.g., about 800°C) heating process as in the reflow process, and therefore there is no need to worry about damage to the device during fabrication due to the heating process. Furthermore, the etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process using CMP due to the effects of warping, etc.

[0375] Other examples of the planarization treatment for a thin film include dry etching and plasma treatment. The polishing, dry etching, and plasma treatment may be performed multiple times, or a combination of these may be performed. When a combination of these treatments is used, the order of the steps is not particularly limited, and it is preferable to set the order appropriately according to the unevenness of the surface to be treated.

[0376] To precisely process a thin film to a desired thickness, for example, CMP is used. In this case, the thin film is first polished at a constant processing speed until a portion of the top surface of the thin film is exposed. Then, the thin film is polished at a slower processing speed until the thin film reaches the desired thickness, thereby enabling highly precise processing.

[0377] Methods for detecting the end point of polishing include an optical method in which light is irradiated onto the surface of the surface to be treated and changes in the reflected light are detected, a physical method in which changes in the polishing resistance that the processing device receives from the surface to be treated are detected, and a method in which magnetic field lines are applied to the surface to be treated and changes in the magnetic field lines due to the eddy currents that are generated are used.

[0378] After the upper surface of the thin film is exposed, the thickness of the thin film can be controlled with high precision by performing a polishing process at a slow processing speed while monitoring the thickness of the thin film by an optical method such as a laser interferometer. If necessary, the polishing process may be performed multiple times until the thin film reaches the desired thickness.

[0379] 23A to 30C are diagrams illustrating a method for manufacturing the semiconductor device 100A. (A) in each diagram shows a plan view corresponding to FIG. 1A. (B) in each diagram shows a cross-sectional view taken along dashed line A1-A2 in the plan view shown in FIG. 1A. (C) in each diagram shows a cross-sectional view taken along dashed line B1-B2 in the plan view shown in FIG. 1A.

[0380] First, a conductive film to be the conductive layer 112a is formed over the substrate 102, and then part of the conductive film is removed to form the conductive layer 112a (FIGS. 23A to 23C). The conductive film can be formed by, for example, a sputtering method. The conductive film can be processed by one or both of a wet etching method and a dry etching method.

[0381] Subsequently, an insulating film 110a1f, an insulating film 110b1f, and an insulating film 110c1f are formed in this order on the conductive layer 112a and the substrate 102.

[0382] The insulating film 110a1f can be made of any of the materials that can be used for the insulating layer 110a1 described above.

[0383] The insulating film 110a1f can be formed using, for example, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide.

[0384] Specifically, the insulating film 110a1f can be formed by, for example, a silicon nitride film by a sputtering method, a PEALD method, or an aluminum oxide film by a sputtering method.

[0385] Alternatively, for example, a structure in which aluminum oxide and silicon nitride are stacked can be used, for example, a structure in which aluminum oxide formed by sputtering and silicon nitride formed by PEALD are stacked.

[0386] The insulating film 110b1f can be made of any of the materials that can be used for the insulating layer 110b1 described above.

[0387] For example, silicon oxide, silicon oxynitride, or the like can be suitably used as the insulating film 110b1f.

[0388] Specifically, the insulating film 110b1f can be formed by, for example, a silicon oxide film by a sputtering method, a silicon oxide film by a PECVD method, or a silicon oxynitride film by a PECVD method.

[0389] Alternatively, for example, a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked and used.

[0390] After the insulating film 110b1f is formed, heat treatment may be performed. By performing the heat treatment, water and hydrogen can be released from the surface and the interior of the insulating film 110b1f.

[0391] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) may be used. Note that the atmosphere preferably contains as little hydrogen, water, or the like as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, or the like as possible can prevent hydrogen, water, or the like from being taken into the insulating film 110b1f as much as possible. The heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. By using an RTA device, the heat treatment time can be shortened.

[0392] After the heat treatment, a step of supplying oxygen to the insulating film 110b1f may be performed. For example, after the insulating film 110b1f is formed, a metal oxide layer may be formed on the insulating film 110b1f to supply oxygen to the insulating film 110b1f. Alternatively, heat treatment may be performed after the metal oxide layer is formed. By performing heat treatment after the metal oxide layer is formed, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110b1f, and oxygen can be contained in the insulating film 110b1f. In a later step, the oxygen supplied to the insulating film 110b1f is supplied to the semiconductor layer 108, thereby forming oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0393] After the metal oxide layer is formed or after the heat treatment, oxygen may be supplied to the insulating film 110b1f through the metal oxide layer. Examples of a method for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be preferably used. Examples of apparatus that convert gas into plasma using high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.

[0394] The metal oxide layer may be an insulating layer or a conductive layer, and may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0395] For the metal oxide layer, it is preferable to use an oxide material containing one or more of the same elements as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 108. This allows the metal oxide layer to be formed using the same sputtering target as that for the semiconductor layer 108, thereby reducing manufacturing costs.

[0396] When a metal oxide material containing indium and gallium is used for the metal oxide layer, a material having a higher gallium content than the semiconductor layer 108 can be used. By using a material having a higher gallium content for the metal oxide layer, the blocking property against oxygen can be further improved, which is preferable because oxygen contained in the insulating film 110b1f can be prevented from being released to the outside.

[0397] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film 110b1f during the formation of the metal oxide layer.

[0398] Next, the metal oxide layer is removed, for example, by wet etching.

[0399] The process of supplying oxygen to the insulating film 110b1f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like may be supplied to the insulating film 110b1f by ion doping, ion implantation, plasma treatment, or the like. Alternatively, a film that suppresses oxygen desorption may be formed over the insulating film 110b1f, and then oxygen may be supplied to the insulating film 110b1f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption may be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten.

[0400] The insulating film 110c1f can be made of any of the materials that can be used for the insulating layer 110c1 described above.

[0401] For the material and the deposition method that can be used for the insulating film 110c1f, the above description of the material and the deposition method that can be used for the insulating film 110a1f can be referred to.

[0402] Next, a conductive film 112bf is formed over the insulating film 110c1f (FIGS. 24A to 24C). The conductive film 112bf can be formed using any of the materials that can be used for the conductive layer 112b described above. The conductive film 112bf can be formed by, for example, a sputtering method.

[0403] Next, a part of the conductive film 112bf is removed to form a conductive layer 112be (FIGS. 25A to 25C). The conductive layer 112be may be formed by wet etching or dry etching, or both. The conductive layer 112be is formed to have a region overlapping with the conductive layer 112a.

[0404] Next, the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112cf are formed in this order over the conductive layer 112be and the insulating film 110c1f ( FIGS. 26A to 26C ). For materials that can be used for the insulating film 110a2f, the insulating film 110b2f, the insulating film 110c2f, and the conductive film 112cf, as well as their formation methods, the descriptions of the insulating film 110a1f, the insulating film 110b1f, the insulating film 110c1f, and the conductive film 112bf can be referred to, respectively.

[0405] Next, a part of the conductive film 112cf is removed to form a conductive layer 112ce (FIGS. 27A to 27C). The conductive layer 112ce may be formed by wet etching or dry etching, or both. The conductive layer 112ce is formed to have a region overlapping with the conductive layer 112be and the conductive layer 112a.

[0406] Next, a process is performed to remove parts of the conductive layer 112ce, the insulating film 110c2f, the insulating film 110b2f, the insulating film 110a2f, the conductive layer 112be, the insulating film 110c1f, the insulating film 110b1f, and the insulating film 110a1f, thereby forming an opening 143 that reaches the conductive layer 112a. For example, dry etching can be suitably used for this process. By this process, the conductive layer 112c, the insulating layer 110c2, the insulating layer 110b2, the insulating layer 110a2, the conductive layer 112b, the insulating layer 110c1, the insulating layer 110b1, and the insulating layer 110a1, each having an opening, are formed ( FIGS. 28A to 28C ).

[0407] Next, a semiconductor film to be the semiconductor layer 108 is formed in contact with the top surface of the conductive layer 112a in the opening 143, the side surfaces of the insulating layer 110_1 (insulating layer 110a1, insulating layer 110b1, and insulating layer 110c1) in the opening 143, the side surfaces of the conductive layer 112b in the opening 143, the side surfaces of the insulating layer 110_2 (insulating layer 110a2, insulating layer 110b2, and insulating layer 110c2) in the opening 143, the side surfaces of the conductive layer 112c in the opening 143, and the top surface of the conductive layer 112c. Then, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108 ( FIGS. 29A to 29C ). The semiconductor layer 108 is provided so as to have a region overlapping with the opening 143. The semiconductor layer 108 is also provided so that an end portion thereof is in contact with the conductive layer 112c.

[0408] For the semiconductor film that becomes the semiconductor layer 108, the above-described materials that can be used for the semiconductor layer 108 can be used as appropriate.

[0409] A sputtering method, for example, can be used to form the semiconductor film that becomes the semiconductor layer 108. For example, when a metal oxide is used for the semiconductor layer 108, the semiconductor layer 108 can be formed by a sputtering method using a metal oxide target. The sputtering method is preferable because a film with a low hydrogen content can be formed relatively easily.

[0410] When a metal oxide is used for the semiconductor layer 108, the semiconductor layer 108 can be formed by an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0411] For example, when forming an In—Ga—Zn oxide, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0412] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0413] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0414] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0415] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0416] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions successively.

[0417] The use of an ALD method for forming the semiconductor film to be the semiconductor layer 108 is preferable because the semiconductor layer 108 can be formed with a uniform thickness on the side surfaces of the insulating layer 110_1, the conductive layer 112b, the insulating layer 110_2, and the conductive layer 112c.

[0418] Heat treatment may be performed after the formation of the semiconductor film to be the semiconductor layer 108. The heat treatment can reduce water and hydrogen contained in the semiconductor film and supply oxygen to the semiconductor film from the insulating layers 110_1 and 110_2. Note that the heat treatment may be performed after the semiconductor film is processed.

[0419] The substrate temperature (stage temperature) during the formation of the semiconductor layer 108 is preferably from room temperature (25° C.) to 200° C., more preferably from room temperature to 130° C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when a large-area glass substrate is used.

[0420] The higher the substrate temperature during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed.Furthermore, the higher the oxygen flow rate ratio, the higher the crystallinity of the metal oxide layer that can be formed.

[0421] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112c, and the insulating layer 110c2 (FIGS. 30A to 30C). The insulating layer 106 has regions in contact with the top and side surfaces of the semiconductor layer 108, the top and side surfaces of the conductive layer 112c, and the top surface of the insulating layer 110c2.

[0422] The insulating layer 106 can be formed using any of the materials described above as appropriate.

[0423] The insulating layer 106 can be formed by, for example, an ALD method. The ALD method is preferable because it allows the insulating layer 106 to be formed with good coverage over the semiconductor layer 108 formed to cover the opening 143. Note that, if the semiconductor layer 108 can be sufficiently covered, a method other than the ALD method may be used to form the insulating layer 106. For example, a PECVD method, a sputtering method, or the like can be used. This allows the insulating layer 106 to be formed at a higher rate than when the ALD method is used, thereby improving productivity.

[0424] Subsequently, a conductive film to be the conductive layer 104 is formed over the insulating layer 106. The conductive film to be the conductive layer 104 can be formed using any of the materials that can be used for the conductive layer 104 described above. The conductive film to be the conductive layer 104 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate. The conductive film to be the conductive layer 104 is preferably formed in contact with the side surfaces of the insulating layer 110_1 and the insulating layer 106 that faces the side surfaces of the insulating layer 110_2 in the opening 143. Therefore, the conductive film to be the conductive layer 104 is preferably formed using a method that has good coverage or embedding properties, and more preferably using a CVD method, an ALD method, or the like.

[0425] Next, a part of the conductive film that will become the conductive layer 104 is removed to form the conductive layer 104. The conductive layer 104 is formed to have a region that overlaps with the opening 143. In addition, in the region where the conductive film that will become the conductive layer 104 is removed, the top surface of the insulating layer 106 is exposed. The conductive layer 104 may be formed by using one or both of a wet etching method and a dry etching method.

[0426] As a result, the transistor 10A_1 and the transistor 10A_2 are formed.

[0427] Through the above steps, the semiconductor device 100A can be manufactured (FIGS. 1A to 2B).

[0428] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0429] A semiconductor device according to one embodiment of the present invention can be applied to, for example, a scan line driver circuit of a display device. In this embodiment, a configuration example of the circuit, an application location of the semiconductor device in the circuit, and the like will be described.

[0430] Examples of the display device of one embodiment of the present invention include a liquid crystal display device, an organic EL device, a light-emitting device including a light-emitting device such as an LED, and electronic paper that displays images using an electrophoresis system or the like.

[0431] 31A to 31C show examples of the configuration of a driver circuit to which the semiconductor device of one embodiment of the present invention can be applied. The driver circuit can function as, for example, a scan line driver circuit of a display device. FIG. 31A is an example of a sequential circuit. FIG. 31B is an example of a driver circuit including the sequential circuit shown in FIG. 31A. FIG. 31C is an example of a timing chart of the driver circuit shown in FIG. 31B.

[0432] <Configuration Example of Driver Circuit> An example of a driver circuit that is formed by connecting multiple sequential circuits in stages and functions as a shift register will be described below. As described above, the semiconductor device of one embodiment of the present invention described in the above embodiment can be applied to the driver circuit.

[0433] 31A is a diagram illustrating input / output terminals of the sequential circuit 20. The sequential circuit 20 has input terminals to which the signals LIN, RIN, RES, CLK1, CLK2, and CLK3 are respectively input, and output terminals to which the signals SROUT, OUTA, and OUTB are respectively input.

[0434] 31B shows a configuration example of the driver circuit 30. The driver circuit 30 includes a plurality of sequential circuits 20. Sequential circuits 20_1 to 20_6 are shown in FIG. 31B. Hereinafter, the n-th sequential circuit from the side closest to the input of the driver circuit 30 will be referred to as a sequential circuit 20_n (n is an integer equal to or greater than 1).

[0435] In sequential circuit 20_n, any three of signals CLK1 to CLK4 are used as signals CLK1, CLK2, and CLK3. The combinations of signals CLK1 to CLK4 are the same for every four stages. That is, the same signals are input to sequential circuit 20_n and sequential circuit 20_n+4 as signals CLK1, CLK2, and CLK3. For example, in the case of sequential circuits 20_1 to 20_6 constituting the driver circuit 30 shown in FIG. 31B, the same signals (here, signals CLK1, CLK2, and CLK3) are input to sequential circuit 20_1 and sequential circuit 20_5 as signals CLK1, CLK2, and CLK3. The sequential circuit 20_2 and the sequential circuit 20_6 receive the same signals (here, the signals CLK2, CLK3, and CLK4) as the signals CLK1, CLK2, and CLK3.

[0436] Here, clock signals can be used as the signals CLK1 to CLK4. The clock signals can be preferably signals with a duty ratio (the ratio of the period during which the signal is at a high level potential in one cycle) of 45% to 55%. More preferably, the clock signals can be signals with a duty ratio of 50%. The duty ratio of the clock signals is not limited to the above and can be changed as appropriate depending on the driving method.

[0437] In this specification, a clock signal refers to a signal in which high and low potentials are repeated, and the interval between the rising edge of one potential and the rising edge of the next potential, or the interval between the falling edge of one potential and the falling edge of the next potential, is constant. In this specification, a pulse signal refers to a signal whose potential changes over time. Pulse signals also include signals whose potential changes periodically. For example, pulse signals include signals whose potential changes periodically, such as rectangular waves, triangular waves, sawtooth waves, and sine waves. Therefore, a clock signal can also be considered one form of a pulse signal.

[0438] The sequential circuit 20_1 receives the signal SP as the signal LIN. The sequential circuit 20_n, where n is 2 or greater, receives the signal LIN from the output terminal SROUTn-1 of the preceding sequential circuit 20_n-1. The sequential circuit 20_n receives the signal RIN from the output terminal SROUTn+2 of the succeeding sequential circuit 20_n+2.

[0439] Specifically, the sequential circuit 20_1 receives the signals CLK1, CLK2, CLK3, and SP, and the signal at the output terminal SROUT3 of the sequential circuit 20_3, and outputs output signals to the output terminals SROUT1, OUTA1, and OUTB1, respectively. The sequential circuit 20_2 receives the signals CLK2, CLK3, and CLK4, the signal at the output terminal SROUT1 of the sequential circuit 20_1, and the signal at the output terminal SROUT4 of the sequential circuit 20_4, and outputs output signals to the output terminals SROUT2, OUTA2, and OUTB2, respectively.

[0440] Fig. 31C shows a timing chart relating to the driving method of the driving circuit 30. Fig. 31C shows, from the top to the bottom, the changes in potential over time for the signal SP, signals CLK1 to CLK4, signal RES, output terminals OUTA1 to OUTA6, output terminals OUTB1 to OUTB6, and output terminals SROUT1 to SROUT6.

[0441] First, at time T0, signals SP, CLK3, and CLK4 are at high potential, and signals CLK1 and CLK2 are at low potential. At this time, low potentials are output to output terminals OUTA2 through OUTA6, high potentials are output to output terminals OUTB2 through OUTB6, and low potentials are output to output terminals SROUT1 through SROUT6. Furthermore, as signal SP is at high potential, a high potential is output to output terminal OUTA1 and a low potential is output to output terminal OUTB1.

[0442] Next, at time T1, the signal CLK1 changes from low potential to high potential, and the signal CLK3 changes from high potential to low potential, so that the sequential circuit 20_1 maintains the high potential output to the output terminal OUTA1 and the low potential output to the output terminal OUTB1, and a high potential is output to the output terminal SROUT1. Also, a high potential is output to the output terminal OUTA2, and a low potential is output to the output terminal OUTB2.

[0443] Thereafter, signals CLK1 to CLK4 sequentially output high potentials to the output terminals from output terminal OUTA2 onwards, low potentials to the output terminals from output terminal OUTB2 onwards, and high potentials to the output terminals from output terminal SROUT2 onwards.

[0444] The signals CLK1 to CLK4 are clock signals that are shifted by a quarter period, and therefore, as shown in Fig. 31C, the output terminals OUTA1 to OUTA6, the output terminals OUTB1 to OUTB6, and the output terminals SROUT1 to SROUT6 output signals that are shifted by a quarter period, such as the signal CLK1.

[0445] The configuration of the driver circuit is not limited to this, and the signals, output terminals, etc. can be changed as appropriate to match the configuration of the sequential circuit used.

[0446] The above is a description of an example of the configuration of the drive circuit.

[0447] 32A illustrates a configuration example of a sequential circuit 20A of one embodiment of the present invention. The sequential circuit 20A includes a circuit 11 and a circuit 12. The circuit 11 includes a wiring WA connected to an output terminal OUTA and a wiring WB connected to an output terminal OUTB. The circuit 11 and the circuit 12 are connected to each other through the wiring WA and the wiring WB.

[0448] The circuit 11 includes a transistor Tr11, a transistor Tr12, a transistor Tr13, a transistor Tr14, a transistor Tr15, a transistor Tr21, a transistor Tr22, and a capacitor C21.

[0449] The circuit 12 includes a transistor Tr16, a transistor Tr20, a transistor Tr23, and a capacitor C11.

[0450] The circuit 11 and the circuit 12 are supplied with a potential VDD from a high potential power supply and a potential VSS from a low potential power supply.

[0451] The signals CLK2, CLK3, LIN, RIN, and RES are input to the circuit 11. The circuit 11 has a function of outputting a first signal to the wiring WA and an inverted second signal of the first signal to the wiring WB in accordance with the potentials of the signals CLK2, CLK3, LIN, and RIN. That is, the circuit 11 can also be called a control circuit. A signal for controlling the reset operation of the sequential circuit 20A is supplied to the signal RES.

[0452] The circuit 12 receives the signal CLK1, the first signal, and the second signal. The circuit 12 has a function of outputting one of the signal CLK1 and the potential VSS to the output terminal SROUT based on the potentials of the signal CLK1, the first signal, and the second signal. The circuit 12 outputs the signal CLK1 when the first signal is at a high potential (the second signal is at a low potential), and outputs the potential VSS when the second signal is at a high potential (the first signal is at a low potential). The circuit 12 can be called an amplifier circuit, a buffer circuit, or the like.

[0453] The sequential circuit 20A functions as a flip-flop circuit and can be used as part of a shift register circuit. For example, the sequential circuit 20A can be used as part of a drive circuit of a display device. In particular, the sequential circuit 20A can be suitably used as part of a scan line drive circuit of a display device.

[0454] When the sequential circuit 20A is applied to a scanning line driver circuit, scanning lines (also called gate lines) connected to a plurality of pixels of a display device can be connected to at least one or both of the output terminal OUTA and the output terminal OUTB. By connecting scanning lines to both the output terminal OUTA and the output terminal OUTB, it becomes possible to drive pixels with two types of scanning line signals, thereby realizing more multifunctional pixels.

[0455] The configuration of the sequential circuit 20A will be described in detail below.

[0456] In the circuit 11, the gate of the transistor Tr11 is connected to a wiring that receives a signal LIN, one of its source or drain is connected to a wiring WA and one of the source or drain of the transistor Tr21, and the other of its source or drain is connected to a wiring that receives a potential VDD. The gate of the transistor Tr12 is connected to a wiring that receives a signal CLK3, one of its source or drain is connected to one of the source or drain of the transistor Tr13, and the other of its source or drain is connected to a wiring that receives a potential VDD. The gate of the transistor Tr13 is connected to a wiring that receives a signal CLK2, and the other of its source or drain is connected to a wiring WB, one electrode of the capacitor C21, and the gate of the transistor Tr21. The gate of the transistor Tr14 is connected to a wiring that receives a signal RIN, one of its source or drain is connected to the wiring WB, and the other of its source or drain is connected to a wiring that receives a potential VDD. The transistor Tr15 has a gate connected to a wiring to which a signal RES is applied, one of a source or a drain connected to a wiring WB, and the other of a source or a drain connected to a wiring to which a potential VDD is applied. The transistor Tr21 has the other of a source or a drain connected to a wiring to which a potential VSS is applied. The transistor Tr22 has a gate connected to a wiring to which a signal LIN is applied, one of a source or a drain connected to a wiring WB, and the other of a source or a drain connected to a wiring to which a potential VSS is applied. The capacitor C21 has the other electrode connected to a wiring to which a potential VSS is applied.

[0457] In the circuit 12, the gate of the transistor Tr16 is connected to a wiring to which a potential VDD is applied, one of the source and the drain is connected to a wiring WA, and the other of the source and the drain is connected to one electrode of the capacitor C11 and the gate of the transistor Tr20. The transistor Tr20 has one of the source and the drain connected to the other electrode of the capacitor C11 and the output terminal SROUT, and the other of the source and the drain connected to a wiring to which a signal CLK1 is applied. The transistor Tr23 has a gate connected to a wiring WB, one of the source and the drain connected to the output terminal SROUT, and the other of the source and the drain connected to a wiring to which a potential VSS is applied.

[0458] The transistors Tr11 and Tr22 are turned on or off in accordance with the potential of the signal LIN, and the transistor Tr14 is turned on or off in accordance with the potential of the signal RIN.

[0459] When the signal LIN is at a high potential and the signal RIN is at a low potential, the transistors Tr11 and Tr22 are turned on, and the transistor Tr14 is turned off. Therefore, the wiring to which the potential VDD is applied is connected to the wiring WA via the transistor Tr11. Furthermore, the wiring to which the potential VSS is applied is connected to the wiring WB via the transistor Tr22. At this time, since the wiring WA is at a high potential, a high potential is also applied to the gate of the transistor Tr20 via the transistor Tr16, so that the transistor Tr20 is turned on. Therefore, the signal CLK1 is output to the output terminal SROUT via the transistor Tr20.

[0460] On the other hand, when the signal LIN is at a low potential and the signal RIN is at a high potential, the transistor Tr14 is turned on, and the transistors Tr11 and Tr22 are turned off. Therefore, the wiring to which the potential VDD is applied is connected to the wiring WB via the transistor Tr14. Furthermore, when the wiring WB is at a high potential, the transistor Tr21 is turned on. Therefore, the wiring to which the potential VSS is applied is connected to the wiring WA via the transistor Tr21. At this time, when the wiring WB is at a high potential, a high potential is also applied to the gate of the transistor Tr23, so that the transistor Tr23 is turned on. Therefore, the potential VSS is output to the output terminal SROUT via the transistor Tr23.

[0461] As described above, when a high potential is applied to the wiring WA, the transistor Tr20 is turned on. At this time, if the high potential applied to the wiring WA is equal to the potential VDD, a potential lower than the potential VDD by the threshold voltage of the transistor Tr16 is applied to the gate of the transistor Tr20. Because the output terminal SROUT and the gate of the transistor Tr20 are connected via the capacitor C11, the potential of the gate of the transistor Tr20 (the potential of the other of the source or drain of the transistor Tr16) increases as the potential of the output terminal SROUT increases due to the bootstrap effect. Since the potential of the gate of the transistor Tr20 increases to, for example, a potential nearly twice the potential VDD, the potential VDD can be output to the output terminal SROUT without being affected by the threshold voltage of the transistor Tr20. This allows the sequential circuit 20A to have high output performance without increasing the number of power supply potentials.

[0462] Thereafter, when the potential of the other of the source and drain of transistor Tr16 exceeds the potential VDD, transistor Tr16 is turned off, so that the gate of transistor Tr20 and the wiring WA are electrically disconnected, and the gate of transistor Tr23 is brought into a floating state. Furthermore, because transistor Tr16 is turned off, the potential of the wiring WA does not rise above the output potential of circuit 12, so that a potential higher than the output potential is prevented from being applied to transistors, etc. in circuit 12 via the wiring WA. This improves the reliability of sequential circuit 20A.

[0463] Each transistor included in the sequential circuit 20A is preferably an OS transistor. The leakage current flowing between the source and drain of an OS transistor in an off state is significantly smaller than that of a Si transistor. By using OS transistors in the circuits 11 and 12, the power consumption of each circuit can be significantly reduced.

[0464] As described above, the sequential circuit 20A includes multiple transistors, each of which has one of its electrodes (source electrode, drain electrode, and gate electrode) connected to another. Therefore, simply arranging these transistors on the same plane increases the area occupied by the transistors on the substrate, making it difficult to fabricate a narrow-framed scanning line driver circuit. Furthermore, because the transistors have various interconnections, the layout of each transistor or the layout of the wiring connecting the transistors becomes complicated, resulting in an extremely large number of steps required to fabricate the entire scanning line driver circuit.

[0465] In contrast, the semiconductor device of one embodiment of the present invention has a stacked structure of multiple vertical transistors sharing some components. Therefore, the area occupied by the transistors in the substrate surface can be significantly reduced compared to when planar transistors are arranged on the same plane. Furthermore, by applying different voltages to the sources and drains of the stacked vertical transistors, the operation method of each semiconductor device can be changed. For example, each transistor can be appropriately switched between a series connection and a parallel connection. Furthermore, the transistors can be operated individually. Therefore, the semiconductor device of one embodiment of the present invention can be suitably used for each portion of the scan line driver circuit. This reduces the number of steps required to fabricate the entire scan line driver circuit compared to when transistors are individually fabricated. Furthermore, a high-performance scan line driver circuit with an extremely narrow frame can be realized.

[0466] <Configuration Example 2 of Sequential Circuit> Fig. 32B shows a configuration example of a sequential circuit 20B that is different from the sequential circuit 20A shown in Fig. 32A. The sequential circuit 20B differs from the sequential circuit 20A in the configuration of transistors.

[0467] Specifically, in the sequential circuit 20B, all the transistors included in the circuit 11 and the circuit 12 are transistors with back gates.

[0468] Of these, the back gates of the transistors Tr21 and Tr23 are connected to a wiring to which the potential VSS is applied, that is, the back gates of the transistors Tr21 and Tr23 are connected to the sources.

[0469] When the sequential circuit 20B is used in a scanning line driving circuit, the period during which the wiring WB is at a high potential is significantly longer than the period during which it is at a low potential. Therefore, the transistors Tr21 and Tr23, whose gates are connected to the wiring WB, are in an on state for a significantly longer period than the off state. Therefore, the threshold voltages of the transistors Tr21 and Tr23 are more likely to fluctuate than the other transistors. Specifically, the threshold voltages of the transistors are more likely to shift in the positive direction.

[0470] Therefore, the transistors Tr21 and Tr23 have a pair of gates that overlap with each other with a semiconductor layer sandwiched therebetween, and one of the gates is connected to a wiring to which a low potential is applied (a wiring to which the potential VSS is applied). This configuration can suitably prevent the threshold voltages of the transistors Tr21 and Tr23 from shifting in the positive direction. This can improve the reliability of the sequential circuit 20B, or a semiconductor device, a display device, an electronic device, or the like that uses the sequential circuit 20B.

[0471] Furthermore, by configuring transistors Tr21 and Tr23 so that one gate and one source are connected, it is possible to preferably prevent the threshold voltage from becoming a negative value. That is, it is easy to make transistors Tr21 and Tr23 have normally-off characteristics. Furthermore, by configuring transistors Tr21 and Tr23 so that one gate and one source are connected, it is also possible to achieve an effect of improving saturation. This simplifies the design of circuits 11 and 12 and enables the realization of circuits that can operate stably.

[0472] On the other hand, transistors other than the transistor Tr21 and the transistor Tr23 are configured with a pair of gates connected to each other. By connecting a pair of gates that overlap with each other with a semiconductor layer sandwiched therebetween, it is possible to increase the on-state current of the transistors. This makes it possible to improve the driving capability of the sequential circuit 20B.

[0473] Note that in the sequential circuit 20B, all the transistors included in the circuit 11 and the circuit 12 have a back gate; however, this is not limited thereto, and any one or more of the transistors included in the circuit 11 and the circuit 12 may have a back gate.

[0474] For example, the semiconductor device 100G described in the first embodiment can be applied to the sequential circuit 20B.

[0475] For the sequential circuit 20B, other than the above, the description of the sequential circuit 20A can be referred to.

[0476] 33A shows a configuration example of a sequential circuit 20C that is different from the sequential circuit 20A shown in Fig. 32A. The sequential circuit 20C differs from the sequential circuit 20A in the configuration of transistors included in the circuit 12.

[0477] Specifically, in the sequential circuit 20C, the transistor corresponding to the transistor Tr20 in the sequential circuit 20A is configured with two transistors, a transistor Tr20a and a transistor Tr20b.

[0478] One of the source or drain of transistor Tr20a is connected to one of the source or drain of transistor Tr20b. The other of the source or drain of transistor Tr20a is connected to the other of the source or drain of transistor Tr20b. The gate of transistor Tr20a is connected to the gate of transistor Tr20b. In other words, transistor Tr20a and transistor Tr20b can be said to be connected in parallel with each other.

[0479] In this way, by configuring two transistors in parallel, it is possible to obtain approximately twice the on-state current compared to a configuration having only one transistor, assuming that each transistor has the same current generating capacity. Note that, although the sequential circuit 20C shows an example of a configuration in which two transistors, transistor Tr20a and transistor Tr20b, are connected in parallel, this is not limitative and a configuration in which three or more transistors are connected in parallel is also possible. Increasing the number of transistors connected in parallel is preferable because it allows for a larger overall output current.

[0480] As described above, the circuit 12 functions as an amplifier circuit and plays a role in outputting the signal generated by the circuit 11 to the output terminal SROUT. It is preferable that the circuit 12 amplifies the signal generated by the circuit 11 as much as possible and supplies the amplified signal to the output terminal SROUT. Therefore, as in the circuit 12 included in the sequential circuit 20C, it is preferable to configure the transistor located immediately before the output terminal SROUT as a plurality of transistors connected in parallel, because this allows a larger current to be supplied to the output terminal SROUT than when only one transistor is included.

[0481] Note that, when multiple transistors are connected in parallel, as in the circuit 12 included in the sequential circuit 20C, the output current can be increased, but the increased number of transistors may increase the overall area occupied by the semiconductor device. However, in one embodiment of the present invention, transistors can be stacked, thereby increasing the output current without increasing the area occupied by the semiconductor device. For example, the semiconductor device 100A described in Embodiment 1 can be applied to the combination of the transistor Tr20a and the transistor Tr20b included in the sequential circuit 20C. In this case, the transistor 10A_1 included in the semiconductor device 100A corresponds to either the transistor Tr20a or the transistor Tr20b, and the transistor 10A_2 corresponds to the other transistor Tr20a or the transistor Tr20b. For example, by applying the operation methods shown in FIGS. 4A and 4B to the semiconductor device 100A, it is possible to achieve an operation equivalent to that achieved when the transistors Tr20a and Tr20b are connected in parallel.

[0482] Furthermore, the number of parallel-connected transistors included in the sequential circuit 20C is not limited to two, and may be three or more. For example, if the sequential circuit 20C has a portion where four transistors are connected in parallel, the semiconductor device 100C described in the first embodiment can be applied to that portion. For example, by applying the operation methods shown in FIGS. 15 and 16 to the semiconductor device 100C, it is possible to realize an operation equivalent to the operation of four transistors connected in parallel.

[0483] In the sequential circuit 20C, only the transistors corresponding to the transistor Tr20 in the sequential circuit 20A are connected in parallel, but this is not limited thereto, and transistors other than the transistor Tr20 may also be connected in parallel.

[0484] For the sequential circuit 20C, the description of the sequential circuit 20A can be referred to for other details.

[0485] <Configuration Example 4 of Sequential Circuit> Fig. 33B shows a configuration example of a sequential circuit 20D that is different from the sequential circuit 20A shown in Fig. 32A. The sequential circuit 20D differs from the sequential circuit 20A in the configuration of transistors.

[0486] Specifically, in sequential circuit 20D, the transistor corresponding to transistor Tr14 in sequential circuit 20A is composed of two transistors, transistor Tr14a and transistor Tr14b. Furthermore, the transistor corresponding to transistor Tr15 in sequential circuit 20A is composed of two transistors, transistor Tr15a and transistor Tr15b. Furthermore, the transistor corresponding to transistor Tr21 in sequential circuit 20A is composed of two transistors, transistor Tr21a and transistor Tr21b. Furthermore, the transistor corresponding to transistor Tr22 in sequential circuit 20A is composed of two transistors, transistor Tr22a and transistor Tr22b. Furthermore, the transistor corresponding to transistor Tr23 in sequential circuit 20A is composed of two transistors, transistor Tr23a and transistor Tr23b.

[0487] The source or drain of transistor Tr14a is connected to the source or drain of transistor Tr14b. The gate of transistor Tr14a is connected to the gate of transistor Tr14b. That is, transistor Tr14a and transistor Tr14b are connected in series. The same applies to transistors Tr15a and Tr15b, transistors Tr21a and Tr21b, transistors Tr22a and Tr22b, and transistors Tr23a and Tr23b.

[0488] In this way, by using a configuration in which two transistors are connected in series, and each transistor has the same current generating capability, the off-state current can be reduced to about half compared to a configuration having only one transistor, and the source-drain breakdown voltage can be increased.

[0489] Note that, when multiple transistors are connected in series as in the sequential circuit 20D, it is possible to reduce the off-state current and improve the source-drain breakdown voltage. However, an increase in the number of transistors may increase the overall area occupied by the semiconductor device. However, in one embodiment of the present invention, transistors can be stacked, thereby reducing the off-state current and improving the source-drain breakdown voltage without increasing the area occupied by the semiconductor device. For example, the semiconductor device 100A described in Embodiment 1 can be applied to the combination of two series-connected transistors included in the sequential circuit 20D. For example, by applying the operation method shown in FIGS. 3C and 3D to the semiconductor device 100A, it is possible to achieve an operation equivalent to the operation of two series-connected transistors. Alternatively, for example, the semiconductor device 100B described in Embodiment 1 can be applied to the combination of two series-connected transistors included in the sequential circuit 20D. For example, by applying the operation method shown in FIGS. 7A and 7B to the semiconductor device 100B, it is possible to achieve an operation equivalent to the operation of two series-connected transistors.

[0490] Furthermore, the number of series-connected transistors included in the sequential circuit 20D is not limited to two, and may be three or more. For example, if the sequential circuit 20D has a portion where four transistors are connected in series, the semiconductor device 100C described in the first embodiment can be applied to that portion. For example, by applying the operation method shown in FIG. 14A to the semiconductor device 100C, it is possible to realize an operation equivalent to the operation of four transistors connected in series. Alternatively, the semiconductor device 100D described in the first embodiment can be applied. For example, by applying the operation method shown in FIGS. 20A and 20B to the semiconductor device 100D, it is possible to realize an operation equivalent to the operation of four transistors connected in series.

[0491] 13A or 14B, it is possible to operate only any two of the four transistors in series connection. Also, for example, by applying the operation method shown in Fig. 13B, it is possible to operate only any three of the four transistors in series connection.

[0492] In the sequential circuit 20D, two transistors are connected in series for the transistors corresponding to transistors Tr14, Tr15, Tr21, Tr22, and Tr23 in the sequential circuit 20A. However, this is not limited to this. Two transistors may also be connected in series for the transistors corresponding to transistors Tr11, Tr12, Tr13, Tr16, and Tr20 in the sequential circuit 20A. Furthermore, as described above, the number of transistors connected in series is not limited to two, and three or more transistors may be connected in series. Increasing the number of transistors connected in series is preferable because it reduces the overall off-state current. It is also preferable because it increases the overall source-drain breakdown voltage.

[0493] For the sequential circuit 20D, other than the above, the description of the sequential circuit 20A can be referred to.

[0494] As described above, the semiconductor device of one embodiment of the present invention has a structure in which two vertical transistors having various connection relationships (parallel connection, series connection, etc.) are stacked. Therefore, for example, by using the semiconductor device of one embodiment of the present invention in a scan line driver circuit of a display device, the area occupied by the scan line driver circuit can be reduced compared to when the transistors are provided on the same plane, and the frame of the display device can be narrowed.

[0495] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0496] Embodiment 3 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 34A to 36F.

[0497] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0498] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0499] In particular, the display device of one embodiment of the present invention can be suitably used in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0500] The display device of one embodiment of the present invention preferably has an extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0501] The electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0502] The electronic device of the present embodiment can have various functions, such as a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, time, etc., a function of executing various software (programs), a wireless communication function, a function of reading out programs or data recorded on a recording medium, etc.

[0503] 34A to 34D , examples of wearable devices that can be worn on the head are described. These wearable devices have at least one of the functions of displaying AR content, VR content, SR content, and MR content. By having an electronic device with the function of displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion felt by the user.

[0504] The electronic device 700A shown in Figure 34A and the electronic device 700B shown in Figure 34B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0505] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0506] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0507] Each of electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of it as an imaging unit. Furthermore, each of electronic device 700A and electronic device 700B may be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0508] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0509] The electronic device 700A and the electronic device 700B are each provided with a battery (not shown), which can be charged wirelessly and / or wired.

[0510] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can broaden the range of operations.

[0511] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0512] When an optical touch sensor is used, a photoelectric conversion element can be used as the light receiving element. The active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0513] The electronic device 800A shown in Figure 34C and the electronic device 800B shown in Figure 34D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0514] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided. This allows a user to feel a high sense of immersion.

[0515] The display unit 820 is provided inside the housing 821 at a position where it can be viewed through the lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0516] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0517] It is preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the left-right positions of the lens 832 and the display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic device 800A and the electronic device 800B each have a mechanism for adjusting the focus by changing the distance between the lens 832 and the display unit 820.

[0518] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that in Fig. 34C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0519] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0520] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0521] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0522] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like, or power for charging a battery provided in the electronic device.

[0523] The electronic device of one embodiment of the present invention may have a function of wirelessly communicating with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, an electronic device 700A shown in FIG. 34A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, an electronic device 800A shown in FIG. 34C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0524] The electronic device may have an earphone unit. Electronic device 700B shown in Fig. 34B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0525] Similarly, electronic device 800B shown in Fig. 34D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0526] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0527] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type devices (such as the electronic device 700A and the electronic device 700B) and goggle-type devices (such as the electronic device 800A and the electronic device 800B) are suitable.

[0528] An electronic device according to one embodiment of the present invention can transmit information to an earphone via a wired or wireless connection.

[0529] The electronic device 6500 shown in FIG. 35A is a portable information terminal that can be used as a smartphone.

[0530] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0531] The display device of one embodiment of the present invention can be applied to the display portion 6502 .

[0532] FIG. 35B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0533] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0534] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0535] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0536] The display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, the thickness of the electronic device can be reduced and a large-capacity battery 6518 can be mounted thereon. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the display portion 6502, an electronic device with a narrow frame can be realized.

[0537] 35C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0538] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0539] 35C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0540] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is also possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0541] 35D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0542] The display device of one embodiment of the present invention can be applied to the display portion 7000 .

[0543] 35E and 35F show an example of digital signage.

[0544] 35E includes a housing 7301, a display portion 7000, a speaker 7303, and the like. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0545] 35F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0546] 35E and 35F, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0547] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0548] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0549] 35E and 35F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0550] The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0551] Furthermore, the semiconductor device and the display device according to one embodiment of the present invention can be applied to the area around the driver's seat of an automobile, which is a moving object.

[0552] Fig. 36A is a diagram illustrating the area around the windshield in the interior of a vehicle, showing display panels 9001a, 9001b, and 9001c attached to the dashboard, and a display panel 9001d attached to a pillar.

[0553] The display panels 9001a to 9001c can provide various information by displaying navigation information, a speedometer, a tachometer, mileage, a fuel gauge, gear status, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, thereby improving the design. The display panels 9001a to 9001c can also be used as lighting devices.

[0554] The display panel 9001d can display an image from an imaging device installed on the vehicle body to complement the view blocked by the pillar (blind spot). In other words, by displaying an image from an imaging device installed on the outside of the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety confirmation can be performed more naturally and without discomfort. The display panel 9001d can also be used as a lighting device.

[0555] FIG. 36B is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0556] The mobile information terminal 9200 shown in Figure 36B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0557] 36C is a perspective view of a foldable portable information terminal 9201. The portable information terminal 9201 includes a housing 9000a, a housing 9000b, a display portion 9001, and an operation button 9056.

[0558] The housing 9000a and the housing 9000b are joined by a hinge 9055, and the hinge 9055 allows the device to be folded in half.

[0559] A display portion 9001 included in the portable information terminal 9201 is supported by two housings (a housing 9000 a and a housing 9000 b ) connected by a hinge 9055 .

[0560] 36D to 36F are perspective views showing a foldable portable information terminal 9202. Fig. 36D is a perspective view of the portable information terminal 9202 in an unfolded state, Fig. 36F is a perspective view of the portable information terminal 9202 in a folded state, and Fig. 36E is a perspective view of the portable information terminal 9202 in a state in which it is changing from one of Fig. 36D and Fig. 36F to the other. In this way, the portable information terminal 9202 can be folded into three.

[0561] A display portion 9001 of the portable information terminal 9202 is supported by three housings 9000 connected by hinges 9055 .

[0562] 36C to 36F, the display device of one embodiment of the present invention can be applied to the display portion 9001. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm to 150 mm.

[0563] The portable information terminals 9201 and 9202 are each highly portable when folded, and have a seamless, wide display area when unfolded, allowing for excellent display visibility.

[0564] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0565] This embodiment mode can be combined with other embodiment modes as appropriate.

[0566] 10A_1: transistor, 10A_2: transistor, 10B_1: transistor, 10B_2: transistor, 10C_1: transistor, 10C_2: transistor, 10C_3: transistor, 10C_4: transistor, 10D_1: transistor, 10D_2: transistor, 10D_3: transistor, 10D_4: transistor, 10E_1: transistor, 10E_2: transistor, 10F_1: transistor, 10F_2: transistor, 10G_1: transistor, 10G_2: transistor, 11: circuit, 12: circuit, 2 0: sequential circuit, 20_1: sequential circuit, 20_2: sequential circuit, 20_3: sequential circuit, 20_4: sequential circuit, 20_5: sequential circuit, 20_6: sequential circuit, 20A: sequential circuit, 20B: sequential circuit, 20C: sequential circuit, 20D: sequential circuit, 30: driver circuit, 100A: semiconductor device, 100B: semiconductor device, 100C: semiconductor device, 100D: semiconductor device, 100E: semiconductor device, 100F: semiconductor device, 100G: semiconductor device, 102: substrate, 104: conductive layer, 106: insulating layer, 108: semiconductor layer, 110_1: insulating layer, 110_2: insulating layer, 110_3: insulating layer, 110_4: insulating layer, 110a1: insulating layer, 110a1f: insulating film, 110a2: insulating layer, 110a2f: insulating film, 110a3: insulating layer, 110a4: insulating layer, 110b1: insulating layer, 110b1f: insulating film, 110b2: insulating layer, 110b2f: insulating film, 110b3: insulating layer, 110b4: insulating layer, 110c1: insulating layer, 110c1f: insulating film, 110c2: insulating layer, 110c2f: insulating film, 110c3: insulating layer, 110c4: insulating layer, 110d1: insulating layer, 110d2: insulating layer, 110e1: insulating layer, 110e2: insulating layer, 110f1: insulating layer, 110f2: insulating layer, 110g1: insulating layer, 110g2: insulating layer, 110h1: insulating layer, 110h2: insulating layer, 110i1: insulating layer, 110i2: insulating layer, 110s: insulating layer, 112a: conductive layer, 112b: conductive layer, 112be: conductive layer, 112bf: conductive film, 112c: conductive layer, 112ce: conductive layer, 112cf: conductive film, 112d: conductive layer, 112e: conductive layer, 114_1: conductive layer, 114_2: conductive layer, 143: opening, 144: opening, 145: opening, 195: insulating layer, 700A: electronic device, 700B: electronic device, 721: housing, 723: mounting portion,727: earphone unit, 750: earphone, 751: display panel, 753: optical member, 756: display area, 757: frame, 758: nose pad, 800A: electronic device, 800B: electronic device, 820: display unit, 821: housing, 822: communication unit, 823: wearing unit, 824: control unit, 825: imaging unit, 827: earphone unit, 832: lens, 6500: electronic device, 6501: housing, 6502: display part, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display part, 7100: television device, 7101: housing, 7103 : Stand, 7111: Remote control device, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Housing, 9000 a: housing, 9000b: housing, 9001: display unit, 9001a: display panel, 9001b: display panel, 9001c: display panel, 9001d: display panel, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor, 9008: microphone, 9055: hinge, 9056: operation button, 9200: mobile information terminal, 9201: mobile information terminal, 9202: mobile information terminal,

Claims

a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a third insulating layer; the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer are superimposed in this order; the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have an opening reaching the first conductive layer; In the opening, the semiconductor layer is in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, and a side surface of the third conductive layer; the third insulating layer is in contact with an upper surface of the semiconductor layer; the fourth conductive layer overlaps the opening and is in contact with an upper surface of the third insulating layer; Semiconductor device. 　 In claim 1, the semiconductor layer comprises a metal oxide; At least one of the first insulating layer and the second insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 2, The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; Semiconductor device. 　 In claim 2, the first insulating layer includes a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer; the second insulating layer includes a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer; the fourth insulating layer, the sixth insulating layer, the seventh insulating layer, and the ninth insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The fifth insulating layer and the eighth insulating layer each include silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 1 or 2, a tenth insulating layer on the fourth conductive layer, the tenth insulating layer having a region overlapping the opening; The tenth insulating layer has one or both of an organic insulating material and an inorganic insulating material. Semiconductor device. 　 In claim 5, The tenth insulating layer includes one or more selected from an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimideamide resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, and precursors of these resins. Semiconductor device. 　 In claim 1 or 2, an upper surface of the fourth conductive layer is located above an upper end of a side surface of the second conductive layer facing the opening; Semiconductor device. 　 a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer; the first conductive layer, the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, the fourth insulating layer, and the fifth conductive layer are superimposed in this order; the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, the fourth insulating layer, and the fifth conductive layer have an opening reaching the first conductive layer; in the opening, the fifth insulating layer is in contact with a part of an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, a side surface of the second insulating layer, a side surface of the third conductive layer, a side surface of the third insulating layer, a side surface of the fourth conductive layer, a side surface of the fourth insulating layer, and a side surface of the fifth conductive layer; In the opening, the semiconductor layer is in contact with another part of the top surface of the first conductive layer and a side surface of the fifth insulating layer; the sixth insulating layer is in contact with an upper surface of the semiconductor layer; the sixth conductive layer overlaps the opening and contacts an upper surface of the sixth insulating layer; Semiconductor device. 　 In claim 8, the semiconductor layer comprises a metal oxide; At least one of the first insulating layer and the second insulating layer comprises silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 9, The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium; Semiconductor device. 　 In claim 9, the first insulating layer includes a seventh insulating layer, an eighth insulating layer on the seventh insulating layer, and a ninth insulating layer on the eighth insulating layer; the second insulating layer includes a tenth insulating layer, an eleventh insulating layer on the tenth insulating layer, and a twelfth insulating layer on the eleventh insulating layer; the third insulating layer includes a thirteenth insulating layer, a fourteenth insulating layer on the thirteenth insulating layer, and a fifteenth insulating layer on the fourteenth insulating layer; the fourth insulating layer includes a sixteenth insulating layer, a seventeenth insulating layer on the sixteenth insulating layer, and an eighteenth insulating layer on the seventeenth insulating layer; the seventh insulating layer, the ninth insulating layer, the tenth insulating layer, the twelfth insulating layer, the thirteenth insulating layer, the fifteenth insulating layer, the sixteenth insulating layer, and the eighteenth insulating layer each include silicon nitride, silicon oxynitride, hafnium oxide, or aluminum oxide; The eighth insulating layer, the eleventh insulating layer, the fourteenth insulating layer, and the seventeenth insulating layer each include silicon oxide or silicon oxynitride. Semiconductor device. 　 forming a first conductive layer, a first insulating film, a second conductive layer, a second insulating film, and a third conductive layer in this order; removing a portion of each of the first insulating film, the second conductive layer, the second insulating film, and the third conductive layer to form an opening reaching the first conductive layer, and forming a first insulating layer, a fourth conductive layer, a second insulating layer, and a fifth conductive layer; forming a semiconductor layer in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the fourth conductive layer, a side surface of the second insulating layer, and a side surface of the fifth conductive layer in the opening; forming a third insulating layer in contact with an upper surface of the semiconductor layer; forming a sixth conductive layer on the third insulating layer so as to overlap the opening; A method for manufacturing a semiconductor device.

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