Display device and method for manufacturing same

Abstract

A display device (50a) comprises: a lower wiring layer (LW); an interlayer insulating film (IL) that covers the lower wiring layer (LW); an upper wiring layer (UW); a planarization film (TH) that covers the upper wiring layer (UW); frame wiring (18h) that is in the same layer as the upper wiring layer (UW) and that is formed from the same material as the upper wiring layer (UW); and a frame-shaped slit (S) that is formed in the planarization film (TH) of a frame region (F). In the region where the slit (S) is formed, there is provided a connection wiring (16a) that is formed in the same layer as the lower wiring layer (LW) and that is formed from the same material as the lower wiring layer (LW). The frame wiring (18h) that is provided closer to a display region (D) side than the slit (S) is connected to the connection wiring (16a) via a contact hole (H17a) that is formed in the interlayer insulating film (IL).

Description

Display device and manufacturing method thereof

[0001] The present invention relates to a display device and a manufacturing method thereof.

[0002] In recent years, self-luminous organic electroluminescence (EL) display devices using organic electroluminescence (EL) elements have been attracting attention as a display device alternative to liquid crystal display devices. In organic EL display devices, a decrease in reliability due to moisture is a significant issue. Therefore, in order to prevent deterioration of the organic EL elements due to moisture penetration, a sealing structure has been proposed for organic EL display devices, in which a sealing film (Thin Film Encapsulation, hereinafter also referred to as a "TFE film") covering a display area (active area) where the organic EL elements are provided is composed of a laminated film of an inorganic film and an organic film. In this sealing structure, when the organic film in the TFE film is formed by an inkjet method, a wall (bank) must be provided in the frame area surrounding the display area to block the ink that will become the organic film.

[0003] For example, Patent Document 1 proposes a display device having a two-circumference bank structure consisting of a frame-shaped first damming wall and a second damming wall in the frame region.

[0004] International Publication No. 2019 / 187121

[0005] In organic EL display devices having the bank structure, in order to prevent moisture penetration and transmission through the planarization film that forms a flat surface in the display area, slits are formed in the planarization film between the banks and around the banks in the frame area, and the planarization film is partially absent. In this structure, in the slits where the planarization film is absent, the wiring provided below the planarization film (frame wiring provided in the frame area) is exposed and bare. Therefore, if the frame wiring is damaged, for example, by an etching solution used to form the first electrode of the organic EL element during the organic EL element formation process, the end face (cross section) of the frame wiring may shift sideways or become distorted due to the adhesion of foreign matter. In this case, the sealing performance of the TFE film formed on the frame wiring may be reduced during the subsequent TFE film formation process, resulting in moisture penetration and deterioration of the organic EL element, i.e., reduced reliability of the organic EL display device.

[0006] In the display device of Patent Document 1, to address the above-mentioned inconvenience, a conductive layer formed of the same material as each first electrode is provided in the same layer to cover at least the end faces of the frame wiring exposed from the slits, but there is room for improvement in order to suppress damage to the frame wiring during the manufacturing process.

[0007] The present invention has been made in view of the above points, and an object of the present invention is to prevent the frame wiring from being damaged in the manufacturing process that follows the formation of the frame wiring.

[0008] In order to achieve the above object, a display device according to the present invention includes a base substrate, a thin film transistor layer provided on the base substrate, the thin film transistor layer including a lower wiring layer, an interlayer insulating film provided so as to cover the lower wiring layer, an upper wiring layer provided on the interlayer insulating film, and a planarizing film provided so as to cover the upper wiring layer, a light emitting element layer provided on the thin film transistor layer and constituting a display area, a frame area provided around the display area, a terminal section provided at one end of the frame area, a plurality of frame wires formed in the same layer as the upper wiring layer and made of the same material as the upper wiring layer so as to be routed from the display area to the frame area and extend toward the terminal section, and A display device comprising a frame-shaped slit formed in the planarization film in the frame region, wherein in the frame region on the terminal portion side, the plurality of frame wirings are arranged closer to the display region than the slits, and in the region where the slits are formed, a plurality of connecting wirings formed in the same layer and made of the same material as the lower wiring layer are arranged along the direction in which the plurality of frame wirings extend, and a plurality of contact holes are formed in the interlayer insulating film and electrically connect the plurality of frame wirings to the plurality of connecting wirings, respectively, and the plurality of frame wirings are respectively reconnected to the plurality of connecting wirings via the plurality of contact holes.

[0009] A method for manufacturing a display device according to the present invention includes a base substrate, a thin film transistor layer provided on the base substrate and including a lower wiring layer, an interlayer insulating film provided so as to cover the lower wiring layer, an upper wiring layer provided on the interlayer insulating film, and a planarizing film provided so as to cover the upper wiring layer, a light emitting element layer provided on the thin film transistor layer and constituting a display area, a frame area provided around the display area, a terminal portion provided at one end of the frame area, a plurality of frame wires formed in the same layer and made of the same material as the upper wiring layer so as to be routed from the display area to the frame area and extend toward the terminal portion, and a frame-shaped slit formed in the planarizing film in the frame area. A method for manufacturing a display device, characterized in that in a thin film transistor layer formation process for forming the thin film transistor layer, in the frame region on the terminal portion side, in an area where the slits are formed, a plurality of connecting wires are formed in the same layer using the same material as the lower wiring layer along the direction in which the plurality of frame wires extend, the interlayer insulating film is formed to cover the plurality of connecting wires, a plurality of contact holes are formed in the interlayer insulating film to electrically connect the plurality of frame wires to the plurality of connecting wires, respectively, and the plurality of frame wires are formed on the display region side of the slits, thereby reconnecting the plurality of frame wires to the plurality of connecting wires via the plurality of contact holes.

[0010] According to the present invention, it is possible to prevent the frame wiring from being damaged in the manufacturing process that follows the formation of the frame wiring.

[0011] FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention. FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view of an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 6 is an enlarged plan view of a main portion of region A in FIG. 1 showing the wiring structure of the frame region on the terminal side of the organic EL display device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 6 showing the wiring structure of the frame region on the terminal side of the organic EL display device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6 showing the wiring structure of the frame region on the terminal side of the organic EL display device according to the first embodiment of the present invention. FIG. 9 is an enlarged plan view of a main portion of region A in FIG. 1 showing the wiring structure of the frame region on the terminal side of the organic EL display device according to a second embodiment of the present invention, and corresponds to FIG. 6 . 10 is a cross-sectional view taken along line XX in FIG. 9, showing the wiring structure in the frame region on the terminal portion side of the organic EL display device according to the second embodiment of the present invention, and corresponds to FIG.

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0013] First Embodiment FIGS. 1 to 8 illustrate a first embodiment of a display device according to the present invention. In the following embodiments, an organic EL display device including organic EL elements will be exemplified as a display device including light-emitting elements. FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50a according to this embodiment. FIG. 2 is a plan view of a display region D of the organic EL display device 50a. FIG. 3 is a cross-sectional view of the display region D of the organic EL display device 50a. FIG. 4 is an equivalent circuit diagram of a TFT layer 20 constituting the organic EL display device 50a. FIG. 5 is a cross-sectional view of an organic EL layer 33 constituting the organic EL display device 50a. FIG. 6 is an enlarged plan view of a main portion of region A in FIG. 1, showing the wiring structure of the frame region F on the terminal portion T side of the organic EL display device 50a. FIG. 5 is a cross-sectional view taken along line VII-VII in FIG. 6, showing the wiring structure of the frame region F on the terminal portion T side of the organic EL display device 50a. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6, showing the wiring structure of the frame region F on the terminal portion T side of the organic EL display device 50a. 6, the sealing film 40 is omitted. In FIGS. 7 and 8, the first inorganic sealing film 41 and the second inorganic sealing film 43 that constitute the sealing film 40 are omitted.

[0014] 1 , the organic EL display device 50a includes, for example, a rectangular display area D for displaying an image, and a frame area F surrounding the display area D. While the rectangular display area D is illustrated in the present embodiment, the rectangular shape also includes a substantially rectangular shape, such as a shape with arc-shaped sides, a shape with arc-shaped corners, or a shape with a notch in one side. The organic EL display device 50a has a first direction X parallel to the substrate surface of a resin substrate 10 (described later), a second direction Y perpendicular to the first direction X and parallel to the substrate surface, and a third direction Z perpendicular to the first direction X and the second direction Y (see FIGS. 7 and 8 ).

[0015] In the display region D, a plurality of sub-pixels P are arranged in a matrix, as shown in Fig. 2. In the display region D, for example, a sub-pixel P having a red light-emitting region Lr for displaying red, a sub-pixel P having a green light-emitting region Lg for displaying green, and a sub-pixel P having a blue light-emitting region Lb for displaying blue are arranged adjacent to one another, as shown in Fig. 2. In the display region D, one pixel is formed by, for example, three adjacent sub-pixels P each having a red light-emitting region Lr, a green light-emitting region Lg, and a blue light-emitting region Lb. The arrangement of the sub-pixels P is not particularly limited, and examples thereof include a pentatile arrangement and a stripe arrangement.

[0016] Terminal portions T are provided at one end (the lower end in FIG. 1 ) of the frame region F so as to extend in one direction (first direction X, the horizontal direction in FIG. 1 ). Also, as shown in FIG. 1 , in the frame region F, a frame-shaped slit S is formed in a planarization film 19 (described later) so as to surround the display region D. Note that, in the frame region F between the display region D and the terminal portions T, a folding portion (not shown) that can be folded, for example, 180° (in a U-shape) with the first direction X as the folding axis may be provided so as to extend in one direction (first direction X).

[0017] As shown in FIG. 3 , the organic EL display device 50 a includes a resin substrate 10 provided as a base substrate, a thin film transistor (hereinafter also referred to as “TFT”) layer 20 provided on the resin substrate 10, an organic EL element layer 30 provided as a light-emitting element layer constituting a display region D, and a sealing film 40 provided on the organic EL element layer 30 (hereinafter, the sealing film 40 provided on the display region D will also be referred to as “sealing film 40 d”).

[0018] The resin substrate 10 is made of, for example, polyimide resin.

[0019] As shown in FIG. 3, the TFT layer 20 includes a base coat film 11 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 11 for each subpixel P, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. 3, the TFT layer 20 includes a base coat film 11, semiconductor layers 12a and 12b, a gate insulating film 13, a first wiring layer including gate lines 14 (see FIG. 2), gate electrodes 14a and 14b, and a lower conductive layer 14c, a first interlayer insulating film 15, a second wiring layer including upper conductive layer 16, a second interlayer insulating film 17, a third wiring layer including source lines 18f (see FIG. 2), source electrodes 18a and 18c, drain electrodes 18b and 18d, and a power line 18g, and a planarization film 19, which are stacked in this order on a resin substrate 10. Also, as shown in FIGS. 2 and 4, the TFT layer 20 includes a plurality of gate lines 14 extending parallel to one another in the horizontal direction in the drawings. Also, as shown in FIGS. 2 and 4, the TFT layer 20 includes a plurality of source lines 18f extending parallel to one another in a direction intersecting (orthogonal to) the plurality of gate lines 14, i.e., in the vertical direction in the drawings. 2 and 4, the TFT layer 20 is provided with a plurality of power supply lines 18g extending parallel to one another in the vertical direction in the drawings. Each power supply line 18g is provided adjacent to a corresponding source line 18f, as shown in Fig. 2. Furthermore, in the TFT layer 20, a first TFT 9a, a second TFT 9b, and a capacitor 9c are provided in each sub-pixel P, as shown in Fig. 4.

[0020] The base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 may be made of, for example, silicon nitride (SiNx (x is a positive number)), silicon oxide (SiO ２The semiconductor layers 12a and 12b are composed of a single layer or a stacked layer of an inorganic insulating film such as silicon oxynitride (SiON). The semiconductor layers 12a and 12b are composed of, for example, a low-temperature polysilicon film or an In—Ga—Zn—O-based oxide semiconductor film. The first wiring layer, the second wiring layer, and the third wiring layer are composed of, for example, a metal single layer film of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), or the like, or a metal stacked layer film such as Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, or Cu / Ti. The second wiring layer and the third wiring layer are preferably composed of a metal stacked layer film such as Ti / Al / Ti.

[0021] The first TFT 9a and the second TFT 9b are p-type TFTs in which semiconductor layers 12a and 12b (described later) are doped with impurities such as boron.

[0022] As shown in FIG. 4 , the first TFT 9a is electrically connected to the corresponding gate line 14 and source line 18f in each subpixel P. As shown in FIG. 3 , the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18a, and a drain electrode 18b, which are sequentially disposed on a base coat film 11. As shown in FIG. 3 , the semiconductor layer 12a is disposed on the base coat film 11 in an island shape and has, for example, a channel region, a source region, and a drain region. As shown in FIG. 3 , the gate insulating film 13 is disposed so as to cover the semiconductor layer 12a. As shown in FIG. 3 , the gate electrode 14a is disposed on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12a. As shown in FIG. 3 , the first interlayer insulating film 15 and the second interlayer insulating film 17 are disposed so as to cover the gate electrode 14a. 3, the source electrode 18a and the drain electrode 18b are provided spaced apart from each other on the second interlayer insulating film 17. The source electrode 18a and the drain electrode 18b are electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively, through contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.

[0023] As shown in FIG. 4 , the second TFT 9b is electrically connected to the corresponding first TFT 9a and power line 18g in each subpixel P. As shown in FIG. 3 , the second TFT 9b includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18c, and a drain electrode 18d, which are sequentially disposed on a base coat film 11. As shown in FIG. 3 , the semiconductor layer 12b is disposed on the base coat film 11 in an island shape and has, for example, a channel region, a source region, and a drain region. As shown in FIG. 3 , the gate insulating film 13 is disposed so as to cover the semiconductor layer 12b. As shown in FIG. 3 , the gate electrode 14b is disposed on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12b. As shown in FIG. 3 , the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed so as to cover the gate electrode 14b. 3, the source electrode 18c and the drain electrode 18d are provided spaced apart from each other on the second interlayer insulating film 17. The source electrode 18c and the drain electrode 18d are electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively, through contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17.

[0024] In this embodiment, the first TFT 9a and the second TFT 9b are top-gate type TFTs, but the first TFT 9a and the second TFT 9b may be bottom-gate type TFTs.

[0025] As shown in Fig. 4, the capacitor 9c is electrically connected to the corresponding first TFT 9a and power supply line 18g in each subpixel P. Here, as shown in Fig. 3, the capacitor 9c includes a lower conductive layer 14c formed in the same layer and made of the same material as the gate electrodes 14a and 14b, a first interlayer insulating film 15 provided so as to cover the lower conductive layer 14c, and an upper conductive layer 16 provided on the first interlayer insulating film 15 so as to overlap the lower conductive layer 14c. Note that the upper conductive layer 16 is electrically connected to the power supply line 18g via a contact hole formed in a second interlayer insulating film 17, as shown in Fig. 3.

[0026] The planarization film 19 (hereinafter also referred to as the "first planarization film 19") has a flat surface in the display area D and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0027] As shown in FIG. 3, the organic EL element layer 30 includes a plurality of organic EL elements 35 as a plurality of light-emitting elements arranged in a matrix corresponding to a plurality of sub-pixels P.

[0028] 3, the organic EL element 35 includes a plurality of first electrodes 31 provided in order on the first planarization film 19, a plurality of organic EL layers 33 provided on the first electrodes 31 in respective sub-pixels P, and a second electrode 34 provided on the organic EL layer 33 in common to the plurality of sub-pixels P. In addition, as shown in FIG. 3, the organic EL element 35 is covered with a sealing film 40d.

[0029] 3, the first electrodes 31 are provided in a matrix on the first planarization film 19 so as to correspond to the plurality of sub-pixels P. Also, as shown in FIG. 3, each first electrode 31 is electrically connected to the drain electrode 18d (or source electrode 18c) of each second TFT 9b via a contact hole formed in the first planarization film 19. Also, the first electrode 31 has a function of injecting holes (positive holes) into the organic EL layer 33. Also, it is more preferable that the first electrode 31 be formed of a material with a large work function in order to improve the efficiency of hole injection into the organic EL layer 33. Here, examples of materials constituting the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Examples of materials constituting the first electrode 31 include astatine (At) / astatine oxide (AtO ２The first electrode 31 may be made of an alloy of tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), or another conductive oxide. The first electrode 31 may be formed by stacking multiple layers made of the above materials. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0030] The peripheral edge of the first electrode 31 is covered with an edge cover 32 provided in a lattice pattern and shared by multiple sub-pixels P. Examples of materials that form the edge cover 32 include positive photosensitive resin materials such as polyimide resin, acrylic resin, polysiloxane resin, and novolac resin, as well as polysiloxane-based SOG materials. As shown in FIG. 3 , a portion of the surface of the edge cover 32 protrudes upward in the drawing to form island-shaped pixel photospacers.

[0031] 3, the organic EL layer 33 is disposed on each first electrode 31, and is provided in a matrix so as to correspond to a plurality of sub-pixels P. Here, each organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are provided in this order on the first electrode 31, as shown in FIG.

[0032] The hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer to each other, thereby improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0033] The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0034] The light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and where the holes and electrons recombine when a voltage is applied between the first electrode 31 and the second electrode 34. The light-emitting layer 3 is made of a material with high luminous efficiency. Examples of materials that can be used for the light-emitting layer 3 include metal oxinoid compounds (8-hydroxyquinoline metal complexes), naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzthiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, and polysilane.

[0035] The electron transport layer 4 has a function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.

[0036] The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 closer to each other and improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33, and this function can reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Here, examples of materials constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF ２ ), calcium fluoride (CaF ２ ), strontium fluoride (SrF ２ ), barium fluoride (BaF ２ inorganic alkali compounds such as aluminum oxide (Al ２ O ３ ), strontium oxide (SrO), etc.

[0037] 3 , the second electrode 34 is provided to cover each organic EL layer 33 and the edge cover 32. The second electrode 34 has a function of injecting electrons into the organic EL layer 33. The second electrode 34 is preferably made of a material with a small work function to improve the efficiency of electron injection into the organic EL layer 33. Examples of materials that can be used for the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). The second electrode 34 may be made of, for example, magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), or astatine (At) / astatine oxide (AtO ２ The second electrode 34 may be formed of an alloy such as lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The second electrode 34 may be formed by stacking multiple layers made of the above materials. Examples of materials with a low work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0038] 3, the sealing film 40d (TFE film) is provided on the organic EL element layer 30 so as to cover each organic EL element 35. As shown in FIG. 3, the sealing film 40d includes a first inorganic sealing film 41 provided so as to cover the second electrode 34, an organic sealing film 42 provided on the first inorganic sealing film 41, and a second inorganic sealing film 43 provided so as to cover the organic sealing film 42, and has a function of protecting the organic EL layer 33 from moisture, oxygen, etc. The first inorganic sealing film 41 and the second inorganic sealing film 43 are made of, for example, silicon oxide (SiO ２ ) and aluminum oxide (Al ２ O ３ ), trisilicon tetranitride (Si ３ N ４ The organic sealing film 42 is made of an inorganic material such as silicon nitride (SiNx (x is a positive number)) or silicon carbonitride (SiCN). The organic sealing film 42 is made of an organic material such as acrylic resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.

[0039] 1 and 6 to 8, the organic EL display device 50a includes, in a frame region F, a resin substrate 10; an inorganic insulating laminate film provided on the resin substrate 10; a plurality of frame wirings 18h, 18i (upper wiring layer UW) provided on the inorganic insulating laminate film; first planarization films 19, 19c (planarization film TH), a first damming wall Wa, and a second damming wall Wb provided on the plurality of frame wirings 18h, 18i and the inorganic insulating laminate film; and a sealing film 40 provided on the first planarization film 19, the first damming wall Wa, and the second damming wall Wb (hereinafter, the sealing film 40 provided on the frame region F will also be referred to as "sealing film 40f").

[0040] As shown in FIGS. 7 and 8, the inorganic insulating laminated film is composed of a base coat film 11, a gate insulating film 13, a first interlayer insulating film 15, and a second interlayer insulating film 17 (interlayer insulating film IL) which constitute a TFT layer 20.

[0041] The frame wiring 18h (upper wiring layer UW) refers to wiring routed from the display region D to the frame region F. As shown in FIGS. 1 and 6 , in the frame region F on the terminal portion T side, a plurality of frame wirings 18h are provided so as to extend in the second direction Y from the display region D toward the terminal portion T. The frame wirings 18h (their terminal portion T-side ends) are provided inside (on the display region D side) frame-shaped slits S (first slits Sa described later). The frame wirings 18h are provided up to just before the first slits Sa. In other words, the frame wirings 18h are not provided so as to reach the terminal portion T, but are cut off just before the first slits Sa and separated from the frame wirings 18i. Therefore, as shown in FIG. 7 , the frame wirings 18h are covered by the first planarization film 19 on the display region D side and are not exposed (bare) from the slits S (first slits Sa). 7, the frame wiring 18h is provided on the second interlayer insulating film 17 (interlayer insulating film IL) constituting the uppermost layer of the inorganic insulating laminate film. Therefore, the frame wiring 18h is formed in the same layer and made of the same material as the third wiring layer (source lines 18f, source electrodes 18a and 18c, drain electrodes 18b and 18d, power supply lines 18g, etc.) provided in the TFT layer 20 constituting the display region D. The frame wiring 18h routed from the third wiring layer is preferably formed of a metal laminate film such as Ti / Al / Ti.

[0042] As shown in FIG. 6 , the frame wiring 18i (upper wiring layer UW) is a wiring separated from the frame wiring 18h by the width of the slit S (length in the second direction Y) in the frame region F on the terminal portion T side, and is provided so as to reach the terminal portion T. Therefore, the frame wiring 18i is covered with the first planarization film 19c (planarization film TH) on the side opposite the display region D (the terminal portion T side) and is not exposed from the slit S (the third slit Sc described later). A plurality of frame wirings 18i are provided so as to extend in the second direction Y toward the terminal portion T in correspondence with the plurality of frame wirings 18h. The terminal portion T-side end of the frame wiring 18i is electrically connected to each terminal arranged in the terminal portion T. Also, as shown in FIG. 7 , the frame wiring 18i, like the frame wiring 18h, is provided on the second interlayer insulating film 17 (interlayer insulating film IL). Therefore, like the frame wiring 18h, the frame wiring 18i is formed in the same layer as the third wiring layer using the same material. The frame wiring 18i is preferably formed of a metal laminate film such as Ti / Al / Ti.

[0043] 6 and 7, the frame wirings 18h and 18i are not provided inside the slit S. The inside of the slit S refers to the area (within the frame of the slit S) between the first slit Sa, the first damming wall Wa, the second slit Sb (described later), the second damming wall Wb, and the third slit Sc, as shown in FIGS. 1 and 6. In other words, the frame wirings 18h and 18i do not overlap with the slit S in a plan view. The frame wirings 18h and 18i may be power supply wiring such as ELVDD or ELVSS, or may be other signal wiring.

[0044] As shown in FIGS. 6 and 7, the first planarization film 19 (planarization film TH) is separated into frame-shaped first planarization films 19a, 19b, and 19c by frame-shaped slits S in the frame region F.

[0045] As shown in FIGS. 6 to 8 , the slits S are formed so as to expose at least a portion of the second interlayer insulating film 17 (interlayer insulating film IL), which is an underlying layer of the first planarization film 19. The slits S include a frame-shaped first slit Sa arranged between the first planarization film 19 on the display region D side and the first damming wall Wa, a frame-shaped second slit Sb arranged between the first damming wall Wa and the second damming wall Wb, and a frame-shaped third slit Sc arranged between the second damming wall Wb and the first planarization film 19c. As shown in FIGS. 6 and 7 , the first slit Sa separates the first planarization film 19a from the first planarization film 19 on the display region D side. The second slit Sb separates the first planarization film 19b from the first planarization film 19a. The third slit Sc separates the first planarization film 19c from the first planarization film 19b.

[0046] 6 and 7 , the first damming wall Wa is provided in a frame shape on the display region D side inside the slit S and is configured to suppress the spread of the organic sealing film 42 of the sealing film 40f. Specifically, the first damming wall Wa is provided along the frame-shaped first slit Sa so as to surround the first planarization film 19 on the display region D side. Also, as shown in FIG. 7 , the first damming wall Wa is composed of a first planarization film 19a formed in the same layer and made of the same material as the first planarization film 19, and a second planarization film 32a provided on the first planarization film 19a and formed in the same layer and made of the same material as the edge cover 32.

[0047] 6 and 7, the second damming wall Wb is provided in a frame shape so as to surround the first damming wall Wa inside the slit S and is configured to suppress the spread of the organic sealing film 42 of the sealing film 40f. Specifically, the second damming wall Wb is provided along the frame-shaped second slit Sb. Also, as shown in FIG. 7, the second damming wall Wb is composed of a first planarization film 19b formed in the same layer as the first planarization film 19 and made of the same material as the edge cover 32, and a second planarization film 32b provided on the first planarization film 19b and made of the same material as the edge cover 32.

[0048] The sealing film 40f is configured as a laminated film formed in the same layer and made of the same material as the first inorganic sealing film 41, the organic sealing film 42, and the second inorganic sealing film 43 that constitute the sealing film 40d. As shown in Fig. 7, the organic sealing film 42 of the sealing film 40f may reach the upper surface of the second damming wall Wb. In other words, in the outer (terminal portion T side) region of the upper surface of the second damming wall Wb, the sealing film 40f may be configured as an inorganic laminated film (not shown) formed in the same layer and made of the same material as the first inorganic sealing film 41 and the second inorganic sealing film 43 that constitute the sealing film 40d.

[0049] Here, in the organic EL display device 50a of this embodiment, as shown in Figures 1 and 6 to 8, in the frame region F on the terminal portion T side, a connecting wiring 16a (lower wiring layer LW) is provided that connects (connects) the frame wiring 18h (its end on the terminal portion T side) and the frame wiring 18i (its end on the display region D side) in the second direction Y.

[0050] 1, 6, and 7, a plurality of connecting wires 16a (lower wiring layer LW) are provided corresponding to the plurality of frame wires 18h, 18i so as to extend in the direction in which the frame wires 18h, 18i extend (i.e., the second direction Y). The connecting wires 16a are provided in an area in which the slits S are formed. In other words, the connecting wires 16a overlap with the slits S (all of the first slits Sa, the second slits Sb, and the third slits Sc) in a planar view. Both ends of the connecting wires 16a in the second direction Y overlap with the end of the frame wire 18h on the terminal portion T side and the end of the frame wire 18i on the display area D side in a planar view, respectively.

[0051] As shown in FIGS. 7 and 8 , the connecting wires 16a are provided on the first interlayer insulating film 15 constituting the inorganic insulating laminate film. Therefore, the connecting wires 16a are formed in the same layer and made of the same material as the second wiring layer (e.g., upper conductive layer 16) provided in the TFT layer 20 constituting the display region D. The wiring layer constituting the connecting wires 16a is not limited to the second wiring layer, and may be formed in the same layer and made of the same material as the first wiring layer (e.g., gate lines 14, gate electrodes 14a and 14b, lower conductive layer 14c). The following describes an example of a wiring structure in which the connecting wires 16a are formed in the same layer and made of the same material as the second wiring layer. The connecting wires 16a are preferably formed of a metal laminate film such as Ti / Al / Ti. The connecting wires 16a are also covered with a second interlayer insulating film 17 (interlayer insulating film IL). 6 and 7, the second interlayer insulating film 17 is exposed from the slits S (all of the first slit Sa, the second slit Sb, and the third slit Sc), while the connecting wire 16a is not exposed. In other words, the connecting wire 16a is interposed between the first interlayer insulating film 15 and the second interlayer insulating film 17.

[0052] As shown in FIGS. 1 , 6 , and 7 , the connecting wires 16a (their end portions on the display region D side) are electrically connected to the frame wires 18h (their end portions on the terminal portion T side) via contact holes H17a. The contact holes H17a are portions (contact portions) that connect the connecting wires 16a and the frame wires 18h. The contact holes H17a are formed in the second interlayer insulating film 17 so as to penetrate the second interlayer insulating film 17. The contact holes H17a are formed for each connecting wire 16a so as to expose at least a portion of the end portions of the connecting wires 16a on the display region D side. Furthermore, as shown in FIGS. 6 and 7 , the contact holes H17a overlap the first planarization film 19 (planarization film TH) on the display region D side in a planar view. In other words, the contact holes H17a are covered by the first planarization film 19 on the display region D side.

[0053] On the other hand, as shown in FIGS. 6 and 7 , the connecting wire 16a (its end on the terminal portion T side) is electrically connected to the frame wire 18i (its end on the display area D side) via a contact hole H17b. The contact hole H17b is a portion (contact portion) that connects the connecting wire 16a and the frame wire 18i. The contact hole H17b is formed in the second interlayer insulating film 17 so as to penetrate the second interlayer insulating film 17. The contact hole H17b is formed for each connecting wire 16a so as to expose at least a portion of the end of the connecting wire 16a on the terminal portion T side. Also, as shown in FIGS. 6 and 7 , the contact hole H17b overlaps with the first planarization film 19c (planarization film TH) on the terminal portion T side in a planar view. In other words, the contact hole H17b is covered by the first planarization film 19c on the terminal portion T side.

[0054] In this way, in the organic EL display device 50a, in the region (inside the slit S) where the slit S is formed in the first planarization film 19 (planarization film TH) in the frame region F on the terminal portion T side, the frame wiring 18h (third wiring layer, upper wiring layer UW) routed from the display region D is reconnected to the connecting wiring 16a (second wiring layer or first wiring layer, lower wiring layer LW) located below the frame wiring 18h and the second interlayer insulating film 17 (interlayer insulating film IL).

[0055] The organic EL display device 50a described above is configured such that, in each subpixel P, a gate signal is input to the first TFT 9a via the gate line 14 to turn the first TFT 9a on, a data signal is written to the gate electrode 14b and capacitor 9c of the second TFT 9b via the source line 18f, and a current from the power supply line 18g corresponding to the gate voltage of the second TFT 9b is supplied to the organic EL layer 33, causing the light-emitting layer 3 of the organic EL layer 33 to emit light, thereby displaying an image. In the organic EL display device 50a, even if the first TFT 9a is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c, so that light emission by the light-emitting layer 3 is maintained until a gate signal for the next frame is input.

[0056] Next, a method for manufacturing the organic EL display device 50a of this embodiment will be described. The method for manufacturing the organic EL display device 50a of this embodiment includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step.

[0057] <TFT layer formation process> For example, a base coat film 11, a first TFT 9 a, a second TFT 9 b, a capacitor 9 c, a first planarization film 19, etc. are formed on the surface of a resin substrate 10 formed on a glass substrate using a well-known method, thereby forming a TFT layer 20.

[0058] In the manufacturing method of the organic EL display device 50a, when forming the second wiring layer (such as the upper conductive layer 16), the connecting wire 16a is simultaneously formed in the region of the frame region F on the terminal portion T side where the slit S is formed. Subsequently, a second interlayer insulating film 17 is formed to cover the connecting wire 16a, and then contact holes H17a and H17b are formed in the second interlayer insulating film 17 in portions that overlap, in plan view, with both ends of the connecting wire 16a in the second direction Y (i.e., the end of the frame wire 18h on the terminal portion T side and the end of the frame wire 18i on the display region D side). Furthermore, when forming the third wiring layer (such as the source line 18f, source electrodes 18a and 18c, drain electrodes 18b and 18d, and power line 18g), the frame wires 18h and 18i are simultaneously formed in the frame region F on the terminal portion T side. At this time, the frame wire 18h is formed inward (toward the display region D) from the display region D relative to the slit S (first slit Sa). Furthermore, when the first planarization film 19 is formed on the first TFT 9 a, the second TFT 9 b, and the frame wirings 18 h and 18 i, the lower layer (first planarization film 19 a) of the first damming wall Wa and the lower layer (first planarization film 19 b) of the second damming wall Wb are simultaneously formed in the frame region F. At this time, the first planarization films 19 a and 19 b are formed so as to cover the contact holes H17 a and H17 b, respectively.

[0059] <Organic EL element layer forming process> In the display region D, a first electrode 31, an edge cover 32, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light-emitting layer 3, electron transport layer 4, electron injection layer 5), and a second electrode 34 are formed by using a well-known method on the first planarization film 19 of the TFT layer 20 formed in the TFT layer forming process, thereby forming an organic EL element 35 and forming the organic EL element layer 30.

[0060] Here, in the manufacturing method of the organic EL display device 50a, when forming the edge cover 32, the upper layer of the first dam wall Wa (second planarization film 32a) and the upper layer of the second dam wall Wb (second planarization film 32b) are simultaneously formed in the frame region F.

[0061] In this case, in conventional display devices, the frame wiring (its end faces) exposed through the slits in the planarization film are exposed to (come into contact with) the etchant (etching solution) used to form the first electrode or the developer used to develop the photosensitive resin precursor that forms the edge cover, causing damage to the frame wiring. Damage from the solution is particularly pronounced when, for example, the frame wiring is formed of a Ti / Al / Ti metal laminate film and the first electrode is formed of an Ag-based material. Specifically, since the first electrode etching solution is a PAN-based etching solution, like the Al etching solution, when the first electrode etching solution comes into contact with the exposed Al portion of the edge face of the frame region, the exposed Al portion may be etched and side-shifted inward, or Ag foreign matter produced by the reaction between the Al and the first electrode etching solution may adhere to the exposed Al portion, resulting in a distorted shape.

[0062] In contrast, in the organic EL display device 50a, the frame wiring 18h (upper wiring layer UW) is cut just before the first slit Sa and is covered with the first planarization film 19 (planarization film TH) on the display region D side, and is therefore not exposed from the slit S. Furthermore, the connecting wiring 16a (lower wiring layer LW) that is reconnected from the frame wiring 18h is covered with the second interlayer insulating film 17 (interlayer insulating film IL), and is therefore not exposed from the slit S. Therefore, the frame wiring 18h and the connecting wiring 16a (see FIG. 8) are unlikely to come into contact with the etching solution for the first electrode 31 or the developing solution, i.e., are unlikely to be damaged by these solutions, thereby suppressing the above-mentioned inconvenience.

[0063] <Sealing Film Forming Process> First, on the substrate surface on which the organic EL element layer 30 formed in the organic EL element layer forming process is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD (chemical vapor deposition) using a CMM as a deposition mask so as to cover each organic EL element 35, thereby forming a first inorganic sealing film 41. Next, an organic resin material such as an acrylic resin is formed on the first inorganic sealing film 41 by, for example, an inkjet method, thereby forming an organic sealing film 42. Thereafter, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using the CMM as a deposition mask so as to cover the organic sealing film 42, thereby forming a second inorganic sealing film 43. Through the above processes, sealing films 40d and 40f are formed in which the first inorganic sealing film 41, the organic sealing film 42, and the second inorganic sealing film 43 are stacked in order. In addition, the sealing film 40f in the frame region F may be formed as an organic sealing film 42 so as to reach the upper surface of the second dam wall Wb, and in the region outside the upper surface (towards the terminal portion T), it may be formed as a laminated film of a first inorganic sealing film 41 and a second inorganic sealing film 43 excluding the organic sealing film 42.

[0064] Finally, a protective sheet (not shown) is attached to the surface of the substrate, and then laser light is irradiated from the glass substrate side of the resin substrate 10 to peel the glass substrate from the underside of the resin substrate 10, and a protective sheet (not shown) is attached to the underside of the resin substrate 10 from which the glass substrate has been peeled. In this manner, the organic EL display device 50a can be manufactured.

[0065] <Effects> As described above, the organic EL display device 50a of this embodiment can achieve the following effects. (1) In the organic EL display device 50a, in the frame region F, a frame-shaped slit S is formed in the first planarization film 19 (planarization film TH) to prevent moisture from penetrating and being transmitted to the display region D, and the organic EL display device 50a has a structure in which the first planarization film 19 is not disposed in parts. Furthermore, in the frame region F on the terminal portion T side, the frame wiring 18h (upper wiring layer UW) routed from the third wiring layer provided in the TFT layer 20 that constitutes the display region D is cut just before the first slit Sa, and is reconnected, in the part of the slit S where the first planarization film 19 is not disposed, to a connecting wiring 16a (lower wiring layer LW) formed in the second wiring layer (or first wiring layer) that is lower than the third wiring layer and the second interlayer insulating film 17 (interlayer insulating film IL). In this structure, the frame wiring 18h is covered with the first planarization film 19 on the display region D side, and the connecting wiring 16a is covered with the second interlayer insulating film 17, so that the frame wiring 18h and the connecting wiring 16a are not exposed from the slits S. Therefore, in the manufacturing process following the formation of the frame wiring 18h, the frame wiring 18h and the connecting wiring 16a are unlikely to come into contact with the etchant (etching solution) used to form the first electrode 31 or the developer that develops the photosensitive resin precursor that forms the edge cover 32, and therefore damage from these solutions can be suppressed. (2) In the organic EL display device 50a, due to the above (1), the end faces of the frame wiring 18h and the connecting wiring 16a are prevented from becoming distorted, so that the sealing performance of the sealing film 40f (TFE film) formed on the frame wiring 18h can be suppressed from being reduced. (3) In the organic EL display device 50a, the above (1) and (2) prevent the organic EL elements 35 from deteriorating due to the intrusion of moisture, thereby improving the reliability of the display device.

[0066] Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. 9 and 10 . FIG. 9 is an enlarged plan view of a main portion of region A in FIG. 1 , illustrating the wiring structure of the frame region F on the terminal portion T side of an organic EL display device 50b according to this embodiment, and corresponds to FIG. 6 . FIG. 10 is a cross-sectional view taken along line X-X in FIG. 9 , illustrating the wiring structure of the frame region F on the terminal portion T side of an organic EL display device 50b, and corresponds to FIG. 7 . Note that the sealing film 40f is omitted in FIG. 9 . The first inorganic sealing film 41 and the second inorganic sealing film 43 constituting the sealing film 40f are also omitted in FIG. 10 . The overall configuration of the organic EL display device 50b is the same as that of the first embodiment described above, except for the configuration of the frame region F on the terminal portion T side, and therefore a detailed description thereof will be omitted here. Furthermore, components similar to those of the first embodiment described above will be denoted by the same reference numerals, and their description will be omitted.

[0067] 9 and 10 , the organic EL display device 50b of this embodiment differs from the organic EL display device 50a of the first embodiment in the structure in the third direction Z between the first planarization film 19 and the sealing film 40f in the frame region F on the terminal portion T side. In the organic EL display device 50b, second frame wirings 21a and 21b (upper wiring layer UW) are provided as upper layers of frame wirings 18h and 18i (hereinafter also referred to as "first frame wirings 18h and 18i"). Specifically, the organic EL display device 50b includes, in the frame region F, a resin substrate 10; an inorganic insulating laminate film (including a base coat film 11, a gate insulating film 13, a first interlayer insulating film 15, and a second interlayer insulating film 17) provided on the resin substrate 10; a plurality of first frame wirings 18h and 18i provided on the second interlayer insulating film 17 constituting the inorganic insulating laminate film; and a plurality of first frame wirings 18h and 18i provided on the first frame wirings 18h and 18i or the inorganic insulating laminate film. The organic EL display device 50b further includes a first planarization film 19, 19c, a first damming wall Waa, and a second damming wall Wbb formed on the first planarization film 19, 19c, second frame wirings 21a, 21b (upper wiring layer UW) formed on the first planarization film 19, 19c, respectively, a second planarization film 22, 22c (planarization film TH) formed so as to cover the second frame wirings 21a, 21b, and a sealing film 40f formed on the second planarization film 22, the first damming wall Waa, and the second damming wall Wbb. The organic EL display device 50b further includes a connecting wiring 16a (lower wiring layer LW) formed on the first interlayer insulating film 15 in the frame region F on the terminal portion T side.

[0068] As shown in FIGS. 9 and 10, in the organic EL display device 50b, the first frame wiring 18h is not a wiring routed from the display region D to the frame region F, but is provided in a plurality of islands in a plan view.

[0069] As shown in Figures 9 and 10, in the organic EL display device 50b, the first frame wiring 18i is not a wiring that is arranged to reach the terminal portion T in the frame region F on the terminal portion T side, but is arranged in multiple islands in a planar view.

[0070] The second frame wiring 21a (upper wiring layer UW) refers to wiring routed from the display region D to the frame region F and corresponds to the frame wiring 18h constituting the organic EL display device 50a. As shown in FIG. 9 , in the frame region F on the terminal portion T side, a plurality of second frame wirings 21a are provided to correspond to the plurality of island-shaped first frame wirings 18h and extend in the second direction Y from the display region D toward the terminal portion T. The second frame wiring 21a (its end portion on the terminal portion T side) is provided inside (on the display region D side) the frame-shaped slit S (first slit Sa). The second frame wiring 21a is provided up to just before the first slit Sa. In other words, the second frame wiring 21a is not provided so as to reach the terminal portion T, but is cut just before the first slit Sa and separated from the second frame wiring 21b. Therefore, the second frame wiring 21a is covered by the second planarization film 22 on the display area D side and is not exposed (stretched) from the slit S (first slit Sa). Also, as shown in FIG. 10 , the second frame wiring 21a is provided on the first planarization film 19 on the display area D side, which constitutes the TFT layer 20. Therefore, the second frame wiring 21a is formed in the same layer and made of the same material as the fourth wiring layer, which is located above the third wiring layer provided in the TFT layer 20 constituting the display area D. The fourth wiring layer refers to, for example, a conductive layer between the third wiring layer and the first electrode 31. The fourth wiring layer is formed of a metal single layer film or a metal laminate film similar to the first, second, or third wiring layer. The second frame wiring 21a routed from the fourth wiring layer is preferably formed of a metal laminate film such as Ti / Al / Ti.

[0071] As shown in FIG. 9 , the second frame wiring 21b (upper wiring layer UW) is a wiring that is separated from the second frame wiring 21a by the width of the slit S (length in the second direction Y) in the frame region F on the terminal portion T side and is provided so as to reach the terminal portion T. This corresponds to the frame wiring 18i that constitutes the organic EL display device 50a. Therefore, the second frame wiring 21b is covered with the second planarization film 22c and is not exposed from the slit S (third slit Sc). A plurality of second frame wirings 21b are provided so as to extend in the second direction Y toward the terminal portion T, corresponding to the plurality of island-shaped first frame wirings 18i and the plurality of second frame wirings 21a. The terminal portion T-side end of the second frame wiring 21b is electrically connected to each terminal arranged in the terminal portion T. Furthermore, as shown in FIG. 10 , the second frame wiring 21b is provided on a first planarization film 19c that is formed in the same layer and from the same material as the first planarization film 19. Therefore, like the second frame wiring 21a, the second frame wiring 21b is formed in the same layer as the fourth wiring layer using the same material. The second frame wiring 21b is preferably formed of a metal laminate film such as Ti / Al / Ti.

[0072] 9 and 10 , the second frame wirings 21a and 21b are not provided inside the slit S. In other words, the second frame wirings 21a and 21b do not overlap the slit S in a plan view. The second frame wirings 21a and 21b may be power supply wiring such as ELVDD or ELVSS, or may be other signal wiring.

[0073] The second planarization films 22 and 22 c (planarization film TH) are made of the same material as the first planarization film 19 or the edge cover 32 .

[0074] As shown in Figure 10, the first dam wall Waa is composed of a first planarization film 19a formed in the same layer as the first planarization film 19 and made of the same material, a second planarization film 22a provided on the first planarization film 19a, and a third planarization film 32aa provided on the second planarization film 22a and formed in the same layer as the edge cover 32 and made of the same material.

[0075] As shown in Figure 10, the second dam wall Wbb is composed of a first planarization film 19b formed in the same layer as the first planarization film 19 and made of the same material, a second planarization film 22b provided on the first planarization film 19b, and a third planarization film 32bb provided on the second planarization film 22b and formed in the same layer as the edge cover 32 and made of the same material.

[0076] Here, in the organic EL display device 50b of this embodiment, as shown in Figures 9 and 10, in the frame region F on the terminal portion T side, the second frame wirings 21a and 21b (upper wiring layer UW) are connected to the connecting wiring 16a (lower wiring layer LW) via the first frame wirings 18h and 18i.

[0077] As shown in FIGS. 9 and 10 , the connecting wiring 16a (its end on the display region D side) is electrically connected to the island-shaped first frame wiring 18h (its end on the terminal portion T side) via a contact hole H17a. The first frame wiring 18h (its end on the display region D side) is electrically connected to the second frame wiring 21a via a contact hole H19a (hereinafter also referred to as the “second contact hole H19a”). The second contact hole H19a is a portion (contact portion) that connects the first frame wiring 18h and the second frame wiring 21a. The second contact hole H19a is formed in the first planarization film 19 so as to penetrate the first planarization film 19 on the display region D side. The second contact hole H19a is formed for each first frame wiring 18h so as to expose at least a portion of the end on the display region D side of the first frame wiring 18h. 9 and 10 , the second contact hole H19a overlaps, in a planar view, with the second planarization film 22 (planarization film TH) on the display region D side. In other words, the second contact hole H19a is covered with the second planarization film 22 on the display region D side.

[0078] On the other hand, as shown in FIGS. 9 and 10 , the connecting wiring 16a (its end on the terminal portion T side) is electrically connected to the island-shaped first frame wiring 18i (its end on the display area D side) via a contact hole H17b. The first frame wiring 18i (its end on the terminal portion T side) is electrically connected to the second frame wiring 21b via a contact hole H19b (hereinafter also referred to as the “second contact hole H19b”). The second contact hole H19b is a portion (contact portion) that connects the first frame wiring 18i and the second frame wiring 21b. The second contact hole H19b is formed in the first planarization film 19c so as to penetrate the first planarization film 19c. The second contact hole H19b is formed for each first frame wiring 18i so as to expose at least a portion of the end on the terminal portion T side of the first frame wiring 18i. 9 and 10 , the second contact hole H19b overlaps, in a plan view, with the second planarization film 22c on the terminal portion T. In other words, the second contact hole H19b is covered with the second planarization film 22c on the terminal portion T.

[0079] In this way, in the organic EL display device 50b, in the region (inside the slit S) in the frame region F on the terminal portion T side where the slit S is formed in the first planarization film 19 and the second planarization film 22 (planarization film TH), the second frame wiring 21a (fourth wiring layer, upper wiring layer UW) routed from the display region D is reconnected to the connecting wiring 16a (second wiring layer or first wiring layer, lower wiring layer LW) located below the first frame wiring 18h and the second interlayer insulating film 17 (interlayer insulating film IL) via the island-shaped first frame wiring 18h (third wiring layer) located below the second frame wiring 21a and the first planarization film 19.

[0080] The organic EL display device 50b can be obtained by modifying the TFT layer forming process and the organic EL element layer forming process of the organic EL display device 50a as follows.

[0081] In the TFT layer formation process, after forming the first planarization film 19, second contact holes H19a and H19b are formed in the frame region F on the terminal portion T side. Subsequently, when forming the fourth wiring layer (such as a conductive layer between the third wiring layer and the first electrode 31), the second frame wirings 21a and 21b are simultaneously formed. Furthermore, when forming the second planarization film 22 on the second frame wirings 21a and 21b, the intermediate layer of the first damming wall Waa (second planarization film 22a), the intermediate layer of the second damming wall Wbb (second planarization film 22b), and the second planarization film 22c are simultaneously formed.

[0082] In the organic EL element layer forming step, when the edge cover 32 is formed, the upper layer (third planarization film 32aa) of the first damming wall Waa and the upper layer (third planarization film 32bb) of the second damming wall Wbb are simultaneously formed.

[0083] <Effects> The organic EL display device 50b described above can achieve the same effects as those described in (1) to (3) above. Specifically, the organic EL display device 50b further includes, in addition to a third wiring layer provided in the TFT layer 20 that constitutes the display region D, a fourth wiring layer that is above the third wiring layer as auxiliary wiring, and a second planarization film 22 (planarization film TH) that is provided to cover the fourth wiring layer. In the organic EL display device 50b, in the frame region F, frame-shaped slits S are formed in the first planarization film 19 and the second planarization film 22 (planarization film TH) to prevent moisture from penetrating and transmitting to the display region D, resulting in a structure in which the first planarization film 19 and the second planarization film 22 are not disposed in certain areas. In addition, in the frame region F on the terminal portion T side, the second frame wiring 21a (upper wiring layer UW) routed from the fourth wiring layer provided in the TFT layer 20 constituting the display region D is cut just before the first slit Sa, and in the part of the slit S where the first planarization film 19 and the second planarization film 22 are not arranged, it is reconnected to the connecting wiring 16a (lower wiring layer LW) formed in the second wiring layer (or first wiring layer) below the first frame wiring 18h and the second interlayer insulating film 17 (interlayer insulating film IL) via the island-shaped first frame wiring 18h formed in the third wiring layer below the fourth wiring layer and the first planarization film 19. In this structure, the second frame wiring 21a is covered with the second planarization film 22 on the display region D side, the first frame wiring 18h is covered with the first planarization film 19 on the display region D side, and the connecting wiring 16a is covered with the second interlayer insulating film 17, so that the second planarization film 22, the first frame wiring 18h, and the connecting wiring 16a are not exposed from the slits S. Therefore, in the manufacturing process following the formation of the second frame wiring 21a, the second planarization film 22, the first frame wiring 18h, and the connecting wiring 16a are unlikely to come into contact with the etchant (etching solution) used to form the first electrode 31 or the developer that develops the photosensitive resin precursor that forms the edge cover 32, and therefore damage from these solutions can be suppressed. Therefore, the organic EL display device 50b in which the second frame wiring 21a is formed as the fourth wiring layer can achieve the same effects as the organic EL display device 50a.

[0084] Other Embodiments In each of the above embodiments, the inorganic laminate film is composed of four layers, namely, a gate insulating film, a first interlayer insulating film, and a second interlayer insulating film, laminated in this order on a base coat film. However, the inorganic laminate film may be composed of a single layer of the base coat film, or may be composed of two layers, namely, a base coat film and a gate insulating film.

[0085] In each of the above embodiments, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer has been exemplified. However, the organic EL layer may have a three-layer stacked structure of, for example, a hole injection layer / hole transport layer, a light-emitting layer, and an electron transport layer / electron injection layer.

[0086] In addition, in each of the above embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, and the first electrode is a cathode and the second electrode is an anode.

[0087] In each of the above embodiments, an organic EL display device is exemplified in which the electrode of the TFT connected to the first electrode is used as the drain electrode, but the present invention can also be applied to an organic EL display device in which the electrode of the TFT connected to the first electrode is called the source electrode.

[0088] In the above embodiments, an organic EL display device is used as the display device, but the present invention can also be applied to display devices such as an active matrix driving liquid crystal display device.

[0089] In the above embodiments, an organic EL display device has been described as an example of a display device, but the present invention is not limited to organic EL display devices and can be applied to any flexible display device. For example, the present invention can be applied to a flexible display device including a quantum-dot light emitting diode (QLED), which is a light emitting element using a quantum dot-containing layer.

[0090] As described above, the present invention is useful for flexible display devices.

[0091] D Display area F Frame area H17a, H17b Contact holes H19a, H19b Contact holes IL Interlayer insulating film LW Lower wiring layer P Subpixel S Slit Sa First slit Sb Second slit Sc Third slit T Terminal portion TH Planarizing film UW Upper wiring layer Wa, Waa First damming wall Wb, Wbb Second damming wall 10 Resin substrate (base substrate) 16a Connecting wiring 17 Second interlayer insulating film 18h, 18i Frame wiring 19, 19a to 19c First planarizing film (planarizing film) 20 TFT (thin film transistor) layer 21a, 21b Second frame wiring 22, 22a to 22c Second planarizing film 30 Organic EL element layer (light emitting element layer) 32a, 32b Second planarization film 32aa, 32bb Third planarization film 35 Organic EL element (light-emitting element) 40, 40d, 40f Sealing film 50a, 50b Organic EL display device

Claims

1. A base substrate; a lower wiring layer provided on the base substrate; an interlayer insulating film provided to cover the lower wiring layer; an upper wiring layer provided on the interlayer insulating film; a planarization film provided to cover the upper wiring layer, a thin-film transistor layer including these; a light-emitting element layer provided on the thin-film transistor layer and constituting a display region; a frame region provided around the display region; a terminal portion provided at one end of the frame region; a plurality of frame wirings formed of the same material as the upper wiring layer and formed in the same layer so as to be led from the display region to the frame region and extend toward the terminal portion; and a frame-shaped slit formed in the planarization film in the frame region. In the frame region on the terminal portion side, the plurality of frame wirings are provided closer to the display region side than the slit, and in the region where the slit is formed, a plurality of connection wirings formed of the same material as the lower wiring layer and formed in the same layer are provided along the extending direction of the plurality of frame wirings. A plurality of contact holes are formed in the interlayer insulating film to electrically connect the plurality of frame wirings and the plurality of connection wirings, respectively. The plurality of frame wirings are reconnected to the plurality of connection wirings through the plurality of contact holes, respectively. A display device characterized by this.

2. The display device according to claim 1, characterized in that the plurality of frame wirings and the plurality of connection wirings are not exposed from the slit.

3. The display device according to claim 1 or 2, characterized in that the interlayer insulating film is exposed from the slit.

4. The display device according to any one of claims 1 to 3, characterized in that the plurality of connection wirings overlap the slit in a plan view.

5. The display device according to any one of claims 1 to 4, characterized in that the plurality of connection wirings intersect the slit.

6. The display device according to any one of claims 1 to 5, characterized in that the plurality of contact holes are covered with the planarization film.

7. The display device according to any one of claims 1 to 6, wherein the thin film transistor layer includes a first wiring layer and a second wiring layer as an upper layer thereof, and the plurality of connection wirings are formed in the same layer as the first wiring layer or the second wiring layer with the same material as the lower wiring layer.

8. The display device according to claim 7, wherein the thin film transistor layer includes a third wiring layer as an upper layer of the second wiring layer, and the plurality of frame wirings are formed in the same layer as the third wiring layer with the same material as the upper wiring layer.

9. The display device according to claim 8, wherein the plurality of light emitting elements constituting the light emitting element layer include a first electrode, the thin film transistor layer includes a fourth wiring layer provided between the third wiring layer and the first electrode as an upper layer of the third wiring layer, and the plurality of frame wirings are formed in the same layer as the fourth wiring layer with the same material as the upper wiring layer.

10. The display device according to claim 9, wherein the plurality of frame wirings include a plurality of first frame wirings formed in an island shape in the same layer with the same material as the third wiring layer, and a plurality of second frame wirings formed in the same layer with the same material as the fourth wiring layer as the upper wiring layer, and the plurality of second frame wirings are respectively connected to the plurality of connection wirings via the plurality of first frame wirings.

11. The display device according to claim 10, wherein a plurality of second contact holes are provided in the planarization film to electrically connect the plurality of second frame wirings and the plurality of first frame wirings respectively, the plurality of second frame wirings are respectively connected to the plurality of first frame wirings via the plurality of second contact holes, and the plurality of first frame wirings are respectively connected to the plurality of connection wirings via the plurality of contact holes.

12. The display device according to any one of claims 1 to 11, wherein the plurality of frame wirings are formed of a metal laminated film in which a titanium film, an aluminum film, and a titanium film are laminated in this order.

13. The display device according to any one of claims 1 to 12, wherein the plurality of connection wirings are formed of a metal laminated film in which a titanium film, an aluminum film, and a titanium film are laminated in this order.

14. The display device according to any one of claims 1 to 13, further comprising a sealing film provided so as to cover the light-emitting element layer, the sealing film including a first inorganic film, an organic film, and a second inorganic film laminated in this order.

15. The display device according to any one of claims 1 to 14, wherein the light-emitting element layer is an organic electroluminescence element layer.

16. A method for manufacturing a display device, the display device including: a base substrate; a thin film transistor layer provided on the base substrate, the thin film transistor layer including a lower wiring layer, an interlayer insulating film provided so as to cover the lower wiring layer, an upper wiring layer provided on the interlayer insulating film, and a planarization film provided so as to cover the upper wiring layer; a light-emitting element layer provided on the thin film transistor layer and constituting a display region; a frame region provided around the display region; a terminal portion provided at one end of the frame region; a plurality of frame wirings formed of the same material and in the same layer as the upper wiring layer, the plurality of frame wirings being drawn from the display region to the frame region and extending toward the terminal portion; and a frame-shaped slit formed in the planarization film in the frame region. The method includes: a thin film transistor layer forming step of forming the thin film transistor layer, in which, in the frame region on the terminal portion side, a plurality of connection wirings are formed of the same material and in the same layer as the lower wiring layer along the extending direction of the plurality of frame wirings in a region where the slit is formed; forming the interlayer insulating film so as to cover the plurality of connection wirings; forming a plurality of contact holes in the interlayer insulating film to electrically connect the plurality of frame wirings and the plurality of connection wirings respectively; and forming the plurality of frame wirings on the display region side of the slit, thereby reconnecting the plurality of frame wirings to the plurality of connection wirings respectively via the plurality of contact holes.

17. In the method of manufacturing a display device according to claim 16, in the step of forming the thin film transistor layer, in the frame region on the terminal portion side, a planarization film is formed so as to cover the plurality of contact holes. A method of manufacturing a display device, characterized by this.

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