Light detection device

Abstract

Provided is a light detection device capable of improving performance. This light detection device comprises: a first semiconductor substrate; a plurality of sensor pixels provided on the first semiconductor substrate; and an inter-pixel separation unit that is provided on the first semiconductor substrate and that separates one and the other sensor pixels adjacent to each other. In a plan view in the thickness direction of the first semiconductor substrate, each of the plurality of sensor pixels has a rectangular shape. The plurality of sensor pixels are arranged, via the inter-pixel separation unit and having the edges adjacent to each other, side by side in a first direction and a second direction intersecting the first direction. Each of the plurality of sensor pixels has: a first photoelectric conversion unit that photoelectrically converts light that enters from a first surface; a second photoelectric conversion unit that is adjacent to the first photoelectric conversion unit and photoelectrically converts light that enters from the first surface; and an intra-pixel separation unit that separates the first photoelectric conversion unit and the second photoelectric conversion unit. The intra-pixel separation unit extends in a direction oblique to the first direction and the second direction.

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] A technique is known for detecting a phase difference in a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor by irradiating light onto a pair of photodiodes through the same on-chip lens (see, for example, Patent Document 1).

[0003] US Patent Application Publication No. 2017 / 0012066

[0004] There is a demand for further improvement in performance of imaging devices such as CMOS image sensors.

[0005] An object of the present disclosure is to provide a photodetector device that can improve performance.

[0006] A photodetector according to one aspect of the present disclosure includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, a plurality of sensor pixels provided on the first semiconductor substrate, and an inter-pixel isolation portion provided on the first semiconductor substrate and separating adjacent sensor pixels from each other of the plurality of sensor pixels. Each of the plurality of sensor pixels has a rectangular shape in a plan view from a thickness direction of the first semiconductor substrate. The plurality of sensor pixels are arranged side by side in a first direction and a second direction intersecting the first direction, with their edges adjacent to each other via the inter-pixel isolation portion. Each of the plurality of sensor pixels includes a first photoelectric conversion portion that photoelectrically converts light incident on the first surface, a second photoelectric conversion portion that is adjacent to the first photoelectric conversion portion and performs photoelectric conversion on the light incident on the first surface, and an intra-pixel isolation portion that separates the first photoelectric conversion portion from the second photoelectric conversion portion. The intra-pixel isolation portion extends in a direction oblique to each of the first direction and the second direction.

[0007] In this case, the intra-pixel separator extends in two directions (for example, the horizontal direction and the vertical direction) that intersect with each other, and the first photoelectric conversion unit and the second photoelectric conversion unit are arranged adjacent to each other in the horizontal direction or the vertical direction via the intra-pixel separator, thereby enabling the photodetector to obtain phase difference information in both the horizontal direction and the vertical direction.

[0008] Furthermore, the pixel wiring can be extended in a direction oblique to the first direction and the second direction in which the plurality of sensor pixels are arranged, respectively, which makes it possible to increase the distance between adjacent pixel wirings and suppress crosstalk between the adjacent pixel wirings compared to when the pixel wirings are extended in a direction horizontal or perpendicular to the first direction and the second direction, respectively.

[0009] From the above, it is possible to improve the performance of the photodetector.

[0010] FIG. 1 is a diagram illustrating an example of the overall configuration of an imaging device according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of the configuration of a pixel circuit according to the first embodiment of the present disclosure. FIG. 3 is a plan view illustrating an example of the configuration of a unit pixel of the imaging device according to the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view illustrating an example of the configuration of one sensor pixel included in a unit pixel according to the first embodiment of the present disclosure. FIG. 5 is a cross-sectional view illustrating an example of the configuration of one sensor pixel included in a unit pixel according to the first embodiment of the present disclosure. FIG. 6 is a plan view illustrating an example of the configuration of a unit pixel of the imaging device according to the first embodiment of the present disclosure and an example of the arrangement of transistors in the unit pixel. FIG. 7 is a plan view illustrating the positional relationship between a unit pixel and vertical pixel wiring in an imaging device according to an embodiment of the present disclosure. FIG. 8 is a plan view illustrating the configuration of a unit pixel of an imaging device according to a comparative example of the present disclosure. FIG. 9 is a plan view illustrating the configuration of a unit pixel of an imaging device according to a comparative example of the present disclosure and the arrangement of transistors in the unit pixel. FIG. 10 is a plan view illustrating the configuration of an imaging device according to a first modification of the first embodiment of the present disclosure. FIG. 11 is a plan view illustrating the configuration of an imaging device according to a second modification of the first embodiment of the present disclosure. FIG. 12 is a cross-sectional view showing an example of a stacked structure of an imaging device according to a second embodiment of the present disclosure. FIG. 13 is a plan view showing an example of the configuration of a first substrate unit of an imaging device according to the second embodiment of the present disclosure. FIG. 14 is a plan view showing an example of the positional relationship between unit pixels and reference potential wiring in an imaging device according to the second embodiment of the present disclosure. FIG. 15 is a plan view showing an example of the positional relationship between unit pixels and vertical pixel wiring in an imaging device according to the second embodiment of the present disclosure. FIG. 16 is a plan view showing an example of the arrangement of pixel transistors in unit pixels in an imaging device according to the second embodiment of the present disclosure. FIG. 17 is a plan view showing an example of the positional relationship between unit pixels including pixel transistors, vertical pixel wiring, and reference potential wiring in an imaging device according to the second embodiment of the present disclosure. FIG. 18 is a plan view showing the configuration of an imaging device according to a first modification of the second embodiment of the present disclosure. FIG. 19 is a plan view showing an example of the layout of vertical pixel wiring in an imaging device according to the first modification of the second embodiment of the present disclosure. FIG. 20 is a plan view showing an example of the layout of reference potential wiring in an imaging device according to the first modification of the second embodiment of the present disclosure. FIG. 21 is a plan view illustrating a configuration of an imaging device according to Modification 2 of Embodiment 2 of the present disclosure.FIG. 22 is a plan view showing a configuration example of an imaging device according to a third embodiment of the present disclosure. FIG. 23 is a plan view showing a configuration example of a sensor pixel according to a fourth embodiment of the present disclosure. FIG. 24 is a plan view showing a configuration example of a sensor pixel according to a comparative example of the present disclosure. FIG. 25A is a plan view schematically showing a 2×2 type layout example (part 1) according to a fourth embodiment of the present disclosure. FIG. 25B is a plan view schematically showing a 2×2 type layout example (part 2) according to a fourth embodiment of the present disclosure. FIG. 25C is a plan view schematically showing a 2×2 type layout example (part 3) according to a fourth embodiment of the present disclosure. FIG. 25D is a plan view schematically showing a 2×2 type layout example (part 4) according to a fourth embodiment of the present disclosure. FIG. 25E is a plan view schematically showing a 2×2 type layout example (part 5) according to a fourth embodiment of the present disclosure. FIG. 25F is a plan view schematically showing a 2×2 type layout example (part 6) according to a fourth embodiment of the present disclosure. FIG. 25G is a plan view schematically showing a 2×2 type arrangement example (part 7) according to the fourth embodiment of the present disclosure. FIG. 25H is a plan view schematically showing a 2×2 type arrangement example (part 8) according to the fourth embodiment of the present disclosure. FIG. 25I is a plan view schematically showing a 2×2 type arrangement example (part 9) according to the fourth embodiment of the present disclosure. FIG. 26A is a plan view schematically showing a 3×3 type arrangement example (part 1) according to the fourth embodiment of the present disclosure. FIG. 26B is a plan view schematically showing a 3×3 type arrangement example (part 2) according to the fourth embodiment of the present disclosure. FIG. 26C is a plan view schematically showing a 3×3 type arrangement example (part 3) according to the fourth embodiment of the present disclosure. FIG. 26D is a plan view schematically showing a 3×3 type arrangement example (part 4) according to the fourth embodiment of the present disclosure. FIG. 26E is a plan view schematically showing a 3×3 type arrangement example (part 5) according to the fourth embodiment of the present disclosure. Fig. 26F is a plan view schematically showing a 3x3 type arrangement example (part 6) according to the fourth embodiment of the present disclosure. Fig. 26G is a plan view schematically showing a 3x3 type arrangement example (part 7) according to the fourth embodiment of the present disclosure. Fig. 26H is a plan view schematically showing a 3x3 type arrangement example (part 8) according to the fourth embodiment of the present disclosure. Fig. 27A is a plan view schematically showing a 4x4 type arrangement example (part 1) according to the fourth embodiment of the present disclosure. Fig. 27B is a plan view schematically showing a 4x4 type arrangement example (part 2) according to the fourth embodiment of the present disclosure.FIG. 27C is a plan view schematically showing a 4×4 type arrangement example (part 3) according to the fourth embodiment of the present disclosure. FIG. 27D is a plan view schematically showing a 4×4 type arrangement example (part 4) according to the fourth embodiment of the present disclosure. FIG. 27E is a plan view schematically showing a 4×4 type arrangement example (part 5) according to the fourth embodiment of the present disclosure. FIG. 28A is a plan view schematically showing a configuration and arrangement example (part 1) of a unit pixel P according to the fourth embodiment of the present disclosure. FIG. 28B is a plan view schematically showing a configuration and arrangement example (part 2) of a unit pixel P according to the fourth embodiment of the present disclosure. FIG. 28C is a plan view schematically showing a configuration and arrangement example (part 3) of a unit pixel P according to the fourth embodiment of the present disclosure. FIG. 28D is a plan view schematically showing a configuration and arrangement example (part 4) of a unit pixel P according to the fourth embodiment of the present disclosure. FIG. 29A is a plan view schematically showing a shape example (part 1) of an intra-pixel separator according to the fourth embodiment of the present disclosure. FIG. 29B is a plan view schematically showing a shape example (part 2) of the intra-pixel separation portion according to the fourth embodiment of the present disclosure. FIG. 29C is a plan view schematically showing a shape example (part 3) of the intra-pixel separation portion according to the fourth embodiment of the present disclosure. FIG. 29D is a plan view schematically showing a shape example (part 4) of the intra-pixel separation portion according to the fourth embodiment of the present disclosure. FIG. 29E is a plan view schematically showing a shape example (part 5) of the intra-pixel separation portion according to the fourth embodiment of the present disclosure. FIG. 30 is a cross-sectional view schematically showing a shape example of the intra-pixel separation portion according to the fourth embodiment of the present disclosure. FIG. 31A is a plan view schematically showing a color filter arrangement example (part 1) according to the fifth embodiment of the present disclosure. FIG. 31B is a plan view schematically showing a color filter arrangement example (part 2) according to the fifth embodiment of the present disclosure. FIG. 31C is a plan view schematically showing a color filter arrangement example (part 3) according to the fifth embodiment of the present disclosure. Fig. 31D is a plan view schematically showing a fourth example of a color filter arrangement according to the fifth embodiment of the present disclosure. Fig. 31E is a plan view schematically showing a fifth example of a color filter arrangement according to the fifth embodiment of the present disclosure. Fig. 31F is a plan view schematically showing a sixth example of a color filter arrangement according to the fifth embodiment of the present disclosure. Fig. 31G is a plan view schematically showing a seventh example of a color filter arrangement according to the fifth embodiment of the present disclosure. Fig. 31H is a plan view schematically showing an eighth example of a color filter arrangement according to the fifth embodiment of the present disclosure.FIG. 31I is a plan view schematically illustrating a ninth example of a color filter arrangement according to the fifth embodiment of the present disclosure.

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0013] In the following description, directions may be described using the terms X-axis, Y-axis, and Z-axis. For example, the Z-axis is the thickness direction of the semiconductor substrate 30, which will be described later. The X-axis and Y-axis directions are parallel to the rear surface 30b of the semiconductor substrate 30 and are perpendicular to the Z-axis direction. The X-axis, Y-axis, and Z-axis directions are perpendicular to each other.

[0014] In the following description, the term "planar view" means, for example, a view from the thickness direction of the semiconductor substrate 30 (for example, the Z-axis direction).

[0015] 1 is a diagram showing an example of the overall configuration of an imaging device 1 according to embodiment 1 of the present disclosure. The imaging device 1 is an example of the "photodetection device" of the present disclosure, and is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor used in electronic devices such as digital still cameras and video cameras.

[0016] As shown in FIG. 1, the imaging device 1 includes a pixel array section 10, a system control section 12, a vertical drive section 13, a column readout circuit section 14, a column signal processing section 15, a horizontal drive section 16, and a signal processing section 17.

[0017] The pixel array section 10, system control section 12, vertical drive section 13, column readout circuit section 14, column signal processing section 15, horizontal drive section 16 and signal processing section 17 are provided on the same semiconductor substrate or on multiple electrically connected stacked semiconductor substrates.

[0018] The pixel array section 10 has sensor pixels 11 arranged two-dimensionally in a matrix, each having a photoelectric conversion element (photodiode PD (see Figure 2)) that can photoelectrically convert an amount of charge corresponding to the amount of incident light, store it internally, and output it as a signal.

[0019] In addition to the sensor pixels 11, the pixel array section 10 may include an area in which dummy pixels having a structure that does not have a photodiode PD, and light-shielding pixels that block light incident from outside by shading the light-receiving surface, etc. are arranged in rows and / or columns.

[0020] The light-shielded pixels may have the same configuration as the sensor pixels 11, except that the light-receiving surfaces are structured so as to be light-shielded. In the following description, the photocharges having an amount corresponding to the amount of incident light may also be simply referred to as "charges."

[0021] In the pixel array unit 10, pixel drive lines LD are formed for each row in the matrix-like pixel arrangement along the left-right direction in Fig. 1 (the direction in which pixels in a pixel row are arranged), and vertical pixel wiring LV (an example of "pixel wiring" in the present disclosure) is formed for each column along the up-down direction in Fig. 1 (the direction in which pixels in a pixel column are arranged). One end of the pixel drive line LD is connected to an output terminal of the vertical driving unit 13 corresponding to each row.

[0022] The column readout circuit unit 14 includes at least a circuit that supplies a constant current to the sensor pixels 11 in a selected row in the pixel array unit 10 for each column, a current mirror circuit, and a switch for selecting the sensor pixel 11 to be read out.

[0023] The column readout circuit unit 14 forms an amplifier together with the transistors in the selected pixels in the pixel array unit 10, converts the photocharge signal into a voltage signal, and outputs it to the vertical pixel line LV.

[0024] The vertical drive unit 13 includes a shift register, an address decoder, etc., and drives each sensor pixel 11 of the pixel array unit 10 all at once or row by row, etc. Although the specific configuration of this vertical drive unit 13 is not shown in the figure, it is configured to have a readout scanning system and a sweep scanning system or a batch sweep and batch transfer system.

[0025] The readout scanning system sequentially selects and scans the sensor pixels 11 of the pixel array unit 10 row by row in order to read out pixel signals from the sensor pixels 11. In the case of row driving (rolling shutter operation), for sweeping, for a readout row on which readout scanning is performed by the readout scanning system, sweeping scanning is performed prior to the readout scanning by the shutter speed.

[0026] In the case of global exposure (global shutter operation), a collective discharge is performed prior to the collective transfer by the time of the shutter speed. This discharge discharges (resets) unnecessary charges from the photodiodes PD of the sensor pixels 11 in the readout row. The discharge (reset) of unnecessary charges then performs a so-called electronic shutter operation.

[0027] Here, the electronic shutter operation refers to an operation of discarding unnecessary photocharges that have been accumulated in the photodiode PD until just before, and starting new exposure (starting accumulation of photocharges).

[0028] The signal read by the readout operation by the readout scanning system corresponds to the amount of light that has entered since the immediately preceding readout operation or electronic shutter operation. In the case of row driving, the period from the readout timing of the immediately preceding readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation is the accumulation time (exposure time) of the photocharges in the sensor pixels 11. In the case of global exposure, the time from the collective sweep to the collective transfer is the accumulation time (exposure time).

[0029] The pixel signals output from each sensor pixel 11 in a pixel row selected and scanned by the vertical drive unit 13 are supplied through each vertical pixel wiring LV to the column signal processing unit 15. The column signal processing unit 15 performs predetermined signal processing on the pixel signals output from each sensor pixel 11 in the selected row through the vertical pixel wiring LV for each pixel column in the pixel array unit 10, and temporarily stores the pixel signals after signal processing.

[0030] Specifically, the column signal processing unit 15 performs at least noise removal processing, such as correlated double sampling (CDS) processing, as signal processing. The CDS processing by the column signal processing unit 15 removes pixel-specific fixed pattern noise such as reset noise and threshold variation of the amplification transistor AMP.

[0031] In addition to the noise removal processing, the column signal processing unit 15 may also be configured to have, for example, an AD conversion function so as to output pixel signals as digital signals.

[0032] The horizontal drive unit 16 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column signal processing unit 15. By selective scanning by this horizontal drive unit 16, pixel signals processed by the column signal processing unit 15 are sequentially output to the signal processing unit 17.

[0033] The system control unit 12 includes a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 13, column signal processing unit 15, horizontal driving unit 16, etc. based on the various timing signals generated by the timing generator.

[0034] The imaging device 1 further includes a signal processing unit 17 and a data storage unit (not shown). The signal processing unit 17 has at least an addition processing function and performs various signal processing such as addition processing on the pixel signals output from the column signal processing unit 15.

[0035] The data storage unit temporarily stores data necessary for signal processing in the signal processing unit 17. The signal processing unit 17 and the data storage unit may be an external signal processing unit provided on a board separate from the imaging device 1, such as a DSP (Digital Signal Processor) or software processing, or may be mounted on the same board as the imaging device 1.

[0036] (Configuration Example of Pixel Circuit) Next, a configuration example of a pixel circuit will be described with reference to Fig. 2. Fig. 2 is a diagram showing a configuration example of a pixel circuit according to embodiment 1 of the present disclosure. As shown in Fig. 2, in embodiment 1, four sensor pixels 11 share one readout circuit 18. Here, "shared" means that the four sensor pixels 11 are electrically connected to the common readout circuit 18, i.e., the outputs of the four sensor pixels 11 are input to the common readout circuit 18.

[0037] The sensor pixels 11 have common components. In Fig. 2, in order to distinguish the components of the sensor pixels 11 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the component of each sensor pixel 11.

[0038] In the present disclosure, when it is necessary to distinguish the components of each sensor pixel 11 from one another, an identification number is added to the end of the reference numeral of the component of each sensor pixel 11. On the other hand, in the present disclosure, when it is not necessary to distinguish the components of each sensor pixel 11 from one another, the identification number at the end of the reference numeral of the component of each sensor pixel 11 is omitted.

[0039] Each sensor pixel 11 includes, for example, a photodiode PD and a transfer transistor TR electrically connected to the photodiode PD.

[0040] These sensor pixels 11 share a floating diffusion FD electrically connected to each transfer transistor TR. Here, "sharing" means that the photodiode PD of each sensor pixel 11 is electrically connected to the floating diffusion FD.

[0041] The photodiode PD performs photoelectric conversion to generate an electric charge according to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (for example, ground potential).

[0042] The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR, that is, the transfer gate TG, is electrically connected to the pixel drive line LD (see FIG. 1). The transfer transistor TR is, for example, a CMOS transistor.

[0043] The floating diffusion FD is common to the sensor pixels 11 that share one readout circuit 18, and is electrically connected to the input terminal of the readout circuit 18 that is common to these sensor pixels 11. This floating diffusion FD temporarily holds the charge output from the photodiode PD via the transfer transistor TR.

[0044] 2, the read circuit 18 includes, for example, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and a switching transistor FDG. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the switching transistor FDG are, for example, CMOS transistors. Note that the selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0045] The source of the switching transistor FDG, which is the input of the readout circuit 18, is electrically connected to the floating diffusion FD, the drain of the switching transistor FDG is electrically connected to the source of the reset transistor RST, and the gate of the switching transistor FDG is electrically connected to the pixel drive line LD.

[0046] The drain of the reset transistor RST is electrically connected to a power supply voltage VDD, and the gate of the reset transistor RST is electrically connected to a pixel drive line LD.

[0047] The source of the amplifier transistor AMP is electrically connected to the drain of the select transistor SEL, the drain of the amplifier transistor AMP is electrically connected to the power supply voltage VDD, and the gate of the amplifier transistor AMP is electrically connected to the source of the switching transistor FDG and the floating diffusion FD.

[0048] The source of the selection transistor SEL, which is the output part of the readout circuit 18, is electrically connected to the vertical pixel line LV, and the gate of the selection transistor SEL is electrically connected to the pixel drive line LD.

[0049] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD.

[0050] The reset transistor RST resets the potential of the floating diffusion FD to a preset potential (e.g., power supply voltage VDD). When the reset transistor RST is turned on, the reset transistor RST resets the potential of the floating diffusion FD to the potential of the power supply voltage VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 18.

[0051] The amplifier transistor AMP amplifies a pixel signal, which is output from the sensor pixel 11 and has a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplifier transistor AMP forms a source follower amplifier, and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD.

[0052] When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing unit 15 (see FIG. 1) via the vertical pixel line LV.

[0053] The switching transistor FDG is used to switch the conversion efficiency. Generally, pixel signals are small when shooting in dark places. Based on Q = CV, when performing charge-voltage conversion, if the capacitance of the floating diffusion FD (hereinafter also referred to as FD capacitance) is large, V when converted to voltage by the amplification transistor AMP will be small.

[0054] On the other hand, in bright places, pixel signals become larger, so unless the FD capacitance is large, the floating diffusion FD cannot receive all the charge from the photodiode PD. Furthermore, the FD capacitance needs to be large so that V does not become too large (in other words, so that it becomes small) when converted to a voltage by the amplification transistor AMP.

[0055] That is, when the switching transistor FDG is turned on, the gate capacitance of the switching transistor FDG increases, and the overall FD capacitance increases. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance decreases. In this way, by switching the state of the switching transistor FDG, the FD capacitance can be made variable, and the conversion efficiency can be changed.

[0056] (Configuration example of unit pixel) Fig. 3 is a plan view showing a configuration example of a unit pixel P of the imaging device 1 according to the first embodiment of the present disclosure. Figs. 4 and 5 are cross-sectional views showing a configuration example of one sensor pixel 11 included in the unit pixel P according to the first embodiment of the present disclosure. Fig. 3 schematically shows a configuration example of the unit pixel P when viewed in plan from the front surface 30a side (i.e., the side opposite to the light incident surface) of the semiconductor substrate 30 (an example of a "first semiconductor substrate" in the present disclosure) shown in Fig. 4.

[0057] In FIG. 3 , in order to illustrate the shapes and relative positions of a first photodiode PDA, a second photodiode PDB, an inter-pixel isolation portion 31, an intra-pixel isolation portion 33, a floating diffusion FD, and an on-chip lens OCL, which will be described later, the transistors shown in FIG. 2 (for example, a transfer transistor TR, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and a switching transistor FDG) are omitted.

[0058] Also, in Figure 3, (R) indicates a sensor pixel 11 in which a red color filter CF is arranged, (G) indicates a sensor pixel 11 in which a green color filter CF is arranged, and (B) indicates a sensor pixel 11 in which a blue color filter CF is arranged.

[0059] 4 and 5 show cross sections of one sensor pixel 11 included in the unit pixel P shown in FIG. 3 taken along line AA' and line BB', respectively.

[0060] 4 and 5 , the pixel array unit 10 includes a semiconductor substrate 30, a planarization film 50, a color filter CF, an on-chip lens OCL, and a multilayer wiring layer (not shown). The semiconductor substrate 30 has a back surface 30b (an example of a "first surface" in the present disclosure) that serves as an incident surface for light L (hereinafter also referred to as a light incident surface), and a front surface 30a located opposite the light incident surface. The semiconductor substrate 30 is made of, for example, a silicon (Si) substrate.

[0061] A plurality of unit pixels P are arranged two-dimensionally in a matrix on the semiconductor substrate 30. Each of the plurality of (e.g., four) sensor pixels 11 constituting the unit pixel P includes a photodiode PD and a transfer transistor TR (see FIG. 2 ). A planarization film 50, a color filter CF, and an on-chip lens OCL are provided in this order on the back surface 30b side, which is the light incident surface of the semiconductor substrate 30. In addition, a multilayer wiring layer (not shown) is provided on the front surface 30a side, which is the opposite side to the light incident surface, with an insulating film (not shown) interposed therebetween.

[0062] As shown in Figures 4 and 5, the photodiode PD has a first photodiode PDA (an example of a "first photoelectric conversion unit" in the present disclosure) and a second photodiode PDB (an example of a "second photoelectric conversion unit" in the present disclosure).

[0063] The first photodiode PDA and the second photodiode PDB are each, for example, a PIN (Positive Intrinsic Negative) type photodiode. The first photodiode PDA is configured with a first impurity region 21 of a first conductivity type (e.g., N-type) and a second impurity region 22 of a second conductivity type (e.g., P-type). In the first photodiode PDA, the first impurity region 21 is disposed in the center, and the second impurity region 22 is disposed along the sides and bottom of the first impurity region 21 (the portion opposite to the side where light L is incident).

[0064] Similarly, the second photodiode PDB is also composed of a first conductivity type (e.g., N type) first impurity region 21 and a second conductivity type (e.g., P type) second impurity region 22. In the second photodiode PDB, the first impurity region 21 is disposed in the center, and the second impurity region 22 is disposed along the sides and bottom of the first impurity region 21 (the portion on the side opposite to the side where light L is incident).

[0065] The semiconductor substrate 30 further has an inter-pixel isolation portion 31 and an intra-pixel isolation portion 33. The inter-pixel isolation portion 31 is provided between adjacent sensor pixels 11. In other words, the inter-pixel isolation portion 31 is provided around the sensor pixel 11.

[0066] As shown in FIG. 3 , the inter-pixel isolation portion 31 is provided in a lattice shape (hereinafter also referred to as a lattice pattern) in a plan view. The inter-pixel isolation portion 31 electrically and optically isolates adjacent sensor pixels 11 from each other. The inter-pixel isolation portion 31 is configured, for example, by a trench penetrating between the front surface 30 a and the back surface 30 b of the semiconductor substrate 30 and a buried film filling the trench. The buried film constituting the inter-pixel isolation portion 31 includes, for example, one or more of a silicon oxide film, a silicon nitride film, an undoped polysilicon (Poly-Si) film, and an undoped amorphous silicon (a-Si) film.

[0067] The intra-pixel isolation portion 33 is provided between the adjacent first photodiode PDA and second photodiode PDB. As described above, the shape of the inter-pixel isolation portion 31 in a plan view (hereinafter also referred to as the planar shape) is a lattice shape. The intra-pixel isolation portion 33 is arranged along the diagonal of a unit cell, which is the smallest unit of this lattice shape. As a result, the intra-pixel isolation portion 33 electrically and optically isolates the adjacent first photodiode PDA and second photodiode PDB.

[0068] 3 and 5 , a slit SL (an example of a “communication portion” in the present disclosure) that communicates between the first photodiode PDA and the second photodiode PDB is provided in the intra-pixel isolation portion 33. The slit SL is provided in the center of the sensor pixel 11 in a plan view.

[0069] The intra-pixel isolation portion 33, excluding the slit SL, is composed of a trench that penetrates between the front surface 30a and the back surface 30b of the semiconductor substrate 30, and a buried film that fills the trench. The buried film that constitutes the intra-pixel isolation portion 33 includes, for example, one or more of a silicon oxide film, a silicon nitride film, an undoped polysilicon (Poly-Si) film, and an undoped amorphous silicon (a-Si) film.

[0070] Each of the sensor pixels 11 includes a first photodiode PDA and a second photodiode PDB for detecting, for example, image plane phase difference information. The first photodiode PDA and the second photodiode PDB function as a pair of phase difference detection pixels during phase difference detection. That is, the phase difference can be detected by detecting the difference (or the ratio of pixel signals) between pixel signals based on charges generated by the pair of first photodiode PDA and second photodiode PDB. This phase difference can be detected as a differential signal by, for example, the signal processing unit 17 shown in FIG. 1 , and the amount of defocus can be calculated based on the detected phase difference, and an imaging lens (not shown) can be adjusted (moved) to achieve autofocus.

[0071] Furthermore, during normal imaging, the slit SL in the intra-pixel isolation portion 33 functions as an overflow path. In each of the multiple sensor pixels 11, when charge in one of the first photodiode PDA and the second photodiode PDB approaches saturation during normal imaging, charge can be transferred from one of the first photodiode PDA and the second photodiode PDB to the other via the slit SL (overflow path), thereby preventing charge saturation. This ensures the linearity of the pixel signal output from each of the multiple sensor pixels 11 and prevents degradation of the captured image.

[0072] The slit SL may be provided from the back surface 30b of the semiconductor substrate 30 to the front surface 30a, or may be provided from the back surface 30b of the semiconductor substrate 30 to a position midway in the thickness direction of the semiconductor substrate 30 (e.g., the Z-axis direction).

[0073] 3, for example, a color filter CF of the same color is arranged for four sensor pixels 11 (i.e., one unit pixel P) arranged in two rows and two columns. Hereinafter, the arrangement of four sensor pixels 11 in two rows and two columns is also referred to as a 2×2 type.

[0074] Furthermore, two color filters CF (see FIGS. 4 and 5 described below) that selectively transmit green light (G) are arranged on a diagonal line, and two color filters CF that selectively transmit red light (R) and blue light (B) are arranged on each diagonal line that is perpendicular to the diagonal line. In the unit pixels P provided with each color filter CF, for example, the corresponding color light is detected by the respective photodiodes PD. That is, in the pixel array section 10, the unit pixels P that respectively detect red light (R), green light (G), and blue light (B) are arranged in a Bayer pattern.

[0075] The on-chip lens 24 is for collecting light L incident from above onto the photodiode PD, and is provided, for example, for each unit pixel P. That is, the on-chip lens 24 is provided across the multiple photodiodes PD in the unit pixel P. In addition, in a plan view, the inter-pixel isolation portion 31 and the boundaries between the multiple on-chip lenses 24 approximately coincide with each other.

[0076] 3 , the floating diffusion FD is disposed in the center of the unit pixel P in a plan view and is surrounded by four sensor pixels 11. In each of the four sensor pixels 11 constituting the unit pixel P, one end of the intra-pixel isolation portion 33 is adjacent to the floating diffusion FD, and the other end of the intra-pixel isolation portion 33 is adjacent to the inter-pixel isolation portion 31.

[0077] Furthermore, P-type contact regions CON connected to the semiconductor substrate 30 are arranged at the four corners of the unit pixel, which has a rectangular planar shape. A reference potential (for example, a ground potential) is supplied to the contact regions CON.

[0078] The contact region CON may be provided in a region other than the four corners of the unit pixel P. For example, as shown in Fig. 3, a contact region CON may be provided at an intermediate position between one contact region CON and the other contact region CON arranged at the corners of the unit pixel P, at a position overlapping with the inter-pixel isolation portion 31 in plan view.

[0079] (Regarding the Inclination of the Pixel Layout) As shown in FIG. 2 , the planar shape of the multiple sensor pixels 11 (or unit pixels P) is rectangular, for example, a square. The directions in which the sensor pixels 11 (or unit pixels P) are arranged with their edges adjacent to each other are defined as a first direction and a second direction. The first direction and the second direction are perpendicular to each other. As shown in FIG. 3 , the intra-pixel separation portion 33 extends in a direction oblique (for example, a direction oblique at 45°) with respect to the first direction and the second direction in which the multiple sensor pixels 11 (or unit pixels P) are arranged.

[0080] Not only the sensor pixels 11 but also the semiconductor substrate 30 have a rectangular planar shape. The first and second directions in which the plurality of sensor pixels 11 (or the plurality of unit pixels P) are arranged are directions that intersect obliquely with the edges 30LH and 30LV, which are the four sides of the periphery of the semiconductor substrate 30 (for example, directions that intersect at an angle of 45°).

[0081] The intra-pixel isolation portion 33 extends in a direction perpendicular or parallel to the four outer periphery sides 30LH and 30LV of the semiconductor substrate 30 .

[0082] In this way, in the imaging device 1 according to the first embodiment of the present disclosure, the pixel layout is tilted by, for example, 45°, which allows for intra-pixel separation for acquiring phase difference information to be performed separately in the horizontal and vertical directions, thereby enabling more accurate autofocus to be achieved.

[0083] (Transistor Arrangement Example) FIG. 6 is a plan view showing a configuration example of a unit pixel P of the imaging device 1 according to the first embodiment of the present disclosure and an arrangement example of transistors in the unit pixel P. FIG. 6 schematically shows a plan view of the unit pixel P viewed from the front surface 30a side of the semiconductor substrate 30. As shown in FIG. 6, each of the plurality of unit pixels P is, for example, a 2×2 type. One reset transistor RST, two selection transistors SEL, two amplification transistors AMP, one switching transistor FDG, and two dummy transistors DMY are arranged in each unit pixel P. The reset transistor RST, the selection transistor SEL, the amplification transistor AMP, the switching transistor FDG, and the dummy transistor DMY are provided on the semiconductor substrate 30.

[0084] For example, the source regions of the two select transistors SEL are connected to each other via a wiring 61 (see FIG. 7 described later). The drain regions of the two select transistors SEL are connected to each other via a wiring (not shown). The gate electrodes of the two select transistors SLE are connected to each other via a wiring (not shown). As a result, the two select transistors SEL essentially operate as a single select transistor SEL.

[0085] For example, the gate electrodes of the two amplifier transistors AMP are connected to each other via a wiring 62 (see FIG. 7 described later). The source regions of the two amplifier transistors AMP are connected to each other via a wiring (not shown). The drain regions of the two amplifier transistors AMP are connected to each other via a wiring (not shown). As a result, the two amplifier transistors AMP essentially operate as a single amplifier transistor AMP.

[0086] The dummy transistor DMY is not connected to any other element and does not output a signal.

[0087] Furthermore, two transfer gates TG of the transfer transistor TR are arranged in each sensor pixel 11. The two transfer gates TG are provided corresponding to the first photodiode PDA and the second photodiode PDB, respectively. This makes it possible, during phase difference detection, to transfer the charges generated by photoelectric conversion in the first photodiode PDA and the charges generated by photoelectric conversion in the second photodiode PDB to the floating diffusion FD at different times.

[0088] 7 is a plan view illustrating the positional relationship between a unit pixel P and vertical pixel wirings LV0 and LV1 in an imaging device 1 according to an embodiment of the present disclosure. As shown in FIG. 7 , the vertical pixel wirings LV0 and LV1 are arranged at positions overlapping the unit pixel P in a planar view, with an insulating film (not shown) interposed therebetween. The vertical pixel wirings LV0 and LV1 are part of the multiple vertical pixel wirings LV shown in FIG. 1 . For example, the vertical pixel wiring LV0 is connected to the source region of the selection transistor SEL of the unit pixel P that detects green light (G). The vertical pixel wiring LV1 is connected to the source region of the selection transistor SEL of the unit pixel P that detects red light (R) and the source region of the selection transistor SEL of the unit pixel P that detects blue light (B).

[0089] The vertical pixel wirings LV0 and LV1 extend in a direction that is horizontal or perpendicular to the intra-pixel isolation portion 33, for example, in the Y-axis direction. In other words, the intra-pixel isolation portion 33 extends in a direction that is vertical or horizontal to the vertical pixel wirings LV0 and LV1. The vertical pixel wirings LV0 and LV1 also extend in a direction that is oblique at 45° with respect to the first direction or the second direction in which the multiple sensor pixels 11 are arranged. Although not shown, the vertical pixel wirings LV0 and LV1 are arranged alternately in the X-axis direction.

[0090] 7 , the wiring 61 connecting the source regions of the two select transistors SEL intersects with the vertical pixel wirings LV0 and LV1 in a plan view. The wiring 61 and the vertical pixel wirings LV0 and LV1 are on different layers, and an insulating film (not shown) is interposed between the wiring 61 and the vertical pixel wirings LV0 and LV1. For example, in an intersection region 63 where the wiring 61 intersects with the vertical pixel wiring LV0, the wiring 61 and the vertical pixel wiring LV0 are connected via a via (not shown). Similarly, in an intersection region 63 where the wiring 61 intersects with the vertical pixel wiring LV1, the wiring 61 and the vertical pixel wiring LV1 are connected via a via (not shown).

[0091] Comparative Example FIG. 8 is a plan view showing the configuration of a unit pixel P′ of an imaging device 901 according to a comparative example of the present disclosure. FIG. 9 is a plan view showing the configuration of a unit pixel P′ of an imaging device 901 according to a comparative example of the present disclosure and the arrangement of transistors in the unit pixel P′. As shown in FIGS. 8 and 9 , in the unit pixel P′ according to the comparative example, a sensor pixel 911 having a square planar shape is divided into two rectangular parts in order to detect image plane phase difference information. The intra-pixel separator 933 dividing the sensor pixel 911 into two parts extends in a direction that is horizontal or perpendicular to the first direction and the second direction in which the multiple sensor pixels 911 (or the multiple unit pixels P′) are arranged. The extension direction of the intra-pixel separator 933 is not oblique to the first direction or the second direction.

[0092] 9 , in the unit pixel P′ according to the comparative example, a reset transistor RST, a selection transistor SEL, an amplification transistor AMP, and a switching transistor FDG are arranged at four corners of the unit pixel P′. In addition, a contact region CON is provided at an intermediate position between one transistor and the other transistor arranged at the corners of the unit pixel P′, at a position overlapping with the inter-pixel isolation portion 931 in plan view.

[0093] (Comparison) The image pickup device 1 according to the first embodiment of the present disclosure and the image pickup device 901 according to the comparative example differ in the following respects: (1) The first photodiode PDA and the second photodiode PDB constituting the sensor pixel 11 are each separated by an intra-pixel separation portion 33. In addition, the first photodiode PDA and the second photodiode PDB are each provided with a transfer transistor TR that transfers charges generated by photoelectric conversion to the floating diffusion FD. Therefore, the first photodiode PDA and the second photodiode PDB each function as a single pixel.

[0094] In the image pickup device 1 according to the first embodiment, the unit pixel P is made up of eight pixels (i.e., four first photodiodes PDA and four second photodiodes PDB, for a total of eight pixels), and one floating diffusion FD is arranged corresponding to each of the eight pixels. In other words, the image pickup device 1 has an 8-pixel-1 FD structure.

[0095] In contrast, in the image pickup device 901 according to the comparative example, the unit pixel P' is composed of eight pixels, and there are two floating diffusions FD in the unit pixel P' composed of eight pixels. The image pickup device 901 has a four-pixel-one-FD structure. Note that, as shown in FIG. 8 , the two floating diffusions FD in the unit pixel P' are connected to each other via a wiring 964.

[0096] In the imaging device 1 according to the first embodiment, one floating diffusion FD is shared by eight pixels, so the load capacitance is small and it is possible to increase the conversion efficiency.

[0097] (2) In the imaging device 1 of embodiment 1, the distance D-FD between the floating diffusion FD included in one adjacent unit pixel P and the floating diffusion FD included in the other adjacent unit pixel P (hereinafter also referred to as the distance between adjacent FDs) can be made longer than in the imaging device 901 of the comparative example.

[0098] 6 and 9, if the distance between adjacent FDs in the image capture device 1 according to the first embodiment is D-FD and the distance between adjacent FDs in the image capture device 901 according to the comparative example is D-FD', then D-FD>D-FD'. The image capture device 1 according to the first embodiment has a longer distance between adjacent FDs than the image capture device 901 according to the comparative example.

[0099] Furthermore, for the vertical pixel wirings LV connected to the source electrodes of the selection transistors SEL, the distance between adjacent vertical pixel wirings LV0 and LV1 is defined as the distance between adjacent LVs. The imaging device 1 according to the first embodiment has a longer distance between adjacent LVs than the imaging device 901 according to the comparative example. For example, assume that the unit pixels P and P' have square planar shapes and are the same size. In this case, if the distance between adjacent LVs in the comparative example is 1, the distance between adjacent LVs in the first embodiment is √2. In other words, the distance between adjacent LVs in the first embodiment can be made √2 times larger than that in the comparative example.

[0100] In this way, the imaging device 1 according to the first embodiment can reduce crosstalk by increasing the distance between adjacent FDs and by increasing the distance between adjacent LVs.

[0101] (3) In the imaging device 1 according to the first embodiment, the intra-pixel separation portion 33 extends in the X-axis direction and the Y-axis direction. This allows the imaging device 1 according to the first embodiment to acquire phase difference information in both the horizontal and vertical directions. On the other hand, in the imaging device 901 according to the comparative example, the intra-pixel separation portion 933 extends only in the Y-axis direction. Therefore, the imaging device 901 according to the comparative example can acquire phase difference information in the horizontal direction, but cannot acquire phase difference information in the vertical direction.

[0102] (4) The imaging device 1 according to the first embodiment has an 8-pixel-1-FD structure, and the floating diffusion FD can be disposed at the center of the unit pixel P. This allows for greater flexibility in the layout of transistors (hereinafter also referred to as pixel transistors) such as the reset transistor RST, selection transistor SEL, amplification transistor AMP, and switching transistor FDG included in the readout circuit 18. This can be expected to increase (expand) the saturation signal due to improved layout efficiency.

[0103] On the other hand, the image pickup device 901 according to Comparative Example 1 has a four-pixel-one-FD structure. Two floating diffusions are arranged within a unit pixel P'. In the image pickup device 901 according to Comparative Example 1, the floating diffusions FD are arranged in two locations, which reduces the degree of freedom in the layout of the pixel transistors.

[0104] Effect of First Embodiment As described above, the imaging device 1 according to the first embodiment of the present disclosure includes a semiconductor substrate 30 having a back surface 30b that is a light incident surface and a front surface 30a located on the opposite side of the back surface 30b, a plurality of sensor pixels 11 provided on the semiconductor substrate 30, and an inter-pixel separation portion 31 provided on the semiconductor substrate 30 and separating adjacent ones of the plurality of sensor pixels 11 from each other. In a plan view from the thickness direction of the semiconductor substrate 30, each of the plurality of sensor pixels 11 has a rectangular shape. The plurality of sensor pixels 11 are arranged side by side in a first direction and a second direction intersecting the first direction, with the inter-pixel separation portion 31 interposed therebetween and with their edges adjacent to each other. Each of the plurality of sensor pixels 11 has a first photodiode PDA that photoelectrically converts light incident from the back surface 30 b, a second photodiode PDB that is adjacent to the first photodiode PDA and photoelectrically converts light incident from the back surface 30 b, and an intra-pixel isolation portion 33 that isolates the first photodiode PDA from the second photodiode PDB. The intra-pixel isolation portion 33 extends in a direction oblique to each of the first direction and the second direction.

[0105] For example, each of the multiple sensor pixels 11 has a square shape in plan view. The intra-pixel isolation portions 33 extend in directions that are oblique at 45° with respect to both the first direction and the second direction. The semiconductor substrate 30 has a rectangular shape in plan view. The intra-pixel isolation portions 33 extend in directions that are perpendicular or horizontal to the four outer periphery sides (edges 30LH, 30LV) of the semiconductor substrate 30.

[0106] According to this, the extension directions of the intra-pixel isolation portion 33 are the horizontal and vertical directions in a plan view, and the first photodiode PDA and the second photodiode PDB are arranged adjacent to each other in the horizontal or vertical direction via the intra-pixel isolation portion 33. This allows the imaging device 1 to acquire phase difference information in both the horizontal and vertical directions.

[0107] Furthermore, the vertical pixel wirings LV0 and LV1 can be extended in directions oblique (for example, 45° oblique) with respect to the first and second directions in which the plurality of sensor pixels 11 are arranged. This allows the distance between adjacent vertical pixel wirings LV0 and LV1 to be longer than when the vertical pixel wirings LV0 and LV1 are extended in directions horizontal or perpendicular to the first and second directions, making it possible to suppress crosstalk between the vertical pixel wirings LV0 and LV1. From the above, it is possible to improve the performance of the imaging device 1.

[0108] (Modifications of Embodiment 1) (1) Modification 1 FIG. 10 is a plan view showing the configuration of an imaging device 1A (an example of the "photodetection device" of the present disclosure) according to Modification 1 of Embodiment 1 of the present disclosure. In the above-described Embodiment 1, as shown in FIG. 6, for example, pixel transistors such as the reset transistor RST, the selection transistor SEL, the amplification transistor AMP, and the switching transistor FDG are arranged along the periphery of the unit pixel P. However, in the embodiments of the present disclosure, the arrangement of the pixel transistors is not limited to this. For example, as shown in FIG. 10, the pixel transistors do not have to be arranged along the periphery of the unit pixel P. The pixel transistors may be arranged in the center of the sensor pixel 11 in a plan view.

[0109] Furthermore, in the above-described first embodiment, for example, as shown in FIG. 6 , the slit SL of the intra-pixel separation portion 33 is disposed in the center of the sensor pixel 11. However, in the embodiments of the present disclosure, the arrangement of the slit SL is not limited to this. For example, as shown in FIG. 10 , the slit SL may be disposed near the outer periphery of the unit pixel P. The slit SL may be disposed on the opposite side of the floating diffusion FD across the pixel transistor in a plan view. Even in such an arrangement, the same effects as those of the above-described first embodiment can be achieved.

[0110] 11 is a plan view showing a configuration of an image pickup device 1B (an example of a "photodetector" of the present disclosure) according to Modification 2 of Embodiment 1 of the present disclosure. As shown in Fig. 11 , in the image pickup device 1B according to Modification 2 of Embodiment 1, at least a part of the gate electrode TG of the transfer transistor TR (see Fig. 1) is a buried gate VG buried inside the semiconductor substrate 30 from the front surface 30a (see Fig. 5) side of the semiconductor substrate 30.

[0111] This embodiment provides the same effects as those of the above-described embodiment 1. Furthermore, since at least a part of the gate electrode TG of the transfer transistor TR is the buried gate VG, it is expected that the efficiency of charge transfer from the photodiode PD (see FIG. 1 ) to the floating diffusion FD can be improved.

[0112] <Embodiment 2> In an embodiment of the present disclosure, the imaging device may have a stacked structure in which multiple semiconductor substrates are stacked. (Configuration example in cross section) Figure 12 is a cross-sectional view showing an example of the stacked structure of an imaging device 1C (an example of the "photodetector" of the present disclosure) according to embodiment 2 of the present disclosure. First, the stacked structure of the imaging device 1C will be described using a cross-sectional view.

[0113] As shown in FIG. 12 , in the imaging device 1C according to the second embodiment, the semiconductor substrate 30 of the first substrate unit 110 is provided with a photodiode PD, a well region 114 in which the channel of the transfer transistor TR is formed, a contact region CON connected to the well region 114, and a floating diffusion FD corresponding to the drain of the transfer transistor TR. The photodiode PD has, for example, an N-type impurity diffusion layer and a P-type impurity diffusion layer forming a PN junction with the N-type impurity diffusion layer. The well region 114 and the contact region CON are, for example, P-type impurity diffusion layers. The contact region CON has a higher P-type impurity concentration than the well region 114. The floating diffusion FD is an N-type impurity diffusion layer. Furthermore, a transfer gate TG, which is the gate electrode of the transfer transistor TR, is provided on the semiconductor substrate 30 via a gate insulating film.

[0114] A first insulating film 161 is provided on the semiconductor substrate 30. The transfer gate TG is covered with the first insulating film 161. A first wiring layer 117 and a second insulating film 162 are provided on the first insulating film 161. The first wiring layer 117 is covered with the second insulating film 162. In addition, a third insulating film 163 is provided on the second insulating film 162.

[0115] The second substrate unit 120 is bonded to the first substrate unit 110. For example, the third insulating film 163 of the first substrate unit 110 and the fourth insulating film 143 of the second substrate unit 120 are bonded to each other. The fourth insulating film 143 is, for example, a silicon oxide film (SiO ２ It is composed of a membrane.

[0116] Pixel transistors such as a reset transistor RST, a switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL (see FIG. 1) are provided on the semiconductor substrate 121 of the second substrate unit 120. A dummy transistor DMY (see FIG. 7) may also be provided on the second substrate unit 120. In FIG. 12, the amplification transistor AMP is illustrated as an example of a pixel transistor.

[0117] As shown in FIG. 12, the amplification transistor AMP has a semiconductor layer 211 that serves as a channel region, a gate electrode AG that covers the semiconductor layer 211, and a gate insulating film 142 that is arranged between the semiconductor layer 211 and the gate electrode AG.

[0118] The semiconductor layer 211 is, for example, a part of the semiconductor substrate 121 (an example of a "second semiconductor substrate" in the present disclosure) and is made of single-crystal silicon. The semiconductor layer 211 is a portion formed by etching a part of the upper surface side of the semiconductor substrate 121. The shape of the semiconductor layer 211 is, for example, a fin shape. The fin shape is, for example, a rectangular parallelepiped shape that is long in the gate length direction and short in the gate width direction perpendicular to the gate length direction.

[0119] 12, the gate insulating film 142 is provided so as to continuously cover the upper surface and both left and right side surfaces of the semiconductor layer 211. The gate insulating film 142 is made of, for example, a silicon oxide film (SiO ２ The gate electrode AG is provided so as to continuously cover the upper surface and both left and right side surfaces of the semiconductor layer 211 via the gate insulating film 142. The gate electrode AG is made of, for example, a polysilicon (Poly-Si) film.

[0120] As a result, the gate electrode AG can simultaneously apply a gate voltage to the top surface and both left and right side surfaces of the semiconductor layer 211. In other words, the gate electrode AG can simultaneously apply a gate voltage to the semiconductor layer 211 from a total of three directions, namely, the top side and both left and right sides. As a result, the gate electrode AG can completely deplete the semiconductor layer 211.

[0121] The source region and drain region of the amplifier transistor AMP are provided in a region of the semiconductor layer 211 that is exposed from under the gate electrode AG. In the gate length direction of the amplifier transistor AMP, the source region is connected to one side of the semiconductor layer 211 where a channel is formed, and the drain region is connected to the other side of the semiconductor layer 211 where the channel is formed. The conductivity type of the source region and drain region is, for example, N type.

[0122] The amplification transistor AMP is not limited to a FinFET (Fin Field Effect Transistor) in which the semiconductor layer 211 in which a channel is formed is formed in a fin shape. The amplification transistor AMP may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a planar gate structure in which a channel is formed only on the surface of the semiconductor substrate 121 and in the vicinity thereof.

[0123] In the second substrate unit 120, the reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL are isolated from one another by a fifth insulating film 145, and are covered with a sixth insulating film 146. The fifth insulating film 145 is, for example, a silicon oxide film (SiO ２ The sixth insulating film 146 is made of, for example, SiO ２ The insulating film is made of a silicon nitride film (SiN film), or a laminate of these.

[0124] A plurality of through holes are provided in the first insulating film 161, the second insulating film 162, the third insulating film 163, the fourth insulating film 164, the fifth insulating film 145, and the sixth insulating film 146. Through wirings 151 and 152 are provided in these through holes. In addition, a second wiring layer 153 is provided on the sixth insulating film 146. The gate electrode AG of the amplification transistor AMP is connected to the source of the reset transistor RST and the floating diffusion FD of the first substrate unit 110 via the through wiring 151 and the second wiring layer 153.

[0125] In the first substrate unit 110, a color filter CF and an on-chip lens OCL (see FIGS. 4 and 5) are arranged on the side opposite to the surface to which the second substrate unit 120 is bonded.

[0126] (Configuration Example in Plan View) Next, a configuration example in plan view of an image pickup device 1C according to Embodiment 2 of the present disclosure will be described. Fig. 13 is a plan view showing a configuration example of the first substrate unit 110 of the image pickup device 1C according to Embodiment 2 of the present disclosure. As shown in Fig. 13, the configuration of the first substrate unit 110 of the image pickup device 1C according to Embodiment 2 is similar to the configuration of the substrate unit (including the semiconductor substrate 30) of the image pickup device 1 shown in Fig. 6, except that the reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL are not arranged.

[0127] That is, also in the imaging device 1C according to the second embodiment, the planar shape of the plurality of sensor pixels 11 (or unit pixels P) is rectangular, for example, a square. If the directions in which the sensor pixels 11 (or unit pixels P) are arranged with their edges adjacent to each other are defined as a first direction and a second direction, the first direction and the second direction are orthogonal to each other. As shown in Fig. 13 , the intra-pixel separation portion 33 extends in a direction oblique (for example, a direction oblique at 45°) with respect to the first direction and the second direction in which the plurality of sensor pixels 11 (or unit pixels P) are arranged.

[0128] 14 is a plan view illustrating the positional relationship between a unit pixel P and a reference potential wiring GND in an imaging device 1C according to the second embodiment of the present disclosure. The reference potential wiring GND is a wiring connected to a reference potential (e.g., a ground potential). As shown in FIG. 14 , the reference potential wiring GND is disposed at a position overlapping the unit pixel P in a plan view with an insulating film (not shown) interposed therebetween.

[0129] The extension direction of each of the reference potential wirings GND is a direction horizontal or perpendicular to the intra-pixel isolation portion 33 provided on the semiconductor substrate 30 of the first substrate unit 110, for example, in the Y-axis direction. The reference potential wirings GND extend in a direction oblique at 45° with respect to the first direction or the second direction in which the plurality of sensor pixels 11 are arranged. Although not shown, the reference potential wirings GND are arranged alternately in the X-axis direction.

[0130] 14, the contact region CON is connected to the reference potential wiring GND via a wiring 64. The wiring 64 and the reference potential wiring GND are on different layers, and an insulating film (not shown) is interposed between the wiring 64 and the reference potential wiring GND. For example, in the intersection region where the wiring 64 and the vertical pixel wiring LV0 intersect, the wiring 64 and the reference potential wiring GND are connected via a via (not shown). As a result, the contact region CON is fixed to a reference potential (e.g., ground potential) via the reference potential wiring GND and the wiring 64.

[0131] The reference potential wiring GND may be provided in the first substrate part 110 or in the second substrate part 120 (see FIG. 12 ). At least a part of the wiring 64 connecting the reference potential wiring GND and the contact region CON is configured by, for example, a through wiring 151 and a second wiring layer 153 (see FIG. 12 ).

[0132] 15 is a plan view illustrating the positional relationship between a unit pixel P and vertical pixel wirings LV0 and LV1 in an image pickup device 1C according to Embodiment 2 of the present disclosure. As shown in Fig. 15 , in the image pickup device 1C according to Embodiment 2 as well, the vertical pixel wirings LV0 and LV1 are arranged at positions overlapping with the unit pixel P in a plan view via an insulating film (not shown).

[0133] The vertical pixel wirings LV0 and LV1 extend in a direction that is horizontal or perpendicular to the intra-pixel isolation portion 33 provided on the semiconductor substrate 30 of the first substrate unit 110, for example, in the Y-axis direction. The vertical pixel wirings LV0 and LV1 extend in a direction that is oblique at 45° with respect to the first direction or the second direction in which the plurality of sensor pixels 11 are arranged. Although not shown, the vertical pixel wirings LV0 and LV1 are arranged alternately in the X-axis direction.

[0134] The vertical pixel lines LV0 and LV1 may be provided on the first substrate unit 110 or on the second substrate unit 120 (see FIG. 12).

[0135] 16 is a plan view showing an example of the arrangement of pixel transistors in a unit pixel P in an image pickup device 1C according to the second embodiment of the present disclosure. As shown in Fig. 16, for example, one reset transistor RST, one selection transistor SEL, one amplification transistor AMP, and one switching transistor FDG are arranged in each unit pixel P.

[0136] In the imaging device 1C according to the second embodiment, the reset transistor RST, the selection transistor SEL, the amplification transistor AMP, and the switching transistor FDG are provided on the semiconductor substrate 121 of the second substrate unit 120 (see FIG. 12).

[0137] The floating diffusion FD and the transfer transistor TR are provided on the semiconductor substrate 30 (see FIG. 12) of the first substrate unit 110. At least a portion of the wiring 62 connecting the floating diffusion FD and the gate electrode of the amplification transistor AMP is configured by, for example, a through wiring 151 and a second wiring layer 153 (see FIG. 12).

[0138] 17 is a plan view illustrating the relative positions of a unit pixel P including a pixel transistor, the vertical pixel wirings LV0 and LV1, and the reference potential wiring GND in an image pickup device 1C according to the second embodiment of the present disclosure. As shown in Fig. 17, the reference potential wiring GND is disposed between the vertical pixel wirings LV0 and LV1 in a plan view. In addition, in the thickness direction of the image pickup device 1C (e.g., the Z-axis direction), the reference potential wiring GND is disposed between the pixel transistor and the semiconductor substrate 30 (see Fig. 12) of the first substrate unit 110 via an insulating film.

[0139] 17, the source region of the select transistor SEL and the vertical pixel wirings LV0 and LV1 are connected via wiring 61. At least a part of the wiring 61 is formed of, for example, the first wiring layer 117 or the second wiring layer 153 (see FIG. 12).

[0140] (Effects of Second Embodiment) As described above, the imaging device 1C according to the second embodiment of the present disclosure includes: a semiconductor substrate 121 bonded to the front surface 30a side of the semiconductor substrate 30 via the first insulating film 161, the second insulating film 162, the third insulating film 163, etc.; an amplification transistor AMP provided on the semiconductor substrate 121 and configured to amplify a voltage signal corresponding to the level of charge output from the sensor pixel 11; a selection transistor SEL provided on the semiconductor substrate 121 and configured to control the output timing of the signal from the amplification transistor AMP; and a reset transistor RST provided on the semiconductor substrate 121 and configured to reset the potential of the floating diffusion FD to a predetermined potential (for example, a power supply voltage VDD). The amplification transistor AMP, the selection transistor SEL, and the reset transistor RST are arranged for each unit pixel P.

[0141] This improves the degree of freedom in the layout of pixel transistors such as the amplifier transistor AMP, the select transistor SEL, and the reset transistor RST. For example, at least a portion of the pixel transistor can be arranged in a position overlapping the photodiode PD or the transfer transistor TR in a planar view. This increases the proportion of the area of ​​the semiconductor substrate 30 occupied by the photodiode PD, which is expected to increase the amount of saturation signal. In addition, it becomes easier to increase the size of the amplifier transistor, which is expected to reduce noise.

[0142] (Modifications of Embodiment 2) (1) Modification 1 FIG. 18 is a plan view showing the configuration of an image pickup device 1D (an example of the "photodetector" of the present disclosure) according to Modification 1 of Embodiment 2 of the present disclosure. As shown in FIG. 18 , the image pickup device 1D according to Modification 1 of Embodiment 2 of the present disclosure has a wiring 65 that extends from the transfer gate TG in a horizontal direction parallel to the surface of the semiconductor substrate. This wiring 65 is made of, for example, polysilicon (Poly-Si). The wiring 65 may be made of only the first wiring layer 117 provided in the first substrate unit 110. Alternatively, the wiring 65 may be made of a through-wiring that penetrates the insulating films (e.g., the first insulating film 161, the second insulating film 162, and the third insulating film 163) of the first substrate unit 110 and the second substrate unit 120, and the second wiring layer 153.

[0143] In this embodiment, it is possible to improve the degree of freedom in the layout of the wiring connected to the transfer gate TG (for example, the pixel drive line LD shown in FIG. 1 ). Furthermore, by changing the layout of the wiring connected to the transfer gate TG, it is possible to improve the degree of freedom in the layout of other wiring (for example, the vertical pixel wirings LV0, LV0, the reference potential wiring GND, the wiring for supplying the power supply voltage VDD, etc.).

[0144] 19 is a plan view showing an example layout of vertical pixel wirings LV0 and LV1 in an image pickup device 1D according to a first modification of the second embodiment of the present disclosure. As shown in FIG. 19 , in the image pickup device 1D, the vertical pixel wirings LV0 and LV1 may be arranged to pass through a position that overlaps (e.g., directly above) the source region of the select transistor SEL in a planar view. Furthermore, the source region of the select transistor SEL and the vertical pixel wirings LV0 and LV1 located directly above it may be connected via a via 66. This allows the length of the wiring connecting the source region of the select transistor SEL to the vertical pixel wirings LV0 and LV1 to be shortened.

[0145] 20 is a plan view showing an example layout of the reference potential wiring GND in an image pickup device 1D according to Modification 1 of Embodiment 2 of the present disclosure. As shown in Fig. 20, in the image pickup device 1D, the reference potential wiring GND may be arranged so as to pass through a position overlapping with (e.g., directly above) the contact region CON in a plan view or in the vicinity thereof. Fig. 20 illustrates a case where the reference potential wiring GND is arranged so as to pass through the vicinity of directly above the contact region CON.

[0146] When the reference potential wiring GND passes directly above the contact region CON, the wiring 64 connecting the reference potential wiring GND and the contact region CON may be formed only by a via, or may be formed only by a through wiring 152 (see FIG. 12). Furthermore, when the reference potential wiring GND passes near directly above the contact region CON, the wiring 64 connecting the reference potential wiring GND and the contact region CON may be formed by a via and the first wiring layer 117 (see FIG. 12), or may be formed by the through wiring 152 and the second wiring layer 153. This allows the length of the wiring 64 connecting the contact region CON and the reference potential wiring GND to be shortened.

[0147] (2) Modification 2 FIG. 21 is a plan view illustrating a configuration of an imaging device 1E (an example of a “photodetector” of the present disclosure) according to Modification 2 of Embodiment 2 of the present disclosure. As illustrated in FIG. 21 , the source regions or drain regions of pixel transistors such as the reset transistor RST, the switching transistor FDG, the amplifier transistor AMP, and the selection transistor SEL may be arranged so as not to face each other across the gate electrode in a planar view. For example, one of the source region and the drain region of the pixel transistor may be arranged vertically relative to the gate electrode, and the other may be arranged horizontally relative to the gate electrode. FIG. 21 illustrates a case in which the source region of the amplifier transistor AMP (which is also the drain region of the selection transistor SEL) is arranged vertically relative to the gate electrode of the amplifier transistor AMP, and the drain region of the amplifier transistor AMP is arranged horizontally relative to the gate electrode of the amplifier transistor AMP. FIG. 21 also illustrates a case in which the source region of the reset transistor RST (which is also the drain region of the switching transistor FDG) is arranged vertically relative to the gate electrode of the reset transistor RST, and the drain region of the reset transistor RST is arranged horizontally relative to the gate electrode of the reset transistor RST. In this case, it is possible to widen the gate width of the pixel transistor.

[0148] For example, in the above-described first and second embodiments, a unit pixel P in which a color filter CF of the same color is arranged is configured of four sensor pixels 11 arranged in two rows and two columns (i.e., a 2×2 type). However, in the embodiments of the present disclosure, the unit pixel P is not limited to the 2×2 type.

[0149] 22 is a plan view showing a configuration example of an imaging device 1F (an example of a "photodetection device" of the present disclosure) according to a third embodiment of the present disclosure. As shown in FIG. 22, the unit pixel P may be composed of 16 sensor pixels 11 arranged in, for example, 4 rows and 4 columns. Alternatively, the unit pixel P may be composed of, for example, 2n rows and 2n columns (2n) ２ The number of sensor pixels 11 may be n, where n is an integer of 1 or more.

[0150] Fourth Embodiment Fig. 23 is a plan view showing a configuration example of a sensor pixel 11 included in an imaging device 1G according to a fourth embodiment of the present disclosure. The sensor pixel 11 shown in Fig. 23 has, for example, a square planar shape and has an intra-pixel isolation portion 33 on its diagonal. The intra-pixel isolation portion 33 is arranged to pass through the center of the sensor pixel 11 (i.e., the center of the square) in a planar view. Although not shown in Fig. 23 , a first photodiode PDA (an example of a "first photoelectric conversion portion" of the present disclosure; see Fig. 4 and Fig. 25A described later, etc.) and a second photodiode PDB (an example of a "second photoelectric conversion portion" of the present disclosure; see Fig. 4 and Fig. 25A described later, etc.) are arranged on both sides of the intra-pixel isolation portion 33.

[0151] Light incident on the sensor pixel 11 from the back surface 30b (see FIG. 4 ) side of the semiconductor substrate 30 is condensed by the on-chip lens OCL to the center of the sensor pixel 11. Therefore, in the intra-pixel separation portion 33, light is scattered mainly in a portion 33C (hereinafter also referred to as the center) located at the center of the sensor pixel 11. As shown by the arrows in FIG. 23 , the main scattering direction of light is orthogonal to the extension direction of the intra-pixel separation portion 33 (i.e., the direction of the diagonal of the square, which is an oblique direction intersecting with the inter-pixel separation portion 31 at an angle of 45°) in a plan view.

[0152] 24 is a plan view showing a configuration example of a sensor pixel 911 according to a comparative example of the present disclosure. In the sensor pixel 911, the intra-pixel separation portion 933 is disposed so as to pass through the center of the sensor pixel 911 and to be parallel or perpendicular to the inter-pixel separation portion 931. In the comparative example, too, the on-chip lens OCL collects light at the center of the sensor pixel 911, and light is scattered at a center portion 933C of the intra-pixel separation portion 933. The main scattering direction of light is a direction orthogonal to the extension direction of the intra-pixel separation portion 33 in plan view, as indicated by the arrow in FIG. 24 .

[0153] Here, as shown in Fig. 23 , the distance from the center 33C of the intra-pixel separation portion 33 to the pixel boundary along the light scattering direction is defined as A. Also, as shown in Fig. 24 , the distance from the center 933C of the intra-pixel separation portion 933 to the pixel boundary along the light scattering direction is defined as B. Distance A is longer than distance B. If the planar shapes of the sensor pixels 11 and 911 are square and have the same size (area), distance A is √2 times the length of distance B. Therefore, the sensor pixel 11 shown in Fig. 23 is less likely to allow scattered light to reach adjacent pixels than the sensor pixel 911 shown in Fig. 24 , and color mixing due to scattered light can be suppressed.

[0154] Below, several specific examples will be shown of the configurations of the sensor pixel 11 capable of suppressing color mixing and the unit pixel P having the sensor pixel 11.

[0155] (1) Specific Example 1 (2×2 Type) Specific Example 1 of Embodiment 4 shows variations of 2×2 type arrangement examples. Figures 25A to 25I are plan views schematically showing 2×2 type arrangement examples (Nos. 1 to 9) of unit pixels P of an imaging device 1G according to Embodiment 4 of the present disclosure. Figure 25A shows the same arrangement example as the unit pixel P of the imaging device 1 shown in Figure 3.

[0156] 25A , four sensor pixels 11 are arranged in 2×2 rows to form one unit pixel P. Each sensor pixel 11 has a square planar shape. The directions in which the sensor pixels 11 are arranged with their edges adjacent to each other are defined as a first direction and a second direction. The first direction and the second direction are orthogonal to each other. The intra-pixel separator 33 extends in a direction oblique to the first direction and the second direction in which the multiple sensor pixels 11 are arranged (for example, a direction oblique at 45°).

[0157] In Figure 25A, the extension directions of the intra-pixel separator 33 are the horizontal and vertical directions in a plan view. The first photodiode PDA and the second photodiode PDB are arranged adjacent to each other in the horizontal or vertical direction via the intra-pixel separator 33. This allows the imaging device 1G to acquire phase difference information in both the horizontal and vertical directions. Furthermore, as described with reference to Figures 23 and 24, by arranging the intra-pixel separator 33 on the diagonal of the sensor pixel 11, color mixing due to scattered light can be suppressed.

[0158] One on-chip lens OCL is disposed for each sensor pixel 11. The planar shape of the on-chip lens OCL is a perfect circle (or an approximately perfect circle). The on-chip lens OCL is disposed so as to cover the intra-pixel isolation portion 33 and the first photodiode PDA and second photodiode PDB located on both sides of the intra-pixel isolation portion 33. In addition, color filters (not shown) of the same color are disposed for four sensor pixels 11 (i.e., one unit pixel P) arranged in two rows and two columns. As shown in FIG. 4 , the color filter CF is disposed between the on-chip lens OCL and the back surface 30b of the semiconductor substrate 30, on which the first photodiode PDA and second photodiode PDB are provided.

[0159] 25A to 25I, similar to the unit pixel P of the imaging device 1 shown in FIG. 3, in the imaging device 1G, a floating diffusion FD is disposed in the center of the unit pixel P in a plan view, and is surrounded by four sensor pixels 11. In each of the four sensor pixels 11 constituting the unit pixel P, one end of the intra-pixel isolation portion 33 is adjacent to the floating diffusion FD, and the other end of the intra-pixel isolation portion 33 is adjacent to the inter-pixel isolation portion 31.

[0160] 25A to 25I, the intra-pixel isolation portion 33 of the imaging device 1G may also be provided with a slit SL (an example of a "communicating portion" of the present disclosure) shown in FIG. 3, similar to the unit pixel P of the imaging device 1 shown in FIG. 3. The slit SL functions as an overflow path during normal imaging. Charge can be transferred from one of the first photodiode PDA and the second photodiode PDB to the other via the slit SL, thereby preventing charge saturation. This ensures the linearity of the pixel signal output from each of the multiple sensor pixels 11 and prevents degradation of the captured image.

[0161] 25B , the extension direction of the intra-pixel separator 33 may be only the vertical direction in a plan view. The first photodiode PDA and the second photodiode PDB are arranged adjacent to each other in the horizontal direction via the intra-pixel separator 33. This allows the imaging device 1G to acquire phase difference information in the horizontal direction. Furthermore, by arranging the intra-pixel separator 33 on the diagonal of the sensor pixel 11, color mixing due to scattered light can be suppressed.

[0162] 25C , the extension direction of the intra-pixel separator 33 may be only the horizontal direction in a plan view. The first photodiode PDA and the second photodiode PDB are arranged adjacent to each other in the vertical direction via the intra-pixel separator 33. This allows the imaging device 1G to acquire phase difference information in the vertical direction. Furthermore, by arranging the intra-pixel separator 33 on the diagonal of the sensor pixel 11, color mixing due to scattered light can be suppressed.

[0163] As shown in FIG. 25D , the unit pixel P may be composed of two sensor pixels 11 each having a square planar shape and one sensor pixel 11A each having a rectangular planar shape. For example, this rectangle has a long side twice the length of its short side, and has an area twice that of the sensor pixel 11. The sensor pixel 11A includes a first photodiode PDA, a second photodiode PDB, and an intra-pixel isolation portion 33 interposed between the first photodiode PDA and the second photodiode PDB. An on-chip lens OCLA having an elliptical planar shape is provided on the sensor pixel 11A having a rectangular planar shape. The long side direction of the rectangle and the longitudinal direction of the ellipse (i.e., the direction in which the diameter is greatest) coincide (or nearly coincide). In the sensor pixel 11A, the intra-pixel isolation portion 33 is disposed on a diagonal line of the rectangle and extends in a diagonal direction intersecting the horizontal and vertical directions in a plan view. Even in this configuration, the imaging device 1G can acquire phase difference information in directions (for example, vertical and horizontal directions in the sensor pixel 11, and diagonal directions in the sensor pixel 11A) that are orthogonal in plan view to the extension direction of the intra-pixel separator 33. Furthermore, by arranging the intra-pixel separator 33 on the diagonal lines of the sensor pixels 11 and 11A, color mixing due to scattered light can be suppressed.

[0164] Note that the unit pixel P shown in Fig. 25D is not strictly a 2x2 type because it is composed of a total of three pixels. However, because the rectangular sensor pixel 11A has an area twice that of the square sensor pixel 11, and because the planar shape of the unit pixel P shown in Fig. 25D is square and its area is the same as that of the 2x2 type unit pixel P shown in Fig. 25A etc., the unit pixel P shown in Fig. 25D is also classified as a 2x2 type in this specification. The same applies to the unit pixels P shown in Figs. 25E and 25I described below.

[0165] 25E , a unit pixel P may be composed of two sensor pixels 11A each having a rectangular planar shape. In the unit pixel P, the two sensor pixels 11A may be arranged line-symmetrically with respect to the inter-pixel separator 31. Even in this configuration, the imaging device 1G can acquire phase difference information in a direction (e.g., a diagonal direction) orthogonal to the extension direction of the intra-pixel separator 33 in a planar view. Furthermore, by arranging the intra-pixel separator 33 on the diagonal of the sensor pixel 11A, color mixing due to scattered light can be suppressed.

[0166] As shown in FIG. 25F , the imaging device 1G may include sensor pixels 11 having intra-pixel separators 33 and sensor pixels (hereinafter also referred to as normal pixels) 11B that do not have intra-pixel separators 33. One photodiode is provided in each normal pixel 11B, and this photodiode is not separated by an intra-pixel separator 33. Even in this configuration, the sensor pixels 11 having the intra-pixel separators 33 can acquire phase difference information in a direction (e.g., the vertical direction) that is orthogonal to the extension direction of the intra-pixel separators 33 in a planar view. Furthermore, by arranging the intra-pixel separators 33 diagonally across the sensor pixels 11, color mixing due to scattered light can be suppressed.

[0167] Fig. 25G is a modified example of Fig. 25F. In the example shown in Fig. 25G, the extension direction of the intra-pixel separator 33 is the vertical direction. The sensor pixel 11 having the intra-pixel separator 33 can acquire phase difference information in a direction (e.g., the horizontal direction) perpendicular to the extension direction of the intra-pixel separator 33 in a planar view. Furthermore, by arranging the intra-pixel separator 33 on the diagonal of the sensor pixel 11, color mixing due to scattered light can be suppressed.

[0168] 25H , in a unit pixel P, one on-chip lens OCLA may be arranged so as to straddle two adjacent normal pixels 11B. Even in this configuration, the sensor pixel 11 having the intra-pixel separator 33 can acquire phase difference information in directions (e.g., the vertical direction and the horizontal direction) orthogonal to the extension direction of the intra-pixel separator 33 in a planar view. Furthermore, by arranging the intra-pixel separator 33 on the diagonal of the sensor pixel 11, color mixing due to scattered light can be suppressed.

[0169] FIG. 25I is a modified example of FIG. 25D . In the example shown in FIG. 25I , the intra-pixel separator 33 provided in the sensor pixel 11A extends not on the diagonal of the rectangle but in a direction perpendicular to the long side of the rectangle. For example, the intra-pixel separator 33 extends in a direction oblique to the vertical and horizontal directions. Even in this configuration, the sensor pixel 11A having the intra-pixel separator 33 can acquire phase difference information in a direction (e.g., an oblique direction) perpendicular to the extension direction of the intra-pixel separator 33 in a planar view. Furthermore, by arranging the intra-pixel separator 33 on the diagonal of the sensor pixel 11, color mixing due to scattered light can be suppressed.

[0170] Furthermore, in the rectangular sensor pixel 11A, the intra-pixel separator 33 is arranged along the short-side direction of the ellipse (i.e., the direction in which the diameter is smallest). Therefore, in the sensor pixel 11A, the light scattering direction (e.g., see the arrow in FIG. 23 ) that is orthogonal to the intra-pixel separator 33 in a planar view can be made to coincide (or nearly coincide) with the longitudinal direction of the ellipse. This makes it possible to increase the distance from the center of the sensor pixel 11A along the scattering direction to the pixel boundary, compared to when the intra-pixel separator 33 is arranged along the longitudinal direction of the ellipse, and to suppress color mixing due to scattered light.

[0171] (2) Specific Example 2 (3x3 Type) Specific Example 2 of Embodiment 4 illustrates a variation of a 3x3 type arrangement example. FIGS. 26A to 26H are plan views schematically illustrating 3x3 type arrangement examples (Nos. 1 to 8) of unit pixels P of an imaging device 1G according to Embodiment 4 of the present disclosure. In each of the examples illustrated in FIGS. 26A to 26H , an intra-pixel separator 33 is disposed in a sensor pixel 11 having a square planar shape or a sensor pixel 11A having a rectangular planar shape, thereby making it possible to acquire phase difference information in a direction perpendicular to the extension direction of the intra-pixel separator 33. Furthermore, by disposing the intra-pixel separator 33 on the diagonal of each of the sensor pixels 11 and 11A, color mixing due to scattered light can be suppressed.

[0172] Note that the unit pixel P shown in Fig. 26D is not strictly a 3x3 type because it is composed of a total of eight pixels. However, because the rectangular sensor pixel 11A has an area twice that of the square sensor pixel 11, and because the planar shape of the unit pixel P shown in Fig. 26D is square and its area is the same as that of the 3x3 type unit pixel P shown in Fig. 26A etc., the unit pixel P shown in Fig. 26D is also classified as a 3x3 type in this specification. The same applies to the unit pixels P shown in Figs. 26E, 26G, and 26H.

[0173] (3) Specific Example 3 (4x4 Type) Specific Example 3 of Embodiment 4 shows variations of a 4x4 type arrangement example. Figures 27A to 27E are plan views schematically showing 4x4 type arrangement examples (Nos. 1 to 5) of unit pixels P of an imaging device 1G according to Embodiment 4 of the present disclosure. In all of the examples shown in Figures 27A to 27E, an intra-pixel separator 33 is disposed in a sensor pixel 11 having a square planar shape, thereby making it possible to acquire phase difference information in a direction (e.g., the vertical direction or the horizontal direction) orthogonal to the extension direction of the intra-pixel separator 33.

[0174] 27A to 27E , similar to the 2×2 and 3×3 types, in the case of the 4×4 type, a sensor pixel 11A having a rectangular planar shape may be included in the unit pixel P. In this case, similar to the sensor pixel 11, the sensor pixel 11A can also acquire phase difference information in a direction perpendicular to the extension direction of the intra-pixel separator 33 (for example, a diagonal direction). Furthermore, by arranging the intra-pixel separator 33 on the diagonal of each of the sensor pixels 11 and 11A, color mixing due to scattered light can be suppressed.

[0175] Note that the unit pixel P shown in Figure 27C is not strictly a 4x4 type because it is made up of a total of 13 pixels. However, since the large-area normal pixel 11B, which has a square planar shape, has an area equivalent to four normal pixels 11B (see Figure 27A), and since the planar shape of the unit pixel P shown in Figure 27C is square and its area is the same as that of the 4x4 type unit pixel P shown in Figure 27A etc., the unit pixel P shown in Figure 27C is also classified as a 4x4 type in this specification. The same applies to the unit pixel P shown in Figure 27D.

[0176] (4) Specific Example 4 (Examples of Configuration and Arrangement of Unit Pixel) FIGS. 28A to 28D are plan views schematically illustrating examples (1 to 4) of the configuration and arrangement of a unit pixel P of an imaging device 1G according to Embodiment 4 of the present disclosure. As shown in FIG. 28A , a unit pixel P may have an intra-pixel separation portion 33 and may be composed of only a sensor pixel 11 that detects a phase difference. A unit pixel P may be arranged adjacent to another unit pixel P with no gap between them. Also, as shown in FIG. 28B , a unit pixel P may include a sensor pixel 11 and a normal pixel 11B. As shown in FIG. 28C , the imaging device 1G may include, as the unit pixel P, a first unit pixel P1 that is composed of only a sensor pixel 11 that detects a phase difference and a second unit pixel P2 that is composed of only a normal pixel 11B. The first unit pixel P1 and the second unit pixel P2 may be arranged adjacent to each other with no gap between them as shown in FIG. 28C , or may be arranged with a gap between them as shown in FIG. 28D . As shown in Figure 28D, the first unit pixel P1 may be disposed diagonally (for example, tilted at 45°) relative to the second unit pixel P2 in a plan view. The areas of the first unit pixel P1 and the second unit pixel P2 in a plan view (hereinafter also referred to as planar areas) may be the same or different. For example, as shown in Figure 28D, the planar area of ​​the first unit pixel P1 may be larger than the planar area of ​​the second unit pixel P2.

[0177] (5) Specific Example 5 (Shape Examples of Intra-Pixel Separation Portion) FIGS. 29A to 29E are plan views schematically showing shape examples (Nos. 1 to 5) of the intra-pixel separation portion 33 according to the fourth embodiment of the present disclosure. The intra-pixel separation portion 33 shown in FIG. 29A is the same as the configuration example of the intra-pixel separation portion 33 shown in FIG. 3. As shown in FIG. 29A , a slit SL may be provided in the intra-pixel separation portion 33. The slit SL may be provided in the center of the sensor pixel 11 in a planar view. Alternatively, as shown in FIG. 29B , the slit SL may be provided in a non-center portion of the sensor pixel 11 in a planar view. That is, the intra-pixel separation portion 33 may be provided in the center of the sensor pixel 11 in a planar view.

[0178] 29C , the intra-pixel separator 33 may be located at a position off the diagonal of the sensor pixel 11 and extend in a direction obliquely intersecting the inter-pixel separator 31. As shown in FIG. 29D , the intra-pixel separator 33 may be provided in a dotted pattern in a planar view. That is, the intra-pixel separator 33 may be provided intermittently in a planar view. Alternatively, as shown in FIG. 29E , the intra-pixel separator 33 may not have a slit SL. That is, the intra-pixel separator 33 may be provided continuously in a planar view. In either case, phase difference information in a direction perpendicular to the extension direction of the intra-pixel separator 33 can be acquired. Furthermore, color mixing due to scattered light can be suppressed compared to the comparative example shown in FIG. 26 .

[0179] FIG. 30 is a cross-sectional view schematically illustrating an example of the shape of the intra-pixel separator 33 according to the fourth embodiment of the present disclosure. In the first embodiment, as illustrated in FIG. 4 , the intra-pixel separator 33 is provided to penetrate between the front surface 30 a and the back surface 30 b of the semiconductor substrate 30. However, the embodiments of the present disclosure are not limited to this. As illustrated in FIG. 30 , the intra-pixel separator 33 does not have to penetrate the semiconductor substrate 30. For example, the intra-pixel separator 33 may be provided from the back surface 30 b of the semiconductor substrate 30 to a position partway along the thickness direction of the semiconductor substrate 30. Even in such a configuration, phase difference information can be acquired and color mixing due to scattered light can be suppressed.

[0180] Fifth Embodiment In the embodiments of the present disclosure, various arrangements of the color filters CF can be employed. Below, several specific examples of the arrangement of the color filters CF are shown. FIGS. 31A to 31I are plan views schematically illustrating examples (numbers 1 to 9) of the arrangement of the color filters CF according to the fifth embodiment of the present disclosure. In FIGS. 31A to 31I, (R) indicates a sensor pixel 11 in which a red color filter CF is arranged, (G) indicates a sensor pixel 11 in which a green color filter CF is arranged, and (B) indicates a sensor pixel 11 in which a blue color filter CF is arranged. In addition, in FIGS. 31A to 31I, portions of the sensor pixels 11 are shown exposed from under the color filters CF to make the sensor pixels 11 more easily visible.

[0181] As shown in FIG. 31A , the color filter CF may have a “4×4 Bayer coding” arrangement. This arrangement is the same as the arrangement of the color filter CF shown in FIG. 22 . As shown in FIG. 31B , the color filter CF may have a “Quad Bayer coding” arrangement. This arrangement is the same as the arrangement of the color filter CF shown in FIG. 3 . As shown in FIG. 31C , the color filter CF may have a “Bayer coding” arrangement. As shown in FIG. 31D , the color filter CF may have a “3×3 coding” arrangement. As shown in FIG. 31E , the color filter CF may have a “Deca Octa coding” arrangement. As shown in FIG. 31F , the color filter CF may have a “Cross coding” arrangement. As shown in FIGS. 31G to 31I , the color filter CF may have an arrangement with “high resolution and high sensitivity” specifications. In either case, it is possible to detect phase difference information and suppress color mixing due to scattered light.

[0182] <Other Embodiments> As described above, the present disclosure has been described using embodiments and modifications. However, the descriptions and drawings that form a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure. Furthermore, the application of the technology according to the present disclosure is not limited to imaging devices such as CMOS image sensors, but may also be applied to distance measurement devices such as direct Time of Flight (ToF) sensors and indirect ToF sensors. In other words, the light detection device of the present disclosure may be not only an imaging device but also a distance measurement device. It goes without saying that the present technology includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components may be made within the scope of the above-described embodiments and modifications. Furthermore, the effects described in this specification are merely exemplary and are not limiting, and other effects may also be present.

[0183] The present disclosure may also have the following configuration: (1) A semiconductor device comprising: a first semiconductor substrate having a first surface and a second surface located opposite to the first surface; a plurality of sensor pixels provided on the first semiconductor substrate; and an inter-pixel separation section provided on the first semiconductor substrate, separating adjacent sensor pixels from the other sensor pixel of the plurality of sensor pixels, wherein each of the plurality of sensor pixels has a rectangular shape in a plan view in a thickness direction of the first semiconductor substrate, and the plurality of sensor pixels are arranged side by side in a first direction and a second direction intersecting with the first direction, with edges adjacent to each other via the inter-pixel separation section, and each of the plurality of sensor pixels has: a first photoelectric conversion section that photoelectrically converts light incident from the first surface; a second photoelectric conversion section that is adjacent to the first photoelectric conversion section and photoelectrically converts light incident from the first surface; and an intra-pixel separation section that separates the first photoelectric conversion section from the second photoelectric conversion section, (2) The photodetector according to (1), wherein the shape of each of the plurality of sensor pixels in a plan view is square, and the intra-pixel isolation portion extends in a direction oblique to each of the first direction and the second direction. (3) The photodetector according to (1) or (2), wherein the shape of the first semiconductor substrate in a plan view is rectangular, and the intra-pixel isolation portion extends in a direction perpendicular or horizontal to four sides of an outer periphery of the first semiconductor substrate. (4) The photodetector according to any one of (1) to (3), further comprising pixel wiring provided on the second surface side of the first semiconductor substrate for outputting signals generated by photoelectric conversion in the plurality of sensor pixels to outside the plurality of sensor pixels, and the intra-pixel isolation portion extends in a direction perpendicular or horizontal to the pixel wiring. (5) The photodetector according to any one of (1) to (4), wherein the inter-pixel isolation portion has a lattice shape in plan view, and the intra-pixel isolation portion is arranged along a diagonal of a unit lattice, which is the smallest unit of the lattice.(6) The photodetector according to any one of (1) to (5), wherein the intra-pixel isolation section is provided with a communication section that communicates the first photoelectric conversion section and the second photoelectric conversion section. (7) The photodetector according to (6), wherein the communication section is arranged in a center of the sensor pixel in the planar view. (8) The photodetector according to any one of (1) to (7), further comprising a floating diffusion provided on the second surface side of the first semiconductor substrate, wherein the plurality of sensor pixels have unit pixels each including two sensor pixels lined up in the first direction and two sensor pixels lined up in the second direction, and the floating diffusion is arranged in a center of the unit pixel in the planar view. (9) The photodetector according to (8), wherein in each of the four sensor pixels that constitute the unit pixel, one end of the intra-pixel isolation section is adjacent to the floating diffusion, and the other end of the intra-pixel isolation section is adjacent to the inter-pixel isolation section. (10) The photodetector according to (8) or (9), further comprising: a transfer transistor provided on the second surface side of the first semiconductor substrate and configured to transfer charge generated by photoelectric conversion in the sensor pixel to the floating diffusion, the transfer transistor being disposed in each of the first photoelectric conversion unit and the second photoelectric conversion unit. (11) The photodetector according to any one of (8) to (10), further comprising: an amplifier transistor provided on the first semiconductor substrate and configured to amplify a voltage signal corresponding to a level of charge output from the sensor pixel; a selection transistor provided on the first semiconductor substrate and configured to control an output timing of the signal from the amplifier transistor; and a reset transistor provided on the first semiconductor substrate and configured to reset a potential of the floating diffusion to a preset potential, the amplifier transistor, the selection transistor, and the reset transistor being disposed for each unit pixel.(12) The photodetector according to any one of (8) to (10), comprising: a second semiconductor substrate bonded to the second surface side of the first semiconductor substrate; an amplifying transistor provided on the second semiconductor substrate and amplifying a voltage signal corresponding to the level of charge output from the sensor pixel; a selecting transistor provided on the second semiconductor substrate and controlling the output timing of the signal from the amplifying transistor; and a reset transistor provided on the second semiconductor substrate and resetting the potential of the floating diffusion to a preset potential, wherein the amplifying transistor, the selecting transistor, and the reset transistor are arranged for each unit pixel. (13) A semiconductor device comprising: a first semiconductor substrate having a first surface and a second surface located opposite to the first surface; a plurality of sensor pixels provided on the first semiconductor substrate; and an inter-pixel separation portion provided on the first semiconductor substrate and separating adjacent sensor pixels from the other sensor pixel of the plurality of sensor pixels, wherein each of the plurality of sensor pixels has a rectangular shape in a plan view in a thickness direction of the first semiconductor substrate, and the plurality of sensor pixels are arranged side by side in a first direction and a second direction intersecting the first direction, with edges adjacent to each other via the inter-pixel separation portion, and each of the plurality of sensor pixels has: a first photoelectric conversion portion that photoelectrically converts light incident from the first surface; a second photoelectric conversion portion that is adjacent to the first photoelectric conversion portion and performs photoelectric conversion on the light incident from the first surface; and an intra-pixel separation portion that separates the first photoelectric conversion portion from the second photoelectric conversion portion, (14) The photodetector according to (13), wherein the intra-pixel separation portion is provided on a diagonal line of the rectangle. (14) The photodetector according to (13), wherein the rectangle is a square or a rectangle whose long sides are twice as long as its short sides.

[0184] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G Imaging device 10 Pixel array section 11, 11A Sensor pixel 11B Normal pixel 12 System control section 13 Vertical drive section 14 Column readout circuit section 15 Column signal processing section 16 Horizontal drive section 17 Signal processing section 18 Readout circuit 21 First impurity region 22 Second impurity region 24 On-chip lens 30, 121 Semiconductor substrate 30a Front surface 30b Back surface 30LH, 30LV Edge 31 Inter-pixel isolation section 33 Intra-pixel isolation section 33C Central section 50 Planarization film 61, 62, 64, 65 Wiring 63 Intersection region 66 Via 110 First substrate section 114 Well region 117 First wiring layer 120 Second substrate section 142 Gate insulating film 143 Fourth insulating film 145 Fifth insulating film 146 Sixth insulating film 151, 152 Through wiring 153 Second wiring layer 161 First insulating film 162 Second insulating film 163 Third insulating film 164 Fourth insulating film 211 Semiconductor layer 901 Imaging device 911 Sensor pixel 931 Inter-pixel isolation portion 933 Intra-pixel isolation portion 933C Central portion 964 Wiring AG Gate electrode (of amplifying transistor) AMP Amplifying transistor CF Color filter CON Contact region DMY Dummy transistor FD Floating diffusion FDG Switching transistor GND Reference potential wiring L Light LD Pixel drive line LV, LV0, LV1 Vertical pixel wiring OCL, OCLA On-chip lens P Unit pixel P1 First unit pixel P2 Second unit pixel PD Photodiode PDA First photodiode PDB Second photodiode RST Reset transistor SEL Select transistor SL Slit SLE Select transistor TG Gate electrode (of transfer transistor), transfer gate TR Transfer transistor VG Buried gate

Claims

1. A semiconductor device comprising: a first semiconductor substrate having a first surface and a second surface located opposite to the first surface; a plurality of sensor pixels provided on the first semiconductor substrate; and an inter-pixel separation section provided on the first semiconductor substrate, separating adjacent sensor pixels from the other sensor pixel of the plurality of sensor pixels, wherein each of the plurality of sensor pixels has a rectangular shape in a plan view in a thickness direction of the first semiconductor substrate, and the plurality of sensor pixels are arranged in a first direction and a second direction intersecting the first direction, with edges adjacent to each other, via the inter-pixel separation section, and each of the plurality of sensor pixels has: a first photoelectric conversion section that photoelectrically converts light incident from the first surface; a second photoelectric conversion section that is adjacent to the first photoelectric conversion section and that photoelectrically converts light incident from the first surface; and an intra-pixel separation section that separates the first photoelectric conversion section from the second photoelectric conversion section, The intra-pixel separation portion extends in a direction oblique to each of the first direction and the second direction.

2. The light detection device described in claim 1, wherein the shape of each of the plurality of sensor pixels in the planar view is a square, and the intra-pixel separation portion extends in a direction that is inclined at 45° to the first direction and the second direction.

3. The photodetector device described in claim 1, wherein the shape of the first semiconductor substrate in a planar view is rectangular, and the intra-pixel isolation portion extends in a direction perpendicular or horizontal to the four outer periphery sides of the first semiconductor substrate.

4. The photodetection device according to claim 1, further comprising pixel wiring provided on the second surface side of the first semiconductor substrate for outputting signals generated by photoelectric conversion in the plurality of sensor pixels to the outside of the plurality of sensor pixels, the intra-pixel isolation portion extending vertically or horizontally relative to the pixel wiring.

5. The photodetector according to claim 1, wherein the inter-pixel isolation portion has a lattice shape in a planar view, and the intra-pixel isolation portion is arranged along a diagonal of a unit lattice, which is the smallest unit of the lattice.

6. The photodetector according to claim 1, wherein the intra-pixel isolation section is provided with a communication section that communicates the first photoelectric conversion section and the second photoelectric conversion section.

7. The light detection device according to claim 6, wherein the communication portion is disposed in a center portion of the sensor pixel in the plan view.

8. The photodetection device according to claim 1, further comprising a floating diffusion provided on the second surface side of the first semiconductor substrate, the plurality of sensor pixels having unit pixels each including two sensor pixels arranged in the first direction and two sensor pixels arranged in the second direction, and the floating diffusion disposed in the center of the unit pixel when viewed in the plane.

9. The photodetection device according to claim 8, wherein in each of the four sensor pixels constituting the unit pixel, one end of the intra-pixel isolation portion is adjacent to the floating diffusion, and the other end of the intra-pixel isolation portion is adjacent to the inter-pixel isolation portion.

10. A photodetection device as described in claim 8, further comprising a transfer transistor provided on the second surface side of the first semiconductor substrate for transferring charges generated by photoelectric conversion in the sensor pixel to the floating diffusion, the transfer transistor being disposed in each of the first photoelectric conversion section and the second photoelectric conversion section.

11. A photodetection device as described in claim 8, comprising: an amplifying transistor provided on the first semiconductor substrate, amplifying a voltage signal corresponding to the level of charge output from the sensor pixel; a selection transistor provided on the first semiconductor substrate, controlling the output timing of the signal from the amplifying transistor; and a reset transistor provided on the first semiconductor substrate, resetting the potential of the floating diffusion to a preset potential, wherein the amplifying transistor, the selection transistor and the reset transistor are arranged for each unit pixel.

12. A photodetection device as described in claim 8, comprising: a second semiconductor substrate joined to the second surface side of the first semiconductor substrate; an amplifying transistor provided on the second semiconductor substrate, amplifying a voltage signal corresponding to the level of charge output from the sensor pixel; a selecting transistor provided on the second semiconductor substrate, controlling the output timing of the signal from the amplifying transistor; and a reset transistor provided on the second semiconductor substrate, resetting the potential of the floating diffusion to a preset potential, wherein the amplifying transistor, the selecting transistor and the reset transistor are arranged for each unit pixel.

13. A semiconductor device comprising: a first semiconductor substrate having a first surface and a second surface located opposite to the first surface; a plurality of sensor pixels provided on the first semiconductor substrate; and an inter-pixel separation portion provided on the first semiconductor substrate and separating adjacent sensor pixels from the other sensor pixel of the plurality of sensor pixels, wherein each of the plurality of sensor pixels has a rectangular shape in a plan view in a thickness direction of the first semiconductor substrate, and the plurality of sensor pixels are arranged in a line in a first direction and a second direction intersecting the first direction, with edges adjacent to each other via the inter-pixel separation portion, and each of the plurality of sensor pixels has: a first photoelectric conversion portion that photoelectrically converts light incident from the first surface; a second photoelectric conversion portion that is adjacent to the first photoelectric conversion portion and that photoelectrically converts light incident from the first surface; and an intra-pixel separation portion that separates the first photoelectric conversion portion from the second photoelectric conversion portion, A photodetection device, wherein the intra-pixel separation portion is provided on a diagonal line of the rectangle.

14. The optical detection device according to claim 13, wherein the rectangle is a square or a rectangle whose long side is twice as long as its short side.

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