Semiconductor device and electronic apparatus

Abstract

A semiconductor device according to one embodiment of the present disclosure comprises: a channel layer that includes a first nitride semiconductor; a semiconductor layer that is provided so as to be layered with the channel layer and includes a second nitride semiconductor; a gate electrode and a drain electrode that are provided above the semiconductor layer; a first insulating film that is provided above the semiconductor layer between the gate electrode and the drain electrode; and a second insulating film that is provided so as to be layered with the first insulating film and includes silicon. The semiconductor layer includes a halogen element below the gate electrode. The silicon content of the semiconductor layer below the space between the gate electrode and the drain electrode is no more than 2 atomic%.

Description

Semiconductor devices and electronic devices

[0001] The present disclosure relates to a semiconductor device and an electronic device.

[0002] Semiconductor devices have been proposed that include a barrier layer having a negative ion region.

[0003] Special Publication No. 2009-507396

[0004] In semiconductor devices, it is required to suppress an increase in leakage current.

[0005] It is desirable to provide a semiconductor device that can reduce leakage current.

[0006] A semiconductor device according to an embodiment of the present disclosure includes a channel layer including a first nitride semiconductor, a semiconductor layer including a second nitride semiconductor and stacked with the channel layer, a gate electrode and a drain electrode provided above the semiconductor layer, a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film including silicon and stacked with the first insulating film. The semiconductor layer includes a halogen element below the gate electrode. The silicon content of the semiconductor layer below the gap between the gate electrode and the drain electrode is 2 atomic % or less. An electronic device according to an embodiment of the present disclosure includes a circuit including: a channel layer including a first nitride semiconductor, a semiconductor layer including a second nitride semiconductor and stacked with the channel layer, a gate electrode and a drain electrode provided above the semiconductor layer, a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film including silicon and stacked with the first insulating film. The semiconductor layer includes a halogen element below the gate electrode. The silicon content of the semiconductor layer below the gap between the gate electrode and the drain electrode is 2 atomic % or less.

[0007] FIG. 1 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a diagram for explaining an example of a composition distribution in a semiconductor device according to an embodiment of the present disclosure. FIG. 3A is a diagram showing an example of the composition of each layer of a semiconductor device according to the present disclosure. FIG. 3B is a diagram showing an example of the composition of each layer of a semiconductor device according to the present disclosure. FIG. 4 is a diagram showing a leak path in a semiconductor device according to a comparative example. FIG. 5 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure. FIG. 6 is a diagram for explaining a configuration example of a semiconductor device according to an embodiment of the present disclosure. FIG. 7 is a diagram for explaining a configuration example of a semiconductor device according to a first modified example of the present disclosure. FIG. 8 is a diagram showing a configuration example of a wireless communication device according to the present disclosure.

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. Embodiment 2. Modification 3. Application Example

[0009] 1. Embodiments Fig. 1 is a diagram illustrating an example of the configuration of a semiconductor device according to an embodiment of the present disclosure. Fig. 1 shows an example of a cross-sectional configuration of semiconductor device 1. Semiconductor device 1 is configured using, for example, a compound semiconductor, and can be applied to a device (circuit) that processes high-frequency signals. As an example, semiconductor device 1 is configured using a III-V group compound semiconductor or the like, and can be applied to a communication device as a high-frequency circuit.

[0010] The semiconductor device 1 is formed using a nitride semiconductor, such as gallium nitride (GaN). GaN (gallium nitride) is a wide-gap semiconductor material with a wide band gap. GaN also has characteristics such as high breakdown voltage, high heat resistance, and a high saturated drift velocity.

[0011] Two-dimensional electron gas (2DEG) formed at a GaN-based heterojunction has high mobility and high sheet electron density, which allows GaN-based heterojunction field-effect transistors (HFETs) to have low resistance and operate at high speeds and withstand high voltages.

[0012] Furthermore, Schottky HEMTs having a Schottky structure are characterized by small fluctuations in characteristics (e.g., fluctuations in threshold voltage during operation, drain lag, etc.). GaN-based HFETs can be suitably used in power devices, RF devices, etc. For example, GaN-based HFETs may be applied to high-frequency devices for fifth-generation mobile communications (5G).

[0013] The semiconductor device 1 may be applied to an integrated circuit such as an MMIC (Monolithic Microwave Integrated Circuit). The semiconductor device 1 can be used in electronic devices that use frequency bands such as microwave bands and millimeter wave bands. The semiconductor device 1 can be applied to, for example, RF signal switch circuits, power amplifier circuits, filter circuits, etc.

[0014] 1, the semiconductor device 1 is configured as a field effect transistor (FET) having gate, source, and drain terminals. The semiconductor device 1 is, for example, a heterojunction FET (HFET) and is configured using a compound semiconductor.

[0015] The semiconductor device 1 may have a two-dimensional electron gas (two-dimensional electron gas layer) formed using a heterojunction. The semiconductor device 1 includes, for example, a gate using a Schottky junction and is configured as a transistor having a Schottky gate. The semiconductor device 1 has a Schottky gate structure and can also be called a Schottky FET.

[0016] 1, the semiconductor device 1 includes a substrate 10, a buffer layer 21, a channel layer 22, a spacer layer 23, a barrier layer 24, a protective layer 25, a semiconductor region 26 a, and a semiconductor region 26 b. The semiconductor device 1 also includes an insulating film 31, an insulating film 32, a gate electrode 40, a source electrode 50 a, and a drain electrode 50 b.

[0017] The substrate 10 is made of a semiconductor material, for example, a III-V compound semiconductor material. As an example, the substrate 10 may be made of GaN. The substrate 10 may also be other substrates, such as a SiC (silicon carbide) substrate, a sapphire substrate, or a Si (silicon) substrate. In the semiconductor device 1, the lattice constant can be controlled by providing a buffer layer 21, which will be described later, and the substrate 10 may be a SiC substrate, a sapphire substrate, a Si substrate, or the like.

[0018] The buffer layer 21 is provided so as to be stacked on the substrate 10. In the example shown in Fig. 1, the buffer layer 21 is provided on the substrate 10 and is located between the substrate 10 and the channel layer 22. The buffer layer 21 is made of, for example, AlN, AlGaN, GaN, or the like. As an example, the buffer layer 21 can be made of a compound semiconductor layer epitaxially grown on the substrate 10.

[0019] When the lattice constant of the substrate 10 differs from that of the channel layer 22, the crystalline state of the channel layer 22 can be improved and warpage (warpage of the substrate 10, the channel layer 22, etc.) can be suppressed by controlling (adjusting) the lattice constant using the buffer layer 21. For example, when the substrate 10 is made of a Si substrate and the channel layer 22 is made of GaN, the buffer layer 21 may be made of AlN, AlGaN, GaN, or the like.

[0020] The channel layer 22 is made of a compound semiconductor, for example, a nitride semiconductor. The channel layer 22 is a semiconductor layer containing a nitride semiconductor, for example, made of GaN. The channel layer 22 is provided so as to be stacked above the substrate 10. In the example shown in FIG. 1 , the channel layer 22 is formed on the buffer layer 21 and is located between the buffer layer 21 and the spacer layer 23.

[0021] The channel layer 22 and the barrier layer 24 may be made of different compound semiconductors. For example, the channel layer 22 and the barrier layer 24 may be made of different nitride semiconductors. The channel layer 22 and the barrier layer 24 may be configured to have different bandgaps.

[0022] The channel layer 22 is, for example, an epitaxially grown layer of GaN, and is a region where carriers (signal charges) are accumulated due to polarization in the channel layer 22 and the barrier layer 24. The channel layer 22 can generate and accumulate charges due to a polarization difference between the channel layer 22 and the barrier layer 24. The channel layer 22 forms part of the current path between the source electrode 50 a and the drain electrode 50 b.

[0023] In the semiconductor device 1, carriers are induced by polarization in the channel layer 22 and the barrier layer 24, and a two-dimensional electron gas (2DEG) is formed at the interface between the channel layer 22 and the barrier layer 24. The semiconductor device 1 is, for example, a semiconductor device (semiconductor element) in which a two-dimensional electron gas is formed, and can be configured as a high electron mobility transistor (HEMT).

[0024] The channel layer 22 may be made of u-GaN to which no impurities are added (undoped). In this case, impurity scattering of carriers in the channel layer 22 is suppressed, and high carrier mobility can be achieved. The channel layer 22 may also be made of other semiconductor materials. Furthermore, impurities may be added to the channel layer 22 for band engineering.

[0025] The spacer layer 23 is provided between the channel layer 22 and the barrier layer 24. The spacer layer 23 is made of, for example, a material having a band gap larger than the band gap of the channel layer 22. The spacer layer 23 is made of a nitride semiconductor, for example, an epitaxially grown layer of AlN, and is located on the channel layer 22.

[0026] The spacer layer 23 is made of Al ｘ In ｙ Ga １－ｘ－ｙ N (0<x<1, 0≦y<1, 0<x+y<1). The spacer layer 23 may be made of a ternary material (e.g., AlGaN) or a quaternary material (e.g., AlGaInN).

[0027] In the semiconductor device 1, the provision of the spacer layer 23 can reduce the effect of alloy scattering by the barrier layer 24 on carriers (i.e., two-dimensional electron gas) induced at the interface between the spacer layer 23 and the channel layer 22. This can increase carrier mobility.

[0028] The barrier layer 24 is made of, for example, a compound semiconductor material, and is provided so as to be stacked on the channel layer 22. In the example shown in Fig. 1, the barrier layer 24 is formed on the spacer layer 23 and is located between the spacer layer 23 and the protective layer 25. The barrier layer 24 can be made of, for example, a material having a band gap larger than the band gap of the channel layer 22.

[0029] The barrier layer 24 is made of a nitride semiconductor, for example, Al ｘ In １－ｘ The semiconductor device 1 is composed of an N (0<x<1) epitaxially grown layer and is located on a spacer layer 23. In the semiconductor device 1, polarization occurs in the barrier layer 24 and the channel layer 22, and a two-dimensional electron gas layer 60 can be generated at the heterojunction interface, as shown by the dotted line in FIG.

[0030] The barrier layer 24 is made of undoped u-Al. ｘ In １－ｘ In this case, the barrier layer 24 can suppress impurity scattering of carriers in the channel layer 22, thereby further increasing carrier mobility.

[0031] The barrier layer 24 may be made of a compound semiconductor material that can accumulate carriers according to the difference in polarization charge amount at the interface between the channel layer 22 and the spacer layer 23. The channel layer 22 may be made of Al, In, etc., and the barrier layer 24 may be made of Al, １－ｘ－ｙ In ｘ Ga ｙ The semiconductor layer may be composed of N epitaxially grown layers (0≦x<1, 0≦y<1, x+y≦1).

[0032] The barrier layer 24 is made of undoped Al １－ｘ－ｙ In ｘ Ga ｙThe barrier layer 24 may be made of N. The barrier layer 24 is a nitride semiconductor layer made of a nitride semiconductor, and may also be called a carrier supply layer (or an electron supply layer). The barrier layer 24 is also called a carrier transit layer (or an electron transit layer).

[0033] The protective layer 25 is provided on the barrier layer 24. The protective layer 25 is made of, for example, GaN, SiN, or the like. The provision of the protective layer 25 suppresses, for example, oxidation of the surface (upper surface) of the barrier layer 24. The protective layer 25 may be formed of a single layer or may be formed by stacking multiple layers (films).

[0034] The protective layer 25 may be formed of, for example, a composite layer in which GaN and SiN are stacked. Furthermore, for example, the protective layer 25 may have a structure in which the composition gradually changes in the thickness direction. The protective layer 25 is also called a cap layer.

[0035] The protective layer 25 is made of a compound semiconductor material, for example, Al １－ｘ－ｙ In ｘ Ga ｙ N (0≦x≦1, 0≦y≦1, x+y≦1). In this case, for example, the barrier layer 24 formed by an epitaxially grown layer can be effectively protected. Note that the protective layer 25 may not be provided depending on the desired device characteristics, mass productivity, and the like.

[0036] The semiconductor regions 26a and 26b are, for example, n+ type semiconductor regions formed using n-type impurities (dopants). The semiconductor regions 26a and 26b are, for example, formed using GaN. The semiconductor regions 26a and 26b may be made of the same material as the channel layer 22. The semiconductor regions 26a and 26b are also referred to as contact layers.

[0037] The semiconductor regions 26a and 26b are each In ｘ Ga １－ｘ It may be formed using N (0≦x≦1) or other materials. As the n-type impurity (dopant), Si (silicon), Ge (germanium), etc. are used. The impurity concentration is, for example, 1×10１８ cm ―３ or more, or 1 x 10 １９ cm ―３ The semiconductor regions 26a and 26b each become a high-concentration n+ layer.

[0038] The semiconductor regions 26a and 26b are formed, for example, so as to be in contact with the channel layer 22 in which the two-dimensional electron gas layer 60 is formed. In the example shown in FIG. 1 , the semiconductor region 26a is provided from the source electrode 50a to within the channel layer 22. The semiconductor region 26b is provided from the drain electrode 50b to within the channel layer 22. The semiconductor regions 26a and 26b can be formed in the barrier layer 24 and the channel layer 22.

[0039] For example, the semiconductor regions 26 a, 26 b may be formed in a region of the channel layer 22 deeper than the vicinity of the barrier layer 24 where the two-dimensional electron gas layer 60 is formed. The semiconductor regions 26 a, 26 b form part of the current path between the source electrode 50 a and the drain electrode 50 b.

[0040] One of the semiconductor regions 26a and 26b, for example, the semiconductor region 26a, constitutes a part of the source of the transistor. The other of the semiconductor regions 26a and 26b, for example, the semiconductor region 26b, constitutes a part of the drain of the transistor. The semiconductor region 26a can also be called the source region, and the semiconductor region 26b can also be called the drain region.

[0041] In the semiconductor device 1, the semiconductor regions 26a and 26b are provided, so that the two-dimensional electron gas layer 60 in the channel layer 22 can be electrically connected to the source electrode 50a (and the drain electrode 50b) with low resistance. The semiconductor regions 26a and 26b do not need to be in contact with the two-dimensional electron gas layer 60. Depending on the configurations of the channel layer 22 and the barrier layer 24, the semiconductor region 26a (or the semiconductor region 26b) and the two-dimensional electron gas layer 60 do not need to be in direct contact with each other.

[0042] The semiconductor regions 26 a and 26 b may be formed, for example, by partially removing the barrier layer 24, the channel layer 22, etc. by etching, and then selectively growing epitaxially in the removed regions. Alternatively, the semiconductor regions 26 a and 26 b may be formed by, for example, ion implantation.

[0043] The source electrode 50a and the drain electrode 50b are each made of, for example, titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), etc. The source electrode 50a is provided for the semiconductor region 26a, and the drain electrode 50b is provided for the semiconductor region 26b. Note that the source electrode 50a and the drain electrode 50b may each be made of another metal material.

[0044] The source electrode 50a is electrically connected to the semiconductor region 26a, and the drain electrode 50b is electrically connected to the semiconductor region 26b. For example, the source electrode 50a forms an ohmic junction with the semiconductor region 26a, and the drain electrode 50b forms an ohmic junction with the semiconductor region 26b. The source electrode 50a and the drain electrode 50b can also be called ohmic electrodes.

[0045] The insulating film 31 is provided above the barrier layer 24. In the example shown in FIG. 1, the insulating film 31 is provided on the protective layer 25 and is located between the protective layer 25 and the insulating film 32. The insulating film 31 is made of an insulating material that does not contain Si (silicon), for example, aluminum oxide (Al ２ O ３ ), hafnium oxide (HfO ２ ) etc.

[0046] As another example, the insulating film 31 may be made of AlN or TiO ２ , NbO, Nb ２ O ５ , or Ta ２ O ５ The insulating film 31 may be formed of any other insulating material. The insulating film 31 may be formed of a single film or a laminate of multiple films.

[0047] The insulating film 32 is provided so as to be stacked on the insulating film 31. In the example shown in Fig. 1, the insulating film 32 is formed on the insulating film 31 between the source electrode 50a and the gate electrode 40 and between the drain electrode 50b and the gate electrode 40. The insulating film 32 is made of an insulating material containing Si (silicon).

[0048] The insulating film 32 is made of, for example, silicon nitride (SiN or Si ３ N ４ ), silicon oxide (SiO ２ The insulating film 32 may be a single layer made of one of silicon oxynitride (SiON), silicon oxynitride (SiON), or a laminated film made of two or more of these materials. As an example, the insulating film 32 may be made of a SiN film, which has excellent insulating properties and stress controllability. Alternatively, two or more SiN films may be laminated in multiple steps depending on the manufacturing process. Furthermore, the insulating film 32 may be made of two or more SiN layers with different refractive indices. The insulating film 32 may be made of AlSiO, or may be formed using other insulating materials.

[0049] The insulating film 32 may be provided as an interlayer insulating film in a wiring layer in which a plurality of wirings are provided. For example, the insulating film 32 is formed between a plurality of wirings, between an electrode (e.g., a via) and a wiring, or between a plurality of electrodes. The insulating film 32 may be formed of a single film or may be formed by stacking a plurality of films.

[0050] 1 , the insulating films 31 and 32 have a gate opening 35. The gate opening 35 is an opening (opening) formed by, for example, removing by etching a portion of the insulating films 31 and 32 between the source electrode 50 a and the drain electrode 50 b. A gate electrode 40 is provided in the gate opening 35. The gate electrode 40 is provided so as to fill the gate opening 35, and may have, for example, a T-shaped cross section.

[0051] The gate electrode 40 is made of a metal material such as nickel (Ni) or gold (Au). The gate electrode 40 is formed so as to be embedded in the gate opening 35. In the example shown in FIG. 1, the bottom (lower end) of the gate electrode 40 is disposed on the protective layer 25. Note that the gate electrode 40 may be made of other conductive materials.

[0052] The semiconductor device 1 according to this embodiment is configured to contain a halogen group element below the gate electrode 40. For example, the semiconductor device 1 is configured to contain fluorine (F) as a halogen group element in a region below the gate electrode 40. In the example shown in FIG. 1 , the protective layer 25, the barrier layer 24, the spacer layer 23, and the like below the gate electrode 40 may be configured to contain fluorine.

[0053] Furthermore, the semiconductor device 1 may be configured to contain oxygen (O) below the gate electrode 40. In the example shown in Fig. 1 , the protective layer 25, the barrier layer 24, the spacer layer 23, and the like below the gate electrode 40 may be configured to contain oxygen. In the semiconductor device 1, for example, as will be described later, fluorine and oxygen may be introduced into the region (position) below the gate electrode 40 by dry etching, wet etching, or the like.

[0054] 2 is a diagram illustrating an example of a composition distribution in a semiconductor device according to an embodiment, in which the peak positions of the fluorine (F) content and the oxygen (O) content in the semiconductor device 1 are schematically shown as rectangles.

[0055] 3A and 3B are diagrams showing an example of the composition of each layer of the semiconductor device. Fig. 3B shows an enlarged view of a portion of Fig. 3A. Note that such composition distribution can be confirmed by, for example, X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectroscopy (SIMS), or the like.

[0056] 2, the semiconductor device 1 is configured to contain fluorine and oxygen at the interface between the gate electrode 40 and the protective layer 25. The semiconductor device 1 is also configured to contain fluorine and oxygen at the interface between the protective layer 25 and the barrier layer 24. The semiconductor device 1 can also be configured to contain fluorine and oxygen at the interface between the barrier layer 24 and the spacer layer 23.

[0057] 3A and 3B , the semiconductor device 1 has a peak (maximum part) of the fluorine content and a peak of the oxygen content near the interface between the protective layer 25 and the barrier layer 24. The semiconductor device 1 may also have a peak of the fluorine content and a peak of the oxygen content near the interface between the barrier layer 24 and the spacer layer 23.

[0058] As described above, the semiconductor device 1 is configured to contain at least one of fluorine and oxygen below the gate electrode 40. By implanting fluorine as negative ions (negative fixed charges) below the gate electrode 40, for example, in the protective layer 25, the barrier layer 24, the spacer layer 23, etc., it becomes possible to reduce the electric field (potential gradient) in each layer of the semiconductor device 1.

[0059] In the semiconductor device 1, it is possible to suppress the occurrence of electric field concentration (strong electric field) between the gate electrode 40 and the drain electrode 50b. Also, it is possible to alleviate the electric field between the gate electrode 40 and the source electrode 50a. The gate end electric field is alleviated, and it is possible to reduce the leakage current.

[0060] Furthermore, in the semiconductor device 1, it is possible to effectively suppress leakage current by implanting oxygen into the protective layer 25, the barrier layer 24, the spacer layer 23, etc. below the gate electrode 40. For example, the trap levels in each layer formed by oxygen implantation capture unnecessary carriers leaking from the two-dimensional electron gas layer 60, thereby reducing the leakage current.

[0061] In the semiconductor device 1, the maximum fluorine content in each of the protective layer 25, the barrier layer 24, and the spacer layer 23 below the gate electrode 40 may be 0.5 atomic % (atomic percent) or more. Also, the maximum oxygen content in each of the protective layer 25, the barrier layer 24, and the spacer layer 23 below the gate electrode 40 may be 1 atomic % or more. By configuring the semiconductor device 1 in this manner, it is possible to effectively suppress leakage current.

[0062] Furthermore, in the semiconductor device 1, an insulating film 31 is provided below the insulating film 32 containing silicon. The insulating film 31 is made of an insulating material that does not contain silicon, such as aluminum oxide. This makes it possible to prevent silicon contained in the insulating film 32 from diffusing (mixing) into regions below the insulating film 31 (such as the protective layer 25 and the barrier layer 24). For example, it becomes possible to prevent silicon in the insulating film 32 from diffusing into the barrier layer 24 during a manufacturing process (such as a heat treatment process).

[0063] In the semiconductor device 1, the insulating film 31 is provided, thereby making it possible to suppress a decrease in resistance of the protective layer 25 and the like due to the diffusion of silicon from the insulating film 32. This makes it possible to effectively suppress a leakage current (off-leak current) between the gate electrode 40 and the drain electrode 50b (or the source electrode 50a).

[0064] The silicon content in each of the protective layer 25 and the barrier layer 24 below the gate electrode 40 and the drain electrode 50 b may be, for example, 2 atomic % or less. In this case, it is possible to effectively suppress leakage current between the gate electrode 40 and the drain electrode 50 b (or the source electrode 50 a). Note that the silicon composition ratio in the protective layer 25 etc. may be a magnitude (value) below the detection limit.

[0065] If the semiconductor device 1 does not contain fluorine and oxygen in the region below the gate electrode 40 and does not have an insulating film 31, a leakage path may be formed between the two-dimensional electron gas layer 60 and the gate electrode 40, as shown schematically by the arrow in Figure 4, and the leakage current may increase.

[0066] In contrast to this, in the present embodiment, the electric field is alleviated by implanting fluorine and oxygen, and the diffusion of silicon is suppressed by the insulating film 31, so that the leakage current between the two-dimensional electron gas layer 60 and the gate electrode 40 can be effectively suppressed, as schematically represented by the "X" mark in Fig. 5. When the semiconductor device 1 is applied to an electronic device (for example, a mobile terminal), it is possible to reduce the power consumption of the electronic device.

[0067] 6 is a diagram illustrating an example of the configuration of a semiconductor device according to an embodiment. The insulating film 31 has a thickness smaller than that of the insulating film 32, for example. The thickness Th1 of the insulating film 31 may be greater than 1 nm. The thickness Th1 of the insulating film 31 may be greater than 2 nm, or greater than 3 nm. The thickness Th1 of the insulating film 31 may be in the range of 2 nm to 15 nm.

[0068] The thickness Th2 of the insulating film 32 may be, for example, within a range of 40 nm to 150 nm. The insulating films 31 and 32 may be formed so as to satisfy, for example, Th1 / Th2>0.005. By configuring the insulating films 31 and 32 in this manner, it is possible to effectively suppress the diffusion of silicon from the insulating film 31 into the protective layer 25 and the like, and reduce the leakage current.

[0069] Next, an example of a manufacturing method of the semiconductor device 1 according to this embodiment will be described. First, a substrate 10 is prepared. For example, single crystal Si is used for the substrate 10. Note that the substrate 10 is, for example, a semiconductor wafer having a plurality of transistor formation regions before the dicing process. A buffer layer 21, a channel layer 22, a spacer layer 23, a barrier layer 24, and a protective layer 25 are sequentially stacked on the substrate 10. Each of the buffer layer 21, the channel layer 22, the spacer layer 23, the barrier layer 24, and the protective layer 25 will be further described.

[0070] The buffer layer 21 is formed on the substrate 10 by epitaxial growth (e.g., MOCVD). The buffer layer 21 is formed of one or more compound semiconductor layers selected from AlN, AlGaN, and GaN. The channel layer 22 is formed on the buffer layer 21 by epitaxial growth. The channel layer 22 is formed using, for example, GaN as a compound semiconductor layer.

[0071] The spacer layer 23 is formed on the channel layer 22 by epitaxial growth. The spacer layer 23 is formed as a compound semiconductor layer using, for example, a nitride semiconductor material including AlN. The barrier layer 24 is formed on the spacer layer 23 by epitaxial growth. The barrier layer 24 is formed as a compound semiconductor layer using, for example, a nitride semiconductor material.

[0072] The protective layer 25 is formed on the barrier layer 24 by one film formation method selected from the group consisting of epitaxial growth, atomic layer deposition (ALD), and chemical vapor deposition (CVD). Then, the semiconductor regions 26 a and 26 b are formed by, for example, regrowth. The semiconductor regions 26 a and 26 b may be formed after the gate electrode 40 is formed.

[0073] An insulating film 31 and an insulating film 32 are sequentially stacked between the gate electrode 40 and the source electrode 50a, and between the gate electrode 40 and the drain electrode 50b. The insulating film 31 is formed on the protective layer 25 by using, for example, the ALD method or the CVD method. The insulating film 31 is made of, for example, Al ２ O ３ The insulating film 32 is formed on the insulating film 31 by ALD, CVD, or sputtering. The insulating film 32 is formed as a single layer or a composite layer using an insulating material such as SiN.

[0074] A gate opening 35 is formed in the insulating film 32 in the region where the gate electrode 40 is to be formed. The gate opening 35 in the insulating film 32 is formed by, for example, dry etching or wet etching. When the gate opening 35 is formed in the insulating film 32, the surface of the underlying insulating film 31 is exposed. Subsequently, etching is performed in the thickness direction of the insulating film 31 by an etching method. The etching method may be dry etching or wet etching.

[0075] The gate opening 35 in the insulating film 31 is formed by etching using a mask formed by, for example, photolithography. As the etching method, for example, an anisotropic dry etching method is used in order to effectively suppress the expansion of the opening dimension.

[0076] The plasma energy during dry etching and the thermal energy generated when the light (e.g., deep ultraviolet light) having strong (high) energy emitted by the plasma is absorbed by the protective layer 25 and the barrier layer 24, etc., cause fluorine, supplied from the etching gas (SF6, CF4), to diffuse into the protective layer 25, the barrier layer 24, etc. At the same time, the Al insulating film 31 ２ O ３ The oxygen contained in the fluorine also diffuses into the protective layer 25 and the barrier layer 24 together with the fluorine.

[0077] Alternatively, fluorine and oxygen may be introduced (diffused) into the protective layer 25, the barrier layer 24, and the spacer layer 23 by wet etching using a solution containing fluorine, oxygen, or the like and heat treatment. As described above, dry etching or wet etching can be used to effectively inject fluorine, etc. into the protective layer 25, etc., while preventing damage.

[0078] In the case of a high-temperature environment (e.g., annealing) in the manufacturing process, the insulating film 31 suppresses the diffusion of Si contained in the insulating film 32. When a gate opening 35 is formed in the insulating film 32, the insulating film 31 can effectively suppress or prevent the diffusion of Si into the surface of the semiconductor layer (e.g., the protective layer 25).

[0079] Next, the gate electrode 40 is formed. A portion of the gate electrode 40 is electrically connected to and mechanically bonded to the protective layer 25 through the gate opening 35. The gate electrode 40 is formed, for example, by using a mask vapor deposition method. The gate electrode 40 is formed, for example, by sequentially stacking Ni and Au.

[0080] Then, a source electrode 50a and a drain electrode 50b are formed on the semiconductor region 26a (and the semiconductor region 26b) by sequentially depositing Ti, Al, Ni, and Au using, for example, a mask deposition method. The source electrode 50a is electrically connected to and mechanically bonded to the semiconductor region 26a. The drain electrode 50b is electrically connected to and mechanically bonded to the semiconductor region 26b.

[0081] The semiconductor device 1 can be manufactured by the manufacturing method described above. Through a series of processes, fluorine and oxygen can be diffused into the semiconductor layers (protective layer 25, barrier layer 24, etc.) below the gate electrode 40, while the diffusion of Si from the insulating film 32 into the protective layer 25 can be suppressed. It is possible to obtain a desired composition profile of fluorine, oxygen, and silicon. Note that the manufacturing method described above is merely an example, and other manufacturing methods may also be adopted.

[0082] [Operations and Effects] The semiconductor device (semiconductor device 1) according to this embodiment includes a channel layer (channel layer 22) containing a first nitride semiconductor, a semiconductor layer (e.g., barrier layer 24) stacked with the channel layer and containing a second nitride semiconductor, a gate electrode (gate electrode 40) and a drain electrode (drain electrode 50b) provided above the semiconductor layer, a first insulating film (insulating film 31) provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film (insulating film 32) containing silicon and stacked with the first insulating film. The semiconductor layer contains a halogen-group element below the gate electrode. The silicon content of the semiconductor layer below the gate electrode and the drain electrode is 2 atomic % or less.

[0083] In the semiconductor device 1 according to this embodiment, the semiconductor layer, for example, the barrier layer 24, below the gate electrode 40 contains fluorine as a halogen element. The silicon content of the semiconductor layer below the gate electrode 40 and the drain electrode 50b is 2 atomic % or less. This makes it possible to suppress leakage current in the semiconductor device 1. It is possible to realize a semiconductor device capable of reducing leakage current.

[0084] Next, a modified example of the present disclosure will be described. In the following, the same components as those in the above embodiment will be denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

[0085] <2. Modifications> (2-1. Modification 1) In the above-described embodiment, a configuration example of the semiconductor device 1 has been described, but this is merely an example, and the configuration of the semiconductor device 1 is not limited to the above-described example. Fig. 7 is a diagram for explaining a configuration example of a semiconductor device according to Modification 1 of the present disclosure. The semiconductor device 1 may have an underlayer 28 and a back barrier layer 29, as in the example shown in Fig. 7.

[0086] The underlayer 28 is provided, for example, so as to be stacked on the buffer layer 21. In the example shown in FIG. 7 , the underlayer 28 is provided on the buffer layer 21 and is located between the buffer layer 21 and the back barrier layer 29. The underlayer 28 may be made of GaN, for example. Alternatively, the underlayer 28 may be made of u-GaN to which no impurities have been added (undoped). The underlayer 28 may be formed by stacking a plurality of layers (films).

[0087] The back barrier layer 29 is provided so as to be stacked above the buffer layer 21. In the example shown in Fig. 7, the back barrier layer 29 is formed on the base layer 28 and is located between the base layer 28 and the channel layer 22. The back barrier layer 29 is made of, for example, a compound semiconductor material.

[0088] The back barrier layer 29 can be formed using a semiconductor material that is bonded to the channel layer 22 with band bending. ｘ Ga １－ｘThe back barrier layer 29 may be formed of an epitaxially grown layer of u-AlGaN (where 0≦x≦1) or u-AlGaN without doping with impurities. The back barrier layer 29 may be formed by stacking a plurality of films.

[0089] (2-2. Modification 2) In the above-described embodiment, an example has been described in which the semiconductor device 1 contains fluorine (F) as a halogen element in the region below the gate electrode 40. However, the semiconductor device 1 may be configured to contain another halogen element (for example, chlorine (Cl)) in the region below the gate electrode 40.

[0090] 3. Application Examples The semiconductor device 1 described above can be applied to, for example, various electronic devices having communication functions. Fig. 8 is a diagram showing a configuration example of a wireless communication device 200 according to the present disclosure. As shown in Fig. 8, the wireless communication device 200 includes an antenna ANT, an antenna switch circuit 201, a high-power amplifier HPA, a radio frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F.

[0091] The interface unit I / F is, for example, an interface circuit that uses a wireless local area network (W-LAN), Bluetooth (registered trademark), etc. The wireless communication device 200 is, for example, a mobile phone system that has multiple functions such as voice and data communication and LAN connection.

[0092] The wireless communication device 200 is configured by applying any of the semiconductor devices according to the above-described embodiments or modifications to the antenna switch circuit 201, the high power amplifier HPA, the radio frequency integrated circuit RFIC, the baseband unit BB, etc. For example, by applying the technology according to the present disclosure to the antenna switch circuit 201, the baseband unit BB, etc., it becomes possible to effectively suppress leakage current.

[0093] Although the present disclosure has been described above by way of embodiments, modifications, and application examples, the present technology is not limited to the above-described embodiments, etc., and various modifications are possible. For example, although the modifications described above have been described as modifications of the above-described embodiments, the configurations of the modifications can be combined as appropriate.

[0094] A semiconductor device according to an embodiment of the present disclosure includes a channel layer including a first nitride semiconductor, a semiconductor layer including a second nitride semiconductor and stacked with the channel layer, a gate electrode and a drain electrode provided above the semiconductor layer, a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film including silicon and stacked with the first insulating film. The semiconductor layer includes a halogen element below the gate electrode. The silicon content of the semiconductor layer below the gap between the gate electrode and the drain electrode is 2 atomic % or less. This makes it possible to realize a semiconductor device capable of reducing leakage current.

[0095] Note that the effects described in this specification are merely examples and are not limited to those described above, and other effects may be present. The present disclosure may also have the following configurations. (1) A semiconductor device comprising: a channel layer including a first nitride semiconductor; a semiconductor layer including a second nitride semiconductor and stacked with the channel layer; a gate electrode and a drain electrode provided above the semiconductor layer; a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode; and a second insulating film including silicon and stacked with the first insulating film, wherein the semiconductor layer contains a halogen element below the gate electrode, and the silicon content of the semiconductor layer below the gate electrode and the drain electrode is 2 atomic % or less. (2) The semiconductor device according to (1), wherein the semiconductor layer contains fluorine as the halogen element below the gate electrode. (3) The semiconductor device according to (1) or (2), wherein the maximum fluorine content in the semiconductor layer below the gate electrode is 0.5 atomic % or more. (4) The semiconductor device according to any one of (1) to (3), wherein the semiconductor layer contains oxygen below the gate electrode. (5) The semiconductor device according to (4), wherein the maximum oxygen content in the semiconductor layer below the gate electrode is 1 atomic % or more. (6) The semiconductor device according to any one of (1) to (5), further comprising a protective layer provided between the semiconductor layer and the gate electrode, wherein the semiconductor layer is a barrier layer containing a second nitride semiconductor, and wherein the protective layer and the semiconductor layer contain fluorine below the gate electrode. (7) The semiconductor device according to (6), wherein the maximum fluorine content in the protective layer and the semiconductor layer below the gate electrode is 0.5 atomic % or more. (8) The semiconductor device according to (6) or (7), wherein the protective layer and the semiconductor layer contain oxygen below the gate electrode.(9) The semiconductor device according to (8), wherein the maximum oxygen content in the protective layer and the semiconductor layer below the gate electrode is 1 atomic % or more. (10) The semiconductor device according to (8) or (9), wherein the protective layer and the semiconductor layer contain fluorine and oxygen at the interface between the protective layer and the semiconductor layer. (11) The semiconductor device according to any one of (8) to (10), wherein the protective layer and the semiconductor layer have a peak fluorine content and a peak oxygen content near the interface between the protective layer and the semiconductor layer. (12) The semiconductor device according to any one of (1) to (11), further comprising: a protective layer provided between the semiconductor layer and the gate electrode; and a spacer layer provided between the semiconductor layer and the channel layer, wherein the semiconductor layer is a barrier layer containing a second nitride semiconductor, the protective layer, the semiconductor layer, and the spacer layer contain fluorine below the gate electrode, and a maximum fluorine content in the protective layer, the semiconductor layer, and the spacer layer below the gate electrode is 0.5 atomic % or more. (13) The semiconductor device according to (12), wherein the protective layer, the semiconductor layer, and the spacer layer contain oxygen below the gate electrode, and a maximum oxygen content in the protective layer, the semiconductor layer, and the spacer layer below the gate electrode is 1 atomic % or more. (14) The semiconductor device according to (12) or (13), wherein the semiconductor layer and the spacer layer contain fluorine and oxygen at an interface between the semiconductor layer and the spacer layer. (15) The semiconductor device according to any one of (12) to (14), wherein the semiconductor layer and the spacer layer have a peak fluorine content and a peak oxygen content near the interface between the semiconductor layer and the spacer layer. (16) The semiconductor device according to any one of (1) to (15), wherein the film thickness of the first insulating film is greater than 1 nm. (17) The semiconductor device according to any one of (1) to (16), wherein, where Th1 is the film thickness of the first insulating film and Th2 is the film thickness of the second insulating film, Th1 / Th2>0.005 is satisfied.(18) The first insulating film is made of Al. ２ O ３ , AlN, HfO ２ , TiO ２ , NbO, Nb ２ O ５ , or Ta ２ O ５ (19) The semiconductor device according to any one of (1) to (17), wherein the second insulating film is made of SiN, SiO ２ , SiON, or AlSiO. (20) An electronic device comprising: a circuit having: a channel layer containing a first nitride semiconductor, a semiconductor layer containing a second nitride semiconductor and stacked on the channel layer, a gate electrode and a drain electrode provided above the semiconductor layer, a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode, and a second insulating film containing silicon and stacked on the first insulating film, wherein the semiconductor layer contains a halogen element below the gate electrode, and a silicon content of the semiconductor layer below the gate electrode and the drain electrode is 2 atomic % or less.

[0096] This application claims priority based on Japanese Patent Application No. 2023-213294, filed on December 18, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0097] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: a channel layer including a first nitride semiconductor; a semiconductor layer including a second nitride semiconductor and stacked with the channel layer; a gate electrode and a drain electrode provided above the semiconductor layer; a first insulating film provided above the semiconductor layer between the gate electrode and the drain electrode; and a second insulating film including silicon and stacked with the first insulating film, wherein the semiconductor layer includes a halogen element below the gate electrode, and the silicon content of the semiconductor layer below the gate electrode and the drain electrode is 2 atomic % or less.

2. The semiconductor device according to claim 1, wherein the semiconductor layer below the gate electrode contains fluorine as the halogen element.

3. The semiconductor device according to claim 2, wherein the maximum value of the fluorine content in the semiconductor layer below the gate electrode is 0.5 atomic % or more.

4. The semiconductor device according to claim 2, wherein the semiconductor layer contains oxygen below the gate electrode.

5. The semiconductor device according to claim 4, wherein the maximum oxygen content in the semiconductor layer below the gate electrode is 1 atomic % or more.

6. The semiconductor device according to claim 1, further comprising a protective layer provided between the semiconductor layer and the gate electrode, the semiconductor layer being a barrier layer containing a second nitride semiconductor, and the protective layer and the semiconductor layer containing fluorine below the gate electrode.

7. The semiconductor device according to claim 6, wherein the maximum value of the fluorine content in said protective layer and said semiconductor layer below said gate electrode is 0.5 atomic % or more.

8. The semiconductor device according to claim 6, wherein the protective layer and the semiconductor layer contain oxygen below the gate electrode.

9. The semiconductor device according to claim 8, wherein the maximum oxygen content in the protective layer and the semiconductor layer below the gate electrode is 1 atomic % or more.

10. The semiconductor device according to claim 8, wherein the protective layer and the semiconductor layer contain fluorine and oxygen at the interface between the protective layer and the semiconductor layer.

11. The semiconductor device according to claim 8, wherein the protective layer and the semiconductor layer have a peak in fluorine content and a peak in oxygen content near the interface between the protective layer and the semiconductor layer.

12. The semiconductor device according to claim 1, further comprising: a protective layer provided between the semiconductor layer and the gate electrode; and a spacer layer provided between the semiconductor layer and the channel layer, wherein the semiconductor layer is a barrier layer containing a second nitride semiconductor, the protective layer, the semiconductor layer and the spacer layer contain fluorine below the gate electrode, and a maximum value of the fluorine content in the protective layer, the semiconductor layer and the spacer layer below the gate electrode is 0.5 atomic % or more.

13. The semiconductor device according to claim 12, wherein the protective layer, the semiconductor layer and the spacer layer contain oxygen below the gate electrode, and a maximum value of the oxygen content in the protective layer, the semiconductor layer and the spacer layer below the gate electrode is 1 atomic % or more.

14. The semiconductor device according to claim 12, wherein the semiconductor layer and the spacer layer contain fluorine and oxygen at the interface between the semiconductor layer and the spacer layer.

15. The semiconductor device according to claim 12, wherein the semiconductor layer and the spacer layer have a peak in fluorine content and a peak in oxygen content in the vicinity of the interface between the semiconductor layer and the spacer layer.

16. The semiconductor device according to claim 1, wherein the first insulating film has a thickness greater than 1 nm.

17. The semiconductor device according to claim 1, wherein the following relationship is satisfied: Th1 / Th2>0.005, where Th1 is the thickness of the first insulating film and Th2 is the thickness of the second insulating film.

18. The first insulating film is Al ２ O ３ , AlN, HfO ２ , TiO ２ , NbO, Nb ２ O ５ , or Ta ２ O ５ The semiconductor device according to claim 1 , 19. The second insulating film is made of SiN, SiO ２ 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of silicon nitride, silicon nitride, or silicon oxide.

20. An electronic device comprising a circuit having: a channel layer containing a first nitride semiconductor; a semiconductor layer containing a second nitride semiconductor and disposed so as to be stacked with the channel layer; a gate electrode and a drain electrode disposed above the semiconductor layer; a first insulating film disposed above the semiconductor layer between the gate electrode and the drain electrode; and a second insulating film containing silicon and disposed so as to be stacked with the first insulating film, wherein the semiconductor layer contains a halogen element below the gate electrode, and the silicon content of the semiconductor layer below the area between the gate electrode and the drain electrode is 2 atomic % or less.

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