Solid-state imaging device

Abstract

[Problem] To provide a solid-state imaging device with which it is possible to suitably form various devices. [Solution] A solid-state imaging device according to the present disclosure comprises a first substrate, a photoelectric conversion unit that is provided within the first substrate and performs photoelectric conversion, and a holding unit that holds a charge or a voltage generated in response to the photoelectric conversion. The holding unit includes a first semiconductor layer formed from a first semiconductor having a band gap wider than the band gap of silicon (Si). The first semiconductor has a band gap of 3.0 eV or greater.

Description

solid-state imaging device

[0001] TECHNICAL FIELD An embodiment of the present disclosure relates to a solid-state imaging device.

[0002] In solid-state imaging devices, devices such as floating diffusion regions, pixel memories, and pixel transistors are often formed in or on a silicon substrate, and capacitors in solid-state imaging devices often have electrodes formed from metal layers or polysilicon layers.

[0003] JP 2014-160740 A International Patent Application Publication No. WO2019 / 131965 A

[0004] However, forming floating diffusion regions and pixel memories in a silicon substrate can cause problems such as PLS (parasitic light sensitivity) and dark signals. Also, forming pixel transistors on a silicon substrate can cause problems with leakage current from the pixel transistors. Furthermore, forming capacitor electrodes from a silicon layer can cause problems with leakage current from the capacitors.

[0005] Therefore, the present disclosure provides a solid-state imaging device that can suitably form the various devices described above.

[0006] A solid-state imaging device according to a first aspect of the present disclosure includes a first substrate, a photoelectric conversion unit provided within the first substrate and performing photoelectric conversion, and a holding unit that holds a charge or voltage generated in response to the photoelectric conversion, the holding unit including a first semiconductor layer formed of a first semiconductor having a band gap wider than that of Si (silicon), the first semiconductor having the band gap of 3.0 eV or greater, thereby enabling the holding unit to be suitably formed.

[0007] In this first aspect, the first semiconductor may contain In (indium), Ga (gallium), or Zn (zinc), which makes it possible to easily achieve a band gap of, for example, 3.0 eV or more.

[0008] In this first aspect, the holding portion may be a floating diffusion portion including the first semiconductor layer provided in the first substrate and holding the charge. This allows the floating diffusion portion to be suitably formed. For example, it is possible to suppress dark signals or suppress PLS by forming the floating diffusion portion without using a light-shielding layer.

[0009] In this first aspect, the storage unit may be a pixel memory including the first semiconductor layer provided in the first substrate and configured to store the charge. This allows the pixel memory to be suitably formed to suppress PLS. For example, it is possible to suppress dark signals or form the pixel memory without using a light-shielding layer.

[0010] In this first aspect, the first semiconductor layer may include both an n-type semiconductor layer and a p-type semiconductor layer, which makes it possible to suppress generation of carriers due to depletion, for example.

[0011] The solid-state imaging device of the first aspect may further include a first transistor provided on the first substrate, and the first semiconductor layer may be provided in the first substrate and function as a source region or a drain region of the first transistor, thereby making it possible to make the holding unit also function as the source region or the drain region of the first transistor, for example.

[0012] In this first aspect, the first transistor may be a transfer transistor that transfers the charge, which allows the holding portion to function as a source region or a drain region of the transfer transistor, for example.

[0013] In the first aspect, the holding unit may be a capacitor that includes the first semiconductor layer provided above the first substrate and holds the voltage. This allows the capacitor to be formed in a suitable manner. For example, it is possible to suppress leakage current from the capacitor.

[0014] The solid-state imaging device according to the first aspect may further include a second transistor electrically connected to the capacitor, thereby making it possible to suppress leakage current from the capacitor for the second transistor, for example.

[0015] In this first aspect, the second transistor may be a switch transistor that functions as a switch that electrically connects the capacitor and the amplification transistor, thereby making it possible to suppress, for example, a leakage current from a capacitor for the switch transistor.

[0016] In this first aspect, the capacitor may include a first electrode including the first semiconductor layer and a second electrode including a second semiconductor layer different from the first semiconductor layer, and the second transistor may be electrically connected to the first semiconductor layer, thereby making it possible to suppress leakage current from an electrode (first electrode) on the second transistor side, for example.

[0017] A solid-state imaging device according to a second aspect of the present disclosure includes a first substrate, a photoelectric conversion unit disposed within the first substrate and performing photoelectric conversion, a first transistor disposed on an upper surface of the first substrate, a first semiconductor layer disposed above the first substrate and spaced apart from the first substrate, the first semiconductor layer being formed from a first semiconductor having a bandgap wider than that of Si (silicon), and a second transistor disposed on an upper or lower surface of the first semiconductor layer. This allows the second transistor to be formed in an optimal manner. For example, it is possible to suppress leakage current from the second transistor.

[0018] In the second aspect, the first semiconductor may have a band gap of 3.0 eV or more, which makes it possible to form the second transistor more suitably.

[0019] In the second aspect, the first semiconductor may contain In (indium), Ga (gallium), or Zn (zinc), which makes it possible to easily achieve a band gap of, for example, 3.0 eV or more.

[0020] In the second aspect, the first semiconductor layer may be provided on the upper or lower surface of a second substrate disposed above the first substrate, which makes it possible to make the first semiconductor layer thinner and easier to prepare than when the first semiconductor layer is a substrate.

[0021] The solid-state imaging device according to the second aspect may further include a third substrate disposed above the second substrate and a third transistor provided on the lower surface of the third substrate, thereby enabling, for example, a logic circuit to be formed by the third transistor.

[0022] In the second aspect, the first semiconductor layer may be a second substrate disposed above the first substrate and formed of the first semiconductor, thereby making it possible to realize the first semiconductor layer by a substrate, for example.

[0023] The solid-state imaging device according to the second aspect may further include a third substrate disposed above the second substrate and a third transistor provided on the lower surface of the third substrate, thereby enabling, for example, a logic circuit to be formed by the third transistor.

[0024] The solid-state imaging device according to the second aspect may further include a holding unit that includes the first semiconductor layer and holds the charge or voltage generated in response to the photoelectric conversion, thereby enabling the holding unit to be suitably formed.

[0025] In the second aspect, the storage unit may be a pixel memory that stores the charge or a capacitor that stores the voltage. This allows the pixel memory or capacitor to be formed in an appropriate manner. For example, it is possible to suppress PLS and dark signals, form the pixel memory without using a light-shielding layer, and suppress leakage current from the capacitor.

[0026] 1 is a block diagram showing the configuration of a solid-state imaging device of a first embodiment; FIG. 2 is a circuit diagram showing the configuration of the solid-state imaging device of the first embodiment; FIG. 3 is a cross-sectional view and a plan view showing the structure of the solid-state imaging device of the first embodiment; FIG. 4 is a cross-sectional view and a band diagram for explaining the structure and characteristics of the solid-state imaging device of the first embodiment; FIG. 5 is a table for explaining the characteristics of the solid-state imaging device of the first embodiment; FIG. 6 is a cross-sectional view showing the structure of solid-state imaging devices of first and second comparative examples of the first embodiment; FIG. 7 is a cross-sectional view and a band diagram for explaining the structure and characteristics of a solid-state imaging device of a modified example of the first embodiment; FIG. 8 is a circuit diagram showing the configuration of a solid-state imaging device of a second embodiment; FIG. 9 is a cross-sectional view and a plan view showing the structure of a solid-state imaging device of the second embodiment; FIG. 10 is a cross-sectional view showing the structure of a solid-state imaging device of a first modified example of the second embodiment; FIG. 11 is a cross-sectional view and a plan view showing the structure of a solid-state imaging device of a second modified example of the second embodiment; FIG. 12 is a cross-sectional view showing the structure of solid-state imaging devices of a first and second comparative examples of the second embodiment; FIG. 13 is a circuit diagram showing the configuration of a solid-state imaging device of a third embodiment; FIG. 14 is a cross-sectional view showing the structure of a solid-state imaging device of a first comparative example of the third embodiment and the structure of a solid-state imaging device of the third embodiment; FIG. 15 is a cross-sectional view showing the structure of a solid-state imaging device of the third embodiment. 10. A cross-sectional view showing the structure of a solid-state imaging device according to a modification of the third embodiment. A cross-sectional view showing the structure of a solid-state imaging device according to a second comparative example of the third embodiment. A cross-sectional view showing the structure of a solid-state imaging device according to the fourth embodiment. A cross-sectional view showing the structure of a solid-state imaging device according to a first modification of the fourth embodiment. A cross-sectional view showing the structure of a solid-state imaging device according to a second modification of the fourth embodiment. A cross-sectional view showing the structure of a solid-state imaging device according to a third modification of the fourth embodiment. A circuit diagram showing the configuration of a solid-state imaging device according to a fourth modification of the fourth embodiment. A circuit diagram showing the configuration of a solid-state imaging device according to a fifth modification of the fourth embodiment. A circuit diagram showing the configuration of a solid-state imaging device according to a sixth modification of the fourth embodiment. A circuit diagram showing the configuration of a solid-state imaging device according to a seventh modification of the fourth embodiment. A circuit diagram showing the configuration of a solid-state imaging device according to an eighth modification of the fourth embodiment. A circuit diagram showing the configuration of a solid-state imaging device according to a ninth modification of the fourth embodiment. A circuit diagram showing the configuration of a solid-state imaging device according to a tenth modification of the fourth embodiment.46 is a circuit diagram showing the configuration of a solid-state imaging device according to an eleventh modified example of the fourth embodiment. FIG. 47 is a cross-sectional view showing the structure of a solid-state imaging device according to the fifth embodiment. FIG. 48 is a cross-sectional view showing a manufacturing method of a solid-state imaging device according to the fifth embodiment. FIG. 49 is a cross-sectional view showing the structure of a solid-state imaging device according to a sixth embodiment. FIG. 49 is a cross-sectional view (1 / 3) showing a manufacturing method of a solid-state imaging device according to the sixth embodiment. FIG. 49 is a cross-sectional view (2 / 3) showing a manufacturing method of a solid-state imaging device according to the sixth embodiment. FIG. 49 is a cross-sectional view (3 / 3) showing a manufacturing method of a solid-state imaging device according to the sixth embodiment. FIG. 49 is a cross-sectional view (1 / 2) showing a manufacturing method of a solid-state imaging device according to a modified example of the sixth embodiment. FIG. 49 is a cross-sectional view (2 / 2) showing a manufacturing method of a solid-state imaging device according to a modified example of the sixth embodiment. FIG. 49 is a cross-sectional view showing the structure of a solid-state imaging device according to a seventh embodiment. FIG. 49 is a cross-sectional view (1 / 2) showing a manufacturing method of a solid-state imaging device according to the ... showing the structure of a solid-state imaging device according to an eighth embodiment. FIG. 49 is a cross-sectional view showing the structure of a solid-state imaging device according to a modified example of the eighth embodiment. FIG. 49 is a block diagram showing a configuration example of an electronic device. FIG. 49 is a block diagram showing a configuration example of a mobile object 1 is a block diagram showing an example of a functional configuration of a camera head and a CCU of an endoscopic surgery system;

[0027] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0028] First Embodiment FIG. 1 is a block diagram showing the configuration of a solid-state imaging device according to a first embodiment.

[0029] The solid-state imaging device in FIG. 1 is a CMOS (Complementary Metal Oxide Semiconductor) type image sensor (CIS), and includes a pixel array 2 including a plurality of pixels 1, a control circuit 3, a vertical drive circuit 4, a plurality of column signal processing circuits 5, a horizontal drive circuit 6, an output circuit 7, a plurality of vertical signal lines (VSL) 8, and a horizontal signal line (HSL) 9.

[0030] Each pixel 1 includes a photodiode that functions as a photoelectric conversion unit and a MOS transistor that functions as a pixel transistor. Examples of the pixel transistor include a transfer transistor, a reset transistor, an amplification transistor, a selection transistor, and a switch transistor. These pixel transistors may be shared by several pixels 1.

[0031] The pixel array 2 includes a plurality of pixels 1 arranged in a two-dimensional array. The pixel array 2 also includes an effective pixel region that receives light, performs photoelectric conversion, and outputs signal charges generated by the photoelectric conversion, and a black reference pixel region that outputs optical black, which serves as a reference for the black level. In general, the black reference pixel region is arranged on the periphery of the effective pixel region.

[0032] The control circuit 3 generates various signals that serve as references for the operation of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, a master clock, etc. The signals generated by the control circuit 3 are, for example, clock signals and control signals, and are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0033] The vertical drive circuit 4 includes, for example, a shift register, and vertically scans each pixel 1 in the pixel array 2 row by row. The vertical drive circuit 4 further supplies a pixel signal based on the signal charge generated by each pixel 1 to a column signal processing circuit 5 through a vertical signal line 8.

[0034] The column signal processing circuit 5 is arranged, for example, for each column of pixels 1 in the pixel array 2, and performs signal processing for each column of signals output from one row of pixels 1 based on signals from the black reference pixel region. Examples of this signal processing include noise removal and signal amplification.

[0035] The horizontal drive circuit 6 includes, for example, a shift register, and supplies pixel signals from each column signal processing circuit 5 to a horizontal signal line 9 .

[0036] The output circuit 7 processes the signals supplied from each column signal processing circuit 5 through the horizontal signal line 9, and outputs the processed signals.

[0037] FIG. 2 is a circuit diagram showing the configuration of the solid-state imaging device of the first embodiment.

[0038] 2, each pixel 1 of this embodiment includes a photodiode PD, a floating diffusion region FD, a transfer transistor TG, a reset transistor RST, an amplifier transistor AMP, and a select transistor SEL. At least one of these transistors may be shared by several pixels 1.

[0039] The photodiode PD performs photoelectric conversion of incident light. The anode of the photodiode PD is electrically connected to the ground wiring, and the cathode of the photodiode PD is electrically connected to the transfer transistor TG. The act of irradiating light onto the photodiode PD is called exposing the photodiode PD.

[0040] The transfer transistor TG transfers the charges generated by the photoelectric conversion to the floating diffusion FD. One of the source and drain of the transfer transistor TG is electrically connected to the photodiode PD, and the other of the source and drain of the transfer transistor TG is electrically connected to the floating diffusion FD.

[0041] The floating diffusion FD accumulates the charges transferred by the transfer transistor TG and is electrically connected to the transfer transistor TG, the reset transistor RST, and the amplification transistor AMP.

[0042] Before exposure of the photodiode PD begins, the reset transistor RST drains charge from the floating diffusion FD and resets the potential of the floating diffusion FD to the potential of the power supply wiring (VDD). One of the source and drain of the reset transistor RST is electrically connected to the power supply wiring, and the other of the source and drain of the reset transistor RST is electrically connected to the floating diffusion FD.

[0043] The amplifier transistor AMP receives the charge transferred to the floating diffusion region FD at its gate and outputs it to the select transistor SEL via a source follower. The gate of the amplifier transistor AMP is electrically connected to the floating diffusion region FD. One of the source and drain of the amplifier transistor AMP is electrically connected to the power supply wiring, and the other of the source and drain of the amplifier transistor AMP is electrically connected to the select transistor SEL. The amplifier transistor AMP converts the charge accumulated in the floating diffusion region FD into a voltage signal and outputs it to the select transistor SEL.

[0044] The select transistor SEL can electrically connect the amplifier transistor AMP and VSL (vertical signal line 8: see FIG. 1). When the select transistor SEL is turned on, the amplifier transistor AMP and VSL are electrically connected, and when the select transistor SEL is turned off, the amplifier transistor AMP and VSL are electrically isolated. One of the source and drain of the select transistor SEL is electrically connected to the amplifier transistor AMP, and the other of the source and drain of the select transistor SEL is electrically connected to VSL.

[0045] 3A and 3B are a cross-sectional view and a plan view showing the structure of the solid-state imaging device of the first embodiment. Fig. 3A is a cross-sectional view showing almost the entirety of one pixel 1 and parts of two pixels 1. Fig. 3B is a plan view showing the planar structure of one pixel 1.

[0046] 3A and 3B show X-axis, Y-axis, and Z-axis that are perpendicular to each other. The X-axis and Y-axis correspond to the lateral direction (horizontal direction), and the Z-axis corresponds to the longitudinal direction (vertical direction). The +Z-axis corresponds to the upward direction, and the -Z-axis corresponds to the downward direction. Note that the -Z-axis may or may not strictly coincide with the direction of gravity.

[0047] 3A and 3B , the solid-state imaging device of this embodiment includes a substrate 11, a lens layer 12, an interlayer insulating film 13, and three wiring layers 14, 15, and 16. The substrate 11 is an example of a first substrate of the present disclosure.

[0048] The structure of the solid-state imaging device of this embodiment will be described below with reference to Fig. 3A. In this description, Fig. 3B will also be referred to as appropriate.

[0049] The substrate 11 is, for example, a Si (silicon) substrate. However, the substrate 11 may be a semiconductor substrate other than a Si substrate. In Fig. 3A, the X direction and the Y direction are parallel to the upper and lower surfaces of the substrate 11, and the Z direction is perpendicular to the upper and lower surfaces of the substrate 11. In Fig. 3A, the lower surface of the substrate 11 is the front surface S1 of the substrate 11, and the upper surface of the substrate 11 is the back surface S2 of the substrate 11.

[0050] As shown in FIGS. 3A and 3B , each pixel 1 includes a photodiode PD and a floating diffusion FD within a substrate 11. The photodiode PD converts light incident on each pixel 1 into an electric charge through photoelectric conversion. The floating diffusion FD holds the electric charge generated in response to the photoelectric conversion. In each pixel 1 of this embodiment, the floating diffusion FD is disposed laterally of the photodiode PD. The photodiode PD and the floating diffusion FD are examples of a photoelectric conversion unit and a holding unit, respectively, of the present disclosure.

[0051] In this embodiment, the photodiode PD is part of the substrate 11, but the floating diffusion FD is not. The floating diffusion FD in this embodiment is a wide band gap (WBG) layer formed in the substrate 11. The WBG layer is formed of a WBG material, which is a semiconductor having a band gap wider than that of Si. The floating diffusion FD in this embodiment is formed of a WBG material having a band gap of 3.0 eV or greater and containing In (indium), Ga (gallium), or Zn (zinc). An example of the WBG material in this embodiment is IGZO, which contains In, Ga, Zn, and O (oxygen). The WBG material is an example of a first semiconductor in this disclosure, and the WBG layer is an example of a first semiconductor layer in this disclosure.

[0052] The lens layer 12 is formed on the upper surface of the substrate 11. The lens layer 12 in each pixel 1 acts as a lens that collects incident light. The light collected by the lens is incident on the photodiode PD in each pixel 1.

[0053] The lens layer 12 may be formed on the substrate 11 via a color filter layer (not shown). In this case, the color filter layer in each pixel 1 acts as a color filter that transmits light of a predetermined wavelength. The light collected by the lens passes through the color filter and enters the photodiode PD in each pixel 1.

[0054] The interlayer insulating film 13 is formed on the lower surface of the substrate 11. The wiring layers 14 to 16 are formed in the interlayer insulating film 13 below the substrate 11 and are stacked in order in the Z direction. Each of the wiring layers 14 to 16 includes a plurality of wires. The wiring layers 14 to 16 form a multilayer wiring structure of the solid-state imaging device. In this embodiment, the wiring layers 14 to 16 form a multilayer wiring structure including three layers, but may also form a multilayer wiring structure including N layers (N is a positive integer) other than three layers.

[0055] Although the solid-state imaging device of this embodiment is a back-illuminated type, it may be a front-illuminated type.

[0056] FIG. 4 is a cross-sectional view and a band diagram for explaining the structure and characteristics of the solid-state imaging device of the first embodiment.

[0057] Fig. 4A is a cross-sectional view showing the details of the structure shown in Fig. 3A. However, the orientation of the solid-state imaging device shown in Fig. 4A is opposite to that of the solid-state imaging device shown in Fig. 3A. In Fig. 4A, the upper surface of the substrate 11 is the surface S1 of the substrate 11.

[0058] 4A , the solid-state imaging device of this embodiment includes a p-type semiconductor region 11a, an n-type semiconductor region 11b, a p-type semiconductor region 11c, and an n-type WBG layer 11d within a substrate 11. The p-type semiconductor region 11a, the n-type semiconductor region 11b, and the p-type semiconductor region 11c are part of the substrate 11, but the n-type WBG layer 11d is not part of the substrate 11. The n-type WBG layer 11d is an n-type semiconductor layer formed of a WBG material within the substrate 11. The n-type WBG layer 11d is an example of a first semiconductor layer of the present disclosure. In FIG. 4A , the photodiode PD is formed by a pn junction between the n-type semiconductor region 11b and the p-type semiconductor region 11c, and the floating diffusion FD is formed by the n-type WBG layer 11d.

[0059] 4A , the solid-state imaging device of this embodiment further includes a transistor 17 formed on the upper surface (surface S1) of the substrate 11. The transistor 17 includes a gate insulating film 17a and a gate electrode 17b, which are provided in this order on the p-type semiconductor region 11a, and a sidewall insulating film 17c provided on the side of the gate electrode 17b. The transistor 17 is, for example, a transfer transistor TG. The n-type WBG layer 11d of this embodiment also functions as a source region or a drain region of the transistor 17. The transistor 17 is an example of a first transistor of the present disclosure.

[0060] 4A , the solid-state imaging device of this embodiment further includes an element isolation insulating film 18 formed in the substrate 11. The element isolation insulating film 18 does not have to penetrate the substrate 11 in the Z direction, or may penetrate the substrate 11 in the Z direction. The element isolation insulating film 18 is, for example, a pixel isolation insulating film provided between adjacent pixels 1.

[0061] FIG. 4B shows the Fermi level E in the structure including the gate electrode 17b, the n-type WBG layer 11d, and the p-type semiconductor region 11a. ｆ The details of FIG. 4B will be described later.

[0062] FIG. 5 is a table for explaining the characteristics of the solid-state imaging device of the first embodiment.

[0063] FIG. 5 shows the energy of various types of visible light. Specifically, FIG. 5 shows the energy of red, orange, yellow, green, light blue, blue, and violet visible light. According to FIG. 5, the energy of visible light is less than 3.0 eV in all wavelength ranges (frequency ranges) of red, orange, yellow, green, light blue, and blue. Furthermore, violet visible light also includes a wavelength range (frequency range) in which the energy is less than 3.0 eV.

[0064] Therefore, the floating diffusion portion FD (n-type WBG layer 11d) of this embodiment is made of a WBG material having a band gap of 3.0 eV or more. The reason for using such a WBG material will be described in more detail later.

[0065] 6A and 6B are cross-sectional views showing the structures of solid-state imaging devices of first and second comparative examples of the first embodiment. The cross-sectional views of Fig. 6A and Fig. 6B correspond to the cross-sectional view of Fig. 3A.

[0066] FIG. 6A shows a solid-state imaging device of a first comparative example. The solid-state imaging device of this comparative example has a structure similar to that of the solid-state imaging device of the first embodiment. However, the floating diffusion FD of this comparative example is part of the substrate 11 and is therefore formed of Si rather than a WBG material. If the floating diffusion FD is formed of Si, there is a risk of PLS ​​and dark signals being generated. FIG. 6A shows, using arrows and figures shown above the floating diffusion FD, a schematic representation of how light is incident on the floating diffusion FD and how PLS is generated in the floating diffusion FD.

[0067] 6B shows a solid-state imaging device of a second comparative example. The solid-state imaging device of this comparative example has a structure similar to that of the solid-state imaging device of the first comparative example. However, the solid-state imaging device of this comparative example includes a light-shielding layer 19 formed in the substrate 11. The light-shielding layer 19 is arranged to suppress light from entering the floating diffusion FD. However, the light-shielding layer 19 cannot completely prevent light from entering the floating diffusion FD. Therefore, even in this comparative example, PLS of the floating diffusion FD may occur.

[0068] On the other hand, the solid-state imaging device of this embodiment has a floating diffusion FD formed of a WBG material instead of Si. The WBG material has a band gap wider than that of Si, making it less likely for current to leak from the WBG material. Therefore, this embodiment makes it possible to suppress dark signals.

[0069] Furthermore, according to this embodiment, as shown in FIG. 3A , it is possible to adopt a structure in which the floating diffusion FD is formed without using a light-shielding layer 19. This is because the floating diffusion FD itself has properties that make it less susceptible to PLS. The floating diffusion FD of this embodiment is formed of a WBG material with a bandgap of 3.0 eV or greater. This makes it less likely for PLS to occur in the floating diffusion FD, even when various types of visible light are incident on the floating diffusion FD. This is because most visible light has an energy of less than 3.0 eV (see FIG. 5 ). A WBG material with a bandgap of 3.0 eV or greater can be achieved, for example, by forming the WBG material from IGZO.

[0070] Generally, a solid-state imaging device includes a color filter that transmits red (R) visible light, a color filter that transmits green (G) visible light, and a color filter that transmits blue (B) visible light. Therefore, the light incident on the floating diffusion FD is often red, green, or blue visible light. As shown in FIG. 5 , the energy of visible light is less than 3.0 eV in all wavelength (frequency) ranges of red, green, and blue. Therefore, according to this embodiment, PLS can be effectively suppressed by forming the floating diffusion FD using a WBG material with a band gap of 3.0 eV or more.

[0071] The floating diffusion FD of this embodiment may be formed of a WBG material other than IGZO. For example, the floating diffusion FD of this embodiment may be formed of SiC, GaN, Ga ２ O ３ , Ga ２ O ５ , AlGaN, AlN, BN, or diamond (C stands for carbon, N stands for nitrogen, Al stands for aluminum, and B stands for boron).

[0072] 7A and 7B are a cross-sectional view and a band diagram for explaining the structure and characteristics of a solid-state imaging device according to a modification of the first embodiment, respectively.

[0073] 7A shows a solid-state imaging device according to this modification. The solid-state imaging device according to this modification has a structure similar to that of the solid-state imaging device according to the first embodiment. However, the solid-state imaging device according to this modification includes a p-type semiconductor region 11a, an n-type semiconductor region 11b, a p-type semiconductor region 11c, an n-type WBG layer 11d, and a p-type WBG layer 11e within a substrate 11. Like the n-type WBG layer 11d, the p-type WBG layer 11e is not part of the substrate 11. The p-type WBG layer 11e is a p-type semiconductor layer formed of a WBG material within the substrate 11 and is provided below the n-type WBG layer 11d. Like the n-type WBG layer 11d, the p-type WBG layer 11e is an example of the first semiconductor layer of the present disclosure. The floating diffusion FD according to this modification is formed by the n-type WBG layer 11d and the p-type WBG layer 11e. Of the n-type WBG layer 11d and the p-type WBG layer 11e, only the n-type WBG layer 11d may be considered as the floating diffusion portion FD.

[0074] FIG. 7B shows the Fermi level E in the structure including the gate electrode 17b, the n-type WBG layer 11d, the p-type WBG layer 11e, and the p-type semiconductor region 11a. ｆ This shows:

[0075] Here, the structure of the first embodiment shown in Figures 4A and 4B is compared with the structure of this modified example shown in Figures 7A and 7B. In the first embodiment, there is a concern about crystal defects at the interface between the n-type WBG layer 11d and the p-type semiconductor region 11a. Therefore, in this modified example, a p-type WBG layer 11e is disposed between the n-type WBG layer 11d and the p-type semiconductor region 11a. This makes it possible to change the band structure shown in Figure 4B to the band structure shown in Figure 7B, thereby reducing leakage current.

[0076] As described above, the solid-state imaging device of this embodiment includes a floating diffusion FD formed of a WBG material, which is a semiconductor having a bandgap wider than that of Si. For example, the floating diffusion FD of this embodiment is formed of a WBG material having a bandgap of 3.0 eV or more. Therefore, this embodiment makes it possible to form a suitable floating diffusion FD that can suppress PLS and dark signals.

[0077] Second Embodiment FIG. 8 is a circuit diagram showing the configuration of a solid-state imaging device according to a second embodiment.

[0078] In the solid-state imaging device of this embodiment, the floating diffusion region FD, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are shared by two pixels 1. The arrangement of these components is the same as in the solid-state imaging device of the first embodiment ( FIG. 2 ).

[0079] 8, each pixel 1 of this embodiment includes a photodiode PD, a pixel memory MEM, a transfer transistor TG, a transfer transistor TX, and an overflow gate transistor OFG. The solid-state imaging device of this embodiment has a charge domain global shutter function (CDGS).

[0080] The following describes the arrangement and functions of the components shown in Fig. 8. In the description of Fig. 8, descriptions of matters common to the description of Fig. 2 will be omitted as appropriate.

[0081] The photodiode PD performs photoelectric conversion of incident light. The anode of the photodiode PD is electrically connected to the ground wiring, and the cathode of the photodiode PD is electrically connected to the transfer transistor TX and the overflow gate transistor OFG.

[0082] The transfer transistor TX transfers the charges generated by the photoelectric conversion to the pixel memory MEM. One of the source and drain of the transfer transistor TX is electrically connected to the photodiode PD and the overflow gate transistor OFG, and the other of the source and drain of the transfer transistor TX is electrically connected to the pixel memory MEM and the transfer transistor TG.

[0083] The pixel memory MEM temporarily stores the charge transferred by the transfer transistor TX. The pixel memory MEM is electrically connected to the transfer transistor TX and the transfer transistor TG.

[0084] The transfer transistor TG transfers the charge temporarily stored in the pixel memory MEM to the floating diffusion FD. One of the source and drain of the transfer transistor TG is electrically connected to the pixel memory MEM and the transfer transistor TX, and the other of the source and drain of the transfer transistor TG is electrically connected to the floating diffusion FD.

[0085] The overflow gate transistor OFG drains charge from the photodiode PD and resets the potential of the photodiode PD to the potential of the power supply wiring. One of the source and drain of the overflow gate transistor OFG is electrically connected to the transfer transistor TX and the photodiode PD, and the other of the source and drain of the overflow gate transistor OFG is electrically connected to the power supply wiring.

[0086] 9A and 9B are a cross-sectional view and a plan view showing the structure of a solid-state imaging device according to the second embodiment, respectively corresponding to FIGS. 3A and 3B.

[0087] Similar to the solid-state imaging device of the first embodiment, the solid-state imaging device of this embodiment includes a substrate 11, a lens layer 12, an interlayer insulating film 13, and wiring layers 14, 15, and 16. The structure of the solid-state imaging device of this embodiment will be described below with reference to Figures 9A and 9B. In the description of Figures 9A and 9B, descriptions of matters common to the description of Figures 3A and 3B will be omitted.

[0088] 9A and 9B , each pixel 1 includes a photodiode PD and a pixel memory MEM within a substrate 11. The photodiode PD converts light incident on each pixel 1 into an electric charge through photoelectric conversion. The pixel memory MEM temporarily stores the electric charge generated in response to the photoelectric conversion until it is transferred to a floating diffusion region ( FIG. 8 ). In each pixel 1 of this embodiment, the pixel memory MEM is disposed laterally of the photodiode PD. The pixel memory MEM is an example of a storage region of the present disclosure.

[0089] In this embodiment, the photodiode PD is part of the substrate 11, but the pixel memory MEM is not part of the substrate 11. The pixel memory MEM in this embodiment is a WBG layer formed in the substrate 11, similar to the floating diffusion FD in the first embodiment. The pixel memory MEM in this embodiment also has a band gap of 3.0 eV or more and is formed of a WBG material containing In, Ga, or Zn. The WBG material in this embodiment is also, for example, IGZO containing In, Ga, Zn, and O.

[0090] Like the solid-state imaging device of the second comparative example of the first embodiment ( FIG. 6B ), the solid-state imaging device of this embodiment includes a light-shielding layer 19 formed in the substrate 11. However, the light-shielding layer 19 of this embodiment is formed only in a limited area compared to the light-shielding layer 19 of the comparative example.

[0091] Furthermore, although the solid-state imaging device of this embodiment is a back-illuminated type, it may be a front-illuminated type.

[0092] Fig. 10 is a cross-sectional view showing the structure of the solid-state imaging device according to the second embodiment, and corresponds to Fig. 4A.

[0093] 10, the solid-state imaging device of this embodiment, like the solid-state imaging device of the first embodiment, includes a p-type semiconductor region 11a, an n-type semiconductor region 11b, a p-type semiconductor region 11c, and an n-type WBG layer 11d within a substrate 11. The solid-state imaging device of this embodiment further includes an n-type WBG layer 11f within the substrate 11, as shown in FIG.

[0094] The n-type WBG layer 11f, like the n-type WBG layer 11d, is not part of the substrate 11. The n-type WBG layer 11f is an n-type semiconductor layer formed of a WBG material within the substrate 11. Like the n-type WBG layer 11d, the n-type WBG layer 11f is an example of the first semiconductor layer of the present disclosure. In FIG. 10 , the pixel memory MEM is formed of the n-type WBG layer 11f.

[0095] 10, the solid-state imaging device of this embodiment further includes a transistor 17 and an element isolation insulating film 18, similar to the solid-state imaging device of the first embodiment. The solid-state imaging device of this embodiment further includes a transistor 21, as shown in FIG.

[0096] The transistor 21 includes a gate insulating film 21a and a gate electrode 21b provided in this order on the p-type semiconductor region 11a, and a sidewall insulating film 21c provided on a side surface of the gate electrode 21b. The transistor 21 is, for example, a transfer transistor TX. The n-type WBG layer 11f of this embodiment also functions as a source region or drain region of the transistor 17, or as a source region or drain region of the transistor 21. Like the transistor 17, the transistor 21 is an example of a first transistor of the present disclosure.

[0097] The solid-state imaging device of this embodiment includes a floating diffusion region FD and a pixel memory MEM formed of a WBG material instead of Si. Therefore, according to this embodiment, similar to the first embodiment, it is possible to suppress PLS and dark signals. Furthermore, according to this embodiment, by forming the floating diffusion region FD and the pixel memory MEM from a WBG material having a band gap of 3.0 eV or more, it is possible to effectively suppress PLS and dark signals.

[0098] The pixel memory MEM of this embodiment may be formed of a WBG material other than IGZO, similar to the floating diffusion portion FD of this embodiment. For example, the pixel memory MEM of this embodiment may be formed of SiC, GaN, Ga ２ O ３ , Ga ２ O ５ , AlGaN, AlN, BN, or diamond.

[0099] 11 is a cross-sectional view showing the structure of a solid-state imaging device according to a first modification of the second embodiment, and corresponds to FIG.

[0100] Similar to the solid-state imaging device of the second embodiment (FIG. 10), the solid-state imaging device of this modification includes a p-type semiconductor region 11a, an n-type semiconductor region 11b, a p-type semiconductor region 11c, an n-type WBG layer 11d, and an n-type WBG layer 11f within a substrate 11. Similar to the solid-state imaging device of the modification of the first embodiment (FIG. 7A), the solid-state imaging device of this modification also includes a p-type WBG layer 11e within the substrate 11. As shown in FIG. 11, the solid-state imaging device of this modification also includes a p-type WBG layer 11g within the substrate 11.

[0101] Like the n-type WBG layer 11f, the p-type WBG layer 11g is not part of the substrate 11. The p-type WBG layer 11g is a p-type semiconductor layer formed of a WBG material in the substrate 11 and is provided below the n-type WBG layer 11f. Like the n-type WBG layer 11f, the p-type WBG layer 11g is an example of the first semiconductor layer of the present disclosure. The pixel memory MEM of this modification is formed of the n-type WBG layer 11f and the p-type WBG layer 11g. According to this modification, as with the modification of the first embodiment, it is possible to suppress the occurrence of crystal defects at the interface between the n-type WBG layer 11f and the p-type semiconductor region 11a.

[0102] 12A and 12B are a cross-sectional view and a plan view showing the structure of a solid-state imaging device according to a second modification of the second embodiment, respectively corresponding to FIGS. 9A and 9B.

[0103] The solid-state imaging device of this modification has the same components as the solid-state imaging device of the second embodiment. However, in each pixel 1 of this modification, the pixel memory MEM is arranged in the vertical direction of the photodiode PD, rather than in the horizontal direction of the photodiode PD. Specifically, the pixel memory MEM is arranged below the photodiode PD in FIG. 12A . As a result, for example, when the area of ​​the pixel 1 is the same, it is possible to improve the sensitivity and saturation signal amount by increasing the area of ​​the photodiode PD.

[0104] FIG. 13 is a cross-sectional view showing the structure of a solid-state imaging device of a first comparative example and a second comparative example of the second embodiment.

[0105] FIG. 13A shows a solid-state imaging device of the first comparative example. This solid-state imaging device has a structure similar to that of the solid-state imaging device of the second embodiment ( FIG. 9A ). However, the pixel memory MEM of this comparative example is part of the substrate 11 and is therefore formed of Si rather than a WBG material. If the pixel memory MEM were formed of Si, there is a risk of PLS ​​and dark signals being generated. Therefore, the solid-state imaging device of this comparative example is provided with a light-shielding layer 19 covering a wide area to prevent light from entering the pixel memory MEM. However, this light-shielding layer 19 cannot completely prevent light from entering the pixel memory MEM.

[0106] On the other hand, the solid-state imaging device of this embodiment includes a pixel memory MEM formed of a WBG material instead of Si ( FIG. 9A ). This makes it possible to suppress PLS and dark signals even if the light-shielding layer 19 is formed only in a limited area. The light-shielding layer 19 of this embodiment ( FIG. 9A ) is formed only in the area between pixels 1.

[0107] FIG. 13B shows a solid-state imaging device of a second comparative example. This solid-state imaging device has a structure similar to that of the solid-state imaging device of the second modified example of the second embodiment ( FIG. 12A ). However, the pixel memory MEM of this comparative example is part of the substrate 11 and is therefore formed of Si rather than a WBG material. If the pixel memory MEM is formed of Si, there is a risk of PLS ​​and dark signals being generated. Therefore, the solid-state imaging device of this comparative example is provided with a light-shielding layer 19 over a wide area to prevent light from entering the pixel memory MEM.

[0108] On the other hand, the solid-state imaging device of the second modification has a pixel memory MEM made of a WBG material instead of Si ( FIG. 12A ). This makes it possible to suppress PLS and dark signals even if the light-shielding layer 19 is formed only in a limited area. The light-shielding layer 19 in FIG. 12A is formed only in the area between pixels 1.

[0109] As described above, the solid-state imaging device of this embodiment includes a pixel memory MEM formed of a WBG material, which is a semiconductor having a bandgap wider than that of Si. For example, the pixel memory MEM of this embodiment is formed of a WBG material having a bandgap of 3.0 eV or more. Therefore, this embodiment makes it possible to form a suitable pixel memory MEM that can suppress PLS and dark signals.

[0110] Third Embodiment FIG. 14 is a circuit diagram showing the configuration of a solid-state imaging device according to a third embodiment.

[0111] As shown in Fig. 14, the solid-state imaging device of this embodiment has a two-story structure including a first floor indicated by reference symbol F1 and a second floor indicated by reference symbol F2. The dashed line shown in Fig. 14 indicates the boundary between the first and second floors. Further details of the two-story structure will be described later.

[0112] As shown in FIG. 14 , each pixel 1 of this embodiment includes, on the first floor, a photodiode PD, a floating diffusion region FD, a transfer transistor TG, a reset transistor RST, a conversion efficiency switching transistor FDG, an amplification transistor SF1 (=AMP), a switch transistor SW, an overflow gate transistor OFG, capacitors Ca, Cb, and switch transistors Sa, Sb. Each pixel 1 of this embodiment further includes, on the second floor, a current source transistor PC, a subsequent current source transistor VB, a VREG voltage transistor RB, a subsequent amplification transistor SF2, and a selection transistor SEL. At least one of these transistors may be shared by several pixels 1. The solid-state imaging device of this embodiment has a voltage-domain global shutter function (VDGS).

[0113] The following describes the arrangement and functions of the components shown in Fig. 14. In the description of Fig. 14, descriptions of matters common to the descriptions of Figs. 2 and 8 will be omitted as appropriate.

[0114] The photodiode PD performs photoelectric conversion of incident light. The anode of the photodiode PD is electrically connected to the ground wiring, and the cathode of the photodiode PD is electrically connected to the transfer transistor TG and the overflow gate transistor OFG.

[0115] The transfer transistor TG transfers the charges generated by the photoelectric conversion to the floating diffusion FD. One of the source and drain of the transfer transistor TG is electrically connected to the photodiode PD and the overflow gate transistor OFG, and the other of the source and drain of the transfer transistor TG is electrically connected to the floating diffusion FD.

[0116] The floating diffusion FD accumulates the charges transferred by the transfer transistor TG and is electrically connected to the transfer transistor TG, the conversion efficiency switching transistor FDG, and the amplification transistor SF1.

[0117] The reset transistor RST drains electric charges from the floating diffusion region FD and resets the potential of the floating diffusion region FD to the potential of the power supply line before the exposure of the photodiode PD starts. One of the source and drain of the reset transistor RST is electrically connected to the power supply line, and the other of the source and drain of the reset transistor RST is electrically connected to the conversion efficiency switching transistor FDG.

[0118] The conversion efficiency switching transistor FDG functions as a switch for switching the conversion efficiency of photoelectric conversion by the photodiode PD. One of the source and drain of the conversion efficiency switching transistor FDG is electrically connected to the floating diffusion region FD, and the other of the source and drain of the conversion efficiency switching transistor FDG is electrically connected to the reset transistor RST.

[0119] The amplifier transistor SF1 receives the charge transferred to the floating diffusion region FD at its gate and outputs the charge to the switch transistor SW via a source follower. The gate of the amplifier transistor SF1 is electrically connected to the floating diffusion region FD. One of the source and drain of the amplifier transistor SF1 is electrically connectable to a power supply wiring, and the other of the source and drain of the amplifier transistor SF1 is electrically connected to the switch transistor SW. The amplifier transistor SF1 converts the charge accumulated in the floating diffusion region FD into a voltage signal and outputs it to the switch transistor SW.

[0120] The switch transistor SW functions as a switch that electrically connects the amplifier transistor SF1 and the capacitors Ca and Cb. When the switch transistor SW is turned on, the amplifier transistor SF1 and the capacitors Ca and Cb are electrically connected, and when the switch transistor SW is turned off, the amplifier transistor SF1 and the capacitors Ca and Cb are electrically isolated. One of the source and drain of the switch transistor SW is electrically connected to the amplifier transistor SF1, and the other of the source and drain of the switch transistor SW is electrically connected to the current source transistor PC and the capacitors Ca and Cb.

[0121] The overflow gate transistor OFG drains charge from the photodiode PD and resets the potential of the photodiode PD to the potential of the power supply wiring. One of the source and drain of the overflow gate transistor OFG is electrically connected to the transfer transistor TG and the photodiode PD, and the other of the source and drain of the overflow gate transistor OFG is electrically connected to the power supply wiring.

[0122] The capacitors Ca and Cb are electrically connected to a node V1 between the switch transistor SW and the current source transistor PC. One electrode of the capacitor Ca is electrically connected to the node V1, and the other electrode of the capacitor Ca is electrically connected to the switch transistor Sa. One electrode of the capacitor Cb is electrically connected to the node V1, and the other electrode of the capacitor Cb is electrically connected to the switch transistor Sb. The capacitors Ca and Cb are connected in parallel to the node V1.

[0123] The switch transistor Sa can electrically connect the capacitor Ca and the post-amplification transistor SF2. When the switch transistor Sa is turned on, the capacitor Ca and the post-amplification transistor SF2 are electrically connected, and when the switch transistor Sa is turned off, the capacitor Ca and the post-amplification transistor SF2 are electrically isolated. One of the source and drain of the switch transistor Sa is electrically connected to the capacitor Ca, and the other of the source and drain of the switch transistor Sa is electrically connected to the VREG voltage transistor RB and the post-amplification transistor SF2.

[0124] The switch transistor Sb can electrically connect the capacitor Cb and the post-amplification transistor SF2. When the switch transistor Sb is turned on, the capacitor Cb and the post-amplification transistor SF2 are electrically connected, and when the switch transistor Sb is turned off, the capacitor Cb and the post-amplification transistor SF2 are electrically isolated. One of the source and drain of the switch transistor Sb is electrically connected to the capacitor Cb, and the other of the source and drain of the switch transistor Sb is electrically connected to the VREG voltage transistor RB and the post-amplification transistor SF2.

[0125] The VREG voltage transistor RB is electrically connected to a node V2 between the switch transistors Sa, Sb and the rear-stage amplification transistor SF2. When the VREG voltage transistor RB is turned on, the VREG voltage is supplied to the node V2.

[0126] The post-amplification transistor SF2 receives the charges output by the capacitors Ca and Cb at its gate and outputs the charges to VSL (vertical signal line 8: see FIG. 1) via a source follower. The gate of the post-amplification transistor SF2 is electrically connected to the capacitors Ca and Cb and the VREG voltage transistor RB. One of the source and drain of the post-amplification transistor SF2 is electrically connected to the power supply wiring, and the other of the source and drain of the post-amplification transistor SF2 is electrically connected to the selection transistor SEL.

[0127] The select transistor SEL can electrically connect the post-amplification transistor SF2 and VSL. When the select transistor SEL is turned on, the post-amplification transistor SF2 and VSL are electrically connected, and when the select transistor SEL is turned off, the post-amplification transistor SF2 and VSL are electrically isolated. One of the source and drain of the select transistor SEL is electrically connected to the post-amplification transistor SF2, and the other of the source and drain of the select transistor SEL is electrically connected to VSL.

[0128] The current source transistor PC and the subsequent-stage current source transistor VB function as a current source. One of the source and drain of the current source transistor PC is electrically connected to the switch transistor SW, and the other of the source and drain of the current source transistor PC is electrically connected to the subsequent-stage current source transistor VB. One of the source and drain of the subsequent-stage current source transistor VB is electrically connected to the current source transistor PC.

[0129] FIG. 15 is a cross-sectional view showing the structure of a solid-state imaging device of a first comparative example of the third embodiment and the structure of the solid-state imaging device of the third embodiment.

[0130] 15A shows the planar structure of the first floor of a solid-state imaging device of the first comparative example. Specifically, Fig. 15A shows the layout of gate electrodes of pixel transistors formed on the upper surface (surface S1) of the substrate 11. The solid-state imaging device of this comparative example includes, on the upper surface of the substrate 11, a transfer transistor TG, a reset transistor RST, a conversion efficiency switching transistor FDG, an amplification transistor AMP, a switch transistor SW, and an overflow gate transistor OFG.

[0131] 15B shows the planar structure of the first floor of the solid-state imaging device of the third embodiment. Fig. 15B also shows the layout of the gate electrodes of the pixel transistors formed on the upper surface (surface S1) of the substrate 11. The solid-state imaging device of this embodiment includes a transfer transistor TG, a reset transistor RST, a conversion efficiency switching transistor FDG, an amplification transistor AMP, and an overflow gate transistor OFG on the upper surface of the substrate 11.

[0132] On the other hand, the switch transistor SW in this embodiment is formed as part of a multilayer wiring structure above the top surface of the substrate 11. This increases the area of ​​the gate electrode of the amplifier transistor AMP in plan view ( FIG. 15B ), making it possible to reduce noise in the solid-state imaging device. Further details of the layout of the switch transistor SW will be described later.

[0133] Fig. 16 is a cross-sectional view showing the structure of the solid-state imaging device of the third embodiment. Fig. 16 corresponds to Fig. 4A. Fig. 16 shows the cross-sectional structure of the first floor of the solid-state imaging device of this embodiment.

[0134] 16, the solid-state imaging device of this embodiment includes, in addition to the components shown in FIG. 4A, a contact plug 31, a wiring layer 32, a transistor 33, a via plug 34, and a capacitor 35 in an interlayer insulating film 13. The transistor 33 is an example of a second transistor of the present disclosure. The capacitor 35 is an example of a holding unit of the present disclosure.

[0135] The contact plug 31 is formed on the floating diffusion region FD. The wiring layer 32 is formed on the contact plug 31. The wiring layer 32 is, for example, a Si layer. The transistor 33 includes a gate insulating film 33a and a gate electrode 33b formed in this order on the wiring layer 32. The transistor 33 is, for example, a switch transistor SW. The transistor 33 is formed above the upper surface (surface S1) of the substrate 11 as part of a multilayer wiring structure including the wiring layer 32. The gate electrode 33b is, for example, a Si layer or a metal layer. The source region and drain region of the transistor 33 are formed in the wiring layer 32, for example.

[0136] The via plug 34 is provided below the wiring layer 32. The capacitor 35 includes an n-type WBG layer 35a, an insulating film 35b, and an n-type semiconductor layer 35c, which are provided in this order below the via plug 34. The n-type WBG layer 35a is an n-type semiconductor layer formed from a WBG material. The n-type WBG layer 35a is an example of a first semiconductor layer of the present disclosure. The n-type WBG layer 35a of this embodiment has a band gap of 3.0 eV or more and is formed from a WBG material containing In, Ga, or Zn. The WBG material of this embodiment is, for example, IGZO containing In, Ga, Zn, and O. Meanwhile, the n-type semiconductor layer 35c is, for example, an n-type Si layer. The n-type semiconductor layer 35c is an example of a second semiconductor layer of the present disclosure.

[0137] The capacitor 35 is electrically connected to the transistor 33 through the via plug 34. Specifically, the n-type WBG layer 35a in the capacitor 35 is electrically connected to the transistor 33. The n-type WBG layer 35a functions as an electrode of the capacitor 35 on the transistor 33 side. The n-type semiconductor layer 35c functions as an electrode of the capacitor 35 on the opposite side to the transistor 33. The insulating film 35b functions as a dielectric film between the electrodes of the capacitor 35. Like the transistor 33, the capacitor 35 is provided above the upper surface of the substrate 11.

[0138] The capacitor 35 is, for example, the capacitor Ca shown in Fig. 14. In this embodiment, the charge generated in response to photoelectric conversion is converted into a voltage signal by the amplifier transistor AMP, and the voltage generated in response to this voltage signal is held by the capacitor Ca (and the capacitor Cb). As described above, it is desirable that the n-type WBG layer 35a has a band gap of 3.0 eV or more.

[0139] The wiring layer 32 may be a WBG layer to provide the transistor 33 with the same effect as the transistors 17 and 21. This WBG layer may have a band gap of 3.0 eV or more and may be formed of a WBG material containing In, Ga, or Zn. On the other hand, the switch transistor SW may be an atom switch.

[0140] FIG. 17 is a cross-sectional view showing the structure of a solid-state imaging device according to a modification of the third embodiment.

[0141] The solid-state imaging device of this modification has the structure shown in Fig. 17 instead of the structure shown in Fig. 16. The solid-state imaging device of this modification includes a substrate 11, a lens layer 12, an interlayer insulating film 13, etc., similar to the solid-state imaging devices shown in Fig. 3A (first embodiment) and Fig. 9A (second embodiment).

[0142] As shown in FIG. 17, the solid-state imaging device of this modified example has a two-story structure including a first floor indicated by reference character F1 and a second floor indicated by reference character F2.

[0143] The first floor includes a substrate 11, an interlayer insulating film 13, contact plugs 41, a wiring layer 42, via plugs 43, a wiring layer 44, via plugs 45, and metal pads 46. In Fig. 17, the interlayer insulating film 13 is formed on the lower surface (the surface S1 described above) of the substrate 11. The contact plugs 41, the wiring layer 42, the via plugs 43, the wiring layer 44, the via plugs 45, and the metal pads 46 are formed in this order in the interlayer insulating film 13 below the substrate 11, forming a multilayer wiring structure on the first floor.

[0144] The first floor further includes a plurality of transistors Tr1. Each transistor Tr1 includes a gate insulating film A1 and a gate electrode A2 formed in this order on the lower surface of the substrate 11. These transistors Tr1 include, for example, a transfer transistor TG, a reset transistor RST, a conversion efficiency switching transistor FDG, an amplification transistor AMP, an overflow gate transistor OFG, and the like.

[0145] The second floor includes a substrate 51, an interlayer insulating film 52, contact plugs 53, contact plugs 54, a wiring layer 55, via plugs 56, a wiring layer 57, via plugs 58, via plugs 61, via plugs 62, a wiring layer 63, via plugs 64, and a metal pad 65. In FIG. 17 , the interlayer insulating film 52 is formed on the upper surface of the substrate 51. The contact plugs 53, contact plugs 54, a wiring layer 55, via plugs 56, a wiring layer 57, via plugs 58, via plugs 61, via plugs 62, a wiring layer 63, via plugs 64, and a metal pad 65 are formed in this order in the interlayer insulating film 52 on the substrate 51, forming a multilayer wiring structure on the second floor. The upper surfaces of the interlayer insulating film 52 and the metal pad 65 are bonded to the lower surfaces of the interlayer insulating film 13 and the metal pad 46, respectively.

[0146] The second floor further includes a plurality of transistors Tr2. Each transistor Tr2 includes a gate insulating film B1 and a gate electrode B2, which are formed in this order on the upper surface of the substrate 51. These transistors Tr2 include, for example, a current source transistor PC, a subsequent current source transistor VB, switch transistors Sa and Sb, a VREG voltage transistor RB, a subsequent amplification transistor SF2, and a selection transistor SEL.

[0147] The second floor further includes a capacitor 35 and a capacitor 36. Like the capacitor 35 of the third embodiment, the capacitor 35 of this modification includes an n-type WBG layer 35a, an insulating film 35b, and an n-type semiconductor layer 35c, which are arranged in this order in the vertical direction. The capacitor 35 is, for example, the capacitor Ca shown in FIG. 14 , as described above. Similarly, the capacitor 36 includes an n-type WBG layer 36a, an insulating film 36b, and an n-type semiconductor layer 36c, which are arranged in this order in the vertical direction. The capacitor 36 is, for example, the capacitor Cb shown in FIG. 14 . The materials of the n-type WBG layer 36a, the insulating film 36b, and the n-type semiconductor layer 36c are the same as those of the n-type WBG layer 35a, the insulating film 35b, and the n-type semiconductor layer 35c, respectively.

[0148] The switch transistor SW (not shown) of this modification is formed using a multi-layer wiring structure on the first floor or a multi-layer wiring structure on the second floor. For example, the switch transistor SW of this modification is formed using a structure similar to that of the transistor 33 shown in FIG. 16. In this case, the wiring layer 32 (FIG. 16) is formed in the interlayer insulating film 13 or the interlayer insulating film 52 and is electrically connected to both of the n-type WBG layers 35 a and 36 a. In FIG. 17, via plugs 58 are provided on the lower surfaces of the n-type semiconductor layers 35 c and 36 c, and via plugs 62 are provided on the upper surfaces of the n-type WBG layers 35 a and 36 a.

[0149] FIG. 18 is a cross-sectional view showing the structure of a solid-state imaging device of a second comparative example of the third embodiment.

[0150] The solid-state imaging device of this comparative example has a structure similar to that of the solid-state imaging device of the modified example of the second embodiment ( FIG. 17 ). However, the capacitors Ca and Cb of this comparative example have an MIM (Metal Insulator Metal) structure. Therefore, both electrodes of the capacitor Ca of this comparative example and both electrodes of the capacitor Cb of this comparative example are formed of metal layers.

[0151] On the other hand, the capacitors Ca and Cb (capacitors 35 and 36) of the above-described modified example have electrodes (n-type WBG layers 35a and 36a) formed of a WBG material. As described above, the n-type WBG layers 35a and 36a preferably have a band gap of 3.0 eV or more.

[0152] As described above, the solid-state imaging device of this embodiment includes a capacitor Ca whose electrodes are formed of a WBG material, which is a semiconductor having a bandgap wider than that of Si. For example, the electrodes of the capacitor Ca of this embodiment are formed of a WBG material having a bandgap of 3.0 eV or more. The same applies to the capacitor Cb.

[0153] Fourth Embodiment 1) Cross-sectional Structure of Solid-State Imaging Device FIG. 19 is a cross-sectional view showing the structure of a solid-state imaging device according to a fourth embodiment.

[0154] Similar to the solid-state imaging device of the modified example of the third embodiment (FIG. 17), the solid-state imaging device of this embodiment has a two-story structure including a first floor indicated by reference symbol F1 and a second floor indicated by reference symbol F2. FIG. 19 shows three pixels 1 and a peripheral region R in the solid-state imaging device of this embodiment. The orientation of the solid-state imaging device shown in FIG. 19 is opposite to the orientation of the solid-state imaging device shown in FIG. 17.

[0155] The first floor of this embodiment includes a substrate 11, an interlayer insulating film 13, and the like. Each pixel 1 includes a photodiode PD and a transistor Tr1 on the first floor. The photodiode PD is formed in the substrate 11. The transistor Tr1 includes a gate insulating film A1 and a gate electrode A2 formed in this order on the upper surface of the substrate 11, and a source region and a drain region (not shown) formed in the substrate 11. The substrate 11 and the transistor Tr1 are examples of the first substrate and the first transistor, respectively, of the present disclosure. The first floor portion is also called a sensor chip.

[0156] The second floor of this embodiment includes a substrate 51, an interlayer insulating film 52, and the like. Each pixel 1 includes a transistor Tr2 on the second floor. The transistor Tr2 includes a gate insulating film B1 and a gate electrode B2 formed in this order on the upper surface of the substrate 51, and a source region and a drain region (not shown) formed within the substrate 51. The transistor Tr2 is an example of a second transistor of the present disclosure. The second floor is also called a logic chip.

[0157] The substrate 11 in this embodiment is, for example, a Si substrate. The interlayer insulating film 13 is formed on the substrate 11. The substrate 51 is disposed on the interlayer insulating film 13 and is disposed above the substrate 11 at a distance from the substrate 11. The substrate 51 in this embodiment includes a semiconductor substrate 51a, such as a Si substrate, and a WBG layer 51b formed on the upper surface of the semiconductor substrate 51a. The transistor Tr2 in this embodiment includes a gate insulating film B1 and a gate electrode B2 formed in this order on the upper surface of the WBG layer 51b, and the above-mentioned source region and drain region (not shown) formed in the WBG layer 51b. The semiconductor substrate 51a and the WBG layer 51b are examples of the second substrate and the first semiconductor layer, respectively, of the present disclosure.

[0158] In this embodiment, the second floor further includes a transistor Tr2 in the peripheral region R.

[0159] The solid-state imaging device of this embodiment further includes an insulating film 71 , a plurality of contact plugs 72 , a wiring layer 73 , a plurality of via plugs 74 , a wiring layer 75 , and a plurality of through plugs 76 .

[0160] The insulating film 71 is formed in the substrate 51 and penetrates the substrate 51 in the vertical direction. The contact plug 72, the wiring layer 73, the via plug 74, and the wiring layer 75 are formed in the interlayer insulating film 52, and the through plug 76 is formed in the interlayer insulating film 13, the insulating film 71, and the interlayer insulating film 52. In each pixel 1, the through plug 76 is formed on the substrate 11, the contact plug 72 is formed on the WBG layer 51b, and the wiring layer 73 is formed on the through plug 76 and the contact plug 72. In each pixel 1, the via plug 74 is formed on the wiring layer 73, and the wiring layer 75 is formed on the via plug 74. The same applies to the peripheral region R.

[0161] Here, the WBG layer 51b will be described in detail.

[0162] The WBG layer 51b is made of a WBG material, which is a semiconductor having a bandgap wider than that of Si. In this embodiment, the WBG layer 51b is made of a WBG material having a bandgap of 3.0 eV or more and containing In, Ga, or Zn. The WBG material is, for example, IGZO, which contains In, Ga, Zn, and O.

[0163] In this embodiment, the substrate 11 is, for example, a Si substrate. As a result, the photodiode PD is formed in the Si substrate, and the transistor Tr1 is formed on the upper surface of the Si substrate. However, forming a transistor on a Si substrate may cause a large leakage current from the transistor.

[0164] Therefore, the substrate 51 of this embodiment is formed by forming a WBG layer 51b on a semiconductor substrate 51a such as a Si substrate. Therefore, according to this embodiment, by forming the transistor Tr2 on the upper surface of the WBG layer 51b, it is possible to reduce the leakage current from the transistor Tr2. To effectively reduce the leakage current, the WBG layer 51b desirably has a band gap of 3.0 eV or more, as described above. Furthermore, it is more desirable to form a pixel transistor for which it is desirable to reduce the leakage current as the transistor Tr2 on the WBG layer 51b rather than forming it as the transistor Tr1 on the substrate 11.

[0165] As described above, the solid-state imaging device of this embodiment includes the substrate 11, such as a Si substrate, and the substrate 51 including the WBG layer 51b. This allows the photodiode PD to be formed within the substrate 11, and the transistor Tr2 with reduced leakage current to be formed on the substrate 51, which is separate from the substrate 11.

[0166] [First Modification] FIG. 20 is a cross-sectional view showing the structure of a solid-state imaging device according to a first modification of the fourth embodiment.

[0167] The solid-state imaging device of this modification has a three-story structure including a first floor indicated by reference symbol F1, a second floor indicated by reference symbol F2, and a third floor indicated by reference symbol F3. Fig. 20 shows four pixels 1 and a peripheral region R in the solid-state imaging device of this modification. In this modification, these pixels 1 are included in the first and second floors, and the peripheral region R is included in the third floor.

[0168] The structures of the first and second floors of this modification are almost the same as those of the fourth embodiment, except that the second floor of this modification has a plurality of metal pads 77 in the interlayer insulating film 52.

[0169] The third floor of this modification includes a substrate 81, an interlayer insulating film 82, a plurality of contact plugs 83, a wiring layer 84, a plurality of via plugs 85, a wiring layer 86, a plurality of metal pads 87, and a plurality of transistors Tr3. The substrate 81 is an example of a third substrate of the present disclosure. The transistor Tr3 is an example of a third transistor of the present disclosure.

[0170] The substrate 81 is a semiconductor substrate such as a Si substrate. The substrate 81 is disposed above the substrate 51 at a distance from the substrate 51. The interlayer insulating film 82 is provided on the lower surface of the substrate 81 and on the upper surface of the interlayer insulating film 52. Each transistor Tr3 includes a gate insulating film C1 and a gate electrode C2 formed in this order on the lower surface of the substrate 81, and a source region and a drain region formed in the substrate 81. The source region and the drain region are silicide layers S formed in the substrate 81.

[0171] Contact plugs 83, wiring layers 84, via plugs 85, wiring layers 86, and metal pads 87 are provided in the interlayer insulating film 82. The contact plugs 83 are provided below the silicide layer S, and the wiring layer 84 is provided below the contact plugs 83. The via plugs 85 are provided below the wiring layer 84, and the wiring layer 86 is provided below the via plugs 85. The metal pads 87 are provided on the metal pads 77, and electrically connect the second and third floors.

[0172] According to this modification, like the fourth embodiment, it is possible to reduce the leakage current from the transistor Tr2.

[0173] [Second Modification] FIG. 21 is a cross-sectional view showing the structure of a solid-state imaging device according to a second modification of the fourth embodiment.

[0174] The solid-state imaging device of this modification has a structure similar to that of the solid-state imaging device of the fourth embodiment shown in FIG. 19 . However, the substrate 51 of this modification is a WBG substrate 51c formed of a WBG material. In this modification, the WBG substrate 51c is formed of a WBG material having a band gap of 3.0 eV or more and containing In, Ga, or Zn. This WBG material is, for example, IGZO containing In, Ga, Zn, and O. The WBG substrate 51c is an example of the second substrate of the present disclosure and an example of the first semiconductor layer of the present disclosure.

[0175] According to this modification, by forming the transistor Tr2 on the upper surface of the WBG substrate 51c, it is possible to reduce the leakage current from the transistor Tr2. To effectively reduce the leakage current, the WBG substrate 51c desirably has a band gap of 3.0 eV or more, as described above. Furthermore, it is more desirable to form the pixel transistor, for which it is desirable to reduce the leakage current, as the transistor Tr2 on the WBG substrate 51c rather than forming it as the transistor Tr1 on the substrate 11.

[0176] According to this modification, like the fourth embodiment, it is possible to reduce the leakage current from the transistor Tr2.

[0177] [Third Modification] FIG. 22 is a cross-sectional view showing the structure of a solid-state imaging device according to a third modification of the fourth embodiment.

[0178] The solid-state imaging device of this modification has a structure similar to that of the solid-state imaging device of the first modification shown in Fig. 20. However, the substrate 51 of this modification is a WBG substrate 51c made of a WBG material. The details of the WBG substrate 51c of this modification are similar to those of the WBG substrate 51c of the second modification.

[0179] According to this modification, like the fourth embodiment, it is possible to reduce the leakage current from the transistor Tr2.

[0180] 2) Circuit Configuration of Solid-State Imaging Device FIG. 23 is a circuit diagram showing the configuration of a solid-state imaging device according to the fourth embodiment.

[0181] Each pixel 1 of this embodiment includes the above-described overflow gate transistor OFG, transistor FCG, and capacitor FC in addition to the components shown in FIG. 2 (first embodiment).

[0182] One of the source and drain of the overflow gate transistor OFG is electrically connected to the transfer transistor TG and the photodiode PD, and the other of the source and drain of the overflow gate transistor OFG is electrically connected to the transistor FCG and the capacitor FC. One of the source and drain of the transistor FCG is electrically connected to the overflow gate transistor OFG and the capacitor FC, and the other of the source and drain of the transistor FCG is electrically connected to the transfer transistor TG and the floating diffusion FD. One electrode of the capacitor FC is electrically connected to the overflow gate transistor OFG and the transistor FCG, and the other electrode of the capacitor FC is electrically connected to the power supply wiring.

[0183] 23 is formed on the upper surface of the WBG layer 51b (or the WBG substrate 51c; the same applies below). That is, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the transistor FCG are formed on the WBG layer 51b.

[0184] In this embodiment, pixel transistors that are not electrically connected to the photodiode PD are formed on the WBG layer 51b, which makes it possible to reduce the leakage current from these pixel transistors.

[0185] [Fourth Modification] FIG. 24 is a circuit diagram showing the configuration of a solid-state imaging device according to a fourth modification of the fourth embodiment.

[0186] Each pixel 1 of this modified example includes the components shown in Fig. 23 (fourth embodiment). In this modified example, pixel transistors surrounded by dashed lines in Fig. 24 are formed on the upper surface of the WBG layer 51b. These pixel transistors are the same as the pixel transistors surrounded by dashed lines in Fig. 23.

[0187] In this modification, one electrode of the capacitor FC is also formed by the WBG layer 51b. The capacitor FC is used to hold overflowed charges. According to this modification, by using a MOS capacitor for the capacitor FC, it is possible to reduce leakage current from the capacitor FC and improve the image quality of the solid-state imaging device. Furthermore, according to this modification, by using a MOS capacitor for the capacitor FC and forming the electrode of the capacitor FC on the substrate 51 instead of the substrate 11, it is possible to reduce visible light reaching the capacitor FC and suppress PLS.

[0188] [Fifth Modification] FIG. 25 is a circuit diagram showing the configuration of a solid-state imaging device according to a fifth modification of the fourth embodiment.

[0189] The two pixels 1 shown in Fig. 25 have the same configuration as the two pixels 1 shown in Fig. 8 (second embodiment). In this modification, the pixel transistors surrounded by dashed lines in Fig. 25 are formed on the upper surface of the WBG layer 51b. That is, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are formed on the WBG layer 51b. This makes it possible to reduce the leakage current from these pixel transistors.

[0190] [Sixth Modification] FIG. 26 is a circuit diagram showing the configuration of a solid-state imaging device according to a sixth modification of the fourth embodiment.

[0191] The two pixels 1 shown in Fig. 26 also have the same configuration as the two pixels 1 shown in Fig. 8 (second embodiment). In this modification, the pixel transistors surrounded by dashed lines in Fig. 26 are formed on the upper surface of the WBG layer 51b. That is, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the transfer transistor TG are formed on the WBG layer 51b. In addition, in this modification, the pixel memory MEM is formed in the WBG layer 51b.

[0192] In each pixel 1 of this modified example, the pixel memory MEM and the transfer transistors TG and TX electrically connected to the pixel memory MEM are formed using the WBG layer 51b. This makes it possible to reduce leakage current from the pixel memory MEM and the transfer transistors TG and TX. Furthermore, according to this modified example, by forming the pixel memory MEM in the substrate 51 rather than in the substrate 11, it is possible to reduce visible light reaching the pixel memory MEM and suppress PLS. Furthermore, according to this modified example, by forming the pixel memory MEM in the substrate 51 rather than in the substrate 11, it is possible to increase the size of the photodiode PD in the substrate 11.

[0193] [Seventh Modification] FIG. 27 is a circuit diagram showing the configuration of a solid-state imaging device according to a seventh modification of the fourth embodiment.

[0194] The pixel 1 shown in Fig. 27 has the same circuit configuration as the pixel 1 shown in Fig. 14 (third embodiment). However, the pixel 1 shown in Fig. 27 does not include an overflow gate transistor OFG. The dashed line (straight line) shown in Fig. 27 indicates the boundary between the second and third floors shown in Fig. 20 (or Fig. 22).

[0195] 27 is formed on the upper surface of the WBG layer 51b. That is, the reset transistor RST is formed on the WBG layer 51b. This makes it possible to reduce the leakage current from the reset transistor RST.

[0196] [Eighth Modification] FIG. 28 is a circuit diagram showing the configuration of a solid-state imaging device according to an eighth modification of the fourth embodiment.

[0197] The pixel 1 shown in Fig. 28 has the same circuit configuration as the pixel 1 shown in Fig. 27 (seventh modification). In this modification, the pixel transistors surrounded by the dashed line in Fig. 28 are formed on the upper surface of the WBG layer 51b. That is, the reset transistor RST and the conversion efficiency switching transistor FDG are formed on the WBG layer 51b. This makes it possible to reduce the leakage current from these pixel transistors.

[0198] [Ninth Modification] FIG. 29 is a circuit diagram showing the configuration of a solid-state imaging device according to a ninth modification of the fourth embodiment.

[0199] The pixel 1 shown in Fig. 29 has the same circuit configuration as the pixel 1 shown in Fig. 27 (seventh modification). In this modification, the pixel transistors surrounded by the dashed line in Fig. 29 are formed on the upper surface of the WBG layer 51b. That is, the reset transistor RST, the conversion efficiency switching transistor FDG, and the amplification transistor AMP are formed on the WBG layer 51b. This makes it possible to reduce the leakage current from these pixel transistors.

[0200] [Tenth Modification] FIG. 30 is a circuit diagram showing the configuration of a solid-state imaging device according to a tenth modification of the fourth embodiment.

[0201] The pixel 1 shown in FIG. 30 has a circuit configuration similar to that of the pixel 1 shown in FIG. 27 (seventh modification). In this modification, the pixel transistors enclosed by the dashed line in FIG. 30 are formed on the upper surface of the WBG layer 51b. That is, the reset transistor RST, the conversion efficiency switching transistor FDG, the amplification transistor AMP, the current source transistor PC, the subsequent current source transistor VB, the switch transistor Sa, and the switch transistor Sb are formed on the WBG layer 51b. This makes it possible to reduce leakage current from these pixel transistors. Furthermore, it is possible to suppress loss of the holding voltage for VDGDS, thereby improving the image quality of the solid-state imaging device.

[0202] [Eleventh Modification] FIG. 31 is a circuit diagram showing the configuration of a solid-state imaging device according to an eleventh modification of the fourth embodiment.

[0203] The pixel 1 shown in Fig. 31 has a circuit configuration similar to that of the pixel 1 shown in Fig. 27 (seventh modification). In this modification, the pixel transistors surrounded by dashed lines in Fig. 31 are formed on the upper surface of the WBG layer 51b. That is, the reset transistor RST, the conversion efficiency switching transistor FDG, the amplification transistor AMP, the current source transistor PC, the subsequent current source transistor VB, the switch transistor Sa, and the switch transistor Sb are formed on the WBG layer 51b. This makes it possible to reduce the leakage current from these pixel transistors.

[0204] Furthermore, according to the seventh to eleventh modifications, by reducing the number of pixel transistors formed on the upper surface of the substrate 11, it is possible to increase the size of the photodiode PD in the substrate 11.

[0205] As described above, the solid-state imaging device of this embodiment includes a transistor Tr2 on a WBG layer 51b formed of a WBG material, which is a semiconductor having a bandgap wider than that of Si. For example, the WBG layer 51b of this embodiment is formed of a WBG material having a bandgap of 3.0 eV or greater. Therefore, this embodiment makes it possible to form a suitable transistor Tr2 capable of suppressing leakage current.

[0206] Fifth Embodiment FIG. 32 is a cross-sectional view showing the structure of a solid-state imaging device according to a fifth embodiment.

[0207] The solid-state imaging device of this embodiment has a structure similar to that of the solid-state imaging device of the fourth embodiment ( FIG. 19 ). However, the substrate 51 of this embodiment includes a WBG layer 51b provided on the lower surface of the semiconductor substrate 51a. The interlayer insulating film 52 of this embodiment is provided on the lower surface of the semiconductor substrate 51a and on the upper surface of the interlayer insulating film 13. Each transistor Tr2 of this embodiment includes a gate insulating film B1 and a gate electrode B2 formed in this order on the lower surface of the WBG layer 51b, and source and drain regions (not shown) formed in the WBG layer 51b. This makes it possible to reduce leakage current from the transistor Tr2. The solid-state imaging device of this embodiment does not include an insulating film 71 ( FIG. 19 ) in the substrate 51.

[0208] The substrate 51 of this embodiment may include the above-described WBG substrate 51c instead of including the semiconductor substrate 51a and the WBG layer 51b.

[0209] The solid-state imaging device of this embodiment also includes, as components of the multilayer wiring structure, a plurality of contact plugs 91, wiring layers 92 and 93, and a plurality of metal pads 94 provided in the interlayer insulating film 13, and a plurality of contact plugs 95, wiring layers 96, and metal pads 97 provided in the interlayer insulating film 52. The metal pad 97 is provided on the metal pad 94, and electrically connects the first floor and the second floor.

[0210] 33A to 33C are cross-sectional views showing a method for manufacturing the solid-state imaging device of the fifth embodiment.

[0211] First, a photodiode PD is formed in a substrate 11, and then a transistor Tr1, an interlayer insulating film 13, a contact plug 91, a wiring layer 92, a wiring layer 93, and a metal pad 94 are formed on the substrate 11 (FIG. 33A). Also, a substrate 51 including a semiconductor substrate 51a and a WBG layer 51b is prepared, and then a transistor Tr2, an interlayer insulating film 52, a contact plug 95, a wiring layer 96, and a metal pad 97 are formed on the substrate 51 (FIG. 33A).

[0212] Next, the substrate 11 and the substrate 51 are bonded together so that the interlayer insulating film 13 and the interlayer insulating film 52 are bonded together and the metal pad 94 and the metal pad 97 are bonded together (FIG. 33B). As a result, the second floor is placed on top of the first floor.

[0213] Thereafter, the substrate 11 is thinned, and then the substrates 11 and 51 are divided into a plurality of chips by dicing, thereby completing the manufacture of the solid-state imaging device of this embodiment.

[0214] According to this embodiment, similarly to the fourth embodiment, it is possible to form a suitable transistor Tr2 capable of suppressing leakage current.

[0215] Sixth Embodiment FIG. 34 is a cross-sectional view showing the structure of a solid-state imaging device according to a sixth embodiment.

[0216] The solid-state imaging device of this embodiment has a structure similar to that of the solid-state imaging device of the fourth embodiment ( FIG. 19 ). However, the second floor of this embodiment includes a WBG layer 51b obtained by removing the semiconductor substrate 51a from a substrate 51 including the semiconductor substrate 51a and the WBG layer 51b. Therefore, the solid-state imaging device of this embodiment does not include the semiconductor substrate 51a.

[0217] 35 to 37 are cross-sectional views showing a method for manufacturing the solid-state imaging device of the sixth embodiment.

[0218] First, a photodiode PD is formed in a substrate 11, and then a transistor Tr1 and an interlayer insulating film 13 are formed on the substrate 11 (FIG. 35A). A substrate 51 including a semiconductor substrate 51a and a WBG layer 51b is prepared, an insulating film 71 is formed in the substrate 51, and then a transistor Tr2 and an insulating film 52a (part of the interlayer insulating film 52) are formed on the substrate 51 (FIG. 35A). The insulating film 71 is formed in the WBG layer 51b so as to penetrate the WBG layer 51b.

[0219] Next, the substrate 51 is bonded to the support substrate 98 so that the interlayer insulating film 52 contacts the support substrate 98 (FIG. 35B). Next, the substrate 51 is thinned to remove the semiconductor substrate 51a from the substrate 51 (FIG. 36A). Next, the support substrate 98 is bonded to the substrate 11 so that the interlayer insulating film 13 contacts the WBG layer 51b and the insulating film 71 (FIG. 35B). Next, the support substrate 98 is removed (FIG. 36A). As a result, the second floor is placed above the first floor.

[0220] Next, a contact plug 72 is formed in the insulating film 52a, and a through plug 76 is formed in the interlayer insulating film 13, the insulating film 71, and the insulating film 52a (FIG. 36B). Next, an insulating film 52b (part of the interlayer insulating film 52), a wiring layer 73, a via plug 74, and a wiring layer 75 are formed on the insulating film 52a (FIG. 36B).

[0221] Thereafter, the substrate 11 is thinned and then divided into a plurality of chips by dicing, thereby completing the manufacture of the solid-state imaging device of this embodiment.

[0222] 38 and 39 are cross-sectional views showing a method for manufacturing a solid-state imaging device according to a modification of the sixth embodiment.

[0223] First, a photodiode PD is formed in a substrate 11, and a transistor Tr1 and an interlayer insulating film 13 are formed on the substrate 11 (FIG. 38A). Next, a WBG layer 51b is formed on the interlayer insulating film 13 (FIG. 38B). In this manner, the WBG layer 51b of this modification is formed without using a semiconductor substrate 51a.

[0224] In this case, if the WBG layer 51b is formed at a high temperature, there is a risk that the multilayer wiring structure (not shown) in the interlayer insulating film 13 may be damaged. Therefore, it is desirable that the WBG layer 51b in this modification be formed from a WBG material that can be formed at a low temperature (for example, 400° C. or less). This makes it possible to arrange the multilayer wiring structure in the interlayer insulating film 13 in this modification.

[0225] Next, an insulating film 71 is formed in the WBG layer 51b, and a transistor Tr2 is formed on the WBG layer 51b (FIG. 39A). Next, an interlayer insulating film 52, contact plugs 72, a wiring layer 73, via plugs 74, a wiring layer 75, and through plugs 76 are formed on the WBG layer 51b and in other locations (FIG. 39B).

[0226] Thereafter, the substrate 11 is thinned and then divided into a plurality of chips by dicing, thereby completing the manufacture of the solid-state imaging device of this modified example.

[0227] According to this embodiment, similarly to the fourth and fifth embodiments, it is possible to form a suitable transistor Tr2 capable of suppressing leakage current.

[0228] Seventh Embodiment FIG. 40 is a cross-sectional view showing the structure of a solid-state imaging device according to the seventh embodiment.

[0229] The solid-state imaging device of this embodiment has a structure similar to that of the solid-state imaging device ( FIG. 39B ) of the modified example of Embodiment 6. However, each transistor Tr2 of this embodiment includes a gate insulating film B1 and a gate electrode B2 formed in this order on the lower surface of the WBG layer 51 b, and a source region and a drain region (not shown) formed in the WBG layer 51 b.

[0230] The solid-state imaging device of this embodiment also includes an insulating film 71, a plurality of contact plugs 72, a wiring layer 73, a wiring layer 75, and a plurality of through plugs 76. However, the shapes and arrangements of these components in this embodiment are different from those in the modified example of the sixth embodiment.

[0231] The solid-state imaging device of this embodiment further includes a plurality of contact plugs 99 in the interlayer insulating film 13. In each pixel 1, the contact plugs 99 are provided on the upper surface of the substrate 11 and on the lower surface of the WBG layer 51b.

[0232] 41 and 42 are cross-sectional views showing a method for manufacturing the solid-state imaging device of the seventh embodiment.

[0233] First, a photodiode PD is formed in the substrate 11, and then a transistor Tr1, an interlayer insulating film 13, a contact plug 72, a wiring layer 73, a contact plug 99, and a gate insulating film B1 and a gate electrode B2 of the transistor Tr2 are formed on the substrate 11 (FIG. 41A). Next, a WBG layer 51b is formed on the interlayer insulating film 13 (FIG. 42B). In this way, the WBG layer 51b of this embodiment is formed without using a semiconductor substrate 51a.

[0234] In this case, if the WBG layer 51b is formed at a high temperature, the multilayer wiring structure (such as the wiring layer 73) in the interlayer insulating film 13 may be damaged. Therefore, it is desirable to form the WBG layer 51b of this embodiment from a WBG material that can be formed at a low temperature (for example, 400° C. or less). This makes it possible to arrange the multilayer wiring structure in the interlayer insulating film 13 of this embodiment.

[0235] Next, an insulating film 71 and a source region and a drain region (not shown) of the transistor Tr2 are formed in the WBG layer 51b (FIG. 42A). Next, an interlayer insulating film 52, a wiring layer 75, and a through plug 76 are formed on the WBG layer 51b and in other locations (FIG. 42B).

[0236] Thereafter, the substrate 11 is thinned and then divided into a plurality of chips by dicing, thereby completing the manufacture of the solid-state imaging device of this embodiment.

[0237] According to this embodiment, similarly to the fourth to sixth embodiments, it is possible to form a suitable transistor Tr2 capable of suppressing leakage current.

[0238] Eighth Embodiment FIG. 43 is a cross-sectional view showing the structure of a solid-state imaging device according to an eighth embodiment.

[0239] The solid-state imaging device of this embodiment has a structure similar to that of the solid-state imaging device of the sixth embodiment ( FIG. 34 ). However, like the solid-state imaging device of the first modified example of the fourth embodiment ( FIG. 20 ), the solid-state imaging device of this embodiment further includes a plurality of metal pads 77, a substrate 81, an interlayer insulating film 82, a plurality of contact plugs 83, a wiring layer 84, a plurality of via plugs 85, a wiring layer 86, a plurality of metal pads 87, and a plurality of transistors Tr3. Therefore, the solid-state imaging device of this embodiment has a three-story structure including a first floor indicated by symbol F1, a second floor indicated by symbol F2, and a third floor indicated by symbol F3.

[0240] FIG. 44 is a cross-sectional view showing the structure of a solid-state imaging device according to a modification of the eighth embodiment.

[0241] The solid-state imaging device of this modification has a structure similar to that of the solid-state imaging device of the seventh embodiment ( FIG. 40 ). However, like the solid-state imaging device of the first modification of the fourth embodiment ( FIG. 20 ), the solid-state imaging device of this modification further includes a plurality of metal pads 77, a substrate 81, an interlayer insulating film 82, a plurality of contact plugs 83, a wiring layer 84, a plurality of via plugs 85, a wiring layer 86, a plurality of metal pads 87, and a plurality of transistors Tr3. Therefore, the solid-state imaging device of this modification has a three-story structure including a first floor indicated by symbol F1, a second floor indicated by symbol F2, and a third floor indicated by symbol F3.

[0242] According to this embodiment, similarly to the fourth to seventh embodiments, it is possible to form a suitable transistor Tr2 capable of suppressing leakage current.

[0243] 45 is a block diagram showing an example of the configuration of an electronic device. The electronic device shown in FIG.

[0244] The camera 100 includes an optical unit 101 including a lens group and the like, an imaging device 102 which is a solid-state imaging device according to any one of the first to eighth embodiments, a DSP (Digital Signal Processor) circuit 103 which is a camera signal processing circuit, a frame memory 104, a display unit 105, a recording unit 106, an operation unit 107, and a power supply unit 108. The DSP circuit 103, the frame memory 104, the display unit 105, the recording unit 106, the operation unit 107, and the power supply unit 108 are connected to one another via a bus line 109.

[0245] The optical unit 101 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 102. The imaging device 102 converts the amount of incident light formed on the imaging surface by the optical unit 101 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0246] The DSP circuit 103 performs signal processing on the pixel signals output by the imaging device 102. The frame memory 104 is a memory for storing one frame of a moving image or still image captured by the imaging device 102.

[0247] The display unit 105 includes a panel display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 102. The recording unit 106 records the moving images or still images captured by the imaging device 102 on a recording medium such as a hard disk or semiconductor memory.

[0248] The operation unit 107, under the operation of the user, issues operation commands for various functions of the camera 100. The power supply unit 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display unit 105, recording unit 106, and operation unit 107 as operating power sources.

[0249] By using the solid-state imaging device according to any one of the first to eighth embodiments as the imaging device 102, it is possible to expect to obtain a good image.

[0250] The solid-state imaging device can be applied to various other products, for example, the solid-state imaging device may be mounted on various moving objects such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0251] 46 is a block diagram showing an example of the configuration of a mobile object control system. The mobile object control system shown in FIG. 46 is a vehicle control system 200.

[0252] The vehicle control system 200 includes a plurality of electronic control units connected via a communication network 201. In the example shown in Fig. 46, the vehicle control system 200 includes a drive system control unit 210, a body system control unit 220, an outside-vehicle information detection unit 230, an inside-vehicle information detection unit 240, and an integrated control unit 250. Fig. 46 further shows, as components of the integrated control unit 250, a microcomputer 251, an audio / video output unit 252, and an in-vehicle network I / F (Interface) 253.

[0253] The drivetrain control unit 210 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 210 functions as a control device for a drive force generating device such as an internal combustion engine or a drive motor that generates drive force for the vehicle, a drive force transmission mechanism that transmits drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, a braking device that generates braking force for the vehicle, etc.

[0254] Body system control unit 220 controls the operation of various devices equipped in the vehicle body in accordance with various programs. For example, body system control unit 220 functions as a control device for a smart key system, a keyless entry system, a power window device, various lamps (e.g., head lamps, backup lamps, brake lamps, blinkers, fog lamps), etc. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to body system control unit 220. Body system control unit 220 receives input of such radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0255] The outside-vehicle information detection unit 230 detects information outside the vehicle equipped with the vehicle control system 200. For example, an imaging unit 231 is connected to the outside-vehicle information detection unit 230. The outside-vehicle information detection unit 230 causes the imaging unit 231 to capture images outside the vehicle and receives the captured images from the imaging unit 231. The outside-vehicle information detection unit 230 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0256] The imaging unit 231 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 231 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 231 may be visible light or invisible light such as infrared light. The imaging unit 231 includes a solid-state imaging device according to any one of the first to eighth embodiments.

[0257] The in-vehicle information detection unit 240 detects information about the inside of a vehicle equipped with the vehicle control system 200. A driver state detection unit 241 that detects the state of the driver is connected to the in-vehicle information detection unit 240, for example. For example, the driver state detection unit 241 includes a camera that captures an image of the driver, and the in-vehicle information detection unit 240 may calculate the degree of fatigue or concentration of the driver or determine whether the driver is dozing off based on the detection information input from the driver state detection unit 241. This camera may include the solid-state imaging device of any of the first to eighth embodiments, and may be, for example, the camera 100 shown in FIG. 45 .

[0258] The microcomputer 251 can calculate control target values ​​for the driving force generation device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside information detection unit 230 or the inside information detection unit 240, and output control commands to the drivetrain control unit 210. For example, the microcomputer 251 can perform cooperative control aimed at realizing functions of an Advanced Driver Assistance System (ADAS), such as vehicle collision avoidance, impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, collision warning, and lane departure warning.

[0259] In addition, the microcomputer 251 can perform cooperative control for purposes such as autonomous driving, in which the vehicle travels autonomously without the driver's operation, by controlling the driving force generating device, steering mechanism, or braking device based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 230 or the inside vehicle information detection unit 240.

[0260] Furthermore, the microcomputer 251 can output a control command to the body system control unit 220 based on the information about the outside of the vehicle acquired by the outside information detection unit 230. For example, the microcomputer 251 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 230, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0261] The audio / video output unit 252 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 46, such output devices include an audio speaker 261, a display unit 262, and an instrument panel 263. The display unit 262 may include, for example, an on-board display or a head-up display.

[0262] FIG. 47 is a plan view showing a specific example of the setting position of the imaging unit 231 in FIG.

[0263] 47 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 300.

[0264] The imaging unit 301 provided on the front nose mainly acquires images of the front of the vehicle 300. The imaging unit 302 provided on the left side mirror and the imaging unit 303 provided on the right side mirror mainly acquire images of the sides of the vehicle 300. The imaging unit 304 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 300. The imaging unit 305 provided on the top of the windshield inside the vehicle mainly acquires images of the front of the vehicle 300. The imaging unit 305 is used to detect, for example, leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0265] FIG. 47 shows an example of the imaging ranges of imaging units 301, 302, 303, and 304 (hereinafter referred to as "imaging units 301 to 304"). Imaging range 311 indicates the imaging range of imaging unit 301 provided on the front nose. Imaging range 312 indicates the imaging range of imaging unit 302 provided on the left side mirror. Imaging range 313 indicates the imaging range of imaging unit 303 provided on the right side mirror. Imaging range 314 indicates the imaging range of imaging unit 304 provided on the rear bumper or back door. For example, by overlaying the image data captured by imaging units 301 to 304, an overhead image of vehicle 300 viewed from above can be obtained. Hereinafter, imaging ranges 311, 312, 313, and 314 will be referred to as "imaging ranges 311 to 314."

[0266] At least one of the image capturing units 301 to 304 may have a function of acquiring distance information. For example, at least one of the image capturing units 301 to 304 may be a stereo camera including multiple image capturing devices, or may be an image capturing device having pixels for detecting a phase difference.

[0267] For example, the microcomputer 251 (FIG. 46) calculates the distance to each three-dimensional object within the imaging ranges 311-314 and the change in this distance over time (relative speed with respect to the vehicle 300) based on the distance information obtained from the imaging units 301-304. Based on these calculation results, the microcomputer 251 can extract, as a preceding vehicle, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 300 and traveling in approximately the same direction as the vehicle 300 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 251 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle and perform automatic braking control (including adaptive cruise control), automatic acceleration control (including adaptive cruise control), and the like. In this way, according to this example, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without driver operation.

[0268] For example, based on the distance information obtained from the imaging units 301 to 304, the microcomputer 251 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and can use the data for automatic obstacle avoidance. For example, the microcomputer 251 distinguishes obstacles around the vehicle 300 into obstacles that are visible to the driver of the vehicle 300 and obstacles that are difficult to see. The microcomputer 251 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and a collision is possible, the microcomputer 251 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 261 or the display unit 262, or by performing forced deceleration or avoidance steering via the drivetrain control unit 210.

[0269] At least one of the image capturing units 301-304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 301-304. Such pedestrian recognition is performed, for example, by extracting feature points in the images captured by the image capturing units 301-304 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 251 determines that a pedestrian is present in the images captured by the image capturing units 301-304 and recognizes the pedestrian, the audio / image output unit 252 controls the display unit 262 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 252 may also control the display unit 262 to display an icon or the like representing the pedestrian in a desired position.

[0270] FIG. 48 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0271] 48 shows a state in which an operator (doctor) 531 is performing surgery on a patient 532 on a patient bed 533 using an endoscopic surgery system 400. As shown in the figure, the endoscopic surgery system 400 is composed of an endoscope 500, other surgical tools 510 such as an insufflation tube 511 and an energy treatment tool 512, a support arm device 520 that supports the endoscope 500, and a cart 600 on which various devices for endoscopic surgery are mounted.

[0272] The endoscope 500 is composed of a lens barrel 501, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 532, and a camera head 502 connected to the base end of the lens barrel 501. In the example shown in the figure, the endoscope 500 is configured as a so-called rigid lens barrel having a rigid lens barrel 501, but the endoscope 500 may also be configured as a so-called flexible lens barrel having a flexible lens barrel.

[0273] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 501. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 501, and is irradiated via the objective lens toward an observation target inside the body cavity of the patient 532. The endoscope 500 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0274] An optical system and an image sensor are provided inside the camera head 502, and light reflected from an object to be observed (observation light) is collected by the optical system onto the image sensor. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 601 as RAW data.

[0275] The CCU 601 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 500 and the display device 602. Furthermore, the CCU 601 receives an image signal from the camera head 502 and performs various types of image processing on the image signal, such as development processing (demosaic processing), for displaying an image based on the image signal.

[0276] Under the control of the CCU 601 , the display device 602 displays an image based on the image signal that has been subjected to image processing by the CCU 601 .

[0277] The light source device 603 is configured from a light source such as an LED (Light Emitting Diode), and supplies the endoscope 500 with irradiation light when photographing an operation site or the like.

[0278] The input device 604 is an input interface for the endoscopic surgery system 11000. The user can input various information and instructions to the endoscopic surgery system 400 via the input device 604. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 500.

[0279] The treatment tool control device 605 controls the driving of the energy treatment tool 512 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 606 sends gas into the body cavity of the patient 532 via the insufflation tube 511 to ensure a clear field of view for the endoscope 500 and a working space for the surgeon. The recorder 607 is a device capable of recording various types of information related to the surgery. The printer 608 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0280] The light source device 603, which supplies illumination light to the endoscope 500 when photographing the surgical site, can be configured from a white light source formed, for example, by an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 603 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 502 in synchronization with the irradiation timing. This method allows color images to be obtained without providing a color filter to the image sensor.

[0281] Furthermore, the light source device 603 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 502 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0282] The light source device 603 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 603 may be configured to supply narrow band light and / or excitation light corresponding to such special light observation.

[0283] FIG. 49 is a block diagram showing an example of the functional configuration of the camera head 502 and the CCU 601 shown in FIG.

[0284] The camera head 502 has a lens unit 701, an imaging unit 702, a drive unit 703, a communication unit 704, and a camera head control unit 705. The CCU 601 has a communication unit 711, an image processing unit 712, and a control unit 713. The camera head 502 and the CCU 601 are connected to each other via a transmission cable 700 so as to be able to communicate with each other.

[0285] The lens unit 701 is an optical system provided at the connection portion with the lens barrel 501. Observation light taken in from the tip of the lens barrel 501 is guided to the camera head 502 and enters the lens unit 701. The lens unit 701 is configured by combining multiple lenses including a zoom lens and a focus lens.

[0286] The imaging unit 702 is composed of an imaging element. The imaging element constituting the imaging unit 702 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 702 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and these may be combined to obtain a color image. Alternatively, the imaging unit 702 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 531 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 702 is composed of a multi-chip type, multiple lens units 701 may be provided corresponding to each imaging element. The imaging unit 702 may be, for example, a solid-state imaging device according to any of the first to eighth embodiments.

[0287] Furthermore, the imaging unit 702 does not necessarily have to be provided in the camera head 502. For example, the imaging unit 702 may be provided inside the lens barrel 501, immediately after the objective lens.

[0288] The driving unit 703 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera head control unit 705. This allows the magnification and focus of the image captured by the imaging unit 702 to be adjusted appropriately.

[0289] The communication unit 704 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 601. The communication unit 704 transmits the image signal obtained from the imaging unit 702 to the CCU 601 via the transmission cable 700 as RAW data.

[0290] Furthermore, the communication unit 704 receives a control signal for controlling the driving of the camera head 502 from the CCU 601 and supplies the control signal to the camera head control unit 705. The control signal includes information relating to the image capturing conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of capturing an image, and / or information specifying the magnification and focus of the captured image.

[0291] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 713 of the CCU 601 based on the acquired image signal. In the latter case, the endoscope 500 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0292] The camera head control unit 705 controls the driving of the camera head 502 based on a control signal received from the CCU 601 via the communication unit 704 .

[0293] The communication unit 711 is configured by a communication device for transmitting and receiving various information to and from the camera head 502. The communication unit 711 receives an image signal transmitted from the camera head 502 via the transmission cable 700.

[0294] Furthermore, the communication unit 711 transmits to the camera head 502 a control signal for controlling the driving of the camera head 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0295] The image processing unit 712 performs various types of image processing on the image signal, which is RAW data, sent from the camera head 502 .

[0296] The control unit 713 performs various controls related to the imaging of the surgical site, etc. by the endoscope 500 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 713 generates a control signal for controlling the driving of the camera head 502.

[0297] Furthermore, the control unit 713 causes the display device 602 to display the captured image showing the surgical site, etc., based on the image signal subjected to image processing by the image processing unit 712. At this time, the control unit 713 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 713 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated during use of the energy treatment tool 512, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 602, the control unit 713 may use the recognition results to superimpose various surgical support information on the image of the surgical site. Superimposing the surgical support information and presenting it to the surgeon 531 reduces the burden on the surgeon 531 and enables the surgeon 531 to proceed with the surgery reliably.

[0298] The transmission cable 700 connecting the camera head 502 and the CCU 601 is an electric signal cable for communication of electric signals, an optical fiber for optical communication, or a composite cable of these.

[0299] In the illustrated example, communication is performed by wire using the transmission cable 700, but communication between the camera head 502 and the CCU 601 may also be performed wirelessly.

[0300] Although the embodiments of the present disclosure have been described above, these embodiments may be implemented with various modifications within the scope of the gist of the present disclosure. For example, two or more embodiments may be implemented in combination.

[0301] The present disclosure may also be configured as follows.

[0302] (1) A solid-state imaging device comprising: a first substrate; a photoelectric conversion unit provided within the first substrate and performing photoelectric conversion; and a holding unit that holds an electric charge or a voltage generated in response to the photoelectric conversion, wherein the holding unit includes a first semiconductor layer formed of a first semiconductor having a band gap wider than the band gap of Si (silicon), and the first semiconductor has the band gap of 3.0 eV or more.

[0303] (2) The solid-state imaging device according to (1), wherein the first semiconductor includes In (indium), Ga (gallium), or Zn (zinc).

[0304] (3) The solid-state imaging device according to (1), wherein the holding portion includes the first semiconductor layer provided in the first substrate and is a floating diffusion portion that holds the electric charges.

[0305] (4) The solid-state imaging device according to (1), wherein the holding unit includes the first semiconductor layer provided in the first substrate and is a pixel memory that holds the electric charges.

[0306] (5) The solid-state imaging device according to (1), wherein the first semiconductor layer includes both an n-type semiconductor layer and a p-type semiconductor layer.

[0307] (6) The solid-state imaging device according to (1), further comprising: a first transistor provided on the first substrate; and the first semiconductor layer is provided in the first substrate and functions as a source region or a drain region of the first transistor.

[0308] (7) The solid-state imaging device according to (6), wherein the first transistor is a transfer transistor that transfers the electric charges.

[0309] (8) The solid-state imaging device according to (1), wherein the holding unit is a capacitor that includes the first semiconductor layer provided above the first substrate and holds the voltage.

[0310] (9) The solid-state imaging device according to (8), further comprising: a second transistor electrically connected to the capacitor.

[0311] (10) The solid-state imaging device according to (9), wherein the second transistor is a switch transistor that functions as a switch that electrically connects the capacitor and the amplification transistor.

[0312] (11) The solid-state imaging device according to (10), wherein the capacitor includes a first electrode including the first semiconductor layer and a second electrode including a second semiconductor layer different from the first semiconductor layer, and the second transistor is electrically connected to the first semiconductor layer.

[0313] (12) A solid-state imaging device comprising: a first substrate; a photoelectric conversion unit provided within the first substrate and performing photoelectric conversion; a first transistor provided on an upper surface of the first substrate; a first semiconductor layer provided above and spaced apart from the first substrate, the first semiconductor layer having a band gap wider than the band gap of Si (silicon); and a second transistor provided on an upper surface or a lower surface of the first semiconductor layer.

[0314] (13) The solid-state imaging device according to (12), wherein the first semiconductor has the band gap of 3.0 eV or more.

[0315] (14) The solid-state imaging device according to (12), wherein the first semiconductor includes In (indium), Ga (gallium), or Zn (zinc).

[0316] (15) The solid-state imaging device according to (12), wherein the first semiconductor layer is provided on an upper surface or a lower surface of a second substrate disposed above the first substrate.

[0317] (16) The solid-state imaging device according to (15), further including: a third substrate disposed above the second substrate; and a third transistor provided on a lower surface of the third substrate.

[0318] (17) The solid-state imaging device according to (12), wherein the first semiconductor layer is a second substrate disposed above the first substrate and formed of the first semiconductor.

[0319] (18) The solid-state imaging device according to (17), further including: a third substrate disposed above the second substrate; and a third transistor provided on a lower surface of the third substrate.

[0320] (19) The solid-state imaging device according to (12), further comprising: a holding section that includes the first semiconductor layer and holds a charge or a voltage generated in response to the photoelectric conversion.

[0321] (20) The solid-state imaging device according to (19), wherein the holding unit is a pixel memory that holds the charge or a capacitor that holds the voltage.

[0322] 1: pixel, 2: pixel array, 3: control circuit, 4: vertical drive circuit, 5: column signal processing circuit, 6: horizontal drive circuit, 7: output circuit, 8: vertical signal line, 9: horizontal signal line, 11: substrate, 11a: p-type semiconductor region, 11b: n-type semiconductor region, 11c: p-type semiconductor region, 11d: n-type WBG layer, 11e: p-type WBG layer, 11f: n-type WBG layer, 11g: p-type WBG layer, 12: lens layer, 13: interlayer insulating film, 14: wiring layer, 15: wiring layer, 16: wiring layer, 17: transistor, 17a: gate insulating film, 17b: gate electrode, 17c: sidewall insulating film, 18: element isolation insulating film, 19: light-shielding layer, 21: transistor, 21a: gate insulating film, 21b: gate electrode, 21c: sidewall insulating film, 31: contact plug, 32: wiring layer, 33: transistor, 33a: gate insulating film, 33b: gate electrode, 34: via plug, 35: capacitor, 35a: n-type WBG layer, 35b: insulating film, 35c: n-type semiconductor layer, 36: capacitor, 36a: n-type WBG layer, 36b: insulating film, 36c: n-type semiconductor layer, 41: contact plug, 42: wiring layer, 43: via plug, 44: wiring layer, 45: via plug, 46: metal pad, 51: substrate, 51a: semiconductor substrate, 51b: WBG layer, 51c: WBG substrate, 52: interlayer insulating film, 52a: insulating film, 52b: insulating film, 53: contact plug, 54: contact plug, 55: wiring layer, 56: via plug, 57: wiring layer, 58: via plug, 61: via plug, 62: via plug, 63: wiring layer, 64: via plug, 65: metal pad, 71: insulating film, 72: contact plug, 73: wiring layer, 74: via plug, 75: wiring layer, 76: through plug, 77: metal pad, 81: substrate, 82: interlayer insulating film, 83: contact plug, 84: wiring layer, 85: via plug, 86: wiring layer, 87: metal pad, 91: contact plug, 92: wiring layer, 93: wiring layer, 94: metal pad, 95: contact plug, 96: wiring layer, 97: metal pad, 98: supporting substrate, 99: contact plug

Claims

1. A solid-state imaging device comprising: a first substrate; a photoelectric conversion unit provided within the first substrate for performing photoelectric conversion; and a holding unit for holding an electric charge or voltage generated in response to the photoelectric conversion, the holding unit including a first semiconductor layer formed of a first semiconductor having a band gap wider than the band gap of Si (silicon), the first semiconductor having the band gap of 3.0 eV or greater.

2. The solid-state imaging device according to claim 1, wherein the first semiconductor contains In (indium), Ga (gallium), or Zn (zinc).

3. The solid-state imaging device according to claim 1, wherein the holding portion includes the first semiconductor layer provided in the first substrate, and is a floating diffusion portion that holds the electric charges.

4. The solid-state imaging device according to claim 1, wherein the holding section includes the first semiconductor layer provided in the first substrate, and is a pixel memory that holds the electric charges.

5. The solid-state imaging device according to claim 1, wherein the first semiconductor layer includes both an n-type semiconductor layer and a p-type semiconductor layer.

6. The solid-state imaging device according to claim 1, further comprising a first transistor provided on the first substrate, the first semiconductor layer being provided within the first substrate and functioning as a source region or a drain region of the first transistor.

7. The solid-state imaging device according to claim 6, wherein the first transistor is a transfer transistor that transfers the electric charges.

8. The solid-state imaging device according to claim 1, wherein the holding section includes the first semiconductor layer provided above the first substrate, and is a capacitor that holds the voltage.

9. The solid-state imaging device according to claim 8, further comprising a second transistor electrically connected to the capacitor.

10. The solid-state imaging device according to claim 9, wherein the second transistor is a switch transistor that functions as a switch that electrically connects the capacitor and the amplifying transistor.

11. The solid-state imaging device described in claim 10, wherein the capacitor includes a first electrode including the first semiconductor layer and a second electrode including a second semiconductor layer separate from the first semiconductor layer, and the second transistor is electrically connected to the first semiconductor layer.

12. A solid-state imaging device comprising: a first substrate; a photoelectric conversion unit provided within the first substrate and performing photoelectric conversion; a first transistor provided on an upper surface of the first substrate; a first semiconductor layer provided above and spaced apart from the first substrate, the first semiconductor layer being made of a first semiconductor having a band gap wider than the band gap of Si (silicon); and a second transistor provided on an upper surface or a lower surface of the first semiconductor layer.

13. The solid-state imaging device according to claim 12, wherein the first semiconductor has a band gap of 3.0 eV or more.

14. The solid-state imaging device according to claim 12, wherein the first semiconductor includes In (indium), Ga (gallium), or Zn (zinc).

15. The solid-state imaging device according to claim 12, wherein the first semiconductor layer is provided on an upper surface or a lower surface of a second substrate disposed above the first substrate.

16. The solid-state imaging device according to claim 15, further comprising: a third substrate disposed above the second substrate; and a third transistor provided on a lower surface of the third substrate.

17. The solid-state imaging device according to claim 12, wherein the first semiconductor layer is a second substrate disposed above the first substrate and formed from the first semiconductor.

18. The solid-state imaging device according to claim 17, further comprising: a third substrate disposed above the second substrate; and a third transistor provided on a lower surface of the third substrate.

19. The solid-state imaging device according to claim 12, further comprising a holding section that includes the first semiconductor layer and holds the charge or voltage generated in response to the photoelectric conversion.

20. The solid-state imaging device according to claim 19, wherein the holding unit is a pixel memory that holds the charge, or a capacitor that holds the voltage.

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