Light detection device, method for manufacturing light detection device, and electronic device

Abstract

The present invention enhances the degree of freedom for arrangement of elements in a photoelectric conversion region. Provided is a light detection device comprising: a semiconductor layer; and a photoelectric conversion region that is partitioned by a separation region and is provided in the semiconductor layer. The separation region includes: a first separation region comprising a first excavated part extending from a first surface part side toward a second surface part side of the semiconductor layer; and a second separation region comprising a second excavated part that is formed by selectively removing a portion of the first excavated part on the first surface part side and that is formed so that a width in a lateral direction which intersects one direction (thickness direction of the semiconductor layer) is wider than a width in a shorter-side direction of the first excavated part. The photoelectric conversion region includes a pinning layer formed by introducing an impurity into the semiconductor layer around the first excavated part from the inside of the first excavated part. The pinning layer has a first portion extending from the first surface part toward the second surface part side of the semiconductor layer together with the first separation region, and a second portion extending from a bottom part of the second separation region toward the second surface part side of the semiconductor layer together with the first separation region.

Description

Photodetector, method of manufacturing the same, and electronic device

[0001] The present technology (technology related to the present disclosure) relates to a photodetector, a method for manufacturing a photodetector, and an electronic device, and in particular to a photodetector having a pinning layer at the interface between a photoelectric conversion region and an isolation region, a method for manufacturing the same, and technology that is effective when applied to an electronic device equipped with the same.

[0002] In photodetection devices such as distance measuring devices and solid-state imaging devices, a photoelectric conversion region of a semiconductor layer is divided by an isolation region. A known isolation region of this type is a recessed isolation region, which divides the photoelectric conversion region by forming a recessed portion in the semiconductor layer (see Patent Document 1). Another known technology is to provide a pinning layer at the interface between the semiconductor layer in the photoelectric conversion region and the recessed portion of the isolation region, thereby suppressing dark current caused by damage to the semiconductor layer due to the formation of the recessed portion (see Patent Document 2).

[0003] JP 2011-222900 A JP 2021-103793 A

[0004] Conventionally, pinning layers have been formed in two steps, similar to the formation of isolation regions. Specifically, first, a shallow recessed portion (shallow trench portion) is formed in the main surface portion of the main surface portion and the back surface portion, which are located opposite each other in the thickness direction of the semiconductor layer. Next, the semiconductor layer at the bottom of the shallow recessed portion is etched while side surfaces of the semiconductor layer are selectively covered with a mask from inside the shallow recessed portion (masked state), thereby forming a deep recessed portion (deep trench portion) that extends from the bottom of the shallow recessed portion toward the back surface of the semiconductor layer and has a width in the lateral direction narrower than that of the shallow recessed portion in a plan view. Next, while side surfaces of the semiconductor layer inside the shallow recessed portion are masked, impurities are selectively introduced from inside the deep recessed portion into the semiconductor layer surrounding the deep recessed portion to form a first pinning portion that pins damage caused to the semiconductor layer by the formation of the deep recessed portion. Next, an impurity introduction mask is formed on the main surface side of the semiconductor layer, and then impurities are selectively introduced into the semiconductor layer outside the impurity introduction mask from outside the main surface of the semiconductor layer to form a second pinning portion that pins damage caused in the semiconductor layer by the formation of the shallow recessed portion. In this way, a pinning layer including the first and second pinning portions is formed in two steps.

[0005] The conventional pinning layer thus formed can be selectively provided to avoid the floating diffusion region as a charge retention section provided on the main surface of the photoelectric conversion region, which is on the main surface side of the semiconductor layer.

[0006] However, due to factors such as the processing limits of the impurity introduction mask and misalignment of the impurity introduction mask, it is difficult to narrow the short-side width of the second pinning portion (the width from the shallow recess toward the photoelectric conversion region), and the short-side width of the first pinning portion formed by introducing impurities into the side portion of the semiconductor layer from inside the second recess (the width from the shallow recess toward the photoelectric conversion region) becomes wide.

[0007] Furthermore, impurities introduced into the main surface portion of the semiconductor layer from outside the main surface portion of the semiconductor layer diffuse in the vertical direction, which is the thickness direction of the semiconductor layer, and also in the horizontal direction, which intersects the thickness direction of the semiconductor layer, making it difficult to form the width of the second pinning portion in the short side direction (horizontal direction) to be equal to the width of the first pinning portion in the short side direction (horizontal direction).

[0008] On the other hand, on the main surface of the photoelectric conversion region, elements such as a charge holding section that holds the signal charge photoelectrically converted by the photoelectric conversion section, a transfer transistor that transfers the signal charge photoelectrically converted by the photoelectric conversion section to the charge holding section, and a pixel transistor included in a pixel circuit (readout circuit) that reads out the signal charge held in the charge holding section and outputs a pixel signal based on the readout signal charge are arranged.

[0009] These elements must be positioned away from the pinning layer to avoid interference with the pinning layer, and because the width of the second pinning section in the short direction is wider than the width of the first pinning section in the short direction, the element placement area in which elements can be placed on the main surface of the photoelectric conversion region is smaller, thereby reducing the freedom of element placement on the main surface of the photoelectric conversion region.

[0010] Furthermore, in conventional manufacturing, the deep recess is formed by etching the bottom of the shallow recess. Therefore, in order to surround the periphery of the photoelectric conversion region with an isolation region, the shallow recess must be wider in the short direction than the deep recess, which reduces the area available for element placement on the main surface of the photoelectric conversion region. This also reduces the degree of freedom in element placement on the main surface of the photoelectric conversion region.

[0011] An object of the present technology is to provide a technology that can increase the degree of freedom in arranging elements in a photoelectric conversion region having a pinning layer.

[0012] (1) A photodetector according to one aspect of the present technology includes a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction, and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region. The isolation region includes: a first isolation region including a first carved portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a second isolation region including a second carved portion formed on the first surface portion side of the semiconductor layer by selectively removing a portion of the first carved portion and having a width in a lateral direction intersecting the one direction that is wider than the width of the first carved portion. The photoelectric conversion region includes a pinning layer formed by introducing impurities into the semiconductor layer around the first carved portion from inside the first carved portion. The pinning layer includes a first portion that extends from the first surface portion of the semiconductor layer toward the second surface portion together with the first isolation region, and a second portion that extends from the bottom of the second isolation region toward the second surface portion of the semiconductor layer together with the first isolation region.

[0013] (2) A photodetector according to another aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending from the first surface portion of the semiconductor layer toward the second surface portion; and a pinning layer provided on the semiconductor layer side of an interface between the separation region and the photoelectric conversion region, wherein the separation region includes: a first separation region extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a second separation region provided on the first surface portion side of the semiconductor layer so as to selectively overlap with the first separation region and having a width in a lateral direction in a plan view that is wider than the width of the first separation region in the lateral direction, wherein the pinning layer includes: a first portion extending from the first surface portion of the semiconductor layer toward the second surface portion side along the first separation region, a second portion extending from a bottom portion of the second separation region toward the second surface portion along the first separation region.

[0014] (3) A method for manufacturing a photodetector according to another aspect of the present technology includes: forming a first carved portion extending from a first surface portion of a first surface portion and a second surface portion located on opposite sides of a semiconductor layer in one direction toward the second surface portion; introducing impurities from inside the first carved portion into a side surface portion of the semiconductor layer around the first carved portion to form a pinning layer in the side surface portion of the semiconductor layer extending from the first surface portion toward the second surface portion of the semiconductor layer; and selectively removing a portion of each of the first carved portion and the pinning layer on the first surface portion side of the semiconductor layer to form a second carved portion whose width in the short side direction is wider than the width in the short side direction of the first carved portion.

[0015] (4) An electronic device according to another aspect of the present technology includes the above-mentioned photodetector; an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that performs signal processing on a signal output from the photodetector.

[0016] 5A is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 6A is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. FIG. 7A is an equivalent circuit diagram showing a configuration example of a pixel and a pixel circuit according to a first embodiment of the present technology. FIG. 8A is a plan view schematically showing a configuration example of a pixel block included in the pixel array section of FIG. 1. FIG. 4A is an enlarged plan view of a main part in which a central part of the pixel block of FIG. 4A is enlarged. FIG. 8B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a4-a4 cutting line of FIG. 4. FIG. 8B is a longitudinal sectional view schematically showing a part of FIG. 5A. FIG. 8A is a plan view schematically showing a process of a manufacturing method of a solid-state imaging device according to a first embodiment of the present technology. FIG. 8A is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a6-a6 cutting line of FIG. 6A. FIG. 8B is a longitudinal sectional view schematically showing a process subsequent to FIG. 6A. FIG. 8A is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a7-a7 cutting line of FIG. 7A. FIG. 8B is a plan view schematically showing a process subsequent to FIG. 7A. FIG. 8A is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a8-a8 cutting line of FIG. 11A. FIG. 12A is a plan view schematically showing a step subsequent to FIG. 8A. FIG. 13A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a9-a9 cutting line of FIG. 9A. FIG. 14A is a plan view schematically showing a step subsequent to FIG. 9A. FIG. 14B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a10-a10 cutting line of FIG. 10A. FIG. 14B is a plan view schematically showing a step subsequent to FIG. 10A. FIG. 15A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a11-a11 cutting line of FIG. 11A. FIG. 15A is a longitudinal cross-sectional view schematically showing a step subsequent to FIG. 11A. FIG. 16A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a12-a12 cutting line of FIG. 12A. FIG. 16B is a longitudinal cross-sectional view schematically showing a step subsequent to FIG. 12A. FIG. 17A is a longitudinal cross-sectional view schematically showing a step subsequent to FIG. 17A. 14B is a longitudinal sectional view schematically showing a step subsequent to Fig. 14C; Fig. 15A is a longitudinal sectional view schematically showing one pixel block, which is a modified example 1-2 according to the first embodiment of the present technology; Fig. 15B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a15-a15 cutting line in Fig. 15A; Fig. 15C is a longitudinal sectional view schematically showing one pixel block, which is a modified example 1-3 according to the first embodiment of the present technology;16A . FIG. 17A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a16-a16 cutting line in FIG. 16A . FIG. 17B is a plan view schematically showing one pixel block, illustrating a modified example 1-4 according to the first embodiment of the present technology. FIG. 17A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a17-a17 cutting line in FIG. 17A . FIG. 17C is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure, illustrating a modified example 1-5 according to the first embodiment of the present technology. FIG. 17D is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure, illustrating a modified example 1-6 according to the first embodiment of the present technology. FIG. 17E is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure, illustrating a modified example 1-7 according to the first embodiment of the present technology. FIG. 17F is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure, illustrating a modified example 1-8 according to the first embodiment of the present technology. FIG. 17G is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure, illustrating a modified example 1-9 according to the first embodiment of the present technology. FIG. 17H is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure, illustrating a modified example 1-10 according to the first embodiment of the present technology. FIG. 17H is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure, illustrating a modified example 1-11 according to the first embodiment of the present technology. 28. FIG. 28 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a modified example 1-12 according to the first embodiment of the present technology. FIG. 29 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a modified example 1-13 according to the first embodiment of the present technology. FIG. 30 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a modified example 1-14 according to the first embodiment of the present technology. FIG. 31 is a plan view schematically showing a configuration example of a pixel block of a solid-state imaging device according to a second embodiment of the present technology. FIG. 32 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a28-a28 cutting line of FIG. 28. FIG. 33 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b28-b28 cutting line of FIG. 28. FIG. 34 is a plan view schematically showing a configuration example of a pixel block of a modified example 2-1 according to the second embodiment of the present technology. FIG. 35 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a30-a30 cutting line of FIG. 30. FIG. 36 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b30-b30 cutting line of FIG. 35. FIG. 37 is a plan view schematically showing a configuration example of a pixel block of a modified example 2-2 according to the second embodiment of the present technology. Fig. 33 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a32-a32 cutting line in Fig. 32. Fig. 34 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b32-b32 cutting line in Fig. 32. Fig. 35 is a plan view schematically showing a configuration example of a pixel block, which is a modified example 2-3 according to a second embodiment of the present technology.36A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a34-a34 cutting line of FIG. 34 . FIG. 36B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b34-b34 cutting line of FIG. 34 . FIG. 36C is a plan view schematically showing a configuration example of one pixel block in a solid-state imaging device according to a third embodiment of the present technology. FIG. 36A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a36-a36 cutting line of FIG. 36A . FIG. 36C is a plan view schematically showing a configuration example of a pixel in a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 37 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a37-a37 cutting line of FIG. 37 . FIG. 37B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b37-b37 cutting line of FIG. 37B . FIG. 39A is a plan view schematically showing a configuration example of a pixel in Modification 3-1 according to the third embodiment of the present technology. FIG. 39B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a39-a39 cutting line of FIG. 39A . FIG. 39C is a plan view schematically showing a configuration example of a pixel in Modification 3-2 according to the third embodiment of the present technology. Fig. 40B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a40-a40 cutting line in Fig. 40A. Fig. 40C is a diagram showing a schematic configuration of an electronic device according to a fifth embodiment of the present technology.

[0017] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0018] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0019] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0020] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0021] In addition, in the following embodiments, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type as the conductivity type of the semiconductor, but the conductivity types may be selected in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type.

[0022] In the following embodiments, among the three directions orthogonal to each other in space, a first direction and a second direction orthogonal to each other in the same plane are referred to as the X direction and the Y direction, respectively, and a third direction orthogonal to each of the first direction and the second direction is referred to as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 21 (described later) will be described as the Z direction. In the following embodiments, the Z direction will be described as "one direction" of the present technology.

[0023] In addition, in the following embodiments, the thickness of the semiconductor layer 21 is the distance between the first surface portion S1 and the second surface portion S2, which are located on opposite sides in the Z direction, and the thickness direction of the semiconductor layer 21 is the direction representing the thickness of the semiconductor layer 21.

[0024] In the following embodiments, a plan view refers to a case where the semiconductor layer 21 is viewed from the Z direction (one direction). A cross-sectional view refers to a case where a cross section along the Z direction (one direction) is viewed from a direction (Z direction) perpendicular to the cross section.

[0025] First Embodiment In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector will be described. Also, in this first embodiment, a pixel in which one photoelectric conversion unit is provided in a photoelectric conversion region will be described.

[0026] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1A will be described. As shown in Fig. 1 , the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in Fig. 41 , this solid-state imaging device 1A (101) captures image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0027] As shown in FIG. 1 , a semiconductor chip 2 on which a solid-state imaging device 1A is mounted includes, in a two-dimensional plane including mutually orthogonal X and Y directions, a rectangular pixel array section 2A provided in the center and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. The semiconductor chip 2 is formed in a manufacturing process by dicing a semiconductor wafer including a semiconductor layer 21 (described below) into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in a wafer state before the semiconductor wafer is diced. In other words, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0028] The pixel array unit 2A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in Fig. 41. The pixel array unit 2A has a plurality of pixels (sensor pixels) 3 arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0029] 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 functions as an input / output terminal (external terminal) that electrically connects the semiconductor chip 2 to an external device.

[0030] <Logic Circuit> The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0031] 2 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion section of each pixel 3 in accordance with the amount of received light to the column signal processing circuit 5 via vertical signal lines 11.

[0032] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0033] 2 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0034] 2 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 via the horizontal signal line 12, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0035] 2 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0036] <Pixel Block> The semiconductor chip 2 includes a pixel block 15 and a pixel circuit (readout circuit) 16 shown in Fig. 3. As shown in Fig. 3 and Fig. 4A, the pixel block 15 includes a plurality of pixels 3. The pixel block 15 of the first embodiment includes, for example, a 2x2 arrangement of four pixels 3 (3a, 3b, 3c, 3d) arranged two by two adjacent to each other in each of the X and Y directions in a plan view, although this is not limited thereto. Although Fig. 3 and Fig. 4A mainly illustrate one pixel block 15, the pixel blocks 15 are repeatedly arranged in each of the X and Y directions to form the pixel array section 2A shown in Fig. 1.

[0037] As shown in FIG. 3 , the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 each have common components. Specifically, each of the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 includes a photoelectric conversion unit 25, a floating diffusion region FD serving as a charge storage unit for storing (accumulating) signal charges photoelectrically converted by the photoelectric conversion unit 25, and a transfer transistor TR for transferring the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. Each of the four pixels 3 a, 3 b, 3 c, and 3 d included in one pixel block 15 also includes a photoelectric conversion region 22 of the semiconductor layer 21 shown in FIGS. 4A and 5A . The photoelectric conversion unit 25, the floating diffusion region FD, and the transfer transistor TR are each provided in the photoelectric conversion region 22, as shown in FIG. 5A . In FIG. 5A, two pixels 3a and 3d out of four pixels 3a, 3b, 3c and 3d included in one pixel block 15 are shown.

[0038] 3 is configured by, for example, a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 25 also temporarily holds (accumulates) the generated signal charge.

[0039] The photoelectric conversion unit 25 has a cathode side electrically connected to the source region of the transfer transistor TR, and an anode side electrically connected to a reference potential line (for example, ground).

[0040] 3 transfers the signal charges photoelectrically converted by the photoelectric conversion unit 25 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 25, and the drain region is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line of the pixel drive lines 10 shown in FIG.

[0041] (Floating Diffusion Region) The floating diffusion region FD shown in FIG. 3 temporarily accumulates and holds the signal charge transferred from the photoelectric conversion unit 25 via the transfer transistor TR.

[0042] <Pixel Circuit> The pixel circuit 16 shown in FIG. 3 has its input side electrically connected to the floating diffusion region FD of the pixel 3. In this first embodiment, the pixel circuit 16 is provided for each pixel block 15, for example. Here, in this first embodiment, as an example, a circuit configuration is used in which one pixel circuit (readout circuit) 16 is assigned to one pixel block 15, each unit of which includes four pixels 3. However, the assignment of the pixel circuits 16 is not limited to this first embodiment. For example, a circuit configuration in which one pixel circuit 16 is assigned to one pixel block 15, each unit of which includes two or more pixels 3, may also be used. Alternatively, a circuit configuration in which one pixel circuit 16 is assigned to multiple pixel blocks 15, each unit of which includes multiple pixels 3, may also be used. Alternatively, a circuit configuration in which one pixel circuit 16 is assigned to one pixel 3 may also be used.

[0043] 3 reads out the signal charges held in the floating diffusion region FD of the pixel 3 and outputs a pixel signal based on the read-out signal charges. In other words, the pixel circuit 16 converts the signal charges photoelectrically converted by the photoelectric conversion unit 25 (photodiode PD) into a pixel signal based on the signal charges and outputs the pixel signal.

[0044] 3, the pixel circuit 16 includes, but is not limited to, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG as pixel transistors Q. These pixel transistors Q (AMP, SEL, RST, FDG) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２ These pixel transistors are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0045] Of the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG mainly function as switching elements, and the remaining amplification transistor AMP mainly functions as an amplification element.

[0046] 3, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD of each of the four pixels 3 (3a, 3b, 3c, and 3d) and the source region of the switching transistor FDG.

[0047] 3, the source region of the select transistor SEL is electrically connected to the vertical signal line 11 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the select transistor SEL is electrically connected to the select transistor drive line of the pixel drive lines 10 shown in FIG.

[0048] 3, the source region of the reset transistor RST is electrically connected to the drain of the switching transistor FDG, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG.

[0049] 3, the drain region of the switching transistor FDG is electrically connected to the source region of the reset transistor RST, and the drain region is electrically connected to the gate electrode of the amplification transistor AMP and the floating diffusion region FD of each of the four pixels 3 (3 a, 3 b, 3 c, 3 d). The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line among the pixel drive lines 10 shown in FIG.

[0050] The selection transistor SEL and the switching transistor FDG may be omitted as necessary. When the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL). When the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode and floating diffusion region FD of the amplification transistor AMP.

[0051] When the transfer transistor TR shown in FIG. 3 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 25 (photodiode PD) to the floating diffusion region FD.

[0052] 3, when the reset transistor RST is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The selection transistor SEL shown in FIG. 3 controls the output timing of the pixel signal from the pixel circuit 16.

[0053] 3 generates a pixel signal having a voltage corresponding to the level of the signal charge held in the floating diffusion region FD. The amplifier transistor AMP constitutes a source-follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the signal charge generated in the photoelectric conversion unit 25 (photodiode PD). When the selection transistor SEL is turned on, the amplifier transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

[0054] The switching transistor FDG shown in FIG. 3 controls charge retention by the floating diffusion region FD, and adjusts the multiplication factor of the voltage according to the potential amplified by the amplifier transistor AMP.

[0055] During operation of the solid-state imaging device 1A according to the first embodiment, signal charges generated in the photoelectric conversion unit 25 of the pixel 3 are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 3. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 16 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 16. A horizontal line selection control signal is applied from the vertical shift register to the gate electrode of the select transistor SEL of the pixel circuit 16. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 11. By setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 16 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0056] 3 are mounted on a semiconductor layer 21 (see FIG. 5A ), which will be described later. In addition, although not limited thereto, in the first embodiment, the pixel transistors Q (AMP, SEL, RST, FDG) included in the pixel circuit 16 in FIG. 3 are also mounted on the semiconductor layer 21 (see FIG. 4A ), for example.

[0057] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the solid-state imaging device 1A (semiconductor chip 2) will be described with reference to FIGS. 4A, 4B, 5A, and 5B.

[0058] 4A, 4B, 5A, and 5B, the multilayer wiring layer described later is omitted for clarity of illustration. Also, while Fig. 1 is a plan view of the semiconductor chip 2 as viewed from its light incident surface side, Fig. 4A is a plan view of the semiconductor chip 2 as viewed from the opposite side to the light incident surface side (the multilayer wiring layer side).

[0059] 5A, the solid-state imaging device 1A according to the first embodiment includes a semiconductor layer 21 having a first surface portion S1 and a second surface portion S2 located on opposite sides in a thickness direction (Z direction), which is one direction, a separation region 31 provided in the semiconductor layer 21 and extending from the first surface portion S1 side toward the second surface portion S2 side of the semiconductor layer 21, and a photoelectric conversion region 22 provided in the semiconductor layer 21 and partitioned by the separation region 31. The photoelectric conversion region 22 includes the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21.

[0060] In addition, the solid-state imaging device 1A according to the first embodiment further includes a planarization film 61, an optical filter layer 63, and a lens layer 64, which are sequentially provided on the second surface S2 side of the semiconductor layer 21 from the second surface S2 side.

[0061] Although not shown, the solid-state imaging device 1A according to the first embodiment further includes a multi-layer wiring layer provided on the first surface S1 side of the semiconductor layer 21.

[0062] Here, the first surface S1 of the semiconductor layer 21 is sometimes referred to as a main surface or element formation surface, and the second surface S2 is sometimes referred to as a back surface. The solid-state imaging device 1A according to the first embodiment is a back-illuminated image sensor that photoelectrically converts incident light incident from the second surface S2 side of the semiconductor layer 21 using a photoelectric conversion unit 25 (photodiode PD) provided in the photoelectric conversion region 22 of the semiconductor layer 21. Therefore, in the first embodiment, the second surface S2 of the semiconductor layer 21 is sometimes referred to as a light incident surface.

[0063] In the first embodiment, the floating diffusion region FD corresponds to a specific but not limitative example of a "charge holding portion" of the present technology.

[0064] <Planarization Film, Optical Filter Layer, and Lens Layer> As shown in FIG. 5A , the planarization film 61 is provided on the second surface S2 side of the semiconductor layer 21 so as to cover the second surface S2 of the semiconductor layer 21, and planarizes the second surface S2 side of the semiconductor layer 21.

[0065] 5A , the optical filter layer 63 is provided on the side of the planarization film 61 opposite to the semiconductor layer 21. This optical filter layer 63 separates the color of incident light that is incident from the light incident surface side (the second surface portion S2 side) of the solid-state imaging device 1A. This optical filter layer 63 includes an optical filter portion 63 a for each pixel 3 (for each photoelectric conversion region 22) that transmits light of a specific wavelength, such as, but not limited to, red (R), green (G), or blue (B).

[0066] 5A , the lens layer 64 is provided on the side of the optical filter layer 63 opposite to the planarization film 61. The lens layer 64 includes a microlens (on-chip lens) 64 a for each pixel 3 (for each photoelectric conversion region 22) that collects irradiated light and allows the collected light to efficiently enter the photoelectric conversion region 22.

[0067] That is, the pixel 3 of this first embodiment includes a photoelectric conversion region 22, a planarization film 61 provided on the second surface portion S2 side of this photoelectric conversion region 22, an optical filter portion 63a, and a microlens 64a.

[0068] <Semiconductor Layer> As shown in Fig. 5A , the semiconductor layer 21 includes an isolation region 31 extending in the thickness direction (Z direction) of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by this isolation region 31. As shown in Fig. 4A , the photoelectric conversion region 22 is provided for each pixel 3. The semiconductor layer 21 may be a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In this first embodiment, although not limited thereto, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 21.

[0069] 5A , the semiconductor layer 21 further includes a pinning layer 33 provided on the photoelectric conversion region 22 side of the interface Lp between the isolation region 31 and the photoelectric conversion region 22. The pinning layer 33 is composed of a semiconductor region of the same conductivity type as the well region 23 described later.

[0070] 4A , the separation region 31 includes a first extending portion 31x extending in the X direction in a plan view and a second extending portion 31y extending in the Y direction. The separation region 31 further includes an intersection portion (intersection portion) 31xy where the first extending portion 31x and the second extending portion 31y intersect with each other on the same plane. In this first embodiment, the first extending portion 31x and the second extending portion 31y are, for example, perpendicular to each other.

[0071] The first extending portions 31x are repeatedly arranged at predetermined intervals in the Y direction, and the second extending portions 31y are repeatedly arranged at predetermined intervals in the X direction. That is, the separation region 31 has a grid-like planar pattern in plan view.

[0072] 4A , the separation region 31 corresponding to one photoelectric conversion region 22 has a rectangular annular planar pattern (ring-shaped planar pattern) in a plan view, and surrounds the periphery of one photoelectric conversion region 22. On the other hand, as shown in FIGS. 4A and 4B , the separation region 31 corresponding to one pixel block 15 has a composite planar pattern having a cross-shaped planar pattern in which a first extension portion 31 x and a second extension portion 31 y are arranged orthogonal to each other within the rectangular annular planar pattern.

[0073] 4A and 4B , in the separation region 31 corresponding to one pixel block 15, an intersection (intersection) 31xy between the first extending portion 31x and the second extending portion 31y is located in the center of the pixel block 15. The photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) are arranged in a matrix (2 × 2) so as to surround this intersection 31xy. That is, the photoelectric conversion regions 22 of the four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15 are adjacent to each other in the X direction and the Y direction, with the separation region 31 interposed therebetween, in a plan view.

[0074] 5A , the isolation region 31 extends in one direction, that is, the thickness direction (Z direction) of the semiconductor layer 21, and electrically and optically isolates two adjacent photoelectric conversion regions 22 in a plan view. The isolation region 31 is configured, for example, as an indentation type, i.e., a trench type, in which first and second indentations (32 a, 35 a) are formed in the semiconductor layer 21 to partition and isolate the photoelectric conversion regions 22.

[0075] (First Separation Region and Second Separation Region) As shown in FIGS. 4A to 5B , the separation region 31 is formed by selectively removing a part of the first carved portion 32 a on the first surface S1 side of the semiconductor layer 21 and having a width W １ is the width W of the first recessed portion 32a in the short side direction. ２ and a second isolation region 35 including a second dug portion 35a formed wider than the first isolation region 32. In this first embodiment, although not limited thereto, for example, the first isolation region 32 further includes an isolation insulating film 32b provided inside the first dug portion 32a. Furthermore, the second isolation region 35 further includes an isolation insulating film 35b provided inside the second dug portion 35a. The isolation insulating films 32b and 35b may be, for example, silicon oxide films.

[0076] 4A to 5B, the isolation region 31 has a first portion including only the first isolation region 32 of the first isolation region 32 and the second isolation region 35, and a second portion including both the first isolation region 32 and the second isolation region 35. In other words, the isolation region 31 has a first portion including only the first dug portion 32a of the first dug portion 32a and the second dug portion 35a, and a second portion including both the first dug portion 32a and the second dug portion 35a. Each of the first isolation region 32 and the first dug portion 32a in the first portion of the isolation region 31 extends from the first face S1 side toward the second face S2 side of the semiconductor layer 21. On the other hand, each of the first isolation region 32 and the first recessed portion 32a in the second part of the isolation region 31 extends from the bottom of the second isolation region 35 (second recessed portion 35a) toward the second surface S2 of the semiconductor layer 21 and is spaced apart from the first surface S1 of the semiconductor layer 21.

[0077] 4B and 5B , the second isolation region 35 is provided adjacent to the floating diffusion region FD in a plan view. In the first embodiment, as will be described in detail later, the floating diffusion region FD is provided around the intersection 31xy of the isolation region 31 in the pixel block 15, and therefore the second isolation region 35 is provided adjacent to the floating diffusion region FD at the intersection 31xy of the isolation region 31.

[0078] Here, as shown in FIG. 4B , in a plan view of the semiconductor layer 21 viewed from the thickness direction (Z direction) of the semiconductor layer 21, the direction in which the interface Lp between the semiconductor layer 21 in the photoelectric conversion region 22 and the isolation region 31 extends is referred to as the extension direction A. １ This stretching direction A １ The direction perpendicular to the cross direction A ２ The longitudinal direction of each of the first dug portion 32 a (first separation region 32 ) and the second dug portion 35 a (second separation region 35 ) in plan view is referred to as the extension direction A １ The widthwise direction of each of the first dug portion 32 a (first separation region 32 ) and the second dug portion 35 a (second separation region 35 ) in plan view is the cross direction A ２ is.

[0079] As shown in FIG. 4B , the width direction (cross direction A) of the second isolation region 35 ２ ) is the width along the short side direction (cross direction A ２ ) (the width W of the second recessed portion 35a in the short side direction) １ Width W of the first recessed portion 32a in the short side direction ２ 5A and 5B, the isolation region 31 has a step portion 36 due to the difference in width between the second isolation region 35 and the first isolation region 32.

[0080] 4A , the photoelectric conversion region 22 is surrounded by an isolation region 31 in a plan view and has a rectangular planar shape. Specifically, the photoelectric conversion region 22 is surrounded by two first extending portions 31x that extend in the X direction and are spaced apart in the Y direction, and two second extending portions 31y that extend in the Y direction and are spaced apart in the X direction. The photoelectric conversion region 22 is partitioned by the first extending portions 31x and the second extending portions 31y, and is separated from adjacent photoelectric conversion regions 22.

[0081] As shown in FIG. 5A, the photoelectric conversion region 22 has a p-type well region 23 provided in the semiconductor layer 21 across the first surface portion S1 and the second surface portion S2 of the semiconductor layer 21, and an n-type semiconductor region 24 provided in the p-type well region 23 and spaced apart from the first surface portion S1 of the semiconductor layer 21.

[0082] The photoelectric conversion region 22 further includes a p-type well region 23 and an n-type semiconductor region 24, and further includes a photoelectric conversion portion 25 provided in the semiconductor layer 21 at a distance from the first surface portion S1 of the semiconductor layer 21.

[0083] As shown in Figures 4A and 5A, the photoelectric conversion region 22 is provided on the first surface S1 side of the semiconductor layer 21 and further includes a floating diffusion region FD as a charge holding section that holds (accumulates) the signal charge photoelectrically converted by the photoelectric conversion section 25, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion section 25 to the floating diffusion region FD.

[0084] The photoelectric conversion region 22 further includes a p-type power supply contact region WC provided on the first surface S1 side of the semiconductor layer 21, and a pixel transistor Q included in the pixel circuit 16 described above.

[0085] 4A to 5B , the photoelectric conversion region 22 further includes a pinning layer 33 formed by introducing impurities into the side surface of the semiconductor layer 21 around the first carved portion 32 a from inside the first carved portion 32 a of the isolation region 31. The pinning layer 33 is provided on the semiconductor layer 21 (photoelectric conversion region 22) side of the interface Lp between the semiconductor layer 21 of the photoelectric conversion region 22 and the isolation region 31.

[0086] 4A and 5A , the p-type well region 23 is provided over a wide area in the photoelectric conversion region 22, extending across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 21. The p-type well region 23 is composed of a p-type semiconductor region.

[0087] 4A and 5A , the n-type semiconductor region 24 is provided in the p-type well region 23 in the photoelectric conversion region 22. That is, six surfaces of the n-type semiconductor region 24, including the top surface, bottom surface, and four side surfaces, are surrounded by the p-type well region 23. The n-type semiconductor region 24 is separated from the first surface S1 and second surface S2 of the semiconductor layer 21 and the isolation region 31. That is, the n-type semiconductor region 24 forms a pn junction with the p-type well region 23 on the six surfaces of the n-type semiconductor region 24.

[0088] 4A and 5A , the photoelectric conversion unit 25 is provided in the photoelectric conversion region 22. The photoelectric conversion unit 25 includes a p-type well region 23 and an n-type semiconductor region 24 in the photoelectric conversion region 22. The photoelectric conversion unit 25 is configured as a p-n junction photodiode (PD) including a p-n junction between the p-type well region 23 and the n-type semiconductor region 24.

[0089] The photoelectric conversion unit 25 photoelectrically converts light incident on the n-type semiconductor region 24 from the second surface S2 side of the semiconductor layer 21 into signal charges in the n-type semiconductor region 24, and temporarily holds (accumulates) the photoelectrically converted signal charges at the pn junction between the p-type well region 23 and the n-type semiconductor region 24. The photoelectric conversion unit 25 is provided in the semiconductor layer 21, spaced apart from the first surface S1 of the semiconductor layer 21. The photoelectric conversion unit 25 is provided for each photoelectric conversion region 22 (pixel 3).

[0090] (n-Type Floating Diffusion Region) As shown in FIGS. 4A and 5A , the floating diffusion region FD is adjacent to the second isolation region 35 in a plan view. The floating diffusion region FD is provided in the p-type well region 23 on the first surface portion S1 side of the semiconductor layer 21. The floating diffusion region FD overlaps with the n-type semiconductor region 24 in a plan view and is separated from the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21. That is, the p-type well region 23 is provided between the n-type floating diffusion region FD and the n-type semiconductor region 24. The floating diffusion region FD is provided in the p-type well region 23 and is composed of an n-type semiconductor region with a higher impurity concentration than the n-type semiconductor region 24. That is, the floating diffusion region FD of this first embodiment is composed of the same conductivity type, n-type, as the n-type semiconductor region 24.

[0091] Here, in this first embodiment, the n-type floating diffusion region FD overlaps with the n-type semiconductor region 24 in a planar view, but the n-type floating diffusion region FD may not overlap with the n-type semiconductor region 24 in a planar view.

[0092] 5A and 5B , the floating diffusion region FD is provided on the first surface S1 side of the semiconductor layer 21 relative to the step 36 between the first isolation region 32 and the second isolation region 35 of the isolation region 31 in the thickness direction (Z direction) of the semiconductor layer 21. In other words, the floating diffusion region FD is provided on the first surface S1 side of the semiconductor layer 21 relative to the second isolation region 35 of the isolation region 31.

[0093] As shown in Figure 4A, the floating diffusion regions FD of each of the four photoelectric conversion regions 22 (four pixels 3a, 3b, 3c, and 3d) included in one pixel block 15 are arranged outside the intersection 31xy of the isolation region 31 in a planar view, surrounding the intersection 31xy, and adjacent to the intersection 31xy.

[0094] 4A and 5A, the transfer transistor TR is provided on the first surface S1 side of the semiconductor layer 21. The transfer transistor TR has a gate electrode 54 provided on the first surface S1 side of the semiconductor layer 21, and a gate insulating film 53 provided between the gate electrode 54 and the semiconductor layer 21. The transfer transistor TR also has an n-type semiconductor region 24 and an n-type floating diffusion region FD functioning as a source region and a drain region, and a p-type well region 23 functioning as a channel formation region. The transfer transistor TR is, for example, configured as a vertical type in which the gate electrode 54 extends along the thickness direction of the semiconductor layer 21, although this is not limited thereto.

[0095] 4A and 4B , the transfer transistors RT of the four photoelectric conversion regions 22 (four pixels 3a, 3b, 3c, and 3d) included in one pixel block 15 are biased toward the intersection 31xy of the isolation region 31 in plan view. The gate electrodes 54 of the transfer transistors TR of the four photoelectric conversion regions 22 are provided outside the n-type floating diffusion region FD so as to surround the intersection 31xy of the isolation region 31 in plan view.

[0096] 5B , the gate electrode 54 of the transfer transistor TR has a head 54a provided outside the first surface S1 of the semiconductor layer 21 with the gate insulating film 53 interposed therebetween, and a body 54b that protrudes from the head 54a into the semiconductor layer 21 and is adjacent to the semiconductor layer 21 with the gate insulating film 53 interposed therebetween. The gate electrode 54 of the first embodiment is not limited to this, but for example, the body 54b is narrower than the head 54a.

[0097] The body 54b of the gate electrode 54 is provided in the gate trench 52 of the semiconductor layer 21 with the gate insulating film 53 interposed therebetween, and reaches the n-type semiconductor region 24. The gate trench 52 extends from the first surface S1 toward the second surface S2 of the semiconductor layer 21. The gate insulating film 53 is made of, for example, a silicon oxide film. The gate electrode 54 is made of, for example, a polycrystalline silicon film doped with an impurity that reduces resistance.

[0098] 5B, when a gate voltage is applied to the gate electrode 54 to turn on the transfer transistor TR, a charge transfer path (channel) electrically connecting the n-type semiconductor region 24 and the n-type floating diffusion region FD is formed in the p-type well region 23. Then, signal charges photoelectrically converted in the n-type semiconductor region 24 of the photoelectric conversion unit 25 are transferred from the n-type semiconductor region 24 to the n-type floating diffusion region FD through the charge transfer path.

[0099] 4A , in each of the four photoelectric conversion regions 22 included in one pixel block 15, the p-type power supply contact region WC is provided outside the other intersections on the opposite side of the intersections 31xy of the isolation regions 31 located in the center of the pixel block 15 in a plan view. Also, as shown in FIG. 5A , the p-type power supply contact region WC is provided in the p-type well region 23 on the first surface S1 side of the semiconductor layer 21, and is electrically connected to the p-type well region 23. The p-type power supply contact region WC is made of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23.

[0100] A first reference potential (Vss potential) of, for example, 0 V is applied to the p-type power supply contact region WC as a reference potential within the solid-state imaging device 1A (within the semiconductor chip 2) during operation, and the potential is fixed to this first reference potential during operation.

[0101] 4A , as described above, the photoelectric conversion region 22 of each of the four pixels 3 (3 a, 3 b, 3 c, 3 d) included in one pixel block 15 has a pixel transistor Q included in one pixel circuit 16. In the first embodiment, although not limited to this, for example, as shown in FIG. 4A , of the four pixels 3 (3 a, 3 b, 3 c, 3 d) included in one pixel block 15, the photoelectric conversion region 22 of pixel 3 a has an amplification transistor AMP as the pixel transistor Q, the photoelectric conversion region 22 of pixel 3 b has a selection transistor SEL as the pixel transistor Q, the photoelectric conversion region 22 of pixel 3 c has a switching transistor FDG as the pixel transistor Q, and the photoelectric conversion region 22 of pixel 3 d has a reset transistor RST as the pixel transistor Q.

[0102] 4A and 5A, the amplification transistor AMP in the pixel transistor Q included in the pixel circuit 16 has a gate electrode 56 provided on the outside of the first surface portion S1 of the semiconductor layer 21, and a gate insulating film provided between the gate electrode 56 and the first surface portion S1 of the semiconductor layer 21. The amplification transistor AMP also has a pair of main electrode regions 57a and 57b that are provided in the semiconductor layer 21 on both sides of the gate electrode 56 in the gate length direction (direction of the gate length Lg) and function as a source region and a drain region, and a channel formation portion provided between the pair of main electrode regions 57a and 57b.

[0103] Each of the pair of main electrode regions 57a and 57b is made up of, for example, an n-type semiconductor region provided in the p-type well region 23. The channel formation portion is made up of, for example, the p-type well region 23. The gate insulating film is made up of, for example, a silicon oxide film. The gate electrode 56 is made up of, for example, a polycrystalline silicon film into which an impurity that reduces resistance value is introduced.

[0104] In addition, as the pixel transistors Q included in the pixel circuit 16, the selection transistor SEL, the switching transistor FDG, and the reset transistor RST other than the amplification transistor AMP also have the same configuration as the amplification transistor AMP, so a description of these pixel transistors Q (SEL, FDG, RST) will be omitted.

[0105] In addition, in the first embodiment, as an example, a case where one pixel transistor Q is arranged in one photoelectric conversion region 22 is described, but a plurality of pixel transistors Q with the same function may be arranged in one photoelectric conversion region 22, or a plurality of pixel transistors Q with different functions may be arranged in one photoelectric conversion region 22. Also, there is a case where no pixel transistor Q is arranged in the photoelectric conversion region 22. In this case, the pixel transistor Q is arranged in another semiconductor layer provided so as to overlap the semiconductor layer 21 in a planar view.

[0106] 5A and 5B , the pinning layer 33 is provided on the photoelectric conversion region 22 side of the interface Lp between the first isolation region 32 of the isolation region 31 and the semiconductor layer 21 of the photoelectric conversion region 22, in alignment with the first isolation region 32, and extends along the first isolation region 32 in the thickness direction (Z direction) of the semiconductor layer 21. As shown in FIGS. 4A and 4B , the pinning layer 33 extends along the periphery of the photoelectric conversion region 22 in a planar view, and its planar pattern in a planar view is an annular planar pattern (ring-shaped planar pattern). The pinning layer 33 is composed of a p-type semiconductor region of the same conductivity type as the p-type well region 23. The pinning layer 33 is composed of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23.

[0107] As shown in Figure 5A, the p-type pinning layer 33 includes a first portion 33a (left and right sides of Figure 5A) that extends from the first surface S1 of the semiconductor layer 21 toward the second surface S2 side together with the first isolation region 32 of the isolation region 31, and a second portion 33b (center of Figure 5A) that extends from the bottom of the second isolation region 35 toward the second surface S2 side of the semiconductor layer 21 together with the first isolation region 32 of the isolation region 31.

[0108] The pinning layer 33 is formed in the manufacturing process of the solid-state imaging device 1A by introducing impurities from inside a first dug portion 32a formed in the semiconductor layer 21 to the side surface portion of the semiconductor layer 21 around the first dug portion 32a. The first portion 33a and the second portion 33b of the pinning layer 33 are formed in the manufacturing process of the solid-state imaging device 1A by selectively removing a portion of the pinning layer 33 together with a portion of the first dug portion 32a (first isolation region 32) when forming the second dug portion 35a. Therefore, the first portion 33a of the pinning layer 33 extends from the first surface S1 toward the second surface S2 of the semiconductor layer 21 together with the first isolation region 32 of the isolation region 31. The second portion 33b of the pinning layer 33 extends from the bottom of the second isolation region 35 toward the second surface S2 of the semiconductor layer 21 together with the first isolation region 32 of the isolation region 31, and terminates together with the first isolation region 32 at the bottom of the second recessed portion 35a.

[0109] 5A , the first isolation region 32 of the isolation region 31 has a first portion extending from the first surface S1 of the semiconductor layer 21 toward the second surface S2, and a second portion extending from the bottom of the second isolation region 35 of the isolation region 31 toward the second surface S2 of the semiconductor layer 21. In the first embodiment, although not limited thereto, the first isolation region 32 and the pinning layer 33 each reach the second surface S2 of the semiconductor layer 21.

[0110] Although not shown in detail, the pinning layer 33 has a ring shape that continuously surrounds the periphery of the photoelectric conversion region 22 in a planar view on the second surface S2 side of the semiconductor layer 21 relative to the bottom of the second isolation region 35. In contrast, as shown in FIG. 4A , the pinning layer 33 has a ring shape that surrounds the photoelectric conversion region 22 in a planar view and is divided by the second isolation region 35 on the first surface S1 side of the semiconductor layer 21 relative to the bottom of the second isolation region 35.

[0111] 4A to 5B , the pinning layer 33 is provided on the semiconductor layer 21 side of the interface Lp between the semiconductor layer 21 of the photoelectric conversion region 22 and the first isolation region 32, except for the interface Lp between the semiconductor layer 21 of the photoelectric conversion region 22 and the second isolation region 35. The pinning layer 33 is provided on the semiconductor layer 21 side of the interface Lp between the semiconductor layer 21 of the photoelectric conversion region 22 and the first isolation region 32, except for the interface Lp between the semiconductor layer 21 of the photoelectric conversion region 22 and the second isolation region 35. ２ is the width W of the first recessed portion 32a in the lateral direction. １ In the first embodiment, the width W of the first dug portion 32a in the lateral direction is set to be larger than the width W of the first dug portion 32a. １ and the width W of each pinning layer 33 located on both sides of the first dug portion 32 a in the short direction. ２ The second carved portion 35 a is formed by the p-type pinning layer 33 . Therefore, the second isolation region 35 protrudes further toward the photoelectric conversion region 22 side than the p-type pinning layer 33 .

[0112] The pinning layer 33 pins damage (dangling bonds) that occurs in the side surfaces of the semiconductor layer 21 around the first dug portion 32a due to the formation of the first dug portion 32a, and suppresses dark current caused by this damage. The dark current is suppressed by absorbing electrons that cause the dark current into holes, which are majority carriers in the p-type pinning layer 33.

[0113] <Plane Pattern of Photoelectric Conversion Region> As shown in FIG. 4A , each of the four pixels 3 (3 a, 3 b, 3 c, 3 d) included in one pixel block 15 has a different plane pattern, including the arrangement of the transfer transistor TR and the pixel transistor Q, in a planar view.

[0114] In the first embodiment, as shown in Fig. 4A, the planar patterns of pixels 3a and 3b arranged in the Y direction are inverted patterns with the boundary between pixels 3a and 3b as the inversion axis. Furthermore, the planar patterns of pixels 3c and 3d arranged in the Y direction are inverted patterns with the boundary between pixels 3c and 3d as the inversion axis. Furthermore, the planar patterns of pixels 3a and 3c arranged in the X direction are inverted patterns with the boundary between pixels 3a and 3c as the inversion axis. Furthermore, the planar patterns of pixels 3b and 3d arranged in the X direction are inverted patterns with the boundary between pixels 3b and 3d as the inversion axis.

[0115] <Method of Manufacturing Solid-State Imaging Device> Next, a method of manufacturing a solid-state imaging device 1A according to the first embodiment of the present technology will be described with reference to FIGS. 6A to 13. FIGS. 6A (plan view) and 5B (longitudinal cross-sectional view taken along the a6-a6 cutting line in FIG. 6A) are diagrams schematically showing steps in the method of manufacturing a solid-state imaging device according to the first embodiment of the present technology. FIGS. 7A (plan view) and 7B (longitudinal cross-sectional view taken along the a7-a7 cutting line in FIG. 7A) are diagrams schematically showing steps subsequent to FIGS. 6A and 6B. FIGS. 8A (plan view) and 8B (longitudinal cross-sectional view taken along the a8-a8 cutting line in FIG. 8A) are diagrams schematically showing steps subsequent to FIGS. 7A and 7B. FIGS. 9A (plan view) and 9B (longitudinal cross-sectional view taken along the a9-a9 cutting line in FIG. 9A) are diagrams schematically showing steps subsequent to FIGS. 8A and 8B. 10A (plan view) and FIG. 10B (longitudinal cross-sectional view along the a10-a10 cutting line of FIG. 10A) are diagrams schematically showing steps subsequent to FIGS. 9A and 9B. FIG. 11A (plan view) and FIG. 11B (longitudinal cross-sectional view along the a11-a11 cutting line of FIG. 11A) are diagrams schematically showing steps subsequent to FIGS. 10A and 10B. FIG. 12A (plan view) and FIG. 12B (longitudinal cross-sectional view along the a12-a12 cutting line of FIG. 12A) are diagrams schematically showing steps subsequent to FIGS. 11A and 11B. FIG. 13 is a longitudinal cross-sectional view schematically showing steps subsequent to FIG. 12.

[0116] In this first embodiment, the description will be focused on the formation of the isolation region 31 and the pinning layer 33, which are included in the manufacturing method of the solid-state imaging device 1A. Also, Figures 6A to 13 illustrate a pixel block formation region 17 corresponding to one pixel block 15 shown in Figures 4A and 5A. Therefore, the pixel block formation region 17 includes four photoelectric conversion regions 22, each surrounded by a recessed portion formation region 37.

[0117] First, as shown in Figures 6A and 6B, a p-type well region 23 and an n-type semiconductor region 24 are formed in the semiconductor layer 21. The p-type well region 23 is formed over the entire region of the semiconductor layer 21, including the photoelectric conversion region 22 and the recessed portion formation region 37. The n-type semiconductor region 24 is selectively formed for each photoelectric conversion region 22. Figure 6A illustrates four photoelectric conversion regions 22 that have not yet been partitioned by recessed portions in one pixel block formation region 17. The four photoelectric conversion regions 22 are arranged in a 2x2 pattern, with two of each arranged in the X and Y directions. The p-type well region 23 and the n-type semiconductor region 24 can be formed using well-known photolithography techniques and impurity ion implantation methods.

[0118] In this process, n-type semiconductor region 24 is provided in p-type well region 23, and is surrounded on its top, bottom, and four side surfaces (six surfaces) by p-type well region 23. Furthermore, in this process, each photoelectric conversion region 22 has not yet been partitioned, and is virtually surrounded on its periphery by dug-out portion formation region 37, where first dug portion 32a (see FIGS. 7A and 7B) and second dug portion 35a (see FIGS. 10A and 10B) will be formed in a subsequent process. Dug-out portion formation region 37 is not physically formed, but is a region where first dug portion 32a and second dug portion 35a are formed during the manufacturing process, and is set in a grid-like planar pattern surrounding each photoelectric conversion region 22 in a plan view.

[0119] In the manufacture of the solid-state imaging device 1A of the first embodiment, a thinning step (thinning process) is carried out to reduce the thickness of the semiconductor layer 21 in the Z direction, as shown in Fig. 17, which will be described in detail later. In this thinning step, the semiconductor layer 21 is thinned to a thinning line S2a shown in Fig. 6B.

[0120] Next, the recessed portion formation region 37 is selectively etched to form first recessed portions 32a extending from the first surface S1 of the semiconductor layer 21 toward the second surface S2 thereof, as shown in FIG. 7A (plan view) and FIG. 7B (longitudinal cross-sectional view). The first recessed portions 32a are formed in a lattice-like planar pattern surrounding each photoelectric conversion region 22, following the planar pattern of the recessed portion formation region 37. The first recessed portions 32a can be formed by selectively etching the recessed portion formation region 37 of the semiconductor layer 21 using, for example, well-known photolithography and anisotropic dry etching techniques. The first recessed portions 32a are formed deeper than the thinning lines S2a that will be used to thin the thickness of the semiconductor layer 21 in the Z direction in the subsequent thinning step. In this step, each photoelectric conversion region 22 is surrounded by the first carved portion 32a and is partitioned into individual regions by the first carved portion 32a.

[0121] Next, as shown in FIGS. 8A and 8B , a pinning layer 33 is formed on the side surface of the semiconductor layer 21 around the first dug portion 32a to pin damage caused to the semiconductor layer 21 around the first dug portion 32a by the formation of the first dug portion 32a. The pinning layer 33 is formed by introducing impurities into the side surface of the semiconductor layer 21 around the first dug portion 32a from inside the first dug portion 32a. The pinning layer 33 is formed of a p-type semiconductor region having a higher impurity concentration than the p-type well region 23. The p-type pinning layer 33 can be formed by, for example, ion implantation, solid-phase diffusion, or plasma doping. In the case of ion implantation or plasma doping, for example, boron (B) or boron difluoride ions (BF ２A p-type impurity such as fluorine (B) or fluorine-containing silicon (Hf) is introduced from inside the first dug portion 32a into the side surface of the semiconductor layer 21 around the first dug portion 32a to form a p-type pinning layer 33, and then a heat treatment is performed to activate the introduced impurity. The heat treatment may be performed before the step of forming the second dug portion 35a, which will be described later, or may be performed after the step of forming the second dug portion 35a. The introduction of the impurity is performed in a state where the first surface S1 of the semiconductor layer 21, excluding the first dug portion 32a, is selectively covered (masked) with a mask such as a photoresist film or an inorganic film. In the case of solid-phase diffusion, for example, boron (B) or boron difluoride (BF ２ A solid-phase diffusion medium film doped (introduced) with a p-type impurity such as SiO 2 is formed in the first dug portion 32a, and then heat treatment is performed to diffuse the impurity from the solid-phase diffusion medium film from inside the first dug portion 32a into the side surface of the semiconductor layer 21 surrounding the first dug portion 32a, thereby forming the p-type pinning layer 33. The solid-phase diffusion medium film is formed, for example, while selectively covering the first surface S1 of the semiconductor layer 21, excluding the first dug portion 32a, with a mask such as a silicon oxide film or a silicon nitride film. The solid-phase diffusion medium film can be, for example, a polycrystalline silicon film doped with an impurity. Whether using ion implantation, plasma doping, or solid-phase diffusion, the p-type pinning layer 33 is formed in alignment with the first dug portion 32a. The p-type pinning layer 33 is then formed along the first dug portion 32a in the thickness direction (Z direction) of the semiconductor layer 21. In the first embodiment, the p-type pinning layer 33 is formed by, for example, plasma doping.

[0122] In this step, the pinning layer 33 is formed in alignment with the first carved portion 32a, and extends together with the first carved portion 32a from the first surface S1 toward the second surface S2 of the semiconductor layer 21. Also, in this step, damage caused to the semiconductor layer 21 around the first carved portion 32a by the formation of the first carved portion 32a can be pinned by the pinning layer 33.

[0123] Here, when forming the pinning layer 33 by introducing impurities into the side portions of the semiconductor layer 21 surrounding the first carved portion 32a from inside the first carved portion 32a, it is necessary to cover the first surface portion S1 side of the semiconductor layer 21 with an impurity introduction mask. However, since this is not affected by the constraints of the processing limits of this impurity introduction mask or misalignment of the impurity introduction mask, it is possible to form a pinning layer 33 having a narrow width in the short direction in a planar view (the width from the first carved portion 32a toward the photoelectric conversion region 22) from the first surface portion S1 to the second surface portion S2 side of the semiconductor layer 21. In contrast, when a pinning layer is formed by forming an impurity introduction mask on the first surface S1 side of the semiconductor layer 21 and introducing impurities into the semiconductor layer 21 outside the impurity introduction mask from outside the first surface S1 of the semiconductor layer 21, it is difficult to form a pinning layer that has a narrow width in the lateral direction in plan view from the first surface S1 to the second surface S2 side of the semiconductor layer 21 due to the influence of constraints such as the processing limit of the impurity introduction mask and misalignment of the impurity introduction mask. That is, the pinning layer 33 formed by introducing impurities into the side surface portions of the semiconductor layer 21 around the first carved portion 32a from inside the first carved portion 32a can have a narrower width in the lateral direction than a pinning layer formed by introducing impurities into the semiconductor layer 21 from the first surface S1 side of the semiconductor layer 21.

[0124] Next, as shown in FIGS. 9A and 9B , an isolation insulating film 32b is selectively formed inside the first carved portion 32a. The isolation insulating film 32b is formed so as to fill the first carved portion 32a. The isolation insulating film 32b inside the first carved portion 32a can be formed, for example, by depositing an insulating film on the entire surface of the first surface S1 side of the semiconductor layer 21, including the inside of the first carved portion 32a, and then selectively removing the insulating film outside the first surface S1 of the semiconductor layer 21 by a CMP method, an etch-back method, or the like, so that the insulating film selectively remains inside the first carved portion 32a. The insulating film can be, for example, a silicon oxide film. In this process, a first isolation region 32 is formed, including the first carved portion 32a and the isolation insulating film 32b and defining the photoelectric conversion region 22.

[0125] In addition, a metal film or a doped polysilicon film with impurities added to reduce the resistance value may be provided inside the first recessed portion 32a with an insulating film interposed therebetween, or a non-doped polysilicon film with no added resistance value may be provided.

[0126] 10A and 10B, a second dug portion 35a is selectively formed by selectively removing a portion of each of the first dug portion 32a and the pinning layer 33 on the first surface S1 side of the semiconductor layer 21. The second dug portion 35a can be formed by selectively etching the first isolation region 32 and the p-type pinning layer 33 of the semiconductor layer 21 using, for example, well-known photolithography and anisotropic dry etching techniques.

[0127] In this step, the second recessed portion 35a is formed at a position adjacent to the n-type floating diffusion region FD formed in a subsequent step in plan view. In this first embodiment, the n-type floating diffusion region FD is disposed around the intersections 31xy of the isolation regions 31, so the second recessed portion 35a is formed at the intersections of the first isolation regions 32, which are the intersections of the isolation regions 31.

[0128] Also, in this process, a p-type pinning layer 33 is formed, which includes a first portion 33a extending from the first surface S1 of the semiconductor layer 21 toward the second surface S2 together with the first isolation region 32 (first carved portion 32a), and a second portion 33b extending from the bottom of the second carved portion 35a toward the second surface S2 of the semiconductor layer 21 together with the first isolation region 32 (first carved portion 32a).

[0129] 11A and 11B , an isolation insulating film 35b is selectively formed inside the second carved portion 35a. The isolation insulating film 35b is formed so as to selectively fill the second carved portion 35a. The isolation insulating film 35b inside the second carved portion 35a can be formed, for example, by forming an insulating film over the entire surface of the first surface S1 of the semiconductor layer 21, including the inside of the second carved portion 35a, and then selectively removing the insulating film outside the first surface S1 of the semiconductor layer 21 by a CMP method, an etch-back method, or the like, so that the insulating film remains inside the second carved portion 35a. For example, a silicon oxide film can be used as the insulating film.

[0130] In this process, a second isolation region 35 is formed, which includes a second recessed portion 35a recessed from the first surface portion S1 of the semiconductor layer 21 toward the first isolation region 32 and an isolation insulating film 35b provided inside this second recessed portion 35a, and which selectively overlaps with a portion of the first isolation region 32 on the first surface portion S1 side of the semiconductor layer 21.

[0131] Also, in this process, an isolation region 31 is formed, which has a first isolation region 32 that surrounds the photoelectric conversion region 22 in a planar view, and a second isolation region 35 that is partially provided overlapping a part of the first isolation region 32 in a planar view.

[0132] Next, in each photoelectric conversion region 22, as shown in Figures 12A and 12B, an n-type floating diffusion region FD, a gate electrode 54, and a p-type power supply contact region WC are formed in the surface layer portion on the first surface portion S1 side of the semiconductor layer 21, and a pixel transistor Q is also formed.

[0133] The floating diffusion region FD is formed for each photoelectric conversion region 22 outside the intersection 31xy of the isolation region 31 in a central portion of the pixel block formation region 17 so as to surround the intersection 31xy of the isolation region 31 in a plan view, and is also formed in contact with the second isolation region 35 at the intersection 31xy of the isolation region 31. The floating diffusion region FD is formed so as to overlap the n-type semiconductor region 24 in a plan view, and to be spaced apart from each of the n-type semiconductor region 24 and the p-type pinning layer 33. The floating diffusion region FD is formed by introducing impurities exhibiting n-type conductivity, such as phosphorus ions (P＋ ) and arsenic ions (As ＋ The SiO 2 layer can be formed by selectively implanting impurity ions such as SiO 2 , and then performing a heat treatment to activate the implanted impurity ions.

[0134] The gate electrode 54 is formed for each photoelectric conversion region 22 outside the floating diffusion region FD in the center of the pixel block formation region 17 so as to surround the intersections 31xy of the isolation regions 31 in a plan view. The gate electrode 54 can be formed by forming a gate trench 52 extending from the first surface S1 side toward the second surface S2 side in a surface layer portion on the first surface S1 side of the semiconductor layer 21, then forming a gate insulating film 53 along the inner wall portions (sidewall portions and bottom wall portions) of the semiconductor layer 21 inside the gate trench 52, then forming a gate electrode film on the first surface S1 side of the semiconductor layer 21 so as to fill the inside of the gate trench 52 via the gate insulating film 53, and then patterning the gate electrode film. The gate electrode film can be, for example, a doped polysilicon film into which impurities that reduce resistance are introduced during or after deposition. The gate electrode 54 of the first embodiment has a head 54a provided outside the first surface S1 of the semiconductor layer 21 with the gate insulating film 53 interposed therebetween, and a body 54b that protrudes from the head 54a into the gate trench 52 of the semiconductor layer 21 and is adjacent to the semiconductor layer 21 with the gate insulating film 53 interposed therebetween. In the gate electrode 54 of the first embodiment, for example, the body 54b is narrower than the head 54a.

[0135] The p-type power supply contact region WC is formed outside the other intersections of the isolation regions 31 on the opposite side to the intersections 31xy in plan view in each of the four photoelectric conversion regions 22 included in one pixel block formation region 17. The p-type power supply contact region WC is formed spaced apart from the n-type semiconductor region 24 in the thickness direction (Z direction) of the semiconductor layer 21. The p-type power supply contact region WC is formed in contact with the first isolation region 32 in plan view, and is formed to overlap with and in contact with the p-type pinning layer 33 in plan view.

[0136] The p-type power supply contact region WC is formed by doping a p-type impurity, such as boron (B ＋ ) and boron difluoride (BF ２ ＋ The p-type power supply contact region WC is formed in the p-type well region 23 and is electrically connected to both the p-type well region 23 and the p-type pinning layer 33.

[0137] In this process, a vertical transfer transistor TR is formed, which has a gate trench 52, a gate insulating film 53, a gate electrode 54, an n-type semiconductor region 24 that functions as a source region and a drain region, and an n-type floating diffusion region FD, and which has a p-type well region 23 as a channel formation region.

[0138] Also, in this process, a photoelectric conversion region 22 is formed, which has a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion section 25, a p-type pinning layer 33, a p-type power supply contact region WC, an n-type floating diffusion region FD, and a transfer transistor RT, and is partitioned by an isolation region 31.

[0139] Furthermore, in this process, the second portion 33b of the p-type pinning layer 33, unlike the first portion 33a of the pinning layer 33, extends from the bottom of the second isolation region 35 toward the second surface portion S2 of the semiconductor layer 21 and terminates at the bottom of the second isolation region 35, so that an n-type floating diffusion region FD can be formed in the photoelectric conversion region 22 in contact with the second isolation region 35 in a planar view.

[0140] Next, an n-type floating diffusion region FD, a gate electrode 54, a p-type power supply contact region WC, pixel transistors (AMP, SEL, RST, FDG) Q, etc. are formed in the photoelectric conversion region 22, and then, although not shown, a multilayer wiring layer is formed on the first surface S1 side of the semiconductor layer 21.

[0141] Next, after forming the multilayer wiring layer, as shown in FIG. 13, a thinning process is carried out in which the second surface portion S2 side of the semiconductor layer 21 is cut up to the thinning line S2a by, for example, a CMP method to thin the thickness of the semiconductor layer 21.

[0142] In this process, a separation region 31 is formed that extends from the first surface S1 side of the semiconductor layer 21 along the thickness direction (Z direction) of the semiconductor layer 21 and reaches the second surface S2 of the semiconductor layer 21, and a photoelectric conversion region 22 partitioned by this separation region 31 is also formed.

[0143] Thereafter, a planarization film 61, an optical filter layer 63, and a lens layer 64 are formed in this order on the second surface S2 side of the semiconductor layer 21, resulting in the state shown in FIGS. 4A to 5B.

[0144] <Main Effects of First Embodiment> Next, main effects of the first embodiment will be described.

[0145] As described above, the solid-state imaging device 1A according to the first embodiment has the pinning layer 33 formed by introducing impurities from inside the first carved portion 32 a into the semiconductor layer 21 around the first carved portion 32 a. The pinning layer 33 includes a first portion 33 a that extends, together with the first isolation region 32, from the first surface S1 of the semiconductor layer 21 toward the second surface S2, and a second portion 33 b that extends, together with the first isolation region 32, from the bottom of the second isolation region 35 toward the second surface S2 of the semiconductor layer 21. According to the solid-state imaging device 1A having such a configuration, the pinning layer 33 formed by introducing impurities into the side portion of the semiconductor layer 21 surrounding the first carved portion 32a from inside the first carved portion 32a is not affected by constraints such as the processing limits of the impurity introduction mask or misalignment of the impurity introduction mask, compared to a pinning layer formed by introducing impurities into the semiconductor layer 21 from the first surface S1 side of the semiconductor layer 21, and therefore the width in the short direction (the width from the first carved portion 32a toward the photoelectric conversion region 22) can be narrowed from the first surface S1 to the second surface S2 side of the semiconductor layer 21. Furthermore, when the pinning layer 33 is formed by introducing impurities from inside the first carved portion 32 a into the side surface portion of the semiconductor layer 21 around the first carved portion 32 a, it is not necessary to diffuse the impurities from the first surface portion S1 toward the second surface portion S2 of the semiconductor layer 21, compared to when the pinning layer 33 is formed by introducing impurities into the semiconductor layer 21 from the first surface portion S1 side of the semiconductor layer 21. This makes it possible to narrow the width in the lateral direction of the pinning layer 33. This makes it possible to increase the element arrangement area on the first surface portion S1 of the photoelectric conversion region 22 in which elements such as the floating diffusion region FD, the transfer transistor TR, and the pixel transistor Q included in the pixel circuit 16 can be arranged. Therefore, according to the solid-state imaging device 1A according to the first embodiment of the present technology, it is possible to increase the degree of freedom in arranging elements on the first surface portion S1 of the photoelectric conversion region 22.

[0146] In addition, a second isolation region 35 having a width in the short side direction wider than the width in the short side direction of the first isolation region 32 is selectively provided, so that in this respect too, the element placement area on the first surface portion S1 of the photoelectric conversion region 22 can be increased.

[0147] Furthermore, since the second portion 33b of the pinning layer 33 terminates at the bottom of the second isolation region 35 together with the first isolation region 32, a floating diffusion region FD can be provided in contact with the second isolation region 35 in plan view. In this first embodiment, the second isolation region 35 is provided at the intersection 31xy of the isolation region 31, so that the floating diffusion region FD can be provided outside the intersection of the isolation region 31 in contact with the second isolation region 35.

[0148] In addition, the manufacturing method of the solid-state imaging device according to the first embodiment includes the steps of forming a first carved portion 32a extending from the first surface S1 of the semiconductor layer 21 toward the second surface S2, introducing impurities into the semiconductor layer 21 around the first carved portion 32a from inside the first carved portion 32a to form a pinning layer 33 on the side of the semiconductor layer 21, extending from the first surface S1 of the semiconductor layer 21 toward the second surface S2, and selectively removing each of the first carved portion 32a and the pinning layer 33 on the first surface S1 side of the semiconductor layer 21 to form a second carved portion 35a whose width in the short direction is wider than the width of the first carved portion 32a in a planar view.

[0149] According to the manufacturing method of the solid-state imaging device 1A including such a process, it is possible to form a pinning layer 33 having a first portion 33a having a narrow width in the short direction (the width from the first recessed portion 32a toward the photoelectric conversion region) extending from the first surface portion S1 of the semiconductor layer 21 toward the second surface portion S2, and a second portion 33b extending from the bottom of the second recessed portion 35a toward the second surface portion S2 of the semiconductor layer 21.

[0150] Furthermore, since the pinning layer 33 can be selectively formed in the first surface S1 of the photoelectric conversion region 22 by introducing impurities in a single process, it is not necessary to selectively form the pinning layer (a deep first pinning portion and a shallow second pinning portion) in two separate processes as in the conventional method. This reduces the number of processes and enables the cost of the solid-state imaging device 1A to be reduced.

[0151] Furthermore, in conventional manufacturing, the deep recessed portion is formed by etching the bottom of the shallow recessed portion. Therefore, in order to surround the periphery of the photoelectric conversion region 22 with the isolation region 31, it is necessary to surround the periphery of the photoelectric conversion region 22 with a shallow recessed portion whose width in the short side direction is wider than the width of the deep recessed portion in a plan view, which reduces the element arrangement area on the first surface S1 of the photoelectric conversion region 22. In contrast, in the first embodiment, first dug portion 32a extending from first surface S1 toward second surface S2 of semiconductor layer 21 is formed, and then pinning layer 33 extending from first surface S1 toward second surface S2 of semiconductor layer 21 is formed. Then, first dug portion 32a and pinning layer 33 are selectively removed on the first surface S1 side of semiconductor layer 21 to form second dug portion 35a whose width in the lateral direction is wider than that of first dug portion 32a in plan view. Therefore, first dug portion 32a can surround photoelectric conversion region 22 without second dug portion 35a surrounding photoelectric conversion region 22. This increases the element placement area on first surface S1 of photoelectric conversion region 22 compared to the conventional method in which the pinning layer is formed in two stages.

[0152] That is, in the conventional technique, the shallow dug portion is formed first, and then the deep dug portion is formed. In contrast, in the present technique, the first dug portion 32a (deep dug portion) is formed first, and then the second dug portion 35a (shallow dug portion) is formed. Therefore, there is no need to form the second dug portion 35a, which has a wide width in the short direction in plan view, so as to surround the periphery of the photoelectric conversion region 22. This makes it possible to increase the element arrangement area on the first surface S1 of the photoelectric conversion region 22.

[0153] <<Variations of the First Embodiment>> <Variation 1-1>> In the above-described first embodiment, the case where the pinning layer 33 is formed by a plasma doping method has been described. However, in this variation 1-1, the case where the pinning layer 33 is formed by a solid-phase diffusion method will be described with reference to FIGS. 14A to 14D.

[0154] Fig. 14A is a longitudinal sectional view schematically showing a step of a manufacturing method according to Modification 1-1 of the first embodiment of the present technology. Fig. 14B is a longitudinal sectional view schematically showing a step subsequent to Fig. 14A. Fig. 14C is a longitudinal sectional view schematically showing a step subsequent to Fig. 14B. Fig. 14D is a longitudinal sectional view schematically showing a step subsequent to Fig. 14C.

[0155] First, as shown in FIG. 14A, a first recessed portion 32a extending from the first surface portion S1 of the semiconductor layer 21 toward the second surface portion S2 is formed in a recessed portion formation region 37 of the semiconductor layer 21 using a method similar to that of the first embodiment described above.

[0156] 14B, a solid-phase diffusion medium film 38 is selectively formed inside the first recessed portion 32a. The solid-phase diffusion medium film 38 may be made of, for example, boron (B) or boron difluoride (BF ２ A polycrystalline silicon film doped (introduced) with a p-type impurity such as SiO 2 can be used.

[0157] The solid-phase diffusion medium film 38 inside the first recessed portion 32a can be formed, for example, by depositing a solid-phase diffusion medium film on the entire surface of the first surface portion S1 of the semiconductor layer 21, including the inside of the first recessed portion 32a, and then selectively removing the solid-phase diffusion medium film outside the first surface portion S1 of the semiconductor layer 21 by a CMP method, an etch-back method, or the like, so that the solid-phase diffusion medium film selectively remains inside the first recessed portion 32a.

[0158] Next, a heat treatment is performed to introduce impurities from the solid-phase diffusion medium film 38 by diffusion from the inside of the first dug portion 32a into the side surface of the semiconductor layer 21, and as shown in Fig. 14C, a p-type pinning layer 33 is formed on the side surface of the semiconductor layer 21 around the first dug portion 32a. The p-type pinning layer 33 is formed in alignment with the first dug portion 32a and extends from the first surface S1 of the semiconductor layer 21 toward the second surface S2.

[0159] Next, the solid-phase diffusion medium film 38 inside the first dug portion 32a is selectively removed, and then, as shown in FIG. 14D , an isolation insulating film 32b is selectively formed inside the first dug portion 32a. The isolation insulating film 32b can be formed by a method similar to that of the first embodiment. In this process, a first isolation region 32 is formed, which includes the first dug portion 32a and the isolation insulating film 32b and defines the photoelectric conversion region 22.

[0160] Thereafter, the second isolation region 35 is formed in the same manner as in the first embodiment.

[0161] The present technology can be applied to this modified example 1-1 as well, and the same effects as those of the first embodiment described above can be obtained.

[0162] 15A is a plan view schematically illustrating one pixel block according to Modification 1-2 of the first embodiment of the present technology, and Fig. 15B is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the a15-a15 cutting line in Fig. 15A.

[0163] 15A and 15B, in this modification 1-2, a floating diffusion region FD is provided in the second isolation region 35 at the intersection 31xy. The other configurations are generally similar to those of the first embodiment.

[0164] 15A and 15B , the floating diffusion region FD of this modification 1-2 is provided in a second isolation region 35 located at a central intersection 31xy of one pixel block 15, and is shared by four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15. The floating diffusion region FD of this modification 1-2 overlaps with the first isolation region 32 and the p-type pinning layer 33 via an isolation insulating film 35b of the second isolation region 35 in a plan view, and is insulated and isolated from the p-type pinning layer 33. The floating diffusion region FD of this modification 1-2 contacts the p-type well region 23 of each photoelectric conversion region 22 at the side portion of the photoelectric conversion region 22 of each of the four pixels 3 (3a, 3b, 3c, 3d) included in one pixel block 15, and is electrically and mechanically connected to the p-type well region 23. That is, the floating diffusion region FD of this modified example 1-2 is provided in the second isolation region 35 adjacent to the side surface portion of the photoelectric conversion region 22. The floating diffusion region FD of this modified example 1-2 is made of, for example, a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced, and is made of n-type conductivity, which is the same conductivity type as the p-type well region 23.

[0165] The present technology can also be applied to this modified example 1-2, and the same effects as those of the first embodiment described above can be obtained.

[0166] 16A is a plan view schematically illustrating one pixel block according to Modification 1-3 of the first embodiment of the present technology, and Fig. 16B is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the a16-a16 cutting line in Fig. 16A.

[0167] 16A and 16B, in this modification 1-3, a transfer transistor TRL having a horizontal structure is provided instead of the transfer transistor TR having a vertical structure shown in FIGS. 4A to 5B of the first embodiment. The other configurations are generally similar to those of the first embodiment.

[0168] 16A and 16B , a transfer transistor TRL having a lateral structure is provided on the first surface S1 side of the semiconductor layer 21 in the photoelectric conversion region 22. The transfer transistor TRL has a gate electrode 59 provided outside the first surface S1 of the semiconductor layer 21 and a gate insulating film 53 provided between the gate electrode 59 and the semiconductor layer 21. The transfer transistor TRL also has a p-type well region 23 functioning as a channel formation region, and an n-type semiconductor region 24 and an n-type floating diffusion region FD functioning as a source region and a drain region. Unlike the transfer transistor TR of the first embodiment described above, this transfer transistor TRL is configured as a planar type in which the gate electrode 59 is disposed only outside the first surface S1 of the semiconductor layer 21.

[0169] The horizontally structured transfer transistors RTL of each of the four photoelectric conversion regions 22 (four pixels 3a, 3b, 3c, and 3d) included in one pixel block 15 are provided biased toward the intersection 31xy of the isolation region 31 in plan view, similar to the vertically structured transfer transistors TR of the first embodiment described above. The gate electrodes 59 of the transfer transistors TRL of each of the four photoelectric conversion regions 22 are provided outside the n-type floating diffusion region FD so as to surround the intersection 31xy of the isolation region 31 in plan view.

[0170] The present technology can also be applied to this modified example 1-3, and the same effects as those of the first embodiment described above can be obtained.

[0171] 17A is a plan view schematically illustrating one pixel block according to Modification 1-4 of the first embodiment of the present technology, and Fig. 17B is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the a17-a17 cutting line in Fig. 17A.

[0172] As shown in FIGS. 17A and 17B , this modification 1-4 differs in the configuration of the isolation region 31. The remaining configuration is generally similar to that of the first embodiment. That is, the isolation region 31 of this modification 1-4 includes a first isolation region 32 and a second isolation region 35, as well as a third isolation region 41. The third isolation region 41 is formed such that its width in the short-side direction in a plan view is wider than the width of the first carved portion 32a, its depth along the thickness direction (Z direction) of the semiconductor layer 21 as one direction is shallower than the depth of the second carved portion 35a, and includes a third carved portion 41a formed by selectively removing a portion of each of the first carved portion 32a and the pinning layer 33 on the first surface S1 side of the semiconductor layer 21. Furthermore, the third isolation region 41 of this modification 1-4 further includes an isolation insulating film 41b provided inside the third carved portion 41a. The third dug portion 41 a may be formed after the formation of the first isolation region 32 and before or after the formation of the second dug portion 35 a. The isolation insulating film 41 b may be formed in the same process as the isolation insulating film 35 b of the second isolation region 35, or may be formed in a separate process.

[0173] In this modification 1-4, the width in the lateral direction of the third dug portion 41a is equal to the width W １ and the width of each of the pinning layers 33 located on both sides of the first dug portion 32 a in the short direction. Therefore, the third isolation region 41 protrudes toward the photoelectric conversion region 22 beyond the p-type pinning layer 33.

[0174] In addition, in this modification 1-4, the pinning layer 33 includes a third portion that extends from the bottom of the third isolation region 41 toward the second surface S2 side of the semiconductor layer 21 together with the first isolation region 32.

[0175] 17A and 17B, this modification 1-4 further includes a relay electrode 42 provided on the outside of the first surface portion S1 of the semiconductor layer 21. The relay electrode 42 overlaps with each of the third isolation region 41 and the power supply contact region WC in a plan view, and is electrically and mechanically connected to the power supply contact region WC. That is, the relay electrode 42 is provided across each of the third isolation region 41 and the power supply contact region WC.

[0176] Although not shown, the relay electrode 42 is electrically connected to wiring in an upper multilayer wiring layer. The relay electrode 42 has a fixed potential at a first reference potential (Vss potential) of, for example, 0 V, which is supplied via wiring when the solid-state imaging device 1A is in operation. The relay electrode 42 may be formed, for example, from a polycrystalline silicon film (doped polysilicon film) doped with impurities that reduce the resistance value.

[0177] The present technology can also be applied to this modified example 1-4, and the same effects as those of the first embodiment described above can be obtained.

[0178] <Modification 1-5> FIG. 18 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-5 according to the first embodiment of the present technology.

[0179] As shown in FIG. 18 , Modification 1-5 differs in the configuration of the isolation region 31. The remaining configuration is generally similar to that of the first embodiment. That is, the isolation region 31 of Modification 1-5 includes a first isolation region 32 and a second isolation region 35, as well as a third isolation region 43. The third isolation region 43 has a width in the lateral direction, in plan view, that is wider than the width of the first dug portion 32a and narrower than the width of the second dug portion 35a, and includes a third dug portion 43a formed by selectively removing a portion of each of the first dug portion 32a and the pinning layer 33 on the first surface S1 side of the semiconductor layer 21. Furthermore, the third isolation region 43 of Modification 1-5 further includes an isolation insulating film 43b provided inside the third dug portion 43a. The third dug portion 43a may be formed after the first isolation region 32 is formed and before or after the second dug portion 35a is formed. The third dug portion 43a may be formed in the same process as the second dug portion 35a. The isolation insulating film 43b may be formed in the same process as the isolation insulating film 35b of the second isolation region 35, or may be formed in a separate process.

[0180] In this modified example 1-5, the width in the lateral direction of the third dug portion 43a is equal to the width W １ and the width of each of the pinning layers 33 located on both sides of the first carved portion 32 a in the short direction. Therefore, a p-type pinning layer 33 is provided on the semiconductor layer 21 side of the interface Lp between the third isolation region 43 and the semiconductor layer 21.

[0181] The pinning layer 33 of this variant 1-5 extends from the first surface S1 of the semiconductor layer 21 toward the second surface S2, even in the third portion including the first isolation region 32 and the third isolation region 41 of the isolation region 31.

[0182] The present technology can also be applied to this modified example 1-5, and the same effects as those of the first embodiment described above can be obtained.

[0183] <Modification 1-6> FIG. 19 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-6 according to the first embodiment of the present technology.

[0184] As shown in FIG. 19 , in this modification 1-6, the third isolation region 43 shown in the above-described modification 1-5 is provided biased toward one of both sides in the short side direction of the first isolation region 32. Therefore, the pinning layer 33 of this modification 1-6 extends from the first surface S1 of the semiconductor layer 21 toward the second surface S2 on one of both sides in the short side direction of the third isolation region 43. Then, the pinning layer 33 of this modification 1-6 extends from the bottom of the third isolation region 43 toward the second surface S2 of the semiconductor layer 21 on the other side of both sides in the short side direction of the third isolation region 43, and terminates at the bottom of the third isolation region 43 together with the first isolation region 32. In this modification 1-6, in FIG. 19 , the third isolation region 43 is offset toward the transfer transistor Q.

[0185] The present technology can also be applied to this modified example 1-6, and the same effects as those of the first embodiment described above can be obtained.

[0186] <Modification 1-7> Fig. 20 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure of Modification 1-7 according to the first embodiment of the present technology. As shown in Fig. 20, Modification 1-7 has the third isolation region 43 provided on the opposite side to that of Modification 1-6. In Modification 1-7, the third isolation region 43 is offset to the side opposite the transfer transistor Q side in Fig. 20.

[0187] The present technology can also be applied to this modified example 1-7, and the same effects as those of the first embodiment described above can be obtained.

[0188] <Modification 1-8> FIG. 21 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure of Modification 1-8 according to the first embodiment of the present disclosure. As shown in FIG. 21 , Modification 1-8 further includes an inter-element isolation region 44 that partitions the element formation region on the first surface S1 side of the photoelectric conversion region 22 (semiconductor layer 21). Other configurations are generally similar to those of the first embodiment. The inter-element isolation region 44 can be formed by forming a shallow recess in the first surface S1 of the semiconductor layer 21 in the photoelectric conversion region 22 and then selectively embedding an isolation insulating film within the shallow recess. A pixel transistor Q is provided in the element formation region partitioned by the inter-element isolation region 44. The second isolation region 35 may be formed in the same process as the inter-element isolation region 44, or may be formed in a separate process from the inter-element isolation region 44.

[0189] The present technology can also be applied to this modified example 1-8, and the same effects as those of the first embodiment can be obtained. Furthermore, when the second isolation region 35 and the inter-element isolation region 44 are formed in the same process, the number of processes can be reduced.

[0190] <Modification 1-9> FIG. 22 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure of Modification 1-9 according to the first embodiment of the present technology. As shown in FIG. 22, Modification 1-9 is configured such that the inter-element isolation region 44 shown in Modification 1-8 described above overlaps with the first isolation region 32 in a plan view. The present technology can also be applied to Modification 1-9, and the same effects as those of the first embodiment described above can be obtained. Furthermore, since the gate width of the pixel transistor Q can be defined by the inter-element isolation region 44, variations in the gate width of the pixel transistor Q can be suppressed. Note that the pixel transistor Q shown in FIG. 21 is not shown in FIG. 22.

[0191] <Modification 1-10> FIG. 23 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-10 according to the first embodiment of the present technology.

[0192] 19, in this modification 1-10, the inter-element isolation region 44 of the above-described modification 1-9 is formed by a dug portion of a different depth. The shallower dug portion side of the inter-element isolation region 44 is on the transfer transistor TR side.

[0193] The present technology can also be applied to this modified example 1-10, and the same effects as those of the first embodiment described above can be obtained.

[0194] <Modification 1-11> FIG. 24 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-11 according to the first embodiment of the present technology.

[0195] 24, in this modification 1-11, the inter-element isolation region 44 of the above-mentioned modification 1-9 is formed by a dug portion having a different depth. The deeper dug portion side of the inter-element isolation region 44 is on the transfer transistor TR side.

[0196] The present technology can also be applied to this modified example 1-11, and the same effects as those of the first embodiment described above can be obtained.

[0197] <Modification 1-12> FIG. 25 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-12 according to the first embodiment of the present technology.

[0198] 25, this modified example 1-12 differs in the configuration of the first isolation region 32. The other configurations are generally similar to those of the above-described embodiment.

[0199] The first isolation region 32 of this modification 1-12 includes a first dug portion 32a, an isolation insulating film 32b provided along the inner wall of the first dug portion 32a, and a conductive film 32c provided inside the first dug portion 32a with the isolation insulating film 32b interposed therebetween. The conductive film 32c may be, for example, a high-melting-point metal film such as a tungsten film or a titanium film, or a polycrystalline silicon film (doped polysilicon film) doped with impurities that reduce resistance. In this case, the conductive film 32c can be used as an electrode.

[0200] The present technology can also be applied to this modified example 1-12, and the same effects as those of the first embodiment described above can be obtained.

[0201] <Modification 1-13> FIG. 26 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-13 according to the first embodiment of the present technology.

[0202] 26, this modification 1-13 differs in the configuration of the pinning layer 33. The other configurations are generally similar to those of the first embodiment described above.

[0203] That is, the pinning layer 33 of this modification 1-13 has an impurity concentration that increases (becomes denser) in a stepwise manner from the first surface portion S1 side of the semiconductor layer 21 to the second surface portion S2 side. The pinning layer 33 of this modification 1-13 includes, but is not limited to, three impurity regions with stepwise different impurity concentrations. Specifically, the pinning layer 33 includes a first impurity region 34a extending from the first surface portion S1 toward the second surface portion S2 side of the semiconductor layer 21, a second impurity region 34b extending from the first impurity region 34a toward the second surface portion S2 side of the semiconductor layer 21, and a third impurity region 34c extending from the second impurity region 34b toward the second surface portion S2 side of the semiconductor layer 21. This stepwise impurity concentration configuration is implemented in each of the first portion 33a and the second portion 33b of the pinning layer 33.

[0204] The pinning layer 33 of this modification 1-13 can be easily formed by gradually increasing the Z-direction depth of the first dug portion 32a from the first face S1 side toward the second face S2 side of the semiconductor layer 21. In this case, the width of the first dug portion 32a in the short direction in a plan view gradually narrows from the first face S1 side toward the second face S2 side of the semiconductor layer 21. In any of the first to third impurity regions (34a, 34b, 34c), impurities can be introduced from inside the first dug portion 32a into the side surface portion of the semiconductor layer 21 around the first dug portion 32a, thereby forming the pinning layer 33 that pins damage caused in the semiconductor layer 21 around the first dug portion 32a by the formation of the first dug portion 32a.

[0205] The present technology can also be applied to this modified example 1-13, and the same effects as those of the first embodiment described above can be obtained.

[0206] Furthermore, since the pinning layer 33 of this variant 1-13 has a lower impurity concentration on the first surface S1 side of the semiconductor layer 21, the transfer capability of the transfer transistor TR provided on the first surface S1 of the semiconductor layer 21 can be improved.

[0207] In this modification 1-13, the pinning layer 33 is described as being composed of three impurity regions with different impurity concentrations, but the pinning layer 33 may be composed of three or more impurity regions with different impurity concentrations, or may be composed of two impurity regions with different impurity concentrations. However, in either case, it goes without saying that the impurity regions with different impurity concentrations are arranged so that the impurity concentration increases stepwise from the first surface S1 side to the second surface S2 side of the semiconductor layer 21.

[0208] <Modification 1-14> FIG. 27 is a plan view schematically showing one pixel block, illustrating Modification 1-14 according to the first embodiment of the present technology.

[0209] As shown in Fig. 4, the separation region 31 of the first embodiment described above is configured in a ring shape that continuously surrounds the photoelectric conversion region 22 in a planar view. In contrast, as shown in Fig. 27, the separation region 31 of this modified example 1-14 is configured to surround the photoelectric conversion region 22 in a planar view and to have interruptions 46 provided in places. In other words, the separation region 31 of this modified example 1-14 is configured such that the continuity surrounding the photoelectric conversion region 22 in a planar view is interrupted by the interruptions 46. In Fig. 27, as an example, two interruptions 46 are provided per pixel 3, but the number of interruptions 46 is not limited to two.

[0210] The present technology can also be applied to this modified example 1-14, and the same effects as those of the first embodiment described above can be obtained.

[0211] Second Embodiment Fig. 28 is a plan view schematically showing a configuration example of a pixel block in a solid-state imaging device according to a second embodiment of the present technology. Fig. 29A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a28-a28 cutting line in Fig. 28. Fig. 29B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b28-b28 cutting line in Fig. 28. Note that Fig. 28 omits the pixel transistor Q shown in Fig. 4A of the first embodiment. Also, Fig. 29B omits the relay electrode 42 shown in Fig. 28.

[0212] A solid-state imaging device 1B according to a second embodiment of the present technology has a configuration basically similar to that of the first embodiment described above, but differs in the configuration of the isolation region 31 and in the arrangement of elements such as the second isolation region 35, the transfer transistor TR, and the p-type power supply contact region WC. The solid-state imaging device 1B of the second embodiment also includes the relay electrode 42 shown in FIGS. 17A and 17B of the above-described modified example 1-4. The other configurations are generally similar to those of the first embodiment described above.

[0213] 28 and 29A , the isolation region 31 of the second embodiment has a first isolation region 32 and a second isolation region 35, and further has a third isolation region 47. The third isolation region 47 is provided at an intersection 31xy of the isolation region 31. The gate electrodes 54 of the transfer transistors TR of each of the four pixels 3 (3a, 3b, 3c, and 3d) are provided in the third isolation region 47.

[0214] The third isolation region 47 has a width in a plan view wider than the width of the first dug portion 32a in the short direction, a depth in one direction (Z direction) of the semiconductor layer 21 that is deeper than the depth of the second dug portion 35a, and includes a third dug portion 47a formed by selectively removing a portion of the first dug portion 32a and the pinning layer 33 on the first surface S1 side of the semiconductor layer 21. The third isolation region 47 also includes an isolation insulating film 47b provided inside the third dug portion 47a. The third isolation region 47 may be formed after the formation of the first isolation region 32 and before or after the formation of the second dug portion 35a. The isolation insulating film 47b may be formed in the same process as the isolation insulating film 35b of the second isolation region 35, or may be formed in a separate process.

[0215] 28 and 29A , the second isolation region 35 of the second embodiment is provided outside another intersection on the opposite side of the intersection 31xy of the isolation region 31 located in the center of the pixel block 15 in a plan view. The power supply contact region WC and the relay electrode 42 of the second embodiment are each provided at another intersection adjacent to and spaced apart from the intersection 31xy of the isolation region 31 in the X direction.

[0216] The present technology can also be applied to the solid-state imaging device 1B according to the second embodiment, and the same effects as those of the first embodiment can be obtained. In addition, in the second embodiment, the gate electrodes 54 of the transfer transistors TR of the four pixels 3 (3 a, 3 b, 3 c, and 3 d) are provided in the third isolation region 47, which allows for greater freedom in the arrangement of elements in the photoelectric conversion region 22 than in the first embodiment.

[0217] <Modification of Second Embodiment> <Modification 2-1> Fig. 30 is a plan view schematically showing a configuration example of a pixel block according to Modification 2-1 of the second embodiment of the present technology. Fig. 31A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a30-a30 cutting line in Fig. 30. Fig. 31B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b30-b30 cutting line in Fig. 30.

[0218] As shown in FIGS. 30 to 31B , in this modification 2-1, one transfer transistor TR is shared by four pixels 3 (3 a, 3 a, 3 c, 3 d) included in one pixel block 15. That is, in the second embodiment described above, four transfer transistors TR are provided in the third isolation region 47. In contrast, in this modification 2-1, one transfer transistor TR shared by the four pixels 3 (3 a, 3 a, 3 c, 3 d) is provided in the third isolation region 47. The present technology can also be applied to this modification 2-1, and the same effects as those of the second embodiment described above can be obtained. Furthermore, in this modification 2-1, one transfer transistor TR shared by the four pixels 3 (3 a, 3 a, 3 c, 3 d) is provided in the third isolation region 47, so the area occupied by the third isolation region 47 can be made smaller than that of the third isolation region 47 in the second embodiment described above.

[0219] <Modification 2-2> Fig. 32 is a plan view schematically showing one configuration example of a pixel block according to Modification 2-2 of the second embodiment of the present technology. Fig. 33A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a32-a32 cutting line in Fig. 32. Fig. 33B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b32-b32 cutting line in Fig. 32.

[0220] 32 to 33B, in this modification 2-2, the isolation region 31 further includes a third isolation region 47X. The third isolation region 47X is provided at another intersection adjacent to and spaced from the intersection 31xy of the isolation region 31 in the X direction, so as to surround the periphery of the power supply contact region WC. The third isolation region 47X is configured as a ring-shaped planar pattern in plan view, and the power supply contact region WC is provided in the center of this ring-shaped planar pattern.

[0221] The third isolation region 47X is a third carved portion 47X formed by selectively removing a portion of each of the first carved portion 32a, the pinning layer 33, and the semiconductor layer 21 on the first surface S1 side of the semiconductor layer 21. １ The third isolation region 47X includes a third recessed portion 47X １ The isolation insulating film 47X provided inside ２The third recessed portion 47X １ The formation of the second dug portion 35a and the third dug portion 47X is carried out after the first isolation region 32 is formed. １ The insulating film 47X may be formed before or after the insulating film 47X is formed. ２ may be formed in the same step as the isolation insulating film 35b of the second isolation region 35, or may be formed in a separate step.

[0222] The present technology can also be applied to this modified example 2-2, and the same effects as those of the second embodiment described above can be obtained.

[0223] <Modification 2-3> Fig. 34 is a plan view schematically showing one configuration example of a pixel block according to Modification 2-3 of the first embodiment of the present technology. Fig. 35A is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a34-a34 cutting line in Fig. 34. Fig. 35B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the b34-b34 cutting line in Fig. 34.

[0224] 34 to 35B, this modification 2-3 is a combination of the above-described modification 2-1 and the third isolation region 47X of the above-described modification 2-3. The present technology can also be applied to this modification 2-3, and the same effects as those of the above-described second embodiment can be obtained.

[0225] [Third Embodiment] In this third embodiment, an example in which the present technology is applied to a stacked-type photodetector in which semiconductor layers are stacked in multiple stages, for example, a two-stage stacked solid-state imaging device in which two semiconductor layers are stacked in two stages, will be described. Fig. 36A is a plan view schematically showing a configuration example of one pixel block in a solid-state imaging device according to a third embodiment of the present technology. Fig. 36B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a36-a36 cutting line in Fig. 36A. Note that Fig. 36A omits illustration of layers above the gate electrode shown in Fig. 36B.

[0226] As shown in Figures 36A and 36B, the solid-state imaging device 1C of the third embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1A of the first embodiment described above, with the following differences in configuration.

[0227] 36A and 36B , the solid-state imaging device 1C according to the third embodiment further includes a semiconductor layer 81 provided on the first surface S1 side of the semiconductor layer 21 with an insulating layer 71 interposed therebetween, and an insulating layer 91 provided on the side of the semiconductor layer 81 opposite the insulating layer 71 side. Unlike the first embodiment described above, the solid-state imaging device 1C according to the third embodiment includes a pixel transistor Q included in the pixel circuit 16 (see FIG. 3 ) provided in the semiconductor layer 81. In FIG. 36B , an amplification transistor AMP is illustrated as an example of the pixel transistor Q.

[0228] 36A and 36B , the photoelectric conversion unit 25, the transfer transistor TR, and the floating diffusion region FD are each provided on a side of the semiconductor layer 21 that is different from the semiconductor layer 81. The solid-state imaging device 1C of the third embodiment has the semiconductor layer 21 and the semiconductor layer 81 stacked with an insulating layer 71 interposed therebetween in the thickness direction (Z direction) of the semiconductor layer 21, which is one direction.

[0229] In the third embodiment, the semiconductor layer 21 corresponds to a specific example of a "first semiconductor layer" in the present technology, and the semiconductor layer 81 corresponds to a specific example of a "second semiconductor layer" in the present technology.

[0230] 36B , the solid-state imaging device 1C according to the third embodiment further includes a conductive path 95 that electrically connects the floating diffusion region FD provided on the semiconductor layer 21 side to the amplification transistor AMP provided in the semiconductor layer 81. The solid-state imaging device 1C according to the third embodiment further includes a relay conductive pad 45 that is provided on the first surface S1 side of the semiconductor layer 21 across the photoelectric conversion region 22 and the isolation region 31 and is electrically connected to the floating diffusion region FD of the photoelectric conversion region 22.

[0231] The conductive path 95 includes a relay conductive pad 45 that is provided across the photoelectric conversion region 22 and the isolation region 31 on the first surface portion S1 side of the semiconductor layer 21 and is electrically connected to the floating diffusion region FD of the photoelectric conversion region 22, and a through contact electrode 92 that extends from the insulating layer 91 to the relay conductive pad 45 in the stacking direction (Z direction) of the semiconductor layer 21 and the semiconductor layer 81 and is connected to the relay conductive pad 45. The conductive path 95 also includes a contact electrode 93 that is embedded in the insulating layer 91 and is connected to the gate electrode 56 of the amplification transistor AMP, and a wiring 94 that is provided on the side of the insulating layer 91 opposite to the semiconductor layer 81 side and is electrically and mechanically connected to each of the through contact electrode 92 and the contact electrode 93.

[0232] The wiring 94 may be formed of, for example, a metal film such as aluminum (Al) or copper (Cu), or an alloy film mainly containing Al or Cu. The insulating layer 91 may be formed of, for example, a silicon oxide film. The insulating layer 71 includes, for example, two insulating films 73 and 75. These two insulating films 73 and 75 may be formed of, for example, silicon oxide films. The semiconductor layer 81 may be formed of, for example, a Si substrate, a SiGe substrate, or an InGaAs substrate. In the second embodiment, the semiconductor layer 81 is formed of, for example, a p-type semiconductor substrate made of single crystal silicon, although this is not limited thereto.

[0233] The through contact electrode 92 is electrically insulated and separated from the semiconductor layer 81. For example, a high-melting-point metal film such as titanium (Ti) or tungsten (W) can be used for the through contact electrode 92 and the contact electrode 93. For example, a polycrystalline silicon film doped with an impurity that reduces the resistance value can be used for the relay conductive pad 45.

[0234] The solid-state imaging device 1C according to the third embodiment also provides the same effects as the solid-state imaging device 1A according to the first embodiment described above. That is, the present technology can also be applied to a two-stage stacked solid-state imaging device 1C in which two semiconductor layers 21 and 81 are stacked in two stages.

[0235] Although not shown, the present technology can also be applied to a multi-layer stacked solid-state imaging device in which three or more semiconductor layers are stacked in multiple stages.

[0236] [Fourth Embodiment] In this fourth embodiment, an example in which the present technology is applied to a solid-state imaging device including phase difference pixels will be described. Fig. 37 is a plan view schematically showing an example of a configuration of a pixel in a solid-state imaging device according to the fourth embodiment of the present technology. Fig. 38A is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the a37-a37 cutting line in Fig. 37A. Fig. 38B is a longitudinal sectional view schematically showing a longitudinal sectional structure taken along the b37-b37 cutting line in Fig. 37B.

[0237] A solid-state imaging device 1D according to a fourth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the first embodiment described above, except for the configuration of the pixel 3 and the location of the second isolation region 35. The other configurations are generally similar to those of the first embodiment described above. That is, as shown in FIGS. 4A to 5B , the pixel 3 according to the first embodiment described above is configured such that one photoelectric conversion unit 25 (PD) is provided in one photoelectric conversion region 22. In contrast, as shown in FIGS. 37 to 38B , the pixel 3 according to the fourth embodiment is configured as a phase difference pixel that detects a phase difference between two photoelectric conversion units 25 provided in one photoelectric conversion region 22. The present technology can also be applied to a solid-state imaging device 1D including such a phase difference pixel.

[0238] 37 to 38B , the photoelectric conversion region 22 of the fourth embodiment includes a first photoelectric conversion cell 22L and a second photoelectric conversion cell 22R that are adjacent to each other in the X direction in a plan view and are provided in the semiconductor layer 21. The photoelectric conversion region 22 of the fourth embodiment further includes a separation barrier 48 that is provided between the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R in a plan view and that extends in the thickness direction of the semiconductor layer 21.

[0239] Each of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R is partitioned by an isolation region 31 and an isolation barrier 48, and has a p-type well region 23, an n-type semiconductor region 24, a photoelectric conversion unit 25, a transfer transistor TR, an n-type floating diffusion region FD, a p-type power supply contact region WC, and a pixel transistor Q. The floating diffusion region FD serving as a charge retention unit of each of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R is provided adjacent to the second isolation region 35 in a plan view.

[0240] 37 to 38B , the separation barriers 48 protrude inward from the middle of each of the two first extending portions 31x that extend in the X direction across the photoelectric conversion region 22 in a plan view, and are spaced apart from each other in the Y direction. That is, in the photoelectric conversion region 22 of the third embodiment, the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R that are adjacent to each other in the X direction are selectively separated by the two separation barriers 48 that protrude inward from the middle of each of the two first extending portions 31x that extend in the X direction.

[0241] Each of the two separation barriers 48 includes, for example, a first carved portion 32a and a separation insulating film 32b provided in this first carved portion 32a, similar to the first separation region 32 of the separation region 31, but is not limited to this, and is integrated with and connected to the first separation region 32 of the separation region 31. Therefore, a p-type pinning layer 33 is also provided on the semiconductor layer 21 side of the interface Lp between each of the two separation barriers 48 and the semiconductor layer 21.

[0242] 37 to 38B , the second separation region 35 of the fourth embodiment is provided in a connecting portion 49 that connects a first separation region between two photoelectric conversion regions 22 aligned in the Y direction in plan view and each separation barrier 48 of the two photoelectric conversion regions 22. In the connecting portion 49, the second separation region 35 is provided across the first separation region 32 and the two separation barriers 48 in plan view. Here, in the third embodiment, the first extension portion 31x and the second extension portion 31y that surround the periphery of the photoelectric conversion region 22 in plan view correspond to a specific example of an "external separation portion" of the present technology, and the separation barriers correspond to a specific example of an "internal separation portion" of the present technology.

[0243] <Autofocus> In an electronic device equipped with the solid-state imaging device 1D of this fourth embodiment, the signal charges of the two photoelectric conversion units 25, 25 provided in one photoelectric conversion region 22 are read out for each pixel 3, and the phase difference therebetween is detected.

[0244] When the focus is correct, there is no difference in the amount of signal charge accumulated in the two photoelectric conversion units 25 included in one photoelectric conversion region 22. In contrast, when the focus is not correct, there is a difference between the amount of signal charge Q1 accumulated in one of the two photoelectric conversion units 25 and the amount of signal charge Q2 accumulated in the other photoelectric conversion unit 25. When the focus is not correct, the electronic device performs an operation such as moving the objective lens so that Q1 and Q2 coincide with each other. This is autofocus.

[0245] <Flow of Signal Charges> In the photoelectric conversion region 22 of the fourth embodiment, the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R are partially separated except for the area between the two isolation barriers 48. The p-type well regions 23 of the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R are connected between the two isolation barriers 48. Therefore, the p-type well regions 23 between the isolation barriers 48 function as an overflow path.

[0246] A first potential barrier can be formed in the well region 23 between the two isolation barriers. The transfer transistor TR of the first photoelectric conversion cell 22L can form a second potential barrier higher than the first potential barrier when not transferring signal charges from the photoelectric conversion unit 25 to the floating diffusion region FD. Furthermore, the transfer transistor TR of the second photoelectric conversion cell 22R can form a second potential barrier higher than the first potential barrier when not transferring signal charges from the photoelectric conversion unit 25 to the floating diffusion region FD.

[0247] The photoelectric conversion units 25, 25 of each of the first and second photoelectric conversion cells 22L, 22R can independently accumulate signal charges up to the height of the first potential barrier. When the amount of accumulated signal charges exceeds the height of the first potential barrier, the signal charges flow from one of the photoelectric conversion units 25 of each of the first and second photoelectric conversion cells 26L, 22R to the other via the overflow path between the two separation barriers 48.

[0248] The present technology can also be applied to the solid-state imaging device 1D according to the fourth embodiment, and the same effects as those of the solid-state imaging device 1A according to the first embodiment described above can be obtained.

[0249] 39A is a plan view schematically showing a configuration example of a pixel according to Modification 4-1 of the first embodiment of the present technology. 39B is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the a39-a39 cutting line in FIG. 39A.

[0250] As shown in FIGS. 39A and 31B, the isolation region 31 of this modification 4-1 includes two second isolation regions 35 (35X, 35Y).

[0251] Of the two second isolation regions 35 (35X, 35Y), the second isolation region 35X is provided in the connecting portion 49 of the isolation region 31, as in the fourth embodiment described above. The remaining second isolation region 35Y is configured with a C-shaped planar pattern. This C-shaped second isolation region 35Y extends across the other first extension portion 31x, which is different from the one first extension portion 31x on which one second isolation region 35 is provided, and across two second extension portions 31y connected to the other first extension portion 31x, and overlaps with the first isolation region 32 in a planar view. In this modification 4-1, the other second isolation region 35 is provided with a gate electrode 54 of the transfer transistor TR. The photoelectric conversion region 22 of this modification 4-1 includes the inter-element isolation region 44 shown in FIG. 21 of the above-described modification 1-8. In this modification 4-1, a p-type power supply contact region WC is provided between the two isolation barriers 48 in plan view.

[0252] The present technology can also be applied to this modification 4-1, and the same effects as those of the solid-state imaging device 1D according to the above-described fourth embodiment can be obtained. Furthermore, in this modification 4-1, the gate electrodes 54 of the transfer transistors TR of the two photoelectric conversion cells (the first photoelectric conversion cell 22L and the second photoelectric conversion cell 22R) are provided in the second isolation region 35, and therefore, compared to the above-described fourth embodiment, the degree of freedom in arranging elements in the photoelectric conversion region 22 can be further increased.

[0253] 40A is a plan view schematically illustrating a configuration example of a pixel according to Modification 4-2 of the first embodiment of the present technology, and Fig. 40B is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure taken along the a40-a40 cutting line in Fig. 40A.

[0254] As shown in Figures 40A and 40B, the separation region 31 of this variant example 4-2 has, as the second separation region 35, two second separation regions 35X and one second separation region 35Y, and also has one second separation region 35Z.

[0255] Two second isolation regions 35X are provided individually on both ends of one of two first extension portions 31x of the isolation region 31 surrounding one photoelectric conversion region 22. One second isolation region 35Y is provided on the side of the other of the two first extension portions 31x, as in the above-described modification 4-1. The remaining second isolation region 31z is provided on the side of one of the two isolation barriers 48 in plan view, overlapping this one isolation barrier 48. The gate electrode 54 of the transfer transistor TR is provided in this second isolation region 35z. Each of the second isolation regions 35Y and 35Z is integrated with the inter-element isolation region 44.

[0256] The present technology can also be applied to this modification 4-2, and the same effects as those of the above-described modification 4-1 can be obtained.

[0257] Fifth Embodiment <Application Example to Electronic Devices> The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0258] FIG. 41 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a fourth embodiment of the present technology.

[0259] 41 , the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 illustrates an embodiment in which the solid-state imaging devices 1A to 1D according to the first to fourth embodiments of the present technology are used as the solid-state imaging device 101 in an electronic device (for example, a camera).

[0260] The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause charge transfer in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0261] With this configuration, the degree of freedom in arranging elements in the photoelectric conversion region 22 in the solid-state imaging device 101 is increased, and the image quality performance of the electronic device 100 of the fifth embodiment can be improved.

[0262] The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0263] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0264] The present technology may also be configured as follows: (1) A semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction, and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region, the isolation region having: a first isolation region including a first carved portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side, and a second isolation region including a second carved portion formed by selectively removing a part of the first carved portion on the first surface portion side of the semiconductor layer and having a width in the lateral direction in a plan view wider than the width of the first isolation region, the photoelectric conversion region having a pinning layer formed by introducing an impurity into the semiconductor layer around the first carved portion from inside the first carved portion, a first isolation region formed on the semiconductor layer and having a first surface portion extending from the first surface portion toward the second surface portion of the semiconductor layer together with the first isolation region, and a second isolation region formed on the semiconductor layer and having a second surface portion extending from a bottom of the second isolation region toward the second surface portion of the semiconductor layer together with the first isolation region. (2) The photodetector according to (1), wherein the pinning layer pins damage to the semiconductor layer around the first carved portion. (3) The photodetector according to (1) or (2), wherein the photoelectric conversion region further has a well region of a first conductivity type, and the pinning layer is a semiconductor region of the first conductivity type having a higher impurity concentration than the well region. (4) The photodetector according to any one of (1) to (3), wherein the photoelectric conversion region further includes: a photoelectric conversion unit that photoelectrically converts light incident from the second surface side of the semiconductor layer into a signal charge, a charge holding unit that is provided on the first surface side of the semiconductor layer and holds the signal charge photoelectrically converted by the photoelectric conversion unit, and a transfer transistor that transfers the signal charge photoelectrically converted by the photoelectric conversion unit to the charge holding unit, and the charge holding unit is adjacent to the second isolation region in a planar view. (5) The photodetector according to any one of (1) to (3), wherein the isolation region further includes a first extension portion that extends in a first direction in a planar view, a second extension portion that intersects with the first direction, and an intersection portion where the first extension portion and the second extension portion intersect, and the second isolation region is provided at the intersection portion.(6) The photodetector according to any one of (1) to (3), wherein the photoelectric conversion region includes a photoelectric conversion unit that photoelectrically converts light incident from the second surface side of the semiconductor layer into signal charges, and a transfer transistor that transfers the signal charges photoelectrically converted in the photoelectric conversion unit to a charge storage unit, and the charge storage unit is provided in the second isolation region adjacent to a side surface of the photoelectric conversion region. (7) The photodetector according to any one of (1) to (6), wherein the isolation region is formed so that its width in the short side direction in a plan view is wider than the width in the short side direction of the first carved portion and its depth along the one direction is shallower than the depth of the second carved portion, and further includes a third isolation region including a third carved portion formed by selectively removing a part of each of the first carved portion and the pinning layer on the first surface side of the semiconductor layer. (8) The photodetector device according to any one of (1) to (6), further comprising a third isolation region including a third carved portion formed by selectively removing a portion of each of the first carved portion and the pinning layer on the first surface side of the semiconductor layer, the third isolation region being formed such that the width in the short side direction in a plan view is wider than the width in the short side direction of the first carved portion and narrower than the width in the short side direction of the second carved portion. (9) The photodetector according to claim (7) or (8), further comprising a relay electrode provided outside the first surface portion of the semiconductor layer, wherein the photoelectric conversion region further comprises: a well region of a first conductivity type; and a power supply contact region of the first conductivity type that is adjacent to the third isolation region in a planar view, and that is in contact with each of the well region and the pinning layer and is provided on the first surface portion side of the semiconductor layer, and wherein the relay electrode overlaps the third isolation region and the power supply contact region in a planar view, and is connected to the power supply contact region.(10) The photodetector according to any one of (1) to (9), wherein the isolation region further includes a third isolation region including a third carved portion formed by selectively removing a portion of the first carved portion on the first surface side of the semiconductor layer, the pinning layer is provided on both sides of the first isolation region in a lateral direction, the third isolation region is provided biased to one of the both sides of the first isolation region in the lateral direction, and at least one of the pinning layers on both sides of the first isolation region extends toward the first surface side of the semiconductor layer beyond a bottom of the third isolation region. (11) The photodetector according to any one of (1) to (10), wherein the photoelectric conversion region further includes an element formation region partitioned by an inter-element isolation region on the first surface side of the semiconductor layer, and the inter-element isolation region is provided so as to overlap a portion of the first isolation region on the first surface side of the semiconductor layer. (12) The photodetector according to any one of (1) to (11) above, wherein the pinning layer has an impurity concentration that increases stepwise from the first surface portion side to the second surface portion side of the semiconductor layer. (13) The photodetector according to any one of (1) to (12) above, wherein the transfer transistor is adjacent to the semiconductor layer with a gate insulating film interposed therebetween and has a gate electrode extending from the first surface portion side to the second surface portion side of the semiconductor layer. (14) The photodetector according to any one of (1) to (12) above, wherein the transfer transistor has a gate electrode provided outside the first surface portion of the semiconductor layer with a gate insulating film interposed therebetween. (15) The photodetector according to (4) or (6) above, further comprising a pixel circuit that reads out signal charges held in the charge holding portion and outputs a pixel signal based on the read signal charges, and the pixel transistor included in the pixel circuit is provided on the first surface portion side of the semiconductor layer in the photoelectric conversion region. (16) The photodetector according to claim (4) or (6), further comprising: a first semiconductor layer as the semiconductor layer; a second semiconductor layer provided so as to overlap the semiconductor layer in the one direction; and a pixel circuit that reads out signal charges held in the charge holding portion and outputs a pixel signal based on the read signal charges, wherein a pixel transistor included in the pixel circuit is provided in the second semiconductor layer.(17) The photodetector device according to any one of (1) to (16), wherein the separation region further includes an external separation portion surrounding the outer periphery of the photoelectric conversion region in a planar view, and an internal separation portion protruding from the external separation portion toward the photoelectric conversion region in a planar view and separating the photoelectric conversion region into two photoelectric conversion cells, and the second separation region is provided across the external separation portion and the internal separation portion. (18) The photodetector device described in (17) above, wherein each of the two photoelectric conversion cells has: a photoelectric conversion unit that photoelectrically converts light incident from the second surface side of the semiconductor layer into signal charges; a charge holding unit that is provided on the first surface side of the semiconductor layer and holds the signal charges photoelectrically converted by the photoelectric conversion unit; and a transfer transistor that transfers the signal charges photoelectrically converted by the photoelectric conversion unit to the charge holding unit; and wherein the charge holding units of each of the two photoelectric conversion cells are provided adjacent to each other and the second isolation region in a planar view. (19) A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending from the first surface portion of the semiconductor layer toward the second surface portion; and a pinning layer provided on the semiconductor layer side of an interface between the separation region and the photoelectric conversion region, wherein the separation region has: a first separation region extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a second separation region provided so as to selectively overlap the first separation region on the first surface portion side of the semiconductor layer and having a width in the short side direction in a planar view that is wider than the width of the first separation region in the short side direction, wherein the pinning layer includes: a first portion extending along the first separation region from the first surface portion of the semiconductor layer toward the second surface portion side; and a second portion extending along the first separation region from a bottom of the second separation region toward the second surface portion side.(20) A method for manufacturing a photodetector, comprising: forming a first carved portion extending from a first surface portion toward a second surface portion of a semiconductor layer, the first surface portion being one of a first surface portion and a second surface portion located on opposite sides of the semiconductor layer; introducing impurities into the semiconductor layer around the first carved portion from inside the first carved portion to form a pinning layer extending from the first surface portion toward the second surface portion of the semiconductor layer on a side portion of the semiconductor layer; and selectively removing each of the first carved portion and the pinning layer on the first surface portion side of the semiconductor layer to form a second carved portion whose width in the short direction is wider than that of the first carved portion in a planar view. (21) A photodetector comprising: an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that processes a signal output from the photodetector, wherein the photodetector comprises a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region, wherein the isolation region comprises: a first isolation region including a first carved portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a second isolation region including a second carved portion formed on the first surface portion side of the semiconductor layer by selectively removing a part of the first carved portion and having a width in the lateral direction wider than the width of the first carved portion in a plan view, wherein the photoelectric conversion region has a pinning layer formed by introducing an impurity into the semiconductor layer around the first carved portion from inside the first carved portion, the pinning layer extends from the first surface of the semiconductor layer toward the second surface together with the first carved portion in a first portion including only the first carved portion of the first and second carved portions, and in a second portion including the first and second carved portions, a portion of the pinning layer is selectively removed together with the first carved portion and terminates at the bottom of the second carved portion.

[0265] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0266] DESCRIPTION OF SYMBOLS 1A, 1B, 1C, 1D...Solid-state imaging device 2...Semiconductor chip 2A...Pixel array section 2B...Peripheral section 3...Pixel 4...Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7...Output circuit 8...Control circuit 10...Pixel drive line 11...Vertical signal line 12...Horizontal signal line 13...Logic circuit 14...Bonding pad 15...Pixel block 16...Pixel circuit 17...Pixel block forming region 21...Semiconductor layer 22...Photoelectric conversion region 23...P-type well region 24...N-type semiconductor region 25...Photoelectric conversion section 26L...First photoelectric conversion cell 25R...Second photoelectric conversion cell 31...Isolation region 31x...First extension portion 31y...Second extension portion 31 ｘｙ...intersection portion (intersection point portion) 32...first isolation region 32a...first carved portion 32b...isolation insulating film 32c...conductive film 33...pinning layer 33a...first portion 33b...second portion 34a...first impurity region 34b...second impurity region 34c...third impurity region 35...second isolation region 35a...second carved portion 35b...isolation insulating film 36...step portion 37...carved portion forming region 38...solid-phase diffusion medium film 41...third isolation region 41a...third carved portion 41b...isolation insulating film 42 relay electrode 43...third isolation region 43a...third carved portion 43b...isolation insulating film 44...inter-element isolation region 45...relay conductive pad 46...discontinued portion 47...third isolation region 48...isolation barrier 49...connecting portion 52...Gate trench portion 53...Gate insulating film 54...Gate electrode 54a...Head portion 54b...Body portion 56...Gate electrode 57a, 57b...Main electrode region 58...Solid-phase diffusion medium film 59Gate electrode 100...Electronic device 101...Solid-state imaging device 102...Optical lens (optical system) 103...Shutter device 104...Drive circuit 105...Signal processing circuit 106...Incident light AMP...Amplifying transistor FD...n-type floating diffusion region Q...Pixel transistor RST...Reset transistor SEL...Selection transistor S1...First surface portion S2...Second surface portion TR...Vertical transfer transistor TRL...Horizontal transfer transistor FD...Floating diffusion region WC...Power supply contact region

Claims

1. A semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction, and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region, the isolation region comprising: a first isolation region including a first carved portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side, and a second isolation region including a second carved portion formed by selectively removing a part of the first carved portion on the first surface portion side of the semiconductor layer and having a width in a short side direction wider than a width in the short side direction of the first isolation region in a plan view, the photoelectric conversion region comprising a pinning layer formed by introducing impurities into the semiconductor layer around the first carved portion from the inside of the first carved portion, A photodetection device, wherein the pinning layer includes a first portion extending, together with the first isolation region, from the first surface of the semiconductor layer toward the second surface, and a second portion extending, together with the first isolation region, from a bottom of the second isolation region toward the second surface of the semiconductor layer.

2. The photodetector according to claim 1, wherein said pinning layer pins damage to said semiconductor layer around said first recessed portion.

3. The photodetector according to claim 1, wherein the photoelectric conversion region further comprises a well region of a first conductivity type, and the pinning layer is a semiconductor region of the first conductivity type having a higher impurity concentration than the well region.

4. The photodetector device of claim 1, wherein the photoelectric conversion region further includes a photoelectric conversion section which photoelectrically converts light incident from the second surface side of the semiconductor layer into a signal charge, a charge holding section which is provided on the first surface side of the semiconductor layer and which holds the signal charge photoelectrically converted by the photoelectric conversion section, and a transfer transistor which transfers the signal charge photoelectrically converted by the photoelectric conversion section to the charge holding section, and the charge holding section is adjacent to the second isolation region in a planar view.

5. The optical detection device described in claim 4, wherein the separation region further has a first extension portion extending in a first direction in a planar view, a second extension portion intersecting the first direction, and an intersection portion where the first extension portion and the second extension portion intersect, and the second separation region is provided at the intersection portion.

6. The photodetector device of claim 1, wherein the photoelectric conversion region has a photoelectric conversion section that photoelectrically converts light incident from the second surface side of the semiconductor layer into a signal charge, and a transfer transistor that transfers the signal charge photoelectrically converted in the photoelectric conversion section to a charge holding section, and the charge holding section is provided in the second isolation region adjacent to a side portion of the photoelectric conversion region.

7. The photodetector device of claim 1, further comprising a third isolation region including a third carved portion whose width in the short side direction in a planar view is wider than the width in the short side direction of the first carved portion and whose depth along the one direction is shallower than the depth of the second carved portion, and which is formed by selectively removing a portion of each of the first carved portion and the pinning layer on the first surface side of the semiconductor layer.

8. The photodetector device of claim 1, further comprising a third isolation region including a third carved portion whose short-side width in a planar view is wider than the short-side width of the first carved portion and narrower than the short-side width of the second carved portion, and which is formed by selectively removing a portion of each of the first carved portion and the pinning layer on the first surface side of the semiconductor layer.

9. The photodetector device of claim 7 or 8, further comprising a relay electrode provided outside the first surface portion of the semiconductor layer, wherein the photoelectric conversion region further comprises: a well region of a first conductivity type; and a power supply contact region of a first conductivity type adjacent to the third isolation region in a planar view and provided on the first surface portion side of the semiconductor layer in contact with each of the well region and the pinning layer, wherein the relay electrode overlaps the third isolation region and the power supply contact region in a planar view and is connected to the power supply contact region.

10. The photodetector device of claim 1, wherein the isolation region further includes a third isolation region including a third recessed portion formed by selectively removing a portion of the first recessed portion on the first surface side of the semiconductor layer, the pinning layer is provided on both sides of the first isolation region in the short direction, the third isolation region is biased to one of the two sides of the first isolation region in the short direction, and at least one of the pinning layers on both sides of the first isolation region extends toward the first surface side of the semiconductor layer beyond the bottom of the third isolation region.

11. The photodetector device of claim 1, wherein the photoelectric conversion region further has an element formation region partitioned by an inter-element isolation region on the first surface side of the semiconductor layer, and the inter-element isolation region is provided so as to overlap a portion of the first isolation region on the first surface side of the semiconductor layer.

12. The photodetector according to claim 1, wherein the pinning layer has an impurity concentration that increases stepwise from the first surface side toward the second surface side of the semiconductor layer.

13. The photodetector device according to claim 1, wherein the transfer transistor has a gate electrode that is adjacent to the semiconductor layer with a gate insulating film interposed therebetween and extends from the first surface side of the semiconductor layer toward the second surface side.

14. The photodetector according to claim 1, wherein the transfer transistor has a gate electrode provided on the outer side of the first surface portion of the semiconductor layer with a gate insulating film interposed therebetween.

15. A photodetection device as described in claim 4 or 6, further comprising a pixel circuit that reads out the signal charge held in the charge holding portion and outputs a pixel signal based on the read-out signal charge, wherein a pixel transistor included in the pixel circuit is provided on the first surface side of the semiconductor layer in the photoelectric conversion region.

16. A photodetection device as described in claim 4 or 6, further comprising: a first semiconductor layer, a second semiconductor layer provided so as to overlap the semiconductor layer in the one direction; and a pixel circuit that reads out the signal charge held in the charge holding portion and outputs a pixel signal based on the read-out signal charge, wherein a pixel transistor included in the pixel circuit is provided in the second semiconductor layer.

17. The optical detection device described in claim 1, wherein the separation region further has an external separation portion surrounding the outer periphery of the photoelectric conversion region in a planar view, and an internal separation portion protruding from the external separation portion toward the photoelectric conversion region in a planar view and separating the photoelectric conversion region into two photoelectric conversion cells, and the second separation region is provided across the external separation portion and the internal separation portion.

18. The photodetection device described in claim 17, wherein each of the two photoelectric conversion cells has a photoelectric conversion section that photoelectrically converts light incident from the second surface side of the semiconductor layer into a signal charge, a charge holding section that is provided on the first surface side of the semiconductor layer and holds the signal charge photoelectrically converted by the photoelectric conversion section, and a transfer transistor that transfers the signal charge photoelectrically converted by the photoelectric conversion section to the charge holding section, and the charge holding section of each of the two photoelectric conversion cells is provided adjacent to the second isolation region in a planar view.

19. A photodetector comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a photoelectric conversion region provided in the semiconductor layer and partitioned by a separation region extending from the first surface portion of the semiconductor layer toward the second surface portion side; and a pinning layer provided on the semiconductor layer side of an interface between the separation region and the photoelectric conversion region, wherein the separation region has: a first separation region extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a second separation region provided selectively overlapping with the first separation region on the first surface portion side of the semiconductor layer and having a width in the short side direction in a planar view that is wider than the width of the first separation region, and the pinning layer includes: a first portion extending along the first separation region from the first surface portion of the semiconductor layer to the second surface portion side; and a second portion extending along the first separation region from a bottom of the second separation region to the second surface portion side.

20. A method for manufacturing a photodetector, comprising: forming a first carved portion extending from a first surface portion toward the second surface portion of a first surface portion and a second surface portion located on opposite sides of a semiconductor layer; introducing impurities into the semiconductor layer around the first carved portion from inside the first carved portion to form a pinning layer extending from the first surface portion side of the semiconductor layer toward the second surface portion side of the semiconductor layer on a side portion of the semiconductor layer; and selectively removing each of the first carved portion and the pinning layer on the first surface portion side of the semiconductor layer to form a second carved portion whose width in the short side direction is wider than that of the first carved portion in a planar view.

21. A photodetector comprising: an optical lens that focuses image light from a subject on an imaging surface of the photodetector; and a signal processing circuit that processes a signal output from the photodetector; wherein the photodetector comprises a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; and a photoelectric conversion region provided in the semiconductor layer and partitioned by an isolation region; wherein the isolation region comprises: a first isolation region including a first carved portion extending from the first surface portion side of the semiconductor layer toward the second surface portion side; and a second isolation region including a second carved portion formed by selectively removing a part of the first carved portion on the first surface portion side of the semiconductor layer and having a width in the short side direction in a plan view wider than the width of the first carved portion; and wherein the photoelectric conversion region comprises a pinning layer formed by introducing impurities into the semiconductor layer around the first carved portion from the inside of the first carved portion; the pinning layer extends together with the first carved portion from the first surface of the semiconductor layer toward the second surface of the semiconductor layer in a first portion including only the first carved portion of the first and second carved portions, and a portion of the pinning layer is selectively removed together with the first carved portion in a second portion including the first and second carved portions, terminating at a bottom of the second carved portion.

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