Optical detection device and electronic apparatus

Abstract

The present invention provides an optical detection device in which a reduction in the effective size of a gate electrode is suppressed. The optical detection device comprises: an interconnect layer having an extension section and an impurity supply layer provided within an insulating film; a first semiconductor layer in which a plurality of transistors having gate electrodes are formed and a first surface of which is in contact with the insulating film of the interconnect layer; and a second semiconductor layer which overlaps the first semiconductor layer and the interconnect layer along the thickness direction and in which a photoelectric conversion element is formed, wherein the first semiconductor layer contains a plurality of semiconductor regions that are isolated from each other, a pair of a main electrode region and a channel formation region of transistors are formed in the semiconductor regions, the channel formation region has a first surface, a second surface which is the surface on the opposite side from the first surface, and third and fourth surfaces that connect the first surface with the second surface, the gate electrodes face the second, third, and fourth surfaces across the gate insulating film, the extension section connects the gate electrodes with the impurity supply layer, and the gate electrodes and the extension section contain impurities supplied from the impurity supply layer.

Description

Photodetector and electronic equipment

[0001] The present technology (technology related to the present disclosure) relates to a photodetector and an electronic device, and in particular to a photodetector and an electronic device including a FINFET as a transistor.

[0002] Japanese Patent Application Laid-Open No. 2003-124222 discloses a configuration in which a photoelectric conversion element and a pixel transistor are provided in separate semiconductor layers.

[0003] International Publication No. 2019 / 130702

[0004] For example, in the imaging device described in Patent Document 1, when the transistor has a FINFET structure, the effective size of the gate electrode may become small.

[0005] The present technology has an object to provide a photodetector and an electronic device in which the effective size of a gate electrode is prevented from being reduced.

[0006] a first semiconductor layer having a first surface in contact with the insulating film of the wiring layer and including a plurality of transistors each having a gate electrode, the first semiconductor layer having a first surface in contact with the insulating film of the wiring layer; and a second semiconductor layer overlapping the first semiconductor layer and the wiring layer along a thickness direction and including a photoelectric conversion element, the first semiconductor layer including a plurality of semiconductor regions separated from each other, the semiconductor regions including a pair of main electrode regions and a channel formation region of the transistor, the channel formation region including the first surface, a second surface opposite to the first surface, and a third surface and a fourth surface connecting the first surface and the second surface, the gate electrode facing the second surface, the third surface, and the fourth surface via a gate insulating film, the extension portion connecting the gate electrode and the impurity supply layer, the gate electrode and the extension portion including impurities supplied from the impurity supply layer.

[0007] An electronic device according to an aspect of the present technology includes the light detection device and an optical system that forms an image light from a subject on the light detection device.

[0008] It is a chip layout diagram showing a configuration example of a photodetection device according to the first embodiment of the present technology. It is a block diagram showing a configuration example of a photodetection device according to the first embodiment of the present technology. It is an equivalent circuit diagram of a pixel of a photodetection device according to the first embodiment of the present technology. It is a longitudinal sectional view showing a cross-sectional configuration of a pixel region of a photodetection device according to the first embodiment of the present technology. It is a longitudinal sectional view showing a cross-sectional configuration when viewed in cross-section along the cutting line A-A of FIG. 4A. It is a partial enlarged view showing an enlarged region C of FIG. 4B. It is an explanatory diagram showing the positional relationship between an impurity supply layer and an extended portion when viewed in cross-section along the cutting line B-B of FIG. 4C. It is a process cross-sectional view showing a manufacturing method of a photodetection device according to the first embodiment of the present technology. It is a process cross-sectional view following FIG. 5A. It is a process cross-sectional view following FIG. 5B. It is a process cross-sectional view following FIG. 5C. It is a process cross-sectional view following FIG. 5D. It is a process cross-sectional view following FIG. 5E. It is a process cross-sectional view following FIG. 5F. It is a process cross-sectional view following FIG. 5G. It is a process cross-sectional view following FIG. 5H. It is a process cross-sectional view following FIG. 5I. It is a process cross-sectional view following FIG. 5J. It is a process cross-sectional view following FIG. 5K. It is a graph showing a simulation result of diffusion when the impurity is arsenic. It is a graph showing a simulation result of diffusion when the impurity is phosphorus. It is a graph showing a simulation result of diffusion when the impurity is boron. It is a longitudinal sectional view showing a cross-sectional configuration of a gate electrode of a transistor according to a comparative example. It is a longitudinal sectional view showing a cross-sectional configuration of a pixel region and a peripheral region of a photodetection device according to the second embodiment of the present technology. It is a process cross-sectional view showing a manufacturing method of a photodetection device according to the second embodiment of the present technology. It is a process cross-sectional view following FIG. 9A. It is a process cross-sectional view following FIG. 9B. It is a process cross-sectional view showing a manufacturing method of a photodetection device according to the second embodiment of the present technology. It is a process cross-sectional view following FIG. 10A. It is a process cross-sectional view following FIG. 10B. It is a process cross-sectional view following FIG. 10C. It is a longitudinal sectional view showing a cross-sectional configuration of a pixel region and a peripheral region of a photodetection device according to the third embodiment of the present technology. It is an explanatory diagram showing the positional relationship between an impurity supply layer and an extended portion of a photodetection device according to the fourth embodiment of the present technology. It is an explanatory diagram showing the positional relationship between an impurity supply layer and an extended portion of a photodetection device according to the fourth embodiment of the present technology. It is a longitudinal sectional view showing a cross-sectional configuration of a transistor included in a photodetection device according to Modification 1 of the fourth embodiment of the present technology.FIG. 13B is an explanatory diagram showing the positional relationship between an impurity supply layer and an extension portion when viewed in cross section along the B-B cutting line in FIG. 13A. FIG. 13C is an explanatory diagram showing the positional relationship between an impurity supply layer and an extension portion in a photodetector according to a second modification of the fourth embodiment of the present technology. FIG. 13D is an explanatory diagram showing the positional relationship between an impurity supply layer and an extension portion in a photodetector according to a second modification of the fourth embodiment of the present technology. FIG. 13E is an explanatory diagram showing the positional relationship between an impurity supply layer and an extension portion in a photodetector according to a second modification of the fourth embodiment of the present technology. FIG. 13F is a vertical cross-sectional view showing a cross-sectional configuration of a transistor included in a photodetector according to a third modification of the fourth embodiment of the present technology. FIG. 13G is a block diagram showing an example of a schematic configuration of an electronic device.

[0009] Hereinafter, preferred embodiments for carrying out the present technology will be described with reference to the drawings. Note that the embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0010] In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined by taking into consideration the following explanation. Furthermore, it goes without saying that the drawings include parts with different dimensional relationships and ratios. Furthermore, since drawings suitable for explaining the present technology are used, there may be differences in configuration between the drawings.

[0011] Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical idea of ​​the present technology, and the technical idea of ​​the present technology does not specify the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical idea of ​​the present technology can be modified in various ways within the technical scope defined by the claims.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0013] First Embodiment In this embodiment, an example in which the present technology is applied to a photodetector device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0014] <Overall Configuration of Photodetection Device> First, the overall configuration of the photodetection device 1 will be described. As shown in Fig. 1 , the photodetection device 1 according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the photodetection device 1 is mounted on the semiconductor chip 2. As shown in Fig. 16 , the photodetection device 1 captures image light (incident light 106) from a subject via an optical system (optical lens) 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal.

[0015] As shown in FIG. 1, the semiconductor chip 2 on which the photodetector 1 is mounted includes, in a two-dimensional plane including an X direction and a Y direction that intersect with each other, a square-shaped pixel region 2A provided in the center, and a peripheral region 2B provided outside the pixel region 2A so as to surround the pixel region 2A.

[0016] The pixel region 2A is a light receiving surface that receives light collected by, for example, the optical system 102 shown in FIG. 16 . In the pixel region 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 3 are repeatedly arranged in each of the X direction and the Y direction that intersect with each other within the two-dimensional plane. In this embodiment, as an example, the X direction and the Y direction are orthogonal to each other. Furthermore, the direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction, stacking direction). Furthermore, the direction perpendicular to the Z direction is the horizontal direction.

[0017] 1, a plurality of bonding pads 14 are arranged in the peripheral region 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 2. Each of the plurality of bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0018] 2, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0019] The vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated by the photoelectric conversion elements of each pixel 3 in accordance with the amount of light received to the column signal processing circuit 5 via vertical signal lines 11.

[0020] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixels and AD (Analog-Digital) conversion. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5 and connected between the output stage and the horizontal signal line 12.

[0021] The horizontal drive circuit 6 is configured by, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0022] The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

[0023] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0024] 3 is an equivalent circuit diagram showing an example of the configuration of a pixel 3. The pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion) FD that accumulates (holds) signal charges photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charges photoelectrically converted by the photoelectric conversion element PD to the charge accumulation region FD. The pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0025] The photoelectric conversion element PD generates a signal charge according to the amount of light received. The photoelectric conversion element PD also temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0026] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD, and the gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0027] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0028] The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. These transistors (AMP, SEL, RST) are made of, for example, a silicon oxide film (SiO ２ The transistors are configured as MOSFETs each having a gate insulating film made of silicon nitride (Si nitride), a gate electrode, a pair of main electrode regions that function as a source region and a drain region, and a channel forming region that connects the pair of main electrode regions. ３ N ４ Alternatively, the readout circuit 15 may be a MISFET (Metal Insulator Semiconductor FET) made of a silicon nitride (SiN) film or a stacked film of a silicon nitride film and a silicon oxide film. The readout circuit 15 may be provided for each photoelectric conversion element PD, or one readout circuit 15 may be shared by multiple photoelectric conversion elements PD. Similarly, the charge accumulation region FD may be provided for each photoelectric conversion element PD, or one charge accumulation region FD may be shared by multiple photoelectric conversion elements PD.

[0029] The amplifier transistor AMP has a source region electrically connected to the drain region of the select transistor SEL, a drain region electrically connected to the power supply line Vdd and the drain region of the reset transistor RST, and a gate electrode electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0030] The selection transistor SEL has a source region electrically connected to the vertical signal line 11 (VSL), a drain electrically connected to the source region of the amplification transistor AMP, and a gate electrode electrically connected to a selection transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0031] The reset transistor RST has a source region electrically connected to the charge storage region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see FIG. 2).

[0032] <<Specific Configuration of Photodetector>> Next, a specific configuration of the photodetector 1 will be described with reference to Figures 4A, 4B, 4C, and 4D. In this embodiment, the configuration of a portion of the photodetector 1 that corresponds to the pixel region 2A (Figure 1) will be described. In the following description, it is assumed that the gate electrodes of each transistor are made of polysilicon.

[0033] <Layer Structure of Photodetector> As shown in Fig. 4A, the photodetector 1 (semiconductor chip 2) includes a layer structure in which, for example, a semiconductor layer 20, a first wiring layer 30, a semiconductor layer 40, and a second wiring layer 50 are layered in that order along the thickness direction. Fig. 4A also shows a bonding surface S between the first wiring layer 30 and the semiconductor layer 40. In addition, a color filter and a microlens (on-chip lens) (not shown) are provided on the light incident surface side of the semiconductor layer 20.

[0034] <Semiconductor Layer (Second Semiconductor Layer)> The semiconductor layer 20 is an example of a second semiconductor layer. The semiconductor layer 20 is composed of a semiconductor substrate. The semiconductor layer 20 is, but is not limited to, composed of, for example, a single-crystal silicon substrate, one surface of which is a light incident surface and the other surface of which is an element formation surface. The light incident surface is sometimes referred to as the back surface, and the element formation surface is sometimes referred to as the main surface. The semiconductor layer 20 includes semiconductor regions 21 and 22 of a first conductivity type and a semiconductor region of a second conductivity type. In this embodiment, an example is described in which the first conductivity type is n-type and the second conductivity type is p-type, but the present technology is not limited to this. The first conductivity type may be p-type and the second conductivity type may be n-type. Examples of impurities (dopants) that make the semiconductor region n-type include donor impurity elements such as arsenic (As) and phosphorus (P). Examples of impurities (dopants) that make the semiconductor region p-type include acceptor impurity elements such as boron (B).

[0035] As shown in FIG. 4A , a photoelectric conversion element PD is configured in the semiconductor layer 20. The photoelectric conversion element PD is configured in the semiconductor layer 20, for example, for each pixel 3. The photoelectric conversion element PD mainly includes a semiconductor region 21 of a first conductivity type (n- type). The photoelectric conversion element PD photoelectrically converts incident light and generates signal charges. The semiconductor layer 20 is configured with a charge accumulation region FD. For example, one charge accumulation region FD may be configured for each pixel 3, or one charge accumulation region FD may be configured for multiple pixels 3. The charge accumulation region FD is configured as a semiconductor region 22 of the first conductivity type (n+ type). The semiconductor layer 20 also is configured with a transfer transistor TR. The transfer transistor TR is configured in the semiconductor layer 20, for example, for each pixel 3. The transfer transistor TR is located closer to the element formation surface of the semiconductor layer 20 in the thickness direction. The transfer transistor TR is turned on or off depending on the voltage applied to the gate electrode TRG. The transfer transistor TR is an n-type MOSFET that, when on, forms a first conductivity type channel (n-channel) between the photoelectric conversion element PD and the charge accumulation region FD and transfers the signal charge generated in the photoelectric conversion element PD to the charge accumulation region FD. In addition, when off, the transfer transistor TR electrically isolates the photoelectric conversion element PD from the charge accumulation region FD.

[0036] <First Wiring Layer (Wiring Layer)> The first wiring layer 30 is an example of a wiring layer. The first wiring layer 30 is a multi-layer wiring layer, with one surface along the thickness direction contacting the semiconductor layer 20 and the other surface contacting the semiconductor layer 40. The first wiring layer 30 includes, but is not limited to, an insulating film 31 made of a known insulating material, FD contacts 32, vias 33 extending mainly along the thickness direction, wiring 34 extending mainly along the horizontal direction, and an extension portion 70. The insulating film 31 includes multiple layers made of a known insulating material. The insulating film 31 may also include films made of different materials (e.g., silicon oxide film and silicon nitride film). The FD contacts 32, vias 33, wiring 34, and extension portion 70 are provided within the insulating film 31. The FD contacts 32 are terminals that contact the charge accumulation region FD, and signal charges accumulated in the charge accumulation region FD flow through the FD contacts 32 to the vias 33 and wiring 34. Furthermore, the first wiring layer 30 is provided with a gate electrode TRG of the transfer transistor TR. The gate electrode TRG, the FD contact 32, and the via 33 are made of, for example, polysilicon. The gate electrode TRG, the FD contact 32, and the via 33 are made of, for example, n+ type polysilicon into which impurities have been ion-implanted. The wirings 34 are made of polysilicon, and a plurality of wirings 34 are provided. More specifically, the wirings 34 are made of n+ type polysilicon into which impurities have been ion-implanted. Some of the plurality of wirings 34 function as impurity supply layers 60. The impurity supply layers 60 and the extension portions 70 will be described in detail later. A plurality of impurity supply layers 60 are also provided in the first wiring layer 30.

[0037] <Semiconductor Layer (First Semiconductor Layer)> The semiconductor layer 40 is an example of a first semiconductor layer. The semiconductor layer 40 is made of a semiconductor substrate. The semiconductor layer 40 is made of, for example, a single crystal silicon substrate, although not limited thereto. A plurality of transistors are configured in the semiconductor layer 40. The semiconductor layer 40 includes a plurality of semiconductor regions (active regions) 41 that are separated from one another. The plurality of semiconductor regions 41 are arranged side by side along the horizontal direction. FIG. 4A shows one of the plurality of semiconductor regions 41. The transistor is configured in the semiconductor region 41. More specifically, the source region, drain region, and channel formation region of the transistor are configured in the semiconductor region 41.

[0038] The semiconductor region 41 shown in FIG. 4A is configured with an amplifier transistor AMP having a gate electrode AMPG and a select transistor SEL having a gate electrode SELG. Pixel transistors such as the amplifier transistor AMP, select transistor SEL, and reset transistor RST are configured in the semiconductor region 41 that overlaps the pixel region 2A in a planar view, i.e., the semiconductor region 41 located in the pixel region 2A. All pixel transistors are transistors (n-type MOSFETs) in which channels of the same conductivity type (first conductivity type) are formed. The semiconductor region 41 shown in FIG. 4A also includes n+ type semiconductor regions 43, 44, and 45. The semiconductor region 43 functions as the drain region of the amplifier transistor AMP, the semiconductor region 44 functions as the source region of the amplifier transistor AMP and the drain region of the select transistor SEL, and the semiconductor region 45 functions as the source region of the select transistor SEL. FIG. 4B is a longitudinal cross-sectional view showing the cross-sectional configuration when viewed along the A-A section line in FIG. 4A. As shown in FIG. 4B, the semiconductor region 41 includes a semiconductor region 42 that functions as a channel formation region of the transistor. 4B is a channel formation region of the amplifier transistor AMP. Hereinafter, the semiconductor region 42 will be referred to as the channel formation region 42. Although not shown, the reset transistor RST is formed in another semiconductor region 41.

[0039] As shown in FIG. 4A , the semiconductor layer 40 has an SOI (Silicon on Insulator) structure in which its first surface S1 is in contact with the insulating film 31 of the first wiring layer 30. The transistor formed in the semiconductor region 41 of the SOI structure is a FINFET (fin FET). As shown in FIG. 4B , the gate electrode of the transistor formed in the semiconductor region 41 three-dimensionally faces the channel formation region via a gate insulating film (not shown). In this way, the transistor formed in the semiconductor region 41 is an SOI-FINFET. Below, the SOI-FINFET will be described in more detail using the amplifier transistor AMP as an example of the transistors formed in the semiconductor region 41. The other transistors formed in the semiconductor region 41 have the same configuration as the amplifier transistor AMP, so their description will be omitted.

[0040] FIG. 4C is an enlarged view of region C shown in FIG. 4B. The channel formation region 42 has a first surface S1, a second surface S2 opposite the first surface S1, and a third surface S3 and a fourth surface S4 connecting the first surface S1 and the second surface S2. The third surface S3 and the fourth surface S4 extend along a direction from one of the semiconductor regions 43 and 44 shown in FIG. 4A to the other. As shown in FIG. 4C, the gate electrode AMPG faces three surfaces of the channel formation region, namely, the second surface S2, the third surface S3, and the fourth surface S4, via a gate insulating film F. The gate insulating film F is a film made of a known insulating material such as silicon oxide. The gate insulating film F is not shown in any figures other than FIG. 4C. The corners between the second surface S2 and the third surface S3 and the corners between the second surface S2 and the fourth surface S4 shown in FIG. 4C may be slightly rounded.

[0041] The dimension h, which is the distance between the first surface S1 and the second surface S2 (i.e., the fin height), is approximately several hundred nanometers. Compared to the fin height of a FINFET used in general logic, the dimension h is one order of magnitude larger. When configuring a pixel transistor using a FINFET, it is desirable to set the dimension h to approximately several hundred nanometers in terms of gain. More specifically, the dimension h may be, for example, approximately several tens of nanometers to 500 nm, approximately 200 nm to 500 nm, or approximately 200 nm to 300 nm.

[0042] As shown in FIG. 4B , the amplifier transistor AMP forms a first-conductivity-type (n-type) channel in the channel formation region 42 in response to the amount of signal charge supplied from the charge storage region FD to the gate electrode AMPG. When the channel is formed, electrical conduction is established between the first-conductivity-type (n-type) source region and the first-conductivity-type (n-type) drain region. The gate electrode AMPG is a portion extending from the junction surface S toward the second wiring layer 50. The gate electrode AMPG is made of polysilicon. The polysilicon constituting the gate electrode AMPG is made conductive by containing impurities, i.e., dopants, that provide carriers to the semiconductor, thereby preventing its electrical resistance from increasing. In this embodiment, the gate electrode AMPG is a first-conductivity-type (n-type) semiconductor by containing donor impurities.

[0043] 4C , the gate electrode AMPG contains both of the donor impurities supplied from the impurity supply layer 60 and the donor impurities ion-implanted into the gate electrode AMPG from the side opposite to the impurity supply layer 60. When the first surface S1 side of the semiconductor layer 40 is the lower side and the second surface S2 side is the upper side, the uppermost reach position in the gate electrode AMPG of the impurity supplied from the impurity supply layer 60 is higher than the lowermost reach position in the gate electrode AMPG of the impurity ion-implanted into the gate electrode AMPG.

[0044] <Impurity Supply Layer 60 and Extension Portion 70> FIG. 4D is an explanatory diagram showing the positional relationship between the impurity supply layer 60 and the extension portion 70 when viewed in cross section along the B-B section line in FIG. 4C. As shown in FIGS. 4C and 4D, the impurity supply layer 60 is a rectangular plate-like member in plan view. The polysilicon constituting the impurity supply layer 60 contains impurities, i.e., dopants, that provide carriers to the semiconductor. In this embodiment, the impurity supply layer 60 is a first conductivity type (n-type) semiconductor due to the inclusion of donor impurities. The impurity supply layer 60 containing donor impurities may be referred to as an impurity supply layer 60n to indicate that it is n-type. When the conductivity type of the impurity supply layer 60 is not important, it is simply referred to as the impurity supply layer 60. The impurity supply layer 60n is an impurity supply source that supplies donor impurities to the gate electrode of the transistor. More specifically, the donor impurities contained in the impurity supply layer 60n are supplied to the gate electrode of the transistor via the extension portion 70. Therefore, the extension portion 70 connects the impurity supply layer 60 and the gate electrode of the transistor, and functions as a transport path that transports impurities from the impurity supply layer 60 to the gate electrode of the transistor. In this embodiment, as an example, the impurity supply layer 60 and the extension portion 70 provided for the gate electrode AMPG of the amplification transistor AMP will be described. The impurity supply layer 60 and the extension portion 70 provided for the gate electrodes of the other pixel transistors also have the same configuration as the impurity supply layer 60 and the extension portion 70 provided for the gate electrode AMPG, and therefore their description will be omitted.

[0045] As shown in FIG. 4C , the extension portion 70 extends between the gate electrode AMPG and the impurity supply layer 60. One end of the extension portion 70 is connected to the end (end face) of the gate electrode AMPG on the first wiring layer 30 side along the thickness direction of the first wiring layer 30, and the other end is connected to the impurity supply layer 60. In this embodiment, the extension portion 70 is formed integrally with the gate electrode AMPG. The extension portion 70 is a portion extending along the thickness direction of the first wiring layer 30 from the junction surface S between the first wiring layer 30 and the semiconductor layer 40 to the impurity supply layer 60. The extension portion 70 does not face the channel formation region 42 and therefore does not function as a gate electrode. The extension portion 70 also includes two portions. To distinguish the two portions of the extension portion 70 from each other, the portion connected to the portion of the gate electrode AMPG facing the third surface S3 is referred to as the first extension portion 70a, and the portion connected to the portion of the gate electrode AMPG facing the fourth surface S4 is referred to as the second extension portion 70b. When the first expansion portion 70a and the second expansion portion 70b are not to be distinguished from each other, they will be simply referred to as expansion portions 70.

[0046] The other ends of the first extension portion 70a and the second extension portion 70b are connected to the impurity supply layer 60n. More specifically, as shown in FIG. 4D , end faces 71 on the other end sides of the first extension portion 70a and the second extension portion 70b are connected to the impurity supply layer 60n. Each end face 71 is entirely connected to the impurity supply layer 60n. The impurity supply layer 60n is a single plate-shaped member and is large enough to entirely overlap the two end faces 71 of the first extension portion 70a and the second extension portion 70b in plan view. The first extension portion 70a and the second extension portion 70b are connected by this impurity supply layer 60n. Impurities are then supplied from the impurity supply layer 60n to the extension portion 70n via the end faces 71. The impurities supplied to the extension portion 70n are then supplied to the gate electrode AMPG.

[0047] The extension portion 70 is made of polysilicon, like the impurity supply layer 60 and the gate electrode AMPG. The polysilicon constituting the extension portion 70 contains donor impurities supplied from the impurity supply layer 60n, and is a semiconductor of the first conductivity type (n-type) like the impurity supply layer 60n. The extension portion 70 containing the donor impurities may be called extension portion 70n to indicate that it is n-type. When the conductivity type of the extension portion 70 is not important, it is simply called extension portion 70.

[0048] <Second Wiring Layer> The second wiring layer 50 is a multi-layer wiring layer, and as shown in FIG. 4A , one surface along the thickness direction is in contact with the semiconductor layer 40. The second wiring layer 50 includes, but is not limited to, an insulating film 51 made of a known insulating material, vias 52 extending mainly along the thickness direction, and wirings 53 extending mainly along the horizontal direction. The insulating film 51 includes multiple layers made of a known insulating material. The insulating film 51 may also include films made of different materials (e.g., a silicon oxide film and a silicon nitride film). A plurality of vias 52 and wirings 53 are provided within the insulating film 51. The vias 52 and wirings 53 are made of a conductor such as a metal. The vias 52 may be made of a material different from that of the wirings 53. Some of the plurality of vias 52 constitute through-electrodes TSVs. The through-electrode TSVs are TSVs (Through Silicon Vias) that penetrate the semiconductor layer 40 in the thickness direction.

[0049] 4B, the gate electrode AMPG is connected to the FD contact 32 via a wiring 53a, which is another part of the wiring 53, the via 52, the via 33, and the wiring 34. As a result, the signal charges accumulated in the charge accumulation region FD are supplied to the gate electrode AMPG. Also, as shown in FIG. 4A, the wiring 53b, which is one of the wirings 53 and electrically connected to the semiconductor region 43, is electrically connected to the power supply line Vdd. Also, the wiring 53c, which is one of the wirings 53 and electrically connected to the semiconductor region 45, is electrically connected to the vertical signal line 11 (VSL).

[0050] <<Method of Manufacturing Photodetector>> Below, a method of manufacturing the photodetector 1 will be described with reference to FIGS. 5A to 5L. In this embodiment, the methods of manufacturing the impurity supply layer 60, the extension portion 70, and the pixel transistor will be mainly described, and descriptions of other parts may be omitted. The manufacturing method will be described using the amplifier transistor AMP as an example. In the following description, the process of forming the gate insulating film will be omitted; however, the gate insulating film may be formed at an appropriate time using a known method. Note that, to simplify the description of the manufacturing method, the cross sections in FIGS. 5A to 5L show the photoelectric conversion element PD, the charge accumulation region FD, and the wiring connected thereto, which would not normally appear in cross section. Furthermore, in all drawings related to the present technology, the illustration of semiconductor conductivity types such as "n," "n+," "p," and "p+" may be omitted.

[0051] First, as shown in Fig. 5A, a semiconductor wafer including a semiconductor layer 20 in which a photoelectric conversion element PD, a charge accumulation region FD, and a transfer transistor TR are configured is prepared, and a portion of a first wiring layer 30 including vias 33 and the like is formed in the semiconductor layer 20 as shown in the figure. Then, a film 34m made of polysilicon is deposited on the exposed surface of the first wiring layer 30. Then, as shown in Fig. 5B, donor impurities are ion-implanted into the film 34m.

[0052] 5C, a resist pattern R2 is formed on the upper surface of the film 34m, and the film 34m is etched using the resist pattern R2 as a mask. This process removes excess portions of the film 34m, leaving portions that will become the interconnects 34 and the impurity supply layer 60n. The resist pattern R2 is then removed. A heat treatment (annealing) is then performed to activate the donor impurities implanted into the film 34m. This results in the interconnects 34 and the impurity supply layer 60n.

[0053] Next, as shown in FIG. 5D , an insulating film 31 is deposited so as to cover the wiring 34 and the impurity supply layer 60 n, and the exposed surface of the insulating film 31 is planarized by chemical mechanical polishing (CMP). Then, as shown in FIG. 5E , a semiconductor wafer for forming pixel transistors is bonded to the planarized exposed surface of the insulating film 31. The exposed surface of the bonded semiconductor wafer is then ground by CMP to reduce the thickness of the semiconductor wafer. The semiconductor wafer is ground until it reaches dimension h, which is the design value for the height of the fin portion (semiconductor region 41) of the SOI-FINFET. This leaves a portion corresponding to the semiconductor layer 40. Then, a hard mask pattern HM is formed so as to cover, in plan view, the portion of the semiconductor layer 40 where the fin portion is to be formed. Then, as shown in FIG. 5F , the semiconductor layer 40 is etched using the hard mask pattern HM as a mask. This process removes excess portions of the semiconductor layer 40, leaving portions that will become the semiconductor region 41.

[0054] 5G, a resist pattern R3 having openings R3a is formed on the exposed surface of the insulating film 31. The openings R3a are provided at positions where the extension portion 70 and the gate electrode AMPG are to be formed in plan view, i.e., on both sides of the channel formation region 42. The extension portion 70 is then removed. The insulating film 31 is then etched using the resist pattern R3 as a mask. This process forms a trench t1 in the insulating film 31. The trench t1 is formed to a depth that reaches the impurity supply layer 60. The resist pattern R3 and hard mask pattern HM are then removed.

[0055] 5H, a film pm made of polysilicon is deposited so as to fill the inside of the trench t1 and cover the exposed surface of the semiconductor region 41. The film pm is deposited by, for example, a chemical vapor deposition (CVD) method. Thereafter, as shown in FIG. 5I, donor impurities are ion-implanted into the film pm to make the gate electrode AMPG conductive.

[0056] 5J, excess portions of the film pm are removed using known lithography and etching techniques, thereby leaving portions of the film pm that will become the gate electrode AMPG and the extension portion 70. The portion of the gate electrode AMPG on the second surface S2 side (hereinafter referred to as the upper portion) contains ion-implanted donor impurities.

[0057] 5K, a heat treatment is then performed to diffuse the donor impurities in the polysilicon. If the first surface S1 side of the semiconductor layer 40 is the lower side and the second surface S2 side is the upper side, the donor impurities ion-implanted into the upper part of the gate electrode AMPG are diffused in a direction from the upper side to the lower side. The donor impurities contained in the impurity supply layer 60n are diffused into the gate electrode AMPG via the extension portion 70. The donor impurities supplied from the impurity supply layer 60n are diffused in the gate electrode AMPG in a direction from the lower side to the upper side.

[0058] At this time, in order to minimize the portion of the gate electrode AMPG that is not made conductive, it is desirable that the uppermost reach position in the gate electrode AMPG of the donor impurity supplied to the gate electrode AMPG from the impurity supply layer 60n be higher than the lowermost reach position in the gate electrode AMPG of the donor impurity ion-implanted directly into the gate electrode AMPG. Thereafter, although not shown, a sidewall is formed for the gate electrode AMPG, and donor impurities are ion-implanted into the semiconductor regions 43, 44, and 45 (FIG. 4A). Thereafter, as shown in FIG. 5L, an insulating film 51 is deposited so as to cover the gate electrode AMPG. Explanation of subsequent steps will be omitted.

[0059] <<Simulation Results of Impurity Diffusion Due to Heat Treatment>> Below, the results of a simulation performed assuming the diffusion of impurities from the impurity supply layer 60 to the gate electrode will be described. In this embodiment, in addition to the donor impurities arsenic and phosphorus as impurities, the diffusion of boron (B) as an acceptor impurity is also simulated. FIG. 6A shows the simulation results when the impurity is arsenic, FIG. 6B shows the simulation results when the impurity is phosphorus, and FIG. 6C shows the simulation results when the impurity is boron. The horizontal axis represents the thickness of the semiconductor layer, and the vertical axis represents the concentration of the impurity contained in the semiconductor layer. As shown in FIGS. 6A to 6C, in the initial state, the thickness of the semiconductor layer AA assuming the impurity supply layer 60 is 200 nm, and the concentration of the impurity contained in the semiconductor layer AA is 2×10 ２０ cm －３ Then, a semiconductor layer BB containing no impurities is provided on the upper surface of the semiconductor layer AA with a thickness of 200 nm. From this initial state, the impurity concentrations in the semiconductor layers AA and BB after heat treatment were simulated. As shown in FIGS. 6A to 6C, in either case of impurities, the diffusion of the impurities from the semiconductor layer AA to the semiconductor layer BB is good. As shown in FIG. 6A, the concentration of arsenic diffused into the semiconductor layer BB is 7×10 １９ cm －３ That's it, 1 x 10 ２０ cm －３ As shown in FIG. 6B, the concentration of phosphorus diffused into the semiconductor layer BB is about 8×10 １９ cm －３ That's it, 1 x 10 ２０ cm －３ As shown in FIG. 6C, the concentration of boron diffused into the semiconductor layer BB is about 8×10 １９ cm －３ That's it, 1 x 10 ２０ cm －３ From the above simulation results, it is understood that the impurity can be supplied from the impurity supply layer 60 to the gate electrode.

[0060] <<Main Effects of First Embodiment>> The main effects of the first embodiment will be described below. Note that in the following description of the effects, the amplifier transistor AMP will be used as an example of a transistor according to the present technology, but similar effects are also achieved for other transistors provided in the semiconductor region 41. Before describing the main effects of the first embodiment, a comparative example will be described. Generally, when a gate electrode of a transistor is formed from polysilicon, impurities are implanted to reduce the resistance value of the polysilicon and make it conductive. If the impurity implantation is insufficient, many portions of the gate electrode will not be made conductive (depleted portions), which may result in a reduced effective size of the gate electrode.

[0061] The transistor T according to the comparative example shown in FIG. 7 has a dimension h in the fin height direction of the channel formation region 42. As already explained, pixel transistors require a larger dimension h than conventional logic transistors. Therefore, the dimension of the gate electrode TG of the transistor T also increases along the fin height direction. As shown in FIG. 7 , when ions are implanted into such a gate electrode from above, the upper region TGa of the gate electrode TG is converted into a conductor, but the impurities do not diffuse to the lower region TGb of the gate electrode TG, resulting in depletion of the lower region TGb. Since the depleted lower region TGb maintains a high resistance, the effective size of the gate electrode TG may decrease. Furthermore, the larger the depleted lower region TGb, the smaller the area of ​​the conductive upper region TGa, resulting in a smaller effective gate width. As a result, there may be adverse effects such as a decrease in the gm / gds characteristics (gm is the mutual conductance, and gds is the mutual conductance between the source and drain) of the transistor T, deterioration in noise characteristics, an increase in on-resistance, and an increase in off-leak current.

[0062] In contrast to this, in the photodetector 1 according to the first embodiment of the present technology, the extension portion 70 connects the gate electrode AMPG and the impurity supply layer 60, and the gate electrode AMPG and the extension portion 70 contain impurities supplied from the impurity supply layer 60. This allows the impurities to be supplied from a portion of the gate electrode AMPG opposite to the portion into which ions are directly implanted, and the impurities can be diffused into a region that was prone to depletion. This makes it possible to prevent the depleted region in the gate electrode AMPG from becoming too large, and to prevent the effective size of the gate electrode AMPG from becoming smaller. This makes it possible to suppress the above-mentioned effects.

[0063] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the gate electrode AMPG contains impurities ion-implanted from the side opposite to the impurity supply layer 60. The gate electrode AMPG contains impurities supplied from both the impurity supply layer 60 side and the side opposite to the impurity supply layer 60. Therefore, impurities are diffused from both the upper and lower sides of the gate electrode AMPG, and the gate electrode AMPG is easily made conductive along the vertical direction, which can prevent the effective size (effective gate width) of the gate electrode AMPG from being reduced.

[0064] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, the uppermost reach position in the gate electrode AMPG of the impurity supplied from the impurity supply layer 60 is higher than the lowermost reach position in the gate electrode AMPG of the impurity ion-implanted into the gate electrode AMPG. This makes the gate electrode AMPG conductive evenly along the Z direction, and prevents the effective size of the gate electrode AMPG from becoming smaller.

[0065] The interconnections may be bonded via a through-electrode TSV as shown in FIG. 4A, or may be bonded by bonding a pair of bonding pads together.

[0066] Second Embodiment A second embodiment of the present technology shown in FIG. 8 will be described below. In the first embodiment described above, a transistor provided in a portion of the semiconductor layer 40 corresponding to the pixel region 2A was described. All of the transistors provided in the portion of the semiconductor layer 40 corresponding to the pixel region 2A were transistors (n-type MOSFETs) in which channels of the same conductivity type (first conductivity type) were formed. In this embodiment, a logic circuit 13 is provided in a portion of the semiconductor layer 40 corresponding to the peripheral region 2B, and the logic circuit 13 includes both a transistor in which a channel of the second conductivity type (e.g., a p-type MOSFET) is formed and a transistor in which a channel of the first conductivity type (e.g., an n-type MOSFET) is formed. The other configuration of the photodetector 1 is basically the same as that of the photodetector 1 of the first embodiment described above. Components already described are denoted by the same reference numerals, and their description will be omitted. Note that, in order to distinguish between impurities that make a semiconductor the first conductivity type and impurities that make a semiconductor the second conductivity type, the impurities that make a semiconductor the first conductivity type may be referred to as first impurities, and the impurities that make a semiconductor the second conductivity type may be referred to as second impurities.

[0067] 8 shows a transistor T1 as an example of an n-type MOSFET (first transistor) and a transistor T2 as an example of a p-type MOSFET (second transistor). A gate electrode G1 of the transistor T1 contains a donor impurity. The configuration of the transistor T1 is the same as the configuration of the pixel transistor described in the first embodiment, and therefore a description thereof will be omitted.

[0068] The transistor T2 and the impurity supply layer 60 and extension portion 70 provided for the transistor T2 will be described below. The configuration of the transistor T2 is the same as the configuration of the pixel transistor described in the first embodiment, except for the conductivity type. The impurity supply layer 60 and extension portion 70 provided for the transistor T2 are also the same as the configuration of the impurity supply layer 60 and extension portion 70 described in the first embodiment, except for the conductivity type.

[0069] The transistor T2 is turned on or off depending on the voltage applied to the gate electrode G2. When the transistor T2 is on, it forms a second conductivity type (p-type) channel in the channel formation region 42, and electrical conduction is established between the second conductivity type (p-type) source region and the second conductivity type (p-type) drain region (not shown). When the transistor T2 is off, electrical isolation is established between the source region and the drain region. The gate electrode G2 is a portion that extends from the junction surface S toward the second wiring layer 50. The polysilicon that constitutes the gate electrode G2 contains acceptor impurities, making it a second conductivity type (p-type) semiconductor.

[0070] The gate electrode G2 contains both impurities: an acceptor impurity supplied from the impurity supply layer 60 and an acceptor impurity ion-implanted from the side of the gate electrode G2 opposite to the impurity supply layer 60. When the first surface S1 side of the semiconductor layer 40 is the lower side and the second surface S2 side is the upper side ( FIG. 4C ), the uppermost reach position in the gate electrode G2 of the impurity supplied from the impurity supply layer 60 is higher than the lowermost reach position in the gate electrode G2 of the impurity ion-implanted into the AMPG.

[0071] The polysilicon constituting the impurity supply layer 60 provided for the transistor T2 contains acceptor impurities, making it a semiconductor of the second conductivity type (p-type). The impurity supply layer 60 containing acceptor impurities may be referred to as the impurity supply layer 60p to indicate that it is p-type. When the conductivity type of the impurity supply layer 60 is not important, it is simply referred to as the impurity supply layer 60. Furthermore, the polysilicon constituting the extension portion 70 provided for the transistor T2 contains acceptor impurities supplied from the impurity supply layer 60p, making it a semiconductor of the second conductivity type (p-type) like the impurity supply layer 60p. The extension portion 70 containing the acceptor impurities may be referred to as the extension portion 70p to indicate that it is p-type. When the conductivity type of the extension portion 70 is not important, it is simply referred to as the extension portion 70.

[0072] The impurity supply layer 60p is an impurity supply source that supplies acceptor impurities to the gate electrode G2 of the transistor T2. More specifically, the acceptor impurities contained in the impurity supply layer 60p are supplied to the gate electrode G2 via the extension portion 70p. Therefore, the extension portion 70p connects the impurity supply layer 60p and the gate electrode G2 and functions as a transport path that transports the acceptor impurities from the impurity supply layer 60p to the gate electrode G2. Furthermore, the impurity supply layer 60n (first impurity supply layer) and the impurity supply layer 60p (second impurity supply layer) are provided at the same depth along the thickness direction of the first wiring layer 30.

[0073] <<Method of Manufacturing Photodetector>> Hereinafter, a method of manufacturing the photodetector 1 will be described with reference to Figures 9A to 9C and Figures 10A to 10D. Note that in this embodiment, a method of manufacturing the impurity supply layers 60n, 60p and a method of manufacturing the extension portions 70n, 70p and the gate electrodes G1, G2 will be mainly described. Descriptions of steps similar to those in the first embodiment will be omitted. First, a method of manufacturing the impurity supply layers 60n, 60p will be described with reference to Figures 9A to 9C.

[0074] First, the process is performed up to the step of depositing a polysilicon film 34m on the exposed surface of the insulating film 31. Then, as shown in FIG. 9A , a resist pattern R4 having an opening R4a is formed on the exposed surface of the film 34m. The opening R4a is provided at a position where the wiring 34 and the impurity supply layer 60n are to be formed in a plan view. The openings R4a may be provided at positions where the wiring 34 and the impurity supply layer 60n are to be formed in a plan view in both the pixel region 2A and the peripheral region 2B. Then, using the resist pattern R4 as a mask, donor impurities are ion-implanted into the portions of the film 34m exposed through the openings R4a. The resist pattern R4 is then removed. Then, as shown in FIG. 9B , a resist pattern R5 having an opening R5a is formed on the exposed surface of the film 34m. The openings R5a are provided at a position where the impurity supply layer 60p is to be formed in a plan view. Then, using the resist pattern R5 as a mask, acceptor impurities are ion-implanted into the portions of the film 34m exposed through the openings R5a. Thereafter, the resist pattern R5 is removed.

[0075] 9C, a resist pattern R6 is formed on the upper surface of the film 34m, and the film 34m is etched using the resist pattern R6 as a mask. This process removes excess portions of the film 34m, leaving portions that will become the interconnects 34, the impurity supply layer 60n, and the impurity supply layer 60p. The resist pattern R2 is then removed. A heat treatment (annealing) is then performed to activate the donor impurities and acceptor impurities implanted into the film 34m. This results in the interconnects 34, the impurity supply layer 60n, and the impurity supply layer 60p.

[0076] Next, with reference to FIGS. 10A to 10D, a method for manufacturing the extension portions 70n, 70p and the gate electrodes G1, G2 will be described. First, a film pm made of polysilicon is formed. Then, as shown in FIG. 10A, donor impurities are selectively ion-implanted into the film pm to make the gate electrode G1 conductive (n-type). At this time, regions of the film pm that should not be made n-type (e.g., regions where the gate electrode G2 is to be formed) are covered with a resist pattern R7. Note that the donor impurity ion implantation may be performed at positions in both the pixel region 2A and the peripheral region 2B where gates made of n-type polysilicon are to be formed in a plan view. The resist pattern R7 is then removed.

[0077] 10B, acceptor impurities are selectively ion-implanted into the film pm to make the gate electrode G2 conductive (p-type). At this time, regions of the film pm that should not be made p-type (for example, regions where the gate electrode G1 is to be provided) are covered with a resist pattern R8. Then, the resist pattern R8 is removed.

[0078] 10C, excess portions of the film pm are removed using known lithography and etching techniques. This leaves portions of the film pm that will become the gate electrodes G1 and G2 and the extension portions 70 n and 70 p. The portions of the gate electrodes G1 and G2 that are on the second surface S2 side (hereinafter referred to as the upper portions) contain ion-implanted donor impurities.

[0079] 10D , a heat treatment is performed to diffuse the donor impurities and acceptor impurities in the polysilicon. When the first surface S1 side of the semiconductor layer 40 is the lower side and the second surface S2 side is the upper side, the impurities ion-implanted into the upper portions of the gate electrodes G1 and G2 diffuse in a direction from the upper side to the lower side. The impurities contained in the impurity supply layers 60 n and 60 p then diffuse into the gate electrodes G1 and G2 via the extension portions 70 n and 70 p. The impurities supplied from the impurity supply layers 60 n and 60 p then diffuse in the gate electrodes G1 and G2 in a direction from the lower side to the upper side.

[0080] At this time, in order to reduce the portions of the gate electrodes G1, G2 that are not made conductive as much as possible, it is desirable that the uppermost position in the gate electrodes G1, G2 that the impurities supplied to the gate electrodes G1, G2 from the impurity supply layers 60n, 60p reach is higher than the lowermost position in the gate electrodes G1, G2 that the impurities ion-implanted directly into the gate electrodes G1, G2 reach.

[0081] <<Main Effects of Second Embodiment>> The main effects of the second embodiment will be described below. The photodetector 1 according to the second embodiment also provides the same effects as the photodetector 1 according to the first embodiment.

[0082] 11 will be described below. In the second embodiment described above, the impurity supply layer 60n and the impurity supply layer 60p are provided at the same depth position along the thickness direction of the first wiring layer 30. In the photodetector 1 according to the third embodiment of the present technology, the impurity supply layer 60n (first impurity supply layer) and the impurity supply layer 60p (second impurity supply layer) are provided at different depth positions along the thickness direction of the first wiring layer 30.

[0083] <<Main Effects of the Third Embodiment>> The main effects of the third embodiment will be described below. The photodetector 1 according to the third embodiment also provides the same effects as the photodetector 1 according to the first embodiment and the photodetector 1 according to the second embodiment.

[0084] Furthermore, in the photodetector 1 according to the third embodiment of the present technology, the impurity supply layer 60n and the impurity supply layer 60p are provided at different depth positions along the thickness direction of the first wiring layer 30. Therefore, ion implantation of a donor impurity for forming the impurity supply layer 60n and ion implantation of an acceptor impurity for forming the impurity supply layer 60p are performed on polysilicon films stacked at different depth positions, respectively. Therefore, interference between the donor impurity and the acceptor impurity can be suppressed compared to when the donor impurity and the acceptor impurity are ion implanted into separate regions of the same polysilicon film.

[0085] [Fourth Embodiment] A fourth embodiment of the present technology shown in FIG. 12A will be described below. In a photodetector 1 according to the fourth embodiment of the present technology, the planar shape of the impurity supply layer 60 is different. As shown in FIG. 4D , the impurity supply layer 60 according to the first embodiment described above has a size that overlaps the entire two end faces 71 of the first extension portion 70a and the second extension portion 70b in a planar view. As shown in FIG. 12A , the impurity supply layer 60 according to this embodiment has a dimension along the vertical direction of the page that is smaller than the dimension along the vertical direction of the end face 71. Only a portion of each end face 71 is connected to the impurity supply layer 60. The first extension portion 70a and the second extension portion 70b are connected by this impurity supply layer 60. Note that, as shown in FIG. 12B , a plurality of such impurity supply layers 60 (two in the illustrated example) may be provided. 12A and 12B are explanatory diagrams showing the positional relationship between the impurity supply layer 60 and the extension portion 70 when the impurity supply layer 60 and the extension portion 70 are observed from the same direction as in FIG. 4D.

[0086] The photodetector 1 according to the fourth embodiment also provides the same effects as those of the photodetector 1 according to the first embodiment.

[0087] Furthermore, in the photodetector 1 according to the fourth embodiment, the area of ​​the impurity supply layer 60 in a planar view is smaller than in the first embodiment, so that the wiring capacitance can be reduced compared to the first embodiment.

[0088] The dimensions of the impurity supply layer 60 in a planar view may be determined taking into consideration the accuracy of alignment with the extension portion 70, and the positional relationship between the impurity supply layer 60 and the extension portion 70 may also be determined taking into consideration the accuracy of alignment, and are not limited to those shown in FIGS. 12A and 12B .

[0089] Modifications of the Fourth Embodiment Modifications of the fourth embodiment will be described below. Note that in the following modifications, the dimensions of the impurity supply layer 60 in a plan view may be determined in consideration of the accuracy of alignment with the extension portion 70, and the positional relationship between the impurity supply layer 60 and the extension portion 70 may also be determined in consideration of the accuracy of alignment, and are not limited to the drawings of each modification.

[0090] 4D, the impurity supply layer 60 according to the first embodiment is a single plate-like member, and has a size that overlaps the entire two end faces 71 of the first extension portion 70a and the second extension portion 70b in plan view. The impurity supply layer 60 according to the first modification of the fourth embodiment is provided separately for each of the first extension portion 70a and the second extension portion 70b, as shown in FIGS.

[0091] The photodetector 1 according to the first modified example of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment described above.

[0092] <Modification 2> In the impurity supply layer 60 according to Modification 2 of the fourth embodiment shown in FIG. 14A , the dimension in the vertical direction of the page is smaller than the dimension in the vertical direction of the page of the end surface 71, and the impurity supply layer 60 is provided separately for each of the first extension portion 70 a and the second extension portion 70 b. Each of the end surfaces 71 is connected to the impurity supply layer 60 only in a portion thereof. Note that the two impurity supply layers 60 shown in FIG. 14A are aligned at the same position in the vertical direction of the page, but as shown in FIG. 14B , they may be positioned at different positions in the vertical direction of the page. Furthermore, as shown in FIG. 14C , multiple impurity supply layers 60 may be arranged in a checkerboard pattern.

[0093] The photodetector 1 according to the second modification of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment described above.

[0094] 13A and 13B , the impurity supply layer 60 according to the first modification of the fourth embodiment is connected to the end surface 71 of the extension portion 70. The impurity supply layer 60 according to the third modification of the fourth embodiment shown in FIG. 15 is connected to the side surface of the extension portion 70.

[0095] The photodetector 1 according to the third modification of the fourth embodiment also provides the same effects as the photodetector 1 according to the fourth embodiment described above.

[0096] Fifth Embodiment The impurity supply layer 60 according to the first embodiment is a polysilicon layer into which impurities are ion-implanted. The impurity supply layer 60 according to the fifth embodiment of the present technology may be a solid-phase diffusion layer. The solid-phase diffusion layer is a film formed by depositing glass or polysilicon containing impurities such as phosphorus, arsenic, or boron by, for example, a CVD method. Examples of the solid-phase diffusion layer include a boron-containing silicon dioxide film (BSG film) and a phosphorus-doped amorphous silicon film.

[0097] The photodetector 1 according to the fifth embodiment also provides the same effects as those of the photodetector 1 according to the first embodiment.

[0098] Sixth Embodiment In the photodetector 1 according to the first embodiment, the impurity supply layer 60 is provided using some of the multiple wirings 34. However, the present technology is not limited to this. The impurity supply layer 60 may be provided separately by performing a dedicated process, rather than using part of other wirings. More specifically, the impurity supply layer 60 may be provided separately from the wirings 34 by performing a dedicated process. For example, the impurity supply layer 60 may be provided in a different layer (at a different depth) from the wirings 34 in the first wiring layer 30. Furthermore, in a design in which the wirings 34 are not provided in the first wiring layer 30, only the impurity supply layer 60 of the wirings 34 and the impurity supply layer 60 needs to be provided. Furthermore, when the pixel transistor is a p-type MOSFET, a polysilicon layer into which acceptor impurities are ion-implanted is used as the impurity supply layer 60. In this case, the impurity supply layer 60 is provided separately from the wirings 34 by performing a dedicated process. Furthermore, by using part of the wirings 32 as the impurity supply layer 60, the number of wirings can be reduced, thereby suppressing an increase in parasitic capacitance. Furthermore, if a part of the wiring 32 is not used as the impurity supply layer 60, the degree of freedom in design increases.

[0099] The photodetector 1 according to the sixth embodiment also provides the same effects as those of the photodetector 1 according to the first embodiment.

[0100] Seventh Embodiment 1. Application Example to Electronic Devices Next, an electronic device 100 according to a seventh embodiment of the present technology shown in Fig. 16 will be described. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, for example, an electronic device such as a camera, but is not limited thereto. The electronic device 100 also includes the above-described photodetector device 1 as the solid-state imaging device 101.

[0101] An optical lens (optical system) 102 focuses image light (incident light 106) from a subject onto the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. A shutter device 103 controls the light irradiation period and light blocking period of the solid-state imaging device 101. A drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Signal transfer from the solid-state imaging device 101 is performed in accordance with the drive signal (timing signal) supplied from the drive circuit 104. A signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0102] The electronic device 100 is not limited to a camera, but may be other electronic devices, such as an imaging device such as a camera module for a mobile device such as a mobile phone.

[0103] Furthermore, the electronic device 100 can be provided with, as the solid-state imaging device 101, a photodetector 1 relating to any of the first to sixth embodiments and modified versions of those embodiments, or a photodetector 1 relating to a combination of at least two of the first to sixth embodiments and modified versions of those embodiments.

[0104] [Other Embodiments] As described above, the present technology has been described by the first to seventh embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present technology. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0105] For example, it is also possible to combine the respective technical concepts described in the first to seventh embodiments. For example, the impurity supply layer 60 according to the fifth embodiment is configured by a solid-phase diffusion layer, but such a technical concept can be applied to the impurity supply layer 60 described in the first to fourth embodiments and the sixth embodiment. Furthermore, for example, the impurity supply layer 60 according to the seventh embodiment is provided separately from the wiring 34, but such a technical concept can be applied to the impurity supply layer 60 described in the first to sixth embodiments, and various combinations according to the respective technical concepts are possible.

[0106] Furthermore, this technology can be applied to photodetection devices in general, including not only the solid-state imaging device as the image sensor described above but also distance measurement sensors that measure distance, also known as ToF (Time of Flight) sensors. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight from when the light is emitted until when the reflected light is received. The gate electrode structure described above can be adopted as the structure of this distance measurement sensor.

[0107] Furthermore, for example, the materials cited as constituting the above-mentioned components may contain additives, unintentional impurities, and the like.

[0108] As such, the present technology naturally includes various embodiments not described herein. Therefore, the technical scope of the present technology is defined only by the invention-specifying matters described in the claims that are appropriate from the above description.

[0109] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0110] Note that the present technology may be configured as follows: (1) A photodetector comprising: an insulating film, and a wiring layer having an impurity supply layer and an extension portion provided in the insulating film; a first semiconductor layer including a plurality of transistors each having a gate electrode, the first surface being in contact with the insulating film of the wiring layer; and a second semiconductor layer overlapping the first semiconductor layer and the wiring layer along a thickness direction and including a photoelectric conversion element, wherein the first semiconductor layer includes a plurality of semiconductor regions separated from each other, and a pair of main electrode regions and a channel formation region of the transistor are configured in the semiconductor region, the channel formation region has the first surface, a second surface opposite to the first surface, and a third surface and a fourth surface connecting the first surface and the second surface, the gate electrode faces the second surface, the third surface, and the fourth surface via a gate insulating film, the extension portion connects the gate electrode and the impurity supply layer, and the gate electrode and the extension portion contain impurities supplied from the impurity supply layer. (2) The photodetector according to (1), wherein the gate electrode contains an impurity ion-implanted from the side opposite to the impurity supply layer. (3) The photodetector according to (2), wherein, when the first surface side of the first semiconductor layer is the lower side and the second surface side is the upper side, the uppermost position in the gate electrode to which the impurity supplied from the impurity supply layer reaches is higher than the lowermost position in the gate electrode to which the ion-implanted impurity reaches. (4) The photodetector according to any one of (1) to (3), wherein the extension portion includes a first extension portion connected to a portion of the gate electrode facing the third surface and a second extension portion connected to a portion of the gate electrode facing the fourth surface. (5) The photodetector according to (4), wherein the impurity supply layer connects the first extension portion and the second extension portion. (6) The photodetector according to (4), wherein the impurity supply layer is provided separately for each of the first extension portion and the second extension portion. (7) The photodetector according to any one of (4) to (6), wherein the end faces of the first extension portion and the second extension portion, which are located on the opposite side to the gate electrode side, are entirely connected to the impurity supply layer.(8) The photodetector according to any one of (4) to (6), wherein only a portion of each of the end faces of the first extension portion and the second extension portion located on the opposite side to the gate electrode is connected to the impurity supply layer. (9) The photodetector according to (4) or (6), wherein the impurity supply layer is connected to a side surface of the extension portion. (10) The photodetector according to any one of (1) to (9), wherein the impurity supply layer is a polysilicon layer into which the impurity is ion-implanted or a solid-phase diffusion layer containing the impurity. (11) The photodetector according to any one of (1) to (10), wherein the transistor includes a first transistor capable of forming a channel of a first conductivity type and a second transistor capable of forming a channel of a second conductivity type, the impurity supply layer includes a first impurity supply layer that supplies an impurity to a gate electrode of the first transistor and a second impurity supply layer that supplies an impurity to a gate electrode of the second transistor, the impurity supplied from the first impurity supply layer to the gate electrode of the first transistor is an impurity that makes a semiconductor of a first conductivity type, and the impurity supplied from the second impurity supply layer to the gate electrode of the second transistor is an impurity that makes a semiconductor of a second conductivity type. (12) The photodetector according to (11), wherein the first impurity supply layer and the second impurity supply layer are provided at the same depth position along a thickness direction of the wiring layer. (13) The photodetector according to (11), wherein the first impurity supply layer and the second impurity supply layer are provided at different depth positions along a thickness direction of the wiring layer.(14) A photodetector and an optical system that forms an image of light from a subject on the photodetector, the photodetector comprising: an insulating film, and a wiring layer having an impurity supply layer and an extension portion provided in the insulating film; a first semiconductor layer in which a plurality of transistors each having a gate electrode are configured, and a first surface of the first semiconductor layer is in contact with the insulating film of the wiring layer; and a second semiconductor layer that overlaps the first semiconductor layer and the wiring layer along a thickness direction and in which a photoelectric conversion element is configured, the first semiconductor layer including a plurality of semiconductor regions separated from each other, and a pair of main electrode regions and a channel formation region of the transistor are configured in the semiconductor region, the channel formation region having the first surface, a second surface opposite to the first surface, and a third surface and a fourth surface connecting the first surface and the second surface, the gate electrode facing the second surface, the third surface and the fourth surface via a gate insulating film, the extension portion connecting the gate electrode and the impurity supply layer, the gate electrode and the extension portion containing impurities supplied from the impurity supply layer. electronic equipment.

[0111] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0112] REFERENCE SIGNS LIST 1 Photodetector 20 Semiconductor layer 21 Semiconductor region 22 Semiconductor region 31, 51 Insulating film 34, 53 Wiring 40 Semiconductor layer 41, 42, 43, 44, 45 Semiconductor region 42 Channel formation region 60, 60n, 60p Impurity supply layer 70, 70n, 70p Extension portion 70a First extension portion 70b Second extension portion 71 End surface 100 Electronic device 102 Optical system AMP Amplifying transistor F Gate insulating film AMPG, SELG, G1, G2 Gate electrode PD Photoelectric conversion element RST Reset transistor S1 First surface S2 Second surface S3 Third surface S4 Fourth surface SEL Select transistor T1, T2 Transistor

Claims

1. A photodetector comprising: an insulating film, a wiring layer having an impurity supply layer and an extension portion provided in the insulating film; a first semiconductor layer including a plurality of transistors each having a gate electrode, the first surface being in contact with the insulating film of the wiring layer; and a second semiconductor layer overlapping the first semiconductor layer and the wiring layer along a thickness direction and including a photoelectric conversion element, the first semiconductor layer including a plurality of semiconductor regions separated from each other, the semiconductor region including a pair of main electrode regions and a channel formation region of the transistor, the channel formation region including the first surface, a second surface being a surface opposite to the first surface, and a third surface and a fourth surface connecting the first surface and the second surface, the gate electrode facing the second surface, the third surface and the fourth surface via a gate insulating film, the extension portion connecting the gate electrode and the impurity supply layer, the gate electrode and the extension portion including impurities supplied from the impurity supply layer.

2. The photodetector according to claim 1, wherein the gate electrode contains impurities ion-implanted from the side opposite to the impurity supply layer.

3. The photodetector device of claim 2, wherein, when the first surface side of the first semiconductor layer is the lower side and the second surface side is the upper side, the uppermost position on the gate electrode that the impurity supplied from the impurity supply layer reaches is higher than the lowermost position on the gate electrode that the ion-implanted impurity reaches.

4. The photodetector device of claim 1, wherein the extension portion includes a first extension portion connected to a portion of the gate electrode facing the third surface, and a second extension portion connected to a portion of the gate electrode facing the fourth surface.

5. The photodetector according to claim 4, wherein the impurity supply layer connects the first extension portion and the second extension portion.

6. The photodetector according to claim 4, wherein the impurity supply layer is provided separately for each of the first extension portion and the second extension portion.

7. The photodetector device according to claim 4, wherein each of the end faces of the first extension portion and the second extension portion located opposite the gate electrode side is entirely connected to the impurity supply layer.

8. The photodetector device according to claim 4, wherein each of the end faces of the first extension portion and the second extension portion located opposite the gate electrode side has only a portion connected to the impurity supply layer.

9. The photodetector according to claim 4, wherein the impurity supply layer is connected to a side surface of the extension portion.

10. The photodetector according to claim 1, wherein the impurity supply layer is a polysilicon layer into which the impurity is ion-implanted or a solid-phase diffusion layer containing the impurity.

11. The photodetector device of claim 1, wherein the transistors include a first transistor capable of forming a channel of a first conductivity type and a second transistor capable of forming a channel of a second conductivity type; the impurity supply layer includes a first impurity supply layer that supplies an impurity to a gate electrode of the first transistor and a second impurity supply layer that supplies an impurity to a gate electrode of the second transistor; the impurity supplied from the first impurity supply layer to the gate electrode of the first transistor is an impurity that makes a semiconductor of a first conductivity type; and the impurity supplied from the second impurity supply layer to the gate electrode of the second transistor is an impurity that makes a semiconductor of a second conductivity type.

12. The photodetector according to claim 11, wherein the first impurity supply layer and the second impurity supply layer are provided at the same depth along the thickness direction of the wiring layer.

13. The photodetector according to claim 11, wherein the first impurity supply layer and the second impurity supply layer are provided at different depths along the thickness direction of the wiring layer.

14. A photodetector and an optical system for forming an image of light from a subject on the photodetector, the photodetector comprising: an insulating film, a wiring layer having an impurity supply layer and an extension portion provided in the insulating film; a first semiconductor layer including a plurality of transistors each having a gate electrode, the first surface of the first semiconductor layer being in contact with the insulating film of the wiring layer; and a second semiconductor layer overlapping the first semiconductor layer and the wiring layer along a thickness direction and including a photoelectric conversion element; the first semiconductor layer including a plurality of semiconductor regions separated from each other, the semiconductor region including a pair of main electrode regions and a channel formation region of the transistor; the channel formation region including the first surface, a second surface opposite to the first surface, and a third surface and a fourth surface connecting the first surface and the second surface; the gate electrode facing the second surface, the third surface and the fourth surface via a gate insulating film; the extension portion connecting the gate electrode and the impurity supply layer; and the gate electrode and the extension portion including impurities supplied from the impurity supply layer. electronic equipment.

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