Gate-definition type quantum-dot structure, semiconductor quantum computer, and method for controlling gate-definition type quantum-dot structure

Abstract

A gate-definition type quantum-dot structure 1 includes: a quantum-well substrate for confining electrons in a quantum dot; a lead-inducing gate 12 for applying a voltage to a lead 17, which is a supply source of the electrons to the quantum dots, and extending the lead 17 to the vicinity of the quantum dots; a lead-quantum dot barrier-gate 13 for controlling entry and exit of the electrons between the lead 17 and the quantum dots; a plunger gate 14 for adjusting the number of the electrons in the quantum dot; an inter quantum-dot barrier-gate 15 for adjusting strength of tunnel coupling between the adjacent quantum dots; a screening gate 11 for shielding the voltage applied to the lead-quantum dot barrier-gate 13, the plunger gate 14, and the inter quantum-dot barrier-gate 15; and a charge meter for detecting the state of the quantum bit represented by the electrons confined in the quantum dot. The screening gate 11, the lead-inducing gate 12, the lead-quantum dot barrier-gate 13, the plunger gate 14, and the inter quantum-dot barrier-gate 15 are laminated on the quantum-well substrate. The lead 17 is tunnel-coupled with all the quantum dots.

Description

Gate-defined quantum dot structure, semiconductor quantum computer, and method for controlling gate-defined quantum dot structure

[0001] The present invention relates to a gate-defined quantum dot structure, a semiconductor quantum computer, and a method for controlling a gate-defined quantum dot structure.

[0002] One method for realizing quantum computers is semiconductor quantum computers that use semiconductor spin qubits. Because semiconductor quantum computers are compatible with integrated circuit technology used in existing industries, they are expected to be suitable for implementing large-scale quantum computers in the future, and research and development into them is becoming increasingly active.

[0003] A semiconductor spin qubit uses the spin 1 / 2 state of a single electron confined within a quantum dot, such as a silicon quantum dot, as the qubit. In this case, an electron with spin down (|↓>) represents the qubit 0 state, and an electron with spin up (|↑>) represents the qubit 1 state.

[0004] Here, quantum dots are zero-dimensional structures in which electrons are spatially confined in all three dimensions, restricting their movement. Quantum dots are also called artificial atoms due to their properties, and electrons can be inserted and removed one by one. Because quantum dots can thus control and detect electron spins at the individual level, they are attracting attention as a physical system for implementing semiconductor quantum computers.

[0005] Semiconductor quantum computers use a structure (hereinafter referred to as a "gate-defined quantum dot structure") that can confine a single electron using a gate electrode fabricated by microfabrication. As mentioned above, a quantum dot is an artificially constructed zero-dimensional structure that confines electrons to a region of approximately the de Broglie wavelength. In a gate-defined quantum dot, one-way confinement is formed by the substrate structure, and the remaining two-way confinement is formed by voltages applied to metal micro-gate electrodes fabricated on the substrate surface. This gate voltage allows precise control of the number of electrons and tunnel coupling.

[0006] The spin 1 / 2 degree of freedom of a single electron is the most typical quantum mechanical two-level system, and has several advantages for implementing qubits. First, because spin is a magnetic degree of freedom, it is insensitive to charge noise, which is the biggest problem in semiconductor environments, and has the advantage of a long coherence time. Furthermore, because the confining potential of gate-defined quantum dots can be electrically controlled, it is possible to quickly and flexibly control the parameters required for qubit operations, thereby enabling the implementation of single-qubit and two-qubit operations, which are important in quantum computers.

[0007] One of the challenges in semiconductor quantum computers is the large-scale integration of quantum dot structures (i.e., increasing the number of controllable quantum bits). Conventionally, the number of quantum dots that could be realized was around 1 to 4. However, recently, six quantum dots (e.g., Non-Patent Document 1) and 12 quantum dots (e.g., Non-Patent Document 2) have been reported.

[0008] Stephan G. J. Philips, Mateusz T. Madzik, Sergey V. Amitonov, Sander L. de Snoo, Maximilian Russ, Nima Kalhor, Christian Volk, William I. L. Lawrie, Delphine Brousse, Larysa Tryputen, Brian Paquelet Wuetz, Amir Sammak, Menno Veldhorst, Giordano Scappucci & Lieven M. K. Vandersypen, "Universal control of a six-qubit quantum processor in silicon", Nature volume 609, pages919-924 (2022)Samuel Neyens, Otto Zietz, Thomas Watson, Florian Luthi, Aditi Nethwewala, Hubert George, Eric Henry, Andrew Wagner, Mohammad Islam, Ravi Pillarisetty, Roza Kotlyar, Kent Millard, Stefano Pellerano, Nathan Bishop, Stephanie Bojarski, Jeanette Roberts, and James S. Clarke, “Probing single electrons across 300 mm spin qubit wafers”, Nature volume 629, pages80-85 (2024)Elzerman J, Hanson R, Willems van Beveren L, Witkamp B, Vandersypen L and Kouwenhoven L P, “Single-shot read-out of an individual electron spin in a quantum dot”, Nature volume 430, pages431-435 (2004)M. Veldhorst, C. H. Yang, J. C. C. Hwang, W.Huang, JP Dehollain, JT Muhonen, S. Simmons, A. Laucht, FE Hudson, KM Itoh, A. Morello & AS Dzurak, “A two-qubit logic gate in silicon”, Nature volume 526, pages410-414 (2015)AMJ Zwerver, T. Krahenmann, TF Watson, L. Lampert, HC George, R. Pillarisetti, SA Bojarski, P. Amin, SV Amitonov, JM Boter, R. Caudillo, D. Correas-Serrano, JP Dehollain, G. Droulers, EM Henry, R. Kotlyar, M. Lodari, F. Luthi, DJ Michalak, BK Mueller, S. Neyens, J. Roberts, N. Samkharadze, G. Zheng, JS Clarke, “Qubits made by advanced semiconductor manufacturing”, Nature Electronics, volume 5, pages 184-190 (2022).

[0009] The quantum dot structures described in Non-Patent Documents 1 and 2 have quantum dots arranged in a linear array, with electron sources (hereinafter also referred to as "leads") provided at both ends of this array (hereinafter also referred to as "quantum dot array"). When such a structure is adopted, there is a problem in that while quantum bits located near both ends of the quantum dot array (i.e., close to the leads) can be accurately and quickly initialized and read out, quantum bits located near the center of the quantum dot array (far from the leads) are difficult to accurately and quickly initialize and read out. This leads to the problem that large-scale integration of quantum bits is difficult.

[0010] The present invention has been made in view of the above circumstances, and its purpose is to provide a highly integrated semiconductor quantum computer capable of accurately and quickly initializing and reading out quantum bits, and a gate-defined quantum dot structure that realizes the same.

[0011] To solve the above problems, a gate-defined quantum dot structure according to one embodiment of the present disclosure includes a quantum well substrate that confines electrons in the quantum dots, a lead-inducing gate that extends a lead, which is a source of electrons for the quantum dots, to the vicinity of the quantum dots, a lead-to-quantum-dot barrier gate that controls the flow of electrons between the lead and the quantum dot, a plunger gate that adjusts the number of electrons in the quantum dot, an inter-quantum-dot barrier gate that adjusts the strength of the tunnel coupling between adjacent quantum dots, a screening gate that blocks voltages applied to the lead-inducing gate, the lead-to-quantum-dot barrier gate, the plunger gate, and the inter-quantum-dot barrier gate, and a charge meter that detects the state of a quantum bit represented by an electron confined in the quantum dot. The screening gate, the lead-inducing gate, the lead-to-quantum-dot barrier gate, the plunger gate, and the inter-quantum-dot barrier gate are stacked on the quantum well substrate. The leads are tunnel-coupled to all of the quantum dots.

[0012] In one embodiment, the screening gate, lead inducing gate, lead-to-quantum-dot barrier gate, plunger gate and inter-quantum-dot barrier gate may all be stacked on the quantum well substrate at different heights.

[0013] In one embodiment, the ratio of the number of charge meters to the number of plunger gates may be greater than or equal to 1 / 3 and less than or equal to 1.

[0014] In one embodiment, the quantum well substrate has a sandwich structure in which a Si layer is sandwiched between SiGe layers and bonded together, or a sandwich structure in which a Ge layer is sandwiched between SiGe layers and bonded together.

[0015] In one embodiment, the quantum well substrate has a MOS structure.

[0016] Another aspect of the present disclosure is a semiconductor quantum computer, comprising the gate-defined quantum dot structure of any of the previous embodiments.

[0017] Yet another aspect of the present disclosure is a method for controlling a gate-defined quantum dot structure, comprising the steps of controlling the flow of electrons between the leads and the quantum dots by controlling a voltage applied to a lead-to-quantum-dot barrier gate, adjusting the number of electrons in each quantum dot by controlling a voltage applied to a plunger gate, and adjusting the strength of tunnel coupling between adjacent quantum dots by adjusting the voltage applied to the inter-quantum-dot barrier gate.

[0018] Any combination of the above components, and conversion of the present disclosure into an apparatus, method, system, recording medium, computer program, etc., are also effective aspects of the present invention.

[0019] According to the present invention, it is possible to provide a gate-defined quantum dot structure that realizes a highly integrated semiconductor quantum computer that can perform accurate and high-speed initialization and readout of quantum bits.

[0020] 9 is a schematic diagram of a gate-defined quantum dot structure (part) according to a comparative example. It is a scanning microscope photograph of the gate-defined quantum dot structure of FIG. 1. It is a diagram illustrating the principle of initialization and readout of a quantum bit using a charge meter. It is a diagram illustrating the principle of initialization and readout of a quantum bit using a charge meter. It is a scanning microscope photograph of a gate-defined quantum dot structure according to a comparative example. It is a schematic diagram of a gate-defined quantum dot structure according to a first embodiment. It is a cross-sectional view of a gate-defined quantum dot structure. The left diagram of FIG. 9 is a diagram extracting the part surrounded by the dotted line in FIG. 7. The center diagram of FIG. 9 is a cross-sectional view taken along line A-A' of the left diagram. The right diagram of FIG. 9 is a cross-sectional view taken along line B-B' of the left diagram. It is a scanning microscope photograph of each layer of the gate-defined quantum dot structure according to the first embodiment. It is a diagram in which the layers of FIG. 10 are superimposed.

[0021] The present disclosure will be described below with reference to the drawings based on preferred embodiments. The embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention. The same or equivalent components, parts, and processes shown in each drawing are designated by the same reference numerals, and redundant description will be omitted where appropriate. The scale and shape of each part shown in each drawing are set for convenience to facilitate explanation and should not be interpreted as limiting unless otherwise specified. Furthermore, when terms such as "first" and "second" are used in this specification or claims, unless otherwise specified, these terms do not represent any order or importance, but are merely used to distinguish one configuration from another. Furthermore, some components that are not important for explaining the embodiments are omitted from each drawing.

[0022] Before describing specific embodiments, basic findings will be described with reference to FIGS. 1 to 4. In the drawings in this specification, the xy plane is taken as the horizontal plane, and the z axis is taken as the vertically upward direction. FIG. 1 is a schematic diagram of a gate-defined quantum dot structure 101 (part) according to a comparative example related to this embodiment. FIG. 2 is a scanning electron microscope photograph of the gate-defined quantum dot structure 101 of FIG. 1. In FIG. 2, quantum dots QD1, QD2, and QD3, leads L1 and L2, and charge meter CM are indicated by leader lines. Note that these are not visible in the scanning electron microscope photograph (surface), but are located in lower layers.

[0023] The gate-defined quantum dot structure 101 comprises a quantum well substrate QS, plunger gates P1, P2, P3, barrier gates B1, B2, B3, B4, a screening gate S, a charge meter CM, leads L1, L2, and a lead induction gate.

[0024] The quantum well substrate QS has a sandwich structure in which a Si layer (silicon layer) is sandwiched and bonded between SiGe layers (silicon germanium layers). Because the SiGe layer has a higher potential than the Si layer, electrons are localized in the Si layer. Because the lattice constants of Si and SiGe are different, the thin Si grown between the SiGe layers (below the critical thickness) does not lattice match, resulting in distortion. This distortion changes the electronic band structure, forming a quantum well potential. In this way, electrons are confined in the z-axis direction within the quantum well substrate QS.

[0025] Hereinafter, the x-axis is taken parallel to the quantum dot array. A screening gate S is stacked on an area of ​​the quantum well substrate QS where the quantum dot array, charge meters, and leads are not to be formed. The screening gate S is, for example, a flat metal electrode.

[0026] Furthermore, plunger gates P1, P2, and P3 and barrier gates B1, B2, B3, and B4 are stacked on the quantum well substrate QS. As shown in the figure, the plunger gates and barrier gates are alternately arranged in the x-direction as B1, P1, B2, P2, B3, P3, and B4. The plunger gates P1, P2, and P3 and the barrier gates B1, B2, B3, and B4 are, for example, flat metal electrodes. The voltage applied to the plunger gates and barrier gates can be adjusted, for example, in the range of about 1 V, typically in units of about 10-100 μV.

[0027] By appropriately setting the voltages applied to the plunger gates P1, P2, and P3 and the barrier gates B1, B2, B3, and B4, quantum dots QD1, QD2, and QD3 can be formed in the regions below the plunger gates P1, P2, and P3 in the quantum well substrate QS. The regions below the screening gate S are shielded from the voltages applied to the plunger gates P1, P2, and P3 and the barrier gates B1, B2, B3, and B4, so quantum dots are not formed in these regions. Therefore, this structure allows electrons to be confined in all directions (x, y, and z) within the quantum well substrate QS (i.e., zero-dimensionally). Figure 1 shows that electrons E1 with an up spin, electron E2 with an up spin, and electron E3 with a down spin are confined in the quantum dots QD1, QD2, and QD3, respectively.

[0028] Furthermore, the number of electrons in each quantum dot can be adjusted by adjusting the voltages applied to the plunger gates P1, P2, and P3, and the strength of the tunnel coupling between adjacent quantum dots or between a quantum dot and a lead can be adjusted by adjusting the voltages applied to the barrier gates B1, B2, B3, and B4.

[0029] As shown in FIG. 2 , a charge meter CM is installed on the opposite side of the quantum dot array of quantum dots QD1, QD2, and QD3 in the y-axis direction. The charge meter CM is formed, for example, of quantum dots. The charge meter QM is electrically insulated from the plunger gates P1, P2, and P3 and the barrier gates B1, B2, B3, and B4. The charge meter QM is capacitively coupled to the plunger gates P1, P2, and P3 and the barrier gates B1, B2, B3, and B4. In particular, the charge meter QM is capacitively coupled to the quantum dots QD1, QD2, and QD3, but is generally not directly tunnel-coupled. The charge meter QM can be used to detect the amount of charge of the quantum dots QD1, QD2, and QD3 (i.e., whether or not electrons exist in the quantum dots QD1, QD2, and QD3, and, if so, how many electrons there are). Specifically, due to the electrostatic coupling between the quantum dots QD1, QD2, and QD3 and the charge meter QM, when the charge amount of the quantum dots QD1, QD2, and QD3 changes, the electrical conductivity of the charge meter QM changes in response. Therefore, by observing the electrical conductivity signal of the charge meter QM, it is possible to monitor the change in the charge amount of the quantum dots QD1, QD2, and QD3. Based on this, the signal from the charge meter QM can be used to realize quantum bit readout, the principle of which will be described later.

[0030] The leads L1 and L2 are electron sources (i.e., electron reservoirs) for the quantum dots QD1, QD2, and QD3. The leads L1 and L2 extend to the Si layer of the quantum well substrate QS directly below the lead-inducing gate. By controlling the voltage applied to the lead-quantum-dot barrier gate and the voltage applied to the plunger gate to adjust the tunnel coupling and energy difference between the quantum dots and the leads, it is possible to control the flow of electrons between the leads L1 and L2 and the quantum dots QD1, QD2, and QD3.

[0031] Quantum computing requires 1-bit manipulation, 2-bit manipulation, initialization, and readout. Of these, 1-bit manipulation and 2-bit manipulation can be achieved by controlling the voltages applied to plunger gates P1, P2, and P3 and barrier gates B1, B2, B3, and B4. On the other hand, readout is difficult to achieve using direct magnetic measurement. This is because the magnetic moment caused by electron spin is extremely small and precise magnetic measurement is difficult. In response to this, a method has been proposed for initializing and reading out quantum bits by converting magnetic information into electrical information using leads L1 and L2 and a charge meter QM (see, for example, Non-Patent Document 3). The principle behind this method is explained below.

[0032] 3 and 4 are diagrams showing the principle of initialization and readout of a quantum bit using a charge meter. The gate voltage is adjusted so that the Fermi energy of the read is intermediate between the energies of the electrons with up-spin and those with down-spin in the quantum dot.

[0033] First, consider the case where an electron with a spin down exists within the quantum dot. In this case, the quantum bit represented by the electron spin is in a state of 0. Figure 3A shows the energy levels at this time. Figure 3B shows the time change in the charge meter signal observed at this time. The electron with a spin down within the quantum dot is in the ground state, and because its energy is lower than the Fermi energy of the lead, it remains in this ground state within the quantum dot over time. In other words, the electron with a spin down within the quantum dot does not move in or out of the lead. Therefore, the amount of charge within the quantum dot does not change, and the charge meter signal remains constant over time, as shown in Figure 3B. In other words, when the waveform of Figure 3B is observed within a given time period by observing the charge meter signal, it is clear that the quantum bit is in a state of 0. In this way, the state of quantum bit 0 is read out.

[0034] Next, consider the case where an electron with an up-spin exists within the quantum dot. In this case, the quantum bit state represented by the electron spin is 1. Because the electron with an up-spin within the quantum dot is in an excited state, it can move to a lower-energy lead via tunnel junction. Subsequently, an electron is again supplied from the lead to the quantum dot via tunnel junction, resulting in a down-spin (qubit state = 0) within the quantum dot. Figure 4A shows the energy levels when an electron with an up-spin within the quantum dot moves to the lead at time t = T1 and is then supplied from the lead at time t = T2. Figure 4B shows the time evolution of the charge meter signal observed at this time. An electron is present in the quantum dot from time t = 0 to T1 and after time t = T2, but is absent from time t = T1 to T2. In response to such changes in the amount of charge within the quantum dot, the charge meter signal exhibits the time evolution shown in Figure 4B. That is, when the waveform of Figure 4B is observed within a given time period, the quantum bit state is determined to be 1. In this way, the state of quantum bit 1 is read out. At this time, the state of quantum bit 1 transitions to the 0 state, and therefore the quantum bit is also initialized at the same time.

[0035] As explained above, by using leads and charge meters, magnetic measurements can be replaced with electrical measurements, enabling the readout of single electron spins with extremely small magnetization. Furthermore, using a similar principle, single electron spin initialization can be achieved. However, from an implementation standpoint, there are limitations to the arrangement of leads and charge meters.

[0036] In the above example, the quantum well substrate QS has a sandwich structure in which a Si layer is sandwiched between SiGe layers and bonded together. However, the quantum well substrate QS is not limited to this, and may have a sandwich structure in which a Ge layer is sandwiched between SiGe layers and bonded together.

[0037] Furthermore, the quantum well substrate QS may have a MOS structure. For example, in the MOS structure described in Non-Patent Document 4, a thin (about 10 nm) SiO ２A quantum well-like two-dimensionally confined conduction layer is formed at the interface between the substrate and the Si. Therefore, if a gate electrode is fabricated on the substrate surface and an appropriate voltage is applied, the device will function as a gate-defined quantum dot sample. The leads are also fabricated by ion implantation, similar to this embodiment, so the design concept of the gate electrode in this embodiment can be applied as is. Fabrication using a 300 mm line has also been reported (see, for example, Non-Patent Document 5).

[0038] Figure 5 is a scanning microscope photograph of a gate-defined quantum dot structure described in Non-Patent Document 1 as a comparative example of this embodiment. Six quantum dots are arranged in a linear array (quantum dot array). Figure 5 shows a top view of the sample, with charge meters and lead-inducing gates visible near both ends of the quantum dot array. In this quantum well, leads are formed below the lead-inducing gate in a region where no screening gate exists.

[0039] Figure 6 is a schematic diagram of a gate-defined quantum dot structure described in Non-Patent Document 2, also as a comparative example to this embodiment. Here, 12 quantum dots are arranged in a linear row (quantum dot row). Figure 6 shows a top view of the sample, with lead-inducing gates visible near both ends of the quantum dot row. In this quantum well, leads are formed below the lead-inducing gates in areas where no screening gates exist. Four charge meters are arranged, one for every three quantum dots.

[0040] In both quantum dot structures shown in Figures 5 and 6, leads serving as electron sources are formed near both ends of the quantum dot array. This structure is adopted because: · The pitch of the plunger gates and barrier gates on the quantum well substrate is approximately 100 nm, while the leads are large, ranging from several μm to 10 μm. Because it is difficult to locate the ion implantation region near the quantum dots, it is necessary to extend the leads from the ion implantation region fabricated approximately 10 μm away using a gate induction gate; · The periphery of the quantum well substrate (other than near both ends) is densely packed with gate control wiring. For these reasons, it is difficult to install leads or charge meters (especially leads) in locations other than near both ends of the quantum dot array (especially near the center of the quantum well substrate in the x-direction). Due to these limitations on the placement of leads and charge meters, in configurations like Figures 5 and 6, it is difficult for quantum dots near the center of the quantum dot array, especially those near the center, to directly transfer electrons between them. Therefore, quantum dots near the center of such quantum dot arrays cannot be accurately initialized or read at high speed. These limitations make further large-scale integration difficult.

[0041] [First embodiment] A first embodiment will be described with reference to Figs. 7 to 9. Fig. 7 is a schematic diagram of a gate-defined quantum dot structure 1 according to a first embodiment of the present disclosure, specifically a perspective view of the gate-defined quantum dot structure 1 as seen from above. Fig. 8 is a cross-sectional view of the gate-defined quantum dot structure 1. The left diagram of Fig. 9 is a diagram of the portion surrounded by the dotted line in Fig. 7 extracted. The center diagram of Fig. 9 is a cross-sectional view taken along line A-A' in the left diagram. The right diagram of Fig. 9 is a cross-sectional view taken along line B-B' in the left diagram.

[0042] The gate-defined quantum dot structure 1 includes a quantum well substrate QS, a screening gate 11, a lead induction gate 12 that extends a lead 17 to the vicinity of the quantum dot, a lead-quantum dot barrier gate 13, a plunger gate 14, an inter-quantum dot barrier gate 15, and a charge meter 16. A quantum dot is formed below each plunger gate 14, and electrons trapped therein function as quantum bits.

[0043] The quantum well substrate QS has a sandwich structure in which a Si layer is sandwiched between SiGe layers. However, since SiGe is unstable, the upper surface of the quantum well substrate QS is covered with a thin (approximately 2 nm) Si layer (which is actually oxidized in the atmosphere to become SiO ２ The Si layer on which the quantum dots (QDs) are disposed is typically 5 to 15 nm thick. The SiGe layers sandwiching the Si layer are typically 30 to 80 nm thick. The ion implantation region 7 is used to create a metallic conductive portion in the semiconductor substrate by ion implantation (lead). Metallic wiring 18 extending from the outside of the sample is disposed on the ion implantation region 7. An insulating layer 19 is provided between the lead-inducing gate 12 and the ion implantation region 7 to prevent electrical short-circuiting between them.

[0044] Five layers, namely, a screening gate 11, a lead-inducing gate 12, a lead-to-quantum-dot barrier gate 13, a plunger gate 14, and an inter-quantum-dot barrier gate 15, are stacked on the quantum well substrate in this order from the bottom up. That is, these gates form a five-layer stacked structure. In particular, it should be noted that the lead 17 is extended in the x-direction of the gate-defined quantum dot structure 1 by the lead-inducing gate 12, and is tunnel-coupled to all of the quantum dots.

[0045] The screening gate 11, the lead inducing gate 12, the lead-quantum dot barrier gate 13, the plunger gate 14, and the quantum dot barrier gate 15 may all be stacked on the quantum well substrate at different heights.

[0046] 7, the number of plunger gates 14 is 12, but is not limited to this and may be any number. The inter-quantum-dot barrier gates 15 are disposed between adjacent plunger gates 14 so as to separate these plunger gates 14. In the example of FIG. 7, the number of inter-quantum-dot barrier gates 15 is 11.

[0047] 7, the number of charge meters 16 is four. That is, one charge meter 16 is arranged for three plunger gates 14. However, the number of charge meters is not limited to this, and, for example, one charge meter 16 may be arranged for one or two plunger gates 14. Alternatively, one charge meter 16 may be arranged for four or more plunger gates 14. However, it should be noted that if the number of charge meters is too small relative to the number of plunger gates, accurate readout of the quantum bit becomes difficult.

[0048] For example, if the number of plunger gates 14 for one charge meter 16 is four or more, a problem occurs in that it is difficult to use in terms of sensitivity. Furthermore, there have been no reported examples of quantum bit samples actually configured with such a ratio of numbers.

[0049] Preferably, the ratio of the number of charge meters 16 to the number of plunger gates 14 is greater than or equal to 1 / 3 and less than or equal to 1.

[0050] The quantum well substrate has a sandwich structure in which a Si layer is sandwiched between SiGe layers, and the quantum well substrate confines electrons in the Si layer.

[0051] The screening gate 11 is, for example, a flat metal electrode, and shields unnecessary voltages applied to the lead-quantum-dot barrier gate 13, plunger gate 14, and inter-quantum-dot barrier gate 15, and confines electrons in the xy directions of the quantum well substrate.

[0052] The lead 17 is a source of electrons to the quantum dot formed below the plunger gate 14. The lead 17 is extended to the Si layer of the quantum well substrate by applying a voltage to the lead induction gate 12. By controlling the voltage applied to the lead-quantum dot barrier gate 13, the flow of electrons between the lead 17 and the quantum dot can be controlled.

[0053] The plunger gate 14 is, for example, a flat metal electrode. The number of electrons in each quantum dot can be adjusted by adjusting the voltage applied to the plunger gate 14.

[0054] The inter-quantum dot barrier gate 15 is, for example, a flat metal electrode. By adjusting the voltage applied to the inter-quantum dot barrier gate 15, it is possible to adjust the strength of the tunnel coupling between adjacent quantum dots.

[0055] The charge meter 16 is formed of, for example, quantum dots. There is electrical insulation between the charge meter 16 and the plunger gate 14 and the inter-quantum dot barrier gate 15. The charge meter 16 is electrostatically coupled to the plunger gate 14 and the inter-quantum dot barrier gate 15. The charge meter 12 can be used to detect the amount of charge on the quantum dot (i.e., the presence or absence of electrons in the quantum dot). Based on the principle described with reference to FIGS. 3 and 4 , the signal from the charge meter 14 can be used to initialize and read out the quantum bit.

[0056] Figure 10 shows scanning microscope photographs of each layer of the gate-defined quantum dot structure 1. Figure 10A is a photograph of the screening gate 11. Figure 10B is a photograph of the lead induction gate 12. Figure 10C is a photograph of the lead-quantum-dot barrier gate 13. Figure 10D is a photograph of the plunger gate 14. Figure 10E is a photograph of the inter-quantum-dot barrier gate 15.

[0057] FIG. 11 shows all the layers of FIG. 10 superimposed together.

[0058] According to this embodiment, the screening gate 11, the lead induction gate 12, the lead-quantum dot barrier gate 13, the plunger gate 14, and the quantum dot barrier gate 15 are configured into a five-layer stack structure, thereby enabling the lead 17 to tunnel-couple to all of the quantum dots. This structure contrasts with the comparative example structures shown in FIGS. 1-2, 5, and 6, i.e., structures in which the leads are arranged near both ends of the quantum dot array. Because the lead 17 is thus tunnel-coupled to all of the quantum dots, the accuracy and speed of quantum bit initialization and readout are not limited, regardless of the number of quantum dots. Therefore, this embodiment can provide a gate-defined quantum dot structure that realizes a highly integrated semiconductor quantum computer capable of accurate and high-speed quantum bit initialization and readout.

[0059] Second Embodiment A second embodiment of the present disclosure is a semiconductor quantum computer, which includes the gate-defined quantum dot structure according to any of the previous embodiments.

[0060] According to this embodiment, it is possible to realize a highly integrated semiconductor quantum computer that can perform accurate and high-speed initialization and reading of quantum bits.

[0061] A third embodiment of the present disclosure is a method for controlling a gate-defined quantum dot structure. This method is a method for controlling the gate-defined quantum dot structure described in any of the previous embodiments, and includes the steps of controlling the flow of electrons between the lead-inducing gate 12 and the quantum dots by controlling a voltage applied to the lead-to-quantum-dot barrier gate 13, adjusting the number of electrons in each quantum dot by controlling a voltage applied to the plunger gate 14, and adjusting the strength of tunnel coupling between adjacent quantum dots by adjusting a voltage applied to the inter-quantum-dot barrier gate 15.

[0062] According to this embodiment, it is possible to control a gate-defined quantum dot structure that realizes a highly integrated semiconductor quantum computer that can perform accurate and high-speed initialization and readout of quantum bits.

[0063] Any combination of the above-described embodiments and modifications is also useful as an embodiment of the present disclosure. A new embodiment resulting from the combination has the combined effects of the respective embodiments and modifications.

[0064] When understanding the abstract technical ideas of the embodiments and modifications, the technical ideas should not be interpreted as being limited to the contents of the embodiments and modifications. The above-described embodiments and modifications are merely illustrative examples, and many design modifications, such as changes, additions, and deletions of components, are possible. In the embodiments, the contents in which such design modifications are possible are emphasized by adding the notation "embodiment." However, design modifications are also permitted even in contents without such notation.

[0065] The present invention can be used in a gate-defined quantum dot structure, a semiconductor quantum computer, and a method for controlling a gate-defined quantum dot structure.

[0066] 1: Gate-defined quantum dot structure. 11: Screening gate. 12: Lead induction gate. 13: Barrier gate between lead and quantum dot. 14: Plunger gate. 15: Barrier gate between quantum dots. 16: Charge meter. 17: Lead. 18: Wiring. 19: Insulating layer. 101: Gate-defined quantum dot structure. B1: Barrier gate. B2: Barrier gate. B3: Barrier gate. CM: Charge meter. E1: Electron. E2: Electron. E3: Electron. L1: Lead. L2: Lead. QD: Quantum dot. QD1: Quantum dot. QD2: Quantum dot. QD3: Quantum dot. QS: Quantum well substrate. S: Screening gate.

Claims

a lead-to-quantum-dot barrier gate that controls the flow of electrons between the lead and the quantum dot; a plunger gate that adjusts the number of electrons in the quantum dot; an inter-quantum-dot barrier gate that adjusts the strength of the tunnel coupling between adjacent quantum dots; a screening gate that blocks voltages applied to the lead-to-quantum-dot barrier gate, the plunger gate, and the inter-quantum-dot barrier gate; and a charge meter that detects the state of a quantum bit represented by an electron trapped in the quantum dot, wherein the screening gate, the lead induction gate, the lead-to-quantum-dot barrier gate, the plunger gate, and the inter-quantum-dot barrier gate are layered on the quantum well substrate, and the lead is tunnel-coupled to all of the quantum dots.

2. The gate-defined quantum dot structure of claim 1, wherein the screening gate, the lead inducing gate, the lead-quantum dot barrier gate, the plunger gate and the quantum dot barrier gate are all stacked on the quantum well substrate at different heights.

3. The gate-defined quantum dot structure of claim 1, wherein the ratio of the number of said charge meters to the number of said plunger gates is greater than or equal to 1 / 3 and less than or equal to 1.

4. The gate-defined quantum dot structure according to claim 1, wherein the quantum well substrate has a sandwich structure in which a Si layer is sandwiched between SiGe layers or a Ge layer is sandwiched between SiGe layers.

5. The gate-defined quantum dot structure of claim 1, wherein said quantum well substrate has a MOS structure.

6. A semiconductor quantum computer comprising a gate-defined quantum dot structure according to any one of claims 1 to 5.

7. A method for controlling a gate-defined quantum dot structure according to any one of claims 1 to 5, comprising the steps of: controlling the flow of electrons between the lead and the quantum dot by controlling a voltage applied to the lead-quantum dot barrier gate; adjusting the number of electrons in each of the quantum dots by controlling a voltage applied to the plunger gate; and adjusting the strength of the tunnel coupling between adjacent quantum dots by adjusting the voltage applied to the inter-quantum dot barrier gate.

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