Display device and manufacturing method therefor

Abstract

A display device according to an embodiment includes: a substrate: a first bottom electrode disposed on the substrate; a first protection layer disposed on the first bottom electrode and including a first additive and at least one of silicon nitride, silicon oxide, and silicon oxynitride; a first insulation layer disposed on the first protection layer; an active layer disposed on the first insulation layer and including an oxide semiconductor; a gate insulation layer disposed on the active layer; a gate electrode disposed on the gate insulation layer; and a second insulation layer disposed on the gate electrode. The first bottom electrode may include a first metal layer and a second metal layer disposed on the first metal layer and exposing a side surface of the first metal layer. The first protection layer may cover the exposed side surface of the first metal layer.

Description

Display device and method for manufacturing the same

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. In response, various types of display devices, including light-emitting displays, are being developed.

[0003] The problem to be solved by the present invention is to provide a display device with improved reliability and a method for manufacturing the same.

[0004] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] According to one embodiment, a display device includes: a substrate; a first bottom electrode disposed on the substrate; a first passivation layer disposed on the first bottom electrode and including at least one of silicon nitride, silicon oxide, and silicon oxynitride, and a first additive; a first insulating layer disposed on the first passivation layer; an active layer disposed on the first insulating layer and including an oxide semiconductor; a gate insulating layer disposed on the active layer; a gate electrode disposed on the gate insulating layer; and a second insulating layer disposed on the gate electrode. The first bottom electrode may include a first metal layer, and a second metal layer disposed on the first metal layer and exposing a side surface of the first metal layer. The first passivation layer may cover the exposed side surface of the first metal layer.

[0006] In one embodiment, the first metal layer may include aluminum or copper, and the second metal layer may include titanium.

[0007] In one embodiment, the first bottom electrode may further include a third metal layer including titanium, the third metal layer being disposed below the first metal layer.

[0008] In one embodiment, the first additive may include at least one of fluorine, chlorine, carbon, and sulfur.

[0009] In one embodiment, the concentration of fluorine, chlorine, carbon or sulfur included in the first protective layer may be at least 2.5 times the concentration of fluorine, chlorine, carbon or sulfur included in the first insulating layer.

[0010] In one embodiment, the first protective layer comprises silicon nitride with added fluorine, and the thickness of the first protective layer may be 100 Å or less.

[0011] In one embodiment, the first insulating layer may include a silicon nitride layer disposed on the first protective layer; and at least one of a silicon oxide layer and a silicon oxynitride layer disposed on the silicon nitride layer.

[0012] In one embodiment, the active layer may include at least one of indium-gallium-zinc oxide, indium-tin-gallium-zinc oxide, and indium-gallium oxide.

[0013] In one embodiment, the gate electrode may further include at least one of a fourth metal layer including aluminum or copper, a fifth metal layer including titanium disposed on the fourth metal layer, and a sixth metal layer including titanium disposed under the fourth metal layer.

[0014] In one embodiment, the display device may further include a second protective layer disposed between the gate electrode and the second insulating layer, covering the gate electrode, and including silicon oxide or silicon oxynitride and a second additive.

[0015] In one embodiment, the second additive may include at least one of fluorine, chlorine, carbon, and sulfur.

[0016] In one embodiment, the second insulating layer may include at least one of silicon oxide and silicon oxynitride.

[0017] In one embodiment, the display device may further include a barrier layer disposed between the substrate and the first bottom electrode; a second bottom electrode disposed between the substrate and the barrier layer; and a third protective layer disposed between the second bottom electrode and the barrier layer, covering the second bottom electrode, and including at least one of silicon nitride, silicon oxide, and silicon oxynitride and a third additive.

[0018] In one embodiment, the second bottom electrode may further include at least one of a seventh metal layer including aluminum or copper, an eighth metal layer including titanium disposed on the seventh metal layer, and a ninth metal layer including titanium disposed under the seventh metal layer.

[0019] In one embodiment, the third additive may include at least one of fluorine, chlorine, carbon, and sulfur.

[0020] In one embodiment, the display device further includes at least one of a source electrode and a drain electrode disposed on the second insulating layer and electrically connected to the active layer, wherein the first bottom electrode overlaps the active layer and can be electrically connected to the source electrode.

[0021] A method for manufacturing a display device according to one embodiment includes: forming a first bottom electrode on a substrate, the first bottom electrode including a first metal layer and a second metal layer on the first metal layer; forming a first protective layer on the substrate, the first protective layer covering the first bottom electrode and including at least one of silicon nitride, silicon oxide, and silicon oxynitride and a first additive; forming a first insulating layer on the first protective layer; forming an active layer including an oxide semiconductor on the first insulating layer; forming a gate insulating layer and a gate electrode on the active layer; and forming a second insulating layer on the active layer, the gate insulating layer, and the gate electrode. The second metal layer may expose a side surface of the first metal layer. The first protective layer may cover the exposed side surface of the first metal layer.

[0022] In one embodiment, the first additive may include at least one of fluorine, chlorine, carbon, and sulfur.

[0023] In one embodiment, the method for manufacturing the display device further includes, prior to forming the second insulating layer, a step of forming a second protective layer covering the gate electrode and including silicon oxide or silicon oxynitride and a second additive, wherein the second additive may include at least one of fluorine, chlorine, carbon, and sulfur.

[0024] In one embodiment, the method for manufacturing the display device further includes, prior to forming the first bottom electrode, a step of sequentially forming, on the substrate, a second bottom electrode, a third protective layer covering the second bottom electrode, and a barrier layer covering the third protective layer, wherein the third protective layer may include a third additive including at least one of silicon nitride, silicon oxide, and silicon oxynitride, and at least one of fluorine, chlorine, carbon, and sulfur.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] According to the display device and its manufacturing method according to the embodiments, the resistance of the conductive layer provided on the display panel can be lowered while effectively preventing corrosion of the conductive layer. Accordingly, the operating characteristics and reliability of the display device can be improved.

[0027] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0028] FIG. 1 is a plan view showing a display device according to one embodiment.

[0029] Figure 2 is a plan view showing the display panel of Figure 1.

[0030] Figure 3 is a circuit diagram showing a pixel according to one embodiment.

[0031] FIG. 4 is a cross-sectional view showing a display panel according to one embodiment.

[0032] Figure 5 is a cross-sectional view showing area A1 of Figure 4 in detail.

[0033] Figure 6 is a cross-sectional view showing area A1 of Figure 4 in detail.

[0034] Fig. 7 is a cross-sectional view showing a display panel according to one embodiment.

[0035] Figure 8 is a cross-sectional view showing area A2 of Figure 7 in detail.

[0036] Figure 9 is a cross-sectional view showing area A2 of Figure 7 in detail.

[0037] Fig. 10 is a cross-sectional view showing a display panel according to one embodiment.

[0038] Figure 11 is a cross-sectional view showing area A3 of Figure 10 in detail.

[0039] Figure 12 is a cross-sectional view showing area A3 of Figure 10 in detail.

[0040] Figure 13 is a graph showing the fluorine concentration measured in a display panel including the first protective layer.

[0041] FIGS. 14 to 25 are cross-sectional views showing a method of manufacturing a display device according to one embodiment.

[0042] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0043] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0044] The features of various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically diverse interconnections and operations. Each embodiment can be implemented independently of the others, or can be implemented together in a related manner.

[0045] Specific embodiments are described below with reference to the attached drawings.

[0046] Fig. 1 is a plan view showing a display device (100) according to one embodiment. Fig. 2 is a plan view showing a display panel (110) of Fig. 1.

[0047] Referring to FIGS. 1 and 2, the display device (100) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and Ultra Mobile PCs (UMPCs), as well as televisions, laptops, monitors, billboards, and Internet of Things (IOT). These are presented only as examples, and the display device (100) can be included in or employed in other electronic devices.

[0048] In one embodiment, the display device (100) may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device including an ultra-small light-emitting diode such as a micro or nano light emitting diode (micro LED or nano LED), but is not limited thereto. For example, the display device (100) may be a type of display device other than a light-emitting display device. Hereinafter, embodiments in which the display device (100) is a light-emitting display device (for example, an organic light-emitting display device) are disclosed.

[0049] The display device (100) may include a display panel (110) including pixels (PX), and a first driving unit (120) and a second driving unit (130) that supply driving signals to the pixels (PX). The display device (100) may further include additional components. For example, the display device (100) may further include a power supply unit for supplying power voltages to the pixels (PX), the first driving unit (120) and the second driving unit (130), and a timing control unit for controlling the operations of the first driving unit (120) and the second driving unit (130).

[0050] The display panel (110) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be an area that displays an image by including pixels (PX). For example, the display area (DA) may include pixel areas in which each pixel (PX) is arranged. The non-display area (NDA) is an area excluding the display area (DA), and an image may not be displayed in the non-display area (NDA). In one embodiment, the non-display area (NDA) may be located around the display area (DA) and may surround the display area (DA).

[0051] In FIGS. 1 and 2, a first direction (D1), a second direction (D2), and a third direction (D3) are defined. In one embodiment, the first direction (D1) may be a horizontal direction of the display panel (110), the second direction (D2) may be a vertical direction of the display panel (110), and the third direction (D3) may be a thickness direction of the display panel (110).

[0052] In one embodiment, the display panel (110) may be formed in a rectangular shape on a plane. Although FIGS. 1 and 2 illustrate a display panel (110) whose horizontal length is longer than its vertical length, the shape of the display panel (110) is not limited thereto. For example, the display panel (110) may have a shape in which the vertical length is longer than the horizontal length, or may have a square shape, etc. The display panel (110) may include angled corners or rounded corners.

[0053] The planar shape of the display panel (110) is not limited to the illustrated rectangular shape, and may be applied in other shapes. For example, the display panel (110) may have a non-rectangular polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes in addition to the planar shape.

[0054] In one embodiment, the display panel (110) may be substantially flat on a plane defined by the first direction (D1) and the second direction (D2), and may have a uniform thickness in the third direction (D3). Alternatively, the display panel (110) may be provided in a three-dimensional shape having a curved surface, etc.

[0055] The display panel (110) may be provided as a rigid panel that is substantially not deformed, or may be provided as a flexible panel that can be deformed in a form such as by folding, bending, or rolling at least in one portion. The display panel (110) may be provided to the display device (100) in an unbent state, or may be provided to the display device (100) in a bent state in some sections.

[0056] A display panel (110) may include a substrate (SUB) and pixels (PX) arranged on the substrate (SUB). The pixels (PX) may be arranged in a display area (DA) on the substrate (SUB).

[0057] The substrate (SUB) is a base member for manufacturing or providing a display panel (110) and may constitute a base surface of the display panel (110). The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA).

[0058] The display area (DA) may have various shapes depending on the embodiments. For example, the display area (DA) may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes. In one embodiment, the display area (DA) may have a shape that matches the shape of the display panel (110).

[0059] Pixels (PX) may be provided and / or arranged in a display area (DA). For example, the display area (DA) may include a plurality of pixel areas in which each pixel (PX) is arranged.

[0060] In one embodiment, the display device (100) may be a light-emitting display device, and each pixel (PX) may include a light-emitting element positioned in each light-emitting area and a pixel circuit connected to the light-emitting element. In describing the embodiments, the term "connection" may include the meaning of electrical connection and / or physical connection. Each pixel circuit may include transistors (for example, transistors including a driving transistor that generates a driving current corresponding to a data signal, and at least one switching transistor) and at least one capacitor (for example, a capacitor including a storage capacitor).

[0061] The non-display area (NDA) may include a pad area (PA) where pads (PD) are arranged. In one embodiment, the non-display area (NDA) may further include a driving circuit area located at least on one side of the display area (DA). At least one driving unit, pads (PD), and / or wiring may be arranged in the non-display area (NDA).

[0062] At least one driving unit for driving the pixels (PX), or a part of the driving unit, may be disposed in the driving circuit area. For example, circuit elements constituting the first driving unit (120) (for example, driving unit transistors and driving unit capacitors constituting the stage circuits of the first driving unit (120)) may be disposed in the driving circuit area on the substrate (SUB). In one embodiment, the circuit elements of the first driving unit (120) may be formed in the display panel (110) together with the pixels (PX). In one embodiment, the driving unit transistors provided to the first driving unit (120) may be transistors of a type and / or structure substantially the same as or similar to the transistors provided to the pixels (PX), and may be formed simultaneously with the transistors of the pixels (PX).

[0063] Pads (PD) may be arranged in the pad area (PA). At least one circuit board (140) may be arranged and / or bonded on the pad area (PA). In one embodiment, a plurality of circuit boards (140) connected to different pads (PD) may be arranged on the pad area (PA). The pads (PD) may include signal pads and power pads for transmitting driving signals and power voltages required for driving the pixels (PX) and / or the first driving unit (120) to the inside of the display panel (110).

[0064] The first driving unit (120) and the second driving unit (130) can generate driving signals for controlling the operation timing and brightness of the pixels (PX) and supply the driving signals to the pixels (PX). For example, the first driving unit (120) can be a gate driving unit including a scan driving unit and can be connected to the pixels (PX) through respective gate lines. The first driving unit (120) can supply respective gate signals (for example, control signals for controlling the operation timing of the pixels (PX) including scan signals and / or emission control signals) to the pixels (PX). The second driving unit (130) can be a data driving unit including source driving circuits and can be connected to the pixels (PX) through respective data lines. The second driving unit (130) can supply respective data signals to the pixels (PX).

[0065] In one embodiment, at least one of the first driving unit (120) and the second driving unit (130), or a portion of the at least one driving unit, may be built into the display panel (110). For example, the first driving unit (120) or a portion of the first driving unit (120) may be disposed on the substrate (SUB) of the display panel (110) and may be disposed and / or formed in a non-display area (NDA).

[0066] In FIG. 1, the first driving unit (120) is exemplified as being formed on one side of the display area (DA) (for example, the non-display area (NDA) on the right side of the display area (DA), but the embodiments are not limited thereto. For example, the first driving unit (120) may be positioned only on the other side of the display area (DA) (for example, the non-display area (NDA) on the left side of the display area (DA)) or on both sides of the display area (DA) (for example, the non-display areas (NDA) on the left and right sides of the display area (DA). Alternatively, a part of the first driving unit (120) may be positioned in the non-display area (NDA), and another part of the first driving unit (120) may be positioned in a non-emitting area (for example, an area between the emitting areas of the pixels (PX)) within the display area (DA).

[0067] In one embodiment, the other driving unit among the first driving unit (120) and the second driving unit (130), or a portion of the other driving unit, may be disposed or formed outside the display panel (110) and electrically connected to the display panel (110). For example, the second driving unit (130) may be implemented with a plurality of integrated circuit chips and may be disposed on circuit boards (140) that are electrically connected to the pixels (PX) of the display panel (110). The second driving unit (130) may also be implemented with at least one integrated circuit chip and mounted on a non-display area (NDA) of the display panel (110).

[0068] The circuit board (140) may be connected to the display panel (110) via pads (PD). In one embodiment, the circuit board (140) may be, but is not limited to, a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF). In one embodiment, the circuit board (140) may be connected to a timing control unit and / or a power supply unit via another circuit board or a connector.

[0069] Fig. 3 is a circuit diagram showing a pixel (PX) according to one embodiment. For example, Fig. 3 shows a pixel (PX) of a light-emitting display device including a light-emitting element (ED). The type and / or structure of the pixel (PX) that may be included in the display device (100) may vary depending on the embodiments.

[0070] Referring to FIG. 3, a pixel (PX) may include a light-emitting element (ED) and a pixel circuit (PC) connected to the light-emitting element (ED). The light-emitting element (ED) is a light source of the pixel (PX), and may be, for example, an organic light-emitting diode, but is not limited thereto. The pixel circuit (PC) may control the light-emitting timing and brightness of the light-emitting element (ED).

[0071] The pixel circuit (PC) may include transistors (T) and at least one capacitor (C). For example, the pixel circuit (PC) may include first to fifth transistors (T1 to T5) and first and second capacitors (C1, C2). Although FIG. 3 illustrates an embodiment in which all of the transistors (T) are N-type transistors, the type of the transistors (T) is not limited thereto. For example, at least one transistor (T) may be formed as a P-type transistor.

[0072] The pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to driving signals supplied from the first driving unit (120) and the second driving unit (130). For example, the pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to each of the gate signals (GS) supplied from the first driving unit (120) through each of the gate lines (GL) and the data signal (DATA) supplied from the second driving unit (130) through the data line (DL).

[0073] The first transistor (T1) may be a driving transistor of a pixel (PX), in which the magnitude of a drain-source current (e.g., a driving current (Id)) is determined according to a gate-source voltage. The second, third, fourth, and fifth transistors (T2, T3, T4, T5) may be switching transistors that are turned on or off according to their respective gate-source voltages. Depending on the type (e.g., a P-type or N-type transistor) and / or operating conditions of each of the first to fifth transistors (T1 to T5), the first electrode of each of the first to fifth transistors (T1 to T5) may be a drain electrode (or a drain region) or a source electrode (or a source region), and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a drain electrode, the second electrode may be a source electrode.

[0074] A pixel (PX) may be connected to a first gate line (GWL) that transmits a first gate signal (GW) (e.g., a scan signal), a second gate line (GIL) that transmits a second gate signal (GIN), a third gate line (GRL) that transmits a third gate signal (GR), an emission control line (ECL) that transmits an emission control signal (EM), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel (PX) may be connected to a first power line (VDL) that transmits a first pixel voltage (ELVDD) (also referred to as a “first pixel power voltage”), and a second power line (VSL) that transmits a second pixel voltage (ELVSS) (also referred to as a “second pixel power voltage”). In one embodiment, the pixel (PX) may be further connected to an initialization power line (VIL) that carries an initialization voltage (VINT) (also referred to as a "third pixel power voltage") and a reference power line (VRL) that carries a reference voltage (VREF) (also referred to as a "fourth pixel power voltage").

[0075] In one embodiment, the first to fifth transistors (T1 to T5) may be positioned in respective pixel areas and may be oxide transistors including oxide semiconductors (also referred to as “oxide semiconductor transistors”). For example, the active layer of each of the first to fifth transistors (T1 to T5) may include an oxide semiconductor. However, the embodiments are not limited thereto. For example, at least one transistor (T) may be formed of a semiconductor material other than an oxide semiconductor (e.g., amorphous silicon or polysilicon).

[0076] In one embodiment, all of the transistors (T) disposed on the display panel (110), including the first to fifth transistors (T1 to T5), may be oxide transistors including oxide semiconductors. Oxide semiconductors have high carrier mobility and low leakage current, and thus, even if the driving time of the oxide transistor is long, a large voltage drop may not occur. For example, in the case of a pixel (PX) including an oxide transistor, even when driven at a low frequency, the brightness and / or color of the image due to the voltage drop does not change significantly, and thus the pixel can be driven at a low frequency. When the first to fifth transistors (T1 to T5) are formed of oxide transistors, the leakage current of the pixel (PX) can be reduced or prevented, and power consumption can be reduced.

[0077] Oxide semiconductors are sensitive to light, and thus their current and other characteristics may fluctuate due to external light. In one embodiment, a light-shielding pattern or a light-shielding electrode (e.g., a bottom electrode or a back-gate electrode) may be disposed below the active layer included in at least one transistor (T) to block external light. Accordingly, the operating characteristics of the transistor (T) may be stabilized.

[0078] A first transistor (T1) may include a gate electrode connected to a first node (N1), a first electrode (e.g., a drain electrode) connected to a second node (N2), and a second electrode (e.g., a source electrode) connected to a third node (N3). The first electrode of the first transistor (T1) may be connected to a first power line (VDL) via a fifth transistor (T5), and the second electrode may be connected to a light-emitting element (ED). The first transistor (T1) may control the size (e.g., the amount of current) of a driving current (Id) flowing to the light-emitting element (ED) in response to a data signal (DATA) transmitted to the first node (N1).

[0079] In one embodiment, the first transistor (T1) may further include a bottom electrode (BE) (for example, the first bottom electrode (BE1) of FIG. 4) connected to a third node (N3). By connecting the bottom electrode (BE) of the first transistor (T1) to the third node (N3) to form the first transistor (T1) into a double-gate structured transistor (for example, a double-gate transistor with a source-sync structure), the operating characteristics of the first transistor (T1) can be improved.

[0080] The second transistor (T2) may include a gate electrode connected to the first gate line (GWL), a first electrode connected to the data line (DL), and a second electrode connected to the first node (N1). The second transistor (T2) may be turned on by a first gate signal (GW) transmitted to the first gate line (GWL) (for example, a first gate signal (GW) of a gate-on voltage) to connect the data line (DL) and the first node (N1). Accordingly, a data signal (DATA) transmitted to the data line (DL) may be transmitted to the first node (N1).

[0081] The third transistor (T3) may include a gate electrode connected to a third gate line (GRL), a first electrode connected to a reference power line (VRL), and a second electrode connected to a first node (N1). The third transistor (T3) may be turned on by a third gate signal (GR) transmitted to the third gate line (GRL) and may transmit a reference voltage (VREF) transmitted to the reference power line (VRL) to the first node (N1).

[0082] The fourth transistor (T4) may include a gate electrode connected to the second gate line (GIL), a first electrode connected to the third node (N3), and a second electrode connected to the initialization power line (VIL). The fourth transistor (T4) may be turned on by the second gate signal (GIN) transmitted to the second gate line (GIL) and may transmit the initialization voltage (VINT) transmitted to the initialization power line (VIL) to the third node (N3).

[0083] The fifth transistor (T5) may include a gate electrode connected to the emission control line (ECL), a first electrode connected to the first power line (VDL), and a second electrode connected to the second node (or the first electrode of the first transistor (T1)). The fifth transistor (T5) may be turned on by an emission control signal (EM) transmitted to the emission control line (ECL) (for example, an emission control signal (EM) of a gate-on voltage) to control the emission timing of the pixel (PX).

[0084] Each of the second to fifth transistors (T2 to T5) may or may not include a bottom electrode. In one embodiment, at least one switching transistor among the second to fifth transistors (T2 to T5) may include a bottom electrode, and the bottom electrode of the at least one switching transistor may be connected to a gate electrode of the corresponding switching transistor. When the bottom electrode of the switching transistor is connected to the gate electrode, the off characteristics and switching speed of the switching transistor are improved, an additional voltage tolerance range is secured, leakage current is reduced, and voltage stability is improved.

[0085] A first capacitor (C1) may be connected between a first node (N1) and a third node (N3). The first capacitor (C1) serves as a storage capacitor of a pixel (PX) and may store a voltage corresponding to a threshold voltage of a first transistor (T1) and a data signal (DATA) (e.g., a data voltage).

[0086] A second capacitor (C2) may be connected between the first power line (VDL) and the third node (N3). In one embodiment, the capacitance of the second capacitor (C2) may be smaller than the capacitance of the first capacitor (C1).

[0087] The light emitting element (ED) may be connected between the third node (N3) and the second power line (VSL). For example, the light emitting element (ED) may include a first electrode (e.g., an anode electrode) connected to the third node (N3), a second electrode (e.g., a cathode electrode) facing the first electrode and connected to the second power line (VSL), and a light emitting layer interposed between the first electrode and the second electrode. In one embodiment, the first electrode of the light emitting element (ED) may be an individual electrode individually provided to each pixel (PX), and the second electrode of the light emitting element (ED) may be a common electrode shared by a plurality of pixels (PX). The light emitting element (ED) may emit light with a brightness corresponding to the driving current (Id) during a period in which the driving current (Id) is supplied from the pixel circuit (PC).

[0088] Fig. 4 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, Fig. 4 shows a portion of a display area (DA) of the display panel (110). Fig. 4 shows a light-emitting display panel including a light-emitting element (ED) (for example, an organic light-emitting diode) as an example of a display panel (110) to which embodiments can be applied.

[0089] Referring to FIG. 4, the display panel (110) may include a substrate (SUB) (or base layer), a panel circuit layer (PCL), a light emitting element layer (LEL), and an encapsulation layer (ENL). The panel circuit layer (PCL), the light emitting element layer (LEL), and the encapsulation layer (ENL) may be arranged on the substrate (SUB) to overlap each other. For example, with respect to the display area (DA), the panel circuit layer (PCL), the light emitting element layer (LEL), and the encapsulation layer (ENL) may be sequentially arranged on the substrate (SUB) along a third direction (D3). The positions of the panel circuit layer (PCL), the light emitting element layer (LEL), and / or the encapsulation layer (ENL) may vary depending on embodiments.

[0090] In one embodiment, the display panel (110) may further include additional elements provided on top and / or bottom of the encapsulation layer (ENL). For example, the display panel (110) may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and / or the protective layer may be provided on top of the encapsulation layer (ENL), or may be provided between the light emitting element layer (LEL) and the encapsulation layer (ENL), etc.

[0091] The substrate (SUB) is a base member for forming the display panel (110), and may be a rigid or flexible substrate (or film). In one embodiment, the substrate (SUB) may be a substrate having rigid properties, including an insulating material such as glass, and may not be bent. Alternatively, the substrate (SUB) may be a flexible substrate including polyimide or another insulating material, and capable of deformation, such as bending, folding, or rolling, and may or may not be bent. The type and / or material of the substrate (SUB) may vary depending on the embodiments.

[0092] A panel circuit layer (PCL) (e.g., a pixel circuit layer or a thin film transistor layer) may be disposed on a substrate (SUB). The panel circuit layer (PCL) may include circuit elements including transistors (T) and capacitors (C) of pixels (PX), and wires (e.g., signal lines and power lines). In one embodiment, the panel circuit layer (PCL) may further include circuit elements of the first driving unit (120) (e.g., driving unit transistors and / or driving unit capacitors provided to the first driving unit (120)) and / or additional conductive patterns (e.g., bridge patterns).

[0093] FIG. 4 shows a transistor (T) and a capacitor (C) arranged in one pixel area (PXA) as examples of circuit elements that may be provided in a panel circuit layer (PCL). The transistor (T) of FIG. 4 may be a driving transistor or a switching transistor provided in a pixel circuit (PC) of the corresponding pixel (PX). For example, the transistor (T) of FIG. 4 may be the first transistor (T1) of FIG. 3. The capacitor (C) of FIG. 4 may be any capacitor (C) provided in the pixel circuit (PC) of the corresponding pixel (PX). For example, the capacitor (C) of FIG. 4 may be the first capacitor (C1) of FIG. 3.

[0094] In one embodiment, the panel circuit layer (PCL) may include a barrier layer (BR). For example, the barrier layer (BR) may be disposed on a substrate (SUB), and circuit elements and wirings may be disposed on the barrier layer (BR).

[0095] A panel circuit layer (PCL) may include conductive layers and a semiconductor layer (SCL) disposed on a barrier layer (BR). The conductive layers may include electrodes constituting circuit elements (e.g., transistors (T) and capacitors (C)) of the panel circuit layer (PCL), conductive patterns (e.g., bridge electrodes (BRE)) connected to the circuit elements, and / or wirings. The semiconductor layer (SCL) may include active layers (ACT) of transistors (T) provided in the panel circuit layer (PCL).

[0096] In one embodiment, the panel circuit layer (PCL) may include a first bottom conductive layer (BCDL1) (also referred to as a “first lower conductive layer” or a “fourth conductive layer”), a semiconductor layer (SCL), a first conductive layer (CDL1) (also referred to as a “gate conductive layer”), and a second conductive layer (CDL2) (also referred to as a “first source-drain conductive layer” or a “first data conductive layer”), which are sequentially disposed on the substrate (SUB) along a third direction (D3). In one embodiment, the panel circuit layer (PCL) may further include a third conductive layer (CDL3) (also referred to as a “second source-drain conductive layer” or a “second data conductive layer”), which is disposed on the second conductive layer (CDL2). For example, a first bottom conductive layer (BCDL1) may be disposed on the lower portion of the semiconductor layer (SCL) (for example, between the substrate (SUB) and the semiconductor layer (SCL)), and a first conductive layer (CDL1), a second conductive layer (CDL2), and a third conductive layer (CDL3) may be disposed on the upper portion of the semiconductor layer (SCL) (for example, between the semiconductor layer (SCL) and the light emitting element layer (LEL)).

[0097] Each of the electrodes, conductive patterns and / or wires provided or arranged on the conductive layers of the panel circuit layer (PCL) may include at least one conductive material. For example, the electrodes, conductive patterns and / or wires arranged on each of the first bottom conductive layer (BCDL1), the first conductive layer (CDL1), the second conductive layer (CDL2) and the third conductive layer (CDL3) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In one embodiment, the electrodes, conductive patterns and / or wires arranged on the same conductive layer may be simultaneously formed using the same conductive material.

[0098] In one embodiment, each of the electrodes, conductive patterns, and / or wires provided in the conductive layers of the panel circuit layer (PCL) may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and / or wires provided in the first bottom conductive layer (BCDL1), the first conductive layer (CDL1), the second conductive layer (CDL2), and the third conductive layer (CDL3) may have a single-layer or multi-layer structure. In one embodiment, the electrodes, conductive patterns, and / or wires provided in the same conductive layer may be formed simultaneously using the same material.

[0099] The panel circuit layer (PCL) may further include a plurality of insulating layers and / or insulating patterns arranged on the substrate (SUB). For example, the panel circuit layer (PCL) may include a barrier layer (BR), a first insulating layer (IL1), a gate insulating layer (GI), a second insulating layer (IL2), a third insulating layer (IL3), and a fourth insulating layer (IL4) sequentially arranged on the substrate (SUB) along a third direction (D3). In embodiments, the panel circuit layer (PCL) may further include a first protective layer (PRL1) arranged between the first bottom conductive layer (BCDL1) and the first insulating layer (IL1).

[0100] A barrier layer (BR) may be disposed between the substrate (SUB) and the first bottom conductive layer (BCDL1). The barrier layer (BR) may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). The barrier layer (BRL) may protect the pixels (PX) from moisture penetrating through the substrate (SUB) that is vulnerable to moisture permeation. The material of the barrier layer (BRL) may vary depending on embodiments.

[0101] The first protective layer (PRL1) may be disposed on the barrier layer (BR) (or substrate (SUB)) and the first bottom conductive layer (BCDL1). The first protective layer (PRL1) may cover the patterns of the first bottom conductive layer (BCDL1). For example, the first protective layer (PRL1) may be disposed on electrodes (for example, the first bottom electrode (BE1) and the first sub-electrode (CE2a) of the second capacitor electrode (CE2)), wires and / or conductive patterns included in the first bottom conductive layer (BCDL1), thereby covering the electrodes, wires and / or conductive patterns of the first bottom conductive layer (BCDL1).

[0102] The first protective layer (PRL1) may include a material that can appropriately protect the patterns of the first bottom conductive layer (BCDL1) from moisture or chemicals used in the manufacturing process of the display panel (110). For example, the first protective layer (PRL1) may include an insulating material (for example, an inorganic insulating material) and a first additive added to the insulating material. In one embodiment, the first protective layer (PRL1) may include silicon nitride (SiN). x ), silicon oxide (SiO x ) and silicon oxynitride (SiON), and a first additive (or first material) added thereto (e.g., doped or deposited). As an example, the first protective layer (PRL1) may be a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer, including the first additive. In one embodiment, silicon nitride (SiN x ) to form the first protective layer (PRL1), the barrier effect that blocks the diffusion of moisture or hydrogen, etc. can be enhanced.

[0103] In one embodiment, the first additive may include at least one of fluorine (F), chlorine (Cl), carbon (C), and sulfur (S). As an example, the first protective layer (PRL1) may be silicon nitride (SiN) to which fluorine (F) is added. x :F), silicon nitride (SiN) with added chlorine (Cl) x :Cl), carbon (C) added silicon nitride (SiN) x :C), sulfur (S) added silicon nitride (SiN) x :S), silicon oxide (SiO) with added fluorine (F) x :F) or silicon oxynitride (SiON:F), silicon oxide (SiO) with chlorine (Cl) added x :Cl) or silicon oxynitride (SiON:Cl), carbon (C) added silicon oxide (SiO x :C) or silicon oxynitride (SiON:C), or silicon oxide (SiO) with sulfur (S) added x:S) or silicon oxynitride (SiON:S). The concentration of the first additive, for example, fluorine (F), chlorine (Cl), carbon (C), or sulfur (S)) included in the first protective layer (PRL1) may be 2.5 times or more the concentration of fluorine (F), chlorine (Cl), carbon (C), or sulfur (S) included in the first insulating layer (IL1) (or the first layer (IL1a) of the first insulating layer (IL1)) on the first protective layer (PRL1).

[0104] The first insulating layer (IL1) may be disposed on the first bottom conductive layer (BCDL1) and the first protective layer (PRL1). The first insulating layer (IL1) may include at least one inorganic insulating layer including an inorganic insulating material.

[0105] In one embodiment, the first insulating layer (IL1) may be an insulating layer of more than one layer. For example, the first insulating layer (IL1) is disposed on the first protective layer (PRL1) and may be made of silicon nitride (SiN). x ) including a first layer (IL1a) (e.g., a silicon nitride layer), and a silicon oxide (SiO) disposed on the first layer (IL1a). x ) and a second layer (IL1b) including at least one of silicon oxide layer and silicon oxynitride (SiON) (for example, at least one of a silicon oxide layer and a silicon oxynitride layer).

[0106] Since the first insulating layer (IL1) includes a first layer (IL1a) and a second layer (IL1b) made of different materials, the insulating properties of the first insulating layer (IL1) can be improved or secured. For example, by arranging at least a double layer of the first insulating layer (IL1) between the first bottom electrode (BE1) and the active layer (ACT) overlapping each other with the first insulating layer (IL1) interposed therebetween, the first bottom electrode (BE1) and the active layer (ACT) can be stably insulated, and defects such as short-circuit defects can be prevented.

[0107] In addition, silicon nitride (SiN) has excellent hydrogen blocking effect. x) by covering the first bottom conductive layer (BCDL1) etc. with the first layer (IL1a) including the first layer, it is possible to effectively block hydrogen from flowing into the semiconductor layer (SCL) from the first bottom conductive layer (BCDL1) etc. Accordingly, it is possible to prevent a change in the characteristics of the transistor (T) and improve or stabilize the operating characteristics of the transistor (T).

[0108] The gate insulating layer (GI) may be disposed on the first insulating layer (IL1) and the semiconductor layer (SCL). For example, the gate insulating layer (GI) may be disposed between the first insulating layer (IL1), the semiconductor layer (SCL), and the first conductive layer (CDL1). The gate insulating layer (GI) may cover a portion of each of the first insulating layer (IL1) and the semiconductor layer (SCL). The gate insulating layer (GI) may be formed of an inorganic insulating material (for example, silicon oxide (SiO). x )) may include at least one inorganic insulating layer.

[0109] The second insulating layer (IL2) may be disposed on the first insulating layer (IL1), the semiconductor layer (SCL), the gate insulating layer (GI), and the first conductive layer (CDL1). For example, the second insulating layer (IL2) may be disposed between the first conductive layer (CDL1) and the second conductive layer (CDL2). The second insulating layer (IL2) may be disposed on and cover the patterns of the semiconductor layer (SCL), the gate insulating layer (GI), and the first conductive layer (CDL1). For example, the second insulating layer (IL2) may be disposed on the active layers (ACT) provided on the semiconductor layer (SCL), the first gate insulating layer (GI1) and the second gate insulating layer (GI2) provided on the gate insulating layer (GI), the gate electrode (GE) of the transistor (T) provided on the first conductive layer (CDL1), and the first sub-electrode (CE1a) of the first capacitor electrode (CE1).

[0110] The second insulating layer (IL2) may include at least one inorganic insulating layer including an inorganic insulating material. For example, the second insulating layer (IL2) may include silicon oxide (SiO x ) and silicon oxynitride (SiON).

[0111] In one embodiment, the second insulating layer (IL2) may be an insulating layer having more than one layer. For example, the second insulating layer (IL2) is disposed on the first conductive layer (CDL1) and may be formed of silicon oxide (SiO x ) or a lower layer including silicon oxynitride (SiON), and on the lower layer, silicon nitride (SiN) x ) may include an upper layer. By first covering the active layer (ACT) with a silicon oxide layer or a silicon oxynitride layer, it is possible to prevent or reduce hydrogen from flowing into or diffusing into the active layer (ACT) from the silicon nitride layer, etc. In addition, by covering the silicon oxide layer or the silicon oxynitride layer with a silicon nitride layer, it is possible to block hydrogen from flowing into or diffusing into the active layer (ACT) from other surrounding conductive layers or insulating layers, etc. Accordingly, the active layer (ACT) can be stably protected, and the operating characteristics of the transistor (T) can be improved or secured.

[0112] The third insulating layer (IL3) may be disposed on the second insulating layer (IL2) and the second conductive layer (CDL2). For example, the third insulating layer (IL3) may be disposed between the second conductive layer (CDL2) and the third conductive layer (CDL3). The third insulating layer (IL3) may be disposed on the patterns of the second conductive layer (CDL2) to cover the patterns. For example, the third insulating layer (IL3) may be disposed on the source electrode (SE) and the drain electrode (DE) of the transistor (T) provided on the second conductive layer (CDL2), the second sub-electrode (CE1b) of the first capacitor electrode (CE1), and the second sub-electrode (CE2b) of the second capacitor electrode (CE2).

[0113] The third insulating layer (IL3) may include at least one organic insulating layer including an organic insulating material (for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or another organic insulating material). The third insulating layer (IL3) may or may not include an inorganic insulating layer. When the third insulating layer (IL3) includes an inorganic insulating layer, the inorganic insulating layer and the organic insulating layer of the third insulating layer (IL3) may be sequentially disposed on the second conductive layer (CDL2). The surface (for example, the upper surface) of the third insulating layer (IL3) may be substantially flat.

[0114] The fourth insulating layer (IL4) may be disposed on the third insulating layer (IL3) and the third conductive layer (CDL3). For example, the fourth insulating layer (IL4) may be disposed between the third conductive layer (CDL3) and the light emitting element layer (LEL). The fourth insulating layer (IL4) may be disposed on the patterns of the third conductive layer (CDL3) to cover the patterns. For example, the fourth insulating layer (IL4) may be disposed on the bridge electrode (BRE) provided on the third conductive layer (CDL3), the third sub-electrode (CE2c) of the second capacitor electrode (CE2), etc.

[0115] The fourth insulating layer (IL4) may include at least one organic insulating layer including an organic insulating material. The fourth insulating layer (IL4) may or may not include an inorganic insulating layer. When the fourth insulating layer (IL4) includes an inorganic insulating layer, the inorganic insulating layer and the organic insulating layer of the fourth insulating layer (IL4) may be sequentially disposed on the third conductive layer (CDL3). The surface (for example, the upper surface) of the fourth insulating layer (IL4) may be substantially flat.

[0116] In one embodiment, at least one insulating layer provided on the panel circuit layer (PCL) may be disposed over the entire display area (DA). For example, a barrier layer (BR), a first insulating layer (IL1), a second insulating layer (IL2), a third insulating layer (IL3), and a fourth insulating layer (IL4) may be disposed over the entire display area (DA).

[0117] In one embodiment, the gate insulating layer (GI) may be partially disposed only on a portion of each pixel area (PXA) and a portion of the display area (DA) including the pixel area (PXA). In one embodiment, the gate insulating layer (GI) may include a first gate insulating layer (GI1) (also referred to as a “first gate insulating pattern”) disposed on a portion of each active layer (ACT) provided on the semiconductor layer (SCL), and a second gate insulating layer (GI2) (also referred to as a “second gate insulating pattern”) disposed on the first insulating layer (IL1) and not overlapping with the active layer (ACT). For example, the first gate insulating layer (GI1) may be disposed between a portion of the active layer (ACT) including the channel area (CH) and the gate electrode (GE), and the second gate insulating layer (GI2) may be disposed between the first insulating layer (IL1) and the first sub-electrode (CE1a) of the first capacitor electrode (CE1). The first gate insulating layer (GI1) and the second gate insulating layer (GI2) may be an integral insulating pattern that is connected to each other when viewed from a planar view, or may be individual insulating patterns that are separated from each other. However, the embodiments are not limited thereto. For example, the gate insulating layer (GI) may be disposed over the entire display area (DA) so as to entirely cover the first insulating layer (IL1) and the semiconductor layer (SCL).

[0118] A transistor (T) may include an active layer (ACT) (also referred to as an “active pattern” or a “semiconductor pattern”) and a gate electrode (GE) (e.g., a top-gate electrode) disposed on a portion of the active layer (ACT). In one embodiment, the transistor (T) may further include at least one of a source electrode (SE) and a drain electrode (DE). For example, the transistor (T) may further include a source electrode (SE) connected to a source region (SR) of the active layer (ACT) and a drain electrode (DE) connected to a drain region (DR) of the active layer (ACT). Alternatively, the transistor (T) may not include separate source electrodes and / or drain electrodes, and the source region (SR) and / or drain region (DR) of the active layer (ACT) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the source electrode and / or the drain electrode of the transistor (T).

[0119] In one embodiment, the transistor (T) may further include a first bottom electrode (BE1) (or, bottom-gate electrode) disposed under the active layer (ACT). For example, the first bottom electrode (BE1) may be connected to one electrode of the transistor (T), etc., and may be utilized as a back-gate electrode (BG) for adjusting the characteristics of the transistor (T). By disposing the first bottom electrode (BE1) under the active layer (ACT), external light may be blocked from entering the channel region (CH) of the active layer (ACT), thereby stabilizing the operating characteristics of the transistor (T).

[0120] Although FIG. 4 discloses an embodiment in which the transistor (T) is formed with a double gate structure including a first bottom electrode (BE1) and a gate electrode (GE) that overlap each other with an active layer (ACT) therebetween, the embodiments are not limited thereto. For example, the transistor (T) may include only one of the first bottom electrode (BE1) and the gate electrode (GE). For example, the transistor (T) may be formed with a top-gate structure including a single gate electrode (GE) disposed on top of the active layer (ACT), or may be formed with a bottom-gate structure including a first bottom electrode (BE1) disposed under the active layer (ACT).

[0121] In one embodiment, the transistor (T) may be an oxide transistor. For example, the transistor (T) may be an N-type oxide transistor.

[0122] The first bottom electrode (BE1) may be provided on a first bottom conductive layer (BCDL1) disposed on a barrier layer (BR) (or substrate (SUB)). The first bottom conductive layer (BCDL1) may be disposed between the barrier layer (BR) and the first insulating layer (IL1) and may be covered with a first protective layer (PRL1). Each of the patterns of the first bottom conductive layer (BCDL1) may be formed as a single layer (for example, a single metal layer) or as multiple layers of two or more layers (for example, metal layers of two or more layers).

[0123] The first bottom electrode (BE1) may overlap the active layer (ACT) and the gate electrode (GE). For example, the first bottom electrode (BE1) may be positioned below the active layer (ACT) so as to overlap at least a portion of the active layer (ACT) including the channel region (CH), and may face the gate electrode (GE) with the active layer (ACT) interposed therebetween.

[0124] In one embodiment, the first bottom electrode (BE1) may be connected to the source electrode (SE) or the gate electrode (GE) of the transistor (T). For example, the transistor (T) may be a driving transistor of the pixel (PX) (for example, the first transistor (T1) of FIG. 3), and the first bottom electrode (BE1) disposed under the active layer (ACT) of the transistor (T) may be connected to the source electrode (SE) of the transistor (T) through a first contact hole (CNT1) penetrating the first protective layer (PRL1), the first insulating layer (IL1), and the second insulating layer (IL2). Alternatively, the transistor (T) may be a switching transistor of the pixel (PX) (for example, one of the second to fifth transistors (T2 to T5) of FIG. 3), and the first bottom electrode (BE1) disposed under the active layer (ACT) of the transistor (T) may be connected to the gate electrode (GE) of the transistor (T). Each of the switching transistors of the pixel (PX) may or may not include a first bottom electrode (BE1) disposed thereunder.

[0125] The active layer (ACT) may be provided on a semiconductor layer (SCL). The semiconductor layer (SCL) may be disposed on a first insulating layer (IL1) covering a first bottom conductive layer (BCDL1), etc., and may be covered by a gate insulating layer (GI) and a second insulating layer (IL2).

[0126] The active layer (ACT) may include a channel region (CH) and a source region (SR) and a drain region (DR) spaced apart from each other with the channel region (CH) therebetween. For example, the source region (SR) and the drain region (DR) may be located on both sides of the channel region (CH). The source region (SR) and the drain region (DR) may be conductive regions that have a higher carrier concentration (e.g., electron concentration) than the channel region (CH).

[0127] The active layer (ACT) may overlap with the first bottom electrode (BE1) and the gate electrode (GE). For example, a portion of the active layer (ACT) including the channel region (CH) may overlap with the first bottom electrode (BE1) and the gate electrode (GE).

[0128] In one embodiment, the active layer (ACT) may include an oxide semiconductor. For example, the active layer (ACT) may include an oxide semiconductor including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), or another oxide semiconductor.

[0129] In one embodiment, the active layer (ACT) can include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors. For example, the active layer (ACT) may include indium-gallium-zinc oxide (IGZO), or may include a high-mobility oxide semiconductor having higher mobility than indium-gallium-zinc oxide (IGZO) (e.g., amorphous IGZO), such as indium-tin-gallium-zinc oxide (ITGZO) or indium-gallium oxide (IGO) (e.g., crystallized IGO). When the active layer (ACT) is formed of a high-mobility oxide semiconductor, the conductivity of the source region (SR) and the drain region (DR) can be appropriately and / or easily secured without performing an additional doping process, etc. In addition, when the active layer (ACT) is formed of a high-mobility oxide semiconductor, the mobility of the transistor (T) can be appropriately secured while forming the transistor (T) in a fine size (e.g., a size including the active layer (ACT) having a width and / or length in the range of approximately several micrometers to several tens of micrometers). The material, crystallinity, and mobility of the active layer (ACT) are not limited and may vary depending on the embodiments.

[0130] A first gate insulating layer (GI1) may be disposed on the active layer (ACT). For example, the first gate insulating layer (GI1) may be disposed between the active layer (ACT) and the gate electrode (GE).

[0131] In one embodiment, the first gate insulating layer (GI1) may cover a portion of the active layer (ACT) including a portion overlapping the gate electrode (GE) and expose another portion of the active layer (ACT). For example, the first gate insulating layer (GI1) may be disposed on a portion of the active layer (ACT) including the channel region (CH) and expose a source region (SR) and a drain region (DR) of the active layer (ACT).

[0132] As the first gate insulating layer (GI1) exposes the source region (SR) and the drain region (DR), the source region (SR) and the drain region (DR) can be appropriately and / or easily made conductive during the manufacturing process of the display panel (110). For example, in the step of etching the gate insulating layer (GI) so that at least a portion of each of the source region (SR) and the drain region (DR) is exposed, oxygen vacancies may occur in the source region (SR) and the drain region (DR) by an etching gas or the like. Accordingly, the source region (SR) and the drain region (DR) can be appropriately made conductive in a subsequent process (for example, a process of forming the second insulating layer (IL2)) without performing a separate doping process.

[0133] A gate electrode (GE) may be disposed on a first gate insulating layer (GI1). The gate electrode (GE) may be provided on a first conductive layer (CDL1). The first conductive layer (CDL1) may be disposed on the first insulating layer (IL1) and the gate insulating layer (GI), and may be covered by a second insulating layer (IL2). Each of the patterns of the first conductive layer (CDL1) may be formed as a single layer (for example, a single metal layer) or as multiple layers of two or more layers (for example, metal layers of two or more layers).

[0134] The gate electrode (GE) may be disposed on the active layer (ACT). For example, the gate electrode (GE) may be disposed on the first gate insulating layer (GI1) covering the channel region (CH) of the active layer (ACT). The gate electrode (GE) and the active layer (ACT) may be separated and / or spaced apart from each other with the first gate insulating layer (GI1) interposed therebetween.

[0135] A second insulating layer (IL2) may be disposed on the gate electrode (GE). The second insulating layer (IL2) may cover the active layer (ACT), the gate insulating layer (GI), and the gate electrode (GE).

[0136] A source electrode (SE) and a drain electrode (DE) may be disposed on a second insulating layer (IL2). The source electrode (SE) and the drain electrode (DE) may be provided on a second conductive layer (CDL2). The second conductive layer (CDL2) may be disposed between the second insulating layer (IL2) and the third insulating layer (IL3). In one embodiment, each of the patterns of the second conductive layer (CDL2) may be formed as a single layer (for example, a single metal layer). Alternatively, each of the patterns of the second conductive layer (CDL2) may be formed as a multilayer or more (for example, a double layer or more metal layers). For example, each of the patterns of the second conductive layer (CDL2) may be formed as a double layer or triple layer including a low-resistance metal layer such as aluminum (Al) or copper (Cu) (or at least one of aluminum (Al) and copper (Cu)), and an upper capping layer and / or a lower capping layer including a capping metal such as titanium (Ti) disposed on top and / or bottom of the low-resistance metal layer.

[0137] The source electrode (SE) may be connected to a portion of the active layer (ACT). For example, the source electrode (SE) may be electrically connected to the source region (SR) of the active layer (ACT) through a second contact hole (CNT2) penetrating the second insulating layer (IL2). In one embodiment, the source electrode (SE) may also be electrically connected to the first bottom electrode (BE1) through a first contact hole (CNT1).

[0138] The drain electrode (DE) may be connected to another portion of the active layer (ACT). For example, the drain electrode (DE) may be connected to the drain region (DR) of the active layer (ACT) through a third contact hole (CNT3) penetrating the second insulating layer (IL2).

[0139] In one embodiment, at least one transistor (T) provided in each pixel area (PXA) may be electrically connected to a light-emitting element (ED) disposed on the transistor (T). For example, at least one transistor (T) (for example, a first transistor (T1)) provided in each pixel area (PXA) may be connected to a bridge electrode (BRE) disposed on a third insulating layer (IL3) covering a second conductive layer (CDL2). For example, a source electrode (SE) (or a drain electrode (DE)) of the first transistor (T1) provided in each pixel area (PXA) may be connected to the bridge electrode (BRE) through a sixth contact hole (CNT6) penetrating the third insulating layer (IL3). The at least one transistor (T) may be connected to a light-emitting element (ED) disposed on a fourth insulating layer (IL4) through the bridge electrode (BRE).

[0140] A bridge electrode (BRE) may be provided in the third conductive layer (CDL3). The bridge electrode (BRE) may be connected to a first electrode (ET1) of a light-emitting element (ED) provided in the light-emitting element layer (LEL) through an eighth contact hole (CNT8) penetrating the fourth insulating layer (IL4).

[0141] The third conductive layer (CDL3) may be disposed between the third insulating layer (IL3) and the fourth insulating layer (IL4). For example, the third conductive layer (CDL3) may be disposed on the third insulating layer (IL3) and covered by the fourth insulating layer (IL4). In one embodiment, each of the patterns of the third conductive layer (CDL3) may be formed of a single layer (for example, a single metal layer). Alternatively, each of the patterns of the third conductive layer (CDL3) may be formed of multiple layers, such as double layers or more layers (for example, double layers or more metal layers). For example, each of the patterns of the third conductive layer (CDL3) may be formed of a double layer or triple layer including a low-resistance metal layer including aluminum (Al) or copper (Cu), and an upper capping layer and / or a lower capping layer including a capping metal such as titanium (Ti) disposed on and / or below the low-resistance metal layer.

[0142] A capacitor (C) may include capacitor electrodes that form electrostatic capacitance. For example, the first capacitor (C1) of FIG. 3 may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2).

[0143] In one embodiment, the first capacitor (C1) may have a multilayer structure including multilayer electrodes. For example, the first capacitor electrode (CE1) may include a first sub-electrode (CE1a) provided on a first conductive layer (CDL1) and a second sub-electrode (CE1b) provided on a second conductive layer (CDL2). The first sub-electrode (CE1a) and the second sub-electrode (CE1b) of the first capacitor electrode (CE1) may be electrically connected to each other through a fourth contact hole (CNT4) penetrating the second insulating layer (IL2). The second capacitor electrode (CE2) may include a first sub-electrode (CE2a) provided on a first bottom conductive layer (BCDL1) and a second sub-electrode (CE2b) provided on a second conductive layer (CDL2). In one embodiment, the second capacitor electrode (CE2) may further include a third sub-electrode (CE2c) provided on a third conductive layer (CDL3). The first sub-electrode (CE2a) and the second sub-electrode (CE2b) of the second capacitor electrode (CE2) can be electrically connected to each other through a fifth contact hole (CNT5) penetrating the first protective layer (PRL1), the first insulating layer (IL1), and the second insulating layer (IL2). The second sub-electrode (CE2b) and the third sub-electrode (CE2c) of the second capacitor electrode (CE2) can be electrically connected to each other through a seventh contact hole (CNT7) penetrating the third insulating layer (IL3). By forming the first capacitor (C1) in a multi-layer structure, the limited size of the pixel area (PXA) can be efficiently utilized to appropriately secure the capacity of the first capacitor (C1).

[0144] The structure of the first capacitor (C1) may vary depending on the embodiments. For example, the structure and position of each of the first capacitor electrode (CE1) and the second capacitor electrode (CE2) may vary depending on the embodiments.

[0145] In one embodiment, the first capacitor electrode (CE1) may be connected to the gate electrode (GE) of the first transistor (T1) located in each pixel area (PXA). For example, the first sub-electrode (CE1a) of the first capacitor electrode (CE1) may be provided integrally with the gate electrode (GE) of the first transistor (T1) on the first conductive layer (CDL1). For example, the first sub-electrode (CE1a) of the first capacitor electrode (CE1) and the gate electrode (GE) of the first transistor (T1) may be formed as an integral electrode that is connected to each other when viewed in a plane (for example, when viewed in a plane defined by the first direction (D1) and the second direction (D2)). In this case, the first gate insulating layer (GI1) located under the gate electrode (GE) of the first transistor (T1) and the second gate insulating layer (GI2) located under the first sub-electrode (CE1a) of the first capacitor electrode (CE1) may be an integral insulating pattern that is connected to each other.

[0146] In one embodiment, the second capacitor electrode (CE2) may be connected to the source electrode (SE) of the first transistor (T1) located in each pixel area (PXA). For example, the first sub-electrode (CE2a) of the second capacitor electrode (CE2) may be provided integrally with the first bottom electrode (BE1) of the first transistor (T1) on the first bottom conductive layer (BCDL1) and may be connected to the source electrode (SE) of the first transistor (T1) through the first contact hole (CNT1). The second sub-electrode (CE2b) of the second capacitor electrode (CE2) may be formed integrally with the source electrode (SE) of the first transistor (T1) located in each pixel area (PXA) or may be formed separately from the source electrode (SE). The third sub-electrode (CE2c) of the second capacitor electrode (CE2) may be formed integrally with the bridge electrode (BRE) located in each pixel area (PXA) or may be formed separately from the bridge electrode (BRE).

[0147] A light emitting element layer (LEL) may be disposed on the panel circuit layer (PCL). For example, the light emitting element layer (LEL) may be disposed on the fourth insulating layer (IL4) and may be located at least in the display area (DA).

[0148] The light emitting element layer (LEL) may include a light emitting element (ED) for each of the pixels (PX). For example, the light emitting element layer (LEL) may include a pixel defining layer (PDL) (also referred to as a “bank”) that defines a light emitting area of ​​each of the pixels (PX) and a light emitting element (ED) positioned in each light emitting area. In one embodiment, the light emitting element layer (LEL) may further include a spacer (SPC) disposed on a portion of the pixel defining layer (PDL).

[0149] Each light emitting element (ED) may include a first electrode (ET1) positioned in each light emitting region, and an emission layer (EML) and a second electrode (ET2) sequentially arranged on the first electrode (ET1). The first electrode (ET1) of the light emitting element (ED) may be connected to at least one transistor (for example, a first transistor (T1)) included in the corresponding pixel (PX).

[0150] The first electrode (ET1) of the light-emitting element (ED) may be a single-layer or multi-layer electrode including at least one conductive material. In one embodiment, the display panel (110) may be a front-emitting display panel, and the first electrode (ET1) may include a reflective electrode layer having a high reflectivity.

[0151] The emission layer (EML) of the light-emitting element (ED) may include a polymer material or a low-molecular material. Light emitted from the emission layer (EML) may contribute to image display.

[0152] The second electrode (ET2) of the light emitting element (ED) may include a conductive material. In one embodiment, the second electrode (ET2) may be a common film formed over the entire display area (DA) in a form that covers the light emitting layer (EML) and the pixel defining layer (PDL). In one embodiment, the display panel (110) may be a front-emitting display panel, and the second electrode (ET2) may include a transparent or translucent electrode layer.

[0153] The pixel defining layer (PDL) has an opening corresponding to each light-emitting area and can surround the light-emitting area. For example, the pixel defining layer (PDL) can be formed to cover an edge of a first electrode (ET1) of a light-emitting element (ED) and can include an opening that exposes the remaining portion of the first electrode (ET1). An area where the exposed first electrode (ET1) and the light-emitting layer (EML) overlap can be a light-emitting area of ​​each pixel (PX). In one embodiment, the pixel defining layer (PDL) can include at least one organic insulating layer including an organic insulating material.

[0154] A spacer (SPC) may be disposed on a portion of a pixel defining layer (PDL). The spacer (SPC) may include at least one organic insulating layer including an organic insulating material. The spacer (SPC) may include the same material as the pixel defining layer (PDL) or a different material from the pixel defining layer (PDL). The pixel defining layer (PDL) and the spacer (SPC) may be formed sequentially through separate mask processes, or may be formed simultaneously and / or integrally using a halftone mask.

[0155] An encapsulation layer (ENL) may be disposed on the light emitting element layer (LEL). The encapsulation layer (ENL) covers the light emitting element layer (LEL) in the display area (DA) and may extend to the non-display area (NDA) to be in contact with the panel circuit layer (PCL). The encapsulation layer (ENL) may block the penetration of oxygen or moisture into the light emitting element layer (LEL) and mitigate electrical and / or physical impacts on the panel circuit layer (PCL) and the light emitting element layer (LEL).

[0156] In one embodiment, the encapsulation layer (ENL) may include a first encapsulation layer (ENL1), a second encapsulation layer (ENL2), and a third encapsulation layer (ENL3) sequentially arranged on the light emitting element layer (LEL). Each of the first encapsulation layer (ENL1) and the third encapsulation layer (ENL3) may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer (ENL2) may be an organic encapsulation layer including an organic material.

[0157] Fig. 5 is a cross-sectional view showing area A1 of Fig. 4 in detail. Fig. 6 is a cross-sectional view showing area A1 of Fig. 4 in detail. For example, Figs. 5 and 6 are enlarged views showing the transistor (T) of Fig. 4 in detail, and show different embodiments with respect to the first bottom electrode (BE1) disposed under the active layer (ACT) of the transistor (T).

[0158] In addition to FIG. 4, referring to FIGS. 5 and 6, the first bottom electrode (BE1) may be formed as at least a double-layer electrode. For example, the first bottom electrode (BE1) may be formed as a double-layer electrode including a first metal layer (ML1a) and a second metal layer (ML1b) disposed on the first metal layer (ML1a), as illustrated in FIG. 5. Alternatively, the first bottom electrode (BE1) may be formed as a triple-layer electrode including a first metal layer (ML1a), a second metal layer (ML1b) disposed on the first metal layer (ML1a), and a third metal layer (ML1c) disposed under the first metal layer (ML1a), as illustrated in FIG. 6.

[0159] In one embodiment, the first metal layer (ML1a) may include a low-resistance metal having relatively low resistance. For example, the first metal layer (ML1a) may include aluminum (Al) or copper (Cu). The first metal layer (ML1a) may also include a low-resistance metal other than aluminum (Al) or copper (Cu). The first metal layer (ML1a) may have a relatively large thickness compared to the second metal layer (ML1b) or the third metal layer (ML1c). Accordingly, the resistance of the electrodes, conductive patterns, and / or wires provided to the first bottom conductive layer (BCDL1), including the first bottom electrode (BE1), can be reduced, and the response speed of the transistor (T) and the pixel (PX) including the transistor (PX) can be improved.

[0160] In one embodiment, each of the second metal layer (ML1b) and the third metal layer (ML1c) may include a capping metal capable of blocking ions of the first metal layer (ML1a) from diffusing to the surroundings. For example, each of the second metal layer (ML1b) and the third metal layer (ML1c) may include titanium (Ti). Each of the second metal layer (ML1b) and the third metal layer (ML1c) may also include a capping metal other than titanium (Ti).

[0161] The second metal layer (ML1b) can cover the upper surface of the first metal layer (ML1a). The third metal layer (ML1c) can cover the lower surface of the first metal layer (ML1a). Accordingly, the formation of voids or seams in or around the first metal layer (ML1a) can be suppressed, and the diffusion of hydrogen in the third direction (D3) or the like can be blocked.

[0162] In one embodiment, the second metal layer (ML1b) and the third metal layer (ML1c) may not be provided on a side surface (or at least a portion of the side surface) of the first metal layer (ML1a). For example, the second metal layer (ML1b) and the third metal layer (ML1c) may expose a side surface of the first metal layer (ML1a).

[0163] In embodiments, the exposed side surface of the first metal layer (ML1a) (for example, the inclined surface not covered by the second metal layer (ML1b) and the third metal layer (ML1c)) may be covered with the first protective layer (PRL1). Accordingly, the first metal layer (ML1a) can be appropriately protected from moisture or chemicals used in the manufacturing process of the display panel (110). For example, even if the first metal layer (ML1a) is formed of a low-resistance metal that is relatively vulnerable to corrosion, corrosion of the first metal layer (ML1a) can be prevented by covering the exposed side surface of the first metal layer (ML1a) with the first protective layer (PRL1).

[0164] In the embodiments, the first protective layer (PRL1) is made of the material exemplified above (for example, silicon nitride (SiN) x ), silicon oxide (SiO x ) and silicon oxynitride (SiON), and a first additive such as fluorine (F), chlorine (Cl), carbon (C), or sulfur (S). In one embodiment, the first protective layer (PRL1) may include silicon nitride (SiN) to which fluorine (F) is added. x :F) can be included. Accordingly, the characteristics of the transistor (T) can be improved while appropriately protecting the first metal layer (ML1a) and the first bottom electrode (BE1) including the first metal layer (ML1a).

[0165] When the first protective layer (PRL1) including fluorine (F) is disposed under the active layer (ACT), fluorine (F) can flow into or diffuse into the active layer (ACT). The fluorine (F) diffused into the active layer (ACT) can occupy the site of an oxygen vacancy existing in the active layer (ACT) and thereby reduce the oxygen vacancy of the active layer (ACT). Accordingly, the deviation in the characteristics of the transistor (T), such as the threshold voltage distribution, can be reduced. In one embodiment, the active layer (ACT) can be formed of a high-mobility oxide semiconductor, such as indium-tin-gallium-zinc oxide (ITGZO) or indium-gallium oxide (IGO), and the oxygen vacancy of the active layer (ACT) is reduced due to the diffusion of fluorine (F), thereby effectively improving (for example, uniformizing and / or stabilizing) the characteristics of the transistor (T) and the pixel (PX) including the transistor (T).

[0166] In addition, as fluorine (F) diffuses into the active layer (ACT), additional carriers may be generated. For example, fluorine (F) diffused into the active layer (ACT) may react with zinc oxide (ZnO) or the like (for example, oxygen and fluorine are substituted) to generate electrons as carriers. Accordingly, traps in the active layer (ACT) (for example, traps formed in the back-channel region adjacent to the first bottom electrode (BE1)) may be reduced, and the reliability (for example, PBTS (Positive Bias Temperature Stress) characteristics) of the transistor (T) may be improved. In one embodiment, the active layer (ACT) may be formed of an oxide semiconductor such as indium-gallium-zinc oxide (IGZO), and as carriers in the active layer (ACT) increase due to the diffusion of fluorine (F), the characteristics (for example, response speed, etc.) of the transistor (T) and the pixel (PX) including the transistor (T) may be effectively improved.

[0167] In one embodiment, the thickness of the first protective layer (PRL1) may be 100 Å or less. Accordingly, the amount of fluorine (F) or the like diffusing from the first protective layer (PRL1) to the active layer (ACT) can be appropriately limited, thereby preventing excessive changes in the characteristics of the transistor (T).

[0168] Fig. 7 is a cross-sectional view showing a display panel (110) according to one embodiment. Fig. 8 is a cross-sectional view showing area A2 of Fig. 7 in detail. Fig. 9 is a cross-sectional view showing area A2 of Fig. 7 in detail. For example, Figs. 8 and 9 are enlarged views showing the transistor (T) of Fig. 7 in detail, showing different embodiments with respect to the gate electrode (GE). Compared to the embodiments of Figs. 4 to 6, Figs. 7 to 9 show a display panel (110) that further includes a second protective layer (PRL2).

[0169] Referring to FIGS. 7 to 9, the gate electrode (GE) may be formed as at least a double-layer electrode. In one embodiment, the gate electrode (GE) may be formed as a double-layer electrode including a fourth metal layer (ML2a) (or a first metal layer of the gate electrode (GE)) and a fifth metal layer (ML2b) (or a second metal layer of the gate electrode (GE)) disposed on the fourth metal layer (ML2a), as illustrated in FIG. 8. Alternatively, the gate electrode (GE) may be formed as a triple-layer electrode including a fourth metal layer (ML2a), a fifth metal layer (ML2b) disposed on the fourth metal layer (ML2a), and a sixth metal layer (ML2c) (or a third metal layer of the gate electrode (GE)) disposed under the fourth metal layer (ML2a), as illustrated in FIG. 9.

[0170] In one embodiment, the fourth metal layer (ML2a) may include a low-resistance metal having relatively low resistance. For example, the fourth metal layer (ML2a) may include aluminum (Al) or copper (Cu). The fourth metal layer (ML2a) may also include a low-resistance metal other than aluminum (Al) or copper (Cu). The fourth metal layer (ML2a) may have a relatively large thickness compared to the fifth metal layer (ML2b) or the sixth metal layer (ML2c). Accordingly, the resistance of the electrodes, conductive patterns, and / or wires provided to the first conductive layer (CDL1), including the gate electrode (GE), can be reduced, and the response speed of the transistor (T) and the pixel (PX) including the transistor (PX) can be improved.

[0171] In one embodiment, each of the fifth metal layer (ML2b) and the sixth metal layer (ML2c) may include a capping metal capable of blocking ions of the fourth metal layer (ML2a) from diffusing to the surroundings. For example, each of the fifth metal layer (ML2b) and the sixth metal layer (ML2c) may include titanium (Ti). Each of the fifth metal layer (ML2b) and the sixth metal layer (ML2c) may also include a capping metal other than titanium (Ti).

[0172] The fifth metal layer (ML2b) can cover the upper surface of the fourth metal layer (ML2a). The sixth metal layer (ML2c) can cover the lower surface of the fourth metal layer (ML2a). Accordingly, the formation of voids or seams in or around the fourth metal layer (ML2a) can be suppressed, and the diffusion of hydrogen in the third direction (D3) or the like can be blocked.

[0173] In one embodiment, the fifth metal layer (ML2b) and the sixth metal layer (ML2c) may not be provided on a side surface (or at least a portion of a side surface) of the fourth metal layer (ML2a). For example, the fifth metal layer (ML2b) and the sixth metal layer (ML2c) may expose a side surface of the fourth metal layer (ML2a).

[0174] In embodiments, the exposed side surface of the fourth metal layer (ML2a) may be covered with a second protective layer (PRL2). For example, the display panel (110) may further include a second protective layer (PRL2). Accordingly, the fourth metal layer (ML2a) can be appropriately protected. For example, even if the fourth metal layer (ML2a) is formed of a low-resistance metal that is relatively vulnerable to corrosion, corrosion of the fourth metal layer (ML2a) can be prevented by covering the exposed side surface of the fourth metal layer (ML2a) (for example, an inclined surface not covered by the fifth metal layer (ML2b) and the sixth metal layer (ML2c)) with the second protective layer (PRL2).

[0175] The second protective layer (PRL2) may be disposed between the first conductive layer (CDL1) and the second insulating layer (IL2). For example, the second protective layer (PRL2) may be disposed on the first insulating layer (IL1), the semiconductor layer (SCL), the gate insulating layer (GI), and the first conductive layer (CDL1), so as to cover the patterns of the semiconductor layer (SCL), the gate insulating layer (GI), and the first conductive layer (CDL1). For example, the second protective layer (PRL2) may cover the gate electrode (GE) of the transistor (T), the first sub-electrode (CE1a) of the first capacitor electrode (CE1), and the like.

[0176] The second protective layer (PRL2) may include a material that can appropriately protect the patterns of the first conductive layer (CDL1) from moisture or chemicals used in the manufacturing process of the display panel (110). In one embodiment, the second protective layer (PRL2) may include silicon oxide (SiO x ) or silicon oxynitride (SiON), and the silicon oxide (SiO x ) or a second additive (or second material) added to silicon oxynitride (SiON). Silicon oxide (SiO x) or silicon oxynitride (SiON), thereby preventing or reducing diffusion of hydrogen from the second protective layer (PRL2) to the active layer (ACT).

[0177] In one embodiment, the second additive may include at least one of fluorine (F), chlorine (Cl), carbon (C), and sulfur (S). As an example, the second protective layer (PRL2) may include silicon oxide (SiO) to which fluorine (F) is added. x :F) or silicon oxynitride (SiON:F), silicon oxide (SiO) with chlorine (Cl) added x :Cl) or silicon oxynitride (SiON:Cl), carbon (C) added silicon oxide (SiO x :C) or silicon oxynitride (SiON:C), or silicon oxide (SiO) with sulfur (S) added x :S) or silicon oxynitride (SiON:S). The concentration of the second additive, for example, fluorine (F), chlorine (Cl), carbon (C), or sulfur (S)) included in the second protective layer (PRL2) may be 2.5 times or more the concentration of fluorine (F), chlorine (Cl), carbon (C), or sulfur (S) included in the second insulating layer (IL2) (or the lower layer of the second insulating layer (IL2)) on the second protective layer (PRL2).

[0178] In one embodiment, the second protective layer (PRL2) is a silicon oxide (SiO) doped with fluorine (F). x:F) or silicon oxynitride (SiON:F). Accordingly, the fourth metal layer (ML2a) and the first conductive layer (CDL1) including the fourth metal layer (ML2a) can be appropriately protected while improving the characteristics of the transistor (T). For example, fluorine (F) of the second protective layer (PRL2) can flow into or diffuse into the active layer (ACT), thereby reducing oxygen vacancies in the active layer (ACT). In addition, the fluorine (F) that flows into or diffuses into the active layer (ACT) can generate carriers (e.g., electrons). Accordingly, the characteristic deviation of the transistor (T) can be prevented or reduced, and the reliability and operating characteristics of the transistor (T) can be improved.

[0179] Fig. 10 is a cross-sectional view showing a display panel (110) according to one embodiment. Fig. 11 is a cross-sectional view showing area A3 of Fig. 10 in detail. Fig. 12 is a cross-sectional view showing area A3 of Fig. 10 in detail. For example, Figs. 11 and 12 show different embodiments with respect to the first bottom electrode (BE1) and the second bottom electrode (BE2). Compared to the embodiments described above (for example, the embodiments of Figs. 4 to 6 or the embodiments of Figs. 7 to 9), Figs. 10 to 12 show a display panel (110) further including a second bottom conductive layer (BCDL2) and a third protective layer (PRL3).

[0180] Referring to FIGS. 10 to 12, the display panel (110) may further include a second bottom conductive layer (BCDL2) and a third protective layer (PRL3) disposed between the substrate (SUB) and the barrier layer (BR).

[0181] The second bottom conductive layer (BCDL2) (also referred to as the “second bottom conductive layer” or the “fifth conductive layer”) may include a second bottom electrode (BE2) disposed below the transistor (T). For example, the second bottom conductive layer (BCDL2) may further include a second bottom electrode (BE2) disposed below the first bottom electrode (BE1). In one embodiment, the second bottom conductive layer (BCDL2) may further include a third sub-electrode (CE1c) of the first capacitor electrode (CE1).

[0182] The second bottom electrode (BE2) may overlap the first bottom electrode (BE1). Accordingly, a capacitor (for example, the second capacitor (C2) of FIG. 3) may be formed between the second bottom electrode (BE2) and the first bottom electrode (BE1). For example, the second bottom electrode (BE2) may form a third capacitor electrode (CE3), and the first bottom electrode (BE1) may form a fourth capacitor electrode. The third capacitor electrode (CE3) and the fourth capacitor electrode may form the second capacitor (C2) of FIG. 3. Alternatively, the second bottom electrode (BE2) may be formed integrally with the third sub-electrode (CE1c) of the first capacitor electrode (CE1) to form the first capacitor (C1).

[0183] The third sub-electrode (CE1c) of the first capacitor electrode (CE1) may overlap at least one sub-electrode forming the second capacitor electrode (CE2) (for example, the first sub-electrode (CE2a) of the second capacitor electrode (CE2)). The third sub-electrode (CE1c) of the first capacitor electrode (CE1) may be connected to at least one of the first sub-electrode (CE1a) and the second sub-electrode (CE1b) of the first capacitor electrode (CE1). For example, the third sub-electrode (CE1c) of the first capacitor electrode (CE1) may be electrically connected to the second sub-electrode (CE1b) of the first capacitor electrode (CE1) through a ninth contact hole (CNT9) penetrating the second insulating layer (IL2), the second protective layer (PRL2), the first insulating layer (IL1), the first protective layer (PRL1), the barrier layer (BR), and the third protective layer (PRL3).

[0184] The electrodes, conductive patterns and / or wires provided or arranged on the second bottom conductive layer (BCDL2) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. The electrodes, conductive patterns and / or wires provided or arranged on the second bottom conductive layer (BCDL2) may be formed as a single layer or multiple layers.

[0185] In one embodiment, the electrodes, conductive patterns, and / or wires provided or arranged on the second bottom conductive layer (BCDL2) may be formed as at least a double layer. For example, the second bottom electrode (BE2) may be formed as a double layer electrode including a seventh metal layer (ML3a) (or a first metal layer of the second bottom electrode (BE2)) and an eighth metal layer (ML3b) (or a second metal layer of the second bottom electrode (BE2)) arranged on the seventh metal layer (ML3a), as illustrated in FIG. 11. Alternatively, the second bottom electrode (BE2) may be formed as a triple-layer electrode including a seventh metal layer (ML3a), an eighth metal layer (ML3b) disposed on the seventh metal layer (ML3a), and a ninth metal layer (ML3c) disposed under the seventh metal layer (ML3a) (or the third metal layer of the second bottom electrode (BE2)), as illustrated in FIG. 12.

[0186] In one embodiment, the seventh metal layer (ML3a) may include a low-resistance metal having relatively low resistance. For example, the seventh metal layer (ML3a) may include aluminum (Al) or copper (Cu). The seventh metal layer (ML3a) may also include a low-resistance metal other than aluminum (Al) or copper (Cu). The seventh metal layer (ML3a) may have a relatively large thickness compared to the eighth metal layer (ML3b) or the ninth metal layer (ML3c). Accordingly, the resistance of the electrodes, conductive patterns, and / or wires provided on the second bottom conductive layer (BCDL2), including the second bottom electrode (BE2), can be reduced.

[0187] In one embodiment, each of the eighth metal layer (ML3b) and the ninth metal layer (ML3c) may include a capping metal capable of blocking ions of the seventh metal layer (ML3a) from diffusing to the surroundings. For example, each of the eighth metal layer (ML3b) and the ninth metal layer (ML3c) may include titanium (Ti). Each of the eighth metal layer (ML3b) and the ninth metal layer (ML3c) may also include a capping metal other than titanium (Ti).

[0188] The eighth metal layer (ML3b) can cover the upper surface of the seventh metal layer (ML3a). The ninth metal layer (ML3c) can cover the lower surface of the seventh metal layer (ML3a). Accordingly, the formation of voids or seams in or around the seventh metal layer (ML3a) can be suppressed, and the diffusion of hydrogen in the third direction (D3) or the like can be blocked.

[0189] In one embodiment, the eighth metal layer (ML3b) and the ninth metal layer (ML3c) may not be provided on a side surface (or at least a portion of a side surface) of the seventh metal layer (ML3a). For example, the eighth metal layer (ML3b) and the ninth metal layer (ML3c) may expose a side surface of the seventh metal layer (ML3a).

[0190] In embodiments, the exposed side surface of the seventh metal layer (ML3a) may be covered with a third protective layer (PRL3). For example, the display panel (110) may further include a third protective layer (PRL3). Accordingly, the seventh metal layer (ML3a) can be appropriately protected. For example, even if the seventh metal layer (ML3a) is formed of a low-resistance metal that is relatively vulnerable to corrosion, corrosion of the seventh metal layer (ML3a) can be prevented by covering the exposed side surface of the seventh metal layer (ML3a) (for example, an inclined surface not covered by the eighth metal layer (ML3b) and the ninth metal layer (ML3c)) with the third protective layer (PRL3).

[0191] The third protective layer (PRL3) may be disposed between the second bottom conductive layer (BCDL1) and the barrier layer (BR). For example, the third protective layer (PRL3) may be disposed on the substrate (SUB) and the second bottom conductive layer (BCDL2) to cover the patterns of the second bottom conductive layer (BCDL2). For example, the third protective layer (PRL3) may cover the second bottom electrode (BE2) and the third sub-electrode (CE1c) of the first capacitor electrode (CE1).

[0192] The third protective layer (PRL3) may include a material that can appropriately protect the patterns of the second bottom conductive layer (BCDL2) from moisture or chemicals used in the manufacturing process of the display panel (110). In one embodiment, the third protective layer (PRL3) may include silicon nitride (SiN). x ), silicon oxide (SiO x ) and silicon oxynitride (SiON), and a third additive (or third material) added thereto. In one embodiment, silicon nitride (SiN x ) to form a third protective layer (PRL3), the barrier effect that blocks the diffusion of moisture or hydrogen, etc. can be enhanced.

[0193] In one embodiment, the third additive may include at least one of fluorine (F), chlorine (Cl), carbon (C), and sulfur (S). As an example, the third protective layer (PRL3) may include silicon nitride (SiN) to which fluorine (F) is added. x :F), silicon nitride (SiN) with added chlorine (Cl) x :Cl), carbon (C) added silicon nitride (SiN) x :C), sulfur (S) added silicon nitride (SiN) x :S), silicon oxide (SiO) with added fluorine (F) x :F) or silicon oxynitride (SiON:F), silicon oxide (SiO) with chlorine (Cl) added x:Cl) or silicon oxynitride (SiON:Cl), carbon (C) added silicon oxide (SiO x :C) or silicon oxynitride (SiON:C), or silicon oxide (SiO) with sulfur (S) added x :S) or silicon oxynitride (SiON:S). The concentration of the third additive, for example, fluorine (F), chlorine (Cl), carbon (C), or sulfur (S), included in the third protective layer (PRL3) may be 2.5 times or more the concentration of fluorine (F), chlorine (Cl), carbon (C), or sulfur (S) included in the barrier layer (BR) (or the lower layer of the barrier layer (BR)) on the third protective layer (PRL3).

[0194] In one embodiment, the third protective layer (PRL3) is silicon nitride (SiN) doped with fluorine (F). x :F) may be included. Accordingly, the seventh metal layer (ML3a) and the second bottom electrode (BE2) including the seventh metal layer (ML3a) may be appropriately protected while improving the characteristics of the transistor (T). For example, the amount of fluorine (F) flowing into or diffusing into the active layer (ACT) may be increased by the third protective layer (PRL3) including fluorine (F). In addition, the fluorine (F) flowing into or diffusing into the active layer (ACT) may reduce oxygen vacancies in the active layer (ACT) and generate carriers (e.g., electrons). Accordingly, the characteristic deviation of the transistor (T) may be prevented or reduced, and the reliability and operating characteristics of the transistor (T) may be improved.

[0195] Fig. 13 is a graph showing the fluorine (F) concentration measured in a display panel (110) including a first protective layer (PRL1). For example, Fig. 13 shows the concentration of fluorine (F) measured in the first protective layer (PRL1) and the surrounding film of the first protective layer (PRL1) through SIMS (Secondary Ion Mass Spectrometry) analysis.

[0196] Referring to FIGS. 4 to 13, it can be confirmed that the fluorine (F) component rapidly increases at a position where the first passivation layer (PRL1) is provided, for example, at the interface between the first layer (IL1a) of the first insulating layer (IL) including silicon nitride (SiNx) and the second metal layer (ML1b) of the first bottom electrode (BE1) including titanium (Ti). For example, in a display panel (110) including the first passivation layer (PRL1) to which fluorine (F) is added, the concentration of fluorine (F) measured at the position where the first passivation layer (PRL1) is provided may rapidly increase compared to the concentration of fluorine (F) in the surroundings. For example, the concentration of fluorine (F) measured at the position where the first passivation layer (PRL1) is provided may be 2.5 times or more the concentration of fluorine (F) measured in the surroundings.

[0197] In one embodiment, the display panel (110) may further include at least one of a second protective layer (PRL2) and a third protective layer (PRL3). In this case, the fluorine (F) component may rapidly increase even at locations where the second protective layer (PRL2) and / or the third protective layer (PRL3) are provided.

[0198] FIGS. 14 to 25 are cross-sectional views showing a method of manufacturing a display device (100) according to one embodiment. For example, FIGS. 14 to 25 sequentially show steps of forming a panel circuit layer (PCL) among the steps of manufacturing the display panel (110) of FIG. 10.

[0199] Referring to Fig. 14, a substrate (SUB) including a display area (DA) can be provided. The display area (DA) can include a pixel area (PXA).

[0200] Thereafter, a second bottom conductive layer (BCDL2) can be formed on the substrate (SUB) (or an additional barrier layer disposed on the substrate (SUB). For example, a second bottom electrode (BE2) and a third sub-electrode (CE1c) of the first capacitor electrode (CE1) can be formed on the substrate (SUB).

[0201] The patterns of the second bottom conductive layer (BCDL2) (for example, the second bottom electrode (BE2) and the third sub-electrode (CE1c) of the first capacitor electrode (CE1)) can be formed by a film formation process (for example, a deposition process) of a conductive film using at least one conductive material as exemplified above and a patterning process (for example, an etching process using a mask) of the conductive film. In one embodiment, each of the patterns of the second bottom conductive layer (BCDL2) can be formed as a double layer including a seventh metal layer (ML3a) and an eighth metal layer (ML3b) as illustrated in FIG. 11, or as a triple layer including a seventh metal layer (ML3a), an eighth metal layer (ML3b), and a ninth metal layer (ML3c) as illustrated in FIG. 12.

[0202] Referring to FIG. 15, a third protective layer (PRL3) covering a second bottom conductive layer (BCDL2) can be formed on a substrate (SUB). For example, the third protective layer (PRL3) can be formed on patterns of the second bottom conductive layer (BCDL2) including the second bottom electrode (BE2) and the third sub-electrode (CE1c) of the first capacitor electrode (CE1). The third protective layer (PRL3) can be formed of the material exemplified above (for example, silicon nitride (SiN)). x ), silicon oxide (SiO x ) and silicon oxynitride (SiON), and at least one of fluorine (F), chlorine (Cl), carbon (C), and sulfur (S). The third protective layer (PRL3) may be formed to cover the side of the seventh metal layer (ML3a) that is not covered by the eighth metal layer (ML3b) and the ninth metal layer (ML3c).

[0203] When manufacturing a display panel (110) that does not include the second bottom conductive layer (BCDL2) and the third protective layer (PRL3) as in the embodiment of FIG. 4 or FIG. 7, the step of forming the second bottom conductive layer (BCDL2) and the third protective layer (PRL3) may be omitted.

[0204] Referring to Fig. 16, a barrier layer (BR) can be formed on the third protective layer (PRL3) (or substrate (SUB)). The barrier layer (BR) can be formed by a film formation process of an insulating film using the insulating material (e.g., an inorganic insulating material) exemplified above.

[0205] Referring to FIG. 17, a first bottom conductive layer (BCDL1) can be formed on the barrier layer (BR). For example, a first bottom conductive layer (BCDL1) including a first bottom electrode (BE1) and a first sub-electrode (CE2a) of a second capacitor electrode (CE2) can be formed on the barrier layer (BR).

[0206] The patterns of the first bottom conductive layer (BCDL1) (for example, the first bottom electrode (BE1) and the first sub-electrode (CE2a) of the second capacitor electrode (CE2)) can be formed by a process for forming a conductive film using at least one conductive material as exemplified above and a process for patterning the conductive film. In one embodiment, each of the patterns of the first bottom conductive layer (BCDL1) can be formed as a double layer including a first metal layer (ML1a) and a second metal layer (ML1b), as illustrated in FIG. 11, or as a triple layer including a first metal layer (ML1a), a second metal layer (ML1b), and a third metal layer (ML1c), as illustrated in FIG. 12.

[0207] Referring to FIG. 18, a first protective layer (PRL1) covering a first bottom conductive layer (BCDL1) can be formed on a barrier layer (BR) (or substrate (SUB)). For example, the first protective layer (PRL1) can be formed on patterns of the first bottom conductive layer (BCDL1) including the first bottom electrode (BE1) and the first sub-electrode (CE2a) of the second capacitor electrode (CE2). The first protective layer (PRL1) can be formed of the material exemplified above (for example, silicon nitride (SiN)). x ), silicon oxide (SiO x) and silicon oxynitride (SiON), and at least one of fluorine (F), chlorine (Cl), carbon (C), and sulfur (S). The first protective layer (PRL1) may be formed to cover a side of the first metal layer (ML1a) that is not covered by the second metal layer (ML1b), the third metal layer (ML1c), etc.

[0208] Referring to Fig. 19, a first insulating layer (IL1) can be formed on a first protective layer (PRL1). The first insulating layer (IL1) can be formed by a film formation process of an insulating film using at least one insulating material (e.g., an inorganic insulating material) as exemplified above.

[0209] In one embodiment, the first insulating layer (IL1) may be formed as at least a double layer including a first layer (IL1a) and a second layer (IL1b). For example, the double layer first insulating layer (IL1) may be formed by sequentially forming the first layer (IL1a) (e.g., a silicon nitride layer) and the second layer (IL1b) (e.g., at least one of a silicon oxide layer and a silicon oxynitride layer) on the first protective layer (PRL1).

[0210] Referring to Fig. 20, a semiconductor layer (SCL) including an active layer (ACT) can be formed on a first insulating layer (IL1). The active layer (ACT) can be formed in each transistor region. The active layer (ACT) can be formed of the material exemplified above. For example, a film formation process and a patterning process (e.g., an etching process using a mask) of a semiconductor film using at least one oxide semiconductor exemplified above can be performed to form an active layer (ACT) including an oxide semiconductor.

[0211] Referring to FIG. 21, a gate insulating layer (GI) and a first conductive layer (CDL1) may be formed on a first insulating layer (IL1). The gate insulating layer (GI) may include a first gate insulating layer (GI1) and a second gate insulating layer (GI2), and the first conductive layer (CDL1) may include a gate electrode (GE) and a first sub-electrode (CE1a) of a first capacitor electrode (CE1). The first gate insulating layer (GI1) and the gate electrode (GE) may be formed on a portion of an active layer (ACT). The second gate insulating layer (GI2) and the first sub-electrode (CE1a) of the first capacitor electrode (CE1) may be formed on a portion of the first insulating layer (IL1) on which the active layer (ACT) is not disposed.

[0212] The gate insulating layer (GI) can be formed by a film deposition process using at least one insulating material (e.g., an inorganic insulating material such as silicon oxide) as exemplified above and a patterning process (e.g., an etching process using a mask).

[0213] The patterns of the first conductive layer (CDL1) (for example, the gate electrode (GE) and the first sub-electrode (CE1a) of the first capacitor electrode (CE1)) can be formed by a process of forming a conductive film using at least one conductive material as exemplified above and a process of patterning the conductive film. In one embodiment, each of the patterns of the first conductive layer (CDL1) can be formed as a double layer including a fourth metal layer (ML2a) and a fifth metal layer (ML2b) as illustrated in FIG. 11, or as a triple layer including a fourth metal layer (ML2a), a fifth metal layer (ML2b), and a sixth metal layer (ML2c) as illustrated in FIG. 12.

[0214] In one embodiment, the first conductive layer (CDL1) and the gate insulating layer (GI) can be etched sequentially or substantially simultaneously by an etching process using a single mask. For example, the mask used in the etching process of the first conductive layer (CDL1) can be utilized, or the first conductive layer (CDL1) can be utilized as a mask to etch the gate insulating layer (GI). Accordingly, the gate insulating layer (GI) can be patterned in a shape corresponding to the first conductive layer (CDL1). For example, the patterns of the gate insulating layer (GI) can have a shape and / or size corresponding to the patterns of the first conductive layer (CDL1).

[0215] During the etching process of the gate insulating layer (GI), the properties of the active layer (ACT) can be changed so that each portion of the active layer (ACT) has different characteristics. Accordingly, the active layer (ACT) can be divided into multiple regions with different characteristics.

[0216] For example, oxygen vacancies may occur in the oxide semiconductor forming the active layer (ACT) by an etching gas or the like, mainly in a portion that does not overlap with the gate electrode (GE) and the first gate insulating layer (GI1). Accordingly, the active layer (ACT) may be divided into a plurality of regions (e.g., a channel region (CH), a source region (SR), and a drain region (DR)) having different characteristics. In one embodiment, the oxygen vacancies may primarily occur in a portion of the active layer (ACT) that does not overlap with the gate electrode (GE) and the first gate insulating layer (GI1) (e.g., the source region (SR) and the drain region (DR)), and may spread to a portion of the region that overlaps with the gate electrode (GE) and / or the first gate insulating layer (GI1).

[0217] Referring to FIG. 22, a second protective layer (PRL2) covering a semiconductor layer (SCL), a gate insulating layer (GI), and a first conductive layer (CDL4) can be formed on a first insulating layer (IL1). For example, the second protective layer (PRL2) can be formed on the patterns of the semiconductor layer (SCL), the gate insulating layer (GI), and the first conductive layer (CDL4). The second protective layer (PRL2) can be formed of the material exemplified above (for example, silicon oxide (SiO). x ) and silicon oxynitride (SiON), and at least one of fluorine (F), chlorine (Cl), carbon (C), and sulfur (S). The second protective layer (PRL2) may be formed to cover the side of the fourth metal layer (ML2a) that is not covered by the fifth metal layer (ML2b) and the sixth metal layer (ML2c).

[0218] When manufacturing a display panel (110) that does not include a second protective layer (PRL2) as in the embodiment of FIG. 4, the step of forming the second protective layer (PRL2) may be omitted.

[0219] Referring to FIG. 23, a second insulating layer (IL2) can be formed on the second protective layer (PRL2). For example, the second insulating layer (IL2) can be formed on the active layer (ACT), the first and second gate insulating layers (GI1, GI2), the gate electrode (GE), and the first sub-electrode (CE1a) of the first capacitor electrode (CE1). The second insulating layer (IL2) can be formed of at least one insulating material (for example, silicon oxide (SiO)) exemplified above. x ) or an inorganic insulating material such as silicon oxynitride (SiON). The second insulating layer (IL2) can be formed as a single layer or multiple layers.

[0220] Hydrogen may be introduced into the active layer (ACT) during the process of forming the second insulating layer (IL2) and / or the heat treatment process before and after the process. As hydrogen is introduced into the active layer (ACT), a portion of the active layer (ACT) may become conductive (e.g., N-type conductive) centered on a portion containing a large number of oxygen vacancies. For example, the source region (SR) and drain region (DR) may become conductive.

[0221] After the second insulating layer (IL2) is formed, a plurality of contact holes can be formed in the second insulating layer (IL2), etc. For example, the first, second, third, fourth, fifth, and ninth contact holes (CNT1, CNT2, CNT3, CNT4, CNT5, CNT9) can be formed by an etching process using a mask. In one embodiment, the first, second, third, fourth, fifth, and ninth contact holes (CNT1, CNT2, CNT3, CNT4, CNT5, CNT9) can be formed substantially simultaneously in a single mask process, but the embodiments are not limited thereto.

[0222] Referring to FIG. 24, a second conductive layer (CDL2) may be formed on a second insulating layer (IL2). The second conductive layer (CDL2) may include a source electrode (SE) and a drain electrode (DE) of the transistor (T), a second sub-electrode (CE1b) of the first capacitor electrode (CE1), and a second sub-electrode (CE2b) of the second capacitor electrode (CE2). In one embodiment, when at least one of the source region (SR) and the drain region (DR) of the active layer (ACT) replaces at least one of the source electrode (SE) and the drain electrode (DE), at least one of the source electrode (SE) and the drain electrode (DE) may not be formed.

[0223] The patterns of the second conductive layer (CDL2) (for example, the source electrode (SE) and the drain electrode (DE) of the transistor (T), the second sub-electrode (CE1b) of the first capacitor electrode (CE1), and the second sub-electrode (CE2b) of the second capacitor electrode (CE2)) can be formed by a process for forming a conductive film using at least one conductive material as exemplified above and a process for patterning the conductive film.

[0224] Referring to Fig. 25, a third insulating layer (IL3), a third conductive layer (CDL3), and a fourth insulating layer (IL4) can be sequentially formed on a second insulating layer (IL2) and a second conductive layer (CDL2). When manufacturing a display panel (110) that does not include a third conductive layer (CDL3), the process of forming the third conductive layer (CDL3) and the fourth insulating layer (IL4) (or the third insulating layer (IL3)) can be omitted.

[0225] The third insulating layer (IL3) may be formed on the second insulating layer (IL2) by a film formation process using at least one of the organic insulating materials exemplified above. A plurality of contact holes may be formed in the third insulating layer (IL3). For example, a sixth contact hole (CNT6) and a seventh contact hole (CNT7) may be formed in the third insulating layer (IL3).

[0226] A third conductive layer (CDL3) may be formed on the third insulating layer (IL3). The third conductive layer (CDL3) may include a bridge electrode (BRE) and a third sub-electrode (CE2c) of the second capacitor electrode (CE2). In one embodiment, when the second capacitor electrode (CE2) does not include the third sub-electrode (CE2c), the third sub-electrode (CE2c) may not be formed.

[0227] The patterns of the third conductive layer (CDL3) can be formed by a process for forming a conductive film using at least one conductive material as exemplified above and a process for patterning the conductive film.

[0228] The fourth insulating layer (IL4) may be formed on the third insulating layer (IL3) and the third conductive layer (CDL3). The fourth insulating layer (IL4) may be formed by a film deposition process of an insulating film using at least one organic insulating material as exemplified above. An eighth contact hole (CNT8) exposing the bridge electrode (BRE) (or source electrode (SE)) may be formed in the fourth insulating layer (IL4).

[0229] Through the above-described process, the panel circuit layer (PCL) of the display panel (110) can be formed. When the display panel (110) includes a light-emitting element layer (LEL) and an encapsulation layer (ENL) as in the embodiments of FIGS. 4, 7, and 10, the light-emitting element layer (LEL) and the encapsulation layer (ENL) can be sequentially formed on the panel circuit layer (PCL). Through the above-described process, the display panel (110) according to the embodiments and the display device (100) including the same can be manufactured.

[0230] As described above, according to the display device (100) and the manufacturing method thereof according to the embodiments, a conductive layer (for example, at least one of a first bottom conductive layer (BCDL1) including a first bottom electrode (BE1), a second bottom conductive layer (BCDL2) including a second bottom electrode (BE2), and a first conductive layer (CDL1) including a gate electrode (GE)) of the display panel (110) can be formed using a low-resistance metal such as aluminum (Al) or copper (Cu). Accordingly, the resistance of the conductive layer and the display panel (110) including the conductive layer can be reduced. In addition, the conductive layer can be covered with a protective layer (for example, at least one of a first protective layer (PRL1), a second protective layer (PRL2), and a third protective layer (PRL3)) including an additive such as fluorine (F), thereby effectively preventing corrosion of the conductive layer. Accordingly, the operating characteristics and reliability of the display device (100) can be improved.

[0231] For example, in the embodiments, a first bottom conductive layer (BCDL1) including a first bottom electrode (BE1) disposed under an active layer (ACT) (for example, an active layer of an oxide transistor (T) including an oxide semiconductor) is formed of silicon nitride (SiN). x ), silicon oxide (SiO x ) and silicon oxynitride (SiON) and a first additive, and a first insulating layer (IL1) and an active layer (ACT) can be disposed on the first protective layer (PRL1). Accordingly, the patterns of the first bottom conductive layer (BCDL1) (for example, electrodes, wires and / or conductive patterns disposed on the first bottom conductive layer (BCDL1)) can be appropriately protected. According to embodiments, by forming the first bottom conductive layer (BCDL1) using a low-resistance metal, the resistance of the first bottom conductive layer (BCDL1) can be lowered, while corrosion of the first bottom conductive layer (BCDL1) can be prevented, thereby increasing the reliability of the display device.

[0232] In some embodiments, the patterns of the first bottom conductive layer (BCDL1) may be covered with a first passivation layer (PRL1) including fluorine (F). Accordingly, the characteristics of an oxide transistor (T) including an active layer (ACT) disposed on the first passivation layer (PRL1) may be improved.

[0233] In some embodiments, at least one of a first conductive layer (CDL1) including a gate electrode (GE) disposed on an active layer (ACT) of an oxide transistor (T) and a second bottom conductive layer (BCDL2) including a second bottom electrode (BE2) disposed on a lower portion of the first bottom electrode (BE1) may be formed of a low-resistance metal and covered with a protective layer (for example, at least one of the second protective layer (PRL2) and the third protective layer (PRL3)) including each additive. Accordingly, the resistance of at least one of the first conductive layer (CDL1) and the second bottom conductive layer (BCDL2) may be lowered while preventing corrosion.

[0234] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A first bottom electrode disposed on the substrate; A first protective layer disposed on the first bottom electrode and including at least one of silicon nitride, silicon oxide and silicon oxynitride, and a first additive; A first insulating layer disposed on the first protective layer; An active layer disposed on the first insulating layer and including an oxide semiconductor; A gate insulating layer disposed on the above active layer; a gate electrode disposed on the gate insulating layer; and A second insulating layer is disposed on the gate electrode, The first bottom electrode comprises a first metal layer, and a second metal layer disposed on the first metal layer and exposing a side surface of the first metal layer, A display device, wherein the first protective layer covers an exposed side surface of the first metal layer.

2. In paragraph 1, The first metal layer comprises aluminum or copper, A display device, wherein the second metal layer comprises titanium.

3. In paragraph 2, A display device, wherein the first bottom electrode is disposed below the first metal layer and further includes a third metal layer including titanium.

4. In paragraph 1, A display device wherein the first additive comprises at least one of fluorine, chlorine, carbon, and sulfur.

5. In paragraph 4, A display device, wherein the concentration of fluorine, chlorine, carbon or sulfur included in the first protective layer is 2.5 times or more the concentration of fluorine, chlorine, carbon or sulfur included in the first insulating layer.

6. In paragraph 1, The above first protective layer comprises silicon nitride with added fluorine, A display device wherein the thickness of the first protective layer is 100Å or less.

7. In paragraph 1, The above first insulating layer is, a silicon nitride layer disposed on the first protective layer; and A display device comprising at least one of a silicon oxide layer and a silicon oxynitride layer disposed on the silicon nitride layer.

8. In paragraph 1, A display device, wherein the active layer comprises at least one of indium-gallium-zinc oxide, indium-tin-gallium-zinc oxide, and indium-gallium oxide.

9. In paragraph 1, A display device, wherein the gate electrode further includes a fourth metal layer including aluminum or copper, a fifth metal layer including titanium disposed on the fourth metal layer, and a sixth metal layer including titanium disposed under the fourth metal layer.

10. In paragraph 9, A display device further comprising a second protective layer disposed between the gate electrode and the second insulating layer, covering the gate electrode and including silicon oxide or silicon oxynitride and a second additive.

11. In paragraph 10, A display device wherein the second additive comprises at least one of fluorine, chlorine, carbon, and sulfur.

12. In paragraph 1, A display device, wherein the second insulating layer comprises at least one of silicon oxide and silicon oxynitride.

13. In paragraph 1, A barrier layer disposed between the substrate and the first bottom electrode; a second bottom electrode disposed between the substrate and the barrier layer; and A display device further comprising a third protective layer disposed between the second bottom electrode and the barrier layer, covering the second bottom electrode, and including at least one of silicon nitride, silicon oxide, and silicon oxynitride and a third additive.

14. In paragraph 13, A display device wherein the second bottom electrode further includes a seventh metal layer including aluminum or copper, an eighth metal layer including titanium disposed on the seventh metal layer, and a ninth metal layer including titanium disposed below the seventh metal layer.

15. In paragraph 13, A display device wherein the third additive comprises at least one of fluorine, chlorine, carbon, and sulfur.

16. In paragraph 1, further comprising at least one of a source electrode and a drain electrode disposed on the second insulating layer and electrically connected to the active layer; A display device, wherein the first bottom electrode overlaps the active layer and is electrically connected to the source electrode.

17. A step of forming a first bottom electrode including a first metal layer and a second metal layer on the first metal layer on a substrate; A step of forming a first protective layer on the substrate, covering the first bottom electrode and including at least one of silicon nitride, silicon oxide and silicon oxynitride and a first additive; A step of forming a first insulating layer on the first protective layer; A step of forming an active layer including an oxide semiconductor on the first insulating layer; A step of forming a gate insulating layer and a gate electrode on the active layer; and A step of forming a second insulating layer on the active layer, the gate insulating layer, and the gate electrode, The second metal layer exposes a side surface of the first metal layer, A method for manufacturing a display device, wherein the first protective layer covers an exposed side surface of the first metal layer.

18. In paragraph 17, A method for manufacturing a display device, wherein the first additive comprises at least one of fluorine, chlorine, carbon, and sulfur.

19. In Article 17, Prior to forming the second insulating layer, a step of forming a second protective layer covering the gate electrode and including silicon oxide or silicon oxynitride and a second additive is further included. A method for manufacturing a display device, wherein the second additive comprises at least one of fluorine, chlorine, carbon, and sulfur.

20. In paragraph 17, Prior to forming the first bottom electrode, the method further comprises the step of sequentially forming a second bottom electrode, a third protective layer covering the second bottom electrode, and a barrier layer covering the third protective layer on the substrate. A method for manufacturing a display device, wherein the third protective layer comprises a third additive comprising at least one of silicon nitride, silicon oxide, and silicon oxynitride, and at least one of fluorine, chlorine, carbon, and sulfur.

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