Electronic device having high anisotropy through edge contact of material having asymmetric crystal structure, and method for manufacturing same

Abstract

An electronic device is provided. The electronic device may comprise: a substrate; a first electrode and a second electrode disposed to be spaced apart from each other on the substrate; a semiconductor layer which is disposed on the substrate between the first electrode and the second electrode such that one side surface is in contact with the first electrode and the other side surface is in contact with the second electrode, and includes a material having an asymmetric crystal structure; and a third electrode disposed on the semiconductor layer, wherein the first electrode is in contact with only the one side surface of the semiconductor layer, and the second electrode is in contact with only the other side surface of the semiconductor layer.

Description

Electronic device with high anisotropy through edge contact of a material having an asymmetric crystal structure and method for manufacturing the same

[0001] The present invention relates to an electronic device and a method for manufacturing the same, and more particularly, to an electronic device having high anisotropy through edge contact of a material having an asymmetric crystal structure and a method for manufacturing the same.

[0002] Since the discovery of monolayer black phosphorus (BP) in 2014, interest in anisotropic two-dimensional materials such as black phosphorus, rhenium diselenide (ReSe2), and group VI monochalcogenides has increased, and research on anisotropic two-dimensional materials is actively underway.

[0003] In particular, anisotropic two-dimensional materials have been confirmed to have anisotropy in electrical and optical properties along various crystallographic directions, and this anisotropy is being utilized in various applications such as tunneling field-effect transistors, inverters, and photodetectors.

[0004] The technical problem to be solved by the present invention is to provide an electronic device using a material having an asymmetric crystal structure and a method for manufacturing the same.

[0005] Another technical problem to be solved by the present invention is to provide an electronic device having high anisotropy and a method for manufacturing the same.

[0006] Another technical problem that the present invention seeks to solve is to provide an electronic device having a high degree of freedom and a method for manufacturing the same.

[0007] The technical problems to be solved by the present invention are not limited to those described above.

[0008] To solve the technical problems described above, the present invention provides an electronic device.

[0009] According to one embodiment, the electronic device may include a substrate, a first electrode and a second electrode disposed on the substrate to be spaced apart from each other, a semiconductor layer disposed on the substrate, the semiconductor layer being disposed between the first electrode and the second electrode such that one side is in contact with the first electrode and the other side is in contact with the second electrode, the semiconductor layer including a material having an asymmetric crystal structure, and a third electrode disposed on the semiconductor layer, wherein the first electrode is in contact only with the one side of the semiconductor layer and the second electrode is in contact only with the other side of the semiconductor layer.

[0010] According to one embodiment, the semiconductor layer may include resistance values ​​measured for the first electrode and the second electrode in a direction in which atoms of the material having the asymmetric crystal structure are arranged in a first direction, and resistance values ​​measured for the first electrode and the second electrode in a direction in which atoms of the material having the asymmetric crystal structure are arranged in a second direction intersecting the first direction are different from each other.

[0011] According to one embodiment, the device may further include a first dielectric layer disposed between the substrate and the semiconductor layer, and a second dielectric layer disposed between the semiconductor layer and the third electrode, wherein the first dielectric layer prevents the first electrode and the second electrode from contacting the lower surface of the semiconductor layer, and the second dielectric layer prevents the first electrode and the second electrode from contacting the upper surface of the semiconductor layer.

[0012] In one embodiment, the first dielectric layer comprises hexagonal boron nitride (hBN) and hafnium oxide (HfO). x , x>0), and the second dielectric layer comprises hexagonal boron nitride (hBN) and hafnium oxide (HfO).x , x>0) can contain any one of them.

[0013] According to one embodiment, the material having the asymmetric crystal structure may include any one of rhenium disulfide (ReS2), rhenium diselenide (ReSe2), black phosphorus, perylenediimide dimer (FPDI), indium-gallium-arsenide (InGaAs), gallium oxide (Ga2O3), and tin oxide (SnO).

[0014] According to one embodiment, the first electrode may include any one of titanium (Ti), gold (Au), aluminum (Al), niobium disulfide (NbS2), antimony (Sb), bismuth (Bi), and graphene, and the second electrode may include any one of titanium (Ti), gold (Au), aluminum (Al), niobium disulfide (NbS2), antimony (Sb), bismuth (Bi), and graphene.

[0015] According to one embodiment, the method may further include an oxide layer disposed between the substrate and the semiconductor layer.

[0016] According to another embodiment, an electronic device including a first transistor and a second transistor sharing a semiconductor layer including a material having an asymmetric crystal structure, wherein the first transistor may include a first source electrode and a first drain electrode arranged on a substrate to be spaced apart from each other in a first direction, a semiconductor layer arranged on the substrate and between the first source electrode and the first drain electrode such that one side is in contact with the first source electrode and the other side is in contact with the first drain electrode, and a first gate electrode arranged on the semiconductor layer, and the second transistor may include a second source electrode and a second drain electrode arranged on the substrate to be spaced apart from each other in a second direction intersecting the first direction, a semiconductor layer arranged on the substrate and between the second source electrode and the second drain electrode such that one side is in contact with the second source electrode and the other side is in contact with the second drain electrode, and a second gate electrode arranged on the semiconductor layer.

[0017] According to another embodiment, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may all be in contact only with a side surface of the semiconductor layer.

[0018] According to another embodiment, the semiconductor layer may include a first contact resistance value with respect to the first source electrode and the first drain electrode and a second contact resistance value with respect to the second source electrode and the second drain electrode that are different from each other.

[0019]

[0020] To solve the technical problems described above, the present invention provides a method for manufacturing an electronic device.

[0021] According to one embodiment, the method for manufacturing the electronic device may include the steps of forming a laminated structure in which a first dielectric layer, a semiconductor layer, and a second dielectric layer are sequentially laminated on a substrate structure, placing a mask having an opening formed therein on the laminated structure, etching the laminated structure through the mask to form a through hole that penetrates the first dielectric layer, the semiconductor layer, and the second dielectric layer in an area of ​​the laminated structure corresponding to the opening of the mask and exposes an upper surface of the substrate structure, and forming an electrode on the substrate structure to fill the through hole.

[0022] According to one embodiment, the electrode may be formed to contact only a side surface of the semiconductor layer.

[0023] According to one embodiment, the step of forming the laminated structure on the substrate structure may include the step of forming the second dielectric layer on the first substrate structure, the step of transferring the second dielectric layer from the first substrate structure to a second substrate structure, the step of forming the semiconductor layer on the first substrate structure, the step of transferring the semiconductor layer from the first substrate structure onto the second dielectric layer of the second substrate structure, the step of forming the first dielectric layer on the first substrate structure, and the step of transferring the second dielectric layer and the semiconductor layer from the second substrate structure onto the first dielectric layer of the first substrate structure.

[0024] According to one embodiment, the through hole may be formed by one of dry etching and wet etching.

[0025] An electronic device according to an embodiment of the present invention may include a substrate, a first electrode and a second electrode disposed on the substrate to be spaced apart from each other, a semiconductor layer disposed on the substrate, the semiconductor layer being disposed between the first electrode and the second electrode such that one side is in contact with the first electrode and the other side is in contact with the second electrode, and including a material having an asymmetrical crystal structure, and a third electrode disposed on the semiconductor layer, wherein the first electrode is in contact only with the one side of the semiconductor layer and the second electrode is in contact only with the other side of the semiconductor layer.

[0026] Accordingly, the electronic device according to the above embodiment can have high anisotropy and a high degree of freedom even though the semiconductor layer is formed of a single material. Therefore, the electronic device according to the above embodiment can be easily applied to various fields such as inverters, logic circuits such as NAND, ternary semiconductors, memories, field-effect transistors, and infrared sensors.

[0027] Figure 1 is a cross-sectional schematic diagram of an electronic device according to a first embodiment of the present invention.

[0028] Figure 2 is a plan schematic diagram of an electronic device according to a first embodiment of the present invention.

[0029] Figure 3 is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention.

[0030] Figure 4 is a planar schematic diagram of an electronic device according to a second embodiment of the present invention.

[0031] FIG. 5 is a flowchart illustrating a method for manufacturing an electronic device according to an embodiment of the present invention.

[0032] FIG. 6 is a flowchart specifically explaining step S100 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0033] FIG. 7 is a drawing for explaining step S110 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0034] FIG. 8 is a drawing for explaining step S120 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0035] FIG. 9 is a drawing for explaining step S130 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0036] FIG. 10 is a drawing for explaining step S140 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0037] FIG. 11 is a drawing for explaining step S150 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0038] FIG. 12 is a drawing for explaining step S160 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0039] FIG. 13 is a drawing for explaining step S200 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0040] FIG. 14 is a drawing for explaining step S300 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0041] FIG. 15 is a drawing for explaining step S400 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0042] Figure 16 is a schematic diagram and a drawing for explaining an HRTEM image of a field effect transistor having an edge contact structure.

[0043] Figures 17 to 19 are drawings for explaining the arrangement direction of atoms in the ReS2 crystal structure.

[0044] Figure 20 is a drawing for explaining the electrical characteristics according to the arrangement direction of atoms in the ReS2 crystal structure.

[0045] Figure 21 is a drawing for explaining the results of measuring IV characteristics by increasing the temperature in the b direction and the cross b direction, respectively.

[0046] Figure 22 is a drawing for explaining the results of measuring the contact resistance in each direction obtained through 4 Point Probe measurement according to the gate voltage and temperature.

[0047] Figure 23 is a diagram for explaining the change in the anisotropy ratio of contact resistance between the b direction and the cross b direction depending on the gate voltage and temperature.

[0048] Figure 24 is a diagram for comparing the contact anisotropy of the top contact and edge contact of ReS2.

[0049] Figure 25 is a schematic diagram and an optical image of an inverter having an edge contact structure.

[0050] Figure 26 is a diagram showing the results of electrical characteristic measurements of an inverter having an edge contact structure.

[0051] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to sufficiently convey the spirit of the present invention to those skilled in the art.

[0052] In this specification, when a component is referred to as being on another component, it means that it can be formed directly on the other component, or a third component may be interposed between them. In addition, in the drawings, the thicknesses of films and regions are exaggerated for the purpose of effectively explaining the technical contents.

[0053] Also, although terms such as first, second, and third have been used to describe various components in various embodiments of this specification, these components should not be limited by these terms. These terms are only used to distinguish one component from another. Thus, what is referred to as a first component in one embodiment may be referred to as a second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiments. Also, the term "and / or" has been used herein to mean including at least one of the components listed before and after.

[0054] In the specification, singular expressions include plural expressions unless the context clearly dictates otherwise. In addition, terms such as "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be construed as excluding the presence or addition of one or more other features, numbers, steps, components, or combinations thereof. In addition, the term "connection" is used in the present specification to mean both indirectly connecting multiple components and directly connecting them.

[0055] In addition, when describing the present invention below, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0056]

[0057] Electronic device according to the first embodiment

[0058] FIG. 1 is a cross-sectional schematic diagram of an electronic device according to a first embodiment of the present invention, and FIG. 2 is a plan schematic diagram of an electronic device according to a first embodiment of the present invention.

[0059] Referring to FIGS. 1 and 2, an electronic device according to a first embodiment of the present invention may include a substrate (100), an oxide layer (200), a first dielectric layer (310), a second dielectric layer (320), a semiconductor layer (400), a first electrode (E1), a second electrode (E2), and a third electrode (E3). Each component is described below.

[0060] The substrate (100) can support the oxide layer (200), the first dielectric layer (310), the second dielectric layer (320), the semiconductor layer (400), the first electrode (E1), the second electrode (E2), and the third electrode (E3). That is, the oxide layer (200), the first dielectric layer (310), the second dielectric layer (320), the semiconductor layer (400), the first electrode (E1), the second electrode (E2), and the third electrode (E3) can be disposed on the substrate (100).

[0061] According to one embodiment, the substrate (100) may be a silicon semiconductor substrate. Alternatively, according to another embodiment, the substrate (100) may be any one of a compound semiconductor substrate, a glass substrate, or a plastic substrate. The type of the substrate (100) is not limited.

[0062] The above oxide layer (200) may be disposed on the substrate (100). According to one embodiment, the oxide layer (200) may include silicon oxide (SiO2). According to one embodiment, when the electronic device according to the first embodiment is applied as an infrared sensor, the oxide layer (200) may be used for light reflection to improve light absorption.

[0063] The first electrode (E1) and the second electrode (E2) may be disposed on the oxide layer (200) and may be disposed to be spaced apart from each other. According to one embodiment, the first electrode (E1) may include any one of titanium (Ti), gold (Au), aluminum (Al), niobium disulfide (NbS2), antimony (Sb), bismuth (Bi), and graphene. According to one embodiment, the second electrode (E2) may include any one of titanium (Ti), gold (Au), aluminum (Al), niobium disulfide (NbS2), antimony (Sb), bismuth (Bi), and graphene.

[0064] The first dielectric layer (310) may be disposed on the oxide layer (200), and may be disposed between the first electrode (E1) and the second electrode (E2). More specifically, the first dielectric layer (310) may be disposed on the oxide layer (200) such that one side is in contact with the first electrode (E1) and the other side is in contact with the second electrode (E2). According to one embodiment, the first dielectric layer (310) may include hexagonal boron nitride (hBN). Alternatively, according to another embodiment, the first dielectric layer (310) may include hafnium oxide (HfO). x , x>0) can be included.

[0065] The semiconductor layer (400) may be disposed on the first dielectric layer (310), and may be disposed between the first electrode (E1) and the second electrode (E2). More specifically, the semiconductor layer (400) may be disposed on the first dielectric layer (310) such that one side is in contact with the first electrode (E1) and the other side is in contact with the second electrode (E2). According to one embodiment, the semiconductor layer (400) may include a material having an asymmetric crystal structure. For example, the material having the asymmetric crystal structure may include a material having high anisotropy, such as a two-dimensional material, an asymmetric compound semiconductor material, and an asymmetric metal oxide. More specifically, the two-dimensional material that may be used as the semiconductor layer (400) may include any one of rhenium disulfide (ReS2), rhenium diselenide (ReSe2), and black phosphorus. In addition, the asymmetric compound semiconductor material that can be used as the semiconductor layer (400) may include any one of perylenediimide dimer (FPDI) and indium-gallium-arsenide (InGaAs). In addition, the metal oxide that can be used as the semiconductor layer (400) may include any one of gallium oxide (Ga2O3) and tin oxide (SnO).

[0066] The second dielectric layer (320) may be disposed on the semiconductor layer (400), and may be disposed between the first electrode (E1) and the second electrode (E2). More specifically, the second dielectric layer (320) may be disposed on the semiconductor layer (400) such that one side is in contact with the first electrode (E1) and the other side is in contact with the second electrode (E2). According to one embodiment, the second dielectric layer (320) may include hexagonal boron nitride (hBN). Alternatively, according to another embodiment, the second dielectric layer (320) may include hafnium oxide (HfO).x , x>0) can be included.

[0067] The third electrode (E3) may be disposed on the second dielectric layer (320). According to one embodiment, the third electrode (E3) may include any one of titanium (Ti), gold (Au), aluminum (Al), niobium disulfide (NbS2), antimony (Sb), bismuth (Bi), and graphene.

[0068] As a result, the electronic device according to the first embodiment may have a structure in which the first dielectric layer (310), the semiconductor layer (400), and the second dielectric layer (320) are disposed between the first electrode (E1) and the second electrode (E2), and the semiconductor layer (400) is disposed between the first dielectric layer (310) and the second dielectric layer (320). Accordingly, the first electrode (E1) and the second electrode (E2) may be prevented from contacting the lower surface of the semiconductor layer (400) by the first dielectric layer (310), and the first electrode (E1) and the second electrode (E2) may be prevented from contacting the upper surface of the semiconductor layer (400) by the second dielectric layer (320). That is, the first electrode (E1) may be in contact only with one side of the semiconductor layer (400), and the second electrode (E2) may be in contact only with the other side of the semiconductor layer (400). In other words, the semiconductor layer (400) may be in edge contact with the first electrode (E1) and the second electrode (E2).

[0069] As described above, when the semiconductor layer (400) is in contact (edge ​​contact) with the first electrode (E1) and the second electrode (E2) only through the side surface, the semiconductor layer (400) can have high anisotropy and a high degree of freedom even though it is made of a single material.

[0070] Specifically, the semiconductor layer (400) may have a contact resistance value measured for the first electrode (E1) and the second electrode (E2) in a direction in which atoms of the material having the asymmetric crystal structure are arranged in a first direction, and a contact resistance value measured for the first electrode (E1) and the second electrode (E2) in a direction in which atoms of the material having the asymmetric crystal structure are arranged in a second direction intersecting the first direction.

[0071] According to one embodiment, when the semiconductor layer (400) includes rhenium disulfide (ReS2), the contact resistance values ​​measured for the first electrode (E1) and the second electrode (E2) in the direction in which atoms of rhenium disulfide (ReS2), i.e., rhenium (Re) and sulfur (S), are arranged in the first direction, and the contact resistance values ​​measured for the first electrode (E1) and the second electrode (E2) in the direction in which they are arranged in the second direction may be different from each other.

[0072] For example, the first direction may be a rhenium chain (Re-chain) direction. More specifically, the first direction may be a rotation angle function for rhenium disulfide (ReS2) as A g 7 The normalized Raman intensity of the first direction can be defined as the maximum at 90° in the polar coordinates. Alternatively, the second direction can be a direction intersecting the first direction (e.g., a orthogonal direction). More specifically, the second direction is defined as a rotation angle function for rhenium disulfide (ReS2) as A g 7 It can be defined as the minimum value of the normalized Raman intensity at polar coordinates 0°.

[0073] In this case, the contact resistance value of the semiconductor layer (400) measured with respect to the first electrode (E1) and the second electrode (E2) when the atoms of rhenium disulfide (ReS2) included in the semiconductor layer (400) are arranged in the first direction between the first electrode (E1) and the second electrode (E2) may be different from the contact resistance value of the semiconductor layer (400) measured with respect to the first electrode (E1) and the second electrode (E2) when the atoms of rhenium disulfide (ReS2) included in the semiconductor layer (400) are arranged in the second direction between the first electrode (E1) and the second electrode (E2). Accordingly, the electronic device according to the first embodiment may have high anisotropy and a high degree of freedom even though the semiconductor layer (400) is formed of a single material. Accordingly, the electronic device according to the first embodiment can be easily applied to various fields such as inverters, logic circuits such as NAND, ternary semiconductors, memories, field effect transistors, and infrared sensors.

[0074]

[0075] Electronic device according to the second embodiment

[0076] FIG. 3 is a cross-sectional schematic diagram of an electronic device according to a second embodiment of the present invention, and FIG. 4 is a plan schematic diagram of an electronic device according to a second embodiment of the present invention.

[0077] Referring to FIGS. 3 and 4, an electronic device according to a second embodiment of the present invention may include a first transistor (TR1) and a second transistor (TR2). Hereinafter, the first transistor (TR1) and the second transistor (TR2) will be described in detail.

[0078] The first transistor (TR1) comprises a substrate (100), an oxide layer (200) disposed on the substrate (100), a first source electrode (S1) and a first drain electrode (D1) disposed on the oxide layer (200) so as to be spaced apart from each other in a first direction (X-axis direction), a first dielectric layer (310) disposed on the oxide layer (200) so as to have one side in contact with the first source electrode (S1) and the other side in contact with the first drain electrode (D1), a semiconductor layer (400) disposed on the first dielectric layer (310) so as to have one side in contact with the first source electrode (S1) and the other side in contact with the first drain electrode (D1), and a second transistor (TR1) disposed on the semiconductor layer (400) so as to have one side in contact with the first source electrode (S1) and the other side in contact with the first drain electrode (D1). It may include a dielectric layer (320) and a first gate electrode (G1) disposed on the second dielectric layer (320).

[0079] The second transistor (TR2) comprises a substrate (100), an oxide layer (200) disposed on the substrate (100), a second source electrode (S2) and a second drain electrode (D2) disposed on the oxide layer (200) to be spaced apart from each other in a second direction (Y-axis direction), a first dielectric layer (310) disposed on the oxide layer (200) such that one side is in contact with the second source electrode (S2) and the other side is in contact with the second drain electrode (D2), a semiconductor layer (400) disposed on the first dielectric layer (310) such that one side is in contact with the second source electrode (S2) and the other side is in contact with the second drain electrode (D2), and a second transistor (TR2) disposed on the semiconductor layer (400) such that one side is in contact with the second source electrode (S2) and the other side is in contact with the second drain electrode (D2). It may include a dielectric layer (320) and a second gate electrode (G2) disposed on the second dielectric layer (320).

[0080] In addition, the first transistor (TR1) and the second transistor (TR2) may have a structure that shares the substrate (100), the oxide layer (200), the first dielectric layer (310), the semiconductor layer (400), and the second dielectric layer (320).

[0081] According to one embodiment, the first direction described in the first transistor (TR1) may be the same as the first direction described in the electronic device according to the first embodiment with reference to FIGS. 1 and 2, and the second direction described in the second transistor (TR2) may be the same as the second direction described in the electronic device according to the first embodiment with reference to FIGS. 1 and 2.

[0082] According to one embodiment, the substrate (100), the oxide layer (200), the first dielectric layer (310), the semiconductor layer (400), and the second dielectric layer (320) included in the first transistor (TR1) and the second transistor (TR2) may be the same as the substrate (100), the oxide layer (200), the first dielectric layer (310), the semiconductor layer (400), and the second dielectric layer (320) of the electronic device according to the first embodiment described with reference to FIGS. 1 and 2, respectively. In addition, the first source electrode (S1) and the second source electrode (S2) included in the first transistor (TR1) and the second transistor (TR2) may be the same as the first electrode (E1), the first drain electrode (D1) and the second drain electrode (D2) may be the same as the second electrode (E2), and the first gate electrode (G1) and the second gate electrode (G2) may be the same as the third electrode (E3).

[0083] That is, the semiconductor layer (400) of the first transistor (TR1) can also contact (edge ​​contact) the first source electrode (S1) and the first drain electrode (D1) only through the side, and the semiconductor layer (400) of the second transistor (TR2) can also contact (edge ​​contact) the second source electrode (S2) and the second drain electrode (D2) only through the side.

[0084] Accordingly, the first contact resistance value that the semiconductor layer (400) has with respect to the first source electrode (S1) and the first drain electrode (D1) and the second contact resistance value that the semiconductor layer (400) has with respect to the second source electrode (S2) and the second drain electrode (D2) may be different from each other. Accordingly, the electronic device according to the second embodiment may also have high anisotropy and a high degree of freedom despite being formed of a single material.

[0085]

[0086] Above, electronic devices according to embodiments of the present invention have been described. Hereinafter, a method for manufacturing an electronic device in which a semiconductor layer contacts the first electrode and the second electrode only through the side surface (edge ​​contact) is described.

[0087] Method for manufacturing an electronic device according to an embodiment

[0088] FIG. 5 is a flowchart for explaining a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 6 is a flowchart for specifically explaining step S100 of a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 7 is a drawing for explaining step S110 of a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 8 is a drawing for explaining step S120 of a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 9 is a drawing for explaining step S130 of a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 10 is a drawing for explaining step S140 of a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 11 is a drawing for explaining step S150 of a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 12 is a drawing for explaining step S160 of a method for manufacturing an electronic device according to an embodiment of the present invention, FIG. 13 is a drawing for explaining step S200 of a method for manufacturing an electronic device according to an embodiment of the present invention, and FIG. 14 is a drawing for explaining step S140 of a method for manufacturing an electronic device according to an embodiment of the present invention. This is a drawing for explaining step S300 of a method for manufacturing an electronic device according to an example, and FIG. 15 is a drawing for explaining step S400 of a method for manufacturing an electronic device according to an embodiment of the present invention.

[0089] Referring to FIG. 5, a method for manufacturing an electronic device according to an embodiment of the present invention may include a step of forming a laminated structure on a substrate structure (S100), a step of placing a mask on the laminated structure (S200), a step of etching the laminated structure through the mask to form a through hole in the laminated structure (S300), and a step of forming an electrode to fill the through hole (S400). Each step is described in detail below.

[0090] Referring to FIGS. 6 and 7, a second dielectric layer (320) may be formed on a first substrate structure (S1) (S110). According to one embodiment, the first substrate structure (S1) may include a first substrate (100) and an oxide layer (200) disposed on the first substrate (100), and the second dielectric layer (320) may be formed on the oxide layer (200). According to one embodiment, the first substrate (100), the oxide layer (200), and the second dielectric layer (320) may be the same as the substrate (100), the oxide layer (200), and the second dielectric layer (320) of the electronic device according to the first embodiment described with reference to FIGS. 1 and 2.

[0091] Referring to FIGS. 6 and 8, the second dielectric layer (320) can be transferred from the first substrate structure (S1) to the second substrate structure (S2) (S120). According to one embodiment, the second substrate structure (S2) can include a second substrate (10) and a transfer layer (20) disposed on the second substrate (10), and the second dielectric layer (320) can be transferred from the first substrate structure (S1) to the transfer layer (20) of the second substrate structure (S2). For example, the second substrate (10) can include polydimethylsiloxane (PDMS), and the transfer layer (20) can include polycarbonate (PC).

[0092] Referring to FIGS. 6 and 9, a semiconductor layer (400) may be formed on the first substrate structure (S1) (S130). According to one embodiment, the semiconductor layer (400) may be formed on the oxide layer (200) of the first substrate structure (S1). In addition, according to one embodiment, the semiconductor layer (400) may be the same as the semiconductor layer (400) of the electronic device according to the first embodiment described with reference to FIGS. 1 and 2.

[0093] Referring to FIG. 6 and FIG. 10, the semiconductor layer (400) can be transferred from the first substrate structure (S1) onto the second dielectric layer (320) of the second substrate structure (S2) (S140).

[0094] Referring to FIGS. 6 and 11, a first dielectric layer (310) may be formed on a first substrate structure (S1) (S150). According to one embodiment, the first dielectric layer (310) may be formed on the oxide layer (200) of the first substrate structure (S1). In addition, according to one embodiment, the first dielectric layer (310) may be the same as the first dielectric layer (310) of the electronic device according to the first embodiment described with reference to FIGS. 1 and 2.

[0095] Referring to FIG. 6 and FIG. 12, the second dielectric layer (320) and the semiconductor layer (400) can be transferred from the second substrate structure (S2) onto the first dielectric layer (310) of the first substrate structure (S1) (S160). Accordingly, a laminated structure (ST) in which the first dielectric layer (310), the semiconductor layer (400), and the second dielectric layer (320) are sequentially laminated on the first substrate structure (S1) can be formed.

[0096] Referring to FIGS. 5 and 13, a mask (M) may be placed on the laminated structure (ST) (S200). According to one embodiment, a plurality of openings (OA) may be formed in the mask (M), and an upper surface of the laminated structure (ST), i.e., an upper surface of the second dielectric layer (320), may be exposed to the outside through the plurality of openings (OA) formed in the mask (M). For example, the mask (M) may include PMMA (Poly(methyl methacrylate)).

[0097] Referring to FIG. 5 and FIG. 14, the layered structure (ST) is etched through the mask (M) to form a through hole (TH) penetrating the first dielectric layer (310), the semiconductor layer (400), and the second dielectric layer (320) in a region of the layered structure (ST) corresponding to the opening (OA) of the mask (M) and exposing the upper surface of the substrate structure (ST) (S300). According to one embodiment, the through hole (TH) may be formed by any one of dry etching and wet etching. For example, the through hole (TH) may be formed by an inductively coupled plasma etching system using SF6 / O2 plasma.

[0098] Referring to FIGS. 5 and 15, after removing the mask (M), electrodes (E1, E2) can be formed on the first substrate structure (S1) to fill the through hole (TH) (S400). Accordingly, the electrodes (E1, E2) can only contact (edge ​​contact) the side surfaces of the semiconductor layer (400).

[0099]

[0100] Above, a method for manufacturing an electronic device according to an embodiment of the present invention has been described. Below, specific experimental examples of electronic devices according to an embodiment of the present invention are described.

[0101] Experimental Example 1: Checking Edge Contact

[0102] Figure 16 is a schematic diagram and a drawing for explaining an HRTEM image of a field effect transistor having an edge contact structure.

[0103] Referring to Fig. 16, a schematic diagram of a field effect transistor having the structure described with reference to Figs. 1 and 2 is shown. Specifically, p-Si was used as a substrate, SiO2 was used as an oxide layer, hBN was used as the first and second dielectric layers, ReS2 was used as a semiconductor layer, and Ti / Au was used as the first and second electrodes. In addition, Fig. 16 (a) shows a state in which ReS2 is arranged in a first direction, Fig. 16 (b) shows a state in which ReS2 is arranged in a second direction, and Fig. 16 (c) shows a high-resolution transmission electron microscopy (HRTEM) image of a cross-section of the field effect transistor. In the following description of experimental examples, the first direction is defined as the b-direction, and the second direction is defined as the cross-b direction.

[0104] As can be seen in (a) to (c) of Fig. 16, as the hBN dielectric layer is placed on the upper and lower sides of the ReS2 semiconductor layer, it can be confirmed that the Ti / Au electrode is in contact (edge ​​contact) only with the side surface of the ReS2 semiconductor layer.

[0105] Figures 17 to 19 are drawings for explaining the arrangement direction of atoms in the ReS2 crystal structure, and Figure 20 is a drawing for explaining electrical characteristics according to the arrangement direction of atoms in the ReS2 crystal structure.

[0106] Referring to Fig. 17, the b direction (b) and the cross-b direction (cross-b) in the ReS2 crystal structure having a rhenium chain (Re-chain) are shown, and referring to Fig. 18, A as a rotation angle function for ReS2 g 7 It represents the polar coordinates of the normalized Raman intensity.

[0107] As can be seen in Figures 17 and 18, the b direction represents the rhenium chain (Re-chaing) direction, but as a function of the rotation angle, A g 7 It can be seen that the normalized Raman intensity can be defined as the maximum at 90° in polar coordinates. In contrast, the cross b direction represents a direction that intersects the rhenium chain direction (e.g., a orthogonal direction), but as a function of the rotation angle A g 7 It can be seen that the normalized Raman intensity can be defined as the minimum value at polar coordinates 0°.

[0108] Referring to Fig. 19, edge contact with metal is shown according to the arrangement direction of atoms in the ReS2 crystal structure. As can be seen in Fig. 19, in the case of edge contact, when the b direction of ReS2 is selected as a channel, the contact surface is aligned along the cross b direction, whereas when the cross b direction is selected as a channel, the contact surface is arranged along the b direction, which can be confirmed to make more clear contact with the rhenium chain. In addition, in the case of the b direction, direct contact with the rhenium chain perpendicular to the rhenium chain occurs during the contact process, whereas in the case of the cross b direction, contact is made parallel to the rhenium chain almost without interruption. Consequently, it can be seen that the etched cross-section of ReS2 in the cross b direction creates a cleaner surface compared to the a direction, enabling more precise contact.

[0109] Referring to Fig. 20, the optical image and electrical performance of the angle-resolved ReS2 edge-contact field-effect transistor are shown. Specifically, Fig. 20 (a) shows the anisotropic direction of the ReS2 crystal defined by the charge transport according to the angle, Fig. 20 (b) shows the electrical transfer curve of ReS2 according to various angles, and Fig. 20 (c) shows the electrical output curve of ReS2 according to various angles.

[0110] As can be seen in Fig. 20, the current value varies at various angles due to the charge transport anisotropy according to the crystal structure of ReS2, and it can be confirmed that the largest difference in current occurs between the b direction and the cross b direction.

[0111]

[0112] Experimental Example 2: Electrical Performance and Contact Anisotropy of Edge Contacts

[0113] As described in Fig. 16, a field effect transistor having an edge contact structure with ReS2 and an electrode was prepared, and the electrical performance and contact anisotropy were confirmed.

[0114] Figure 21 is a drawing for explaining the results of measuring IV characteristics by increasing the temperature in the b direction and the cross b direction, respectively.

[0115] Referring to (a) and (b) of Fig. 21, the temperature range of 76 to 300 K and the drain voltage V D = Temperature-dependent 2PP transfer curves obtained in the b direction and the cross-b direction at 1 V, respectively, are shown. As the temperature increases, the drain current also increases in both the b direction and the cross-b direction. Accordingly, it can be seen that ReS2 and the electrode behave like a typical semiconductor even though they have an edge-contact structure.

[0116] Figure 22 is a drawing for explaining the results of measuring the contact resistance in each direction obtained through 4 Point Probe measurement according to the gate voltage and temperature.

[0117] Referring to Fig. 22(a), the contact resistances obtained in the b direction and the cross-b direction are shown at a temperature of 300 K and a gate voltage range of -60 V to 60 V. As can be seen in Fig. 22(a), the contact resistance in the cross-b direction consistently shows a higher value than the contact resistance in the b direction over the entire range of gate voltages. In addition, it can be seen that the contact resistance in both the b direction and the cross-b direction noticeably decreases as the gate voltage increases.

[0118] Referring to (b) of Fig. 22, a fixed gate voltage (V G = 60 V) as a function of temperature (76 K to 300 K) in the b-direction and cross-b-direction. As can be seen in Fig. 22(b), the contact resistance in the cross-b-direction shows a higher value than that in the b-direction over the entire temperature range, and it can be seen that the resistance in both the b-direction and cross-b-direction decreases as the temperature increases. Accordingly, it can be seen that the Schottky barrier at the interface between ReS2 and the metal can be overcome more efficiently.

[0119] Figure 23 is a diagram for explaining the change in the anisotropy ratio of contact resistance between the b direction and the cross b direction depending on the gate voltage and temperature.

[0120] Referring to (a) and (b) of Fig. 23, the ratio of contact resistance along the cross b direction and the ratio of contact resistance along the b direction are respectively expressed as a function of gate voltage and temperature. As can be seen from (a) and (b) of Fig. 23, the ratio of contact resistance decreases as both the gate voltage and temperature increase, and it can be seen that this ratio increases more at low temperatures and gate voltages.

[0121] Figure 24 is a diagram for comparing the contact anisotropy of the top contact and edge contact of ReS2.

[0122] Referring to (a) of Fig. 24, a comparison of contact resistance anisotropy between top contact and edge contact ReS2 field effect transistors is shown, and referring to (b) of Fig. 24, a comparison of contact resistance ratios in the cross b direction and b direction in various edge contact devices and top contact devices is shown. The edge contact described in (a) and (b) of Fig. 24 means a state in which an electrode is in contact only with a side surface of a ReS2 semiconductor layer, and the top contact means a state in which an electrode is in contact with an upper surface of a ReS2 semiconductor layer.

[0123] As can be seen in (a) and (b) of Fig. 24, in the top contact device, the channel resistance has a greater influence than the contact resistance, whereas in the edge contact device, the contact resistance has a greater influence than the channel resistance, so it can be seen that most edge contact devices exhibit higher contact anisotropy than the top contact device. Accordingly, it can be seen that the contact anisotropy in the edge contact is more prominent than the contact anisotropy in the top contact device.

[0124]

[0125] Experimental Example 3: Verification of Inverter Characteristics with Edge Contact Structure

[0126] An inverter having the structure described with reference to FIGS. 3 and 4 was prepared. Specifically, p-Si was used as the plate, SiO2 was used as the oxide layer, hBN was used as the first and second dielectric layers, ReS2 was used as the semiconductor layer, Ti was used as the first source electrode and the first drain electrode, and Cr was used as the second source electrode and the second drain electrode.

[0127] Fig. 25 is a schematic diagram and an optical image of an inverter having an edge contact structure, and Fig. 26 is a diagram showing the results of electrical characteristic measurements of an inverter having an edge contact structure. As can be seen in Figs. 25 and 26, the inverter having an edge contact structure also exhibits different electrical characteristics depending on the b direction and the cross-b direction.

[0128]

[0129] While the present invention has been described in detail using preferred embodiments, the scope of the present invention is not limited to the specific embodiments described above, and should be construed in accordance with the appended claims. Furthermore, those skilled in the art will appreciate that numerous modifications and variations are possible without departing from the scope of the present invention.

[0130] Electronic devices according to embodiments of the present application can be utilized in various fields, such as inverters, logic circuits such as NAND, ternary semiconductors, memories, field effect transistors, and infrared sensors.

Claims

1. Substrate; First electrodes and second electrodes arranged spaced apart from each other on the substrate; A semiconductor layer disposed on the substrate, between the first electrode and the second electrode such that one side is in contact with the first electrode and the other side is in contact with the second electrode, and including a material having an asymmetric crystal structure; and Including a third electrode disposed on the above semiconductor layer, An electronic device including the first electrode contacting only one side of the semiconductor layer and the second electrode contacting only the other side of the semiconductor layer.

2. In paragraph 1, The semiconductor layer has a contact resistance value measured for the first electrode and the second electrode in the direction in which the atoms of the material having the asymmetric crystal structure are arranged in the first direction, An electronic device including contact resistance values ​​measured for the first electrode and the second electrode are different from each other in a direction in which atoms of a material having the asymmetric crystal structure are arranged in a second direction intersecting the first direction.

3. In paragraph 1, Further comprising a first dielectric layer disposed between the substrate and the semiconductor layer, and a second dielectric layer disposed between the semiconductor layer and the third electrode, The first electrode and the second electrode are prevented from contacting the lower surface of the semiconductor layer by the first dielectric layer, An electronic device comprising: the first electrode and the second electrode being prevented from contacting the upper surface of the semiconductor layer by the second dielectric layer.

4. In paragraph 3, The first dielectric layer is made of hexagonal boron nitride (hBN) and hafnium oxide (HfO). x , x>0), and The second dielectric layer is made of hexagonal boron nitride (hBN) and hafnium oxide (HfO). x An electronic device comprising one of the following: , x>0.

5. In paragraph 1, An electronic device comprising a material having the above asymmetric crystal structure, wherein the material comprises one of rhenium disulfide (ReS2), rhenium diselenide (ReSe2), black phosphorus, perylenediimide dimer (FPDI), indium-gallium-arsenide (InGaAs), gallium oxide (Ga2O3), and tin oxide (SnO).

6. In paragraph 1, The first electrode comprises one of titanium (Ti), gold (Au), aluminum (Al), niobium disulfide (NbS2), antimony (Sb), bismuth (Bi), and graphene, The second electrode is an electronic device including any one of titanium (Ti), gold (Au), aluminum (Al), niobium disulfide (NbS2), antimony (Sb), bismuth (Bi), and graphene.

7. In paragraph 1, An electronic device further comprising an oxide layer disposed between the substrate and the semiconductor layer.

8. A step of forming a laminated structure in which a first dielectric layer, a semiconductor layer, and a second dielectric layer are sequentially laminated on a substrate structure; A step of placing a mask having an opening formed on the above laminated structure; A step of etching the laminated structure through the mask to form a through hole penetrating the first dielectric layer, the semiconductor layer, and the second dielectric layer in an area of ​​the laminated structure corresponding to the opening of the mask and exposing the upper surface of the substrate structure; and A method for manufacturing an electronic device, comprising the step of forming an electrode on the substrate structure to fill the through hole.

9. In paragraph 8, A method for manufacturing an electronic device, wherein the electrode is formed so as to contact only a side surface of the semiconductor layer.

10. In paragraph 8, The step of forming the laminated structure on the above substrate structure is: A step of forming the second dielectric layer on the first substrate structure; A step of transferring the second dielectric layer from the first substrate structure to the second substrate structure; A step of forming the semiconductor layer on the first substrate structure; A step of transferring the semiconductor layer from the first substrate structure onto the second dielectric layer of the second substrate structure; A step of forming the first dielectric layer on the first substrate structure; and A method for manufacturing an electronic device, comprising the step of transferring the second dielectric layer and the semiconductor layer from the second substrate structure onto the first dielectric layer of the first substrate structure.

11. In paragraph 8, A method for manufacturing an electronic device, wherein the through hole is formed by one of dry etching and wet etching.

12. In an electronic device including a first transistor and a second transistor sharing a semiconductor layer including a material having an asymmetric crystal structure, The above first transistor, A first source electrode and a first drain electrode arranged to be spaced apart from each other in a first direction on a substrate; The semiconductor layer is disposed on the substrate, and is disposed between the first source electrode and the first drain electrode so that one side is in contact with the first source electrode and the other side is in contact with the first drain electrode; and Including a first gate electrode disposed on the above semiconductor layer, The second transistor is, A second source electrode and a second drain electrode arranged on the substrate so as to be spaced apart from each other in a second direction intersecting the first direction; The semiconductor layer is disposed on the substrate, and is disposed between the second source electrode and the second drain electrode so that one side is in contact with the second source electrode and the other side is in contact with the second drain electrode; and An electronic device comprising a second gate electrode disposed on the semiconductor layer.

13. In paragraph 12, An electronic device, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are all in contact only with a side surface of the semiconductor layer.

14. In paragraph 12, An electronic device comprising a first contact resistance value that the semiconductor layer has with respect to the first source electrode and the first drain electrode and a second contact resistance value that the semiconductor layer has with respect to the second source electrode and the second drain electrode are different from each other.

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