Semiconductor device, method for producing same, and electronic device

Abstract

The purpose of the present invention is to improve the degree of freedom of interconnection routing. This semiconductor device comprises: a semiconductor layer which has a first surface part and a second surface part that are positioned on opposite sides in one direction; a field insulation part which is provided on the first surface part in the semiconductor layer; a first conductive part which overlaps the field insulation part in plan view and which is provided on the first surface part-side of the semiconductor layer; a second conductive part which overlaps the field insulation part in plan view and which is provided on the second surface part-side of the semiconductor layer; and a through contact electrode which penetrates through the semiconductor layer along the one direction and which is connected to the first conductive part and the second conductive part. The through contact electrode has a stepped shape including a first portion which extends from the second conductive part toward the field insulation part and a second portion which extends from the first portion toward the second conductive part and the outer shape of which is a smaller in size than that of the first portion in plan view.

Description

Semiconductor device, manufacturing method thereof, and electronic device

[0001] The present technology (technology related to the present disclosure) relates to a semiconductor device, a manufacturing method thereof, and an electronic device, and in particular to a semiconductor device having a contact electrode penetrating a semiconductor layer, a manufacturing method thereof, and a technology that is effective when applied to an electronic device having the same.

[0002] As a wiring technology for semiconductor devices, Patent Document 1 discloses a technology in which a multilayer wiring layer is provided on each of a first surface side and a second surface side of a semiconductor layer that are located on opposite sides of the semiconductor layer, and the multilayer wiring layer on the first surface side of the semiconductor layer and the multilayer wiring layer on the second surface side of the semiconductor layer are electrically connected by through contact electrodes. This technology can improve the freedom of routing of wiring.

[0003] JP 2015-65407 A

[0004] However, semiconductor devices are becoming increasingly highly integrated, and there is a demand for further improvement in the degree of freedom in routing wiring.

[0005] An object of the present technology is to provide a technology that can further improve the degree of freedom in routing wiring.

[0006] (1) A semiconductor device according to one aspect of the present technology includes: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction, a field insulator provided in the first surface portion of the semiconductor layer, a first conductive portion overlapping the field insulator in a plan view and provided on the first surface portion of the semiconductor layer, a second conductive portion overlapping the field insulator in a plan view and provided on the second surface portion of the semiconductor layer, and a via contact electrode that penetrates the semiconductor layer along the one direction and is connected to each of the first conductive portion and the second conductive portion. The via contact electrode has a stepped shape including a first portion extending from the second conductive portion toward the field insulator, and a second portion extending from the first portion toward the first conductive portion and having an outer size in a plan view that is one step smaller than the first portion.

[0007] (2) A method for manufacturing a semiconductor device according to another aspect of the present technology includes: forming a field insulating portion having an opening where the semiconductor layer is present, on the first surface of a semiconductor layer out of a first surface and a second surface located opposite each other; forming a first conductive portion outside the first surface of the semiconductor layer, the first conductive portion overlapping the opening via an insulating layer in a planar view; selectively removing the semiconductor layer from the second surface of the semiconductor layer to within the opening, to form a first carved portion connected to the opening and having an outer size larger than the opening in a planar view; selectively removing the insulating layer through the opening, to form a second carved portion reaching the first conductive portion; forming through-contact electrodes connected to the first conductive portion in the first carved portion and the second carved portion; and forming a second electrode portion outside the second surface of the semiconductor layer, the second electrode portion overlapping the through-contact electrode in a planar view and connected to the through-contact electrode.

[0008] (3) A method for manufacturing a semiconductor device according to another aspect of the present technology includes: forming a field insulating portion having an opening in which the semiconductor layer is present, on the first surface portion of a semiconductor layer, of which the semiconductor layer is located opposite each other; forming a first conductive portion outside the first surface portion of the semiconductor layer, the first conductive portion overlapping the opening in a planar view; selectively removing the semiconductor layer from the second surface portion side of the semiconductor layer to within the opening, to form a recessed portion connected to the opening and having an outer size larger than the opening in a planar view; forming a through contact electrode connected to the first conductive portion in the recessed portion and within the opening; and forming a second electrode portion outside the second surface portion of the semiconductor layer, the second conductive portion overlapping the through contact electrode in a planar view and connected to the through contact electrode.

[0009] (4) An electronic device according to another aspect of the present technology includes the semiconductor device described above; an optical lens that focuses image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device.

[0010] 4B. FIG. 4C. FIG. 4D. FIG. 4E. FIG. 4F. FIG. 4G. FIG. 4H. FIG. 4H. FIG. 4C. FIG. 4D. FIG. 4E. FIG. 4F. FIG. 4G. FIG. 4H. FIG. 4H. 7B. A vertical cross-sectional view schematically showing a process of a method for manufacturing a semiconductor device according to a second embodiment of the present technology. FIG. 7C. A vertical cross-sectional view schematically showing a process subsequent to FIG. 7D. FIG. 7E. A vertical cross-sectional view schematically showing a process subsequent to FIG. 7F. FIG. 7D. A vertical cross-sectional view schematically showing a process subsequent to FIG. 7F. FIG. 7C. A vertical cross-sectional view schematically showing a process subsequent to FIG. 7A. FIG. 7D. A vertical cross-sectional view schematically showing a process subsequent to FIG. 7E. FIG. 7F. FIG. 7D. A vertical cross-sectional view schematically showing a process subsequent to FIG. 7A. FIG. 9A. A vertical cross-sectional view schematically showing a process subsequent to FIG. 9B. FIG. 9C. 9D, 9E, and 9F are longitudinal sectional views schematically showing steps subsequent to those in Fig. 9D, 9E, and 9F, respectively.FIG. 10 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a semiconductor device according to a fourth embodiment of the present technology. FIG. 11 is a plan layout view schematically showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 12 is a block diagram schematically showing a configuration example of a solid-state imaging device according to the fifth embodiment of the present technology. FIG. 13 is an equivalent circuit diagram showing a configuration example of pixels and pixel circuits of a solid-state imaging device according to the fifth embodiment of the present technology. FIG. 14 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a pixel array section of a solid-state imaging device according to a sixth embodiment of the present technology. FIG. 15 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a pixel array section of a solid-state imaging device according to a seventh embodiment of the present technology. FIG. 16 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a pixel array section of a solid-state imaging device according to an eighth embodiment of the present technology. FIG. 17 is a diagram showing a schematic configuration of an electronic device according to a ninth embodiment of the present technology.

[0011] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. Note that in the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0012] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0013] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0014] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0015] In the following embodiments, among the three directions orthogonal to each other in space, a first direction and a second direction orthogonal to each other in the same plane are defined as the X direction and the Y direction, respectively, and a third direction orthogonal to each of the first direction and the second direction is defined as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 2 (described later) will be described as the Z direction. In the following embodiments, the Z direction will be described as "one direction" of the present technology.

[0016] In addition, in the following embodiments, the thickness of the semiconductor layer is the distance between the first surface portion S1 and the second surface portion S2 located on opposite sides in the Z direction, and the thickness direction of the semiconductor layer 2 is the direction representing the thickness of the semiconductor layer 2.

[0017] In the following embodiments, a plan view refers to a case where the semiconductor layer 2 is viewed from the Z direction (one direction). A cross-sectional view refers to a case where a cross section along the Z direction (one direction) is viewed from a direction (Z direction) perpendicular to the cross section.

[0018] [First embodiment] In this first embodiment, an example of applying the present technology to a semiconductor device having a through contact electrode that connects wiring of a multilayer wiring layer provided on a first surface side of a semiconductor layer with wiring of a multilayer wiring layer provided on a second surface side of the semiconductor layer will be described.

[0019] <<Overall Configuration of Semiconductor Device>> First, the overall configuration of the semiconductor device 1A will be described with reference to Figures 1 and 2. In Figures 1 and 2, hatching representing cross sections has been partially omitted to make the drawings easier to see.

[0020] As shown in Figures 1 and 2, a semiconductor device 1A according to a first embodiment of the present technology includes a semiconductor layer 2 having a first surface portion S1 and a second surface portion S2 located opposite each other in the Z direction, which is "one direction" of the present technology, an insulating layer 16 provided on the first surface portion S1 side of the semiconductor layer 2, and a first multilayer wiring layer 20 provided on the side of the insulating layer 16 opposite the semiconductor layer 2 side.

[0021] Moreover, the semiconductor device 1A according to the first embodiment of the present technology further includes an insulating film 24 provided on the second surface S2 side of the semiconductor layer 2, and a second multilayer wiring layer 40 provided on the opposite side of the insulating film 24 from the semiconductor layer 2. That is, the semiconductor device 1A according to the first embodiment has a stacked structure in which the first multilayer wiring layer 20 is stacked on the first surface S1 side of the semiconductor layer 2 with the insulating layer 16 interposed therebetween, and the second multilayer wiring layer 40 is stacked on the second surface S2 side of the semiconductor layer 2 with the insulating film 24 interposed therebetween.

[0022] In addition, the semiconductor device 1A according to the first embodiment of the present technology further includes an inter-element isolation region 3 and a field insulation portion 4 provided on the first surface portion S1 side in the semiconductor layer 2, and a through contact electrode 34 that penetrates the semiconductor layer 2 in one direction, that is, the thickness direction (Z direction) of the semiconductor layer 2, and is electrically and mechanically connected to each of the wiring 22 a (first conductive portion) of the first multilayer wiring layer 20 and the wiring 42 a (second conductive portion) of the second multilayer wiring layer 40.

[0023] In the first embodiment, the wiring 22 a of the first multilayer wiring layer 20 corresponds to a specific example of a “first conductive portion” in the present technology, and the wiring 42 a of the second multilayer wiring layer 40 corresponds to a specific example of a “second conductive portion” in the present technology. In addition, in the first embodiment, the first surface S1 of the semiconductor layer 2 may be referred to as a main surface or an element forming surface, and the second surface S2 may be referred to as a back surface.

[0024] 1 , the semiconductor layer 2 has a first surface S1 and a second surface S2 located on opposite sides in the thickness direction (Z direction). The first surface S1 of the semiconductor layer 2 is provided with an inter-element isolation region 3 that defines and separates element formation regions. The first surface S1 of the semiconductor layer 2 is further provided with a field insulator 4. The semiconductor layer 2 may be formed of a Si substrate, a SiGe substrate, an InGaAs substrate, or the like. In the first embodiment, the semiconductor layer 2 is formed of, for example, a p-type semiconductor substrate made of single crystal silicon, although the present invention is not limited thereto.

[0025] <Element Isolation Region> As shown in FIG. 1 , the element isolation region 3 has an STI (Shallow Trench Isolation) structure. That is, the element isolation region 3 includes a shallow trench 3 a recessed from the first surface S1 of the semiconductor layer 2 toward the second surface S2, and an isolation insulating film 3 b provided within the shallow trench 3 a so as to fill the shallow trench 3 a. The shallow trench 3 a can be formed, for example, using photolithography and dry etching. The isolation insulating film 3 b can be formed, for example, by depositing a silicon oxide film as an insulating film on the entire surface of the semiconductor layer 2 on the first surface S1 side, including the interior of the shallow trench 3 a, and then selectively removing the silicon oxide film on the first surface S1 of the semiconductor layer 2 by CMP so that the silicon oxide film in the shallow trench 3 a remains.

[0026] As shown in FIG. 1, a p-type well region 11 is provided in an element formation region partitioned by an element isolation region 3, and a transistor T1 is also provided. The transistor T1 is, for example, an insulated gate field effect transistor. The insulated gate transistor has a gate insulating film made of silicon oxide (SiO ２ A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of a silicon nitride (Si) film can be used. ３ N ４Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0027] 1 , in an element formation region partitioned by an element isolation region 3, the transistor T1 includes a gate insulating film provided on a first surface S1 of a semiconductor layer 2, a gate electrode 13a provided on the first surface S1 of the semiconductor layer 2 with the gate insulating film interposed therebetween, a pair of main electrode regions 14a and 14b provided in the semiconductor layer 2 on both sides of the gate electrode 13a in the gate length direction and functioning as a source region and a drain region, and a p-type well region 11 functioning as a channel formation region. The gate electrode 13a is made of, for example, a polycrystalline silicon film doped with an impurity that reduces resistance. Each of the pair of main electrode regions 14a and 14b is made of, for example, an n-type semiconductor region provided in the p-type well region 11.

[0028] 1, the insulating layer 16 is provided between the first surface S1 of the semiconductor layer 2 and the multi-layer wiring layer 20. The insulating layer 16 includes an etching stopper film 17 provided on the first surface S1 of the semiconductor layer 2 to cover the gate electrode 13a of the transistor T1, and a planarization film 18 provided on the side of the etching stopper film 17 opposite to the semiconductor layer 2 side. The etching stopper film 17 is made of a material that can secure an etching ratio with respect to the semiconductor layer 2 and the field insulating portion 4, such as silicon nitride (Si ３ N ４ The surface of the planarization film 18 on the side opposite to the etching stopper film 17 is planarized, and is made of, for example, a silicon oxide film.

[0029] 1, the first multilayer wiring layer 20 is stacked on the first surface S1 side of the semiconductor layer 2 with an insulating layer 16 interposed therebetween. The first multilayer wiring layer 20 has a multilayer wiring structure in which wiring layers 22 are stacked in multiple stages with an interlayer insulating film 21 interposed therebetween. Although not limited thereto, FIG. 1 illustrates a four-layer wiring structure in which wiring layers 22 are stacked in four stages as an example.

[0030] In the first multilayer wiring layer 20, each of the four wiring layers 22 includes a plurality of wirings. The first wiring layer 22 counting from the insulating layer 16 side includes a wiring 22a serving as a “first conductive portion” of the present technology. The wiring 22a overlaps the field insulating portion 4 in a plan view and is provided outside the first surface portion S1 of the semiconductor layer 2.

[0031] The interlayer insulating film 21 is made of, for example, a silicon oxide film. The wiring layer 22 is made of, for example, a copper (Cu) film or a Cu alloy film containing Cu as a main component, or an aluminum (Al) film or an Al alloy film containing Al as a main component.

[0032] An insulating film 23 is provided on the side of the first multilayer wiring layer 20 opposite to the insulating layer 16 side (semiconductor layer 2 side) so as to cover the first multilayer wiring layer 20. The insulating film 23 is made of, for example, a silicon oxide film.

[0033] 1, the second multilayer wiring layer 40 is stacked on the second surface S2 side of the semiconductor layer 2 with an insulating film 24 interposed therebetween. The second multilayer wiring layer 40 has a multilayer wiring structure in which wiring layers 42 are stacked in multiple stages with an interlayer insulating film 41 interposed therebetween. Although not limited thereto, FIG. 1 illustrates a two-layer wiring structure in which wiring layers 42 are stacked in two stages as an example.

[0034] In the second multilayer wiring layer 40, each of the two wiring layers 42 includes a plurality of wirings. The first wiring layer 42 counting from the insulating film 24 side includes a wiring 42a serving as a “second conductive portion” of the present technology. The wiring 42a overlaps the field insulating portion 4 in a plan view and is provided outside the second surface portion S2 of the semiconductor layer 2.

[0035] The interlayer insulating film 41 is made of, for example, a silicon oxide film. The wiring layer 42 is made of, for example, a copper (Cu) film or a Cu alloy film mainly containing Cu, or an aluminum (Al) film or an Al alloy film mainly containing Al. The insulating film 24 is made of, for example, a silicon oxide film.

[0036] <Through contact electrode and contact hole portion> As shown in Figures 1 and 2, the through contact electrode 34 penetrates each of the insulating film 24, semiconductor layer 2, field insulating portion 4, and insulating layer 16 from the second wiring layer 40 side in the thickness direction (Z direction) of the semiconductor layer 2, and is electrically and mechanically connected to each of the wiring (first conductive portion) 22a of the first multilayer wiring layer 20 and the wiring (second conductive portion) 42a of the second wiring layer 40.

[0037] As described above, the field insulator 4 is provided on the first surface S1 of the semiconductor layer 2. The wiring (first conductive portion) 22a overlaps the field insulator 4 in a plan view and is provided outside the first surface S1 of the semiconductor layer 2. The wiring (second conductive portion) 42a overlaps the field insulator 4 in a plan view and is provided outside the second surface S2 of the semiconductor layer 2.

[0038] 2, the through contact electrode 34 has a stepped shape including a first portion 34a extending from the wiring 42a as the second conductive portion toward the field insulating portion 4, and a second portion 34b extending from the first portion 34a toward the wiring 22a as the first conductive portion and having an outer size Wb in a plan view smaller than the outer size Wa of the first portion 34a. １ is the outer size Wa of the wiring 42 side ２ is smaller than.

[0039] The through contact electrode 34 has a first portion 34a and a second portion 34b that are integrated and aligned in the thickness direction (Z direction) of the semiconductor layer 2. The second portion 34b has a side opposite to the first portion 34a that is electrically and mechanically connected to the wiring 22a, and the first portion 34a has a side opposite to the second portion 34b that is electrically and mechanically connected to the wiring 42a.

[0040] The first portion 34a of the through contact electrode 34 penetrates the insulating film 24 and the semiconductor layer 2 from the wiring 42a toward the field insulating part 4 and terminates in the field insulating part 4. On the other hand, the second portion 34b of the through contact electrode 34 penetrates the insulating layer 16 from the first portion 34a toward the wiring 22a and reaches the wiring 22a. That is, the through contact electrode 34 penetrates the insulating film 24, the semiconductor layer 2, the field insulating part 4, and the insulating layer 16 from the wiring 42a toward the wiring 22a in the thickness direction (Z direction) of the semiconductor layer 2 and is electrically and mechanically connected to each of the wiring 22a and the wiring 42a.

[0041] 2, the through contact electrode 34 is provided inside the contact hole 32. The contact hole 32 includes a first dug portion 31a that extends from the wiring 42a, through the insulating film 24 and the semiconductor layer 2, and terminates in the field insulating portion 4, and a second dug portion 31b that extends from the first dug portion 31a, through the insulating layer 16, and reaches the wiring 22a, and has an outer size smaller than that of the first dug portion 31a in a plan view. The first dug portion 31a and the second dug portion 31b are arranged in this order in a line in the thickness direction (Z direction) of the semiconductor layer 2.

[0042] The first portion 34a of the through contact electrode 34 is provided inside the first carved portion 31a of the contact hole 32 in alignment with the first carved portion 31a via an isolation insulating film (sidewall insulating film) 33, and is electrically isolated from the semiconductor layer 2 by this isolation insulating film 33. The second portion 34b of the through contact electrode 34 is provided inside the second carved portion 31b of the contact hole 32 in alignment with the second carved portion 31b.

[0043] The isolation insulating film 33 is provided along the inner wall of the first carved portion 31 a of the contact hole 32. For example, a thin film made of silicon oxide can be used as the isolation insulating film 33. For example, a high-melting-point metal film such as a tungsten (W) film, a titanium (Ti) film, a tantalum (Ta) film, a molybdenum (Mo), or a niobium (Nb) film can be used as the through-contact electrode 34.

[0044] The wiring 22 a , the through contact electrode 34 , and the wiring 42 a are arranged in a line in this order in the thickness direction of the semiconductor layer 2 .

[0045] <Field Insulator> As shown in FIGS. 1 and 2 , the field insulator 4 has an STI (Shallow Trench Isolation) structure, similar to the inter-element isolation region 3. That is, the field insulator 4 includes a shallow trench 4a recessed from the first surface S1 of the semiconductor layer 2 toward the second surface S2, and an isolation insulating film 4b provided within the shallow trench 4a so as to fill the shallow trench 4a. The field insulator 4 may be formed, for example, in the same process as the inter-element isolation region 3, although this is not limited thereto. In this first embodiment, the field insulator 4 is provided separately from the inter-element isolation region 3, but the inter-element isolation region 3 may also serve as the field insulator. That is, the field insulator 4 may be the inter-element isolation region 3 that partitions the element formation region on the first surface S1 of the semiconductor layer 2.

[0046] 3A, the field insulator 4 has a ring-like planar shape with an opening 4y in the center in a plan view. The planar shapes of the field insulator 4 and the opening 4y are, for example, circular, but are not limited to this. In this first embodiment, as shown in FIGS. 2 and 3A, the opening 4y of the field insulator 4 is included in the first carved portion 31a of the contact hole 32, and the first portion 34a of the through contact electrode 34 extends into the opening 4y of the field insulator 4.

[0047] Referring to FIG. 2, the field insulating portion 4 functions as an etching stopper when the semiconductor layer 2 is etched to form the first recessed portion 31a, and also functions as an etching mask when the second recessed portion 31b is formed.

[0048] The shape of the center of the field insulator 4 differs before and after the formation of the contact hole 32. As shown in FIG. 3A , the field insulator 4 after the formation of the contact hole 32 has an opening 4y in its center in plan view. This opening 4y is formed at the same time as the formation of the second carved portion 31b. On the other hand, as shown in FIG. 3B , the field insulator 4 before the formation of the contact hole 32 is formed so as to surround the protruding portion 2a of the semiconductor layer 2 in plan view, and has an opening 4x in its center. The protruding portion 2a of the semiconductor layer 2 is provided in the opening 4x. This opening 4x is used to position the second carved portion 31b with respect to the wiring 22a serving as the first conductive portion, and the second carved portion 31b is formed through this opening 4x. That is, even if the wiring 22a and the first carved portion 31a are misaligned relative to each other due to distortion of the semiconductor layer 2 or misalignment of the mask when forming the contact hole 32, there will be no relative misalignment between the wiring 22a and the second carved portion 31b formed through the opening 4x. Moreover, since the second portion 34b of the through contact electrode 34 is formed inside the second carved portion 31b and aligned with the second carved portion 31b, there will be no relative misalignment between the wiring 22a and the second portion 34b of the through contact electrode 34. Therefore, the width and pitch of the wiring 22a connected to the through contact electrode 34 can be narrowed.

[0049] The opening 4x of the field insulating portion 4 disappears when the second recessed portion 31b is formed.

[0050] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device 1A according to this first embodiment will be described with reference to FIG. 3B and FIGS. 4A to 4I. FIGS. 4A to 4I are longitudinal cross-sectional views schematically showing longitudinal cross-sectional structures along the X and Z directions. In FIGS. 4A to 4I, hatching representing cross sections has been partially omitted to make the drawings easier to see. In this first embodiment, the description will focus specifically on the formation of the through contact electrodes 34 included in the manufacture of the semiconductor device 1A.

[0051] First, as shown in FIG. 4A , an element isolation region 3 and a field insulating film 4 are formed on the first surface S1 of the semiconductor layer 2. Then, a transistor T1 is formed in the element formation region defined by the element isolation region 3. The element isolation region 3 defines the element formation region and separates the element formation regions. The element isolation region 3 can be formed by forming a shallow groove 3 a on the first surface S1 of the semiconductor layer 2, then depositing an insulating film, such as a silicon oxide film, on the entire surface of the first surface S1 of the semiconductor layer 2, including the interior of the shallow groove 3 a, and then selectively removing the silicon oxide film on the first surface S1 of the semiconductor layer 2 by CMP so that the silicon oxide film (isolation insulating film 3 b) inside the shallow groove 3 a remains. The field insulating film 4 is formed in the same process as the element isolation region 3. The field insulator 4 formed on the first surface S1 of the semiconductor layer 2 includes a shallow groove 4a recessed from the first surface S1 toward the second surface S2 of the semiconductor layer 2, and an isolation insulating film 4b provided within the shallow groove 4a so as to fill the shallow groove 4a. As shown in FIG. 3B , the field insulator 4 is formed in a ring-like planar shape that surrounds the protruding portion 2a of the semiconductor layer 2 in a plan view and has an opening 4x in its center. The protruding portion 2a of the semiconductor layer 2 is provided in the opening 4x. That is, the field insulator 4 is formed in a shape that has the opening 4x where the semiconductor layer 2 is present. The planar shapes of the field insulator 4 and the opening 4y are not limited to this, but may be, for example, circular.

[0052] Next, as shown in FIG. 4B , an insulating layer 16 including an etching stopper film 17 and a planarization film 18 is formed on the first surface S1 side of the semiconductor layer 2, and then a via electrode 19a is formed in the insulating layer 16. The via electrode 19a is formed at a position overlapping the gate electrode 13a of the transistor T1 in a planar view and is electrically and mechanically connected to the gate electrode 13a. The etching stopper film 17 is formed on the first surface S1 of the semiconductor layer 2, covering the transistor T1, the element isolation region 3, and the field insulation 4. The etching stopper film 17 can be a film that has an etching ratio (selectivity) with respect to the semiconductor layer 2 and the field insulation 4, such as a silicon nitride film. The planarization film 18 can be formed by forming, for example, a silicon oxide film on the side of the etching stopper film 17 opposite the semiconductor layer 2 side, and then planarizing the surface of the silicon oxide film by a CMP method or an etch-back method. The via electrode 19a penetrates from the surface of the insulating layer 16 through the planarizing film 18 and the etching stopper film 17, and is electrically and mechanically connected to the gate electrode 13a of the transistor T1.

[0053] Next, as shown in FIG. 4C , a first multilayer wiring layer 20 and an insulating film 23 are formed in this order on the side of the insulating layer 16 opposite the semiconductor layer 2. The multilayer wiring layer 20 is formed, for example, as a four-layer wiring structure in which wiring layers 22 are stacked in four stages with an interlayer insulating film 21 interposed therebetween. In the first multilayer wiring layer 20, the first wiring layer 22 counting from the insulating layer 16 side includes a wiring 22a serving as the “first conductive portion” of the present technology. This wiring 22a is preset as a connection portion to which a through-contact electrode 34 (described later) is connected, and is formed at a position overlapping the opening 4x of the field insulating portion 4 in a plan view, in other words, the protrusion 2a of the semiconductor layer 2. That is, the process of forming the first multilayer wiring layer 20 includes a process of forming the wiring 22a on the outside of the first surface portion S1 of the semiconductor layer 2, overlapping the opening 4x of the field insulating portion 4 (the protrusion 2a of the semiconductor layer 2) with the insulating layer 16 interposed therebetween in a plan view. In this step, the relative positions of the opening 4x of the field insulating section 4 and the wiring 22a of the multilayer wiring layer 20 are fixed.

[0054] Next, the second surface S2 side of the semiconductor layer 2 is cut by, for example, CMP to reduce the thickness of the semiconductor layer 2 in the Z direction (thinning), and then, as shown in Fig. 4D, an insulating film 24 is formed on the second surface S2 side of the semiconductor layer 2. As the insulating film 24, for example, a silicon oxide film can be used.

[0055] Next, the insulating film 24 and the semiconductor layer 2 are selectively removed, and further the semiconductor layer 2 (protrusion 2a) within the opening 4x of the field insulating portion 4 is selectively removed to form a first recessed portion 31a that is connected to the opening 4x of the field insulating portion 4 and has an outer size in plan view larger than that of the opening 4x of the field insulating portion 4, as shown in FIG. 4E.

[0056] The first dug portion 31a is formed using well-known photolithography and dry etching techniques. The semiconductor layer 2, including the protrusion 2a, is etched under conditions that ensure an etching ratio relative to the field insulator 4. The first dug portion 31a is formed under conditions that make its outer size, in plan view, larger than that of the opening 4x of the field insulator 4.

[0057] Next, using the field insulator 4 exposed from the first dug portion 31a in plan view (located within the first dug portion 31a in plan view) as an etching mask, the insulating layer 16 is selectively removed through the opening 4x in the field insulator 4 to form a second dug portion 31b that extends from the first dug portion 31a to the wiring 22a, as shown in Fig. 4F. The second dug portion 31b is formed using, for example, well-known photolithography and dry etching techniques.

[0058] In this process, the second dug-out portion 31b is formed in alignment with the opening 4x of the field insulation portion 4, whose relative position with respect to the wiring 22a is fixed. Therefore, even if a positional shift occurs in the relative position between the wiring 22a (first conductive portion) and the first dug-out portion 31a due to distortion of the semiconductor layer 2 or misalignment of the mask, the second dug-out portion 32b can be formed without causing a positional shift in the relative position between the wiring 22a (first conductive portion) and the second dug-out portion 31b.

[0059] In this process, the field insulating portion 4 that overlaps with the first carved portion 31a in plan view is also etched, so that the opening 4x in the field insulating portion 4 disappears, and a new opening 4y having a planar outer size larger than the planar outer size of the opening 4x is formed, and a new first carved portion 31a is formed that includes the opening 4y. Compared to before the second carved portion 31b was formed, the first carved portion 31a has an increased depth along the thickness direction (Z direction) of the semiconductor layer 2 and an increased length along the Z direction. In this process, a contact hole 32 is formed that includes the first carved portion 31a and the second carved portion 31b and extends from the surface of the insulating film 24 to the wiring 22a.

[0060] 4G, an isolation insulating film (sidewall insulating film) 33 is formed on the inner wall of the contact hole 32, including the first carved portion 31 a and the second carved portion 31 b, so as to extend along the inner wall. The isolation insulating film 33 may be, for example, a thin film made of silicon oxide.

[0061] Next, as shown in FIG. 4H, the isolation insulating film 33 covering the wiring 22a inside the contact hole 32 (second carved portion 31b) is selectively removed.

[0062] 4I , a through-contact electrode 34 electrically and mechanically connected to the wiring 22a of the first multilayer wiring layer 20 is formed inside the contact hole 32, including the first dug portion 31a and the second dug portion 31b. The through-contact electrode 34 can be formed, for example, by depositing a conductive film on the insulating film 24 opposite the semiconductor layer 2 side so as to fill the inside of the contact hole 32, and then selectively removing the conductive film on the insulating film 24 by CMP so that the conductive film in the contact hole 32 remains. The conductive film can be, for example, a high-melting-point metal film such as a tungsten (W) film, a titanium (Ti) film, a tantalum (Ta) film, molybdenum (Mo), or niobium (Nb) film.

[0063] In this process, the through contact electrode 34 is formed in a stepped shape including a first portion 34a provided in the first recessed portion 31a and a second portion 34b provided in the second recessed portion 31b and having an outer size in a plan view that is one step smaller than that of the first portion 34a.

[0064] Furthermore, in this process, the second portion 34b of the through contact electrode 34 is formed in alignment with the second recessed portion 31b, which does not have any positional misalignment relative to the wiring 22a, so that this second portion 34b can also be formed without any positional misalignment relative to the wiring 22a.

[0065] Next, a second multilayer wiring layer 40 including wiring 42a that overlaps the through contact electrode 34 in a planar view and is electrically and mechanically connected to the through contact electrode 34 is formed on the side of the insulating film 24 opposite the semiconductor layer 2 side.

[0066] This process forms a stepped through contact electrode 34 that includes a first portion 34a extending from the second conductive portion 42b toward the field insulating portion 4, and a second portion 34b extending from the first portion 34a toward the wiring 22a and having an external size one step smaller than that of the first portion 34a when viewed in a plane.

[0067] <<Main Effects of First Embodiment>> Next, main effects of this first embodiment will be described. The semiconductor device 1A according to this first embodiment includes a field insulator 4 provided on the first surface S1 of the semiconductor layer 2, a wiring 22a as a first conductive portion that overlaps the field insulator 4 in a plan view and is provided outside the first surface S1 of the semiconductor layer 2, a wiring 42a as a second conductive portion that overlaps the field insulator 4 in a plan view and is provided outside the second surface S2 of the semiconductor layer 2, and a through contact electrode 34 that penetrates the semiconductor layer 2 in one direction, that is, the thickness direction (Z direction) of the semiconductor layer 2, and is connected to each of the wiring 22a and the wiring 42a.

[0068] The through contact electrode 34 has a stepped shape including a first portion 34a extending from the wiring 42a toward the field insulation part 4 and a second portion 34b extending from the first portion 34a toward the wiring 22a and having an outer size in a plan view that is one step smaller than the first portion 34a. Therefore, compared to the case where the first portion 34a is directly connected to the wiring 22a, the width of the wiring 22a to which the second portion 34b of the through contact electrode 34 is connected can be narrowed, and accordingly, the pitch of the wiring in the first multilayer wiring layer 20 can also be narrowed. Therefore, the semiconductor device 1A according to the first embodiment of the present technology can further improve the degree of freedom in routing the wiring.

[0069] Furthermore, since the degree of freedom in routing the wiring can be further improved, the wiring can be made finer, and accordingly, it becomes possible to achieve a higher integration of the semiconductor device 1A.

[0070] Here, the external size of the through contact electrode 34 in plan view tends to increase in proportion to the thickness of the semiconductor layer 2 it penetrates. Although this varies depending on the product, the thickness of the semiconductor layer 2 in the Z direction is typically several μm to several hundred μm. As the thickness of the semiconductor layer 2 increases, the through contact electrode 34 also becomes thicker, resulting in a larger external size in plan view. Meanwhile, the receiving wiring 22 a to which the through contact electrode 34 is connected needs to be wider than the external size of the connection portion of the through contact electrode 34, taking into account misalignment of the mask when forming the contact hole and distortion of the semiconductor layer 2, in order to prevent poor connection with the through contact electrode 34. Therefore, forming the through contact electrode 34 that penetrates the semiconductor layer 2 in a stepped shape, as in the first embodiment, is particularly useful for improving the degree of freedom in routing the wiring.

[0071] A method for manufacturing the solid-state imaging device 1A according to the first embodiment includes the steps of: forming a field insulating section 4 on a first surface S1 of the semiconductor layer 2, the field insulating section 4 having an opening 4x where a protruding section 2a of the semiconductor layer 2 is present; forming a wiring 22a as a first conductive section on the outside of the first surface S1 of the semiconductor layer 2, the wiring 22a overlapping the opening 4x with the insulating layer 16 interposed therebetween in a plan view; selectively removing the semiconductor layer 2 from the second surface S2 side of the semiconductor layer 2 into the opening 4x of the field insulating section 4 to form a first dug section 31a that is continuous with the opening 4x of the field insulating section 4 and has an outer size larger than the opening 4 in a plan view; selectively removing the insulating layer 16 through the opening 4x of the field insulating section 4 to form a second dug section 31b that reaches the wiring 22a; and forming a through contact electrode 34 connected to the wiring 22a in the first dug section 31a and the second dug section 31b. and forming wiring 42 a as a second electrode portion on the outside of the second surface portion S2 of the semiconductor layer 2 , the wiring 42 a overlapping the through contact electrode 34 in a plan view and connected to the through contact electrode 34 .

[0072] According to the manufacturing method of semiconductor device 1A including these steps, it is possible to form stepped through-contact electrode 34 having first portion 34a extending from wiring 42a toward field insulation 4 and second portion 34b extending from first portion 34a toward wiring 22a and having an outer size in a plan view that is one step smaller than first portion 34a. Furthermore, even if there is a positional misalignment between wiring 22a and first dug portion 31a due to distortion of semiconductor layer 2, misalignment of a mask, or the like, second dug portion 31b can be formed without any positional misalignment between wiring 22a and second dug portion 31b or with the positional misalignment minimized. Furthermore, since the second portion 34b of the through contact electrode 34 is formed in alignment with the second carved portion 31b, which is not misaligned relative to the wiring 22a, the second portion 34b of the through contact electrode 34 can also be formed without misalignment relative to the wiring 22a, or with misalignment minimized. This allows the width of the wiring 22a to which the second portion 34b of the through contact electrode 34 is connected to to be narrower than when the first portion 34a is directly connected to the wiring 22a, and therefore the wiring pitch in the first multilayer wiring layer 20 can also be narrower. Therefore, the manufacturing method of the semiconductor device 1A according to the first embodiment of the present technology also allows for further improvement in the degree of freedom in routing the wiring.

[0073] 5A is a plan view showing a schematic planar shape of a field insulating portion after forming a contact hole according to a modification 1-1 of the first embodiment of the present technology. FIG. 5B is a plan view showing a schematic planar shape of a field insulating portion before forming a contact hole according to a modification 1-1 of the first embodiment of the present technology.

[0074] As shown in Figures 5A and 5B, in this modification 1-1, the configuration of the field insulator 4 has been changed. That is, the field insulator 4 of this modification 1-1 has a rectangular planar shape. As shown in Figure 5A, the opening 4y of the field insulator 4 after the contact hole 32 is formed also has a rectangular planar shape. As shown in Figure 5B, the opening 4x of the field insulator 4 before the contact hole 32 is formed also has a rectangular planar shape. The present technology can also be applied to this modification 1-1, and the same effects as those of the first embodiment described above can be obtained.

[0075] [Second Embodiment] In this second embodiment, a case where a through contact electrode is connected to a relay electrode as a first conductive portion will be described. Fig. 6 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a semiconductor device according to a second embodiment of the present disclosure. In Fig. 6, hatching representing a cross section is partially omitted to make the drawing easier to see.

[0076] <Overall Configuration of Semiconductor Device> As shown in Fig. 6 , a semiconductor device 1B according to a second embodiment of the present technology has a configuration basically similar to that of the semiconductor device 1A according to the first embodiment described above, but differs in the following configuration. That is, as shown in Fig. 6 , the semiconductor device 1B according to the second embodiment further includes a relay electrode 13b as a first conductive portion. A through contact electrode 34 is electrically and mechanically connected to this relay electrode 13b. The configuration of the contact hole portion 32B in which this through contact electrode 34 is provided is different.

[0077] 6, the relay electrode 13b is provided between the field insulator 4 and the insulating layer 16. The relay electrode 13b is electrically connected to a wiring 22a provided in the first wiring layer 22 of the multilayer wiring layer 20 through a via electrode 19b provided in the insulating layer 16. The relay electrode 13b is formed, for example, in the same process as the gate electrode 13a of the transistor T1.

[0078] The contact hole 32B is formed by an opening 4x provided in the field insulating part 4 and a recessed part 31a extending from the wiring 42a through the insulating film 24 and the semiconductor layer 2 to reach the field insulating part 4 and connected to the opening 4x of the field insulating part 4. １ The opening 4x of the field insulating section 4 includes the recessed section 31a １ The opening 4x of the field insulator 4 has an outer size in plan view that is equal to or larger than the recessed portion 31a. １ In other words, the recessed portion 31a １ has an outer size in plan view larger than that of the opening 4x of the field insulating portion 4.

[0079] As shown in FIG. 6, the through contact electrode 34 of the second embodiment has a recessed portion 31a １ The recessed portion 31a has a first portion 34a provided in the recessed portion 31a and a second portion 34b provided in the opening 4x of the field insulating portion 4. １ The first portion 34a provided in the recess 31a is electrically and mechanically connected to the wiring 42a serving as the second conductive portion, and extends from the wiring 42a toward the opening 4x of the field insulating portion 4. The first portion 34a is formed in the recess 31a in the same manner as the first portion 34a of the first embodiment. １ The insulating film 33 electrically insulates and separates the semiconductor layer 2 from the insulating film 33 .

[0080] The second portion 34b provided in the opening 4x of the field insulating portion 4 is integrated with the first portion 34a. The second portion 34b extends from the first portion 34a toward the wiring 22a and is electrically and mechanically connected to the wiring 22a.

[0081] That is, the through contact electrode 34 of this second embodiment penetrates each of the insulating film 24, the semiconductor layer 2 and the field insulation portion 4, and is electrically and mechanically connected to the relay electrode 13b provided on the outside of the first surface portion S1 of the semiconductor layer 2, and is also electrically and mechanically connected to the wiring 42a provided on the outside of the second surface portion S2 of the semiconductor layer 2.

[0082] <<Method of Manufacturing Semiconductor Device>> Next, a method of manufacturing the semiconductor device 1B according to the second embodiment will be described with reference to Figures 7A to 7G. Figures 7A to 7G are longitudinal cross-sectional views schematically showing longitudinal cross-sectional structures along the X and Z directions. In Figures 7A to 7G, hatching representing cross sections has been partially omitted to make the drawings easier to see. In this first embodiment, the description will focus specifically on the formation of the through contact electrodes 34 included in the manufacture of the semiconductor device 1A.

[0083] First, as shown in FIG. 7A, an inter-element isolation region 3 and a field insulating portion 4 are formed on the first surface S1 of the semiconductor layer 2, and then a transistor T1 is formed in the element formation region partitioned by the inter-element isolation region 3, and a relay electrode 13b is formed outside the field insulating portion 4 so as to overlap with the opening 4x of the field insulating portion 4 in a planar view.

[0084] The element isolation region 3 can be formed, as in the first embodiment, by forming a shallow groove 3 a in the first surface S1 of the semiconductor layer 2, then depositing, for example, a silicon oxide film as an insulating film over the entire surface of the first surface S1 of the semiconductor layer 2, including the interior of the shallow groove 3 a, and then selectively removing the silicon oxide film on the first surface S1 of the semiconductor layer 2 by CMP so that the silicon oxide film inside the shallow groove 3 a remains. The field insulation 4 is formed in the same process as the element isolation region 3. As in the first embodiment, the field insulation 4 formed on the first surface S1 of the semiconductor layer 2 includes a shallow groove 4 a recessed from the first surface S1 toward the second surface S2 of the semiconductor layer 2, and an isolation insulation film 4 b provided inside the shallow groove 4 a so as to fill the shallow groove 4 a. 3B , the field insulator 4 is formed in a ring-like planar shape that surrounds the protruding portion 2a of the semiconductor layer 2 in a plan view and has an opening 4x in its center. The protruding portion 2a of the semiconductor layer 2 is provided in the opening 4x. That is, the field insulator 4 is formed in a shape that has the opening 4x where the semiconductor layer 2 is present. The planar shapes of the field insulator 4 and the opening 4y are not limited to this, but may be, for example, circular.

[0085] The relay electrode 13b is formed to cover the opening 4x in the field insulator 4, i.e., to cover the protrusion 2a of the semiconductor layer 2. The relay electrode 13b can be formed in the same process as the gate electrode 13a of the transistor T1. The gate electrode 13a and the relay electrode 13b can each be formed, for example, by depositing a polycrystalline silicon film containing impurities that reduce resistance on the first surface S1 side of the semiconductor layer 2, and then patterning this polycrystalline silicon film using well-known photolithography and dry etching techniques. In this process, the relative positions of the opening 4x in the field insulator 4 and the relay electrode 13b are fixed.

[0086] 7B , an insulating layer 16 including an etching stopper film 17 and a planarizing film 18 is formed on the first surface S1 side of the semiconductor layer 2 by the same method as in the first embodiment described above, and then via electrodes 19 a and 19 b are formed in the insulating layer 16. The via electrode 19 a is formed at a position overlapping the gate electrode 13 a of the transistor T1 in a planar view and is electrically and mechanically connected to the gate electrode 13 a. The via electrode 19 b is formed at a position overlapping the opening 4 x of the field insulator 4 (the protrusion 2 a of the semiconductor layer 2) and the relay electrode 13 b in a planar view and is electrically and mechanically connected to the relay electrode 13 b.

[0087] 7C , a first multilayer wiring layer 20 and an insulating film 23, similar to those in the first embodiment, are formed in this order on the side of the insulating layer 16 opposite the semiconductor layer 2. In this second embodiment, unlike the first embodiment, the wiring 22a provided in the first wiring layer 22 of the first multilayer wiring layer 20 is formed so as to overlap the via electrode 19b in a plan view and is electrically and mechanically connected to the via electrode 19b. That is, the process of forming the first multilayer wiring layer 20 includes a process of forming the wiring 22a that overlaps the via electrode 19b of the insulating layer 16 and is electrically and mechanically connected to the via electrode 19b.

[0088] Next, similarly to the first embodiment described above, the thickness of the semiconductor layer 2 in the Z direction is reduced, and then, as shown in FIG. 7D, an insulating film 24 is formed on the second surface S2 side of the semiconductor layer 2.

[0089] Next, the insulating film 24 is selectively removed, and the semiconductor layer 2 is selectively removed from the second surface S2 side of the semiconductor layer 2 to the inside of the opening 4x of the field insulating part 4, to form a dug portion 31a that is connected to the opening 4x of the field insulating part 4 and has an outer size in plan view larger than that of the opening 4x of the field insulating part 4, as shown in FIG. 7E. １ The recessed portion 31a is formed. １ The recessed portion 31a extends from the surface of the insulating film 24 toward the field insulating portion 4 along the thickness direction (Z direction) of the semiconductor layer 2 and connects to the opening 4x of the field insulating portion 4. １The formation of the protrusions 2a is carried out by using well-known photolithography and dry etching techniques. The semiconductor layer 2 including the protrusions 2a is etched under conditions that ensure an etching ratio relative to the field insulating portion 4.

[0090] In this step, the protruding portion 2a of the semiconductor layer 2 located in the opening 4x of the field insulating portion 4 is removed. １ In this process, the contact hole 32B including the opening 4x of the field insulating layer 4 and the recessed portion 31a may be formed due to distortion of the semiconductor layer 2 or misalignment of the mask. １ Even if a positional deviation occurs in the relative position between the relay electrode 13b and the opening 4x of the field insulator 4, no positional deviation occurs in the relative position between the relay electrode 13b and the opening 4x of the field insulator 4, and the recessed portion 31a １ can be formed.

[0091] In the second embodiment, the recessed portion 31a does not include the opening 4x of the field insulating portion 4. １ However, the opening 4x of the field insulating portion 4 is side-etched when the protruding portion 2a of the semiconductor layer 2 is etched. Therefore, the opening 4x of the field insulating portion 4 is included in the recessed portion 31a. １ It may also be possible to use the following.

[0092] Next, as shown in FIG. 7F, the recessed portion 31 a １ An isolation insulating film 33 is formed on the side wall of the insulating film 33 .

[0093] Next, as shown in FIG. 7G, the dug portion 31a １A through contact electrode 34 electrically and mechanically connected to the relay electrode 13b is formed inside the contact hole 32B, including the opening 4x of the field insulating part 4. The through contact electrode 34 can be formed, for example, by depositing a conductive film on the side of the insulating film 24 opposite the semiconductor layer 2 side so as to fill the inside of the contact hole 32B, and then selectively removing the conductive film on the insulating film 24 by CMP so that the conductive film in the contact hole 32B remains. As the conductive film, for example, a high-melting-point metal film similar to that in the first embodiment described above can be used.

[0094] In this step, the through contact electrode 34 is formed in the recessed portion 31a １ The through contact electrode 34 is formed in a stepped shape including a first portion 34a provided in the opening 4x of the field insulating part 4 and a second portion 34b provided in the opening 4x of the field insulating part 4 and having an outer size in a plan view that is one step smaller than the first portion 34a. Furthermore, in this process, the second portion 34b of the through contact electrode 34 is formed in alignment with the opening 4x of the field insulating part 4, which does not have any positional misalignment relative to the relay electrode 13b, so that the second portion 34b can also be formed without any positional misalignment relative to the relay electrode 13b.

[0095] Next, a second multilayer wiring layer 40 including wiring 42a that overlaps the through contact electrode 34 in a planar view and is electrically and mechanically connected to the through contact electrode 34 is formed on the side of the insulating film 24 opposite the semiconductor layer 2 side.

[0096] This process forms a stepped through contact electrode 34 including a first portion 34a extending from the second conductive portion 42b toward the field insulating portion 4, and a second portion 34b extending from this first portion 34a through the opening 4x of the field insulating portion 4 toward the relay electrode 13b and having an outer size one step smaller than that of the first portion 34a when viewed in a plane.

[0097] <<Main effects of the second embodiment>> In the semiconductor device 1B according to the second embodiment, as in the semiconductor device 1A according to the first embodiment described above, it is possible to further improve the degree of freedom in routing wiring and also to achieve a high degree of integration of the semiconductor device 1B.

[0098] Furthermore, in the manufacturing method of the semiconductor device 1B according to the second embodiment, as in the manufacturing method of the semiconductor device 1A according to the first embodiment described above, it is possible to form a stepped through contact electrode 34 having a first portion 34a extending from the wiring 42a as the second conductive portion toward the field insulation portion 4, and a second portion 34b extending from this first portion 34a toward the relay electrode 13b as the first conductive portion and having an outer size one step smaller than that of the first portion 34a when viewed in a plane.

[0099] Furthermore, in the manufacturing method of the semiconductor device 1B according to the second embodiment, as in the manufacturing method of the semiconductor device 1A according to the first embodiment described above, the degree of freedom in routing wiring can be further improved.

[0100] Third Embodiment In this third embodiment, a case will be described in which a through contact electrode is connected to a via electrode serving as a first conductive portion.

[0101] 8 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure of a semiconductor device according to a third embodiment of the present disclosure. In FIG. 8, hatching representing a cross section is partially omitted for ease of viewing the drawing.

[0102] <Overall Configuration of Semiconductor Device> As shown in Fig. 8 , a semiconductor device 1C according to a third embodiment of the present technology has a configuration basically similar to that of the semiconductor device 1A according to the first embodiment described above, but differs in the following configuration. That is, as shown in Fig. 8 , the semiconductor device 1C according to the third embodiment further includes a via electrode 19b as a first conductive portion. A through contact electrode 34 is electrically and mechanically connected to this via electrode 19b. The configuration of the contact hole portion 32C in which this through contact electrode 34 is provided is different.

[0103] 8, the via electrode 19b is provided in the insulating layer 16. The via electrode 19b is electrically connected to a wiring 22a provided in a first wiring layer 22 of the multi-layer wiring layer 20. The via electrode 19b is formed, for example, in the same process as the via electrode 19a connected to the gate electrode 13a of the transistor T1.

[0104] The contact hole 32C is formed by an opening 4x provided in the field insulating part 4 and a recessed part 31a extending from the wiring 42a through the insulating film 24 and the semiconductor layer 2 to reach the field insulating part 4 and connected to the opening 4x of the field insulating part 4. ２ The opening 4x of the field insulating section 4 includes the recessed section 31a ２ The opening 4x of the field insulating part 4 has an outer size in plan view that is equal to or larger than the size of the recessed part 31a. ２ In other words, the recessed portion 31a ２ has an outer size in plan view larger than that of the opening 4x of the field insulating portion 4.

[0105] As shown in FIG. 8, the through contact electrode 34 of the third embodiment has a recessed portion 31a ２ The recessed portion 31a has a first portion 34a provided in the recessed portion 31a and a second portion 34b provided in the opening 4x of the field insulating portion 4. ２ The first portion 34a provided in the recess 31a is electrically and mechanically connected to the wiring 42a serving as the second conductive portion, and extends from the wiring 42a toward the opening 4x of the field insulating portion 4. The first portion 34a is formed in the recess 31a in the same manner as the first portion 34a of the first embodiment. ２ The insulating film 33 electrically insulates and separates the semiconductor layer 2 from the insulating film 33 .

[0106] The second portion 34b provided in the opening 4x of the field insulator 4 is integrated with the first portion 34a. The second portion 34b penetrates the field insulator 4 from the first portion 34a toward the via electrode 19b and is electrically and mechanically connected to the via electrode 19b.

[0107] That is, the through contact electrode 34 of this third embodiment penetrates each of the insulating film 24, the semiconductor layer 2 and the field insulation portion 4, and is electrically and mechanically connected to the via electrode 19b provided on the outside of the first surface portion S1 of the semiconductor layer 2, and is also electrically and mechanically connected to the wiring 42a provided on the outside of the second surface portion S2 of the semiconductor layer 2.

[0108] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device 1C according to the third embodiment will be described with reference to Figures 9A to 9C. Figures 9A to 9C are longitudinal cross-sectional views schematically showing longitudinal cross-sectional structures along the X and Z directions. In Figures 9A to 9C, hatching representing cross sections has been partially omitted to make the drawings easier to see. In this first embodiment, the description will focus specifically on the formation of the through contact electrodes 34 included in the manufacture of the semiconductor device 1A.

[0109] First, the same steps as those in the first embodiment are carried out to form the insulating layer 16 as shown in FIG. 9A.

[0110] 9A can be formed by forming a shallow groove 3a in the first surface S1 of the semiconductor layer 2, forming an insulating film, for example, a silicon oxide film, on the entire surface of the first surface S1 of the semiconductor layer 2, including the interior of the shallow groove 3a, and then selectively removing the silicon oxide film on the first surface S1 of the semiconductor layer 2 by CMP so that the silicon oxide film inside the shallow groove 3a remains. The field insulating portion 4 shown in FIG. 9A is formed in the same process as the element isolation region 3. Similarly to the first embodiment, the field insulating portion 4 formed in the first surface S1 of the semiconductor layer 2 includes a shallow groove 4a recessed from the first surface S1 toward the second surface S2 of the semiconductor layer 2, and an isolation insulating film 4b provided inside the shallow groove 4a so as to fill the shallow groove 4a. 3B , the field insulator 4 is formed in a ring-like planar shape that surrounds the protruding portion 2a of the semiconductor layer 2 in a plan view and has an opening 4x in its center. The protruding portion 2a of the semiconductor layer 2 is provided in the opening 4x. That is, the field insulator 4 is formed in a shape that has the opening 4x where the semiconductor layer 2 is present. The planar shapes of the field insulator 4 and the opening 4y are not limited to this, but may be, for example, circular.

[0111] Next, an insulating layer 16 including an etching stopper film 17 and a planarizing film 18 is formed, and then via electrodes 19a and 19b are formed in the insulating layer 16, as shown in FIG. 9B . The via electrode 19a is formed at a position overlapping the gate electrode 13a of the transistor T1 in a planar view, and is electrically and mechanically connected to the gate electrode 13a. The via electrode 19b is formed at a position overlapping the opening 4x of the field insulator 4 (the protrusion 2a of the semiconductor layer 2) in a planar view. In this process, the relative positions of the opening 4x of the field insulator 4 and the via electrode 19b are fixed.

[0112] 9C , a first multilayer wiring layer 20 and an insulating film 23, similar to those in the first embodiment, are formed in this order on the side of the insulating layer 16 opposite the semiconductor layer 2. In this third embodiment, unlike the first embodiment, the wiring 22a provided in the first wiring layer 22 of the first multilayer wiring layer 20 is formed so as to overlap the via electrode 19a in a plan view and is electrically and mechanically connected to the via electrode 19a. That is, the process of forming the first multilayer wiring layer 20 includes a process of forming the wiring 22a which overlaps the via electrode 19b of the insulating layer 16 and is electrically and mechanically connected to the via electrode 19b.

[0113] Next, similarly to the first embodiment described above, the thickness of the semiconductor layer 2 is reduced, and then, as shown in FIG. 9D, an insulating film 24 is formed on the second surface S2 side of the semiconductor layer 2.

[0114] Next, the insulating film 24 is selectively removed, and the semiconductor layer 2 is selectively removed from the second surface S2 side of the semiconductor layer 2 to the inside of the opening 4x of the field insulating part 4, to form a dug portion 31a that is connected to the opening 4x of the field insulating part 4 and has an outer size in plan view larger than that of the opening 4x of the field insulating part 4, as shown in FIG. ２ The recessed portion 31a is formed. ２ The recessed portion 31a extends from the surface of the insulating film 24 toward the field insulating portion 4 along the thickness direction (Z direction) of the semiconductor layer 2 and connects to the opening 4x of the field insulating portion 4. ２ The formation of the protrusions 2a is carried out by using well-known photolithography and dry etching techniques. The semiconductor layer 2 including the protrusions 2a is etched under conditions that ensure an etching ratio relative to the field insulating portion 4.

[0115] In this step, the protruding portion 2a of the semiconductor layer 2 located in the opening 4x of the field insulating portion 4 is removed. ２ In this process, the opening 4x of the field insulating section 4 and the recessed section 31a may be distorted due to distortion of the semiconductor layer 2 or misalignment of the mask. ２Even if a positional deviation occurs in the relative position between the via electrode 19b and the opening 4x of the field insulating section 4, no positional deviation occurs in the relative position between the via electrode 19b and the opening 4x of the field insulating section 4, and the dug portion 32b ２ can be formed.

[0116] In the third embodiment, the recessed portion 31a does not include the opening 4x of the field insulating portion 4. ２ However, the opening 4x of the field insulating portion 4 is side-etched when the protruding portion 2a of the semiconductor layer 2 is etched. Therefore, the opening 4x of the field insulating portion 4 is included in the recessed portion 31a. ２ It may also be possible to use the following.

[0117] Next, as shown in FIG. 9F, the recessed portion 31a ２ An isolation insulating film 33 is formed on the side wall of the insulating film 33 .

[0118] Next, as shown in FIG. 7G, the dug portion 31a ２ A through contact electrode 34 electrically and mechanically connected to the via electrode 19b is formed inside the contact hole 32C including the opening 4x of the field insulating film 4. The through contact electrode 34 can be formed, for example, by depositing a conductive film on the insulating film 24 opposite the semiconductor layer 2 side so as to fill the inside of the contact hole 32C, and then selectively removing the conductive film on the insulating film 24 by CMP so that the conductive film in the contact hole 32C remains. As the conductive film, for example, a high-melting-point metal film similar to that in the first embodiment described above can be used.

[0119] In this step, the through contact electrode 34 is formed in the recessed portion 31a ２ and a second portion 34b that is provided in the opening 4x of the field insulating portion 4 and has an outer size in plan view that is one step smaller than the first portion 34a. In this process, the second portion 34b of the through contact electrode 34 is formed in alignment with the opening 4x of the field insulating portion 4, with no positional deviation occurring relative to the via electrode 19b, and therefore the second portion 34b can also be formed without any positional deviation occurring relative to the via electrode 19b.

[0120] Next, a second multilayer wiring layer 40 including wiring 42a that overlaps the through contact electrode 34 in a planar view and is electrically and mechanically connected to the through contact electrode 34 is formed on the side of the insulating film 24 opposite the semiconductor layer 2 side.

[0121] This process forms a stepped through contact electrode 34 that includes a first portion 34a extending from the second conductive portion 42b toward the field insulating portion 4, and a second portion 34b extending from this first portion 34a through the opening 4x of the field insulating portion 4 toward the via electrode 19b and having an external size one step smaller than that of the first portion 34a when viewed in a plane.

[0122] <<Main effects of the third embodiment>> In the semiconductor device 1C according to the third embodiment, as in the semiconductor device 1A according to the first embodiment described above, it is possible to further improve the degree of freedom in routing wiring, and also to achieve a high degree of integration of the semiconductor device 1C.

[0123] Furthermore, in the manufacturing method of the semiconductor device 1C according to the third embodiment, as in the manufacturing method of the semiconductor device 1A according to the first embodiment described above, it is possible to form a stepped through contact electrode 34 having a first portion 34a extending from the wiring 42a as the second conductive portion toward the field insulating portion 4, and a second portion 34b extending from this first portion 34a toward the relay electrode 13b as the first conductive portion and having an outer size one step smaller than that of the first portion 34a when viewed in a plane.

[0124] Furthermore, in the manufacturing method of the semiconductor device 1C according to the third embodiment, as in the manufacturing method of the semiconductor device 1A according to the first embodiment described above, the degree of freedom in routing wiring can be further improved.

[0125] Fourth Embodiment In this second embodiment, a case will be described in which a through contact electrode is connected to a bonding metal pad as a second conductive portion.

[0126] 10 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure of a semiconductor device according to a fourth embodiment of the present technology. In Fig. 10, hatching representing a cross section is partially omitted to make the drawing easier to see. As shown in Fig. 10, the semiconductor device 1D according to the fourth embodiment of the present technology has a configuration basically similar to that of the semiconductor device 1A according to the first embodiment described above, but differs in the following configuration.

[0127] That is, as shown in FIG. 10 , the semiconductor device 1D according to the fourth embodiment of the present technology further includes a plurality of bonding metal pads 25 provided on the insulating film 24 on the second surface portion S2 side of the semiconductor layer 2, and a plurality of bonding metal pads 45 provided on the second multilayer wiring layer 40.

[0128] 10 , each of the multiple bonding metal pads 25 faces the surface of the insulating film 24 opposite to the semiconductor layer 2 side. Among the multiple bonding metal pads 25, the bonding metal pad 25 a overlaps the through contact electrode 34 in a plan view and is electrically and mechanically connected to the through contact electrode 34. That is, the through contact electrode 34 of the fourth embodiment penetrates the semiconductor layer 2 along the thickness direction (Z direction) of the semiconductor layer 2 and is electrically and mechanically connected to the wiring 22 a provided on the outside of the first surface portion S1 of the semiconductor layer 2, and is also electrically and mechanically connected to the bonding metal pad 25 a provided on the outside of the second surface portion S2 of the semiconductor layer 2.

[0129] In the fourth embodiment, the wiring 22a corresponds to a specific example of a "first conductive portion" in the present technology, and the bonding metal pad 25a corresponds to a specific example of a "second conductive portion" in the present technology.

[0130] 10, each of the plurality of bonding metal pads 45 faces the surface of the multilayer wiring layer 40 on the insulating film 24 side. The plurality of bonding metal pads 45 and the plurality of bonding metal pads 25 are electrically and mechanically connected by metal-to-metal bonding with their respective bonding surfaces facing each other.

[0131] The bonding surfaces of the bonding metal pad 25 and the bonding metal pad 45 are directly bonded to each other. The bonding surfaces of the insulating film 24 and the uppermost insulating layer of the second multilayer wiring layer 40 are also directly bonded to each other. For example, surface activated bonding using plasma bonding can be used as the direct bonding.

[0132] The material of each of the bonding metal pads 25 and 45 may be, for example, a metal such as aluminum (Al) or copper (Cu), or an alloy containing Al or Cu as a main component.

[0133] The semiconductor device 1D of the fourth embodiment also provides the same effects as the semiconductor device 1A of the first embodiment described above.

[0134] Fifth Embodiment In this fifth embodiment, an example in which the present technology is applied to a solid-state imaging device called a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor as a photodetector included in a semiconductor device will be described with reference to FIGS. 11 to 14 .

[0135] <Overall Configuration of Solid-State Imaging Device> First, the overall configuration of the solid-state imaging device 1E will be described. As shown in Fig. 11 , the solid-state imaging device 1E according to the fifth embodiment of the present technology is mainly composed of a semiconductor chip 102 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1E is mounted on the semiconductor chip 102, and the semiconductor chip 102 can be considered as the solid-state imaging device 1E. As shown in Fig. 18 , this solid-state imaging device 1E (201) captures image light (incident light 206) from a subject via an optical lens 202, converts the amount of incident light 206 formed on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal as a pixel signal (image signal).

[0136] As shown in FIG. 11 , a semiconductor chip 102 on which a solid-state imaging device 1E is mounted includes, in a two-dimensional plane including mutually orthogonal X and Y directions, a rectangular pixel array section 102A provided in the center and a peripheral section 102B provided outside the pixel array section 102A so as to surround the pixel array section 102A. The semiconductor chip 102 is formed in the manufacturing process by dicing a semiconductor wafer including semiconductor layers 2, 60, and 90 (described below) into chip formation regions. Therefore, the configuration of the solid-state imaging device 1E described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, the present technology can be applied to both the semiconductor chip state and the semiconductor wafer state.

[0137] The pixel array unit 102A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 202 shown in Fig. 18. The pixel array unit 102A has a plurality of pixels (sensor pixels) 103 arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the pixels 103 are repeatedly arranged in each of the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.

[0138] 11 , a plurality of bonding pads 114 are arranged in the peripheral portion 102B. Each of the plurality of bonding pads 114 is arranged, for example, along each of the four sides in a two-dimensional plane of the semiconductor chip 102. Each of the plurality of bonding pads 114 functions as an input / output terminal that electrically connects the semiconductor chip 102 to an external device.

[0139] <Logic Circuit> The semiconductor chip 102 includes a logic circuit 113 shown in Fig. 12. As shown in Fig. 12, the logic circuit 113 includes a vertical drive circuit 104, a column signal processing circuit 105, a horizontal drive circuit 106, an output circuit 107, and a control circuit 108. The logic circuit 113 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs.

[0140] The vertical drive circuit 104 is configured with, for example, a shift register. The vertical drive circuit 104 sequentially selects desired pixel drive lines 110, supplies pulses to the selected pixel drive lines 110 for driving the pixels 103, and drives each pixel 103 row by row. That is, the vertical drive circuit 104 sequentially selects and scans each pixel 103 in the pixel array unit 102A row by row in the vertical direction, and supplies pixel signals from the pixels 103 based on signal charges generated by the photoelectric conversion unit (photoelectric conversion element) of each pixel 103 in accordance with the amount of received light to the column signal processing circuit 105 via vertical signal lines 111.

[0141] The column signal processing circuit 105 is arranged, for example, for each column of pixels 103, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 103. For example, the column signal processing circuit 105 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0142] The horizontal drive circuit 106 is configured by, for example, a shift register. The horizontal drive circuit 106 sequentially outputs horizontal scanning pulses to the column signal processing circuits 105, thereby selecting each of the column signal processing circuits 105 in turn and causing each of the column signal processing circuits 105 to output processed pixel signals to a horizontal signal line 112.

[0143] The output circuit 107 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 105 via the horizontal signal line 112, and outputs the processed signals. The signal processing may include, for example, buffering, black level adjustment, column variation correction, various types of digital signal processing, and the like.

[0144] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 108 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 104, column signal processing circuit 105, horizontal drive circuit 106, etc. Then, the control circuit 108 outputs the generated clock signals and control signals to the vertical drive circuit 104, column signal processing circuit 105, horizontal drive circuit 106, etc.

[0145] <Pixel Circuit Configuration> Each of the multiple pixels 103 shown in FIGS. 11 and 12 includes a photoelectric conversion region 121 shown in FIG. 13. The semiconductor chip 102 further includes a pixel circuit (readout circuit) 115 shown in FIG. 13. The photoelectric conversion region 121 includes a photoelectric conversion unit 124, a transfer transistor TR, and a floating diffusion region FD serving as a charge storage unit. The input stage side of the pixel circuit 115 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 121. In this fifth embodiment, as an example, a circuit configuration is used in which one pixel circuit 115 is assigned to one pixel 103. However, the assignment of the pixel circuits 115 is not limited to this fifth embodiment. For example, the circuit configuration may be such that one pixel circuit (readout circuit) 115 is assigned to one pixel block, each unit of which is made up of multiple pixels 103, or such that one pixel circuit 115 is assigned to multiple pixel blocks, each unit of which is made up of multiple pixels 103.

[0146] 13 is configured, for example, by a pn junction photodiode (PD) and generates a signal charge according to the amount of light received. The photoelectric conversion unit 124 has a cathode side electrically connected to the source region of the transfer transistor TR and an anode side electrically connected to a reference potential line (for example, ground).

[0147] 13 transfers signal charges photoelectrically converted by the photoelectric conversion unit 124 to the floating diffusion region FD. The source region of the transfer transistor TR is electrically connected to the cathode side of the photoelectric conversion unit 124, and the drain region of the transfer transistor TR is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 110 shown in FIG.

[0148] The floating diffusion region FD shown in FIG. 13 temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 124 via the transfer transistor TR.

[0149] The photoelectric conversion region 121 including the photoelectric conversion unit 124, the transfer transistor TR, and the floating diffusion region FD is mounted on a semiconductor layer 2 (see FIG. 14) serving as a first semiconductor layer, which will be described later.

[0150] 13 reads out the signal charges held in the floating diffusion region FD and outputs a pixel signal based on the read-out signal charges. In other words, the pixel circuit 115 converts the signal charges photoelectrically converted by the photoelectric conversion unit 124 into a pixel signal based on the signal charges and outputs the pixel signal.

[0151] 13, the pixel circuit 115 includes, but is not limited to, pixel transistors, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a switching transistor FDG. These pixel transistors (AMP, SEL, RST, FDG) and the transfer transistor TR are insulated gate field effect transistors, and the gate insulating film is made of, for example, silicon oxide (SiO ２ These transistors are configured with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) made of a silicon nitride (Si) film. ３ N ４Alternatively, a metal insulator semiconductor field effect transistor (MISFET) made of a laminated film of a silicon nitride film, a silicon oxide film, or the like may be used.

[0152] Of the pixel transistors included in the pixel circuit 115, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG each function as a switching element, and the amplification transistor AMP functions as an amplification element. That is, the pixel circuit 115 includes field effect transistors with different uses.

[0153] 13, the source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplifier transistor AMP is electrically connected to the floating diffusion region FD and the source region of the switching transistor FDG.

[0154] 13, the source of the selection transistor SEL is electrically connected to the vertical signal line 111 (VSL), the drain region is electrically connected to the source region of the amplification transistor AMP, and the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive lines 110 shown in FIG.

[0155] 13, the reset transistor RST has a source region electrically connected to the drain region of the switching transistor FDG, a drain region electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP, and a gate electrode electrically connected to the reset transistor drive line of the pixel drive line 110 shown in FIG.

[0156] 13, the switching transistor FDG has a source region electrically connected to the floating diffusion region FD and the gate electrode of the amplifier transistor AMP, and a drain region electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the switching transistor FDG is electrically connected to a switching transistor drive line among the pixel drive lines 110 shown in FIG.

[0157] The selection transistor SEL and the switching transistor FDG may be omitted as necessary.

[0158] When the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 111 (VSL). When the switching transistor FDG is omitted, the source region of the reset transistor RST is electrically connected to the gate electrode and floating diffusion region FD of the amplification transistor AMP.

[0159] When the transfer transistor TR shown in FIG. 13 is turned on, it transfers the signal charge generated in the photoelectric conversion unit 124 to the floating diffusion region FD.

[0160] 13 resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd when the reset transistor RST is turned on. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 115.

[0161] 13 generates, as a pixel signal, a signal whose voltage corresponds to the level of the signal charge held in the floating diffusion region FD. The amplification transistor AMP constitutes a source-follower amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated in the photoelectric conversion unit 124. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 105 via the vertical signal line 111 (VSL).

[0162] The switching transistor FDG shown in FIG. 13 controls charge retention by the floating diffusion region FD, and adjusts the multiplication factor of the voltage according to the potential amplified by the amplifier transistor AMP.

[0163] During operation of the solid-state imaging device 1E according to the fifth embodiment, signal charges generated in the photoelectric conversion unit 124 of the pixel 103 are held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the pixel 103. The signal charges held in the floating diffusion region FD are then read out by the pixel circuit 115 and applied to the gate electrode of the amplifier transistor AMP of the pixel circuit 115. A horizontal line selection control signal is applied to the gate electrode of the select transistor SEL of the pixel circuit 115 from the vertical shift register. By setting the selection control signal to a high (H) level, the select transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD, amplified by the amplifier transistor AMP, flows through the vertical signal line 111. Furthermore, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 115 to a high (H) level, the reset transistor RST becomes conductive, resetting the signal charges accumulated in the floating diffusion region FD.

[0164] <<Specific Configuration of Solid-State Imaging Device>> Next, a specific configuration of the solid-state imaging device 1E (semiconductor chip 102) will be described with reference to FIG.

[0165] 14 , the solid-state imaging device 1E (semiconductor chip 102) according to the fifth embodiment has a stacked structure in which a light-collecting layer 50, a second semiconductor layer 60, a third multilayer wiring layer 70, a first multilayer wiring layer 20, an insulating layer 16, a first semiconductor layer 2, an insulating film 24, a second multilayer wiring layer 40, a fourth multilayer wiring layer 80, and a third semiconductor layer 90 are stacked in this order. That is, the solid-state imaging device 1E according to the fifth embodiment has a three-dimensional structure in which the first semiconductor layer 2, the second semiconductor layer 60, and the third semiconductor layer 90 are each stacked in one direction.

[0166] Here, in the fifth embodiment, the semiconductor layer 2 of the first embodiment described above will be referred to as the first semiconductor layer 2. In the fifth embodiment, the first semiconductor layer 2 corresponds to a specific example of the "first semiconductor layer" of the present technology, and the second semiconductor layer 60 corresponds to a specific example of the "second semiconductor layer" of the present technology.

[0167] 14 , the second semiconductor layer 60 has a third surface portion S3 and a fourth surface portion S4 located on opposite sides in the thickness direction (Z direction) of the second semiconductor layer 60. The second semiconductor layer 60 is provided so as to overlap the first semiconductor layer 2 in a planar view. The second semiconductor layer 60 also has an inter-pixel isolation region 61 and the above-mentioned photoelectric conversion region 121 partitioned by the inter-pixel isolation region 61. The photoelectric conversion region 121 is provided for each pixel 103. The inter-pixel isolation region 61 separates the photoelectric conversion regions 121 adjacent to each other in a planar view.

[0168] The photoelectric conversion region 121 includes the above-described photoelectric conversion unit 124, a transfer transistor TR, and a floating diffusion region FD. The transfer transistor TR and the floating diffusion region FD are provided on the third surface S3 side of the semiconductor layer 60.

[0169] Although not shown, the photoelectric conversion unit 124 is composed of, for example, a pn junction photodiode (PD) including a pn junction between a p-type well region provided in the photoelectric conversion region 121 and an n-type semiconductor region buried in this p-type well region. The floating diffusion region FD is composed of, for example, an n-type semiconductor region provided in the p-type well region. The semiconductor layer 60 is composed of, for example, a p-type single crystal silicon substrate as the first conductivity type.

[0170] 14 , the light collection layer 50 is provided on the fourth surface S4 side of the semiconductor layer 60. The light collection layer 50 has a layered structure in which, for example, but not limited to, a color filter 51 and an on-chip lens (microlens) 52 are layered in this order from the fourth surface S4 side of the semiconductor layer 60. Each of the color filter 51 and the on-chip lens 52 is provided for each pixel 103.

[0171] The color filter 51 separates the incident light from the light incident surface side of the solid-state imaging device 1 E into different colors. The on-chip lens 52 condenses the irradiated light and allows the condensed light to be incident on the photoelectric conversion region 121 efficiently.

[0172] 14, the third multilayer wiring layer 70 is provided on the third surface S3 side of the semiconductor layer 60. The third multilayer wiring layer 70 has an insulating film 71, wiring 72, and a bonding metal pad 76, and further has the above-mentioned bonding pad 114.

[0173] The bonding pad 114 overlaps with the bonding opening 63 that reaches the bonding pad 114 from the fourth surface S4 of the semiconductor layer 60 in a plan view. The bonding metal pad 76 faces the surface of the third multilayer wiring layer 70 on the side opposite to the semiconductor layer 60 side.

[0174] 14, the first multilayer wiring layer 20 is provided on the opposite side of the third multilayer wiring layer 70 from the second semiconductor layer 60 side. The first multilayer wiring layer 20 of the fifth embodiment has basically the same configuration as the first multilayer wiring layer 20 of the first embodiment described above, and newly includes a bonding metal pad 26. The bonding metal pad 26 faces the surface of the first multilayer wiring layer 20 on the third multilayer wiring layer 70 side.

[0175] The bonding metal pads 26 of the first multilayer wiring layer 20 and the bonding metal pads 76 of the third multilayer wiring layer 70 are electrically and mechanically connected by metal-to-metal bonding, with their respective bonding surfaces facing each other.

[0176] The bonding metal pads 26 and 76 are bonded together at their respective bonding surfaces by direct bonding. The uppermost insulating layer of the first multilayer wiring layer 20 and the uppermost insulating layer of the third multilayer wiring layer 70 are also bonded together at their respective bonding surfaces by direct bonding. For example, surface activated bonding using plasma bonding can be used as the direct bonding. The bonding metal pads 26 and 76 can be made of the same material as the bonding metal pads 25 and 45 of the fourth embodiment.

[0177] 14 , the insulating layer 16 is provided on the side of the first multilayer wiring layer 20 opposite to the third multilayer wiring layer 70 side. The first semiconductor layer 2 is provided on the side of the insulating layer 16 opposite to the first multilayer wiring layer 20 side. The insulating film 24 is provided on the side of the first semiconductor layer 2 opposite to the insulating layer 16 side, i.e., on the second surface S2 side of the first semiconductor layer 2.

[0178] The laminated structure including the insulating film 24, the first semiconductor layer 2, the insulating layer 16, and the first multilayer wiring layer 20 of the fifth embodiment has the same configuration as the laminated structure including the insulating film 24, the semiconductor layer 2, the insulating layer 16, and the first multilayer wiring layer 20 of the first embodiment described above. The insulating film 24, the first semiconductor layer 2, the insulating layer 16, and the first multilayer wiring layer 20 of the fifth embodiment each have the same configuration as the insulating film 24, the semiconductor layer 2, the insulating layer 16, and the first multilayer wiring layer 20 of the first embodiment described above.

[0179] Similar to the first embodiment described above, an inter-device isolation region 3 and a field insulator 4 are provided on the first surface S1 of the first semiconductor layer 2. A transistor T1 is provided in the device formation region separated by the inter-device isolation region 3. This transistor T1 is a pixel transistor (AMP, SEL, RST, FDG) included in the pixel circuit 115 described above. That is, the pixel transistor T1 included in the pixel circuit 115 is provided in the first semiconductor layer 2. On the other hand, the photoelectric conversion unit 124 is provided in a second semiconductor layer 60 different from the first semiconductor layer 2.

[0180] 14, the second multilayer wiring layer 40 is provided on the side of the insulating film 24 opposite to the first semiconductor layer 2. This second multilayer wiring layer 40 basically has the same configuration as the second multilayer wiring layer 40 of the first embodiment described above, and newly includes a bonding metal pad 43. The bonding metal pad 43 faces the surface of the second multilayer wiring layer 40 opposite to the insulating film 24 side.

[0181] 14 , the fourth multilayer wiring layer 80 is provided on the side opposite to the insulating film 24 side of the second multilayer wiring layer 40. The fourth multilayer wiring layer 80 has an insulating film 81, wiring 82, and a bonding metal pad 83. The bonding metal pad 83 faces the surface of the fourth multilayer wiring layer 80 on the second multilayer wiring layer 40 side.

[0182] The bonding metal pad 83 of the fourth multilayer wiring layer 80 and the bonding metal pad 43 of the second multilayer wiring layer 40 are electrically and mechanically connected by their respective intermetallic bonds, with their respective bonding surfaces facing each other.

[0183] The bonding metal pad 83 and the bonding metal pad 43 are bonded together at their respective bonding surfaces by direct bonding. The uppermost insulating layer of the fourth multilayer wiring layer 80 and the uppermost insulating layer of the second multilayer wiring layer 40 are also bonded together at their respective bonding surfaces by direct bonding. For example, surface activated bonding using plasma bonding can be used as the direct bonding. The bonding metal pad 83 and the bonding metal pad 43 can be made of the same material as the bonding metal pads 25 and 45 of the fourth embodiment.

[0184] 14 , the third semiconductor layer 90 is provided on the side of the fourth multilayer wiring layer 80 opposite to the multilayer wiring layer 40. The third semiconductor layer 90 has a fifth surface S5 and a sixth surface S6 located on opposite sides to each other in the thickness direction (Z direction) of the third semiconductor layer 90.

[0185] The third semiconductor layer 90 is made of, for example, a p-type single crystal silicon substrate. A transistor T2 is provided on a fifth surface S5 of the third semiconductor layer 90. The transistor T2 is, for example, a transistor that constitutes the logic circuit 13 shown in FIG.

[0186] 14 , the solid-state imaging device 1E according to the fifth embodiment, like the first embodiment, includes a through-contact electrode 34 that penetrates the first semiconductor layer 2 in the thickness direction (Z direction) of the first semiconductor layer 2 and is connected to a first conductive portion, a wiring 22a, provided on the outside of the first surface portion S1 of the semiconductor layer 2, and a second conductive portion, a wiring 42a, provided on the outside of the second surface portion S2 of the semiconductor layer 2. Similarly to the first embodiment, the through-contact electrode 34 has a stepped shape that includes a first portion 34a extending from the wiring 42a toward the field insulation portion 4 and a second portion 34b extending from the first portion 34a toward the wiring 22a and having an outer size one step smaller than the first portion 34a in a plan view. Therefore, like the semiconductor device 1A according to the first embodiment, the solid-state imaging device 1E according to the fifth embodiment can further improve the degree of freedom in routing the wiring.

[0187] Furthermore, since the degree of freedom in routing the wiring can be further improved, the wiring can be made finer, and therefore the pixels 103 can be made finer, thereby increasing the number of pixels per unit area, i.e., the resolution. In the fifth embodiment, the wiring 22a has been described as the first conductive portion connected to the through contact electrode 34, but the first conductive portion is not limited to the wiring 22a of the fifth embodiment. For example, the first conductive portion connected to the through contact electrode 34 may be the relay electrode 13b shown in FIG. 6 of the second embodiment, or the via electrode 19b shown in FIG. 9 of the third embodiment.

[0188] 15 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a pixel array portion of a solid-state imaging device according to a sixth embodiment of the present technology. As shown in Fig. 15, a solid-state imaging device 1F according to the sixth embodiment of the present technology has a configuration basically similar to that of the fifth embodiment described above, but the layer stacking order is different.

[0189] 15 , the solid-state imaging device 1F according to the sixth embodiment has a stacked structure in which a light-collecting layer 50, a second semiconductor layer 60, a third multilayer wiring layer 70, a second multilayer wiring layer 40, an insulating film 24, a first semiconductor layer 2, an insulating layer 16, a first multilayer wiring layer 20, a fourth multilayer wiring layer 80, and a fourth semiconductor layer 90 are stacked in this order. The stacked body including the insulating layer 16, the first semiconductor layer 2, and the insulating film 24, and the through-contact electrode 34 provided on this stacked body are upside down compared to the fifth embodiment described above.

[0190] 15 , the bonding metal pads 76 of the third multilayer wiring layer 70 and the bonding metal pads 43 of the second multilayer wiring layer 40 are electrically and mechanically connected by metal-to-metal bonding with their bonding surfaces facing each other. The uppermost insulating layer of the third multilayer wiring layer 70 and the uppermost insulating layer of the second multilayer wiring layer 40 are directly bonded to each other.

[0191] Furthermore, the bonding metal pads 26 of the first multilayer wiring layer 20 and the bonding metal pads 83 of the fourth multilayer wiring layer 80 are electrically and mechanically connected by metal-to-metal bonding with their respective bonding surfaces facing each other. The uppermost insulating layer of the first multilayer wiring layer 20 and the uppermost insulating layer of the fourth multilayer wiring layer 80 are directly bonded to each other.

[0192] 15 , the solid-state imaging device 1F according to the sixth embodiment, like the first embodiment, includes a through-contact electrode 34 that penetrates the first semiconductor layer 2 in the thickness direction (Z direction) of the first semiconductor layer 2 and is connected to a wiring 22a serving as a first conductive portion provided on the outside of the first surface portion S1 of the semiconductor layer 2 and a wiring 42a serving as a second conductive portion provided on the outside of the second surface portion S2 of the semiconductor layer 2. Similarly to the first embodiment, the through-contact electrode 34 has a stepped shape that includes a first portion 34a extending from the wiring 42a toward the field insulation portion 4 and a second portion 34b extending from the first portion 34a toward the wiring 22a and having an outer size one step smaller than that of the first portion 34a in a plan view. Therefore, the solid-state imaging device 1F according to the sixth embodiment also provides the same effects as the solid-state imaging device 1E according to the fifth embodiment. In the sixth embodiment, the wiring 22a has been described as the first conductive part connected to the through contact electrode 34, but the first conductive part is not limited to the wiring 22a in the sixth embodiment. For example, the first conductive part connected to the through contact electrode 34 may be the relay electrode 13b shown in Fig. 6 of the second embodiment described above, or the via electrode 19b shown in Fig. 9 of the third embodiment described above.

[0193] Seventh Embodiment FIG. 16 is a longitudinal sectional view schematically showing a longitudinal sectional structure of a pixel array portion of a solid-state imaging device according to a seventh embodiment of the present technology.

[0194] As shown in Fig. 16 , a solid-state imaging device 1G according to the seventh embodiment of the present technology has basically the same configuration as the above-described fifth embodiment, but differs in the following configuration. That is, as shown in Fig. 16 , a bonding metal pad 24a is provided on the insulating film 24, and the second multilayer wiring layer 40 shown in Fig. 14 is omitted. The bonding metal pad 24a faces the surface of the insulating film 24 opposite to the first semiconductor layer 2 side. The bonding metal pad 24a is provided on the outside of the second surface S2 of the first semiconductor layer 2. The bonding metal pad 24a overlaps the through contact electrode 34 in a plan view and is electrically and mechanically connected to the through contact electrode 34.

[0195] Furthermore, the bonding metal pads 24a of the insulating film 24 and the bonding metal pads 83 of the fourth multilayer wiring layer 80 are electrically and mechanically connected by metal-to-metal bonding with their respective bonding surfaces facing each other. The surface of the insulating film 24 opposite to the first semiconductor layer 2 side is directly bonded to the uppermost insulating layer of the fourth multilayer wiring layer 80.

[0196] In the seventh embodiment, the bonding metal pad 24a corresponds to a specific but not limitative example of a "second conductive portion" of the present technology.

[0197] 16 , the solid-state imaging device 1G according to the seventh embodiment, like the first embodiment, includes a through-contact electrode 34 that penetrates the first semiconductor layer 2 in the thickness direction (Z direction) of the first semiconductor layer 2 and is connected to the wiring 22a serving as a first conductive portion provided on the outside of the first surface portion S1 of the semiconductor layer 2 and the bonding metal pad 24a serving as a second conductive portion provided on the outside of the second surface portion S2 of the semiconductor layer 2. Similarly to the first embodiment, the through-contact electrode 34 has a stepped shape that includes a first portion 34a extending from the bonding metal pad 24a serving as the second conductive portion toward the field insulating portion 4 and a second portion 34b extending from the first portion 34a toward the wiring 22a serving as the first conductive portion and having an outer size one step smaller than that of the first portion 34a in a plan view. Therefore, the solid-state imaging device 1G according to the seventh embodiment also provides the same effects as the semiconductor device 1E according to the fifth embodiment. In the seventh embodiment, the wiring 22a has been described as the first conductive part connected to the through contact electrode 34, but the first conductive part is not limited to the wiring 22a in the seventh embodiment. For example, the first conductive part connected to the through contact electrode 34 may be the relay electrode 13b shown in Fig. 6 of the second embodiment described above, or the via electrode 19b shown in Fig. 9 of the third embodiment described above.

[0198] 17 is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure of a pixel array portion of a solid-state imaging device according to an eighth embodiment of the present technology. As shown in Fig. 17, a solid-state imaging device 1H according to the eighth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1G of the above-described seventh embodiment, but differs in the following configuration.

[0199] 17 , in the eighth embodiment, the stacked body including the first multilayer wiring layer and the insulating film 24 and the through-contact electrode shown in FIG. 16 of the seventh embodiment described above are inverted upside down. In the eighth embodiment, the bonding metal pads 76 of the third multilayer wiring layer 70 and the bonding metal pads 24a of the insulating film 24 are electrically and mechanically connected by metal-to-metal bonding with their bonding surfaces facing each other. The surface of the third multilayer wiring layer 70 opposite the light-collecting layer 60 side and the surface of the insulating film 24 opposite the first semiconductor layer 2 side are directly bonded to each other.

[0200] In the eighth embodiment, the bonding metal pads 26 of the first multilayer wiring layer 20 and the bonding metal pads 83 of the fourth multilayer wiring layer 80 are electrically and mechanically connected by metal-to-metal bonding with their bonding surfaces facing each other. The surface of the first multilayer wiring layer 20 opposite to the first semiconductor layer 2 side and the surface of the fourth multilayer wiring layer 80 opposite to the third semiconductor layer 90 side are bonded by direct bonding.

[0201] 17 , the solid-state imaging device 1H according to the eighth embodiment, like the first embodiment, includes a through-contact electrode 34 that penetrates the first semiconductor layer 2 in the thickness direction (Z direction) of the first semiconductor layer 2 and is connected to the wiring 22a serving as a first conductive portion provided on the outside of the first surface portion S1 of the semiconductor layer 2 and the bonding metal pad 24a serving as a second conductive portion provided on the outside of the second surface portion S2 of the semiconductor layer 2. Similarly to the first embodiment, the through-contact electrode 34 has a stepped shape that includes a first portion 34a extending from the bonding metal pad 24a serving as the second conductive portion toward the field insulating portion 4 and a second portion 34b extending from the first portion 34a toward the wiring 22a serving as the first conductive portion and having an outer size one step smaller than that of the first portion 34a in a plan view. Therefore, the solid-state imaging device 1H according to the eighth embodiment also provides the same effects as the semiconductor device 1E according to the fifth embodiment. In the eighth embodiment, the wiring 22a has been described as the first conductive portion connected to the through contact electrode 34, but the first conductive portion is not limited to the wiring 22a of the seventh embodiment. For example, the first conductive portion connected to the through contact electrode 34 may be the relay electrode 13b shown in Fig. 6 of the second embodiment described above, or the via electrode 19b shown in Fig. 9 of the third embodiment described above.

[0202] Ninth Embodiment <Application Example to Electronic Devices> The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0203] FIG. 18 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a ninth embodiment of the present technology.

[0204] 18, an electronic device 200 includes a solid-state imaging device 201, an optical lens 202, a shutter device 203, a drive circuit 204, and a signal processing circuit 205. This electronic device 200 shows an embodiment in which the solid-state imaging devices 1E to 1H according to the fifth to eighth embodiments of the present technology are used as the solid-state imaging device 201 in an electronic device (for example, a camera).

[0205] The optical lens 202 focuses image light (incident light 206) from the subject on the imaging surface of the solid-state imaging device 201. This causes signal charges to accumulate in the solid-state imaging device 201 for a certain period of time. The shutter device 203 controls the light irradiation period and light blocking period for the solid-state imaging device 201. The drive circuit 204 supplies drive signals that control the transfer operation of the solid-state imaging device 201 and the shutter operation of the shutter device 203. The drive signals (timing signals) supplied from the drive circuit 204 cause charge transfer in the solid-state imaging device 201. The signal processing circuit 205 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 201. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0206] With this configuration, the solid-state imaging device 201 has a high resolution, and therefore the image quality performance of the electronic device 200 of the ninth embodiment can be improved.

[0207] The electronic device 300 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for a mobile device such as a mobile phone or a tablet terminal.

[0208] Furthermore, the present technology can be applied to not only the solid-state imaging device as the image sensor described above, but also to photodetection devices in general, including distance measurement sensors called ToF (Time of Flight) sensors that measure distance. A distance measurement sensor emits light toward an object, detects the light reflected from the surface of the object, and calculates the distance to the object based on the time of flight between when the light is emitted and when the reflected light is received. The pixel transistor described above can also be used in this distance measurement sensor.

[0209] The present technology may also be configured as follows: (1) A semiconductor device comprising: a semiconductor layer having a first surface portion and a second surface portion located opposite to each other in one direction, a field insulation portion provided on the first surface portion in the semiconductor layer, a first conductive portion overlapping the field insulation portion in a plan view and provided on the first surface portion side of the semiconductor layer, a second conductive portion overlapping the field insulation portion in a plan view and provided on the second surface portion side of the semiconductor layer, and a through contact electrode that penetrates the semiconductor layer in the one direction and is connected to the first conductive portion and each of the first conductive portions, wherein the through contact electrode has a stepped shape including a first portion extending from the second conductive portion toward the field insulation portion, and a second portion extending from the first portion toward the second conductive portion and having an outer size in a plan view that is one step smaller than the first portion. (2) The semiconductor device according to (1) above, wherein the first portion of the through contact electrode has an outer size on the field insulation portion side smaller than an outer size on the second conductive portion side in a plan view. (3) The semiconductor device according to (1) or (2) above, wherein the first portion of the through contact electrode terminates in the field insulation portion. (4) The semiconductor device according to any of (1) to (3) above, further comprising: an insulating layer provided on the first surface portion side of the semiconductor layer to cover the field insulation portion, the first conductive portion being a wiring provided on the side of the insulating layer opposite to the semiconductor layer side, and the second portion of the through contact electrode penetrating the insulating layer to be connected to the wiring. (5) The semiconductor device according to (1) or (2) above, further comprising: an insulating layer provided on the first surface portion side of the semiconductor layer to cover the field insulation portion, the first conductive portion being a relay electrode provided between the field insulation portion and the insulating layer, and the second portion of the through contact electrode being connected to the relay electrode by penetrating the field insulation portion. (6) The semiconductor device according to (5), further comprising a wiring provided on the insulating layer on the side opposite to the semiconductor layer side, wherein the relay electrode is connected to the wiring through a via electrode provided in the insulating layer.(7) The semiconductor device according to (1) or (2) above, further comprising an insulating layer provided on the first surface side of the semiconductor layer to cover the field insulating portion, the first conductive portion being a via electrode provided in the insulating layer, and the second portion of the through-contact electrode penetrating the field insulating portion and connected to the via electrode. (8) The semiconductor device according to any of (1) to (7) above, wherein the field insulating portion includes a recessed portion provided in the first surface portion of the semiconductor layer and an isolation insulating film provided in the recessed portion. (9) The semiconductor device according to any of (1) to (7) above, wherein the field insulating portion is an inter-element isolation region that partitions an element formation region on the first surface portion of the semiconductor layer. (10) The semiconductor device according to any one of (1) to (8), comprising: a first semiconductor layer as the semiconductor layer; a second semiconductor layer provided so as to overlap the first semiconductor layer in the one direction; a photoelectric conversion unit provided in the second semiconductor layer; and a pixel circuit that reads out signal charges photoelectrically converted in the photoelectric conversion unit and outputs a pixel signal based on the readout signal charges, wherein a pixel transistor included in the pixel circuit is provided in the first semiconductor layer. (11) A method for manufacturing a semiconductor device, comprising: forming a field insulating portion having an opening where the semiconductor layer is present, on the first surface of a semiconductor layer, of which first surface and second surface are located opposite each other; forming a first conductive portion on the outside of the first surface of the semiconductor layer, the first conductive portion overlapping the opening via an insulating layer in a planar view; selectively removing the semiconductor layer from the second surface side of the semiconductor layer to within the opening, to form a first carved portion connected to the opening and having an outer size larger than the opening in a planar view; selectively removing the insulating layer through the opening, to form a second carved portion reaching the first conductive portion; forming through contact electrodes connected to the first conductive portion in the first carved portion and the second carved portion; and forming a second electrode portion on the outside of the second surface of the semiconductor layer, the second electrode portion overlapping the through contact electrode in a planar view and connected to the through contact electrode.(12) A method for manufacturing a semiconductor device, comprising: forming a field insulating portion having an opening in which the semiconductor layer is present, on the first surface portion of a semiconductor layer, the first surface portion being one of a first surface portion and a second surface portion located on opposite sides of the semiconductor layer; forming a first conductive portion that overlaps the opening in a planar view outside the first surface portion of the semiconductor layer; selectively removing the semiconductor layer from the second surface portion side of the semiconductor layer to within the opening, to form a recessed portion that is connected to the opening and has an outer size in a planar view larger than that of the opening; forming a through contact electrode connected to the first conductive portion in the recessed portion and within the opening; and forming a second electrode portion that overlaps the through contact electrode in a planar view outside the second surface portion of the semiconductor layer and is connected to the through contact electrode. (13) An electronic device comprising: a semiconductor device; an optical lens that focuses image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that processes a signal output from the semiconductor device, wherein the semiconductor device comprises: a semiconductor layer having a first surface portion and a second surface portion located opposite each other in one direction; a field insulating portion provided on the first surface portion of the semiconductor layer; a first conductive portion that overlaps the field insulating portion in a planar view and is provided outside the first surface portion of the semiconductor layer; a second conductive portion that overlaps the field insulating portion in a planar view and is provided outside the second surface portion of the semiconductor layer; and a through contact electrode that penetrates the semiconductor layer along the one direction and is connected to each of the first conductive portion and the second conductive portion, wherein the through contact electrode has a stepped shape including a first portion that extends from the second conductive portion toward the field insulating portion and a second portion that extends from the first portion toward the second conductive portion and has an outer size that is one step smaller than the first portion in a planar view.

[0210] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features.

[0211] REFERENCE SIGNS LIST 1A, 1B, 1C, 1D... semiconductor device, 1E, 1F, 1G, 1H... solid-state imaging device 2... semiconductor layer 2a... protrusion 3... inter-element isolation region 3a... shallow trench 3b... isolation insulating film 4... field insulating portion 4a... shallow trench 4b... isolation insulating film 4x, 4y... opening 11... well region 13a... gate electrode 13b... relay electrode 14a, 14b... main electrode region 16... insulating layer 17... etching stopper film 18... planarizing film 19a, 19b... via electrode 20... first multilayer wiring layer 21... interlayer insulating film 22... wiring layer 22a... wiring (first conductive portion) 24... insulating film 24a, 25, 25a... bonding metal pad 31a... first carved portion 31b... second carved portion 31a １ , 31a ２... dug portion 31b... second dug portion 32, 32B, 32C... contact hole portion 33... isolation insulating film 34... through contact electrode 34a... first portion 34b... second portion 40... second multilayer wiring layer 41... interlayer insulating film 42... wiring layer 42a... wiring (second conductive portion) 45... bonding metal pad 50... light collecting layer 51... color filter 52... on-chip lens 60... second semiconductor layer 61... inter-pixel isolation region 63... bonding opening 70... third multilayer wiring layer 71... insulating film 72... wiring 76... bonding metal pad 80... fourth multilayer wiring layer 81... insulating film 82... wiring 83... bonding metal pad 102... semiconductor chip 102A... pixel array portion 102B... peripheral portion 103... pixel (sensor pixel) 104... vertical drive circuit 105...Column signal processing circuit 106...Horizontal drive circuit 107...Output circuit 108...Control circuit 110...Pixel drive line 111...Vertical signal line 112...Horizontal signal line 113...Logic circuit 114...Bonding pad 115...Pixel circuit 121...Photoelectric conversion region 124...Photoelectric conversion unit 200...Electronic device 201...Solid-state imaging device 202...Optical lens (optical system) 203...Shutter device 204...Drive circuit 205...Signal processing circuit 206...Incident light AMP...Amplifying transistor FD...Floating diffusion region FDG...Switching transistor RST...Reset transistor SEL...Selection transistor S1...First surface portion S2...Second surface portion S3...Third surface portion S4...Fourth surface portion S5...Fifth surface portion S6...Sixth surface portion TR...Transfer transistor T1, T2...transistors

Claims

1. A semiconductor device comprising: a semiconductor layer having a first surface portion and a second surface portion located on opposite sides of each other in one direction; a field insulating portion provided on the first surface portion in the semiconductor layer; a first conductive portion overlapping the field insulating portion in a plan view and provided on the first surface portion side of the semiconductor layer; a second conductive portion overlapping the field insulating portion in a plan view and provided on the second surface portion side of the semiconductor layer; and a through contact electrode penetrating the semiconductor layer in the one direction and connected to each of the first conductive portion and the second conductive portion, wherein the through contact electrode has a stepped shape including a first portion extending from the second conductive portion toward the field insulating portion and a second portion extending from the first portion toward the first conductive portion and having an outer shape size in a plan view smaller than that of the first portion.

2. The semiconductor device according to claim 1, wherein the first portion of the through contact electrode has an outer shape size on the field insulating portion side smaller than an outer shape size on the second conductive portion side in a plan view.

3. The semiconductor device according to claim 1, wherein the first portion of the through contact electrode terminates in the field insulating portion.

4. The semiconductor device according to claim 1, further comprising an insulating layer provided to cover the field insulating portion on the first surface portion side of the semiconductor layer, wherein the first conductive portion is a wiring provided on the side opposite to the semiconductor layer side of the insulating layer, and the second portion of the through contact electrode penetrates the insulating layer and is connected to the wiring.

5. The semiconductor device according to claim 1, further comprising an insulating layer provided to cover the field insulating portion on the first surface portion side of the semiconductor layer, wherein the first conductive portion is an intermediate electrode provided between the field insulating portion and the insulating layer, and the second portion of the through contact electrode penetrates the field insulating portion and is connected to the intermediate electrode.

6. The semiconductor device according to claim 5, further comprising a wiring provided on the side opposite to the semiconductor layer side of the insulating layer, wherein the intermediate electrode is connected to the wiring via a via electrode provided in the insulating layer.

7. The semiconductor device according to claim 1, further comprising an insulating layer provided to cover the field insulating portion on the first surface portion side of the semiconductor layer, wherein the first conductive portion is a via electrode provided in the insulating layer, and the second portion of the through contact electrode penetrates the field insulating portion and is connected to the via electrode.

8. The semiconductor device according to claim 1, wherein the field insulating portion includes a dug-in portion provided on the first surface portion of the semiconductor layer and a separation insulating film provided in the dug-in portion.

9. The semiconductor device according to claim 1, wherein the field insulating portion is an element isolation region that partitions an element formation region on the first surface portion of the semiconductor layer.

10. The semiconductor device according to claim 1, wherein the semiconductor layer is a first semiconductor layer, a second semiconductor layer provided to overlap the first semiconductor layer in the one direction, a photoelectric conversion portion provided in the second semiconductor layer, and a pixel circuit that reads out signal charges photoelectrically converted by the photoelectric conversion portion and outputs a pixel signal based on the read signal charges, and the pixel transistors included in the pixel circuit are provided in the first semiconductor layer.

11. A method of manufacturing a semiconductor device, including: forming a field insulating portion having an opening in which the semiconductor layer exists on the first surface portion of the first and second surface portions located on opposite sides of the semiconductor layer; forming a first conductive portion that overlaps the opening via an insulating layer in plan view outside the first surface portion of the semiconductor layer; selectively removing the semiconductor layer from the second surface portion side of the semiconductor layer across the opening to form a first dug-in portion that is connected to the opening and has an outer shape size larger than that of the opening in plan view; selectively removing the insulating layer through the opening to form a second dug-in portion that reaches the first conductive portion; forming a through contact electrode connected to the first conductive portion in the first dug-in portion and the second dug-in portion; and forming a second electrode portion that overlaps the through contact electrode in plan view and is connected to the through contact electrode outside the second surface portion of the semiconductor layer.

12. A method of manufacturing a semiconductor device, comprising: forming a field insulating portion having an opening through which the semiconductor layer exists on the first surface portion of the semiconductor layer, the first surface portion and the second surface portion being located on opposite sides of the semiconductor layer; forming a first conductive portion that overlaps the opening in plan view outside the first surface portion of the semiconductor layer; selectively removing the semiconductor layer from the second surface portion side of the semiconductor layer across the opening to form a recess that is connected to the opening and has an outer size in plan view larger than that of the opening; forming a through contact electrode connected to the first conductive portion in the recess and the opening; and forming a second electrode portion that overlaps the through contact electrode in plan view and is connected to the through contact electrode outside the second surface portion of the semiconductor layer.

13. An electronic device, comprising: a semiconductor device; an optical lens that forms image light from a subject on an imaging surface of the semiconductor device; and a signal processing circuit that performs signal processing on a signal output from the semiconductor device, wherein the semiconductor device includes: a semiconductor layer having a first surface portion and a second surface portion located on opposite sides in one direction; a field insulating portion provided on the first surface portion in the semiconductor layer; a first conductive portion provided on the first surface portion side of the semiconductor layer and overlapping the field insulating portion in plan view; a second conductive portion provided on the second surface portion side of the semiconductor layer and overlapping the field insulating portion in plan view; and a through contact electrode that penetrates the semiconductor layer along the one direction and is connected to each of the first conductive portion and the second conductive portion, and the through contact electrode has a stepped shape including a first portion extending from the second conductive portion toward the field insulating portion and a second portion extending from the first portion toward the first conductive portion and having an outer size in plan view smaller than that of the first portion by one step.

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