Display substrate and display apparatus

Abstract

A display substrate, comprising: a base substrate (10), a plurality of sub-pixels (PX) located in a display area (A1) and located on a side of the base substrate (10), a plurality of first-type data lines (DL1) located in an effective area (AA) and arranged around a hole area (A2), a plurality of first-type data fan-out lines (411, 412, 413) located in a fan-out area and electrically connected to the plurality of first-type data lines (DL1), and a first data signal capacitance compensation structure located in the fan-out area, at least one insulating layer being provided between the first data signal capacitance compensation structure and the plurality of first-type data fan-out lines (411, 412, 413), and the orthographic projection of the first data signal capacitance compensation structure on the base substrate (10) and the orthographic projection of at least one of the first-type data fan-out lines (411, 412, 413) on the base substrate (10) at least partially overlapping each other.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] On the one hand, this embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a first data signal capacitor compensation structure. The substrate comprises an active area and a first frame area located on at least one side of the active area; the active area comprises: a hole area and a display area located around the hole area; the first frame area comprises: a signal access area and a fan-out area located between the signal access area and the display area. A plurality of sub-pixels are located in the display area and on one side of the substrate. A plurality of data lines are located in the active area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; the plurality of data lines include at least: a plurality of first-class data lines arranged along the hole area. A plurality of data fan-out lines are located in the fan-out area, and the plurality of data fan-out lines include at least: a plurality of first-class data fan-out lines, and the plurality of first-class data fan-out lines are electrically connected to the plurality of first-class data lines. A first data signal capacitor compensation structure is located in the fan-out area and on a side of the multiple data fan-out lines away from the substrate, and at least one insulating layer is provided between the first data signal capacitor compensation structure and the multiple data fan-out lines; an orthographic projection of the first data signal capacitor compensation structure on the substrate at least partially overlaps with an orthographic projection of at least one first-class data fan-out line among the multiple first-class data fan-out lines on the substrate.

[0007] In some exemplary embodiments, the plurality of data lines further include: a plurality of second-class data lines located in the display area and extending along the first direction; the plurality of data fan-out lines further include: a plurality of second-class data fan-out lines, the plurality of second-class data fan-out lines being electrically connected to the plurality of second-class data lines; the number of sub-pixels connected to at least one first-class data line among the plurality of first-class data lines is less than the number of sub-pixels connected to at least one second-class data line among the plurality of second-class data lines.

[0008] In some example embodiments, at least two of the plurality of first-type data fan-out lines have different overlapping areas with the orthographic projection of the first data signal capacitance compensation structure on the substrate.

[0009] In some exemplary embodiments, the first bezel region further includes a bending region, the fan-out region includes a first fan-out region located between the display region and the bending region, and the plurality of first-type data fan-out lines include a plurality of first-type first data fan-out lines located in the first fan-out region. The first data signal capacitance compensation structure includes a first capacitance compensation plate located in the first fan-out region, wherein an orthographic projection of the first capacitance compensation plate on the substrate at least partially overlaps with an orthographic projection of at least one first-type first data fan-out line among the plurality of first-type data fan-out lines on the substrate.

[0010] In some exemplary embodiments, the display substrate further includes: a first peripheral power line located in the first fan-out area; and the first capacitor compensation plate is located on a side of the first peripheral power line away from the display area and is electrically connected to the first peripheral power line.

[0011] In some exemplary embodiments, the first capacitor compensation plate and the first peripheral power line are an integrated structure connected to each other.

[0012] In some exemplary embodiments, the orthographic projection of the first capacitive compensation plate on the substrate is asymmetrical.

[0013] In some exemplary embodiments, the first border area further includes: a bending area, and a circuit setting area located between the bending area and the signal access area. The fan-out area includes: a first fan-out area located between the display area and the bending area, a second fan-out area located between the bending area and the circuit setting area, and a third fan-out area located between the circuit setting area and the signal access area. The plurality of first-class data fan-out lines include: a plurality of first-class third data fan-out lines located in the third fan-out area. The first data signal capacitor compensation structure includes: a second capacitor compensation plate located in the third fan-out area, the second capacitor compensation plate having an orthographic projection on the substrate at least partially overlapping with the orthographic projection on the substrate of at least one of the plurality of first-class third data fan-out lines.

[0014] In some exemplary embodiments, the display substrate further includes: a first peripheral power line located in the first fan-out area, and a first power lead line located in at least the second fan-out area and the third fan-out area; the first power lead line is connected to the first peripheral power line; and the second capacitor compensation plate is electrically connected to the first power lead line via a compensation connection line.

[0015] In some exemplary embodiments, the second capacitive compensation plate has a first edge and a second edge on the orthographic projection of the substrate, the second edge is located on the side of the first edge away from the bending area in the first direction, the first edge is a straight line extending along the second direction, the second edge is a broken line extending along the second direction, and the second direction intersects the first direction.

[0016] In some exemplary embodiments, the active area further includes a wiring area located between the aperture area and the display area. The display substrate further includes at least one first compensation resistor located in the wiring area, and at least one first-category data line among the plurality of first-category data lines is connected in series with the at least one first compensation resistor.

[0017] In some exemplary embodiments, the active area further includes a wiring area located between the aperture area and the display area. The display substrate further includes a second data signal capacitance compensation structure located in the wiring area; at least one insulating layer is disposed between the second data signal capacitance compensation structure and the plurality of first-category data lines; and an orthographic projection of the second data signal capacitance compensation structure onto the substrate partially overlaps with an orthographic projection of at least one of the plurality of first-category data lines onto the substrate.

[0018] In some exemplary embodiments, the second data signal capacitance compensation structure includes: at least one third capacitance compensation plate, the orthographic projection of the third capacitance compensation plate on the substrate partially overlapping with the orthographic projection of at least one first-class data line among the plurality of first-class data lines on the substrate, and the third capacitance compensation plate is located on a side of the at least one first-class data line close to the substrate.

[0019] In some exemplary embodiments, the display substrate further includes: a plurality of gate lines and a gate signal capacitance compensation structure. The plurality of gate lines are located in the active area, the plurality of gate lines being electrically connected to the plurality of sub-pixels, and the plurality of gate lines including at least: a plurality of first-class gate lines arranged along the aperture region. The gate signal capacitance compensation structure is located in the active area, at least one insulating layer being disposed between the gate signal capacitance compensation structure and the plurality of gate lines; the orthographic projection of the gate signal capacitance compensation structure onto the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first-class gate lines onto the substrate.

[0020] In some exemplary embodiments, the first border region is located on one side of the active area along a first direction, and the substrate further includes: a second border region and a third border region located on both sides of the active area along a second direction, wherein the second direction intersects the first direction. The display substrate further includes: a plurality of gate drive circuits. At least one first-type gate line is connected to two gate drive circuits transmitting the same signal, and one of the two gate drive circuits is located in the second border region and the other is located in the third border region.

[0021] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0022] On the other hand, the present embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of gate lines, and a gate signal capacitance compensation structure. The substrate comprises an effective area and a frame area located around the effective area, the effective area comprising: a hole area, a display area located around the hole area, and a winding area located between the hole area and the display area. A plurality of sub-pixels are located in the display area and on one side of the substrate. A plurality of gate lines are located in the effective area, the plurality of gate lines are electrically connected to the plurality of sub-pixels, and the plurality of gate lines comprise at least: a plurality of first-class gate lines arranged along the hole area. The gate signal capacitance compensation structure is located in the winding area, at least one insulating layer is provided between the gate signal capacitance compensation structure and the plurality of gate lines; the orthographic projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first-class gate lines on the substrate.

[0023] In some exemplary embodiments, the plurality of first-category gate lines include at least: a plurality of first-category first scan lines and a plurality of second-category first scan lines, the plurality of first-category first scan lines configured to provide first scan signals to data write transistors in pixel circuits of the plurality of sub-pixels; the plurality of first-category second scan lines configured to provide second scan signals to compensation transistors in pixel circuits of the plurality of sub-pixels; the data write transistors and the compensation transistors being of different transistor types. The gate signal capacitor compensation structure includes at least: a first gate signal capacitor compensation plate, the orthographic projection of the first gate signal capacitor compensation plate on the substrate at least partially overlapping the orthographic projection of at least one first-category second scan line from the plurality of first-category second scan lines on the substrate; the first gate signal capacitor compensation plate being located on a side of the plurality of first-category second scan lines away from the substrate.

[0024] In some exemplary embodiments, in a direction perpendicular to the display substrate, the active area of ​​the display substrate includes at least: a first gate metal layer, a second gate metal layer, a third gate metal layer, and a first source / drain metal layer sequentially disposed on the substrate. The first-type second scan line is located in the first gate metal layer in the winding region, and the first gate signal capacitor compensation plate is located in the third gate metal layer or the first source / drain metal layer.

[0025] In some exemplary embodiments, in a direction perpendicular to the display substrate, the active area of ​​the display substrate includes at least: a bottom blocking metal layer, a first gate metal layer, and a second gate metal layer sequentially disposed on the substrate. The gate signal capacitance compensation structure includes: a second gate signal capacitance compensation plate located in the bottom blocking metal layer, wherein the orthographic projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with the orthographic projections of a plurality of first-class gate lines located in the first gate metal layer on the substrate; or, wherein the orthographic projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with the orthographic projections of a plurality of first-class gate lines located in the first gate metal layer and the second gate metal layer on the substrate.

[0026] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0027] Summary of the Figures

[0028] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0029] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0030] FIG2A is a schematic partial cross-sectional view of a display region of a display substrate according to at least one embodiment of the present disclosure;

[0031] FIG2B is another partial cross-sectional schematic diagram of the display region of the display substrate according to at least one embodiment of the present disclosure;

[0032] FIG3 is a schematic diagram of a first border area according to at least one embodiment of the present disclosure;

[0033] FIG4 is a schematic diagram of local wiring in a first border area according to at least one embodiment of the present disclosure;

[0034] FIG5A is a partial schematic diagram of a first fan-out region according to at least one embodiment of the present disclosure;

[0035] FIG5B is a schematic diagram of the first source / drain metal layer in FIG5A ;

[0036] FIG6 is another schematic diagram of the first border area according to at least one embodiment of the present disclosure;

[0037] FIG7A is a partial schematic diagram of a first border area according to at least one embodiment of the present disclosure;

[0038] FIG7B is a schematic diagram of the second capacitance compensation plate in FIG7A ;

[0039] FIG7C is another schematic diagram of a second capacitance compensation plate according to at least one embodiment of the present disclosure;

[0040] FIG7D is another schematic diagram of a second capacitance compensation plate according to at least one embodiment of the present disclosure;

[0041] FIG7E is another schematic diagram of a second capacitance compensation plate according to at least one embodiment of the present disclosure;

[0042] FIG8 is another partial schematic diagram of the first frame area according to at least one embodiment of the present disclosure;

[0043] FIG9 is another schematic diagram of the first border area according to at least one embodiment of the present disclosure;

[0044] FIG10 is a schematic partial cross-sectional view along the PP' direction in FIG1;

[0045] FIG11 is a schematic diagram of the local structure of area S1 in FIG1 ;

[0046] FIG12 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0047] FIG13 is a schematic diagram of the gate line in FIG12;

[0048] FIG14 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0049] FIG15 is a schematic diagram illustrating the configuration of a gate drive circuit according to at least one embodiment of the present disclosure;

[0050] FIG16 is a schematic partial cross-sectional view along the QQ' direction in FIG13;

[0051] FIG17 is another partial cross-sectional schematic diagram along the QQ' direction in FIG13;

[0052] FIG18 is another partial cross-sectional schematic diagram along the QQ' direction in FIG13;

[0053] FIG19 is another partial cross-sectional schematic diagram along the QQ' direction in FIG13;

[0054] FIG. 20 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0055] Details

[0056] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0057] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0058] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0059] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0060] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0061] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0062] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0063] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0064] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0065] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0066] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0067] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0068] In the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The "shape of A" mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0069] With the development of display technology, the demand for full screen is increasing. In order not to lose the effect of taking pictures, the display substrate needs to be specially designed to meet the purpose of exposing the rear camera. Among them, the display area through-hole (AA hole) design is one of the main solutions for full screen. Since no sub-pixels are set in the display area through-hole, the data line that originally passed through the display area through-hole needs to bypass the display area through-hole to connect the sub-pixels on both sides of the display area through-hole. Therefore, the signal load (loading) of the data line that bypasses the display area through-hole and the signal load of the data line that does not need to bypass the display area through-hole will be different, resulting in poor display (Mura) and other situations. Similarly, the gate line that originally passed through the display area through-hole needs to bypass the display area through-hole to connect the sub-pixels on both sides of the display area through-hole. Therefore, the signal load (loading) of the gate line that bypasses the display area through-hole and the signal load of the gate line that does not need to bypass the display area through-hole will be different, resulting in poor display (Mura) and other situations. In particular, for display substrates designed with ultra-large display area through holes (for example, the through hole diameter can range from 6 mm to 20 mm), a large number of data lines and gate lines need to bypass the display area through holes, and the display defects caused by the difference in routing signal loads are more obvious.

[0070] This embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data fan-out lines, and a first data signal capacitor compensation structure. The substrate comprises an effective area and a first frame area located on at least one side of the effective area; the effective area comprises: a hole area and a display area located around the hole area; the first frame area comprises: a signal access area and a fan-out area located between the signal access area and the display area. The plurality of sub-pixels are located in the display area and on one side of the substrate. The plurality of data lines are located in the effective area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; the plurality of data lines include at least: a plurality of first-class data lines arranged along the hole area. The plurality of data fan-out lines are located in the fan-out area, and the plurality of data fan-out lines include at least: a plurality of first-class data fan-out lines, and the plurality of first-class data fan-out lines are electrically connected to the plurality of first-class data lines. The first data signal capacitor compensation structure is located in the fan-out region and on a side of the multiple data fan-out lines away from the substrate. At least one insulating layer is disposed between the first data signal capacitor compensation structure and the multiple data fan-out lines. The orthographic projection of the first data signal capacitor compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one of the multiple first-category data fan-out lines on the substrate. For example, the orthographic projection of the first data signal capacitor compensation structure on the substrate may partially overlap with the orthographic projection of the multiple first-category data fan-out lines on the substrate.

[0071] The display substrate provided in this embodiment, by setting a first data signal capacitance compensation structure in the fan-out area, can compensate for the capacitance of the first type of data fan-out line to compensate for the signal load of the first type of data line connected to the first type of data fan-out line, thereby improving the display uniformity of the display area.

[0072] In some exemplary embodiments, the plurality of data lines may further include: a plurality of second-class data lines located in the display area and extending along the first direction. The plurality of data fan-out lines may further include: a plurality of second-class data fan-out lines electrically connected to the plurality of second-class data lines. The number of sub-pixels connected to at least one first-class data line is less than the number of sub-pixels connected to at least one second-class data line. This example utilizes a first data signal capacitance compensation structure to perform capacitance compensation on the first-class data fan-out lines, thereby reducing the signal load difference between the first-class data lines and the second-class data lines, thereby improving the display effect of the display area.

[0073] In some exemplary embodiments, the overlap areas of at least two first-type data fan-out lines and the first data signal capacitance compensation structure on the substrate, when projected on the substrate, may be different. In this example, the compensation capacitance for the first-type data lines can be adjusted by adjusting the overlap areas of the first-type data fan-out lines and the first data signal capacitance compensation structure on the substrate.

[0074] In some exemplary embodiments, the first border area may further include: a bending area, and the fan-out area may include: a first fan-out area located between the display area and the bending area. The plurality of first-class data fan-out lines may include: a plurality of first-class first data fan-out lines located in the first fan-out area. The first data signal capacitance compensation structure may include: a first capacitance compensation plate located in the first fan-out area, the orthographic projection of the first capacitance compensation plate on the substrate at least partially overlapping with the orthographic projection of at least one first-class first data fan-out line on the substrate. For example, the orthographic projection of the first capacitance compensation plate on the substrate may partially overlap with the orthographic projection of the plurality of first-class first data fan-out lines on the substrate. This example utilizes the first capacitance compensation plate provided in the first fan-out area to perform capacitance compensation on the first-class data fan-out lines to compensate for the signal load of the first-class data lines to which the first-class data fan-out lines are connected.

[0075] In some exemplary embodiments, the display substrate may further include a first peripheral power line located in the first fan-out region. The first capacitor compensation plate may be located on a side of the first peripheral power line away from the display area and electrically connected to the first peripheral power line. For example, the first capacitor compensation plate and the first peripheral power line may be an integrally connected structure. In this example, by electrically connecting the first capacitor compensation plate to the first peripheral power line, adverse effects caused by the first capacitor compensation plate floating can be avoided.

[0076] In some exemplary embodiments, the first border area may further include a bend area and a circuit configuration area located between the bend area and the signal access area. The fan-out area may include a first fan-out area located between the display area and the bend area, a second fan-out area located between the bend area and the circuit configuration area, and a third fan-out area located between the circuit configuration area and the signal access area. The plurality of first-type data fan-out lines may include a plurality of first-type third data fan-out lines located in the third fan-out area. The first data signal capacitance compensation structure may include a second capacitance compensation plate located in the third fan-out area. The orthographic projection of the second capacitance compensation plate on the substrate at least partially overlaps with the orthographic projection of at least one first-type third data fan-out line on the substrate. For example, the orthographic projection of the second capacitance compensation plate on the substrate may partially overlap with the orthographic projection of the plurality of first-type third data fan-out lines on the substrate. In this example, the second capacitance compensation plate located in the third fan-out area performs capacitance compensation on the first-type data fan-out lines to compensate for the signal load of the first-type data lines to which the first-type data fan-out lines are connected. In other examples, the first data signal capacitance compensation structure may include a first capacitance compensation plate located in the first fan-out region and a second capacitance compensation plate located in the third fan-out region. The first capacitance compensation plate and the second capacitance compensation plate may be used in conjunction to compensate for the signal load of the first-type data line connected to the first-type data fan-out line.

[0077] In some exemplary embodiments, the display substrate may further include: a first power lead located at least in the second fan-out region and the third fan-out region. The first power lead may be connected to the first peripheral power line. The second capacitor compensation plate is electrically connected to the first power lead via a compensation connection line. For example, the compensation connection line may be located on a side of the second capacitor compensation plate close to the substrate. The second capacitor compensation plate and the first power lead may be of the same layer structure, or may be of different layers. This embodiment is not limited to this. In this example, by electrically connecting the second capacitor compensation plate to the first power lead, the adverse effects caused by the floating second capacitor compensation plate can be avoided.

[0078] The solutions of the embodiment are illustrated below through some examples.

[0079] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include: an active area AA, and a frame area BB located around the active area AA. The active area AA may include: a hole area A2, a display area A1 located on at least two sides of the hole area A2, and a winding area A3 located between the hole area A2 and the display area A1. There are no sub-pixels set in the hole area A2, and the hole area A2 is not used for display; in other words, the hole area A2 may be a non-display area. In some examples, there may be no sub-pixels set in the winding area A3, and the winding area A3 may not be used for display. However, this embodiment is not limited to this. In other examples, a separate winding area may not be set, and the wiring in the winding area may be interspersed in the display area.

[0080] In some examples, the orthographic projection of the aperture area A2 may be a circle, while the orthographic projection of the active area AA may be a rounded rectangle. For example, the diameter of the aperture area A2 may range from 6 mm to 20 mm, such as approximately 12 mm. In other examples, the orthographic projection of the aperture area may be a rounded rectangle or an ellipse. In still other examples, the orthographic projection of the active area may be a circle, an ellipse, or a polygon.

[0081] In some examples, the edge of the hole area A2 may be the inner edge of the winding area A3, and the outer edge of the winding area A3 may be connected to the display area A1. For example, the orthographic projection of the hole area A2 may be circular, and the orthographic projection of the winding area A3 may be an annular shape. However, this embodiment is not limited to this. In other examples, the orthographic projection of the winding area may be a rectangular ring or an elliptical ring to match the shape of the hole area.

[0082] In some examples, the hole area A2 may be located in the middle of the active area AA, such that the display area A1 surrounds the hole area A2. In other examples, the hole area A2 may be adjacent to the left or right edge of the active area AA, such that the display area A1 surrounds at least the upper and lower sides of the hole area A2. In other examples, the hole area A2 may be adjacent to the upper or lower edge of the active area AA, such that the display area A1 surrounds at least the left and right sides of the hole area A2.

[0083] In some examples, the border area BB may include: a first border area B1 and a fourth border area B4 located on both sides of the effective area AA along the first direction Y, and a second border area B2 and a third border area B3 located on both sides of the effective area AA along the second direction X. The first border area B1 may be connected to the second border area B2 and the third border area B3, and connected to the display area A1. The fourth border area B4 may be connected to the second border area B2 and the third border area B3, and connected to the display area A1. The first border area B1, the second border area B2, the fourth border area B4 and the third border area B3 may surround the display area A1 after being connected. For example, the first border area B1 may be the lower border area of ​​the display substrate, the second border area B2 may be the left border area of ​​the display substrate, the third border area B3 may be the right border area of ​​the display substrate, and the fourth border area B4 may be the upper border area of ​​the display substrate. However, this embodiment is not limited to this.

[0084] In some examples, the display area A1 may include a plurality of sub-pixels PX forming a pixel array, and the plurality of sub-pixels PX may be configured to display a dynamic image or a still image. For example, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0085] In some examples, the effective area AA may include: a plurality of gate lines (not shown) and a plurality of data lines (Data Line). The orthographic projections of the plurality of gate lines and the plurality of data lines on the substrate may intersect to form a plurality of sub-pixel areas, and a sub-pixel PX is provided in each sub-pixel area. The plurality of data lines are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines may be configured to provide gate drive signals to the plurality of sub-pixels PX. For example, the gate drive signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0086] In some examples, as shown in FIG1 , the plurality of data lines in the active area AA may include: a plurality of first-category data lines DL1 and a plurality of second-category data lines DL2. The plurality of first-category data lines DL1 may be arranged along the aperture area A2, and the plurality of second-category data lines DL2 may extend along the first direction Y and be arranged along the second direction X. In the second direction X, the plurality of second-category data lines DL2 may be divided into two groups, and the plurality of first-category data lines DL1 may be located between the two groups of second-category data lines DL2.

[0087] In some examples, because the aperture area A2 is not provided with sub-pixels, the data lines that originally pass through the aperture area A2 need to bypass the aperture area A2. In this example, the data lines that need to bypass the aperture area A2 are the first-type data lines DL1. The first-type data lines DL1 can bypass the aperture area A2 by being arranged in the winding area A3. Each data line can connect to a column of sub-pixels arranged along the first direction Y. Because the aperture area A2 is not provided with sub-pixels, the number of sub-pixels connected to at least one first-type data line DL1 can be smaller than the number of sub-pixels connected to at least one second-type data line DL2, and the signal load of the at least one first-type data line DL1 can be smaller than the signal load of the at least one second-type data line DL2.

[0088] In some examples, as shown in FIG1 , the first-class data line DL1 may include a first data extension segment DL1-1, a second data extension segment DL1-2, and a data winding segment DL1-3. One end of the data winding segment DL1-3 is connected to the first data extension segment DL1-1, and the other end is connected to the second data extension segment DL1-2. The first data extension segment DL1-1 and the second data extension segment DL1-2 may be substantially straight segments extending along a first direction Y and located at least within the display area A1. The data winding segment DL1-3 may be substantially an arc segment or a broken line segment extending along the first direction Y and located at least within the winding area A3. For example, the first data extension segment DL1-1, the second data extension segment DL1-2, and the data winding segment DL1-3 of the first-type data line DL1 may be interconnected and integrated; alternatively, the first data extension segment DL1-1 and the second data extension segment DL1-2 of the first-type data line DL1 may be located in the same conductive layer, while the conductive layer where the data winding segment DL1-3 is located may be different from the conductive layer where the first data extension segment DL1-1 is located. This embodiment is not limited to this.

[0089] In some examples, the plurality of first-class data lines DL1 may be divided into two groups, where the data winding segments DL1-3 of the first-class data lines DL1 of the first group may be located on one side of the hole area A2 along the second direction X, and the data winding segments DL1-3 of the second group of first-class data lines DL1 may be located on a side of the hole area A2 opposite to the second direction X. The number of first-class data lines DL1 in the first group of first-class data lines DL1 may be the same as or different from the number of first-class data lines DL1 in the second group of first-class data lines DL1.

[0090] In some examples, the first direction Y may be an extension direction of data lines in the display area A1 (e.g., a column direction); the second direction X may be an extension direction of gate lines in the display area A1 (e.g., a row direction). The first direction Y and the second direction X may intersect each other, for example, may be perpendicular to each other.

[0091] In some examples, a pixel unit of the display area A1 may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0092] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.

[0093] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0094] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0095] Figure 2A is a schematic partial cross-sectional view of a display region of a display substrate according to at least one embodiment of the present disclosure. Figure 2A illustrates the structure of a sub-pixel in the display region as an example. In this example, the multiple pixel transistors in the pixel circuit can be of different transistor types, such as low-temperature polysilicon thin-film transistors and oxide thin-film transistors.

[0096] In some examples, as shown in FIG2A , in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels. In other examples, the display substrate may further include: a touch structure layer located on a side of the encapsulation structure layer away from the substrate. For example, the touch structure layer may include at least one touch conductive layer.

[0097] In some examples, FIG2A illustrates an example of a first transistor 21, a second transistor 22, and a capacitor 23 included in each sub-pixel. The first transistor 21 and the second transistor 22 may be of different transistor types. The first transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second transistor 22 may be an oxide thin-film transistor. Alternatively, the first transistor 21 may be an oxide thin-film transistor, and the second transistor 22 may be a low-temperature polysilicon thin-film transistor.

[0098] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarizing layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer; the seventh insulating layer 107 may be located on a side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (also referred to as a second planarizing layer) may be disposed on a side of the second source / drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be further provided on the side of the first semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate and can also increase the adhesion of the film layer in the display substrate to the substrate. In other examples, a bottom shading metal layer (BSM, Bottom Shielding Metal) can also be provided on the side of the buffer layer close to the substrate. The bottom shading metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to avoid external light from affecting the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the seventh insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0099] In some examples, as shown in FIG2A , the first semiconductor layer in the display area may include at least a first active layer 210 of the first transistor 21. The first active layer 210 of the first transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate electrode 213 of the first transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate electrode 213 of the first transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may coincide. The second semiconductor layer may include at least a second active layer 220 of the second transistor 22. The third gate metal layer may include at least a second gate electrode 223 of the second transistor 22. An orthographic projection of the second gate 223 of the second transistor 22 on the substrate 10 may partially overlap with an orthographic projection of the second active layer 220 on the substrate 10 .

[0100] In some examples, as shown in FIG2A , the first source-drain metal layer may include at least: a first source 211 and a first drain 212 of the first transistor 21, and a second source 221 and a second drain 222 of the second transistor 22. The fifth insulating layer 105 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105 and the fourth insulating layer 104 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source electrode 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain electrode 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source electrode 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain electrode 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first transition electrode 241. The first transition electrode 241 can be electrically connected to the first drain electrode 212 of the first transistor 21 of the pixel circuit through a fifth pixel via defined between the sixth and seventh insulating layers 106 and 107. In this example, the first transition electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0101] In some examples, as shown in FIG2A , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the eighth insulating layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0102] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0103] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0104] In some examples, as shown in FIG2A , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141, 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress on the first and third encapsulation layers 141, 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic / inorganic.

[0105] Figure 2B is another partial cross-sectional schematic diagram of the display region of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2B , the circuit structure layer 12 of the display region may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer, disposed on the substrate 10. An eighth insulating layer 108 may be disposed between the second source / drain metal layer and the third source / drain metal layer, and a ninth insulating layer 109 may be disposed on the side of the third source / drain metal layer facing away from the substrate. The ninth insulating layer 109 may be an organic insulating layer, for example, also referred to as a third planarization layer. The third source / drain metal layer may include at least a second transfer electrode 242, which may be connected to a first transfer electrode 241 located in the second source / drain metal layer. In this example, the first transfer electrode 241 and the second transfer electrode 242 may be used to electrically connect the pixel circuit to the first electrode 131 of the light-emitting element. The remaining structure of the display region of the display substrate of this example can be referred to the description of the embodiment shown in Figure 2A , and will not be further described here.

[0106] Figure 3 is a schematic diagram of the first border area of ​​at least one embodiment of the present disclosure. Figure 4 is a schematic diagram of the local routing of the first border area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figures 3 and 4, the first border area B1 may include: a first fan-out area B01, a bending area B02, a second fan-out area B03, a circuit setting area B04, a third fan-out area B05, a first signal access area B06, and a second signal access area B07 arranged in sequence along a side away from the active area AA in the first direction Y. In this example, the fan-out area within the first border area B1 may include: a first fan-out area B01, a second fan-out area B03, and a third fan-out area B05. The first fan-out area B01 is located between the active area AA and the bending area B02, the second fan-out area B03 is located between the bending area B02 and the circuit setting area B04, and the third fan-out area B05 is located between the circuit setting area B04 and the first signal access area B06. The signal access area within the first border area B1 may include: a first signal access area B06 and a second signal access area B07. However, this embodiment is not limited to this. In other examples, the first border area B1 may include: a first fan-out area B01, a bending area B02, a second fan-out area B03, a first signal access area B06, and a second signal access area B07, which are arranged in sequence along a side away from the active area AA in the first direction Y.

[0107] In some examples, the bending region B02 can be configured to bend the second fan-out region B03, the circuit configuration region B04, the third fan-out region B05, the first signal access region B06, and the second signal access region B07 toward the back of the display area A1. Multiple zigzag connecting lines (e.g., including multiple data zigzag lines, a first power zigzag line, and a second power zigzag line) can be disposed within the zigzag region B02 to electrically connect the traces transmitting the same signal within the first fan-out region B01 and the second fan-out region B03.

[0108] In some examples, the circuit arrangement area B04 may be provided with at least a plurality of test circuits arranged along the second direction X. In other examples, a plurality of anti-static circuits may be provided on a side of the plurality of test circuits close to the bending area B02, and a plurality of data selection circuits may be provided on a side of the plurality of test circuits away from the bending area B02. This embodiment is not limited to this.

[0109] In some examples, the first signal access area B06 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to connect to a driver integrated circuit (IC). The second signal access area B07 may be provided with a plurality of second contact pads, and the plurality of second contact pads may be configured to be bound and connected to an external flexible printed circuit (FPC). At least one first contact pad in the first signal access area B06 may be connected to at least one second contact pad in the second signal access area B07 via a lead-out connection line.

[0110] In some examples, as shown in FIG4 , a fan-out area may be provided with multiple data fan-out lines. The multiple data fan-out lines may include: multiple first data fan-out lines 411 located in the first fan-out area B01, multiple second data fan-out lines 412 located in the second fan-out area B03, and multiple third data fan-out lines 413 located in the third fan-out area B05. The multiple first data fan-out lines 411 may be configured to connect multiple data lines within the display area A1 in a fan-out routing manner. For example, the multiple first data fan-out lines 411 may be electrically connected to the multiple data lines in a one-to-one correspondence, or at least one first data fan-out line may be electrically connected to at least two data lines. The multiple first data fan-out lines 411 may be connected to the multiple second data fan-out lines 412 in the second fan-out area B03 via multiple data bend lines 421 provided in the bend area B02. For example, the plurality of first data fan-out lines 411 can be electrically connected to the plurality of data bending lines 421 in a one-to-one correspondence, and the plurality of data bending lines 421 can be electrically connected to the plurality of second data fan-out lines 412 in a one-to-one correspondence. The plurality of second data fan-out lines 412 in the second fan-out area B03 can be connected to circuits within the circuit arrangement area B04 (e.g., including a test circuit, or including a test circuit, an anti-static circuit, and a data selection circuit) to receive data signals or test data signals.

[0111] In some examples, the plurality of third data fan-out lines 413 in the third fan-out region B05 can be connected to the plurality of second data fan-out lines 412 via circuits in the circuit configuration region B04. For example, at least one third data fan-out line 413 can be configured to transmit a data signal to at least two second data fan-out lines 412. The plurality of third data fan-out lines 413 can be connected to the plurality of first contact pads in the first signal access region B06 to receive data signals from the driver integrated circuit.

[0112] In some examples, the plurality of data fan-out lines in the fan-out region can be divided into a plurality of first-category data fan-out lines and a plurality of second-category data fan-out lines according to the type of data lines connected thereto. The plurality of first-category data fan-out lines can be configured to transmit data signals to the plurality of first-category data lines DL1, and the plurality of second-category data fan-out lines can be configured to transmit data signals to the plurality of second-category data lines DL2. For example, the plurality of first-class data fan-out lines may include: a plurality of first-class first data fan-out lines (i.e., a plurality of first data fan-out lines connected to a plurality of first-class data lines DL1), a plurality of first-class second data fan-out lines (i.e., a plurality of second data fan-out lines connected to a plurality of first-class data lines DL1), and a plurality of first-class third data fan-out lines (i.e., a plurality of third data fan-out lines connected to a plurality of first-class data lines DL1); the plurality of second-class data fan-out lines may include: a plurality of second-class first data fan-out lines (i.e., a plurality of first data fan-out lines connected to a plurality of second-class data lines DL2), a plurality of second-class second data fan-out lines (i.e., a plurality of second data fan-out lines connected to a plurality of second-class data lines DL2), and a plurality of second-class third data fan-out lines (i.e., a plurality of third data fan-out lines connected to a plurality of second-class data lines DL2).

[0113] In some examples, the plurality of first data fan-out lines 411 of the first fan-out area B01 may be arranged alternately in the first gate metal layer and the second gate metal layer; the plurality of second data fan-out lines 412 of the second fan-out area B03 may be arranged alternately in the first gate metal layer and the second gate metal layer; and the plurality of third data fan-out lines 413 of the third fan-out area B05 may be arranged alternately in the first gate metal layer and the second gate metal layer. However, this embodiment is not limited to this. In other examples, the plurality of first data fan-out lines may all be located in the first gate metal layer or the second gate metal layer; the plurality of second data fan-out lines may all be located in the first gate metal layer or the second gate metal layer; and the plurality of third data fan-out lines may all be located in the first gate metal layer or the second gate metal layer.

[0114] In some examples, as shown in FIG4 , the first fan-out region B01 may further include a first peripheral power line 311 and second peripheral power lines 321a and 321b. Within the first fan-out region B01, the first peripheral power line 311 may extend at least along the second direction X. The first peripheral power line 311 may be located on a side of the plurality of first data fan-out lines 411 away from the substrate. The orthographic projection of the first peripheral power line 311 on the substrate may partially overlap with the orthographic projections of the plurality of first data fan-out lines 411 on the substrate. For example, the orthographic projection of the first peripheral power line 311 on the substrate may partially overlap with the orthographic projection of each first data fan-out line on the substrate.

[0115] In some examples, the second peripheral power line 321a may be located on a side of the first peripheral power line 311 in the opposite direction of the second direction X, and the second peripheral power line 321b may be located on a side of the first peripheral power line 311 in the second direction X. The second peripheral power line 321a may extend toward the second frame area, and the second peripheral power line 321b may extend toward the third frame area.

[0116] In some examples, the first peripheral power line 311 can be configured to be electrically connected to the first power line of the display area A1, and the second peripheral power lines 321a and 321b can be configured to be electrically connected to the second power line of the display area A1 or the cathode of the light-emitting element. The first voltage signal transmitted by the first power line can be greater than the second voltage signal transmitted by the second power line. For example, the first voltage signal can be a positive voltage signal, and the second voltage signal can be a negative voltage signal.

[0117] In some examples, as shown in FIG4 , the first border area may also be provided with a first power lead 312 and second power lead 322a and 322b. The first power lead 312 may include: a power main body 3120 extending along the second direction X, and a first power connection portion 3121 and a second power connection portion 3122 extending along the first direction Y. The first power connection portion 3121 is connected to one end of the power main body 3120, and the second power connection portion 3122 is connected to the other end of the power main body 3120. The power main body 3120 may be located within the second fan-out area B03, and the orthographic projection of the power main body 3120 on the substrate may overlap with the orthographic projection of the plurality of second data fan-out lines 412 on the substrate. The power main body 3120 may be electrically connected to the first peripheral power line 311 within the first fan-out area B01 via at least one first power bend line in the bend area B02. The first power connection portion 3121 can extend from the second fan-out area B03 toward the second signal access area B07, bypass the first signal access area B06 from one side (e.g., the left side) of the first signal access area B06, and connect to at least one second contact pad within the second signal access area B07. The second power connection portion 3122 can extend from the second fan-out area B03 toward the second signal access area B07, bypass the first signal access area B06 from the other side (e.g., the right side) of the first signal access area B06, and connect to at least one second contact pad within the second signal access area B07. The power supply body 3120, the first power connection portion 3121, and the second power connection portion 3122 can be an interconnected, integral structure.

[0118] In some examples, the second power lead 322a can be located on one side of the first power lead 312 in the opposite direction of the second direction X, and the second power lead 322b can be located on one side of the first power lead 312 in the second direction X. The second power lead 322a can extend from the second fan-out area B03 to the second signal access area B07 and connect to at least one second contact pad in the second signal access area B07. The second power lead 322b can extend from the second fan-out area B03 to the second signal access area B07 and connect to at least one second contact pad in the second signal access area B07. The second power lead 322a can be electrically connected to the second peripheral power line 321a in the first fan-out area B01 via at least one second power bending line in the bending area B02, and the second power lead 322b can be electrically connected to the second peripheral power line 321b in the first fan-out area B01 via at least one second power bending line in the bending area B02.

[0119] In some examples, the first data signal capacitor compensation structure may include: a first capacitor compensation plate 511 located in the first fan-out area B01. The first capacitor compensation plate 511 may be located on a side of the first peripheral power line 311 away from the display area A1. At least one insulating layer is provided between the first capacitor compensation plate 511 and the plurality of first data fan-out lines 411. The orthographic projection of the first capacitor compensation plate 511 on the substrate may partially overlap with the orthographic projection of the plurality of first data fan-out lines 411 on the substrate. The first capacitor compensation plate 511 and the first peripheral power line 311 may be of the same layer structure. However, this embodiment is not limited to this. In other examples, the first capacitor compensation plate and the first peripheral power line may be of different layers.

[0120] Figure 5A is a partial schematic diagram of the first fan-out region of at least one embodiment of the present disclosure. Figure 5B is a schematic diagram of the first source / drain metal layer in Figure 5A. Figure 5A provides an overall schematic diagram of multiple first-type data fan-out lines 411a in the first fan-out region B01. The film layer structure of this example is based on the film layer structure of the embodiment shown in Figure 2A.

[0121] In some examples, as shown in Figures 5A and 5B, the plurality of first-class data fan-out lines 411a may include a first group of first-class data fan-out lines 411a-1 and a second group of first-class data fan-out lines 411a-2. For example, the first-class data lines DL1 connected to the first group of first-class data fan-out lines 411a-1 may be routed from the left side of the aperture area A2, and the first-class data lines DL1 connected to the second group of first-class data fan-out lines 411a-2 may be routed from the right side of the aperture area A2.

[0122] In some examples, multiple first-type first data fan-out lines 411a can be alternately arranged in the first gate metal layer and the second gate metal layer. Adjacent first-type first data fan-out lines 411a can be located in different film layers, and their orthographic projections on the substrate can have no overlap. However, this embodiment is not limited to this. For example, multiple first data fan-out lines can all be located in the first gate metal layer or the second gate metal layer.

[0123] In some examples, the first peripheral power line 311 can be a single-layer routing located in the first source-drain metal layer. The first capacitor compensation plate 511 can be located in the first source-drain metal layer and can be an integrated structure interconnected with the first peripheral power line 311. In other examples, the first peripheral power line 311 can include: a first sub-routing located in the first source-drain metal layer and a second sub-routing located in the second source-drain metal layer, the first sub-routing and the second sub-routing being electrically connected. The second sub-routing can be connected to the first power bending line located in the second source-drain metal layer of the bending area B02, and the first sub-routing can be electrically connected to the first power line of the display area A1. For example, the first power line of the display area A1 can be located in the first source-drain metal layer or the second source-drain metal layer. The first capacitor compensation plate can be an integrated structure interconnected with the first sub-routing located in the first source-drain metal layer, or the first capacitor compensation plate can be connected to the second sub-routing located in the second source-drain metal layer. However, this embodiment is not limited to this. In other examples, the first peripheral power line 311 may be a single-layer trace located in the second source / drain metal layer, and the first capacitor compensation plate 511 may be located in the second source / drain metal layer and electrically connected to the first peripheral power line 311 .

[0124] In some examples, the orthographic projection of the first capacitive compensation plate 511 on the substrate may have a first edge 511-1 and a second edge 511-2. The second edge 511-2 is located on the side of the first edge 511-1 away from the first peripheral power line 311 in the first direction Y. The first edge 511-1 may coincide with the edge of the first peripheral power line 311 away from the display area A1. The first edge 511-1 may be a straight line extending along the second direction X, and the second edge 511-2 may be a zigzag line extending along the second direction X. For example, the second edge 511-2 may be approximately inverted V-shaped. The orthographic projection of the first capacitive compensation plate 511 on the substrate may have an asymmetric shape. However, this embodiment is not limited to this. In other examples, the orthographic projection of the first capacitive compensation plate 511 on the substrate may have other shapes, such as an inverted trapezoid, triangle, or rectangle.

[0125] In some examples, the orthographic projection of the first capacitor compensation plate 511 on the substrate may not overlap with the orthographic projection of the plurality of second-class first data fan-out lines on the substrate. The overlapping areas of at least two first-class first data fan-out lines 411a and the orthographic projection of the first capacitor compensation plate 511 on the substrate may be different. The size of the overlapping area of ​​the first capacitor compensation plate 511 and the plurality of first-class first data fan-out lines 411a on the substrate is related to the signal load required to be compensated for the first-class data lines connected to the first-class first data fan-out lines 411a. For example, the overlapping area of ​​the first capacitor compensation plate 511 and the orthographic projection of the first group of first-class first data fan-out lines 411a-1 on the substrate may gradually decrease along the second direction X; and the overlapping area of ​​the first capacitor compensation plate 511 and the orthographic projection of the second group of first-class first data fan-out lines 411a-2 on the substrate may gradually increase along the second direction X. However, this embodiment is not limited to this. In other examples, the overlapping area between the first capacitor compensation plate and the plurality of first-category first data fan-out lines may be adjusted according to the load size required to be compensated by the plurality of first-category data lines.

[0126] In this example, a first capacitor compensation plate is set in the first fan-out area, which overlaps with the orthographic projection of multiple first-class first data fan-out lines on the substrate. This can compensate for the load of the first-class data lines connected to the first-class first data fan-out lines, so that the signal load of the first-class data lines is roughly the same as the signal load of the second-class data lines, thereby improving the poor display caused by the difference in the signal load of the data lines, thereby ensuring the display effect of the display area.

[0127] FIG6 is another schematic diagram of the first border area of ​​at least one embodiment of the present disclosure. In some examples, as shown in FIG6 , the first data signal capacitance compensation structure may include: a second capacitance compensation plate 512 located in the third fan-out area B05. At least one insulating layer is provided between the second capacitance compensation plate 512 and the plurality of third data fan-out lines 413. For example, the plurality of third data fan-out lines 413 may be alternately arranged in the first gate metal layer and the second gate metal layer, and adjacent third data fan-out lines 413 may be located in different conductive layers, and may not overlap in the orthographic projection on the substrate. The plurality of third data fan-out lines 413 may include a plurality of first-type third data fan-out lines and a plurality of second-type third data fan-out lines.

[0128] In some examples, the second capacitive compensation plate 512 can be located in the first source / drain metal layer, the second source / drain metal layer, or the third source / drain metal layer. The orthographic projection of the second capacitive compensation plate 512 on the substrate can partially overlap with the orthographic projections of the plurality of first-type third data fan-out lines on the substrate. For example, the orthographic projection of each first-type third data fan-out line on the substrate can partially overlap with the orthographic projection of the second capacitive compensation plate 512 on the substrate.

[0129] Figure 7A is a partial schematic diagram of the first border region of at least one embodiment of the present disclosure. Figure 7A illustrates the partial routing structure of the second and third fan-out regions. Figure 7A provides an overall schematic diagram of the multiple second data fan-out lines 412 in the second fan-out region B03 and the multiple third data fan-out lines 413 in the third fan-out region B05. Figure 7B is a schematic diagram of the second capacitor compensation plate in Figure 7A. The membrane layer structure of this example is based on the membrane layer structure of the embodiment shown in Figure 2A.

[0130] In some examples, as shown in Figures 7A and 7B, the plurality of third data fan-out lines 413 may include: a first group of first-category third data fan-out lines 413a-1, a second group of first-category third data fan-out lines 413a-2, a first group of second-category third data fan-out lines 413b-1, and a second group of second-category third data fan-out lines 413b-2. For example, the first group of first-category third data fan-out lines 413a-1 may be configured to provide data signals to the first group of first-category data lines in display area A1, and the second group of first-category third data fan-out lines 413a-2 may be configured to provide data signals to the second group of first-category data lines in display area A1. The first group of second-category third data fan-out lines 413b-1 may be configured to provide data signals to the first group of second-category data lines in display area A1, and the second group of second-category third data fan-out lines 413b-2 may be configured to provide data signals to the second group of second-category data lines in display area A1. The first group of first-category data lines can be configured to route from the left side of aperture area A2, while the second group of first-category data lines can be configured to route from the right side of aperture area A2. The first group of second-category data lines can be located on the side of the first group of first-category data lines closer to the edge of the display area, while the second group of second-category data lines can be located on the side of the second group of first-category data lines closer to the edge of the display area. Within the third fan-out area B05, the first group of second-category third data fan-out lines 413b-1, the first group of first-category third data fan-out lines 413a-1, the second group of first-category third data fan-out lines 413a-2, and the second group of second-category third data fan-out lines 413b-2 can be sequentially arranged along the second direction X.

[0131] In some examples, the plurality of third data fan-out lines 413 may be alternately arranged in the first gate metal layer and the second gate metal layer. However, this embodiment is not limited to this. In other examples, the plurality of third data fan-out lines may all be located in the first gate metal layer or the second gate metal layer.

[0132] In some examples, the test circuit in the circuit setting area B04 can be connected to the multiple second contact pads in the second signal access area B07 through multiple test control lines 62, or connected to a separate test contact pad, or connected to the multiple second contact pads and the separate test contact pad in the second signal access area B07. The multiple test control lines 62 can be located in the first source and drain metal layer. A plurality of third data fan-out lines 413 can be provided with a plurality of control lead-out lines 61 on one side along the second direction X, and the plurality of control lead-out lines 61 can extend to the first signal access area B06 and be connected to the plurality of first contact pads in the first signal access area B06. The plurality of control lead-out lines 61 can be configured to provide drive signals (for example, including clock signals, start signals, etc.) to the multiple gate drive circuits. At least one control lead-out line 61 can be located in the first gate metal layer, or a double-layer routing design of the first gate metal layer and the second gate metal layer can be adopted.

[0133] In some examples, at least one insulating layer is disposed between the second capacitive compensation plate 512 located in the third fan-out region B05 and the plurality of third data fan-out lines 413. The orthographic projection of the second capacitive compensation plate 512 on the substrate may partially overlap with the orthographic projections of the plurality of first-type third data fan-out lines on the substrate. For example, the orthographic projection of the second capacitive compensation plate 512 on the substrate may partially overlap with the orthographic projection of each first-type third data fan-out line on the substrate, but may not overlap with the orthographic projection of the second-type third data fan-out line on the substrate.

[0134] In some examples, as shown in FIG7B , the orthographic projection of the second capacitive compensation plate 512 on the substrate may include a first edge 512-1 and a second edge 512-2. The second edge 512-2 may be located on a side of the first edge 512-1 away from the circuit arrangement area B04 in the first direction Y. The first edge 512-1 may be a straight line extending along the second direction X, and the second edge 512-2 may be a zigzag line extending along the second direction X. For example, the second edge 512-2 may be substantially W-shaped. For example, the second edge 512-2 may include: a first oblique line segment 5131, a first straight line segment 5141, a second oblique line segment 5132, a third oblique line segment 5133, a second straight line segment 5142, and a fourth oblique line segment 5134, which are sequentially connected along the second direction X. The second oblique line segment 5132 and the third oblique line segment 5133 may be connected to form a recessed portion that is recessed toward the first edge 512-1. The first straight line segment 5141 can be located on the side of the first oblique line segment 5131 and the second oblique line segment 5132 in the opposite direction of the first direction Y, and the second straight line segment 5142 can be located on the side of the third oblique line segment 5133 and the fourth oblique line segment 5134 in the opposite direction of the first direction Y.

[0135] In some examples, the overlapping areas of at least two first-class third data fan-out lines and the orthographic projection of the second capacitive compensation plate 512 on the substrate can be different. The size of the overlapping area of ​​the second capacitive compensation plate 512 and the plurality of first-class third data fan-out lines on the substrate is related to the signal load required to be compensated for the first-class data lines connected to the first-class third data fan-out lines. For example, the overlapping area of ​​the orthographic projection of the second capacitive compensation plate 512 and the left half of the first group of first-class third data fan-out lines 413a-1 on the substrate can gradually increase along the second direction X; and the overlapping area of ​​the orthographic projection of the second capacitive compensation plate 512 and the right half of the first group of first-class third data fan-out lines 413a-1 on the substrate can gradually decrease along the second direction X. The overlapping area of ​​the orthographic projection of the second capacitive compensation plate 512 and the left half of the second group of first-type third data fan-out lines 413 a - 2 on the substrate may gradually increase along the second direction X; and the overlapping area of ​​the orthographic projection of the second capacitive compensation plate 512 and the right half of the second group of first-type third data fan-out lines 413 a - 1 on the substrate may gradually decrease along the second direction X. However, this embodiment is not limited to this.

[0136] In this example, by setting a second capacitor compensation plate in the third fan-out area that overlaps with the orthographic projection of multiple first-category third data fan-out lines on the substrate, load compensation can be performed on the first-category data lines connected to the first-category third data fan-out lines, so that the signal load of the first-category data lines and the signal load of the second-category data lines are roughly the same, thereby improving the display defects caused by the difference in the signal loads of the data lines, thereby ensuring the display effect of the display area.

[0137] Figure 7C is another schematic diagram of a second capacitive compensation plate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7C, the second edge 512-2 of the second capacitive compensation plate 512 can be in the form of a broken line extending along the second direction X. The second edge 512-2 can include: a third straight line segment 5143, a fifth oblique line segment 5135, a sixth oblique line segment 5136, and a fourth straight line segment 5144, sequentially connected along the second direction X. The fifth oblique line segment 5135 and the sixth oblique line segment 5136 can be connected to form a recessed portion that is recessed in the first direction Y. For example, the overlapping area of ​​the second capacitive compensation plate 512 and the left half of the first group of first-class third data fan-out lines 413a-1 on the substrate can be substantially the same; and the overlapping area of ​​the second capacitive compensation plate 512 and the right half of the first group of first-class third data fan-out lines 413a-1 on the substrate can gradually decrease along the second direction X. The overlapping area of ​​the orthographic projection of the second capacitor compensation plate 512 and the left half of the second group of first-type third data fan-out lines 413a-2 on the substrate can gradually increase along the second direction X; the overlapping area of ​​the orthographic projection of the second capacitor compensation plate 512 and the right half of the second group of first-type third data fan-out lines 413a-1 on the substrate can be approximately the same.

[0138] Figure 7D is another schematic diagram of a second capacitive compensation plate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7D, the second edge 512-2 of the second capacitive compensation plate 512 can be in the form of a broken line extending along the second direction X. The second edge 512-2 can include a seventh oblique line segment 5137, a fifth straight line segment 5145, and an eighth oblique line segment 5138, which are sequentially connected along the second direction X. The fifth straight line segment 5145 can be located on a side opposite to the seventh oblique line segment 5137 and the eighth oblique line segment 5138 along the first direction Y. For example, the overlapping area of ​​the second capacitive compensation plate 512 and the orthographic projection of the left half of the first group of first-class third data fan-out lines 413a-1 onto the substrate can gradually increase along the second direction X; and the overlapping area of ​​the second capacitive compensation plate 512 and the orthographic projection of the right half of the first group of first-class third data fan-out lines 413a-1 onto the substrate can be substantially the same. The overlapping areas of the second capacitance compensation plate 512 and the left half of the second group of first-type third data fan-out lines 413a-2 on the substrate can be approximately the same; the overlapping areas of the second capacitance compensation plate 512 and the right half of the second group of first-type third data fan-out lines 413a-1 on the substrate can gradually decrease along the second direction X.

[0139] Figure 7E is another schematic diagram of the second capacitor compensation plate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 7E, the second edge 512-2 of the second capacitor compensation plate 512 can be a broken line extending along the second direction X. The second edge 512-2 can include: a ninth oblique line segment 5139 and a tenth oblique line segment 5140 connected in sequence along the second direction X. The ninth oblique line segment 5139 and the tenth oblique line segment 5140 can be connected to form a recessed portion that is recessed in the first direction Y. For example, the overlapping area of ​​the second capacitor compensation plate 512 and the orthographic projection of the first group of first-class third data fan-out lines 413a-1 on the substrate can gradually decrease along the second direction X; the overlapping area of ​​the second capacitor compensation plate 512 and the orthographic projection of the second group of first-class third data fan-out lines 413a-2 on the substrate can gradually increase along the second direction X.

[0140] Figure 8 is another partial schematic diagram of the first border area of ​​at least one embodiment of the present disclosure. Figure 8 illustrates the partial routing of the second fan-out area B03 and the third fan-out area B05. Figure 8 provides an overall schematic diagram of multiple second data fan-out lines 412 and multiple third data fan-out lines 413. In some examples, as shown in Figure 8, the second capacitor compensation plate 512 located in the third fan-out area B05 can be electrically connected to the first power lead 312 through the compensation connection line 45. The first edge of the second capacitor compensation plate 512 can extend along the second direction X and be electrically connected to the compensation connection line 45. The compensation connection line 45 can be located on the side of the second capacitor compensation plate 512 close to the substrate.

[0141] In some examples, the first power lead 312 can be a single-layer trace located in the first source-drain metal layer. The second capacitor compensation plate 512 can be located in the first source-drain metal layer. The compensation connection line 45 can be located in the first gate metal layer or the second gate metal layer. The compensation connection line 45 can extend approximately along the second direction X and be connected to the second power connection portion 3122 of the first power lead 312 to achieve electrical connection between the first power lead 312 and the second capacitor compensation plate 512. The compensation connection line 45 can be located on one side of the multiple control lead lines 61 close to the bending area B02. In other examples, the second capacitor compensation plate 512 can be located in the second source-drain metal layer and connected to the first power lead 312 located in the first source-drain metal layer via a compensation connection line located in the first gate metal layer or the second gate metal layer.

[0142] In other examples, the first power lead 312 may be a single-layer trace located in the second source / drain metal layer. The second capacitor compensation plate 512 may be located in the first source / drain metal layer or the second source / drain metal layer and connected to the first power lead 312 via a compensation connection line located in the first gate metal layer or the second gate metal layer.

[0143] In other examples, the first power lead 312 may be a double-layered routing located in the first source / drain metal layer and the second source / drain metal layer. The second capacitor compensation plate 512 may be located in the first source / drain metal layer or the second source / drain metal layer and electrically connected to the sub-routing located in the first source / drain metal layer or the sub-routing located in the second source / drain metal layer of the first power lead 312 via a compensation connection line located in the first gate metal layer or the second gate metal layer.

[0144] This example avoids the adverse effects of the second capacitor compensation plate floating by electrically connecting the second capacitor compensation plate to the first power lead. The remaining structure of this example can refer to the description of the previous embodiment, so it will not be repeated here.

[0145] Figure 9 is another schematic diagram of the first border region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 9, the first data signal capacitance compensation structure may include: a first capacitance compensation plate 511 located in the first fan-out region B01 and a second capacitance compensation plate 512 located in the third fan-out region B05. The orthographic projection of the first capacitance compensation plate 511 onto the substrate may be as shown in Figure 5A or as shown in any of Figures 7B to 7D. The orthographic projection of the second capacitance compensation plate 512 onto the substrate may be as shown in any of Figures 7B to 7E.

[0146] This example, by providing a first capacitive compensation plate and a second capacitive compensation plate, can perform load compensation for the first-class data lines connected to the first-class data fan-out lines, so that the signal loads of the first-class data lines and the second-class data lines are substantially the same. This can improve display defects caused by the difference in signal loads of the data lines, thereby ensuring the display quality of the display area. The remaining structure of this example can be referred to the description of the previous embodiment, and will not be repeated here.

[0147] In other examples, by adjusting the length of the power main body of the first power lead-out line in the second fan-out area along the first direction, space can be freed up for setting a capacitor compensation plate in the second fan-out area; or, by changing the edge shape of the power main body of the first power lead-out line in the second fan-out area away from the bending area, the overlapping area of ​​the power main body and the multiple second data fan-out lines can be changed, thereby achieving differential capacitance compensation for the multiple first-type second data fan-out lines.

[0148] In other examples, the first capacitor compensation plate located in the first fan-out region may be connected to the second peripheral power line, or may be connected to other traces providing a constant voltage signal.

[0149] In other examples, the second capacitor compensation plate located in the third fan-out region may be connected to the second power lead, or may be connected to other traces providing a constant voltage signal.

[0150] FIG10 is a schematic diagram of a partial cross-section along the P-P' direction in FIG1. ​​The film layer structure of the display substrate of this example takes the film layer structure shown in FIG2B as an example. In some examples, as shown in FIG1 and FIG10, the data winding segments DL1-3 of the plurality of first-class data lines DL1 in the winding area A3 can be alternately arranged in the second source-drain metal layer and the third source-drain metal layer, and adjacent data winding segments DL1-3 can be located in different film layers, and there is no overlap in the orthographic projection of the substrate. For example, the plurality of data winding segments DL1-3 in the winding area A3 may include: a plurality of data winding segments DL1-3a located in the second source-drain metal layer, and a plurality of data winding segments DL1-3b located in the third source-drain metal layer.

[0151] In some examples, a second capacitance compensation structure may be provided in the winding area A3. The second capacitance compensation structure may include third capacitance compensation plates 521 and 522 located in different conductive layers. The orthographic projection of the third capacitance compensation plate 521 on the substrate may at least partially overlap with the orthographic projection of at least one data winding segment DL1-3a located in the second source / drain metal layer. The orthographic projection of the third capacitance compensation plate 522 on the substrate may at least partially overlap with the orthographic projection of at least one data winding segment DL1-3b located in the third source / drain metal layer. For example, the third capacitance compensation plate 521 may be located in the third gate metal layer, and the third capacitance compensation plate 522 may be located in the first source / drain metal layer. At least the seventh insulating layer 107 is provided between the third capacitance compensation plate 521 and the data winding segment DL1-3a located in the second source / drain metal layer. At least the eighth insulating layer 108 and the seventh insulating layer 107 are provided between the third capacitance compensation plate 522 and the data winding segment DL1-3b located in the third source / drain metal layer.

[0152] In some examples, the third capacitance compensation plates 521 and 522 of the winding area A3 can be configured to receive a constant voltage signal, for example, can be connected to a constant voltage signal line (such as a first power line or a second power line). However, this embodiment is not limited to this. In other examples, the wiring located in the third gate metal layer in the winding area A3 and overlapping with the orthographic projection of at least one data winding segment DL1-3a in the substrate can serve as the third capacitance compensation plate 521, and the wiring located in the first source and drain metal layer in the winding area A3 and overlapping with the orthographic projection of at least one data winding segment DL1-3b in the substrate can serve as the third capacitance compensation plate 522.

[0153] In this example, within the winding region, a third capacitor compensation plate located on the third gate metal layer overlaps with a data winding segment located on the second source / drain metal layer to compensate for signal loads on the first type of data lines. Similarly, a third capacitor compensation plate located on the first source / drain metal layer overlaps with a data winding segment located on the third source / drain metal layer to compensate for signal loads on the first type of data lines. This configuration ensures effective signal compensation for different first type data lines.

[0154] In other examples, a first data signal capacitor compensation structure (for example, including: at least one of a first capacitor compensation plate and a second capacitor compensation plate) can be set in the first border area, and a second data signal capacitor compensation structure (for example, including a third capacitor compensation plate) can be set in the winding area to achieve signal load compensation for the first type of data line.

[0155] Figure 11 is a schematic diagram of a partial structure of area S1 in Figure 1. In some examples, as shown in Figures 1 and 11, the winding area A3 may be provided with at least one first compensation resistor 53, and at least one first-class data line DL1 may be connected in series with the at least one first compensation resistor 53. For example, the first compensation resistor 53 may be connected in series between the first data extension segment DL1-1 and the data winding segment DL1-3 of the first-class data line DL1. The first compensation resistor 53 may be a serpentine trace. A serpentine trace is a meandering curve. For example, one end of the trace extends a certain distance in one direction, then bends and twists and extends a certain distance in the opposite direction, then bends and twists again and extends in the same direction, repeating this process several times to form a serpentine trace. In other examples, the first compensation resistor may be connected in series between the second data extension segment and the data winding segment of the first-class data line; alternatively, the data winding segment of the first-class data line may include two sub-segments, and the first compensation resistor may be connected in series between the two sub-segments. This embodiment is not limited to this.

[0156] In this example, the first compensation resistor is set to increase the routing length of the first type of data line, thereby increasing the resistance and compensating for the signal load of the first type of data line.

[0157] In other examples, the resistance of the first-type data lines can be increased by thinning the data winding segments of the first-type data lines. Alternatively, the resistance can be increased by increasing the number of jumpers between the segments of the first-type data lines. Alternatively, the resistance of the first-type data lines can be increased by placing the data winding segments of the first-type data lines in a conductive layer with a higher resistivity.

[0158] In other examples, the resistance of the first-class data lines can be reduced by increasing their line width. Alternatively, the resistance of the first-class data lines can be reduced by configuring the first-class data lines to have two or more layers. Alternatively, the resistance of the first-class data lines can be reduced by configuring the first-class data lines to be in a conductive layer with a lower resistivity.

[0159] The resistance compensation size of the first-class data line in this example can be determined according to the signal load difference between the first-class data line and the second-class data line. By increasing or decreasing the resistance of the first-class data line, the signal load difference between the first-class data line and the second-class data line is reduced, thereby improving the display effect.

[0160] In some examples, at least one second compensation resistor may be provided in the first border area. At least one first-class data fan-out line may be connected in series with at least one second compensation resistor. For example, the second compensation resistor may be provided in the first fan-out area and connected in series with the first-class first data fan-out line. However, this embodiment is not limited to this. For example, the second compensation resistor may be provided in the second fan-out area or the third fan-out area. The resistance compensation method for the first-class data fan-out line in the first border area may refer to the resistance compensation method for the first-class data line, so it will not be described in detail here. In this example, the signal load difference between the first-class data line and the second-class data line is improved by performing resistance compensation on the first-class data fan-out line, thereby improving the display effect.

[0161] FIG12 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. FIG13 is a schematic diagram of the gate lines in FIG12 . In some examples, as shown in FIG12 and FIG13 , the active area AA may be provided with a plurality of gate lines extending along the second direction X. The plurality of gate lines may include: a plurality of first-class gate lines GL1 wound along the aperture area A2, and a plurality of second-class gate lines GL2 located in the display area A1 and extending along the second direction X. The plurality of second-class gate lines GL2 may extend along the second direction X and be arranged along the first direction Y. In the first direction Y, the plurality of second-class gate lines GL2 may be divided into two groups, and the plurality of first-class gate lines GL1 may be located in the middle of the two groups of second-class gate lines GL2.

[0162] In some examples, since the hole area A2 is not provided with sub-pixels, the gate lines that originally passed through the hole area A2 need to bypass the hole area. In this example, the gate lines that need to bypass the hole area A2 are the first-class gate lines GL1. The first-class gate lines GL1 can bypass the hole area A2 by being arranged in the winding area A3. Each gate line can connect a row of sub-pixels arranged along the second direction X. Since the hole area A2 is not provided with sub-pixels, the number of sub-pixels connected to at least one first-class gate line GL1 can be less than the number of sub-pixels connected to at least one second-class gate line GL2. The signal load of at least one first-class gate line GL1 is less than the signal load of at least one second-class gate line GL2.

[0163] In some examples, as shown in FIG13 , the first-class gate line GL1 may include: a first gate extension segment GL1-1, a second gate extension segment GL1-2, and a gate winding segment GL1-3. One end of the gate winding segment GL1-3 is connected to the first gate extension segment GL1-1, and the other end is connected to the second gate extension segment GL1-2. The first gate extension segment GL1-1 and the second gate extension segment GL1-2 may be substantially straight segments extending along the second direction X and may be located at least within the display area A1. The gate winding segment GL1-3 may be substantially an arc segment or a broken line segment extending along the second direction X, and the gate winding segment GL1-3 may be located at least within the winding area A3. For example, the first gate extension segment GL1-1, the second gate extension segment GL1-2, and the gate winding segment GL1-3 of the first-type gate line GL1 may be an interconnected integral structure; or the first gate extension segment GL1-1 and the second gate extension segment GL1-2 may be located in the same conductive layer, while the gate winding segment GL1-3 may be located in a conductive layer different from the conductive layer located in the first gate extension segment GL1-1 and the second gate extension segment GL1-2. This embodiment is not limited to this.

[0164] In some examples, the plurality of first-class gate lines GL1 can be divided into two groups. The gate winding segments GL1-3 in the first group of first-class gate lines can be located on one side of the hole area A2 along the first direction Y, for example, winding from the upper side of the hole area A2; and the gate winding segments GL1-3 in the second group of first-class gate lines can be located on the side of the hole area A2 in the opposite direction of the first direction Y, for example, winding from the lower side of the hole area A2. The number of first-class gate lines GL1 in the first group of first-class gate lines can be different from the number of first-class gate lines GL1 in the second group of first-class gate lines.

[0165] Figure 14 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 14, the pixel circuit of this example may include eight pixel transistors (i.e., a first pixel transistor T1 to an eighth pixel transistor T8) and a storage capacitor Cst. The first pixel transistor T1 may also be referred to as a first reset transistor, the second pixel transistor T2 may also be referred to as a compensation transistor, the third pixel transistor T3 may also be referred to as a drive transistor, the fourth pixel transistor T4 may also be referred to as a data write transistor, the fifth pixel transistor T5 may also be referred to as a first light-emitting control transistor, the sixth pixel transistor T6 may also be referred to as a second light-emitting control transistor, the seventh pixel transistor T7 may also be referred to as a second reset transistor, and the eighth pixel transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0166] In some examples, the first pixel transistor T1 and the third pixel transistor T3 to the eighth pixel transistor T8 may be first-type transistors, such as P-type transistors, and the second pixel transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of pixel transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0167] In some examples, the first type of transistor of the pixel circuit (for example, including the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second pixel transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0168] In some examples, as shown in FIG14 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0169] In some examples, as shown in FIG14 , the gate of the third pixel transistor T3 is electrically connected to the first node N1, the first electrode of the third pixel transistor T3 is electrically connected to the second node N2, and the second electrode of the third pixel transistor T3 is electrically connected to the third node N3. The gate of the fourth pixel transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth pixel transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth pixel transistor T4 is electrically connected to the second node N2. The gate of the second pixel transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second pixel transistor T2 is electrically connected to the third node N3, and the second electrode of the second pixel transistor T2 is electrically connected to the first node N1. The gate of the fifth pixel transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth pixel transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth pixel transistor T5 is electrically connected to the second node N2. The gate of the sixth pixel transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth pixel transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth pixel transistor T6 is electrically connected to the fourth node N4. The gate of the first pixel transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first pixel transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first pixel transistor T1 is electrically connected to the third node N3. The first pixel transistor T1 can be configured to reset the third node N3. The gate of the seventh pixel transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh pixel transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh pixel transistor T7 is electrically connected to the fourth node N4. The seventh pixel transistor T7 can be configured to reset the fourth node N4. The gate of the eighth pixel transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth pixel transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth pixel transistor T8 is electrically connected to the second node N2. The eighth pixel transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0170] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second pixel transistor T2 and the third pixel transistor T3, the second node N2 is the connection point of the fifth pixel transistor T5, the fourth pixel transistor T4, the eighth pixel transistor T8 and the third pixel transistor T3, the third node N3 is the connection point of the first pixel transistor T1, the third pixel transistor T3, the second pixel transistor T2 and the sixth pixel transistor T6, and the fourth node N4 is the connection point of the sixth pixel transistor T6, the seventh pixel transistor T7 and the light-emitting element EL.

[0171] The following describes the working process of the pixel circuit shown in Figure 14. The first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 of the pixel circuit are P-type transistors, and the second pixel transistor T2 is an N-type transistor.

[0172] In some examples, during a frame display period, the operation process of the pixel circuit may include at least: a first stage, a second stage, a third stage, and a fourth stage.

[0173] The first stage is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh pixel transistor T7 and the eighth pixel transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor T2. The eighth pixel transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be provided to the second node N2. The seventh pixel transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be provided to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth pixel transistor T4, the first pixel transistor T1, the fifth pixel transistor T5, and the sixth pixel transistor T6. During this stage, the light-emitting element EL does not emit light.

[0174] The second stage is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first pixel transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor T2. The first pixel transistor T1 and the second pixel transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, turning off the seventh pixel transistor T7, the eighth pixel transistor T8, the fourth pixel transistor T4, the fifth pixel transistor T5, and the sixth pixel transistor T6. During this stage, the light-emitting element EL does not emit light.

[0175] The third stage is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth pixel transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third pixel transistor T3 is turned on. The second pixel transistor T2, the fourth pixel transistor T4, and the third pixel transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third pixel transistor T3, the third node N3, and the turned-on second pixel transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third pixel transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third pixel transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the first pixel transistor T1, the seventh pixel transistor T7, the eighth pixel transistor T8, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected.

[0176] In the fourth stage, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth pixel transistor T5 and the sixth pixel transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second pixel transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth pixel transistor T4, the first pixel transistor T1, the seventh pixel transistor T7, and the eighth pixel transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth pixel transistor T5, the third pixel transistor T3, and the sixth pixel transistor T6, driving the light-emitting element EL to emit light.

[0177] During the driving process of the pixel circuit, the driving current flowing through the third pixel transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third pixel transistor T3 is: I=K×(Vgs-Vth) 2=K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 ;

[0178] Among them, I is the driving current flowing through the third pixel transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third pixel transistor T3, Vth is the threshold voltage of the third pixel transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0179] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third pixel transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third pixel transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0180] In some examples, the plurality of gate lines of the display substrate may include: a plurality of first scan lines, a plurality of second scan lines, a plurality of first reset control lines, a plurality of second reset control lines, and a plurality of light-emitting control lines. The plurality of first-category gate lines may include: a first scan line that needs to bypass the hole area (also referred to as a first-category first scan line), a second scan line that needs to bypass the hole area (also referred to as a first-category second scan line), a first reset control line that needs to bypass the hole area (also referred to as a first-category first reset control line), a second reset control line that needs to bypass the hole area (also referred to as a first-category second reset control line), and a light-emitting control line that needs to bypass the hole area (also referred to as a first-category light-emitting control line).

[0181] In some examples, a compensation simulation comparison is performed by taking a first-class gate line (for example, recorded as a first-class gate line A) whose extension line passes through the center of the hole area and a first-class gate line (for example, recorded as a first-class gate line B) whose extension line is away from the edge of the hole area as an example. During the compensation simulation process, capacitance compensation is performed on the first-class gate lines A and B respectively, so that the product of the resistance and capacitance of the portion of the first-class gate line in the winding area is roughly the same as the product of the resistance and capacitance of the corresponding portion of the second-class gate line. According to the compensation simulation results, it can be seen that the first-class first scan line is most affected by the winding, and capacitance compensation needs to be focused on. Capacitance compensation can be performed on the first-class first scan line alone, or capacitance compensation can be performed on all first-class gate lines. This embodiment is not limited to this.

[0182] Figure 15 is a schematic diagram illustrating the configuration of a gate driver circuit according to at least one embodiment of the present disclosure. In some examples, multiple gate driver circuits may be provided in the border region. These multiple gate driver circuits may include: two first scan driver circuits 21a and 21b, two second scan driver circuits 22a and 22b, two first reset driver circuits 23a and 23b, two second reset driver circuits 24a and 24b, and two light-emitting driver circuits 25a and 25b. The first scan driver circuits 21a and 21b may be configured to provide a first scan signal to multiple rows of pixel circuits in display area A1. The second scan driver circuits 22a and 22b may be configured to provide a second scan signal to multiple rows of pixel circuits in display area A1. The light-emitting driver circuits 25a and 25b may be configured to provide a light-emitting control signal to multiple rows of pixel circuits in display area A1. The first reset driver circuits 23a and 23b may be configured to provide a first reset control signal to multiple rows of pixel circuits in display area A1. The second reset driver circuits 24a and 24b may be configured to provide a second reset control signal to multiple rows of pixel circuits in display area A1. In this example, the first scan signal, the second scan signal, the light-emitting control signal, the first reset control signal, and the second reset control signal can all be driven on both sides, thereby improving the signal load difference between the first type of gate line and the second type of gate line by increasing the driving capability. However, this embodiment is not limited to this. In other examples, the second scan signal and the second reset control signal can be driven on both sides, and the first scan signal, the light-emitting control signal, and the first reset control signal can be driven on one side.

[0183] In some examples, the display area A1 includes M rows of pixel circuits as an example for explanation, where M is a positive integer. The multiple rows of pixel circuits within the display area A1 can be marked as the 1st row to the Mth row in the direction from the fourth border area B4 to the first border area B1. The multiple gate drive circuits may include: a first group of gate drive circuits located in the second border area B2 and a second group of gate drive circuits located in the third border area B3. The first group of gate drive circuits may include the following five gate drive circuits: a first scan drive circuit 21a, a second scan drive circuit 22a, a first reset drive circuit 23a, a second reset drive circuit 24a and a light-emitting drive circuit 25a. For example, within the second border area B2, the first scan drive circuit 21a, the second scan drive circuit 22a, the first reset drive circuit 23a, the second reset drive circuit 24a and the light-emitting drive circuit 25a can be arranged in sequence along the direction away from the display area A1. The second group of gate drive circuits may include the following five gate drive circuits: a first scan drive circuit 21b, a second scan drive circuit 22b, a first reset drive circuit 23b, a second reset drive circuit 24b, and a light-emitting drive circuit 25b. For example, within the third border area B3, the first scan drive circuit 21b, the second scan drive circuit 22b, the first reset drive circuit 23b, the second reset drive circuit 24b, and the light-emitting drive circuit 25b may be arranged sequentially in a direction away from the display area A1. However, this embodiment is not limited to this.

[0184] In some examples, the first scan driving circuits 21a and 21b can each include a plurality of cascaded first scan driving units (e.g., including GP(1) to GP(M)). Each level of the first scan driving unit can be configured to provide a first scan signal to a row of pixel circuits in the display area A1. For example, the first-level first scan driving unit GP(1) can be configured to provide a first scan signal to the first row of pixel circuits in the display area A1; and the M-th level first scan driving unit GP(M) can be configured to provide a first scan signal to the M-th row of pixel circuits in the display area A1.

[0185] In some examples, the second scan driving circuits 22a and 22b can each include a plurality of cascaded second scan driving units (e.g., including GN(1) to GN(M)). Each level of the second scan driving unit can be configured to provide a second scan signal to a row of pixel circuits in the display area A1. However, this embodiment is not limited to this. In other examples, each level of the second scan driving unit can be configured to provide a second scan signal to two adjacent rows of pixel circuits in the display area A1.

[0186] In some examples, the light-emitting driving circuits 25a and 25b can each include a plurality of cascaded light-emitting driving units (e.g., including EM(1) to EM(M)). Each level of light-emitting driving units can be configured to provide a light-emitting control signal to a row of pixel circuits in the display area A1. However, this embodiment is not limited to this. In other examples, each level of light-emitting driving units can be configured to provide a light-emitting control signal to two adjacent rows of pixel circuits in the display area A1.

[0187] In some examples, the first reset driving circuits 23a and 23b can each include a plurality of cascaded first reset driving units (e.g., including RP(1) to RP(M)). Each level of the first reset driving unit can be configured to provide a first reset control signal to a row of pixel circuits in the display area A1. However, this embodiment is not limited to this. In other examples, each level of the first reset driving unit can be configured to provide a first reset control signal to two adjacent rows of pixel circuits in the display area A1.

[0188] In some examples, the second reset driving circuits 24a and 24b can each include a plurality of cascaded second reset driving units (e.g., including RH(1) to RH(M)). Each level of the second reset driving unit can be configured to provide a second reset control signal to a row of pixel circuits in the display area A1. However, this embodiment is not limited to this. In other examples, each level of the second reset driving unit can be configured to provide a second reset control signal to two adjacent rows of pixel circuits in the display area A1.

[0189] This example adopts a bilateral driving design to increase the driving capability of the gate signal and improve the display defects caused by the difference in signal load between the first type of gate lines and the second type of gate lines.

[0190] Figure 16 is a schematic partial cross-sectional view taken along the Q-Q' direction in Figure 13. The film layer structure of the display substrate in this example is exemplified by the film layer structure shown in Figure 2A. In some examples, as shown in Figure 16, the winding area A3 may include: a first routing line 601 located in the first gate metal layer, a second routing line 602 located in the second gate metal layer, a third routing line 603 located in the first source / drain metal layer, and a fourth routing line 604 located in the second source / drain metal layer. The orthographic projections of the first routing line 601 and the third routing line 603 on the substrate may at least partially overlap. The first routing line 601 may include: a gate winding segment of a first-class second scan line. For example, the gate winding segment of the first-class second scan line and the first and second gate extension segments may be located in different conductive layers. For example, the first and second gate extension segments may be located in the third gate metal layer. The third routing line 603 may serve as a first gate signal capacitance compensation plate, providing capacitance compensation for the first-class second scan line by overlapping the orthographic projections of the gate winding segments of the first-class second scan line on the substrate. The third wiring 603 may be a wiring that is independently provided and receives a constant voltage signal; or, the third wiring 603 may be a data winding segment of the first type of data line.

[0191] In some examples, the orthographic projections of the second routing line 602 and the fourth routing line 604 on the substrate may at least partially overlap. The second routing line 602 may include a gate winding segment of a first-category first scan line. The fourth routing line 604 may be provided to provide capacitance compensation for the first-category first scan line by overlapping the orthographic projections of the gate winding segment of the first-category first scan line on the substrate. The fourth routing line 604 may be a separate routing line that receives a constant voltage signal; alternatively, the fourth routing line 604 may be a data winding segment of a first-category data line.

[0192] In this example, the first gate signal capacitance compensation plate is provided on the first source-drain metal layer, so that capacitance compensation can be performed on the first type second scan line.

[0193] FIG17 is another partial cross-sectional schematic diagram along the Q-Q' direction in FIG13 . In some examples, as shown in FIG17 , the first gate signal capacitor compensation plate 541 of the winding area A3 can be located in the third gate metal layer. The orthographic projection of the first gate signal capacitor compensation plate 541 on the substrate can at least partially overlap with the orthographic projection of at least one first trace 601 located in the first gate metal layer on the substrate. For example, the first trace 601 can include at least: a gate winding segment of a first-type second scan line. The first gate signal capacitor compensation plate 541 can be configured to receive a constant voltage signal, for example, to be connected to a first voltage signal.

[0194] In this example, the first gate signal capacitance compensation plate provided on the third gate metal layer can be used to perform capacitance compensation on the first type second scan line.

[0195] In other examples, the orthographic projection of the first gate signal capacitor compensation plate 541 on the substrate may at least partially overlap with the orthographic projections of the plurality of first traces on the substrate. For example, the plurality of first traces may include: a gate winding segment of a first-class second scan line, and a gate winding segment of a first-class first reset control line. For example, the first gate signal capacitor compensation plate 541 may cover the orthographic projections of the gate winding segments of the plurality of first-class second scan lines and the gate winding segments of the plurality of first-class first reset control lines on the substrate in the winding region; the orthographic projection of the first gate signal capacitor compensation plate 541 on the substrate may be annular.

[0196] Figure 18 is another partial cross-sectional schematic diagram along the Q-Q' direction in Figure 13. In some examples, as shown in Figure 18, the display substrate may include at least: a bottom blocking metal layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, sequentially disposed on a substrate. A buffer layer 110 is disposed between the bottom blocking metal layer and the first semiconductor layer. The remaining film layer structure of the display substrate of this example can be referred to the embodiment shown in Figure 2A.

[0197] In some examples, as shown in FIG18 , the display substrate may include a second gate signal capacitor compensation plate 542 located in the winding area A3, wherein an orthographic projection of the second gate signal capacitor compensation plate 542 on the substrate at least partially overlaps an orthographic projection of a plurality of first traces 601 (e.g., gate winding segments including a plurality of first-class second scan lines) located in the first gate metal layer on the substrate. The second gate signal capacitor compensation plate 542 may be located in the bottom shielding metal layer and may be configured to receive a constant voltage signal, such as a first voltage signal.

[0198] In this example, by setting a second gate signal capacitance compensation plate on the bottom shielding metal layer, capacitance compensation can be performed on the first type second scan line. The remaining structure of this example can refer to the description of the above embodiment, so it will not be repeated here.

[0199] FIG19 is another partial cross-sectional schematic diagram along the Q-Q' direction in FIG13 . In some examples, the orthographic projection of the second gate signal capacitor compensation plate 542 located in the bottom blocking metal layer on the substrate may at least partially overlap with the orthographic projection of the multiple first traces 601 located in the first gate metal layer and the multiple first traces 602 located in the second gate metal layer on the substrate. For example, the orthographic projection of the second gate signal capacitor compensation plate 542 located in the bottom blocking metal layer on the substrate may cover the orthographic projection of the multiple first traces 601 located in the first gate metal layer and the multiple first traces 602 located in the second gate metal layer on the substrate. For example, the orthographic projection of the second gate signal capacitor compensation plate 542 on the substrate may be annular.

[0200] In some examples, the plurality of first traces 601 may include: a plurality of gate winding segments of first-type second scan lines, a plurality of gate winding segments of first-type first reset control lines; and the plurality of second traces 602 may include: a plurality of gate winding segments of first-type first scan lines, a plurality of gate winding segments of first-type second reset control lines, and a plurality of gate winding segments of first-type light-emitting control lines. This embodiment is not limited to this.

[0201] This example provides a second gate signal capacitance compensation plate on the bottom shielding metal layer to perform capacitance compensation on the first type of gate lines corresponding to the wiring of the first gate metal layer and the second gate metal layer in the winding area. This example prevents the thin wires of the bottom shielding metal layer from affecting the wiring of the upper conductive layer by providing a large-area second gate metal capacitance compensation plate. The remaining structure of this example can be referred to the description of the previous embodiment, so it will not be repeated here.

[0202] This embodiment also provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of gate lines, and a gate signal capacitance compensation structure. The substrate comprises an effective area and a frame area located around the effective area, the effective area comprising: a hole area, a display area located around the hole area, and a winding area located between the hole area and the display area. A plurality of sub-pixels are located in the display area and on one side of the substrate. A plurality of gate lines are located in the effective area, the plurality of gate lines are electrically connected to the plurality of sub-pixels, and the plurality of gate lines comprise at least: a plurality of first-class gate lines arranged along the hole area. The gate signal capacitance compensation structure is located in the winding area, at least one insulating layer is provided between the gate signal capacitance compensation structure and the plurality of gate lines; the orthographic projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first-class gate lines on the substrate.

[0203] The display substrate provided in this embodiment, by setting a gate signal capacitance compensation structure in the winding area, can compensate the capacitance of the first type of gate lines to compensate for the signal load of the first type of data lines connected to the first type of data fan-out lines, thereby improving the display uniformity of the display area.

[0204] In some exemplary embodiments, the plurality of first-category gate lines include at least: a plurality of first-category first scan lines and a plurality of second-category first scan lines, the plurality of first-category first scan lines configured to provide first scan signals to data write transistors in the pixel circuits of the plurality of sub-pixels; the plurality of first-category second scan lines configured to provide second scan signals to compensation transistors in the pixel circuits of the plurality of sub-pixels; the data write transistors and the compensation transistors being of different transistor types. The gate signal capacitor compensation structure includes at least: a first gate signal capacitor compensation plate, the orthographic projection of the first gate signal capacitor compensation plate on the substrate at least partially overlapping the orthographic projection of at least one first-category second scan line on the substrate; the first gate signal capacitor compensation plate being located on a side of the plurality of first-category second scan lines away from the substrate. In some examples, in a direction perpendicular to the display substrate, the active area of ​​the display substrate includes at least: a first gate metal layer, a second gate metal layer, a third gate metal layer, and a first source / drain metal layer sequentially disposed on the substrate. The first type second scan line is located in the first gate metal layer in the winding area, and the first gate signal capacitor compensation plate is located in the third gate metal layer or the first source and drain metal layer.

[0205] In some exemplary embodiments, in a direction perpendicular to the display substrate, the active area of ​​the display substrate includes at least: a bottom blocking metal layer, a first gate metal layer, and a second gate metal layer sequentially disposed on the substrate. The gate signal capacitance compensation structure includes: a second gate signal capacitance compensation plate located in the bottom blocking metal layer, wherein the orthographic projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with the orthographic projections of a plurality of first-class gate lines located in the first gate metal layer on the substrate; or, wherein the orthographic projection of the second gate signal capacitance compensation plate on the substrate at least partially overlaps with the orthographic projections of a plurality of first-class gate lines located in the first gate metal layer and the second gate metal layer on the substrate.

[0206] The rest of the description of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be repeated here.

[0207] In other examples, the gate signal capacitance compensation structure can be set in a border area (for example, including at least one of the second border area and the third border area), and the gate signal capacitance compensation structure is arranged in the border area and overlaps with the peripheral routing connected to the first type of gate line to achieve capacitance compensation for the first type of gate line.

[0208] Figure 20 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 20 , the display panel 910 may be an OLED display panel. The display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited to this.

[0209] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example" or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0210] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, comprising: A substrate comprising an active area and a first frame area located on at least one side of the active area; The effective area includes: a hole area and a display area located around the hole area; the first frame area includes: a signal access area and a fan-out area located between the signal access area and the display area; a plurality of sub-pixels located in the display area and on one side of the substrate; A plurality of data lines are located in the active area, and the plurality of data lines are electrically connected to the plurality of sub-pixels; the plurality of data lines at least include: a plurality of first-type data lines arranged along the hole area; a plurality of data fan-out lines located in the fan-out area, the plurality of data fan-out lines comprising at least: a plurality of first-category data fan-out lines, the plurality of first-category data fan-out lines being electrically connected to the plurality of first-category data lines; A first data signal capacitor compensation structure is located in the fan-out area and on a side of the multiple data fan-out lines away from the substrate, at least one insulating layer is provided between the first data signal capacitor compensation structure and the multiple data fan-out lines; an orthographic projection of the first data signal capacitor compensation structure on the substrate at least partially overlaps with an orthographic projection of at least one first-class data fan-out line among the multiple first-class data fan-out lines on the substrate.

2. The display substrate according to claim 1, wherein The plurality of data lines further include: a plurality of second-type data lines located in the display area and extending along the first direction; The plurality of data fan-out lines further include: a plurality of second-type data fan-out lines, the plurality of second-type data fan-out lines being electrically connected to the plurality of second-type data lines; The number of sub-pixels connected to at least one first-type data line among the plurality of first-type data lines is smaller than the number of sub-pixels connected to at least one second-type data line among the plurality of second-type data lines.

3. The display substrate according to claim 1, wherein At least two of the plurality of first-type data fan-out lines have different overlapping areas with the orthographic projection of the first data signal capacitance compensation structure on the substrate.

4. The display substrate according to claim 1, wherein The first frame area further includes: a bending area, the fan-out area includes: a first fan-out area located between the display area and the bending area; the plurality of first-type data fan-out lines include: a plurality of first-type first data fan-out lines located in the first fan-out area; The first data signal capacitance compensation structure includes: a first capacitance compensation plate located in the first fan-out area, the first capacitance compensation plate having an orthographic projection on the substrate at least partially overlapping with an orthographic projection on the substrate of at least one first-type first data fan-out line among the plurality of first-type first data fan-out lines.

5. The display substrate according to claim 4, further comprising: a first peripheral power line located in the first fan-out area; The first capacitor compensation plate is located on a side of the first peripheral power line away from the display area and is electrically connected to the first peripheral power line.

6. The display substrate according to claim 5, wherein: The first capacitor compensation plate and the first peripheral power line are an integrated structure connected to each other.

7. The display substrate according to claim 4, wherein: The orthographic projection of the first capacitor compensation plate on the substrate is an asymmetric shape.

8. The display substrate according to any one of claims 1 to 7, wherein: The first frame area further includes: a bending area, and a circuit arrangement area located between the bending area and the signal access area; The fan-out area includes: a first fan-out area located between the display area and the bending area, a a second fan-out area between the bending area and the circuit setting area, and a third fan-out area between the circuit setting area and the signal access area; The plurality of first-category data fan-out lines include: a plurality of first-category third data fan-out lines located in the third fan-out area; The first data signal capacitance compensation structure includes: a second capacitance compensation plate located in the third fan-out area, wherein an orthographic projection of the second capacitance compensation plate on the substrate at least partially overlaps with an orthographic projection of at least one first-type third data fan-out line among the plurality of first-type third data fan-out lines on the substrate.

9. The display substrate according to claim 8, further comprising: A first peripheral power line located in the first fan-out area, and a first power lead line located at least in the second fan-out area and the third fan-out area; The first power lead is connected to the first peripheral power line; the second capacitor compensation plate is electrically connected to the first power lead through a compensation connection line.

10. The display substrate according to claim 8, wherein The second capacitor compensation plate has a first edge and a second edge in the positive projection of the substrate, the second edge is located on the side of the first edge away from the bending area in the first direction, the first edge is a straight line extending along the second direction, and the second edge is a broken line extending along the second direction, and the second direction intersects with the first direction.

11. The display substrate according to claim 1, wherein: The effective area further includes: a winding area located between the hole area and the display area; The display substrate further includes: at least one first compensation resistor located in the winding area, and at least one first-type data line among the plurality of first-type data lines is connected in series with the at least one first compensation resistor.

12. The display substrate according to claim 1, wherein The effective area further includes: a winding area located between the hole area and the display area; The display substrate also includes: a second data signal capacitor compensation structure located in the winding area; at least one insulating layer is arranged between the second data signal capacitor compensation structure and the multiple first-class data lines; the second data signal capacitor compensation structure has an orthographic projection on the substrate that overlaps with the orthographic projection of at least one first-class data line among the multiple first-class data lines on the substrate.

13. The display substrate according to claim 12, wherein: The second data signal capacitance compensation structure includes: at least one third capacitance compensation plate, the orthographic projection of the third capacitance compensation plate on the substrate overlaps with the orthographic projection of at least one first-class data line among the multiple first-class data lines on the substrate, and the third capacitance compensation plate is located on a side of the at least one first-class data line close to the substrate.

14. The display substrate according to claim 1, further comprising: A plurality of gate lines are located in the active area, the plurality of gate lines are electrically connected to the plurality of sub-pixels, and the plurality of gate lines at least include: a plurality of first-type gate lines arranged along the hole area; A gate signal capacitance compensation structure is located in the effective area, and at least one insulating layer is arranged between the gate signal capacitance compensation structure and the multiple gate lines; the orthographic projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one first-class gate line among the multiple first-class gate lines on the substrate.

15. The display substrate according to claim 14, wherein: The first frame region is located on one side of the active region along a first direction, and the substrate further includes: a second frame region and a third frame region located on both sides of the active region along a second direction; the second direction intersects the first direction; The display substrate further includes: a plurality of gate driving circuits; The at least one first type gate line is connected to two gate driving circuits that transmit the same signal, and the two gate driving circuits One of the driving circuits is located in the second frame area, and the other is located in the third frame area. 16 . A display device comprising the display substrate according to claim 1 .

17. A display substrate, comprising: A substrate comprising an active area and a frame area surrounding the active area, wherein the active area comprises a hole area, a display area surrounding the hole area, and a winding area between the hole area and the display area; a plurality of sub-pixels located in the display area and on one side of the substrate; A plurality of gate lines are located in the active area, the plurality of gate lines are electrically connected to the plurality of sub-pixels, and the plurality of gate lines at least include: a plurality of first-type gate lines arranged along the hole area; A gate signal capacitance compensation structure is located in the winding area, and at least one insulating layer is arranged between the gate signal capacitance compensation structure and the multiple gate lines; the orthographic projection of the gate signal capacitance compensation structure on the substrate at least partially overlaps with the orthographic projection of at least one first-class gate line among the multiple first-class gate lines on the substrate.

18. The display substrate according to claim 17, wherein: The plurality of first-category gate lines at least include: a plurality of first-category first scan lines and a plurality of first-category second scan lines, the plurality of first-category first scan lines being configured to provide a first scan signal to a data write transistor of a pixel circuit of the plurality of sub-pixels; the plurality of first-category second scan lines being configured to provide a second scan signal to a compensation transistor of a pixel circuit of the plurality of sub-pixels; the data write transistor and the compensation transistor being of different transistor types; The gate signal capacitor compensation structure includes at least: a first gate signal capacitor compensation plate, the orthographic projection of the first gate signal capacitor compensation plate on the substrate at least partially overlapping with the orthographic projection of at least one first-category second scan line among the multiple first-category second scan lines on the substrate; the first gate signal capacitor compensation plate is located on a side of the multiple first-category second scan lines away from the substrate.

19. The display substrate according to claim 18, wherein: In a direction perpendicular to the display substrate, the active area of ​​the display substrate at least includes: a first gate metal layer, a second gate metal layer, a third gate metal layer and a first source-drain metal layer sequentially arranged on the substrate; The first type second scan line is located in the first gate metal layer in the winding area, and the first gate signal capacitor compensation plate is located in the third gate metal layer or the first source and drain metal layer.

20. The display substrate according to claim 17, wherein In a direction perpendicular to the display substrate, the active area of ​​the display substrate at least includes: a bottom blocking metal layer, a first gate metal layer, and a second gate metal layer sequentially arranged on the substrate; The gate signal capacitor compensation structure includes: a second gate signal capacitor compensation plate located in the bottom blocking metal layer, the orthographic projection of the second gate signal capacitor compensation plate on the substrate at least partially overlapping with the orthographic projection of multiple first-class gate lines located in the first gate metal layer on the substrate; or, the orthographic projection of the second gate signal capacitor compensation plate on the substrate at least partially overlapping with the orthographic projection of multiple first-class gate lines located in the first gate metal layer and the second gate metal layer on the substrate.

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