Display panel and driving method therefor, and display apparatus

Abstract

A display panel and a driving method therefor, and a display apparatus, which belong to the technical field of display. The display panel comprises: a timing controller, a gate driving circuit, a source driving circuit and a subpixel array, wherein the timing controller is configured to provide a frame start signal and a plurality of clock signals for the gate driving circuit; the gate driving circuit is configured to provide a plurality of gate driving signals for the subpixel array on the basis of the frame start signal and the plurality of clock signals, such that the duration in which two adjacent rows of subpixels are in a turned-on state at the same time is greater than or equal to twice a unit scanning time; the source driving circuit is configured to provide data signals for the subpixels in the turned-on state; and the timing controller is configured in a way that the duration of the active level of the clock signals provided to clock signal lines corresponding to subpixel rows where real data is written is longer than the duration of the active level of the clock signals provided to clock signal lines corresponding to subpixel rows where interpolated data is written.

Description

Display panel and its driving method, display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and its driving method, and a display device. Background Technology

[0002] In related technologies, a shift register unit in the gate drive circuit provides a gate scan signal for only one gate line. However, as display panel sizes continue to increase—from 65 inches and 75 inches to 98 inches and 110 inches—resolution also increases, from FHD and UHD to 8K products, and refresh rates rise from 60Hz to 120Hz. This significantly increases the design complexity of the products, especially since the pixel charging rate cannot be guaranteed, thus affecting display quality. For example, in a 110-inch, 8K, 120Hz product, the charging time for each row of pixels is only 1.85µs, which fails to meet design requirements for charging time and rate.

[0003] Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a display panel, including a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array includes a plurality of sub-pixels arranged in an N*M array, where N and M are both integers greater than 1;

[0005] The timing controller is configured to provide a frame start signal and multiple clock signals to the gate driving circuit; the gate driving circuit is configured to provide multiple gate driving signals to the sub-pixel array based on the frame start signal and the multiple clock signals, and to scan the sub-pixel array row by row using the multiple gate driving signals to turn on each scanned row of sub-pixels, such that the duration for which two adjacent rows of sub-pixels are simultaneously in the turned-on state is greater than or equal to twice the unit scan time, where the unit scan time is the time required to scan one row of sub-pixels; the source driving circuit is configured to provide data signals to the sub-pixels in the turned-on state; wherein...

[0006] The gate driving circuit includes N shift register units that are respectively connected to N rows of sub-pixels of the sub-pixel array, and each shift register unit is connected to at least one clock signal line for transmitting clock signals;

[0007] The timing controller is configured such that the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing real data is greater than the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing interpolated data.

[0008] In some embodiments, subpixel rows in which real data is written and subpixel rows in which interpolated data is written are alternately set.

[0009] In some embodiments, the N shift register units include a first-stage shift register unit connected to a first row of sub-pixels in the sub-pixel array; the plurality of clock signals include a first clock signal for driving the first-stage shift register unit to output a gate drive signal;

[0010] The rising edge of the frame start signal is earlier than the rising edge of the first clock signal, and the falling edge of the frame start signal is no later than the falling edge of the first clock signal. The phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

[0011] In some embodiments, the first-stage shift register unit to the p-th-th-stage shift register unit among the N shift register units are connected to the frame start signal; the plurality of clock signals further include a p-th clock signal for driving the p-th-th-stage shift register unit to output a gate drive signal;

[0012] The duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%, and the phase difference and the duty cycle are configured such that the falling edge of the frame start signal is aligned with the rising edge of the p-th clock signal, where p is an integer greater than 1.

[0013] In some embodiments, the phase difference between the rising edges of any two adjacent clock signals in the plurality of clock signals is the unit scan time, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%.

[0014] In some embodiments, the period during which each row of subpixels is in the on state includes a charging period and a pre-charging period preceding the charging period, wherein the duration of the charging period is equal to twice the unit scan time, and the duration of the pre-charging period is greater than or equal to the unit scan time.

[0015] In some embodiments, the gate driving circuit includes m gate driving sub-circuits, and the gate driving sub-circuit includes 4n shift register units, where 1≤m≤6 and 1≤n≤4; m and n are both integers.

[0016] The gate drive sub-circuit includes a first shift register group and a second shift register group; one of the first shift register group and the second shift register group includes each odd-numbered shift register unit in 4n shift register units, and the other includes each even-numbered shift register unit.

[0017] Each of the 4n adjacent shift register units is connected to one of the 4n clock signal lines, and the i-th shift register unit is connected to the same clock signal line as the (i+4n)-th shift register; i ranges from 1 to N-4n.

[0018] In some embodiments, the gate driving circuit includes a gate driving sub-circuit, and the gate driving sub-circuit includes eight shift register units;

[0019] The signal input terminals of the first to fourth shift register units respond to the frame start signal; the signal output terminal of the a-th shift register unit is connected to the signal input terminal of the (a+4)-th shift register unit; the frame start signal terminal STV0 of the b-th shift register unit is connected to the signal output terminal of the (b+4)-th shift register unit; 1≤a≤4, 1≤b≤4.

[0020] In some embodiments, the gate driving circuit includes a gate driving sub-circuit, which includes 12 of the shift register units;

[0021] The signal input terminals of the 1st to 6th shift register units respond to the frame start signal; the signal output terminal of the ath shift register unit is connected to the signal input terminal of the (a+6th)th shift register unit; the frame start signal terminal STV0 of the bth shift register unit is connected to the signal output terminal of the (b+6th)th shift register unit; 1≤a≤6, 1≤b≤6.

[0022] In some embodiments, the shift register unit includes:

[0023] The input circuit is configured to transmit a first-level signal to the pull-up node under the control of the first input signal;

[0024] The first reset circuit is configured to transmit a second-level signal to the pull-up node under the control of the second input signal;

[0025] The first pull-down circuit is configured to transmit the second level signal to the pull-down node under the control of the third input signal;

[0026] The second pull-down circuit is configured to transmit the second level signal to the pull-up node under the control of the pull-down node voltage;

[0027] The first pull-down control circuit is configured to transmit the second level signal to the pull-down control node and the pull-down node under the control of the pull-up node voltage;

[0028] The second pull-down control circuit is configured to transmit the power signal to the pull-down node and the pull-down control node under the control of the power signal;

[0029] The second reset circuit is configured to reset the pull-up node under the control of a reset signal;

[0030] The third pull-down circuit is configured to transmit the second level signal to the cascade terminal under the control of the pull-down node voltage;

[0031] The fourth pull-down circuit is configured to transmit a third-level signal to the signal output terminal under the control of the pull-down node;

[0032] The output circuit is configured to transmit the clock signal to the signal output terminal under the control of the pull-up node voltage;

[0033] The cascaded circuit is configured to transmit the clock signal to the cascaded terminal under the control of the pull-up node voltage.

[0034] In some embodiments, the power signal includes a first power signal and a second power signal; the first power signal and the second power signal are signals with the same frequency but opposite direction.

[0035] In some embodiments, the input circuit includes a first transistor; the control electrode of the first transistor is connected to a first signal input terminal, the first electrode is connected to a first level signal terminal, and the second electrode is connected to the pull-up node.

[0036] In some embodiments, the first reset circuit includes a second transistor; the control electrode of the second transistor is connected to a second signal input terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to a second level signal terminal.

[0037] In some embodiments, the drop-down node includes a first drop-down node, and the drop-down control node includes a first drop-down control node;

[0038] The first pull-down control circuit includes: a seventh transistor and an eighth transistor;

[0039] The control electrode of the seventh transistor is connected to the pull-up node, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal; the control electrode of the eighth transistor is connected to the pull-up node, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal.

[0040] The second pull-down control circuit includes: a ninth transistor and a tenth transistor;

[0041] The control electrode and the first electrode of the ninth transistor are both connected to the first power signal terminal, and the second electrode is connected to the first pull-down control node; the control electrode of the tenth transistor is connected to the first pull-down control node, the first electrode is connected to the first power signal terminal, and the second electrode is connected to the first pull-down node.

[0042] In some embodiments, the drop-down node further includes a second drop-down node, and the drop-down control node further includes a second drop-down node;

[0043] The first pull-down control circuit also includes: an eleventh transistor and a twelfth transistor;

[0044] The control electrode of the eleventh transistor is connected to the pull-up node, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal; the control electrode of the twelfth transistor is connected to the pull-up node, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal.

[0045] The second pull-down control circuit also includes: a thirteenth transistor and a fourteenth transistor;

[0046] The control electrode and the first electrode of the thirteenth transistor are both connected to the second power signal terminal, and the second electrode is connected to the second pull-down control node; the control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode is connected to the second power signal terminal, and the second electrode is connected to the second pull-down node.

[0047] In some embodiments, the drop-down node includes a first drop-down node;

[0048] The first pull-down circuit includes a fourth transistor; the control electrode of the fourth transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal.

[0049] The second pull-down circuit includes a sixth transistor; the control electrode of the sixth transistor is connected to the first pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal.

[0050] The third pull-down circuit includes a sixteenth transistor; the control electrode of the sixteenth transistor is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal;

[0051] The fourth pull-down circuit includes a nineteenth transistor; the control stage of the nineteenth transistor is connected to the first pull-down node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the third level signal terminal.

[0052] In some embodiments, the drop-down node further includes a second drop-down node;

[0053] The first pull-down circuit further includes a third transistor; the control electrode of the third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal.

[0054] The second pull-down circuit further includes a fifth transistor; the control electrode of the fifth transistor is connected to the second pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal;

[0055] The third pull-down circuit also includes a seventeenth transistor; the control electrode of the seventeenth transistor is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal;

[0056] The fourth pull-down circuit also includes a twentieth transistor; the control stage of the twentieth transistor is connected to the second pull-down node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the third level signal terminal.

[0057] In some embodiments, the second reset circuit includes a fifteenth transistor; the control terminal of the fifteenth transistor is connected to the frame start signal terminal STV0, the first terminal is connected to the clock signal terminal, and the second terminal is connected to the cascade terminal.

[0058] In some embodiments, the output circuit includes a twenty-first transistor and a first storage capacitor;

[0059] The control electrode of the 21st transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal; one electrode of the first storage capacitor is connected to the pull-up node, and the other electrode is connected to the signal output terminal.

[0060] In some embodiments, the cascaded circuit includes an eighteenth transistor; the control electrode of the eighteenth transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal.

[0061] In some embodiments, the shift register unit further includes a third pull-down control circuit; the third pull-down control circuit is configured to transmit a second level signal to the pull-down control node under the control of a third input signal.

[0062] In some embodiments, the drop-down control node includes a first drop-down control node;

[0063] The third pull-down control circuit includes a twenty-second transistor; the control electrode of the twenty-second transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal.

[0064] In some embodiments, the drop-down control node further includes a second drop-down control node;

[0065] The third pull-down control circuit package also includes a twenty-third transistor; the control electrode of the twenty-third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal.

[0066] Secondly, this disclosure provides a driving method for a display panel, wherein the display panel includes a timing controller, a gate driving circuit, and a source driving circuit, and the method includes:

[0067] The timing controller applies a frame start signal and multiple clock signals to the gate drive circuit; the timing controller is configured such that the effective level duration of the clock signal provided by the clock signal line corresponding to the odd-numbered rows of sub-pixels is greater than the effective level duration of the clock signal provided by the clock signal line corresponding to the even-numbered rows of sub-pixels.

[0068] The gate driving circuit outputs multiple gate driving signals to the sub-pixel array based on the frame start signal and the multiple clock signals. It uses these multiple gate driving signals to scan the sub-pixel array row by row, turning on each scanned row of sub-pixels, such that the duration for which two adjacent rows of sub-pixels are simultaneously turned on is greater than or equal to twice the unit scan time. The unit scan time is the time required to scan one row of sub-pixels. The sub-pixel array includes multiple sub-pixels arranged in an N×M array, where N and M are both integers greater than 1. The gate driving circuit includes N shift register units connected to the N rows of sub-pixels of the sub-pixel array, each shift register unit connected to at least one clock signal line for transmitting clock signals. The gate driving circuit also includes multiple sets of alternately cascaded shift register groups.

[0069] The source drive circuit applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, such that the duration for which data signals are applied to at least some of the rows of sub-pixels is greater than the unit scan time.

[0070] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, which is the last unit scan time in the pre-charging period, and the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time.

[0071] Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes:

[0072] During the charging period of the sub-pixel in row 2k-1, one of the data signal in row 2k-1 and the data signal in row 2k is applied to the sub-pixel in row 2k-1;

[0073] During the first pre-charging period of the 2kth row sub-pixel and the first half of the charging period of the 2kth row sub-pixel, one of the 2k-1 row data signal and the 2kth row data signal is applied to the 2kth row sub-pixel; during the second half of the charging period of the 2kth row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2kth row sub-pixel; and

[0074] During the first pre-charge period of the sub-pixel in row 2k+1, one of the data signals from row 2k-1 and row 2k is applied to the sub-pixel in row 2k+1;

[0075] Where k = 1, 2, 3, ...

[0076] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, which is the last unit scan time in the pre-charging period, and the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time.

[0077] Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes:

[0078] During the latter half of the charging period of the sub-pixel in row 2k-1, one of the data signals of row 2k-1 and row 2k is applied to the sub-pixel in row 2k-1.

[0079] During the charging period of the 2kth row sub-pixel, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row sub-pixel;

[0080] During the first pre-charging period and the first half of the charging period of the 2k+1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k+1 row sub-pixel; during the second half of the charging period of the 2k+1 row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k+1 row sub-pixel; and

[0081] During the first pre-charging period of the second (k+1) row sub-pixel, one of the second (k-1) row data signal and the second (k) row data signal is applied to the second (k+1) row sub-pixel; during the charging period of the second (k+1) row sub-pixel, one of the second (k+1) row data signal and the second (k+1) row data signal is applied to the second (k+1) row sub-pixel.

[0082] Where k = 1, 2, 3, ...

[0083] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, which is the last unit scan time in the pre-charging period, and the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time.

[0084] Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes:

[0085] During the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-5 is applied to the sub-pixels in row 6k-5.

[0086] During the first pre-charging period of the 6k-4 row sub-pixels and the first half of the charging period of the 6k-4 row sub-pixels, the 6k-5 row data signal is applied to the 6k-4 row sub-pixels; during the second half of the charging period of the 6k-4 row sub-pixels, the 6k-3 row data signal is applied to the 6k-4 row sub-pixels.

[0087] During the first pre-charging period of the 6k-3 row sub-pixel, the 6k-5 row data signal is applied to the 6k-3 row sub-pixel; during the charging period of the 6k-3 row sub-pixel, the 6k-3 row data signal is applied to the 6k-3 row sub-pixel.

[0088] During the first pre-charging period of the 6k-2 row sub-pixel and the first half of the charging period of the 6k-2 row sub-pixel, the 6k-3 row data signal is applied to the 6k-2 row sub-pixel; during the second half of the charging period of the 6k-2 row sub-pixel, the 6k-1 row data signal is applied to the 6k-2 row sub-pixel.

[0089] During the first pre-charging period of the 6k-1 row sub-pixel, the 6k-3 row data signal is applied to the 6k-1 row sub-pixel; during the charging period of the 6k-1 row sub-pixel, the 6k-1 row data signal is applied to the 6k-1 row sub-pixel.

[0090] During the first pre-charging period of the 6k row sub-pixel and the first half of the charging period of the 6k row sub-pixel, the 6k-1 row data signal is applied to the 6k row sub-pixel; during the second half of the charging period of the 6k row sub-pixel, the 6k+1 row data signal is applied to the 6k row sub-pixel.

[0091] Where k = 1, 2, 3, ...

[0092] In some embodiments, the pre-charging period of each row of sub-pixels includes a first pre-charging period, which is the last unit scan time in the pre-charging period, and the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time.

[0093] Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes:

[0094] During the latter half of the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-5.

[0095] During the charging period of the sub-pixels in row 6k-4, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-4;

[0096] During the first pre-charging period of the 6k-3 row sub-pixel and the first half of the charging period of the 6k-3 row sub-pixel, the 6k-4 row data signal is applied to the 6k-3 row sub-pixel; during the second half of the charging period of the 6k-3 row sub-pixel, the 6k-2 row data signal is applied to the 6k-3 row sub-pixel.

[0097] During the first pre-charging period of the 6k-2 row sub-pixel, the 6k-4 row data signal is applied to the 6k-2 row sub-pixel; during the charging period of the 6k-2 row sub-pixel, the 6k-2 row data signal is applied to the 6k-2 row sub-pixel.

[0098] During the first pre-charging period of the 6k-1 row sub-pixel and the first half of the charging period of the 6k-1 row sub-pixel, the 6k-2 row data signal is applied to the 6k-1 row sub-pixel; during the second half of the charging period of the 6k-1 row sub-pixel, the 6k row data signal is applied to the 6k-1 row sub-pixel.

[0099] During the first pre-charging period of the 6k row sub-pixel, the 6k-2 row data signal is applied to the 6k row sub-pixel; during the charging period of the 6k row sub-pixel, the 6k row data signal is applied to the 6k row sub-pixel.

[0100] Where k = 1, 2, 3, ...

[0101] Thirdly, this disclosure provides a display device including the aforementioned display panel. Attached Figure Description

[0102] Figure 1 shows a schematic diagram of a display device provided in at least one embodiment of the present disclosure;

[0103] Figure 2 shows a timing diagram of a driving method according to an embodiment of the present disclosure;

[0104] Figure 3 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure;

[0105] Figure 4 shows a schematic diagram of the frame start signal line and clock signal line according to an embodiment of the present disclosure;

[0106] Figures 5a and 5b show example structural diagrams of a gate drive circuit provided in at least one embodiment of the present disclosure;

[0107] Figures 6a and 6b show example structural diagrams of another gate drive circuit provided in at least one embodiment of the present disclosure;

[0108] Figures 7a-7b show example structural diagrams of a shift register unit provided in this disclosure;

[0109] Figure 7c shows an example structural diagram of another shift register unit provided in this disclosure;

[0110] Figure 7d shows an example structural diagram of another shift register unit provided in this disclosure;

[0111] Figure 8 shows a flowchart of a driving method according to an embodiment of the present disclosure;

[0112] Figure 9a is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0113] Figure 9b is a schematic diagram of extracting odd-numbered rows of data from an initial data frame according to at least one embodiment of this disclosure;

[0114] Figure 10 is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to at least one embodiment of the present disclosure;

[0115] Figure 11 shows a signal timing diagram of a driving method according to an embodiment of the present disclosure;

[0116] Figure 12 shows a signal timing diagram of a driving method according to another embodiment of the present disclosure;

[0117] Figure 13 shows a timing diagram of another frame start signal and clock signal according to an embodiment of the present disclosure;

[0118] Figure 14 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure;

[0119] Figure 15 shows a signal timing diagram of another driving method according to an embodiment of the present disclosure. Detailed Implementation

[0120] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0121] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates an "or" relationship between related objects. The terms "first," "second," and "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," and "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0122] It should be noted that the transistors used in the embodiments of this invention can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this invention, to distinguish the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for illustration. When using an N-type transistor, the first terminal is the source, the second terminal is the drain, and when the gate input is high, the source and drain are conducting; the opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is also within the scope of protection of the embodiments of this invention.

[0123] In this embodiment of the invention, since the transistor used is an N-type transistor, the working level signal in this embodiment of the invention refers to a high-level signal, and the non-working level signal is a low-level signal; the corresponding working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal.

[0124] A typical display panel consists of multiple grid lines and multiple data lines. The grid lines and data lines intersect to define multiple pixel areas, each containing a pixel unit. The structure of the display panel is explained using the extension direction of the grid lines as the row direction and the extension direction of the data lines as the column direction as an example. When driving the display panel to display an image, grid scan signals are written to the grid lines row by row, and data voltage signals are simultaneously written to each data line, so that the pixel units in the display panel are lit row by row.

[0125] In this design, the gate scan signal is provided by the gate driving circuit, and the data voltage signal is provided by the source driving circuit. In related technologies, the gate driving circuit can be integrated into the gate driving chip, and the source driving circuit can be integrated into the source driving chip. Currently, in order to reduce the number of chips and achieve narrow bezels or bezel-less designs, a technique of integrating the gate driving circuit on the array substrate (Gate On Array; GOA) has been proposed. The gate driving circuit includes multiple cascaded shift register units integrated on the array substrate. Each shift register unit is connected to a gate line in a one-to-one correspondence and is used to provide the gate scan signal to the gate line connected to it.

[0126] In a first aspect, this disclosure provides a display panel 100, as shown in FIG1. ​​The display panel 100 includes a timing controller 30, a gate driving circuit 10, a source driving circuit 20, and a sub-pixel array. The sub-pixel array includes a plurality of sub-pixels P arranged in an N×M array, where N and M are both integers greater than 1. The timing controller 30 is configured to provide a frame start signal and a plurality of clock signals to the gate driving circuit 10. The gate driving circuit 10 is configured to provide a plurality of gate driving signals to the sub-pixel array based on the frame start signal and the plurality of clock signals, and to scan the sub-pixel array row by row using the plurality of gate driving signals to turn on each row of sub-pixels scanned, such that the duration for which two adjacent rows of sub-pixels are simultaneously in the turned-on state is greater than or equal to twice the unit scan time, where the unit scan time is the time required to scan one row of sub-pixels. The source driving circuit 20 is configured to provide data signals to at least two rows of sub-pixels that are simultaneously in the turned-on state.

[0127] Specifically, the timing controller 30 is connected to the gate drive circuit 10 and the source drive circuit 20, and can provide relevant control signals to the gate drive circuit 10 and the source drive circuit 20. For example, the timing controller 30 can provide a data control signal TP to the source drive circuit 20, and the source drive circuit 20 can output data signals for each row under the control of the data control signal TP. The timing controller 30 can also provide other control signals to the source drive circuit 20, including but not limited to row data start signals, data synchronization signals, data inversion signals, etc. The timing controller 30 can also provide various control signals to the gate drive circuit 10, including but not limited to frame start signals, clock signals, etc. required by the gate drive circuit 10.

[0128] The gate driving circuit 10 includes N shift register units connected to N rows of sub-pixels of the sub-pixel array, each shift register unit connected to at least one clock signal line for transmitting a clock signal. The gate driving circuit 10 can be connected to the N rows of sub-pixels respectively via multiple gate signal lines extending along a first direction (x-direction in FIG1). For example, a first gate signal line can be connected to a first row of sub-pixels P to provide a first gate driving signal G1 to the first row of sub-pixels P, and a second gate signal line can be connected to a second row of sub-pixels P to provide a second gate driving signal G2 to the second row of sub-pixels P, and so on. The first row of sub-pixels P turns on in response to receiving the first gate driving signal G1, the second row of sub-pixels P turns on in response to receiving the second gate driving signal G2, and so on. Continuing to refer to FIG1, the source driving circuit 20 can be connected to M columns of sub-pixels P respectively via multiple data lines extending along a second direction (y-direction in FIG1). For example, the source driving circuit 20 can be connected to the first column of sub-pixels P via a first data line to provide a first data signal D1 to the first column of sub-pixels P, and to provide a second data signal D2 to the second column of sub-pixels P via a second data line, and so on. For example, when the first row of sub-pixels P is turned on, the source driving circuit 20 can provide M data signals D11, D12, ..., D1M for the first row of sub-pixels P via M data lines respectively; when the second row of sub-pixels P is turned on, the source driving circuit 20 can provide M data signals D21, D22, ..., D2M for the second row of sub-pixels P via multiple data lines respectively, and so on. Of course, the embodiments of this disclosure are not limited to this, and will be further described in detail below.

[0129] In some embodiments, the gate driving circuit 10 scans the sub-pixels row by row. That is, the gate driving circuit 10 sequentially generates N gate driving signals G1, G2, ... GN to sequentially turn on the first row of sub-pixels P, the second row of sub-pixels P, ... the Nth row of sub-pixels P. At this time, the timing controller 30 is configured such that the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing real data is greater than the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing interpolated data.

[0130] It should be noted that in this embodiment, each row of sub-pixels is electrically connected to a shift register unit, which provides the gate drive signal. When the gate drive signal scans the row of sub-pixels (i.e., the gate drive signal turns on the row of sub-pixels), the first data signal provided by the source drive signal corresponding to that row of sub-pixels is written to the sub-pixel, completing the charging of the row of sub-pixels. Therefore, if the effective level duration of the data signal is long enough, the effective working level duration of the gate drive signal will affect the charging time of the sub-pixel (i.e., the data signal writing time). For each shift register unit, referring to Figure 7a, the effective level duration of the gate drive signal output by the shift register unit depends on the effective level duration of the clock signal transmitted on the clock signal line connected to the output circuit 1010. The longer the effective level duration of the clock signal, the longer the effective level duration of the gate drive signal output by the corresponding shift register unit, and therefore the longer the charging time of the corresponding row of sub-pixels. In this embodiment, the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing real data is set to be greater than the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing interpolated data. This means the charging time of the sub-pixel row for writing real data is greater than the charging time of the sub-pixel row for writing interpolated data, thereby increasing the charging rate of the sub-pixel row for writing real data and improving the overall display effect. Furthermore, this setting allows for different duty cycles for each clock signal, thereby enhancing the signal's anti-interference capability. All shift register units in this document use N-type transistors; therefore, the effective operating level mentioned herein refers to a high level, and the effective level duration refers to the duration of the signal remaining at a high level.

[0131] It should be noted that in a single frame of display, the actual data is the data that needs to be displayed for the corresponding row of sub-pixels, while the interpolated data is data that differs from the corresponding row of sub-pixels. For the entire panel, actual data can be written to a preset row of pixels first, followed by a row of interpolated data. For example, actual data can be written to ten rows of pixels, and then interpolated data can be written to one row of pixels. The charging time of the row of pixels with actual data is set to be greater than that of the row with interpolated data, thereby reducing the power consumption of the display panel. Preferably, in one embodiment, the sub-pixel rows with actual data and the sub-pixel rows with interpolated data are alternately set. This setting can make the display more uniform and improve the display effect. For example, for a 4K2K (resolution 3840×2160) display panel, the number of horizontal pixels is 3840 and the number of vertical pixels is 2160. If the multiple sub-pixels contained in each pixel are arranged horizontally, then the display panel includes 2160 rows of sub-pixels. The sub-pixel rows into which real data is written can include sub-pixels in rows 1, 3, 5, ..., 2159, while the sub-pixel rows into which interpolation data is written can include sub-pixels in rows 2, 4, ..., 2160. If the charging time for each row of subpixels is equal, at a refresh rate of 60Hz, the scanning time for one frame is 1 / 60 of a second. That is, scanning 2160 rows of subpixels takes 1 / 60 of a second. Therefore, the time spent scanning each row of subpixels (i.e., the unit scanning time) H = 1 / 60 ÷ 2160 ≈ 1.85us. In this application, the charging time for subpixel rows that are written with real data is set to be greater than the time for subpixel rows that are written with interpolated data. For example, the scanning time for subpixel rows that are written with real data is set to 2us, and the scanning time for subpixel rows that are written with interpolated data is set to 1.7us. In this way, the average scanning time for scanning one row of subpixels is 1.85us, and the refresh rate can still be maintained at 60Hz. At the same time, the charging rate of local subpixels of the display panel (i.e., the charging rate of subpixel rows that are written with real data) can be improved, thereby improving the display effect of the entire display panel.

[0132] Figure 2 shows a timing diagram of a driving method according to an embodiment of the present disclosure.

[0133] During time period T1 (the first time period), the first row of sub-pixels and the second row of sub-pixels are turned on sequentially. For example, in the first sub-time period T11 of the first time period T1, the first gate drive signal G1 is high, thereby turning on the first row of sub-pixels; in the second sub-time period T12 of the first time period T1, the second gate drive signal G2 is high, thereby turning on the second row of sub-pixels.

[0134] During time period T2 (second time period), the third and fourth rows of sub-pixels are turned on sequentially, and data signals are applied to the first and second rows of sub-pixels. For example, when the first high-level pulse of the data control signal TP arrives, the source drive circuit 20 applies one of the first row data signal DATA1 and the second row data signal DATA2 (in this embodiment, the first row data signal DATA1) to the first and second rows of sub-pixels.

[0135] During time period T3 (the third time period), the first row of subpixels is turned off, and data signals are applied to the second, third, and fourth row of subpixels. For example, when the second high-level pulse of the data control signal TP arrives, one of the third row data signal DATA3 and the fourth row data signal DATA4 is applied to the second, third, and fourth row of subpixels that are in the turned-on state.

[0136] Similarly, for the third and fourth row sub-pixels, the first time period is time period T2 in Figure 2, the second time period is time periods T3 and T4 in Figure 2, and the third time period is time period T5 in Figure 2. During time period T2, the third and fourth row sub-pixels are sequentially activated. For example, in the first sub-time period T21 of time period T2, the third gate drive signal G3 is high, thereby activating the third row sub-pixels; in the second sub-time period T22 of time period T2, the fourth gate drive signal G4 is high, thereby activating the fourth row sub-pixels. During time periods T3 and T4, the fifth and sixth row sub-pixels are sequentially activated, and one of the third row data signals DATA3 and DATA4 is applied to the third and fourth row sub-pixels. During time period T5, the third row sub-pixels are deactivated, and one of the fifth row data signals DATA5 and DATA6 is applied to the fourth, fifth, and sixth row sub-pixels.

[0137] The length of the second time period can be set to be greater than or equal to 2H, such that the duration for which a data signal is applied to each row of sub-pixels is greater than or equal to 2H. For example, in the example in Figure 2, the time period for which a data signal is applied to the first row of sub-pixels is time period T2, and the time periods for which a data signal is applied to the second row of sub-pixels are time periods T2 and T3. The lengths of time periods T1 and T2 can be set to 2H, and the length of time period T3 can be set to H. In this case, the actual charging time of the first row of sub-pixels is 2H (the length of time period T2), and the actual charging time of the second row of sub-pixels is 3H (the sum of the lengths of time periods T2 and T3). Similarly, the actual charging time of the third row of sub-pixels is 2H, and the actual charging time of the fourth row of sub-pixels is 3H.

[0138] In this embodiment, by sequentially turning on two rows of sub-pixels and applying data signals to the two rows of sub-pixels that are simultaneously turned on, the actual charging time of some sub-pixels (e.g., odd-numbered row sub-pixels) can reach 2H or higher, while the actual charging time of other sub-pixels (e.g., even-numbered row sub-pixels) can reach 3H or higher.

[0139] For example, the gate drive circuit includes N shift register units connected to N rows of sub-pixels in the sub-pixel array, including a first-stage shift register unit (such as GOA1) connected to the first row of sub-pixels in the sub-pixel array. Multiple clock signals include a first clock signal (such as CLK1) for driving the gate drive signal output by the first-stage shift register unit. For example, in the disclosed embodiment, the shift register unit connected to the first row of sub-pixels is referred to as the first-stage shift register unit.

[0140] Figure 3 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0141] As shown in Figure 3, the rising edge of the frame start signal STV is earlier than the rising edge of the first clock signal CLK1, and the falling edge of the frame start signal STV is no later than the falling edge of the first clock signal CLK1. The phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time. Based on this setting, display defects can be improved, and a better display effect can be achieved.

[0142] Figure 4 shows a schematic diagram of the frame start signal line and clock signal line according to an embodiment of the present disclosure.

[0143] As shown in Figures 3 and 4, if the falling edge of the frame start signal line STV is aligned with the falling edge of the clock signal line CLK1, then the frame start signal line STV will not cause pull-down interference to the clock signal CLK1 when it is pulled down. The width of the frame start signal line STV is greater than the width of the clock signal line CLK, therefore the resistance of the frame start signal line STV is greater than the resistance of the clock signal line CLK. When the falling edge of the frame start signal line STV is earlier than the falling edge of the clock signal line CLK1, and the phase difference between the falling edge of the frame start signal line STV and the falling edge of the clock signal line CLK1 is, for example, 1H or greater, the falling edge of the frame start signal STV during pull-down is slower, thus having a smaller impact on the clock signal line CLK1, and cannot balance the interference received by CLK2 and subsequent clock signals. In this embodiment of the disclosure, the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is set to 0.2H to 0.6H. This allows the frame start signal STV to have a greater pull-down effect on the clock signal CLK1, thereby balancing the interference experienced by the clock signal CLK1 and its subsequent clock signals, improving the phenomenon of poor horizontal stripes, and achieving a better display effect.

[0144] For example, the first-stage shift register unit to the Pth-stage shift register unit in the N shift register units are connected to the frame start signal; the multiple clock signals also include the Pth clock signal for driving the output gate drive signal of the Pth-stage shift register unit; the duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%, and the phase difference and duty cycle are configured such that the falling edge of the frame start signal is aligned with the rising edge of the Pth clock signal, where P is an integer greater than 1.

[0145] For example, the value of P is related to the number of clock signals connected to the gate drive circuit. When the gate drive circuit is connected to 8CLK signals, P is 4; when the gate drive circuit is connected to 12CLK signals, P is 6.

[0146] For example, if the frame start signal STV is connected to the first to fourth level shift register units, then the P-th level shift register unit is the fourth level shift register unit. Setting the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 to 0.2H to 0.6H, and setting the duty cycle of the clock signal to 40% to 45%, and coordinating the phase difference and duty cycle to align the falling edge of the frame start signal with the rising edge of the fourth clock signal CLK4, can further improve display defects and achieve better display results.

[0147] For example, in some embodiments, the phase difference between the rising edges of any two adjacent clock signals in a plurality of clock signals is a unit scan time H, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%. For example, as shown in Figure 6, the high-level duration t1 of the frame start signal STV is 8H, the high-level duration t3 of each clock signal CLK is 3.2H, and the period time t4 of the clock signal CLK is 8H, then the duty cycle of the clock signal is 3.2 / 8 = 40%. The phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the clock signal CLK1 is 5H, the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.2H, and the start and end times of each clock signal CLK are sequentially 1H apart by t5. The rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. In other words, when the clock signals are 1H apart, and the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.2H and the duty cycle of the clock signal is 40%, the rising edge of the clock signal CLK4 can be aligned with the falling edge of the frame start signal STV.

[0148] For example, in some other embodiments, when the phase difference t6 between the falling edge of the start-of-frame signal STV and the falling edge of the clock signal CLK1 is 0.3H, setting the duty cycle of the clock signal to 3.3 / 8 = 41.25% can align the rising edge of the clock signal CLK4 with the falling edge of the start-of-frame signal STV. As another example, when the phase difference t6 between the falling edge of the start-of-frame signal STV and the falling edge of the clock signal CLK1 is 0.4H, setting the duty cycle of the clock signal to 3.4 / 8 = 42.5% can align the rising edge of the clock signal CLK4 with the falling edge of the start-of-frame signal STV. As yet another example, when the phase difference t6 between the falling edge of the start-of-frame signal STV and the falling edge of the clock signal CLK1 is 0.6H, setting the duty cycle of the clock signal to 3.6 / 8 = 45% can align the rising edge of the clock signal CLK4 with the falling edge of the start-of-frame signal STV.

[0149] For example, when the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV, the clock signal CLK4 immediately starts rising when the frame start signal STV ends, generating a second-order PU, which fully controls the GOA output. This can avoid leakage at the PU point in the shift register unit, allowing each sub-pixel to achieve a better charging effect.

[0150] For example, setting the duty cycle of the clock signal to 40% to 45% can improve display problems in some cases. The duty cycle of the clock signal is usually 50%, but when the duty cycle is 50%, display problems may occur due to in-plane coupling and other reasons. The embodiments of this disclosure set the duty cycle to 40% to 45%, which can solve the display problems in this case.

[0151] For example, each of the multiple initial data frames can be divided into a first target data frame and a second target data frame, wherein one of the first target data frame and the second target data frame corresponding to any initial data frame includes the odd-numbered rows of data of the initial data frame, and the other includes the even-numbered rows of data of the initial data frame.

[0152] In some embodiments, the gate driving circuit can be divided into m gate driving sub-circuits, each including 4n shift register units, where 1 ≤ m ≤ 6, 1 ≤ n ≤ 4, and m and n are integers. The gate driving sub-circuits can be further divided into a first shift register group and a second shift register group, with each group connected to a different initial gate scan signal. Specifically, the first shift register group may include 2n odd-numbered shift register units, such as the 1st, 3rd, 5th, ..., 4n-1th shift register units. Correspondingly, the second shift register group includes 2n even-numbered shift register units, such as the 2nd, 4th, 6th, ..., 4nth shift register units. Of course, the first shift register group may also include even-numbered shift register units, and the second shift register group may include odd-numbered shift register units; this is not limited here.

[0153] Furthermore, the m gate driver sub-circuits are connected to m groups of clock signal lines, each group of clock signal lines including 4n clock signal lines. That is, each adjacent 4n shift register units are connected one-to-one with 4n clock signal lines, and the i-th shift register unit is connected to the (i+4n)-th shift register on the same clock signal line. For example, if m=2 and n=2, the gate driver circuit includes two gate driver sub-circuits, each including 8 shift register units, meaning the gate driver circuit includes 16 shift register units connected to 8 clock signal lines. The 1st to 8th shift registers are connected one-to-one with clk1-clk8, and the 9th to 16th shift register units are also connected one-to-one with clk1-clk8.

[0154] For example, Figures 5a-5b are cascade diagrams of gate drive circuits when m=1 and n=2.

[0155] As shown in Figure 5a, the gate drive circuit includes eight cascaded shift register units GOA1, GOA2, ..., GOA8, connected to eight different CLK lines. The input terminals (Input) of the first to fourth shift register units GOA1 to GOA4 can be connected to the frame start signal terminal STV1. After the fourth shift register unit GOA4, the input terminal (Iaput) of the a-th shift register unit GOAa is connected to the output terminal of the (a-4)-th shift register unit GOA(a-4), where 5 ≤ a ≤ a. For example, the output of GOA1 is connected to the input of GOA5, the output of GOA2 is connected to the input of GOA6, the output of G3 is connected to the input of GOA7, the output of G4 is connected to the input of GOA8, the output of G5 is connected to the input of GOA9, and so on. The reset terminal (RST) of the b-th shift register unit GOAAb is connected to the output terminal (OUT) of the (b+4)-th shift register unit GOA(b+4), where 1 ≤ b ≤ 4.

[0156] For a 4K2K (3840×2160 resolution) display panel, the horizontal pixel count is 3840 and the vertical pixel count is 2160. If each pixel contains multiple sub-pixels arranged horizontally, the display panel includes 2160 rows of sub-pixels. With 2160 rows of sub-pixels and each shift register unit corresponding to one row of sub-pixels, the gate drive circuit can include 2160 shift register units. Figure 5b shows the last shift register unit GOA2160 and the dummy shift register unit (Dummy GOA). As shown in Figure 5b, the last four rows of GOA can be reset using four rows of dummy GOA. For example, dummy GOA1 (Dum1) resets GOA2157, dummy GOA2 (Dum2) resets GOA2158, and so on. Each dummy GOA can be reset using STV1. STV0 is the total reset signal, and STV0 is connected to GOA9 and subsequent units. STV0 and STV1 have identical waveforms, so they can be connected together externally.

[0157] The gate drive circuits shown in Figures 5a and 5b employ eight clock signals CLK1 to CLK8. The clock signal terminal CLK of the first shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the eighth shift register unit GOA8 is connected to receive the eighth clock signal CLK8. Similarly, the ninth to sixteenth shift register units GOA9 to GOA16 are connected to receive the first to eighth clock signals CLK1 to CLK8, respectively.

[0158] Each shift register unit GOA1, GOA2, ..., GOAN can generate an output signal as a gate drive signal (or gate scan signal) at its output OUT under the control of its clock signal CLK and input signals. For example, the first shift register unit GOA1 generates the first gate drive signal G1, the second shift register unit GOA2 generates the second gate drive signal G2, and so on. By connecting them in a series, the gate drive signal generated by one shift register unit can be shifted relative to the gate drive signal generated by another shift register unit.

[0159] For example, Figures 6a-6b are cascade diagrams of gate drive circuits when m=1 and n=3 (12clk).

[0160] As shown in Figure 6a, the gate drive circuit includes 12 cascaded shift register units GOA1, GOA2, ..., GOA12, connected to 12 different CLK lines. The input terminals (Input) of the first to sixth shift register units GOA1 to GOA6 can be connected to the frame start signal terminal STV1. After the sixth shift register unit GOA6, the input terminal (Input) of the a-th shift register unit GOAa is connected to the output terminal of the (a-6)-th shift register unit GOA(a-6), where 7 ≤ a ≤ 12. For example, the output of GOA1 is connected to the input of GOA7, the output of GOA2 is connected to the input of GOA8, the output of G3 is connected to the input of GOA9, the output of G4 is connected to the input of GOA10, the output of G5 is connected to the input of GOA11, and so on. The reset terminal (RST) of the b-th shift register unit GOAb is connected to the output terminal (OUT) of the (b+6)-th shift register unit GOA(b+6), where 1 ≤ b ≤ 6.

[0161] The gate drive circuits shown in Figures 6a and 6b employ 12 clock signals CLK1 to CLK12. The clock signal terminal CLK of the first shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on, with the clock signal terminal CLK of the 12th shift register unit GOA12 connected to receive the 12th clock signal CLK12. Similarly, the 13th to 24th shift register units GOA13 to GOA24 are connected to receive the first to twelfth clock signals CLK1 to CLK12, respectively.

[0162] Each shift register unit GOA1, GOA2, ..., GOAN can generate an output signal as a gate drive signal (or gate scan signal) at its output OUT under the control of its clock signal CLK and input signals. For example, the first shift register unit GOA1 generates the first gate drive signal G1, the second shift register unit GOA2 generates the second gate drive signal G2, and so on. By connecting them in a series, the gate drive signal generated by one shift register unit can be shifted relative to the gate drive signal generated by another shift register unit.

[0163] This disclosure also provides a specific structure of the aforementioned shift register unit, as shown in Figures 7a-7d. The shift register unit may include: an input circuit connected to a first signal input terminal, a first level signal terminal, and a pull-up node, used to respond to a first input signal transmitting a first level signal to the pull-up node; a first reset circuit connected to a second signal input terminal, a second level signal terminal, and a pull-up node, used to respond to a second input signal transmitting a second level signal to the pull-up node; a first pull-down circuit connected to a third signal input terminal, a second level signal terminal, and a pull-down node, used to respond to a third input signal transmitting a second level signal to the pull-down node; a second pull-down circuit connected to a pull-down node, a second level signal terminal, and a pull-up node, used to respond to a pull-down node voltage transmitting a second level signal to the pull-up node; and a first pull-down control circuit connected to the pull-up node, the pull-down node, the pull-down control node, and the second level signal terminal, used to transmit the second level signal to the pull-down node and the pull-down control node under the control of the pull-up node voltage. The second pull-down control circuit, connected to the power signal terminal, the pull-down node, and the pull-down control node, is used to transmit the power signal to the pull-down node and the pull-down control node in response to the power signal. The second reset circuit, connected to the frame start signal terminal STV0 and the pull-up node, is used to reset the pull-up node in response to a reset signal. The third pull-down circuit is used to transmit the second-level signal to the cascaded signal terminal in response to the pull-down node voltage. The fourth pull-down circuit is used to reset the signal output terminal in response to the pull-down node voltage. The output power supply is used to transmit the clock signal to the signal output terminal in response to the pull-up node voltage. The cascaded circuit is used to transmit the clock signal to the cascaded signal terminal output in response to the pull-up node voltage.

[0164] In some examples, the input circuitry includes a first transistor. The control electrode of the first transistor is connected to a first signal input terminal, a first terminal is connected to a first-level signal terminal, and a second terminal is connected to a pull-up node. The first transistor is configured to write the first-level signal to the pull-up node under the control of the first input signal.

[0165] In some examples, the first reset circuit includes a second transistor; the control electrode of the second transistor is connected to a second signal input, the first electrode is connected to a pull-up node, and the second electrode is connected to a second-level signal terminal. The second transistor is configured to write the second-level signal to the pull-up node under the control of the second input signal.

[0166] In some examples, the second reset circuit includes a fifteenth transistor; the control terminal of the fifteenth transistor is connected to the frame start signal terminal STV0, the first terminal is connected to the clock signal terminal, and the second terminal is connected to the cascade terminal. The fifteenth transistor is configured to transmit the clock signal to the cascade terminal under the control of the reset signal.

[0167] In some examples, the output circuit includes a twenty-first transistor and a first storage capacitor; the control terminal of the twenty-first transistor is connected to a pull-up node, the first terminal is connected to a clock signal terminal, and the second terminal is connected to a signal output terminal; one terminal of the first storage capacitor is connected to the pull-up node, and the other terminal is connected to the signal output terminal. The twenty-first transistor is configured to transmit the clock signal to the signal output terminal under the control of the pull-up node voltage.

[0168] In some examples, the cascaded circuit includes an eighteenth transistor; the control terminal of the eighteenth transistor is connected to a pull-up node, the first terminal is connected to a clock signal terminal, and the second terminal is connected to the output signal terminal. In other examples, the control terminal of the eighteenth transistor is connected to a pull-up node, the first terminal is connected to a clock signal terminal, and the second terminal is connected to the cascaded signal terminal.

[0169] In some examples, the power signal terminal includes a first power signal terminal and a second power signal terminal, the pull-down node includes a first pull-down node and a second pull-down node, and the pull-down control node includes a first pull-down control node and a second pull-down control node.

[0170] Correspondingly, in some examples, the first pull-down control circuit includes a seventh transistor and an eighth transistor. The control electrode of the seventh transistor is connected to the pull-up node, its first electrode is connected to the first pull-down node, and its second electrode is connected to the second-level signal terminal. The control electrode of the eighth transistor is connected to the pull-up node, its first electrode is connected to the first pull-down control node, and its second electrode is connected to the second-level signal terminal. The second pull-down control circuit includes a ninth transistor and a tenth transistor. The control electrode and first electrode of the ninth transistor are both connected to the first power supply signal terminal, and its second electrode is connected to the first pull-down control node. The control electrode of the tenth transistor is connected to the first pull-down control node, its first electrode is connected to the first power supply signal terminal, and its second electrode is connected to the first pull-down node. The first pull-down circuit includes a fourth transistor. The control electrode of the fourth transistor is connected to the third signal input terminal, its first electrode is connected to the first pull-down node, and its second electrode is connected to the second-level signal terminal. The second pull-down circuit includes a sixth transistor. The control electrode of the sixth transistor is connected to the first pull-down node, its first electrode is connected to the pull-up node, and its second electrode is connected to the second-level signal terminal. The third pull-down circuit includes a sixteenth transistor. The control electrode of the sixteenth transistor is connected to the first pull-down node, and its second electrode is connected to the second-level signal terminal. The fourth pull-down circuit includes a nineteenth transistor. The control stage of the nineteenth transistor is connected to the first pull-down node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the third level signal terminal.

[0171] In other examples, the first pull-down control circuit further includes an eleventh transistor and a twelfth transistor. The control electrode of the eleventh transistor is connected to the pull-up node, its first electrode is connected to the second pull-down control node, and its second electrode is connected to the second-level signal terminal. The control electrode of the twelfth transistor is connected to the pull-up node, its first electrode is connected to the second pull-down node, and its second electrode is connected to the second-level signal terminal. The second pull-down control circuit further includes a thirteenth transistor and a fourteenth transistor. The control electrode and first electrode of the thirteenth transistor are both connected to the second power supply signal terminal, and its second electrode is connected to the second pull-down control node. The control electrode of the fourteenth transistor is connected to the second pull-down control node, its first electrode is connected to the second power supply signal terminal, and its second electrode is connected to the second pull-down node. The first pull-down circuit also includes a third transistor. The control electrode of the third transistor is connected to the third signal input terminal, its first electrode is connected to the second pull-down node, and its second electrode is connected to the second-level signal terminal. The second pull-down circuit also includes a fifth transistor. The control electrode of the fifth transistor is connected to the second pull-down node, its first electrode is connected to the pull-up node, and its second electrode is connected to the second-level signal terminal. The third pull-down circuit also includes a seventeenth transistor. The control electrode of the seventeenth transistor is connected to the second pull-down node, and its second electrode is connected to the second-level signal terminal. The fourth pull-down circuit also includes the twentieth transistor; the control stage of the twentieth transistor is connected to the second pull-down node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the third level signal terminal.

[0172] It should be noted that the third and fourth transistors in the first pull-down circuit have the same structure and function, and they only operate in a time-sharing manner. Similarly, the fifth and sixth transistors in the second pull-down circuit have the same structure and function. The sixteenth and seventeenth transistors in the third pull-down circuit have the same structure and function. The nineteenth and twentieth transistors in the fourth pull-down circuit have the same structure and function. The seventh and eleventh transistors, and the eighth and twelfth transistors in the first pull-down control circuit have the same structure and function. The ninth and thirteenth transistors, and the tenth and fourteenth transistors in the second pull-down control circuit have the same structure and function. The input circuit, the first reset circuit, the second reset circuit, the output circuit, and the cascaded circuit have the same structure and function as described above, so they will not be repeated here.

[0173] It should be noted that the signals output by the cascaded signal terminal and the signal output terminal are the same; the only difference is that this shift register unit has two output terminals: one is the signal output terminal connected to the gate line, and the other is the cascaded signal output terminal used for cascading. The reason for setting up a separate cascaded sub-circuit is to reduce the load on the signal output terminal, so as to avoid affecting the gate drive signal output by the signal output terminal.

[0174] The specific structure of the shift register unit of this disclosure will be described below with reference to specific embodiments.

[0175] Referring to Figures 7a-7b, which illustrate a first example of a shift register unit provided in this disclosure, the shift register unit includes: an input circuit 1001, a first reset circuit 1002, a first pull-down circuit 1003, a second pull-down circuit 1004, a first pull-down control circuit 1005, a second pull-down control circuit 1006, a second reset circuit 1007, a third pull-down circuit 1008, a fourth pull-down circuit 1009, an output circuit 1010, and a cascaded circuit 1011. Specifically, the shift register unit includes first to twenty-first transistors M21. Specifically, the input circuit 1001 includes a first transistor M1; the first reset circuit 1001 includes a second transistor M2; the first pull-down circuit 1003 includes a fourth transistor M4 and a third transistor M3; the second pull-down circuit 1004 includes a fifth transistor M5 and a sixth transistor M6; the first pull-down control circuit 1005 includes a seventh transistor M7, an eighth transistor M8, an eleventh transistor M11, and a twelfth transistor M12; the second pull-down control circuit 1007 includes a ninth transistor M9, a tenth transistor M10, a thirteenth transistor M13, and a fourteenth transistor M14; the second reset circuit 1006 includes a fifteenth transistor M15; the third pull-down circuit 1008 includes a sixteenth transistor M16 and a seventeenth transistor M17; the cascaded circuit 1011 includes an eighteenth transistor M18; the fourth pull-down circuit 1009 includes a nineteenth transistor M19 and a twentieth transistor M20; and the output circuit 1010 includes a twenty-first transistor M21 and a first storage capacitor C1.

[0176] Specifically, the control electrode of the first transistor M1 is connected to the first signal input terminal Input, the first electrode is connected to the first level signal terminal VDS, and the second electrode is connected to the pull-up node PU; the control electrode of the second transistor M2 is connected to the second signal input terminal Reset, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal terminal LVGL; the control electrode of the third transistor M3 is connected to the third signal input terminal PD_F, the first electrode is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal terminal LVGL; the control electrode of the fourth transistor M4 is connected to the third signal input terminal PD_F, the first electrode is connected to the first pull-down node PD_A, and the second electrode is connected to the second level signal terminal LVGL; the control electrode of the fifth transistor M5 is connected to the second pull-down node PD_B. Node PD_B has its first terminal connected to pull-up node PU and its second terminal connected to the second-level signal LVGL terminal; the control terminal of the sixth transistor M6 is connected to the first pull-down node PD_A, its first terminal connected to pull-up node PU, and its second terminal connected to the second-level signal LVGL terminal; the control terminal of the seventh transistor M7 is connected to pull-up node PU, its first terminal connected to the first pull-down node PD_A, and its second terminal connected to the second-level signal LVGL terminal; the control terminal of the eighth transistor M8 is connected to pull-up node PU, its first terminal connected to the first pull-down control node PD_CNA, and its second terminal connected to the second-level signal LVGL terminal; the control terminal and its first terminal of the ninth transistor M9 are both connected to the first power supply signal terminal VDD1, and its second terminal connected to the first pull-down control node PD_C... NA; The control electrode of the tenth transistor M10 is connected to the first pull-down control node PD_CNA, the first electrode is connected to the first power supply signal terminal VDD1, and the second electrode is connected to the first pull-down node PD_A; The control electrode of the eleventh transistor M11 is connected to the pull-up node PU, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal LVGL terminal; The control electrode of the twelfth transistor M12 is connected to the pull-up node PU, the first electrode is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal LVGL terminal; The control electrode and the first electrode of the thirteenth transistor M13 are both connected to the second power supply signal terminal VDD2, and the second electrode is connected to the second pull-down control node PD_CNB; The control electrode of the fourteenth transistor M14 is connected to the second pull-down... The control node PD_CNB has its first terminal connected to the second power supply signal terminal VDD2, and its second terminal connected to the second pull-down node PD_B; the control terminal of the fifteenth transistor M15 is connected to the frame start signal terminal STV0, its first terminal is connected to the first clock signal terminal VDD1, and its second terminal is connected to the cascade signal terminal OC; the control terminal of the sixteenth transistor M16 is connected to the first pull-down node PD_A, and its second terminal is connected to the second level signal terminal LVGL; the control terminal of the seventeenth transistor M17 is connected to the second pull-down node PD_B, and its second terminal is connected to the second level signal terminal LVGL; the control terminal of the eighteenth transistor M18 is connected to the pull-up node PU, its first terminal is connected to the first clock signal terminal VDD1, and its second terminal is connected to the signal output terminal GoutN;The control stage of the nineteenth transistor M19 is connected to the first pull-down node PD_A, with its first terminal connected to the signal output terminal GoutN and its second terminal connected to the third-level signal VGL. The twentieth transistor M20's control stage is connected to the second pull-down node PD_B, with its first terminal connected to the signal output terminal GoutN and its second terminal connected to the third-level signal VGL. The control stage of the twenty-first transistor M21 is connected to the pull-up node PU, with its first terminal connected to the first clock signal terminal VDD1 and its second terminal connected to the signal output terminal GoutN. One terminal of the first storage capacitor C1 is connected to the pull-up node PU, and the other terminal is connected to the signal output terminal GoutN.

[0177] It should be noted that, in this embodiment, the first input signal input to the first signal input terminal is the cascade signal terminal of the four shift register units above this level (if this level is the Nth level, then it is connected to the cascade signal terminal of the (N-4th)th level shift register unit), the second input signal connected to the second signal input terminal is the cascade signal terminal of the four shift register units below this level (the cascade signal terminal of the (N+4th)th level), and the third input signal input to the third signal input terminal is the pull-up node voltage of the previous level (the pull-up node voltage of the (N-1th)th level). This configuration, when the pull-up node of the previous level shift register unit is pulled high, can pre-pull down the pull-down node and pull-down control node of this level shift register unit, thereby improving the competition relationship between the pull-up and pull-down nodes and enhancing the instantaneous low-temperature start-up capability and service life.

[0178] The working principle of the shift register unit in this embodiment will be explained below.

[0179] During the discharge phase, before the frame is displayed, a high-level signal is input to the frame start signal terminal. The low-level signal input to the low-level signal terminal discharges the pull-up node PU to prevent residual charge in the pull-up node PU from causing display abnormalities.

[0180] During the input phase, a high-level signal is input to the first signal input terminal Input, the first transistor M1 is turned on, the pull-up node PU is pulled high by the high-level signal, and the first storage capacitor C1 is charged.

[0181] During the output phase, since the pull-up node PU is pulled high during the input phase, both the eighteenth transistor M18 and the twenty-first transistor M21 are turned on, and the high-level signal input at the clock signal terminal is output through the signal output terminal GoutN and the cascaded signal terminal OC N.

[0182] During the reset phase, a high-level signal is input to the frame start signal terminal STV0, turning on the fifteenth transistor M15. The second-level signal LVGL, i.e., a low-level signal, pulls down the potential of the pull-up node PU to reset it. Since the pull-up node PU is pulled low, the eighteenth transistor M18 and the twenty-first transistor M21 are turned off, and both the signal output terminal GoutN and the cascaded signal output terminal GoutN no longer output high-level signals. Simultaneously, the first pull-down control node PD_CNA and the pull-down node are both high-level signals, turning on the fifth transistor M5, the sixteenth transistor M16, and the nineteenth transistor M19. These transistors reduce noise on the outputs of the pull-up node PU, the signal output terminal GoutN, and the cascaded signal output terminal OC N, respectively, until the pull-up node PU is pulled high at the start of the next frame scan.

[0183] Referring to Figure 7c, which shows a second example of a shift register unit provided in this disclosure, this example differs from the first example in Figure 7b in that the shift register unit further includes a third pull-down control sub-circuit 1012, and the third input signal input to the third input signal terminal is different. The third pull-down control circuit 1012 includes a twenty-second transistor M22 and a twenty-third transistor M23. Similarly, the twenty-second transistor M22 and the twenty-third transistor M23 have the same structure and function, only their operating times differ.

[0184] Specifically, the shift register unit in the second example includes: transistors M23 from the first to the twenty-third. Specifically, the control electrode of the first transistor M1 is connected to the first signal input terminal Input, the first electrode is connected to the first level signal terminal VDS, and the second electrode is connected to the pull-up node PU; the control electrode of the second transistor M2 is connected to the second signal input terminal Reset, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second level signal terminal LVGL; the control electrode of the third transistor M3 is connected to the third signal input terminal PD_F, the first electrode is connected to the second pull-down node PD_B, and the second electrode is connected to the second level signal terminal LVGL; the control electrode of the fourth transistor M4 is connected to the third signal input terminal PD_F, the first electrode is connected to the first pull-down node PD_A, and the second electrode is connected to the second level signal terminal LVGL. The control electrode of the fifth transistor M5 is connected to the second pull-down node PD_B, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second-level signal LVGL terminal; the control electrode of the sixth transistor M6 is connected to the first pull-down node PD_A, the first electrode is connected to the pull-up node PU, and the second electrode is connected to the second-level signal LVGL terminal; the control electrode of the seventh transistor M7 is connected to the pull-up node PU, the first electrode is connected to the first pull-down node PD_A, and the second electrode is connected to the second-level signal LVGL terminal; the control electrode of the eighth transistor M8 is connected to the pull-up node PU, the first electrode is connected to the first pull-down control node PD_CNA, and the second electrode is connected to the second-level signal LVGL terminal; the control electrode of the ninth transistor M9 and... The first terminal of each transistor is connected to the first power supply signal terminal VDD1, and the second terminal is connected to the first pull-down control node PD_CNA; the control terminal of the tenth transistor M10 is connected to the first pull-down control node PD_CNA, the first terminal is connected to the first power supply signal terminal VDD1, and the second terminal is connected to the first pull-down node PD_A; the control terminal of the eleventh transistor M11 is connected to the pull-up node PU, the first terminal is connected to the second pull-down control node, and the second terminal is connected to the second level signal LVGL terminal; the control terminal of the twelfth transistor M12 is connected to the pull-up node PU, the first terminal is connected to the second pull-down node PD_B, and the second terminal is connected to the second level signal LVGL terminal; the control terminal and the first terminal of the thirteenth transistor M13 are both connected to... The control terminal of the fourteenth transistor M14 is connected to the second power supply signal terminal VDD2, and its second terminal is connected to the second pull-down control node PD_CNB; the control terminal of the fifteenth transistor M15 is connected to the frame start signal terminal STV0, its first terminal is connected to the clock signal terminal, and its second terminal is connected to the cascade terminal; the control terminal of the sixteenth transistor M16 is connected to the first pull-down node PD_A, and its second terminal is connected to the second level signal LVGL terminal; the control terminal of the seventeenth transistor M17 is connected to the second pull-down node PD_B, and its second terminal is connected to the second level signal LVGL terminal.The control electrode of the eighteenth transistor M18 is connected to the pull-up node PU, the first electrode is connected to the first clock signal terminal CLKA, and the second electrode is connected to the signal output terminal GoutN; the control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD_A, the first electrode is connected to the signal output terminal GoutN, and the second electrode is connected to the third level signal terminal VGL; the twentieth transistor M20; the control electrode of the twentieth transistor M20 is connected to the second pull-down node PD_B, the first electrode is connected to the signal output terminal GoutN, and the second electrode is connected to the third level signal terminal VGL; the control electrode of the twenty-first transistor M21 is connected to the pull-up node PU, the first electrode is connected to the first clock signal terminal CLKA, and the second electrode is connected to the signal output terminal GoutN; one electrode of the first storage capacitor C1 is connected to the pull-up node PU, and the other electrode is connected to the signal output terminal GoutN. The control electrode of transistor M22 is connected to the third signal input terminal PD_F, its first electrode is connected to the first pull-down control node PD_CNA, and its second electrode is connected to the second-level signal LVGL terminal. Similarly, the control electrode of transistor M23 is connected to the third signal input terminal PD_F, its first electrode is connected to the second pull-down control node PD_CNB, and its second electrode is connected to the second-level signal LVGL terminal. Transistor M22 is configured to transmit the second-level signal LVGL to the first pull-down control node PD_CNA under the control of the third input signal.

[0185] It should be noted that, in this embodiment, the first input signal input to the first signal input terminal is the cascade signal terminal of the four shift register units above the current shift register unit (if the current shift register unit is the Nth level, then it is connected to the cascade signal terminal of the N-4th level shift register unit). The second input signal connected to the second signal input terminal is the cascade signal terminal of the four shift register units below the current shift register unit (the cascade signal terminal of the N+4th level). The third input signal input to the third signal input terminal is the cascade signal terminal of the five shift register units above (the cascade signal terminal of the N-5th level). That is, when the shift register unit in the N-5th row outputs a high level, the pull-down node and pull-down control node of the Nth level are pulled low. This can reduce the complexity of the circuit while ensuring that the circuit function is not affected, reduce the bezel of the display panel to 200 micrometers, and thus improve the screen ratio.

[0186] The second example works in the same way as the first example. The difference is that when the shift register unit in row N-5 outputs a high level, it can not only pull down the voltage of the pull-down node, but also pull down the voltage of the pull-down control node, further improving the competition relationship between the pull-up node PU and the pull-down node.

[0187] Referring to Figure 7d, which shows a third example of the shift register unit provided in this disclosure, this example differs from the second example in Figure 7c in that the clock signals connected to the first terminal of the eighteenth transistor M18 in the cascaded circuit and the first terminal of the twenty-first transistor M21 in the output circuit are different. The former is connected to the second clock signal terminal CLKB, and the latter is connected to the first clock signal terminal CLKA. That is, the signal output terminal GoutN of the shift register unit outputs the first clock signal CLKA, and the cascaded signal terminal OC N outputs the second clock signal CLKB. This design increases the versatility of the circuit. In addition, the first input signal at the first signal input terminal Input, the second input signal at the second signal input terminal Reset, and the third input signal at the third signal input terminal PD_F are all different from those in the second example. The first signal input terminal Input is connected to the signal output terminal GoutN of the upper four-stage shift register unit (the signal output terminal GoutN of the N-4th stage), the second signal input terminal Reset is connected to the signal output terminal GoutN of the lower four-stage shift register unit (the signal output terminal GoutN of the N+4th stage), and the third signal input terminal PD_F is connected to the cascaded signal terminal OC N of the upper four-stage shift register unit (the cascaded signal terminal OC N of the N-4th stage).

[0188] The other circuit structures and working principles of the third example are the same as those of the second example, and will not be repeated here.

[0189] Secondly, this disclosure provides a driving method for a display panel, and Figure 8 shows a flowchart of the driving method. As shown in Figure 8, the driving method includes steps S801 to S803.

[0190] Step S801: The timing controller applies a frame start signal and multiple clock signals to the gate drive circuit; the clock signals enable the charging time of odd-numbered row sub-pixels to be greater than the charging time of even-numbered row sub-pixels.

[0191] Step S802: The gate driving circuit outputs multiple gate driving signals to the sub-pixel array based on the frame start signal and multiple clock signals. These gate driving signals are used to scan the sub-pixel array row by row to turn on each scanned row of sub-pixels, ensuring that the duration for which two adjacent rows of sub-pixels are simultaneously turned on is greater than or equal to twice the unit scan time. For example, the unit scan time is the time required to scan one row of sub-pixels. The sub-pixel array includes multiple sub-pixels arranged in an N×M array, where N and M are both integers greater than 1. The gate driving circuit includes N shift register units connected to the N rows of sub-pixels in the sub-pixel array, each shift register unit connected to at least one clock signal line for transmitting clock signals; the gate driving circuit also includes multiple sets of alternately cascaded shift register groups.

[0192] Step S803: The source drive circuit applies a data signal to at least two rows of sub-pixels that are simultaneously in the on state, such that the duration for which the data signal is applied to at least some of the rows of sub-pixels is greater than the unit scan time.

[0193] For example, multiple clock signals can include eight clock signals. N shift register units are divided into multiple groups according to their arrangement, with each group containing eight shift register units. Each group of eight shift register units receives eight clock signals. For example, the gate drive circuit, frame start signal, clock signal, gate drive signal, data signal, etc., can be referred to in Figures 1, 2A, and 2B as described above, and will not be repeated here.

[0194] For example, in the first time period, the nth row of subpixels and the (n+1th row of subpixels) are turned on sequentially, where n is an integer and 1≤n≤N-3; in the second time period, the (n+2th row of subpixels) and the (n+3th row of subpixels) are turned on sequentially, and one of the nth row data signal and the (n+1th row data signal) is applied to the nth row of subpixels and the (n+1th row of subpixels), and the length of the second time period is greater than or equal to twice the unit scan time; in the third time period, the nth row of subpixels is turned off, and one of the (n+2th row of data signal and the (n+3rd row data signal) is applied to the (n+1th row of subpixels), the (n+2th row of subpixels), and the (n+3rd row of subpixels).

[0195] Figure 9a is a schematic diagram illustrating the extraction of even-numbered rows of data from an initial data frame according to at least one embodiment of this disclosure. Figure 9b is a schematic diagram illustrating the extraction of odd-numbered rows of data from an initial data frame according to at least one embodiment of this disclosure. As shown in Figures 9a and 9b, odd-numbered rows of data from an initial data frame can be extracted to form a first target data frame, and even-numbered rows of data from the initial data frame can be extracted to form a second target data frame. Alternatively, odd-numbered rows of data from an initial data frame can be extracted to form a second target data frame, and even-numbered rows of data from the initial data frame can be extracted to form a first target data frame. By decomposing a data frame into odd-numbered and even-numbered frames, and displaying two frames of data using the time originally required to display one frame, the refresh rate of the display panel can be increased, thereby improving the display effect. For ease of description, in some embodiments below, odd-numbered frames and even-numbered frames are used to represent the first target data frame and the second target data frame.

[0196] For example, multiple initial data frames include adjacent first and second initial data frames. In the first frame, a first target data frame corresponding to the first initial data frame is applied to the subpixel array; in the second frame, a second target data frame corresponding to the first initial data frame is applied to the subpixel array; in the third frame, a first target data frame corresponding to the second initial data frame is applied to the subpixel array; and in the fourth frame, a second target data frame corresponding to the second initial data frame is applied to the subpixel array. In this manner, the first and second target data frames are displayed alternately.

[0197] Figure 10 is a schematic diagram illustrating the extraction of even-numbered rows of data from an initial data frame according to at least one embodiment of this disclosure. As shown in Figure 10, in Mode 1 and Mode 2, a first target data frame and a second target data frame are displayed alternately. The first initial data frame consists of an odd-numbered frame b1 and an even-numbered frame c1, the second initial data frame consists of an odd-numbered frame b2 and an even-numbered frame c2, the third initial data frame consists of an odd-numbered frame b3 and an even-numbered frame c3, and so on. In Mode 1, odd-numbered frames b can be displayed first, followed by even-numbered frames c, for example, in the order of b1~c1~b2~c2~b3~c3… In Mode 2, even-numbered frames c can be displayed first, followed by odd-numbered frames b, for example, in the order of c1~b1~c2~b2~c3~b3…

[0198] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the subpixel array; in the second frame, data of the second target data frame corresponding to the first initial data frame is applied to the subpixel array; in the third frame, data of the second target data frame corresponding to the second initial data frame is applied to the subpixel array; and in the fourth frame, data of the first target data frame corresponding to the second initial data frame is applied to the subpixel array.

[0199] For example, as shown in Figure 10, in modes 3 and 4, the odd and even frames corresponding to each initial data frame are displayed consecutively, and two adjacent odd frames and two adjacent even frames are displayed consecutively. In mode 3, they are displayed in the order b1~c1~c2~b2~b3~c3… In mode 4, they are displayed in the order c1~b1~b2~c2~c3~b3… The driving method for odd frames can be the same, and the driving method for even frames can be the same. By displaying adjacent odd frames consecutively and adjacent even frames consecutively, repeated switching of driving methods can be avoided, improving efficiency and saving power consumption.

[0200] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; and in the fourth frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0201] For example, as shown in Figure 10, in modes 5 and 6, odd-numbered frames of two adjacent initial data frames are displayed consecutively, as are even-numbered frames of two adjacent initial data frames. Each initial data frame is separated into odd and even frames. In mode 5, the frames are displayed in the order b1~b2~c1~c2~b3~b4… In mode 6, the frames are displayed in the order c1~c2~b1~b2~c3~c4… The driving methods for odd-numbered frames and even-numbered frames can be the same. By displaying adjacent odd-numbered frames consecutively and adjacent even-numbered frames consecutively, repeated switching of driving methods can be avoided, improving efficiency and saving power.

[0202] For example, the period during which each row of subpixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to twice the unit scan time, and the duration of the pre-charging period is greater than or equal to the unit scan time.

[0203] For example, the duration of each row of subpixels in the on state is 3.2 times the unit scan time, the duration of the pre-charge period is 1.2 times the unit scan time, and the start and end times of the periods when two adjacent rows of subpixels are in the on state differ by a unit scan time.

[0204] Figure 10 shows a signal timing diagram of a driving method according to an embodiment of the present disclosure. In Figure 10, the time period during which each row of sub-pixels is in the on state (the corresponding gate driving signals, such as G1-G6, are at a high level) includes a charging period and a pre-charging period before the charging period. The duration of the charging period is equal to twice the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 10, the duration of each row of sub-pixels in the on state is 3.2H, where the first 1.2H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, the duration of which is equal to the unit scan time H. For example, the first pre-charging period is a period before and immediately adjacent to the charging period, and the duration of this period is 1H, that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0205] For example, in some embodiments, as shown in FIG10, the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time H; correspondingly, the start and end times of the pre-charging periods of adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be as follows: during the charging period of the (2k-1)th row sub-pixel, apply one of the (2k-1)th row data signal and the 2kth row data signal to the (2k-1)th row sub-pixel; during the first pre-charging period of the (2k-1)th row sub-pixel and the first half of the charging period of the (2k-1)th row sub-pixel, apply one of the (2k-1)th row data signal and the 2(k+1)th row data signal to the (2k-1)th row sub-pixel; and during the first pre-charging period (or the entire pre-charging period) of the (2k-1)th row sub-pixel, apply one of the (2k-1)th row data signal and the 2kth row data signal to the (2k+1)th row sub-pixel; where k = 1, 2, 3, ...

[0206] For example, as shown in Figure 10, when displaying odd-numbered frames, the first row data signal is applied to the first row sub-pixels during the charging period of the first row sub-pixels; the first row data signal is applied to the second row sub-pixels during the first pre-charging period and the first half of the charging period of the second row sub-pixels; the third row data signal is applied to the second row sub-pixels during the second half of the charging period of the second row sub-pixels; the first row data signal is applied to the third row sub-pixels during the first pre-charging period (or the entire pre-charging period) of the third row sub-pixels; the third row data signal is applied to the third row sub-pixels during the charging period of the third row sub-pixels; and so on.

[0207] For example, in one specific embodiment, as shown in Figure 10, the duration of each row of sub-pixels in the on state is 3.2 times the unit scan time H (i.e., 3.2H), where the first 1.2H is the pre-charging period and the last 2H is the charging period. The start and end times of the on state periods of two adjacent rows of sub-pixels differ by a unit scan time H; correspondingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be:

[0208] During the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-5 is applied to the sub-pixels in row 6k-5.

[0209] During the first pre-charging period of the 6k-4 row sub-pixels and the first half of the charging period of the 6k-4 row sub-pixels, the 6k-5 row data signal is applied to the 6k-4 row sub-pixels; during the second half of the charging period of the 6k-4 row sub-pixels, the 6k-3 row data signal is applied to the 6k-4 row sub-pixels.

[0210] During the first pre-charge period (or the entire pre-charge period) of the 6k-3 row sub-pixel, the 6k-5 row data signal is applied to the 6k-3 row sub-pixel; during the charging period of the 6k-3 row sub-pixel, the 6k-3 row data signal is applied to the 6k-3 row sub-pixel.

[0211] During the first pre-charging period of the 6k-2 row sub-pixel and the first half of the charging period of the 6k-2 row sub-pixel, the 6k-3 row data signal is applied to the 6k-2 row sub-pixel; during the second half of the charging period of the 6k-2 row sub-pixel, the 6k-1 row data signal is applied to the 6k-2 row sub-pixel.

[0212] During the first pre-charge period (or the entire pre-charge period) of the 6k-1 row sub-pixel, the 6k-3 row data signal is applied to the 6k-1 row sub-pixel; during the charging period of the 6k-1 row sub-pixel, the 6k-1 row data signal is applied to the 6k-1 row sub-pixel.

[0213] During the first pre-charging period of the 6k row sub-pixel and the first half of the charging period of the 6k row sub-pixel, the 6k-1 row data signal is applied to the 6k row sub-pixel; during the second half of the charging period of the 6k row sub-pixel, the 6k+1 row data signal is applied to the 6k row sub-pixel.

[0214] Where k = 1, 2, 3, ...

[0215] Figure 11 shows a signal timing diagram of a driving method according to another embodiment of the present disclosure. In Figure 11, the time period during which each row of sub-pixels is in the on state 1 includes a charging period and a pre-charging period preceding the charging period, wherein the duration of the charging period is equal to twice the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 11, the duration of each row of sub-pixels in the on state is 3.2H, wherein the first 1.2H is the pre-charging period, and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, the duration of which is equal to the unit scan time H. For example, the first pre-charging period is a period preceding and immediately adjacent to the charging period, and the duration of this period is 1H.

[0216] For example, in some embodiments, as shown in FIG11, the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time H; correspondingly, the start and end times of the pre-charging periods of adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be:

[0217] During the latter half of the charging period of the sub-pixel in row 2k-1, one of the data signals of row 2k-1 and row 2k is applied to the sub-pixel in row 2k-1.

[0218] During the charging period of the 2kth row sub-pixel, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row sub-pixel;

[0219] During the first pre-charging period and the first half of the charging period of the 2k+1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k+1 row sub-pixel; during the second half of the charging period of the 2k+1 row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k+1 row sub-pixel; and

[0220] During the first pre-charge period (or the entire pre-charge period) of the 2(k+1) row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2(k+1) row sub-pixel; during the charging period of the 2(k+1) row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2(k+1) row sub-pixel.

[0221] Where k = 1, 2, 3, ...

[0222] For example, in some examples, as shown in Figure 11, when displaying even-numbered frames, the second row data signal is applied to the first row sub-pixels during the latter half of the charging period; the second row data signal is applied to the second row sub-pixels during the charging period; the second row data signal is applied to the third row sub-pixels during the first pre-charging period and the first half of the charging period; the fourth row data signal is applied to the third row sub-pixels during the latter half of the charging period; the second row data signal is applied to the fourth row sub-pixels during the first pre-charging period (or the entire pre-charging period); the fourth row data signal is applied to the fourth row sub-pixels during the charging period; and so on.

[0223] For example, in one specific embodiment, as shown in Figure 11, the duration for which each row of sub-pixels is in the on state is 3.2 times the unit scan time H (i.e., 3.2H), where the first 1.2H is the pre-charging period and the last 2H is the charging period. The start and end times of the on state periods of two adjacent rows of sub-pixels differ by a unit scan time H; correspondingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be:

[0224] During the latter half of the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-5.

[0225] During the charging period of the sub-pixels in row 6k-4, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-4;

[0226] During the first pre-charging period of the 6k-3 row sub-pixel and the first half of the charging period of the 6k-3 row sub-pixel, the 6k-4 row data signal is applied to the 6k-3 row sub-pixel; during the second half of the charging period of the 6k-3 row sub-pixel, the 6k-2 row data signal is applied to the 6k-3 row sub-pixel.

[0227] During the first pre-charge period (or the entire pre-charge period) of the 6k-2 row sub-pixel, the 6k-4 row data signal is applied to the 6k-2 row sub-pixel; during the charging period of the 6k-2 row sub-pixel, the 6k-2 row data signal is applied to the 6k-2 row sub-pixel.

[0228] During the first pre-charging period of the 6k-1 row sub-pixel and the first half of the charging period of the 6k-1 row sub-pixel, the 6k-2 row data signal is applied to the 6k-1 row sub-pixel; during the second half of the charging period of the 6k-1 row sub-pixel, the 6k row data signal is applied to the 6k-1 row sub-pixel.

[0229] During the first pre-charge period (or the entire pre-charge period) of the 6k row sub-pixel, the 6k-2 row data signal is applied to the 6k row sub-pixel; during the charging period of the 6k row sub-pixel, the 6k row data signal is applied to the 6k row sub-pixel.

[0230] Where k = 1, 2, 3, ...

[0231] In the above embodiments, pre-charging can achieve charging improvement because the data signal hardly needs to consider the rise delay, and the difference between adjacent data signals is small, thereby displaying good image quality of the display device.

[0232] For example, in the above embodiments, the duration for which a data signal is applied to each row of sub-pixels is greater than the unit scan time; or, the duration for which a data signal is applied to the first row of sub-pixels is equal to the unit scan time, and the duration for which a data signal is applied to each row of sub-pixels other than the first row of sub-pixels is greater than the unit scan time.

[0233] It should be understood that, in the embodiments of this disclosure, the charging period and the pre-charging period are two different (sub)periods in the period when each row of sub-pixels is in the on state. Part or all of the pre-charging period of a certain row or several rows of sub-pixels may not be pre-charged, and the first half of the charging period of the first row of sub-pixels may not be charged.

[0234] The embodiments of this disclosure enable each row of sub-pixels sequentially and apply data signals to each row of sub-pixels that are simultaneously enabled, so that the actual charging time (the total time of the pre-charging period and the charging period) of some sub-pixels can reach 2H or higher.

[0235] In some embodiments, a subset of subpixels and another subset of subpixels can be driven in different ways in different frames, such that the actual charging time of each subpixel in at least one frame is greater than the unit scan time.

[0236] The above embodiments are described with the gate drive circuit connected to 8 CLK signals. In other embodiments, the gate drive circuit can be connected to 12 CLK signals, which will be described below.

[0237] Figure 12 shows a timing diagram of another frame start signal and clock signal according to an embodiment of the present disclosure.

[0238] As shown in Figure 12, the high-level duration t1 of the frame start signal STV is 9H, the high-level duration t3 of the clock signal CLK is 5H, the period t4 of the clock signal CLK is 12H, the phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the first clock signal CLK1 is 4H, the phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is 0H, and the clock signals CLK are sequentially separated by a phase difference T5 of 1H. The duty cycle of the clock signal CLK is 41.6%, mainly selected to consider in-plane signal coupling or display defects. The phase difference between the falling edge of STV and the falling edge of CLK1 is 0H. Because STV connects the first 6 CLKs, STV generates a first-order PU level, so the falling edge of STV is aligned with the rising edge of CLK6. That is, after STV ends, CLK immediately starts to rise, generating a second-order PU, which fully controls the GOA output and avoids leakage at the PU point.

[0239] Figure 13 illustrates a signal timing diagram of another driving method according to an embodiment of the present disclosure. In Figure 13, the time period during which each row of sub-pixels is in the on state includes a charging period and a pre-charging period preceding the charging period, wherein the duration of the charging period is equal to twice the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 14, the duration of each row of sub-pixels in the on state is 5H, where the first 3H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, the duration of which is equal to the unit scan time H. For example, the first pre-charging period is a period preceding and immediately adjacent to the charging period, and its duration is 1H; that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0240] For example, in some embodiments, as shown in FIG14, the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time H; correspondingly, the start and end times of the pre-charging periods of adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be:

[0241] During the charging period of the sub-pixel in row 2k-1, one of the data signal in row 2k-1 and the data signal in row 2k is applied to the sub-pixel in row 2k-1;

[0242] During the first pre-charge period of the 2k-row sub-pixel and the first half of the charging period of the 2k-row sub-pixel, one of the 2k-1 row data signal and the 2k-row data signal is applied to the 2k-row sub-pixel; during the second half of the charging period of the 2k-row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k-row sub-pixel; and

[0243] During the first pre-charge period of the sub-pixel in row 2k+1, one of the data signals of row 2k-1 and row 2k is applied to the sub-pixel in row 2k+1; where k = 1, 2, 3, ...

[0244] For example, in one specific embodiment, as shown in Figure 14, the driving method can be:

[0245] During the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-5 is applied to the sub-pixels in row 6k-5.

[0246] During the first pre-charging period of the 6k-4 row sub-pixels and the first half of the charging period of the 6k-4 row sub-pixels, the 6k-5 row data signal is applied to the 6k-4 row sub-pixels; during the second half of the charging period of the 6k-4 row sub-pixels, the 6k-3 row data signal is applied to the 6k-4 row sub-pixels.

[0247] During the first pre-charging period of the 6k-3 row sub-pixel, the 6k-5 row data signal is applied to the 6k-3 row sub-pixel; during the charging period of the 6k-3 row sub-pixel, the 6k-3 row data signal is applied to the 6k-3 row sub-pixel.

[0248] During the first pre-charging period of the 6k-2 row sub-pixel and the first half of the charging period of the 6k-2 row sub-pixel, the 6k-3 row data signal is applied to the 6k-2 row sub-pixel; during the second half of the charging period of the 6k-2 row sub-pixel, the 6k-1 row data signal is applied to the 6k-2 row sub-pixel.

[0249] During the first pre-charging period of the 6k-1 row sub-pixel, the 6k-3 row data signal is applied to the 6k-1 row sub-pixel; during the charging period of the 6k-1 row sub-pixel, the 6k-1 row data signal is applied to the 6k-1 row sub-pixel.

[0250] During the first pre-charging period of the 6k row sub-pixel and the first half of the charging period of the 6k row sub-pixel, the 6k-1 row data signal is applied to the 6k row sub-pixel; during the second half of the charging period of the 6k row sub-pixel, the 6k+1 row data signal is applied to the 6k row sub-pixel.

[0251] Where k = 1, 2, 3, ...

[0252] Figure 15 illustrates a signal timing diagram of another driving method according to an embodiment of the present disclosure. In Figure 15, the time period during which each row of sub-pixels is in the on state includes a charging period and a pre-charging period preceding the charging period, wherein the duration of the charging period is equal to twice the unit scan time H, and the duration of the pre-charging period is greater than or equal to the unit scan time H. For example, in Figure 15, the duration of each row of sub-pixels in the on state is 5H, where the first 3H is the pre-charging period and the last 2H is the charging period. The pre-charging period of each row of sub-pixels includes a first pre-charging period, the duration of which is equal to the unit scan time H. For example, the first pre-charging period is a period preceding and immediately adjacent to the charging period, and its duration is 1H; that is, the first pre-charging period is the last unit scan time in the pre-charging period.

[0253] For example, in some embodiments, as shown in Figure 15, the start and end times of the periods when adjacent rows of sub-pixels are in the on state differ by a unit scan time H; correspondingly, the start and end times of the pre-charging periods of adjacent rows of sub-pixels differ by a unit scan time H, and the start and end times of the charging periods of adjacent rows of sub-pixels differ by a unit scan time H. In this case, the driving method can be:

[0254] During the latter half of the charging period of the sub-pixel in row 2k-1, one of the data signals of row 2k-1 and row 2k is applied to the sub-pixel in row 2k-1.

[0255] During the charging period of the 2kth row sub-pixel, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row sub-pixel;

[0256] During the first pre-charging period and the first half of the charging period of the 2k+1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k+1 row sub-pixel; during the second half of the charging period of the 2k+1 row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k+1 row sub-pixel; and

[0257] During the first pre-charge period (or the entire pre-charge period) of the 2(k+1) row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2(k+1) row sub-pixel; during the charging period of the 2(k+1) row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2(k+1) row sub-pixel.

[0258] Where k = 1, 2, 3, ...

[0259] For example, in one specific embodiment, as shown in Figure 15, the driving method can be:

[0260] During the latter half of the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-5.

[0261] During the charging period of the sub-pixels in row 6k-4, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-4;

[0262] During the first pre-charging period of the 6k-3 row sub-pixel and the first half of the charging period of the 6k-3 row sub-pixel, the 6k-4 row data signal is applied to the 6k-3 row sub-pixel; during the second half of the charging period of the 6k-3 row sub-pixel, the 6k-2 row data signal is applied to the 6k-3 row sub-pixel.

[0263] During the first pre-charge period (or the entire pre-charge period) of the 6k-2 row sub-pixel, the 6k-4 row data signal is applied to the 6k-2 row sub-pixel; during the charging period of the 6k-2 row sub-pixel, the 6k-2 row data signal is applied to the 6k-2 row sub-pixel.

[0264] During the first pre-charging period of the 6k-1 row sub-pixel and the first half of the charging period of the 6k-1 row sub-pixel, the 6k-2 row data signal is applied to the 6k-1 row sub-pixel; during the second half of the charging period of the 6k-1 row sub-pixel, the 6k row data signal is applied to the 6k-1 row sub-pixel.

[0265] During the first pre-charge period (or the entire pre-charge period) of the 6k row sub-pixel, the 6k-2 row data signal is applied to the 6k row sub-pixel; during the charging period of the 6k row sub-pixel, the 6k row data signal is applied to the 6k row sub-pixel.

[0266] Where k = 1, 2, 3, ...

[0267] In the above embodiments, pre-charging can achieve charging improvement because the data signal hardly needs to consider the rise delay, and the difference between adjacent data signals is small, thereby displaying good image quality of the display device.

[0268] At least one embodiment of this disclosure also provides a display device, which includes the display panel of the above embodiments. The display device can be any device such as a mobile phone, tablet computer, laptop computer, e-book reader, game console, television, digital photo frame, or navigator, or any combination of electronic devices and hardware; the embodiments of this disclosure do not limit this.

[0269] It should be noted that, for clarity and brevity, this disclosure does not show all the constituent units of the display device. To achieve the necessary functions of the electronic device, those skilled in the art can provide and set other constituent units (not shown) according to specific needs, and this disclosure does not limit this.

[0270] For a description of the display device and its technical effects, please refer to the description of the frequency divider provided in the embodiments of this disclosure, which will not be repeated here.

[0271] The following points need to be explained:

[0272] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0273] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0274] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display panel, comprising a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array comprising a plurality of sub-pixels arranged in an N*M array, wherein N and M are both integers greater than 1; The timing controller is configured to provide a frame start signal and multiple clock signals to the gate driving circuit; the gate driving circuit is configured to provide multiple gate driving signals to the sub-pixel array based on the frame start signal and the multiple clock signals, and to scan the sub-pixel array row by row using the multiple gate driving signals to turn on each scanned row of sub-pixels, such that the duration for which two adjacent rows of sub-pixels are simultaneously in the turned-on state is greater than or equal to twice the unit scan time, where the unit scan time is the time required to scan one row of sub-pixels; the source driving circuit is configured to provide data signals to the sub-pixels in the turned-on state; wherein... The gate driving circuit includes N shift register units that are respectively connected to N rows of sub-pixels of the sub-pixel array, and each shift register unit is connected to at least one clock signal line for transmitting clock signals; The timing controller is configured such that the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing real data is greater than the effective level duration of the clock signal provided to the clock signal line corresponding to the sub-pixel row for writing interpolated data.

2. The display panel of claim 1, wherein, The subpixel rows that are written with real data and the subpixel rows that are written with interpolated data are set alternately.

3. The display panel according to claim 1, wherein, The N shift register units include a first-stage shift register unit connected to the first row of sub-pixels in the sub-pixel array; the plurality of clock signals include a first clock signal for driving the first-stage shift register unit to output a gate drive signal; The rising edge of the frame start signal is earlier than the rising edge of the first clock signal, and the falling edge of the frame start signal is no later than the falling edge of the first clock signal. The phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scan time and less than or equal to 0.6 times the unit scan time.

4. The display panel according to claim 3, wherein, The first-stage shift register unit to the p-th-th-stage shift register unit in the N shift register units are connected to the frame start signal; the plurality of clock signals also include a p-th clock signal for driving the output gate drive signal of the p-th-th-stage shift register unit; The duty cycle of each clock signal is greater than or equal to 40% and less than or equal to 45%, and the phase difference and the duty cycle are configured such that the falling edge of the frame start signal is aligned with the rising edge of the p-th clock signal, where p is an integer greater than 1.

5. The display panel according to claim 4, wherein, The phase difference between the rising edges of any two adjacent clock signals in the plurality of clock signals is the unit scan time, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%.

6. The display panel according to any one of claims 1-5, wherein, The period during which each row of subpixels is in the on state includes a charging period and a pre-charging period before the charging period, wherein the duration of the charging period is equal to twice the unit scan time, and the duration of the pre-charging period is greater than or equal to the unit scan time.

7. The display panel according to claim 1, wherein, The gate driving circuit includes m gate driving sub-circuits, and the gate driving sub-circuit includes 4n shift register units, where 1≤m≤6 and 1≤n≤4; m and n are both integers. The gate drive sub-circuit includes a first shift register group and a second shift register group; one of the first shift register group and the second shift register group includes each odd-numbered shift register unit in 4n shift register units, and the other includes each even-numbered shift register unit. Each of the 4n adjacent shift register units is connected to one of the 4n clock signal lines, and the i-th shift register unit is connected to the same clock signal line as the (i+4n)-th shift register; i ranges from 1 to N-4n.

8. The display panel according to claim 7, wherein, The gate driving circuit includes a gate driving sub-circuit, which includes eight shift register units. The signal input terminals of the first to fourth shift register units respond to the frame start signal; the signal output terminal of the a-th shift register unit is connected to the signal input terminal of the (a+4)-th shift register unit; the frame start signal terminal of the b-th shift register unit is connected to the signal output terminal of the (b+4)-th shift register unit; 1≤a≤4, 1≤b≤4.

9. The display panel according to claim 3, wherein, The gate driving circuit includes a gate driving sub-circuit, and the gate driving sub-circuit includes 12 of the shift register units; The signal input terminals of the 1st to 6th shift register units respond to the frame start signal; the signal output terminal of the ath shift register unit is connected to the signal input terminal of the (a+6th)th shift register unit; the frame start signal terminal STV0 of the bth shift register unit is connected to the signal output terminal of the (b+6th)th shift register unit; 1≤a≤6, 1≤b≤6.

10. The display panel according to claim 1, wherein, The shift register unit includes: The input circuit is configured to transmit a first-level signal to the pull-up node under the control of the first input signal; The first reset circuit is configured to transmit a second-level signal to the pull-up node under the control of the second input signal; The first pull-down circuit is configured to transmit the second level signal to the pull-down node under the control of the third input signal; The second pull-down circuit is configured to transmit the second level signal to the pull-up node under the control of the pull-down node voltage; The first pull-down control circuit is configured to transmit the second level signal to the pull-down control node and the pull-down node under the control of the pull-up node voltage; The second pull-down control circuit is configured to transmit the power signal to the pull-down node and the pull-down control node under the control of the power signal; The second reset circuit is configured to reset the pull-up node under the control of a reset signal; The third pull-down circuit is configured to transmit the second level signal to the cascade terminal under the control of the pull-down node voltage; The fourth pull-down circuit is configured to transmit a third-level signal to the signal output terminal under the control of the pull-down node; The output circuit is configured to transmit the clock signal to the signal output terminal under the control of the pull-up node voltage; The cascaded circuit is configured to transmit the clock signal to the cascaded terminal under the control of the pull-up node voltage.

11. The display panel according to claim 10, wherein, The power signal includes a first power signal and a second power signal; the first power signal and the second power signal are signals with the same frequency but opposite direction.

12. The display panel according to claim 11, wherein, The input circuit includes a first transistor; the control electrode of the first transistor is connected to a first signal input terminal, the first electrode is connected to a first level signal terminal, and the second electrode is connected to the pull-up node.

13. The display panel according to claim 11, wherein, The first reset circuit includes a second transistor; the control electrode of the second transistor is connected to the second signal input terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal.

14. The display panel according to claim 11, wherein, The drop-down node includes a first drop-down node, and the drop-down control node includes a first drop-down node; The first pull-down control circuit includes: a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is connected to the pull-up node, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal; the control electrode of the eighth transistor is connected to the pull-up node, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal. The second pull-down control circuit includes: a ninth transistor and a tenth transistor; The control electrode and the first electrode of the ninth transistor are both connected to the first power signal terminal, and the second electrode is connected to the first pull-down control node; the control electrode of the tenth transistor is connected to the first pull-down control node, the first electrode is connected to the first power signal terminal, and the second electrode is connected to the first pull-down node.

15. The display panel according to claim 14, wherein, The drop-down node further includes a second drop-down node, and the drop-down control node further includes a second drop-down node; The first pull-down control circuit also includes: an eleventh transistor and a twelfth transistor; The control electrode of the eleventh transistor is connected to the pull-up node, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal; the control electrode of the twelfth transistor is connected to the pull-up node, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal. The second pull-down control circuit also includes: a thirteenth transistor and a fourteenth transistor; The control electrode and the first electrode of the thirteenth transistor are both connected to the second power signal terminal, and the second electrode is connected to the second pull-down control node; the control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode is connected to the second power signal terminal, and the second electrode is connected to the second pull-down node.

16. The display panel according to claim 11, wherein, The drop-down node includes a first drop-down node; The first pull-down circuit includes a fourth transistor; the control electrode of the fourth transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal. The second pull-down circuit includes a sixth transistor; the control electrode of the sixth transistor is connected to the first pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal. The third pull-down circuit includes a sixteenth transistor; the control electrode of the sixteenth transistor is connected to the first pull-down node, and the second electrode is connected to the second level signal terminal; The fourth pull-down circuit includes a nineteenth transistor; the control stage of the nineteenth transistor is connected to the first pull-down node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the third level signal terminal.

17. The display panel according to claim 16, wherein, The drop-down node also includes a second drop-down node; The first pull-down circuit further includes a third transistor; the control electrode of the third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal. The second pull-down circuit further includes a fifth transistor; the control electrode of the fifth transistor is connected to the second pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the second level signal terminal; The third pull-down circuit also includes a seventeenth transistor; The control electrode of the seventeenth transistor is connected to the second pull-down node, and the second electrode is connected to the second level signal terminal. The fourth pull-down circuit also includes a twentieth transistor; the control stage of the twentieth transistor is connected to the second pull-down node, the first terminal is connected to the signal output terminal, and the second terminal is connected to the third level signal terminal.

18. The display panel according to claim 11, wherein, The second reset circuit includes a fifteenth transistor; the control terminal of the fifteenth transistor is connected to the frame start signal terminal STV0, the first terminal is connected to the clock signal terminal, and the second terminal is connected to the cascade terminal.

19. The display panel according to claim 11, wherein, The output circuit includes a twenty-first transistor and a first storage capacitor; The control electrode of the 21st transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal; one electrode of the first storage capacitor is connected to the pull-up node, and the other electrode is connected to the signal output terminal.

20. The display panel according to claim 11, wherein, The cascaded circuit includes an eighteenth transistor; the control electrode of the eighteenth transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal.

21. The display panel according to claim 10, wherein, The shift register unit further includes a third pull-down control circuit; the third pull-down control circuit is configured to transmit a second level signal to the pull-down control node under the control of a third input signal.

22. The display panel according to claim 21, wherein, The drop-down control node includes a first drop-down control node; The third pull-down control circuit includes a twenty-second transistor; the control electrode of the twenty-second transistor is connected to the third signal input terminal, the first electrode is connected to the first pull-down control node, and the second electrode is connected to the second level signal terminal.

23. The display panel according to claim 22, wherein, The drop-down control node also includes a second drop-down control node; The third pull-down control circuit package also includes a twenty-third transistor; the control electrode of the twenty-third transistor is connected to the third signal input terminal, the first electrode is connected to the second pull-down control node, and the second electrode is connected to the second level signal terminal.

24. A method for driving a display panel, wherein, The display panel includes a timing controller, a gate driving circuit, and a source driving circuit; the method includes: The timing controller applies a frame start signal and multiple clock signals to the gate drive circuit; the timing controller is configured such that the effective level duration of the clock signal provided by the clock signal line corresponding to the odd-numbered rows of sub-pixels is greater than the effective level duration of the clock signal provided by the clock signal line corresponding to the even-numbered rows of sub-pixels. The gate driving circuit outputs multiple gate driving signals to the sub-pixel array based on the frame start signal and the multiple clock signals. It uses these multiple gate driving signals to scan the sub-pixel array row by row, turning on each scanned row of sub-pixels, such that the duration for which two adjacent rows of sub-pixels are simultaneously turned on is greater than or equal to twice the unit scan time. The unit scan time is the time required to scan one row of sub-pixels. The sub-pixel array includes multiple sub-pixels arranged in an N×M array, where N and M are both integers greater than 1. The gate driving circuit includes... The circuit includes N shift register units respectively connected to N rows of sub-pixels of the sub-pixel array, each shift register unit being connected to at least one clock signal line for transmitting a clock signal; the gate drive circuit includes multiple sets of alternately cascaded shift register groups; and The source drive circuit applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, such that the duration for which data signals are applied to at least some of the rows of sub-pixels is greater than the unit scan time.

25. The driving method according to claim 22, wherein, The pre-charge period of each row of sub-pixels includes a first pre-charge period, which is the last unit scan time in the pre-charge period. The start and end times of the periods when two adjacent rows of sub-pixels are in the on state differ by a unit scan time. Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes: During the charging period of the sub-pixel in row 2k-1, one of the data signal in row 2k-1 and the data signal in row 2k is applied to the sub-pixel in row 2k-1; During the first pre-charge period of the 2k-row sub-pixel and the first half of the charging period of the 2k-row sub-pixel, one of the 2k-1 row data signal and the 2k-row data signal is applied to the 2k-row sub-pixel; during the second half of the charging period of the 2k-row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k-row sub-pixel; and During the first pre-charge period of the sub-pixel in row 2k+1, one of the data signals from row 2k-1 and row 2k is applied to the sub-pixel in row 2k+1; Where k = 1, 2, 3, ...

26. The driving method according to claim 24, wherein, The pre-charge period of each row of sub-pixels includes a first pre-charge period, which is the last unit scan time in the pre-charge period. The start and end times of the periods when two adjacent rows of sub-pixels are in the on state differ by a unit scan time. Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes: During the latter half of the charging period of the sub-pixel in row 2k-1, one of the data signals of row 2k-1 and row 2k is applied to the sub-pixel in row 2k-1. During the charging period of the 2kth row sub-pixel, one of the 2k-1th row data signal and the 2kth row data signal is applied to the 2kth row sub-pixel; During the first pre-charging period and the first half of the charging period of the 2k+1 row sub-pixel, one of the 2k-1 row data signal and the 2k row data signal is applied to the 2k+1 row sub-pixel; during the second half of the charging period of the 2k+1 row sub-pixel, one of the 2k+1 row data signal and the 2(k+1) row data signal is applied to the 2k+1 row sub-pixel; and During the first pre-charging period of the second (k+1) row sub-pixel, one of the second (k-1) row data signal and the second (k) row data signal is applied to the second (k+1) row sub-pixel; during the charging period of the second (k+1) row sub-pixel, one of the second (k+1) row data signal and the second (k+1) row data signal is applied to the second (k+1) row sub-pixel. Where k = 1, 2, 3, ...

27. The driving method according to claim 24, wherein, The pre-charge period of each row of sub-pixels includes a first pre-charge period, which is the last unit scan time in the pre-charge period. The start and end times of the periods when two adjacent rows of sub-pixels are in the on state differ by a unit scan time. Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes: During the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-5 is applied to the sub-pixels in row 6k-5. During the first pre-charging period of the 6k-4 row sub-pixels and the first half of the charging period of the 6k-4 row sub-pixels, the 6k-5 row data signal is applied to the 6k-4 row sub-pixels; during the second half of the charging period of the 6k-4 row sub-pixels, the 6k-3 row data signal is applied to the 6k-4 row sub-pixels. During the first pre-charging period of the 6k-3 row sub-pixel, the 6k-5 row data signal is applied to the 6k-3 row sub-pixel; during the charging period of the 6k-3 row sub-pixel, the 6k-3 row data signal is applied to the 6k-3 row sub-pixel. During the first pre-charging period of the 6k-2 row sub-pixel and the first half of the charging period of the 6k-2 row sub-pixel, the 6k-3 row data signal is applied to the 6k-2 row sub-pixel; during the second half of the charging period of the 6k-2 row sub-pixel, the 6k-1 row data signal is applied to the 6k-2 row sub-pixel. During the first pre-charging period of the 6k-1 row sub-pixel, the 6k-3 row data signal is applied to the 6k-1 row sub-pixel; during the charging period of the 6k-1 row sub-pixel, the 6k-1 row data signal is applied to the 6k-1 row sub-pixel. During the first pre-charging period of the 6k row sub-pixel and the first half of the charging period of the 6k row sub-pixel, the 6k-1 row data signal is applied to the 6k row sub-pixel; during the second half of the charging period of the 6k row sub-pixel, the 6k+1 row data signal is applied to the 6k row sub-pixel. Where k = 1, 2, 3, ...

28. The driving method according to claim 24, wherein, The pre-charge period of each row of sub-pixels includes a first pre-charge period, which is the last unit scan time in the pre-charge period. The start and end times of the periods when two adjacent rows of sub-pixels are in the on state differ by a unit scan time. Applying data signals to at least two rows of subpixels that are simultaneously in the on state includes: During the latter half of the charging period of the sub-pixels in row 6k-5, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-5. During the charging period of the sub-pixels in row 6k-4, the data signal of row 6k-4 is applied to the sub-pixels in row 6k-4; During the first pre-charging period of the 6k-3 row sub-pixel and the first half of the charging period of the 6k-3 row sub-pixel, the 6k-4 row data signal is applied to the 6k-3 row sub-pixel; during the second half of the charging period of the 6k-3 row sub-pixel, the 6k-2 row data signal is applied to the 6k-3 row sub-pixel. During the first pre-charging period of the 6k-2 row sub-pixel, the 6k-4 row data signal is applied to the 6k-2 row sub-pixel; during the charging period of the 6k-2 row sub-pixel, the 6k-2 row data signal is applied to the 6k-2 row sub-pixel. During the first pre-charging period of the 6k-1 row sub-pixel and the first half of the charging period of the 6k-1 row sub-pixel, the 6k-2 row data signal is applied to the 6k-1 row sub-pixel; during the second half of the charging period of the 6k-1 row sub-pixel, the 6k row data signal is applied to the 6k-1 row sub-pixel. During the first pre-charging period of the 6k row sub-pixel, the 6k-2 row data signal is applied to the 6k row sub-pixel; during the charging period of the 6k row sub-pixel, the 6k row data signal is applied to the 6k row sub-pixel. Where k = 1, 2, 3, ...

29. A display device comprising a display panel as claimed in any one of claims 1-23.

Images