Programmable electronic device for implementing a recursive encoder

Abstract

The present description relates to an electronic device (17) that is reconfigurable by programming in order to implement an encoder of a sigma-delta converter based on a generic encoder model with k identical cells Cellk (Cell1, Cell2, Cell3), where k is an integer index ranging from 1 to K and K is an integer between 1 and Kmax, where Kmax is an integer greater than or equal to 1. Each cell Cellk comprises a corresponding weight vector Wk. The device comprises a programmable memory configured to be programmed on the basis of the values of the weights of the K weight vectors Wk. The device further comprises a programmable control circuit (CTRL) configured to be programmed on the basis of the values of the weights of the K weight vectors Wk in order to control summations (SUM1, SUM2, SUM3) and quantisations (Quanti, Quanti, Quant3) in the reconfigurable device so as to implement, in each conversion cycle of an n-cycle conversion, where n is the oversampling rate, the calculations of the vectors Qk[n] as output from the cells Cellk of the encoder.

Description

DESCRIPTION TITLE: Programmable electronic device for implementing a recurrent encoder

[0001] This application is based on, and claims priority from, French patent application FR2403328 filed on March 29, 2024 and entitled "Method of designing a sigma-delta type converter", which is considered to be an integral part of this description within the limits provided by law. Technical field

[0002] The present description relates generally to electronic circuits and, more particularly, to sigma-delta type converters, whether they are analog-to-digital (AD) or analog-to-information (A2I) converters. The present description relates more particularly to an electronic device reconfigurable by programming, adapted to implement an encoder of such a converter, in the case where the encoder is obtained from a generic model, following a step of dimensioning the generic model, for example by supervised deep learning. Prior art

[0003] The use of deep learning processes to design analog and mixed-signal circuits has been proposed for the design of analog-to-digital or analog-to-information converters.

[0004] For example, methods assisted by artificial intelligence (AI) have been used on the outputs of known converters to mitigate material non-idealities of these known converters. However, in this case, artificial intelligence-assisted methods are not directly used to design the converter.

[0005] As another example, converter topologies inspired by neural networks have been proposed, sometimes by applying deep learning methods to adapt the weights of these topologies. However, in these other examples, each proposed topology is predefined from a specific known converter, and therefore cannot be reused to develop a new converter from, for example, a specification or a specification listing the hardware constraints and performances that it would be desirable for this new converter to respect. For example, the article "Design Automation of Analog and Mixed Signal Circuits Using Neural Networks - A Tutorial Brief" by G.Linan-Cembrano et al, published in "IEEE Transactions on Circuits and Systems II: Express Briefs" presents work on the use of artificial intelligence to assist in porting a reference topology to a best-fit hardware implementation.

[0006] In the remainder of the description, a generic encoder model will be described. This generic model is configured to allow sizing of the model during a supervised deep learning step taking into account functional and / or material characteristics targeted for the encoder. Summary of the invention

[0007] There is a need for a programmatically reconfigurable circuit that allows the implementation, in hardware, of an encoder obtained by dimensioning the generic model, for example to validate the sizing of the generic model in relation to the targeted functional and / or material characteristics.

[0008] One embodiment provides a circuit reconfigurable by programming which makes it possible to implement, in hardware, an encoder obtained by dimensioning the generic model described below, for example to validate the dimensioning of the dimensioned model with respect to the targeted functional and / or material characteristics.

[0009] One embodiment overcomes all or part of the drawbacks of known implementations of a sigma-delta type converter encoder.

[0010] An embodiment provides a programmatically reconfigurable electronic device for implementing an encoder of a sigma delta converter operating at an oversampling rate N, with N an integer greater than or equal to 1, and implementing N cycles C[n] at each conversion, with n an integer index ranging from 1 to N, the encoder being based on a generic model comprising a succession of K identical generic cells Cellk, with K an integer parameter and greater than or equal to 1 and less than or equal to Kmax, and k an integer index ranging from 1 to K, each cell Cellk of the generic model corresponding to a recurrent neural network which, at each cycle C[n], is configured to calculate a product of an input vector X[n] by a weight vector Wk of the cell Cellk and to provide an output vector Qk[n] comprising D pairs of outputs Akd[n] and Bkd[n], with D an integer greater than or equal to 1 and less than or equal to Dmax,d an integer index ranging from 0 to Dl, Akd[n] the result of the product calculated by the cell Cellk delayed by d cycles, Bkd[n] a quantification of the result of the product calculated by the cell Cellk delayed by d cycles, the generic model being further configured for, that the vector X[n] is the same for all the cells Cellk at the start of each cycle C[n] and is equal to the concatenation of the K vectors Qk[n] and a sample x[n], for the cycle C[n], of a signal x to be converted, and to calculate, at each cycle C[n], the K vectors Qk[n] sequentially and in order of increasing index k, the device comprising: a programmable memory configured to be programmed from the values ​​of the weights of the K vectors of weight Wk, and a programmable control circuit configured to be programmed from the values ​​of the weights of the K vectors of weight Wk to control summations and quantifications in the reconfigurable device so as to implement, at each cycle C[n], the calculations of the vectors Qk[n] of the encoder.

[0011] According to one embodiment: the device comprises Kmax cell circuits, each cell circuit corresponds to a cell Cellk of the generic model; each cell circuit comprises 1+2. Dmax . Kmax weight circuits, each weight circuit corresponds to a weight of the generic model; each weight circuit comprises at least one programmable value element of resistive or capacitive type; and each weight circuit corresponds to a memory point of the programmable memory of the device.

[0012] According to one embodiment: each cell circuit comprises a summing circuit, each weight circuit of the cell circuit having its output coupled to an input of the summing circuit of the cell circuit; each cell circuit comprises a quantification having an input connected to an output of the summing circuit of the cell circuit; and in each cell circuit, an input of one of the weight circuits is configured to receive a signal determined by the signal x to be converted and inputs of the other weight circuits are coupled to outputs of the summing circuits and the quantification circuits of the device.

[0013] According to one embodiment: the at least one programmable element of each weight circuit is of capacitive type, each weight circuit comprises switches configured to implement a sampling of a voltage on the at least one programmable element of the weight circuit; the output of each summing circuit is connected to Dmax weight circuits in each cell circuit, and an output of each quantification circuit is connected to Dmax weight circuits in each cell circuit.

[0014] According to one embodiment: the at least one programmable value element of each weight circuit is of resistive type; each cell circuit comprises Dmax storage circuits each having an input connected to the output of the summing circuit of the cell circuit and an output connected to an input of one of said other weight circuits of each cell circuit; and each cell circuit comprises Dmax other storage circuits each having an input connected to the output of the quantification circuit of the cell circuit and an output connected to an input of one of said other weight circuits of each cell circuit.

[0015] According to one embodiment, the control circuit comprises the programmable memory.

[0016] According to one embodiment, the device comprises: a summing circuit; a quantization circuit connected to an output of the summing circuit; Dmax.Kmax first memories each coupled to an output of the summing circuit; Dmax.Kmax second memories each coupled to an output of the quantization circuit; 1+2. Dmax . Kmax data paths, one of the data paths being configured to receive the signal x to be converted and being coupled to an input of the summing circuit, the other 2. Dmax. Kmax data paths comprising Dmax.Kmax data paths coupling the first Dmax.Kmax memories to the input of the summing circuit and Dmax.Kmax data paths coupling the first Dmax.Kmax memories to the input of the summing circuit.

[0017] According to one embodiment: the summing circuit comprises a capacitive transimpedance amplifier; and the device comprises at least one resistive element coupled to an input of the summing circuit.

[0018] According to one embodiment, said at least one resistive element is shared for all the data paths and couples each data path to the input of the summing circuit.

[0019] According to one embodiment, said at least one resistive element comprises a resistive element in each data path.

[0020] According to one embodiment: the summing circuit comprises a capacitive transimpedance amplifier; and the device comprises at least one capacitive sampling circuit coupled to an input of the summing circuit.

[0021] According to one embodiment, the at least one capacitive sampling circuit is shared for all the data paths and couples each data path to the input of the summing circuit.

[0022] According to one embodiment, the control circuit is configured to control switches of the device, the control circuit and said switches being adapted, at each update of a first memory or a second memory, to implement sequential readings of the other first and second memories.

[0023] According to one embodiment, the at least one capacitive sampling circuit comprises a sampling circuit in each data path.

[0024] According to one embodiment, the control circuit is configured to control switches of the device, the control circuit and said switches being adapted, at each update of a first memory or a second memory, to implement a parallel reading of the other first and second memories. Brief description of the drawings

[0025] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which:

[0026] Figure 1 schematically represents a sigma-delta type analog-digital converter;

[0027] Figure 2 shows an example of a recurrent autoencoder structure modeling the structure of the sigma-delta converter of Figure 1;

[0028] Figure 3 shows an exemplary embodiment of a part of the converter of Figure 2;

[0029] Figure 4 shows another exemplary embodiment of a part of the converter of Figure 2;

[0030] Figure 5 illustrates an exemplary embodiment of a generic cell based on a recurrent neural network, for a generic recurrent encoder model;

[0031] Figure 6 illustrates an example of a generic model based on the generic cell of Figure 5;

[0032] Figure 7 illustrates an update of the cell outputs of the model of Figure 6;

[0033] Figure 8 illustrates an example of a decoder;

[0034] Figure 9 is a flowchart illustrating a method of designing a sigma-delta converter;

[0035] Figure 10 illustrates steps of the method described in relation to Figure 9;

[0036] Figure 11 illustrates an embodiment of a portion of a programmatically reconfigurable device for hardware implementation of a sized converter model;

[0037] Figure 12 illustrates an embodiment of a programmatically reconfigurable device for hardware implementation of a sized converter model and exemplary control signals of the device;

[0038] Figure 13 illustrates an embodiment of a circuit of a programmatically reconfigurable device for the hardware implementation of a sized converter model;

[0039] Figure 14 illustrates an embodiment of another circuit of a programmatically reconfigurable device for the hardware implementation of a sized converter model;

[0040] Figure 15 illustrates another embodiment of yet another circuit of a programmatically reconfigurable device for hardware implementation of a sized converter model;

[0041] Figure 16 illustrates an embodiment of yet another circuit of a programmatically reconfigurable device for hardware implementation of a sized converter model;

[0042] Figure 17 an embodiment of a programmatically reconfigurable device for hardware implementation of a sized converter model and an example of control signals of the device and an example of control signals of the device, the device comprising the circuits of Figures 13 to 16;

[0043] Figure 18 illustrates an embodiment of a differential type implementation of a circuit of a programmatically reconfigurable device for the hardware implementation of a sized converter model;

[0044] Figure 19 illustrates an embodiment of a differential type implementation of another circuit of a programmatically reconfigurable device for the hardware implementation of a sized converter model;

[0045] Figure 20 illustrates an embodiment of a differential type implementation of yet another circuit of a programmatically reconfigurable device for the hardware implementation of a sized converter model;

[0046] Figure 21 illustrates an embodiment of a differential type implementation of yet another circuit of a programmatically reconfigurable device for the hardware implementation of a sized converter model;

[0047] Figure 22 illustrates an embodiment of a differential type implementation of yet another circuit of a programmatically reconfigurable device for the hardware implementation of a sized converter model;

[0048] Figure 23 illustrates an embodiment of a programmatically reconfigurable device for implementing a sized encoder model, in the case of a differential type implementation;

[0049] Figure 24 illustrates an example of control signals of the device of Figure 23;

[0050] Figure 25 illustrates another embodiment of a programmatically reconfigurable device for implementing a sized encoder model, in the case of a common mode type implementation;

[0051] Figure 26 illustrates an example of implementation of a circuit of the device of Figure 25 and timing diagrams of control signals of this circuit;

[0052] Figure 27 illustrates an alternative embodiment of the device of Figure 25;

[0053] Figure 28 illustrates another embodiment of a programmatically reconfigurable device for implementing a sized encoder model, in the case of a differential mode type implementation; and

[0054] Figure 29 illustrates an example of implementation of a circuit of the device of Figure 28. Description of the embodiments

[0055] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0056] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed.

[0057] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0058] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0059] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0060] Figure 1 schematically represents an example of an analog-to-digital converter of the sigma-delta type of order M, with M an integer greater than or equal to 1 and equal to 1 in the example of Figure 1. The converter is here a converter which is configured to convert an analog signal x and for example continuous (DC from the English "direct current") into a digital signal. The converter is reset at each conversion, each conversion comprising, as will be described in more detail later, N cycles.

[0061] The converter comprises a sigma-delta modulator 100 and a filter 102 (each delimited by dotted lines in Figure 1).

[0062] The modulator 100 comprises an analog integrator 104 (delimited by dotted lines in figure 1) and a quantizer 106, here on one bit.

[0063] The filter 102 is for example implemented by a digital integrator as shown in figure 1.

[0064] The converter operates with an oversampling rate N commonly referred to by the acronym OSR (from the English "OverSampling Rate"), with N an integer greater than or equal to 1, for example greater than or equal to 2. Thus, each conversion of an input signal x comprises N cycles C[n], with n an integer index ranging from 1 to N.

[0065] At each cycle C[n] , the modulator 100 receives a sample xe (or x[nl] ) corresponding to the sampling of the signal x in the previous cycle. At each cycle C[n] , the converter implements the following three operations: - the difference between the xed sample of the previous cycle and the output Bll of the modulator 100 in the previous cycle is integrated by the analog integrator 104, so as to provide the output Ail of the integrator 104; - the output Ail is quantized by the quantizer 106 to update the output Bll of the modulator 100; - the output Bll is supplied to the filter 102 which then calculates the digital output y (or y[n]) of the converter for this cycle n.

[0066] In other words, the filter implements the following equation in z: [Math 1] Garlic = Z -1 (A11 + xe — Bll) with Z - a delay of one cycle.

[0067] This amounts in time to: [Math 2]

[0068] In practice, the internal signals of the converter must remain within a given dynamic range centered on the threshold of the quantizer 106. This is made possible by the negative feedback loop controlled by the sign of the output signal Bll of the quantizer. For example, a weighting can be added between the output of the input differentiator and the input of the integrator 104.

[0069] For the example illustrated in Figure 1, this behavior is expressed according to the equations [Math 3] and [Math 4] above, with the hypotheses [Math 5] respected: [Math 3] [Math 4] where sign(All[n]) is the function returning the sign of Ail[n] with respect to the threshold of quantifier 106. [Math 5]

[0070] The digital signal xq obtained at the end of each conversion, that is to say at the end of N corresponding conversion cycles, is then equal to y [N] and can then be expressed, in this example, according to the equation [Math 6]: [Math 6] normalization in 1 / N not being represented in Figure 1.

[0071] In the example of Figure 1, in the integrator 104, the delay z -1 of a cycle is applied on the direct path. However, the person skilled in the art will know how to adapt this example to the case where, in the integrator 104, the delay z -1 of a cycle is applied on the feedback path, between the output Ail and the summing block, providing that a delay z -1 of a cycle is also applied on the feedback path between output Bll and the subtractor block.

[0072] In the example of Figure 1, in filter 102, the delay z -1of a cycle is applied to the feedback path, between the output y[n] and the summing block. Here too, the person skilled in the art will be able to adapt this example to the case where, in the filter 102, the delay z -1 of a cycle is applied on the direct path, between the summing block and the output y [n] .

[0073] To reduce quantization noise, it is known to use converters of order M greater than 1. In this case, the modulator 104 comprises a succession of integrators, and the filter comprises, for example, a succession of integrators.

[0074] A method described herein allows designing a converter, and, more particularly, the converter's encoder, by implementing supervised deep learning associating input data with output data, based on the exploration of sigma-delta converter topologies. Observing that sigma-delta converters have recursive structures, the method is based on modeling a sigma-delta converter by a recurrent autoencoder structure as illustrated in Figure 2. The recurrent autoencoder then provides a digitized image of the input analog signal x in the example illustrated in Figure 2. In other examples, The recurrent autoencoder provides a digital estimate of one or more latent parameters of the input signal.

[0075] Figure 2 shows an example of a recurrent autoencoder structure modeling the sigma-delta converter structure of Figure 1.

[0076] The modulator 100 (delimited by dotted lines in Figure 2) is here implemented by a recurrent encoder 100. The recurrent encoder 100 comprises, in this example where M is equal to 1, a cell 200 corresponding to a recurrent neural network (RNN). This cell 200 is configured to implement recursive processing where the output data of the cell, for a given cycle, are updated from, or as a function of, the output data of the cell in the previous cycle and one or more input data (or values) of the cell. Recurrent neural networks are well known to those skilled in the art and are not redefined here. For example, a recurrent neural network may be similar from a mathematical point of view to an infinite impulse response filter due to its recurrence.

[0077] The filter 102 is here implemented by a recurrent decoder 102. The recurrent decoder 102 comprises, in this example, a cell 202 corresponding to a simple recurrent neural network (SRNN). For example, a simple recurrent neural network is configured to implement at least the following operation: the output of the cell 202, y[n] in the example of FIG. 2, corresponds to the sum of the output of the cell 202 in the previous cycle, y[nl] in the example of FIG. 2, weighted by a corresponding weight Wc (not shown in FIG. 2), and an input of the cell 202, Bll[n] in the example of FIG. 2, weighted by a corresponding weight Wd (not shown in FIG. 2). This corresponds to a dot product between an input vector and a weight vector (dot product in English) where, in this example, the input vector is equal to the concatenation of y[nl] and Bll[n] and the weight vector is made up of the weights Wc and Wd. Cell 202 of Figure 2 corresponds to filter 102 of Figure 1 when the weights Wc and Wd are unitary. Simple recurrent neural networks are well known to those skilled in the art and are not redefined here. For example, the source code of a simple recurrent neural network is available on the following web page: https: / / github. com / keras- team / keras / blob / v2.14.0 / keras / layers / rnn / simple_rnn. py#Ll93-L214.

[0078] Figure 3 represents an example of a cell 200 corresponding to the modulator 100 of the sigma-delta converter of order M=1 of Figure 2.

[0079] The cell 200 comprises a recurrent layer of neurons, or said, otherwise, corresponds to a recurrent neural network. The cell or layer of neurons 200 is said to be recurrent in that it receives its outputs Ail and Bll on its inputs, and more particularly that it receives, at a cycle C[n] of given index n, the outputs All [n-1] and Bll [n- 1] of the preceding cycle C[n-1] (the delay z -1 of a cycle not being represented in figure 3).

[0080] At each cycle C[n], cell 200 also receives the sample x[nl] corresponding to this cycle.

[0081] The cell 200 is configured to multiply each of its inputs All[n-1], Bll[n-1], and x[nl] by a corresponding weight Wlla, Wllb, and Wllx, respectively, and to sum the results of these products. The result of the summation corresponds to the output Ail[n], and the quantization of the output Ail[n] by the quantizer 106, which in fact corresponds to an activation layer ("activation layer" in English), results in the output Bll[n]. In the example of Figure 3, the quantizer 106 is a two-level quantizer. However, the person skilled in the art will be able to adapt this example to the case where the quantizer 106 quantifies on more than two levels. For example, the quantizer 106 may be a 4-level quantizer and the output Bll[n] may then take 4 quantized values, preferably uniformly distributed, for example between -0.5 and 0.5 using the conditions of the example of equation [Math 4] where Bll belongs to the range -0.5; 0.5. Because the recurrent cell or neuron layer 200 provides a quantized output Bll, this recurrent cell or neuron layer 200 is, for example, said to have a quantized output.

[0082] In other words, the cell 200 is configured to calculate the scalar product of its input vector X[n] = [x[nl], All[n-1], Bll[n-1]] by its weight vector Wll = [Wllx, Wlla, Wllb], provide the output Ail[n] equal to the result of this scalar product, and provide the output Bll[n] corresponding to the one-bit quantization of the output Ail[n]. The cell 200 therefore provides an output vector Q1[n] = [Ail[n], Bll[n].

[0083] The modulator 100 illustrated in figure 1 is obtained with the cell 200 when the weights Wllx, Wlla and Wllb are respectively equal to 1, 1 and -1.

[0084] In the example of Figure 3, the delays z -1of a cycle are not shown. In this example, a one-cycle delay is provided on the feedback path connecting the output Ail [n] to the input All [n-1] of the cell 200, and a one-cycle delay is provided on the feedback path connecting the output Bll [n] to the input Bll [n-1]. However, the person skilled in the art will be able to adapt this example to the case where the feedback paths of the data All and Bll are delay-free, and where a one-cycle delay is provided between the summing block of cell 200 and the output Ail[n], as shown in the example in Figure 1.

[0085] Figure 4 represents an example of a simple neural network 202 corresponding to the example filter 102 of the sigma-delta converter of order M=1 of Figure 2. The neural network 202 is said to be simple in that it comprises only a single recurrent layer of neurons.

[0086] The neural network 202, that is to say its layer of neurons, is recurrent in that it takes as input, at a given cycle C[n] of index n, the output y[nl] that the network 202 provided at the previous cycle C[n-1]. In addition, at a given cycle C[n] of index n, the network 202 also takes as input the output Bll[n] of the cell 200. In this example, the network 202 multiplies each of its inputs y[nl] and Bll[n] by the corresponding weights Wc and Wd respectively, and the output y[n] of the network is then equal to the sum of these products. By setting Wc=1 and Wd=1 / N, we find the example of filter 102 of figure 1 (in which the 1 / N normalization is not represented). One could also introduce a normalization dependent on the index n, so as to obtain a normalized output y[n] for each index n using the following recurrence relation: [Math 7]

[0087] In the example of Figure 4, the delay z -1of a cycle is not shown. In this example, this delay of a cycle is arranged on the feedback path connecting the output y[n] to the input y[nl] of the cell 202. However, the person skilled in the art will be able to adapt this example to the case where the feedback path of the data y is devoid of delay, and where this delay of one cycle is expected between the summing block of the cell and the output y[n] of the cell.

[0088] The figures described above show that a particular sigma-delta converter topology can be modeled by an autoencoder comprising a recursive encoder 100 implemented from a recurrent neural network cell 200 and a recursive decoder 102 implemented from a simple recurrent neural network.

[0089] As an example, the autoencoder described above could undergo a supervised deep learning step, for example to obtain values ​​of the weights Wlla, Wllb, Wllx, Wy and Wb, although this would be of little interest for a sigma-delta converter of order 1. On the other hand, it could be of interest for sigma-delta converters of order strictly higher than 1, provided that each of these converters is modeled by a model based on recurrent neural networks.

[0090] However, there are many different topologies of sigma-delta converters. These topologies are, for example, determined by: the nature of the input signal; and / or the type of information that the converter must provide at the output; and / or the performance that the converter must have in terms of conversion accuracy; and / or the maximum surface area that the converter must have; and / or the order M of the converter; and / or the value N of the oversampling rate; and / or a desired robustness to noise; and / or maximum excursions that the output signals of the converter stages must have; and / or constraints on the converter weights, this list not being exhaustive.

[0091] To improve the operation of a given sigma-delta converter having a particular topology, one could first think of realizing from this particular topology a specific model of this topology, this model comprising an encoder-decoder pair with an encoder model (corresponding to the modulator) based on recurrent neural networks and a decoder model (corresponding to the filter) also based on recurrent neural networks, for example simple recurrent neural networks. Once this formalism is established, a supervised deep learning could then be implemented on the model extracted from this particular topology. However, the design of such a model must be adapted to each topology of the sigma-delta converter considered, which can be complex and tedious.Furthermore, this work of designing a model based on recurrent neural networks would then have to be done for each different sigma-delta converter topology, which is not desirable due to the large number of different sigma-delta converter topologies.

[0092] On the contrary, the method described here for designing a sigma-delta converter is based on the use of a generic converter model, and, more particularly, on a generic modulator model. Supervised deep learning is applied to this generic model to obtain a sized converter model, and, more particularly, a sized model of the converter encoder. This method therefore does not involve training a neural network and then programming a processor dedicated to the implementation of neural networks, but rather obtaining a specific circuit, for example an integrated circuit, satisfying a set of specifications, or criteria, related to the targeted hardware implementation. In other words, rather than proposing a method for sizing a particular sigma-delta converter topology by sequentially ensuring that a set of specifications related to a targeted hardware implementation are satisfied, a generic sigma-delta converter topology model is proposed here, and more particularly a generic topology model of a sigma-delta converter encoder. The sizing of this model is optimized, preferably during deep learning implemented on the model, to jointly satisfy a set of hardware specifications.For example, these hardware specifications are transcribed in the form of constraints and / or regularizations on the weights and data of the model so as to limit the search space during supervised deep learning and to guide the learning (or optimization) process towards a topology satisfying the expected specifications. The converter thus obtained is, for example, designated by the acronym RCN (from the English "Recurrent Converter Network" or "Recurrent Conversion Network").

[0093] In other words, a generic topology is described here with very high degrees of freedom of possible interconnections between internal cells, without the imprint of a particular topology. This generic topology makes it possible to cover a multitude of configurations, without a priori on the final configuration retained. Deep learning will make it possible to assign a particular weight to each of the interconnections so as to converge towards a final topology adapted to the training data. The starting point is therefore a generic (or generalist) topology with a random weighting of the different possible interconnections (and therefore agnostic of the problem addressed) that we will specialize by learning, or with a weighting corresponding to a reference structure that we will want to develop.

[0094] More specifically, this generic model, which corresponds to an autoencoder, includes a recurrent encoder corresponding to the sigma-delta modulator of the generic model, and a recurrent decoder corresponding to the filter of the generic model. Both the encoder and the decoder correspond to layers of recurrent neural networks (RNN).

[0095] Even more particularly, the proposed converter model is said to be generic because the modeling of its encoder is based on a cascade (or succession) of K identical generic cells, with K an integer greater than or equal to 1, preferably greater than or equal to 2, where each generic cell corresponds to a recurrent neural network. The number K is then a parameter (or hyper-parameter) of the generic model. The number K is, for example, determined by the intended order M of the converter, and is, for example, equal to M+1.

[0096] Figure 5 illustrates an exemplary embodiment of a generic cell Cellk, k being an integer index ranging from 1 to K and identifying the cell Cellk among the succession of K cells Cellk of the recurrent encoder.

[0097] At each cycle C[n] , the cell Cellk receives an input vector X[n] . This vector X[n] is updated at the beginning of each cycle C[n] , from the output data of the K cells Cellk obtained at the end of the previous cycle C[n-1]. Although only one cell Cellk is represented, when the generic model includes several successive cells Cellk, these cells receive the same vector X[n] , which is identical for all cells Cellk at the beginning of each cycle C[n] .

[0098] The cell Cellk includes a layer (or vector) Wk of weights, comprising as many weights as there are elements in the input vector X[n] of the cell Cellk.

[0099] The cell Cellk is configured, at each cycle C[n], to multiply each of its inputs by a corresponding weight, to provide the sum Ak0[n] of these products, and the quantization BkO[n] of this sum. In other words, the cell Cellk is configured, at each cycle, to make the scalar product of its input vector X[n] by its weight vector Wk, the result of this scalar product being the output Ak0[n] of the cell, and the quantization of the output Ak0[n] providing the output BkO[n].

[0100] Preferably, to enable a generic model to be obtained allowing greater freedom of choice during the supervised deep learning step, the cell Cellk is configured to also provide outputs corresponding to the outputs Ak0[n] and BkO[n], but with a delay of at least one conversion cycle. In the example of Figure 5, the cell Cellk provides outputs Akl[n] and Bkl[n] corresponding to the respective outputs Ak0[n] and BkO[n] delayed by one cycle, as represented by a DI block in Figure 5.

[0101] More generally, the generic cell Cellk is therefore configured to provide, at each cycle C[n], D pairs of outputs Akd[n], Bkd[n], with Akd[n] the result of the product of the input vector X[nd] by the weight vector Wk, and Bkd[n] the quantification of the result of the product of the input vector X[nd] by the weight vector Wk, D being an integer greater than or equal to 1, preferably 2, and d being an integer index ranging from 0 to Dl.

[0102] Thus, for a cycle C[n] of given index n, the output Ak0[n] corresponds to the scalar product X[n] .Wk (also noted<X[n] ,Wk> ) calculated by the cell Cellk at this cycle C[n] , the output BkO [n] corresponding to the quantization of the output Ak0 [n] .

[0103] Furthermore, for this same cycle C[n] , the output Akd[n] corresponds to the scalar product X[nd] .Wk, and the output Bkd[n] corresponds to the quantization of the output Akd[n] . In other words, at the beginning of each conversion cycle C[n] , Akd[n] = Ak0 [nd] and Bkd[n] = BkO [nd] . In other words, at the beginning of each conversion cycle C[n] , the output Akd[n] corresponds to the output Ak0 [n] calculated by the cell Cellk d cycles before the cycle C[n] and the output Bkd[n] corresponds to the output BkO [n] calculated by the cell Cellk d cycles before the cycle C[n] . Said in another way, at the beginning of each cycle C[n], Akd[n] <— Akd-1 [nl] and Bkd[n] <— Bkd-1 [n-1], with a mathematical operator meaning "receives".

[0104] In the example of Figure 5, and in the rest of the description D, is, for example, chosen equal to 2, and the cell Cellk then provides, at each cycle C[n], a pair of outputs Ak0[n], BkO[n] not delayed, and a pair of outputs Akl[n], Bkl[n] delayed by one cycle. In Figure 5, for each non-zero value of d, a block Dd represents the application of a delay of d cycles between the pair of outputs Ak0[n], BkO[n], not delayed, and a pair of outputs Akd[n], Bkd[n] delayed by d cycles. In the example of Figure 5, the cell Cellk comprises a block DI.

[0105] Note that the integer D is a parameter (or hyper-parameter) of the proposed generic model.

[0106] At each cycle C[n] , the set of D pairs of outputs Akd[n] , Bkd[n] forms the output vector Qk[n] of the cell Cellk.

[0107] At each cycle C[n] , the input vector X[n] of each of the K Cellk cells is then the same for all cells, at least at the beginning of the cycle C[n] before the Cellk cells calculate their outputs Ak0 [n] and BkO [n] which are therefore updated during the cycle C[n] . The vector X[n] is equal to the concatenation of the sample x[n] at the beginning of the cycle C[n] and the K output vectors Qk[n] of the K Cellk cells which are updated during the cycle from the sample x[n] . The vector X[n] therefore comprises 1 + K.2.D elements (or inputs for the Cellk cells), just as the vector Wk of each Cellk cell comprises 1 + K.2.D elements (or weights of the Cellk cells). At each cycle C[n] , the values ​​Ak0 [n] and BkO [n] are updated during the cycle C[n] from the value of x[n] at the beginning of the cycle.

[0108] Thus, for each cell Cellk of index k equal to p, with p an integer index ranging from 1 to K, the vector Wp of the weights of the cell Cellp, that is to say the vector Wk of the weights of the cell Cellk of index k equal to the index p considered, includes: a weight Wpx applied to the input x[n] of the cell Cellp; and K times D pairs of weights Wapkd, Wbpkd, with p the integer index of the cell Cellp considered and k ranging from 1 to K.

[0109] In each cell Cellk of index k equal to p, or, in other words, in each cell Cellp, for k ranging from 1 to K and for d ranging from 0 to Dl, the weight Wapkd of the cell Cellp is applied to the output Akd[n] of the cell Cellk, this output Akd[n] of the cell Cellk being an input of the cell Cellp, and the weight Wbpkd is applied to the output Bkd[n] of the cell Cellk, this output Bkd[n] of the cell Cellk being an input of the cell Cellp.

[0110] Figure 6 illustrates by example the formalism described above.

[0111] Figure 6 represents an example of an encoder 200 based on a generic model with K=3 successive cells Cellk, in the case where D is equal to 2.

[0112] The Cellk cells (Celll, Cell2 and Cell3 in the example of Figure 6) are connected one after the other in order of increasing index k. In other words, at each of the N cycles of a conversion, the Cellk cells update their outputs Ak0 [n] and BkO [n] one after the other in order of increasing index k, or, in other words, update their non-delayed outputs sequentially and in order of increasing index k. Each update of the outputs Ak0 [n] and BkO [n] by a corresponding Cellk cell is carried out during a part of the corresponding cycle C[n], this part of the cycle C[n] being, for example, called intra-cycle, for example intra-cycle of index k. Once a cell Cellk has updated its non-delayed outputs during the intra-cycle of index k, the next cell Cellk+1 updates its non-delayed outputs during the next intra-cycle of index k+1.Once all Cellk cells have updated their undelayed outputs, the delayed outputs of the Cellk cells are updated at the end of cycle C[n], and the next cycle C[n+1] can begin.

[0113] Figure 7 illustrates the sequential update of the undelayed outputs of the Cellk cells, and, more specifically in this example, the update of the outputs of the Cellk cells in the case where K is equal to 3.

[0114] At a time tO the nth conversion cycle C[n] begins.

[0115] From time t0 to a following time tl, still in cycle C[n], cell Celll calculates the product X[n] .Wl, and, at time tl, the new outputs A10[n] and B10[n] of cell Celll are available. The outputs A10[n] and B10[n] are therefore updated at time tl, and do not change until the end of cycle C[n].

[0116] From time tl to a following time t2, still in cycle C[n], cell Cell2 calculates the product X[n].W2, and, at time t2, outputs A20[n] and B20[n] of cell Cell2 are available. Outputs A20[n] and B20[n] are therefore updated at time t2, and do not change again until the end of cycle C[n].

[0117] From time t2 to a following time t3, still in cycle C[n], cell Cell3 calculates the product X[n].W3, and, at time t3, outputs A30[n] and B30[n] of cell Cell2 are available. Outputs A30[n] and B30[n] are therefore updated at time t3, and do not change again until the end of cycle C[n].

[0118] Time t3 marks the end of cycle C[n] and the beginning of the next cycle C[n+1]. Thus, at time t3, for each cell Cellk, the delayed outputs of the cells are updated, or, in other words, at the beginning of each cycle C[n+1], Akd[n+1] = Akd-1[n] and Bkd[n+1] = Bkd-1[n]. For example, at time t0, the delayed output Ail[n] of cell Celll is updated with the value of output A10[nl] calculated by cell Celll in the previous cycle C[n-1]. In other words, at the beginning of each cycle C[n+1], that is to say at the end of each cycle C[n], Akd[n+1] <— Akd-1 [n] and Bkd[n+1] <— Bkd-1 [n], with a mathematical operator meaning "receives". The data Akd[n+1], Bkd[n+1] available at the beginning of each cycle C[n+1] constitute, for example, the inter-cycle data. The inter-cycle data are available at each passage from a cycle C[n] to the following cycle C[n+1], for example at times t0 and t3 in figure 7.

[0119] Then, the operation described for cycle C[n] is repeated in cycle C[n+1]. For example, between time t3 and time t4, cell Celll calculates the product X[n+1].Wl, and, at time t4, the outputs A10[n+l] and B10[n+l] of cell Celll are available, and so on.

[0120] Returning to the example in Figure 6, the updates of the non-delayed outputs Ak0 [n] , BkO [n] of the cells Cellk are therefore carried out from left to right during each cycle C[n] . Thus, in this example, during a given cycle C[n], the outputs A10[n] and B10[n] of the cell Celll are updated before the outputs A20[n] and B20[n] of the cell Cell2, these two outputs being themselves updated before the outputs A30 [n] and B30 [n] of the cell Cell3. This update of the outputs Ak0 [n] and BkO [n] during the cycle C[n] is called, for example, intra-cycle update. The intra-cycle update differs from the update of the outputs Akd[n] and Bkd[n], where d is strictly positive, which is done from the outputs Ak0[n] and BkO[n] between two successive cycles and which is called, for example, inter-cycle update, or transfer.For example, in each cycle C[n] , the output data updated at each intra-cycle of this cycle C[n] constitute the intra-cycle data of cycle C[n] . For example, in Figure 7, the intra-cycle data of cycle C[n] are available at times t1, t2, t3.

[0121] In the example of Figure 6, the vector W1 of the weights of the cell Celll is made up of the following K.2.D+1 = 13 weights: Wlx, WbllO, WallO, Wblll, Walll, Wbl20, Wal20, Wbl21, Wal21, Wbl30, Wal30, Wbl31, Wal31, the vector W2 of the weights of the cell Cell2 is made up of the following K.2.D+1 = 13 weights: W2x, Wb210, Wa210, Wb211, Wa211, Wb220, Wa220, Wb221, Wa221, Wb230, Wa230, Wb231, Wa231, and the vector W3 of the weights of the cell Cell3 is made up of the following K.2.D+1 = 13 weights: W3x, Wb310, Wa310, Wb311, Wa311, Wb320, Wa320, Wb321, Wa321, Wb330, Wa330, Wb331, Wa331.

[0122] Thus, the WM weight matrix of the generic encoder model example in Figure 6 can be written as: [Math 8] transposed matrix.

[0123] The proposed generic model allows for a greater number of degrees of freedom in the hardware implementation compared to the model in the example of Figures 3 and 4 which is very specific to the converter example of Figure 1.

[0124] Indeed, the proposed generic encoder model allows to explore a wide variety of possible topologies, in which each Cellk cell has access, on its inputs, to the outputs of each of the K Cellk cells of the model. For example, the proposed generic encoder model allows to explore by supervised deep learning technical solutions, i.e. topologies, which would be difficult, or even impossible, to size with usual analytical approaches. This also allows to propose original topologies jointly exploiting the quantized data at the output of the different cells. MASH type topologies (from the English "Multi-Stage Noise Shaping") are proposed in the literature, in which the error of quantization is transferred at each cycle from an upstream modulator to a downstream modulator. The proposed approach makes it possible to go beyond this MASH technique by transferring from one cell to another, or from one group of cells to another, any possible configuration of signals.

[0125] Figure 8 shows an example of a filter 102 that can be used in a generic model of a sigma delta converter based on a K-cell Cellk encoder.

[0126] In this example, the sigma-delta converter considered is configured to convert an analog (i.e. non-discretized) and continuous signal x into a digital signal, and is reset at each conversion, each conversion comprising N cycles C[n] .

[0127] For such a converter, the filter 102 is then composed, for example, of a succession of Q SRNNq cells each corresponding to a simple recurrent neural network SRNNq of the type described in relation to FIG. 4, with q an integer index ranging from 1 to Q, and Q an integer. For example, Q at least equal, preferably equal, to the number K of Cellk cells of the encoder. In this example, Q is equal to 3 and the filter 102 is sized for a converter comprising for example K=3 Cellk cells. Thus, in this example, the filter 102 comprises Q equal to 3 successive cells SRNN1, SRNN2 and SRNN3.

[0128] SRNNq networks are connected one after the other in order of increasing index q. Each SRNNq network provides, at each cycle C[n], an output Fq[n].

[0129] In this example, each SRNNq network includes a first input, a second input, and an output. The first input of each SRNNq network is coupled to the output of that SRNNq network, the second input of the first SRNN1 network being coupled to an output of the encoder, and the second input of each subsequent SRNNq network being coupled to the output of the previous SRNNq-1 network.

[0130] For example, at each cycle C[n], each SRNNq network receives its output Fq delayed by one cycle (block z -1 in figure 8), that is to say its output Fq[n-1] of the previous cycle C[n-1], on its first input.

[0131] In this example, the second input of the first SRNN1 network receives a quantized data stream provided by the cell Cellk of index k equal to K, for example the quantized data stream BKO provided by the last cell Cellk of the succession of K cells Cellk of the encoder. As another example, the second input of the first SRNN1 network receives a quantized data stream delayed by d cycles provided by the cell CellK, for example the quantized data stream delayed by d=1 cycle BK1. In this example, the second input of the first SRNN1 network therefore receives the quantized data stream B30. More particularly, in this example, at each cycle C[n], the second input of the first SRNN1 network receives the output B30[n] of the cell Cell3.

[0132] For q greater than or equal to 2, that is to say for SRNNq networks other than the first SRNN1 network, the second input of each SRNNq network is coupled to the output of the previous SRNNq-1 network. Although this is not the case in this example, in other examples not illustrated, one or more SRNNq networks may comprise, in addition to its second input coupled to the output of the previous SRNNq-1 network, a third input coupled to the output of a previous SRNNq-g network, with g an integer index greater than or equal to 2. Furthermore, although this is not the case in the example of figure 8, each SRNNq with index q strictly greater than 1 may have an additional input receiving, like the SRNN1 network, the data BKO [n].

[0133] In this example, for q greater than or equal to 2, the second input of each SRNNq network is coupled to the output Fq-1 of the previous SRNNq-1 network by a NORM normalization stage present on the output of the SRNNq-1 stage. In other words, for q strictly less than 3, the output of each SRNNq network is coupled to the second input of the following network SRNNq+1 by a NORM normalization stage. The objective of these NORM stages is to facilitate deep learning. These NORM stages do not necessarily have a hardware equivalence. These NORM stages are optional. Thus, for q greater than or equal to 2, the second input of each SRNNq network receives a data Fq-1' corresponding to the normalization by a NORM stage of the output Fq-1 of the previous SRNNq-1 stage. For example, at each cycle C[n] , for q greater than or equal to 2, the second input of each SRNNq network receives a data Fq-1 ' [n] .

[0134] For example, each NORM stage scales the output Fq-1 of the preceding SRNNq-1 stage to provide a normalized output Fq-1' for a sequence of N successive cycles. As an example, each NORM normalization stage is configured so that, for each of the N cycles of a conversion, the output of the NORM stage does not exceed a given maximum value, for example 1. For example, each NORM stage applies, at each cycle C[n], a gain to the data it receives to provide its output data, this gain being able to depend on the index n of the cycle considered.

[0135] In another example, the normalization stages NORM between SRNNq networks are omitted, and the second input of each SRNNq network with index q greater than or equal to 2 directly receives the output Fq-1 of the previous SRNNq-1 network.

[0136] The filter further comprises a normalization stage NORMb configured to receive the output Fq of the last network SRNNq, that is, output F3 in this example, and to provide the signal xq.

[0137] The NORMb normalization stage is configured to scale the output value xq of the filter to the same scale as the input signal x of the converter, so as to allow a reconstruction of the signal x at each conversion cycle C[n]. The signal xq then corresponds to the output of the NORMb stage. Alternatively, these normalization stages can also integrate a bias, in order to produce an affine function of the type: F'x[n] = a.Fx[n]+b, where a and b are respectively the gain and the offset of the NORMb function.

[0138] At each cycle C[n], each SRNNq network is configured to compute the dot product between its input vector and a corresponding weight vector, and to update its output with the result of this dot product. In particular, for each SRNNq network, the input vector of the network at cycle C[n] includes the output Fq[n-1] provided by this same network at the previous cycle C[n-1] as well as the output of the SRNNq-1 network.

[0139] In this example where each SRNNq network comprises two inputs and one output, each SRNNq network comprises a weight vector having a first weight Wcq applied to the first input of the SRNNq network considered, and a second weight Wdq applied to the second input of the SRNNq network considered.

[0140] For example, at each cycle C[n]: - the output Fl [n] of the SRNN1 network corresponds to the sum of its input Fl [n-1] multiplied by a weight Wcl and its input B30 [n] multiplied by a weight Wdl; - the output F2 [n] of the SRNN2 network corresponds to the sum of its input F2 [n-1] multiplied by a weight Wc2 and its input F'l [n] multiplied by a weight Wd2; and - the output F3 [n] of the SRNN3 network corresponds to the sum of its input F3[n-1] multiplied by a weight Wc3 and its input F'2[n] multiplied by a weight Wd3.

[0141] An example of a filter adapted to a sigma-delta type converter configured to convert, in N cycles, a continuous analog signal x into a digital signal xq, this converter being reset at the start of each conversion, has been described above.

[0142] Preferably, whatever the sigma-delta type converter considered, the converter filter is implemented from one or more cascades (or successions) of simple recurrent neural networks, or cells, with or without a NORM normalization stage at the output of one or more of these networks.

[0143] The figures described above illustrate a sigma-delta converter model consisting of a generic model-based encoder implemented by K generic Cellk cells of recurrent neural networks, and a decoder implemented from several simple recurrent neural networks also called cells.

[0144] It is then possible to implement supervised deep learning on this converter model.

[0145] Although an example of a sigma-delta converter model has been described above in which the encoder is obtained from a generic model where K is equal to 3, and in which the decoder is of the type described in connection with Figure 8, many other sigma-delta converter models can be obtained from the generic cell Cellk, for example by changing the K value and / or the D value and / or the filter model used for the model.

[0146] Typically, supervised deep learning is implemented using a training dataset, by defining a cost function Fcost that is sought to be minimized during supervised deep learning with the training data. More specifically, the values ​​of the encoder and decoder weights are optimized during deep learning to minimize the cost function.

[0147] The Fcost function includes a fidelity function, or term, Ffid which expresses, for each training data provided as input to the model, therefore to the converter, an image of the error between the output value(s) of the model and the expected (ideal) output value(s) for this input

[0148] For example, in the case of a sigma-delta converter configured to convert a continuous analog signal of value xa into a corresponding digital signal xq, reset at each conversion of N cycles, the fidelity function compares, for each training data, the difference between the value xa of the signal x provided as input to the model and the value of the digital counterpart xq obtained for this value xa of the input signal x.

[0149] However, the person skilled in the art will be able to adapt the examples indicated below of cost function, and in particular the examples of fidelity function, to the case of a sigma-delta type converter reset at each conversion and having a function other than the conversion of a continuous analog signal into a digital signal, for example to a sigma-delta type converter configured to extract one or more latent parameters from an input of the converter. In other words, the person skilled in the art will be able to adapt these examples of cost function, and in particular the examples of fidelity function, to the case where what is minimized is the error between a latent parameter extracted by the converter on a training data provided as input to the converter, and the expected latent parameter corresponding to this training data.

[0150] As an example, for each training batch of dimension S, that is to say that a batch includes, in this example, S input xa values, with S a strictly positive integer, the function Ffid(xa, xq) of the batch can be based on the mean square error Frmse(xa, xq) between the S pairs of values ​​xa[s] and xq[s] of the batch, with s an integer index ranging from 1 to S: [Math 9]

[0151] As another example, the function Fid(xa,xq) of each training batch can be based on a function Flse logarithm of the sum of the exponentials of the differences between the S values ​​xa[s] and xq[s] of the batch: [Math 10]

[0152] As another example, the function Fid(xa, xq) of each training batch can be based on a linear combination Fmix(xa, xq) of the functions Frmse and Flse: [Math 11] Fmix(xa,xq) = A * Frmse(xa,xq) + B * Flse (sa, xq) , with A and B positive factors whose sum is equal to 1, for example equal to 0.8 and 0.2 respectively, although the person skilled in the art may be able to predict other values.

[0153] As another example, the function Fid(xa, xq) of each training batch can be based on a linear combination Fmax(xa, xq) of the maximum error between the batch values ​​xa[s] and xq[s] and the LP norm of the error between the batch values ​​xa[s] and xq[s]: [Math 12] With [Math 13] p is the index of the L norm p , by example p is equal to 5 for the norm L 5 , and where max s{ |xa[s] - xq[s] | ] the function returning the maximum error, in absolute value, of conversion for the training batch considered comprising S pairs of an input value xa[s] and an output value (or converted value) xq[s], it being understood that in this example of a sigma-delta type converter, the expected output value for a given input value xa[s] is equal to this input value.

[0154] Although four examples of fidelity functions Ffid(xa, xq) have been described above, the person skilled in the art is able to provide other fidelity functions adapted to a sigma-delta converter model configured to convert a continuous analog signal x of value xa into a digital signal xq, where the converter is reset at each conversion of N cycles. More generally, the person skilled in the art is able to provide fidelity functions adapted to sigma-delta converter models which are reset at each conversion of N cycles but which aim to extract one or more latent parameters from an input provided to the converter. For example, these fidelity functions may be adapted so as to optimize different metrics (maximum error, average error, outlier authorization, etc.).

[0155] In the examples of fidelity functions Ffid(xa, xq) described above, for each input data of index s of a given training batch, the error calculated between the input xa[s] and its digital counterpart xq[s] is calculated only at the end of the conversion, i.e. at the cycle of index N. However, the person skilled in the art will be able to adapt these examples of fidelity functions to the case where, for each input data item of index s of a given batch, the image of the error is calculated, in the case of a simple regression, as a sum, for example weighted, of the errors calculated at each of the N conversion cycles between the input data item and its digital counterpart. Such weighting makes it possible, for example, to take into account the decrease in the error with the increase in the index n during the N conversion cycles, and, for example, also to maximize the performance of the converter for each conversion cycle.

[0156] Usually, the Fcost function can, in addition to being based on a fidelity function Ffid, be based on or include one or more regularization functions. These regularization functions are, for example, applied to layers of the model or implemented in the model in the form of a specific layer that does not necessarily have a hardware counterpart. Usually, a regularization is applied to weights or data of the model and aims to guide supervised deep learning, for example by expressing a target result (i.e. a target specification), for example in the hardware implementation that will be made of the converter from the trained model.

[0157] Thus, preferably, the Fcost function comprises at least one regularization function.

[0158] For example, said at least one regularization function is determined by a functional property and / or a material property of the converter that one wishes to obtain after supervised deep learning.

[0159] For example, one of these regularizations aims to ensure that the excursions of the modulator's internal signals are bounded, which helps to avoid saturations in the hardware converter that will be manufactured from the trained model.

[0160] For example, a regularization function aims to keep, for each training batch, and for each of the S training data of the batch, the output signals Ak0 of the K cells Cellk of the encoder in K respective value ranges from -Δk to +Δk, with Ak a positive threshold value for example determined by the value of the supply voltage that the converter will receive. By defining, for each training batch, Ak0 [s] as the maximum value taken during the N cycles of a conversion by the signal Ak0 for an input data xa of rank s of the training batch considered, this regularization function Fdr(Ak0) can, for example, be written, for each training batch: [Math 14] clip(Ak0[s],-Δk,Δk) the function that forces the value Ak0[s] to the value -Δk when Ak0[s] is less than -Δk, and to +Δk when the value Ak0[s] is greater than +Δk. As an example, in the rest of the description, Ak is equal to 0.4 in this example where the signals (or data) quantized in the encoder, i.e. the signals Bkd, have a dynamic corresponding to a range from -0.5 to 0.5.

[0161] Thus, according to an example, the function Fcost can be written: [Math 15] Fcost(xa,xq,Ak0) = Ffid(xa,xq ) + λ * Fdr(Ak0) with λ a scalar factor.

[0162] In the same way as a fidelity function, for each training data of index s of a given training batch, a regularization function may be calculated only at the Nth conversion cycle, or, alternatively, be calculated at at least one particular cycle C[n], for example each of the N conversion cycles C[n]. Furthermore, a regularization function calculated at a given cycle C[n] may be calculated from a sequence of data obtained up to this cycle, and may be non-linear, for example corresponding to a minimum or maximum value of a calculation performed on these data, or linear, for example corresponding to a weighted sum of a calculation performed on these data.

[0163] The regularization function Fdr in the Fcost function advantageously aims to ensure the stability of the recurrent modulator for a given value N of oversampling rate.

[0164] Of course, the person skilled in the art will be able to provide other regularization functions determined by functional and / or material properties of the converter to be manufactured.

[0165] In addition to the Fcost function determined by a fidelity function Ffid and, preferably, by at least one regularization function, constraints and / or regularization terms may be applied to the generic model

[0166] Preferably, at least one constraint and / or at least one regularization term is applied to the generic model, on the model weights or on the data.

[0167] For example, at least one constraint and / or at least one regularization (or regularization term) applied to the generic model is determined by a material property and / or a functional property that the converter to be manufactured must respect.

[0168] For example, a constraint is a characteristic that is forced into the model during supervised deep learning. A constraint can be implemented by adding a layer to the model that will not have a hardware counterpart (or in other words, a hardware variation), for example by applying a mask to the model's weights, or by applying a function to layers of the model. A constraint can apply to the model's data tensors, or to the model's weights. A constraint is, for example, a function or layer that acts directly on the data or weights it receives, i.e., it can modify the values ​​of this data or these weights.

[0169] For example, a regularization aims to guide learning in order to obtain a desired result in the trained model or in its hardware counterpart. A regularization can be implemented by adding a layer to the model that will not have a hardware counterpart and that will aim to calculate quantities on the data passing through it without modifying this data, these quantities being then used in the calculation of the cost function, for example by being added to the fidelity function. A regularization can also be implemented by applying a function to layers of the model. A regularization can be applied to the data tensors of the model and is then for example called an activity regularizer, or to the weights of the model and is then for example called a kernel regularizer.Regularization layers or functions on weights or data allow, for example, penalties to be assigned. additional to the cost function, these penalties being defined by deviations between quantities calculated on the latent weights or the model data, and the expected values ​​for these quantities.

[0170] For example, a constraint applied to the model is determined by the maximum possible dynamic range at the output of each Cellk cell in the model. For example, this constraint corresponds to the addition of a clipping layer at the output of each Cellk cell, which clips (or saturates) the output signals of the Cellk cells when these signals go outside the maximum allowed dynamic range.

[0171] For example, a constraint applied to the model is determined by a targeted robustness of the manufactured converter to temporal non-idealities, for example related to kTC noise when the weights of the manufactured converter are implemented by capacitors or capacitive circuits. For example, this constraint corresponds to the addition, on each internal node of the encoder, of a data augmentation layer adding a random Gaussian noise on this internal node.

[0172] For example, a constraint applied to the model weights, in particular to the encoder weights, is determined by a sizing of the circuits (capacitive or resistive) implementing the weights. This constraint corresponds to the search for a common denominator for the encoder weights or a subgroup of encoder weights. The goal of this constraint is to find an adequate sizing of the model weights that favors obtaining a common denominator for all the converter weight values ​​or a subgroup of converter weights. This constraint amounts to implementing supervised deep learning using training focused on the quantification (QAT from the English "Quantification Aware Training"). QAT type training is well known and allows the learning of quantified WM weights (see [Math 8]), these quantified weights being derived from the latent weights, noted WM 1. For example, training to obtain quantized weights includes a Q-step uniform quantization implemented during the feedforward phase, combined with a straight through estimator for the gradient during the back propagation phase. As an alternative example, the person skilled in the art will also be able to provide, instead of a direct estimator, any proxy for the gradient back propagation phase. For example, a proxy makes it possible to replace, for the calculation of the gradient, a non-derivable function used during the inference, such as for example the quantization function, with an alternative function on which the gradient can be calculated. For example, the proposed quantization function is based on the round ( ) function which rounds the fractional part to the nearest integer.The input dynamics of the round() function is set, for example, from the maximum value W. : max of the absolute values ​​of the latent weights of the encoder, with: [Math 16] For example : [Math 17] with qstep the quantization step. A example title qstep is equal to 1 / (round ( (2 -1 ) / W 1 max) ) and q an integer allowing to fix the granularity of the quantification carried out and to fix the maximum ratio between the greatest and the lowest absolute weight. As another example, qstep is a value learned using a weight W l scale learned during training, and is then for example equal to 1 / (round ( (2 e ? -1 ) / W 1 scale) ) .

[0173] In the example above, quantization-driven supervised deep learning allows for finding an adequate sizing of the model weights that favors obtaining a common denominator for all weight values. This allows the implementation of the weights by switched capacitors, each corresponding to one or more identical unit capacitors, each of the unit capacitors having the same value determined by the common denominator obtained during training. In another example, this allows the implementation of the weights by resistors, each corresponding to one or more identical unit resistors, each of the unit resistors having the same value determined by the common denominator obtained during training.

[0174] As an example, a regularization that can be applied to the model during supervised deep learning is determined by a surface area of ​​the converter to be manufactured, and, more specifically, aims to reduce this surface area. For example, it is planned to introduce a regularization applying to the encoder weights that is analogous to a LO norm (representative of the number of non-zero values) or any equivalent form, for example an L1 regularization under certain assumptions, to limit the number of electrical connections in the converter, or, in other words, to prune electrical connections in the converter.

[0175] For example, a constraint applied to the model is determined by a surface of the converter to be manufactured and, more specifically, aims to reduce this surface by hiding connections in the encoder. For example, The encoder model weights are hidden during training to limit the number of effective connections between encoder cells, resulting in a more compact final converter. For example, the WM latent weight matrix 1is multiplied by a binary mask, i.e. by a matrix of latent masking weights, so as to deactivate the corresponding connections. This binary mask is, for example, obtained by thresholding a matrix of latent masking weights. To control the number of harmed weights of the binary mask, a regularization function can depend on the number of harmed weights after thresholding the masking weight matrix, and add a term to the cost function which will be determined by a difference between the number of harmed weights of the binary mask counted by the regularization function and a targeted or expected number of harmed masking weights.For example, rather than being determined by a target surface for the converter to be manufactured, the constraint of applying a binary mask to weights of the model is determined by a target topology for the converter to be manufactured, and the mask is configured to remove data paths (or connections) in the model that do not correspond to any path in the target topology.

[0176] For example, a constraint applied to the model is determined by a surface area of ​​the converter to be manufactured and, more specifically, aims to reduce this surface area. For example, weight clipping techniques can be implemented to reduce the surface area of ​​the converter.

[0177] For example, a regularization applied to the model is determined by material properties of the converter to be manufactured and aims to avoid attenuation of modulator signals. For example, this regularization is applied to the weights corresponding to the feedback path with a delay of one cycle of each cell Cellk, that is to say for example to the weight Wapkl with k equal to p of each cell Cellk with index k equal to p, for example to the weights Walll, Wa221 and Wa331 in the example of figure 6. As an example, this regularization introduces a penalty added to the cost function when one or more of these weights are less than 1. In other words, this regularization corresponds to a regularization function determining the cost function with the fidelity function, and, for example, other regularization functions, for example the function Fdr. In other words, this regularization corresponds to a regularization function used in the calculation of the cost function.

[0178] For example, one or more constraints applied to the model are determined by hardware properties of the converter to be manufactured, and aim to emulate static errors on the value of the weights actually implemented in hardware and the value of the corresponding weights of the model and / or the finite gains of the operational amplifiers implementing in hardware the summation and / or integration functions of the model. For example, each of these constraints is realized by a layer without hardware correspondence which acts on the data or the weights of the model. For example, a data augmentation layer can be used to add an error on the effective weights of the model during the training phase, or even inference.As another example, an augmentation layer can be used downstream of the adder of each Cellk, to introduce a non-unit weighting modeling the gain error of the amplifier implementing the summation.

[0179] As an example, a constraint applied to the model weights (latent or quantized), and more particularly to the weight of the encoder model, is determined by functional properties of the converter to be manufactured, and aims to force the type, positive or negative, of at least some feedbacks implemented in the converter to be manufactured. This constraint consists of forcing the sign of given weights of the encoder model to force negative and positive feedbacks in the model. For example, the sign of weights corresponding to negative feedbacks is forced to be a negative sign, and the sign of weights corresponding to positive feedbacks is forced to be a positive sign.

[0180] For example, in addition to constraints and / or applied to the model, at least some of which are determined by material or functional properties of the converter to be manufactured, a normalization layer is optionally added to the output of the model. This normalization layer consists of adding a sizing factor (or weight) to the output of the decoder model, so as to adapt the dynamics of the output of the converter model to the index n of the current cycle C[n]. For example, the normalization layer is configured so that the converter provides a scaled output data item at each cycle. For example, a regularization function can be assigned to this normalization layer.For example, to smooth the reconstruction between each cycle, an L2 regularization is applied to the derivative of the absolute value of these sizing weights, so that these sizing weights have values ​​that evolve monotonically as a function of the oversampling value N.

[0181] For example, in addition to constraints and / or regulations and / or weightings applied to the model, at least some of which are determined by material or functional properties of the converter to be manufactured, learning strategies are optionally applied to the supervised deep training, or, in other words, are introduced into the supervised deep learning phase.

[0182] For example, this or these learning strategies aim to ensure stable behavior of the model during supervised deep training.

[0183] For example, one of these learning strategies involves implementing one or more callback functions to adjust characteristics of the training phase, for example from one training batch to the next, and / or from one training epoch to the next.

[0184] For example, one of these learning strategies consists of choosing statistical parameters on the input data provided to the model during the supervised deep learning phase. For example, each training batch is selected or constructed from training data, for example from a static database or generated on the fly, so that each training batch respects a statistical property. For example, the distribution of input and output data also allows the introduction of an implicit regularization of the model, for example a regularization favoring homogeneity of the converter performance over the entire dynamic range of the input signal.

[0185] As an example, one of these learning strategies concerns the initialization of latent weights of the encoder model. For example, the latent weights of the encoder model are initialized to purely random values. As another example, the latent weights of the encoder model are initialized to values ​​corresponding to the values ​​of the weights of a reference topology. As another example, the latent weights of the encoder model are initialized with the corresponding weight values ​​of a reference topology if these weights of the reference topology are unnullified, and with a random value otherwise.

[0186] As an example, a callback function of type "ReduceLROnPlateau" (Reduce learning rate on plateau) is used on a metric representative of the desired specifications, for example relating to the hardware implementation and / or the functionalities of the converter, at each end of a learning epoch. For example, this function aims to reduce the learning rate when the considered metric no longer varies. For example, the metric is representative of a hardware property of the converter to be manufactured. An example of a metric that can be used is determined by the ratio between the DR dynamics of the parameter to be inferred on the maximum conversion error on this DR dynamics (for example the quantization error). This metric is representative of a maximum number of quantization steps that can be used without there being a quantization error on this DR dynamics.For example, this metric can be expressed by the following formula [Math 18]: [Math 18].

[0187] For example, a callback function is used at the end of each learning epoch to automatically activate and deactivate random data augmentation layers added on the internal nodes of the encoder, for example data augmentation layers introducing white noise on these internal nodes. This can allow better convergence of the model during training.

[0188] For example, a callback function used during training allows to progressively deactivate static binary masks applied to the latent weights of the encoder model, that is to say that this callback function allows to progressively reactivate connections of the model during training, among the connections which were masked at the beginning of training.

[0189] As an example, a callback function used during training gradually decreases the value of q defined in relation to quantization-oriented learning (QAT).For example, training may start without weight quantization in a first set of training epochs, then weight quantization is enabled with a first quantization level q=ql (with ql an initial quantization level value) for a second set of training epochs starting from the best set of latent weights obtained at the end of the first set of training epochs, then, for subsequent sets of training epochs, each set of training epochs starts, for example, with the best set of latent weights obtained at the end of the previous set of training epochs by reducing the value of q, until a desired value of q determined by material properties of the converter to be manufactured is obtained.

[0190] Figure 9 schematically illustrates, by means of a flowchart, a method of designing (or sizing) a sigma-delta converter.

[0191] At a step 900 (block "SET K, N and D"), the hyperparameters of the model, namely the number K of cells Cellk, the oversampling rate N and the value D defining the delays, are defined by the designer. For example, other hyperparameters of the model can be defined by the designer at this step, such as the number of possible values ​​at the output of each quantizer or, in other words, the quantization resolution of the outputs Bkd.

[0192] For example, the value of the number N can be determined by a hardware constraint from a 902 specification ("HW SPEC" block) defining hardware and / or functional constraints that the converter should respect, as shown in figure 9.

[0193] For example, the value of the D number can be at least partly determined by this specification. For example, the D number can be reduced with the maximum surface area targeted for the converter. Indeed, the larger the D number, the greater the number of connections and weight of the model, and therefore the larger the surface area of ​​the converter will be.

[0194] For example, the number K may be at least partly determined by the specifications 902, for example by a maximum target area for the converter and / or by a target conversion accuracy of the converter. For example, the higher the number K, the larger the converter will be, and / or the higher the number K, the lower the conversion error, for example related to thermal noise and quantization error, will be. For example, the number K may be determined at least partly by the order M of the converter to be manufactured, K preferably being greater than or equal to M.

[0195] Although this is not illustrated in Figure 9, step 900 further comprises a step of determining a filter (or decoder) model from recurrent neural networks, so as to obtain, at the end of step 900, a converter model. By way of example, the filter comprises one or more successions (cascading) of simple recurrent neural networks. An example of a filter model for an analog-to-digital converter has been described in relation to Figure 8. The person skilled in the art will be able to provide other filter models modeled from recurrent neural networks, for example from at least simple recurrent neural networks, for an analog-to-digital converter, or even for analog-to-information converters taking an analog signal as input and providing information on this signal (frequency, amplitude, etc.) as output.

[0196] In an optional next step 904 ("MODEL CONSTRAINT AND / OR REG" block), constraints and / or regularizations are added directly to the converter model. For example, these constraints and / or regularizations are added in the form of layers that have no material counterpart in the converter that will be manufactured, in the form of functions applied to layers of the model, or in the form of masks applied to weights of the model. For example, at least one regularization may be applied to the model in the form of an additional term in the cost function.

[0197] Preferably, at least one constraint and / or at least one regularization applied to the generic model is determined by a material property and / or a functional property that the converter to be manufactured must respect, as illustrated in figure 9 by an arrow going from block 902 to block 904.

[0198] For example, at least one constraint and / or at least one regularization applied to the generic model is determined by saturation values ​​of the modulator's internal signals and corresponds, for example, to the addition of cutoff layers to the model.

[0199] For example, at least one constraint applied to the generic model is determined by a target robustness of the converter to temporal non-idealities, and consists, for example, of inserting data augmentation layers to model noise in the converter.

[0200] For example, at least one constraint applied to the generic model is determined by an implementation of the weights in a quantized form, and corresponds, for example, to an implementation of deep learning using quantization-driven training. In other words, this constraint corresponds to the addition of a quantization layer of the latent weights of the model.

[0201] For example, at least one constraint applied to the generic model is determined by a target surface for the converter to be manufactured, and corresponds, for example, to the application of at least one binary mask to weights of the model and / or to the implementation of a weight cutoff technique.

[0202] For example, at least one constraint applied to the generic model is determined by errors on the finite gains of operational amplifiers that will be used to implement the converter and corresponds, for example, to the addition of an augmentation layer downstream of the adder of each Cellk, to introduce a non-unit weighting modeling the finite gain error of the amplifier implementing the summation.

[0203] For example, at least one constraint applied to the generic model is determined by maximum static errors targeted on component values ​​implementing the model weights and corresponds, for example, to the addition of errors on model weights.

[0204] For example, at least one constraint applied to the generic model is determined by a target converter or modulator topology, and consists of masking weights from the generic model to remove data paths in the model that do not correspond to any data path in the target topology.

[0205] For example, at least one constraint applied to the generic model is determined by the direction of the data paths in the converter to be manufactured (direct paths or feedback paths), and consists of forcing the signs of certain weights of the generic model to implement positive and / or negative feedback loops in the converter to be manufactured.

[0206] For example, at least one constraint applied to the generic model is determined by a maximum target area, and consists of hiding encoder weights to reduce the number of data paths in the model, which amounts to reducing the number of connections in the manufactured converter, and therefore its area.

[0207] For example, at least one regularization applied to the model is determined by a target maximum area, and consists, for example, of an L1 regularization to limit the total number of weights used.

[0208] For example, at least one regularization applied to the model is determined by an output dynamics of the converter to be manufactured. For example, an L2 regularization can be implemented on the derivative of the absolute values sizing factors, or weights, of a weighting layer added to the model output.

[0209] At a following step 906 (block "DEFINE Fcost"), a cost function is defined for the following step of supervised deep training 908 (block "SUPERVISED DL"). The definition of the Fcost function consists of defining a fidelity function Ffid from which the Fcost function is expressed.

[0210] Preferably, the function Fcost is determined by the function Ffid and by at least one regularization function as illustrated in FIG. 9 by block 910 (block "Fcost REG") indicating that the cost function Fcost determined in step 906 is partly determined from a regularization function.

[0211] For example, the Fcost function is determined in part from a regularization function determined by a material property and / or a functional property of the converter to be manufactured as illustrated in Figure 9 by the arrow going from block 902 to block 910. For example, the Fcost function is determined in part from a regularization function, for example Fdr, determined by a maximum excursion of the output signals of each cell Cellk of the modulator, and / or, for example, by a regularization function adding a penalty in the cost function when certain weights, for example the weights Wapkl of each cell Cellk of index k equal to p, are less than 1.

[0212] In the next step 908, the generic converter model is trained by implementing supervised deep training.

[0213] As previously stated, learning strategies can be planned during training deep supervised, as illustrated by a block 916 (“DL STRATEGY” in Figure 9).

[0214] As an example, at least one learning strategy corresponds to a recall function 918 (block "CB FCT") as illustrated in FIG. 9 by an arrow going from block 916 to block 918. The recall function is applied to the learning step 908, i.e. used during step 908, as illustrated in FIG. 9 by an arrow going from block 918 to block 908. Examples of such recall functions have been given previously.

[0215] For example, at least one learning strategy corresponds to a statistical property 919 (block "STAT") applied, or imposed, on the training data as illustrated in Figure 9 by an arrow going from block 919 to block 918. For example, each training batch is selected or constructed from the training data so that each training batch respects a statistical property. For example, to train a converter model configured to convert a continuous analog signal into its digital counterpart, each training batch is constructed so that the average of the absolute values ​​of the training data that composes it is the same in all the training batches, and is, for example, equal to half the positive input dynamics of the converter to be manufactured.

[0216] For example, at least one learning strategy corresponds to an initialization of the latent weights of the model 921 (block "INIT"), and corresponds to a way of initializing the latent weights of the model as illustrated by an arrow going from block 921 to block 908 in figure 9. Various ways of initializing the latent weights of the model have been described previously, for example randomly and / or from the weights of a topology of reference and / or from the weights of a model obtained at the end of a previous step 908.

[0217] The training step 908 is then implemented. It is during the training step 908 that the various learning strategies are applied, such as for example the recall functions and / or the statistical properties defined on the training data and / or the initialization choices of the latent weights of the model.

[0218] At the end of one or more training epochs 908, at a following step 920 (block "Ok?"), it is checked whether the model obtained, i.e. the weights of the model which are obtained after the implementation of a step 908, satisfy the material and / or functional properties defined for the converter to be manufactured. In other words, this step 920 consists of checking whether a training stopping criterion has been reached or not.

[0219] If this is not the case (output NO of block 920), step 908 is implemented again using as starting model the trained model obtained at the end of the previous step 908, or a trained model obtained at the end of one of the epochs of the previous step 908, or a model having different latent weight initialization conditions, for example an initialization of the latent weights which is random and independent of any previously learned topology or any reference topology. As another example, step 908 can be implemented again from a generic model obtained by implementing again steps 900, 904, 906 and 916 but with different constraints and / or regularizations and / or learning strategies.

[0220] If this is the case (output Y of block 920), step 920 is followed by a step 922 ("RESULTING TOPO" block). At this step 922, we have a trained model which satisfies the material properties and / or the material properties that determined the constraints and regularizations applied to the generic model in step 904 and 906. This model defines, or determines, a topology of the converter to be manufactured, that is to say, for example, the connections (or data paths) in the converter to be manufactured, the weights to be applied to each internal signal of the converter, the delays to be applied, and the summations to be implemented.

[0221] In a following step 924 (block "CIRCUIT MAPPING"), the topology of step 922, i.e. the trained model received in step 922, is mapped onto, or transformed into, hardware. For example, each data path of the trained model is implemented by an electrical connection, and / or the weights are implemented by resistive or capacitive components and / or the delays are implemented by corresponding timing signals, the sums between data are implemented by summing circuits, for example from operational amplifiers, etc.

[0222] Preferably, during this step of transforming the trained model into a circuit, the material properties and / or functional properties of the converter to be manufactured that were used in steps 900, 904, 906, 908 and 910 are respected, as illustrated in FIG. 9 by an arrow going from block 902 to block 924. For example, if a regularization based on the dynamics of the converter signals was applied to the model in step 904, the circuit is designed to respect this dynamics. As another example, if the training is focused on quantization, the weights will each be implemented from a unit resistive or capacitive component. For example, if the model used during training includes constraint layers to emulate the maximum gain of the operational amplifiers implementing sums in the converter to be manufactured, the operational amplifiers actually used for the converter circuit have this maximum gain value.

[0223] Finally, in a subsequent step not illustrated, the circuit obtained at the end of step 924 is manufactured. In particular, as will be described in more detail later, the present description proposes a programmatically reconfigurable circuit which allows a hardware implementation of a sized encoder model obtained from the generic model described above.

[0224] Figure 10 illustrates, in a schematic, general and block-like manner, an example of how constraints and regularizations can be applied to the model during training. In other words, Figure 10 illustrates steps of the method described in relation to Figure 9.

[0225] In this figure 10, a block 2600 ("Latent W") represents the latent weights of the encoder. As illustrated by a block 2602 ("C,R"), regularization functions and / or constraints can be applied to these latent weights. For example, a constraint is applied to the latent weights and will directly act on the values ​​of the latent weights, for example by limiting the maximum value that these latent weights can take. For example, an L1 regularization is attached to the latent weights of the encoder, which will assign a penalty term to the cost function. In figure 10, the cost function is represented in the form of a block 2604 ("Fcost") and the penalty(s) assigned to the cost function are represented in the form of a block 2606 ("Pen").

[0226] Additionally, constraints can be applied to the encoder's latent weights by means of one or more layers that will not have a material counterpart. In Figure 10, these constraints are represented by a block 2608 ("C on Data") receiving the latent weights (block 2600), to which constraints and / or regularizations (block 2602) could be applied directly, and providing constrained weights represented in the form of a block 2610 ("Cons W") in Figure 10.

[0227] For example, block 2608 includes such a constraint layer implementing weight quantization. This constraint layer receives the latent weights 2600, and provides quantized weights. The constrained weights 2610 will then be quantized weights.

[0228] For example, when aiming for a capacity-based implementation of weights, block 2608 may include a constraint layer emulating the dispersion of capacity values ​​related to the manufacturing of these capacities. This layer will add fixed dispersions to the data it receives, this data being for example the quantized weights provided by the constraint layer of the example above.

[0229] The constrained latent weights 2610 thus obtained can then directly correspond to the effective weights of the encoder model, the latter being represented by a block 2612 ("Eff W") in figure 10.

[0230] However, as illustrated in the example of Figure 10, these constrained latent weights 2610 can be multiplied by a mask, the result of this multiplication then corresponding to the effective weights 2612.

[0231] For example, in Figure 10, latent masking weights are provided, represented as a block 2614 ("Latent Mask"). In the same way as for the latent weights 2600 of the encoder, constraints and / or regularizations can be applied directly to the latent weights of masking 2614. In Figure 10, these constraints and / or regularizations directly applied to the masking latent weights 2614 are represented in the form of a block 2616 ("C,R").

[0232] At least one constraint is applied to the latent masking weights 2614 by a layer without hardware counterpart, represented in Figure 10 by a block 2618 ("C on data"). This layer 2618 receives the latent masking weights 2614, and provides constrained latent masking weights represented in the form of a block 2620 ("Cons Mask") in Figure 10. For example, layer 2618 performs thresholding on levels of the weights 2614. In practice, the constrained latent masking weights 2620 correspond to a binary mask.

[0233] To control the binary mask 2620, for example the rate of nuisance weights in the binary mask 2620, one or more regularization functions 2616 may be applied to the masking latent weights 2614, and / or one or more regularization functions 2622 ("R on data" block) may be applied to the weights 2620 (i.e., the binary mask). In practice, when provided, these regularizations do not modify the value of the weights of the binary mask 2620. For example, a regularization function 2622 counts the number of nuisance weights in the binary mask 2620, and assigns a penalty 2606 proportional to the deviation between the counted number and a desired number.

[0234] The constrained latent weights 2610 of the encoder are then multiplied by the binary mask 2620, as represented by a block 2624 ("Mult") in Figure 10, to obtain the effective weights 2612.

[0235] These effective weights are used in the encoder model, represented as a block 2626 ("Enc Mod") in Figure 10, and correspond to the weights that will be physically implemented when the trained model is satisfactory in terms of targeted performance.

[0236] In addition, layers without hardware counterpart may be applied, i.e. added, to the encoder model 2626. In FIG. 10, these layers without hardware counterpart are represented in the form of a block 2628 ("Layers"). For example, one or more layers 2628 correspond to constraint layers. For example, a constraint layer 2628 makes it possible to saturate signals in the encoder model 2626 when these signals exceed a threshold. As another example, one or more layers 2628 correspond to data augmentation layers. For example, a data augmentation layer 2628 makes it possible to add Gaussian temporal noise to signals of the encoder model 2626.

[0237] In Figure 10, the decoder model is represented as a block 2630 ("Dec Mod"). This block receives signals from the encoder model 2626, and provides output data Out. The encoder model 2626 receives input data In.

[0238] Although not detailed in Figure 10, regularization functions and / or normalizations can be applied to the 2630 decoder model.

[0239] During training, block 2626 receives the input data In and block 2630 provides the corresponding output data Out.

[0240] The Fcost function is then calculated from the Out data. More specifically, the Fcost function is calculated from a fidelity function 2632 ("Ffid") and, when there are any, penalties 2606 assigned to the cost function by regularization functions. The Fcost function is then representative of an error between the Out data obtained as output from the model, and the expected data for the In inputs supplied to the model.

[0241] This is followed by a BP step of backpropagation of the error. It is for example during this BP step that the model weights will be updated.

[0242] As previously indicated, the present description provides embodiments of a reconfigurable electronic device for implementing a recurrent encoder obtained by sizing the generic encoder model described previously. More particularly, this electronic device is configured to allow the implementation of any recurrent encoder sized from the generic model in which K is less than or equal to Kmax and D is less than or equal to Dmax, with Kmax an integer greater than or equal to 1, and Dmax an integer greater than or equal to 1. By way of example, in the remainder of the description, Kmax is equal to 3 and Dmax is equal to 2.

[0243] Figure 11 illustrates an embodiment of a portion of a programmatically reconfigurable device for hardware implementation of a sized converter model. More particularly, Figure 11 illustrates an example implementation of a cell circuit Cellk of the reconfigurable device, in an example where the weights are implemented by programmable capacitors (or capacitive components).

[0244] The top of Figure 11 represents the implementation of a programmable W-weight circuit, i.e. a circuit programmable with any of the weights Wpx, Wapkd or Wbpkd of a cell Cellk.

[0245] In this example, each weight circuit includes two circuits: Cpos and Cneg. When the weight programmed in the weight circuit is negative, the Cneg circuit will be used. Conversely, when the programmed weight is positive, the Cpos circuit will be used. For example, although not shown in Figure 10, the weight circuit receives a signal indicating what the sign of the weight is, and which of the Cpos and Cneg circuits should therefore be used.

[0246] The Cneg circuit includes a programmable capacitance C. When programming the device, the capacitance will be programmed to a value equal to the absolute value of the weight W times the value of a unit capacitance CO, the resulting capacitance being able to be, for example, greater or less than the unit value CO. The capacitance C is connected between two nodes 1000 and 1002. A switch IT1 connects node 1000 to an input In of the Cneg circuit, and a switch IT2 connects node 1000 to an output Out of the Cneg circuit. A switch IT3 connects node 1002 to a reference potential.

[0247] The Cneg circuit comprises two control inputs wr and rd. Switch IT3 is closed when either of the wr and rd inputs of this Cneg circuit receives an active signal. Switch IT1 is controlled by a signal corresponding to the signal on the wr input of the Cneg circuit with, optionally, a delay to limit charge injections, and is closed when this delayed signal is active, open otherwise. Switch IT2 is controlled by a signal corresponding to the signal on the rd input of the Cneg circuit with, optionally, a delay to limit charge injections, and is closed when this delayed signal is active, and open otherwise.

[0248] The Cpos circuit includes a programmable capacitance C. When programming the device, the capacitance will be programmed to a value equal to the absolute value of the weight W times the value of a unit capacitance C0, the resulting capacitance being able to be for example greater or less than the value unit CO. Capacitance C is connected between two nodes 1004 and 1006. A switch IT4 connects node 1004 to an input In of the circuit Cpos, and a switch IT5 connects node 1006 to an output Out of the circuit Cpos. A switch IT6 connects node 1004 to the reference potential, and a switch IT7 connects node 1006 to the reference potential.

[0249] The Cpos circuit includes two control inputs wr and rd. Switch IT4 is controlled by a signal corresponding to the signal on the wr input of the Cpos circuit with, optionally, a delay to limit charge injections, and is closed when this delayed signal is active, open otherwise. Switch IT5 is controlled by a signal corresponding to the signal on the rd input of the Cpos circuit with, optionally, a delay to limit charge injections, and is closed when this delayed signal is active, open otherwise. Switch IT6 is closed when the signal on the rd input of the Cpos circuit is active, and open otherwise. Switch IT7 is closed when the signal on the wr input of the Cpos circuit is active, and open otherwise.

[0250] Although an example has been described above where each programmable weight circuit is implemented by a Cpos circuit and a Cneg circuit, and where, for each weight, the Cpos or Cneg circuit used after programming the weight in the weight circuit is determined by the sign of the weight, the person skilled in the art is able to adapt this example to the case where each programmable weight circuit is implemented by a single circuit corresponding, for example, to the Cpos circuit in which: an additional switch is connected between node 1004 and output Out to implement the function of switch IT2 of the Cneg circuit when the weight is negative, switch IT7, when the weight is negative, implements the function of switch IT3 of the Cneg circuit, switch IT5 then being unused in this case where the weight is negative.

[0251] The bottom of Figure 11 represents the implementation of a cell circuit Cellk, programmed by the cell Cellk of index k equal to 1 in the example of Figure 10. In this example, Kmax is equal to 3 and Dmax is equal to 2. Thus, the cell circuit Celll comprises 2. Kmax . Dmax + 1 weight circuits, that is to say thirteen weight circuits in this example.

[0252] In this figure, each circuit implementing a corresponding weight is represented by a block having the same reference as the weight it implements. Each circuit implementing a weight Wapkd, respectively Wbpkd receives on its input In the signal Ak0, respectively BkO, from the cell Cellk.

[0253] The signals supplied to the wr and rd inputs of the weight circuits make it possible to implement a data transfer between the Kmax cells Cellk during the same conversion cycle C[n], and between two successive conversion cycles, by implementing the corresponding d cycle delays.

[0254] The Cellk cell circuit further comprises a Sample circuit. An input In of the Sample circuit receives the signal x. In the Cellk cell circuit, the output Out of the Sample circuit is connected to the input In of the circuit implementing the weight Wkx of the cell circuit. The Sample circuit comprises a switch IT8 connected between the input In and the output Out of the Sample circuit, and a switch IT9 connected between the output Out of the Sample circuit and the reference potential.

[0255] The Sample circuit also receives a control signal Rst. Switch IT8 is configured to be closed when the Rst signal is inactive, and open otherwise, while switch IT9 is configured to be closed when the Rst signal is active, and open otherwise. For example, the Rst signal is switched to the active state during a reset phase prior to each conversion in N cycles.

[0256] The cell circuit Cellk includes a SUMk circuit. For example, the cell circuit Celll shown in Figure 10 includes a SUM1 circuit. The SUMk circuit includes an operational amplifier AOP . The AOP amplifier of the cell Cellk has its inverting input (-) connected to an input In of the SUMk circuit of the cell circuit, this input In being connected to the node 108k of the cell circuit (1081 in Figure 11 which represents the cell Celll, or, in other words, the cell Cellk with index k equal to 1). The AOP amplifier has its non-inverting input (+) connected to the reference potential. A unit capacitor C0 is connected between the output and the inverting input of the AOP amplifier. A switch IT10 is connected in parallel with the unit capacitor C0. A switch IT11 couples the output of the AOP amplifier of the SUMk circuit to the output Out of this SUMk circuit. A switch IT12 is connected between the output Out of the SUMk circuit and the reference potential.

[0257] The SUMk circuit receives the Rst signal. Switch IT11 is closed when the Rst signal is inactive, open otherwise. Switch IT12 is closed when the Rst signal is active, open otherwise.

[0258] The SUMk circuit further receives a control signal Rstk from the cell circuit Cellk to which this circuit belongs. For example, in Figure 11, the SUM1 circuit receives the signal Rstl. The switch IT10 is closed when the signal Rstk received by the SUMk circuit to which it belongs is active, open otherwise. For example, in Figure 11, the SUM1 circuit receives the Rstl signal.

[0259] In the cell circuit Cellk, the output Out of the circuit SUMk provides the signal Ak0 of the cell. In the example in Figure 11, the circuit SUM1 provides the signal A10 of the cell Celll on its output Out.

[0260] To provide the BkO signal, the cell circuit Cellk comprises a Quantk circuit having its input In connected to the output Out of the SUMk circuit of this cell circuit Cellk, and its output Out providing the BkO signal of the cell. In the example of Figure 11, the Quanti circuit has its input In connected to the output Out, and its output Out providing the B10 signal of the cell Celll.

[0261] For example, for a two-level quantization, the Quantk circuit includes a threshold comparator COMP whose one input, for example non-inverting, is connected to its input In, and whose other input, for example inverting, is connected to the reference potential. The comparator COMP of each Quantk circuit is clocked by a control signal Cmpk received by this circuit, and for example active in the high state. For example, the output of the COMP circuit is updated when its timing signal is active. For example, in Figure 11, the Quanti circuit receives the signal Cmpl .

[0262] In addition, the Quantk circuit includes a switch IT13 coupling the output of the comparator COMP to the output of the Quantk circuit, and a switch IT14 coupling the output Out of the Quantk circuit to the reference potential. The Quantk circuit receives the control signal Rst. The switch IT13 is closed when the Rst signal is inactive, open otherwise. The switch IT14 is closed when the Rst signal is active, open otherwise.

[0263] In Figure 11, the output signals of each of the 3 cells (or cell circuits) Cell1, Cell2 and Cell3 of the device are shown, which are supplied to the circuits implementing the weights of the illustrated cell circuit Cell1.

[0264] Figure 12 illustrates, at the top, a more detailed implementation of a programmable and reconfigurable device 12 for implementing a trained modulator model, in the case where Kmax is equal to 3 and Dmax is equal to 2.

[0265] In Figure 12, the programmable device 12 therefore comprises Kmax cell circuit Cellk each corresponding to a cell circuit Cellk as illustrated in Figure 11. Each cell circuit Cellk comprises a set of a summing circuit SUMk and a quantization circuit Quantk and 2. Dmax. Kmax programmable weight circuits each connected to the input of the circuit SUMk of the cell circuit Cellk.

[0266] In Figure 12, each cell circuit Cellk provides the signals Ak0 and Bk0, i.e. the undelayed versions of the unquantized and quantized outputs of the corresponding cell Cellk. Indeed, the delayed versions of these signals are obtained (or generated) directly in the weight circuits corresponding to the weights that are applied to these delayed outputs, by means of the control signals provided to these weight circuits. For example, the weight circuit Wa211 which, once programmed, implements the corresponding weight Wa211 that must be applied, in the cell Cell2, to the unquantized and one-cycle delayed output signal of the cell Celll, receives the output signal Ak0 from the cell circuit implementing the cell Celll, and is therefore connected to the output of the circuit SUM1 of the device 12. More generally, in each cell circuit Cellk, the weight circuits configured to be programmed by weights Wapkd and Wbpkd where d is greaterstrictly at 0 are connected to the outputs of the respective circuits SUMk and Quantk. More precisely, if we take the example of the cell Cell2, we will sample for example the output A10 of the cell Celll in the block Wa210 with the signal wr2 then this data will be read via the signal rd2. On the other hand, the output A10 of the cell 1 will be sampled in the block Wa211 only after the activation of rd2, so that this data is integrated into the cell Cell2 with the circuit SUM2 in the next cycle. We can therefore for example sample A10 in the block Wa211 via the signal wrl, that is to say just before the update of the output A10, that is to say before the reset of the circuit SUM1 by the signal Rstl. We could have used as an alternative the signal wr3.More generally, during a given cycle, one can obtain the shifted versions of the Ak0 signals of the Cellk cells by sampling them in the corresponding blocks via the wrl signal, that is, at the beginning of the following cycle, just before the SUM1 circuit is reset.

[0267] In the device 12, each weight circuit therefore comprises at least one programmable capacitive element and switches configured to implement sampling (or memorization) on the at least one programmable capacitive element.

[0268] In Figure 12, the device 12 further comprises a control circuit CTRL shown schematically in the form of a block. This circuit is configured to be programmed from the weight values ​​of the dimensioned encoder model, and to provide, from this programming, the control signals to the weight circuits, the SUMk circuits, the Quantk circuits and the SAMPLE circuits of the device 12. For example, it is this control circuit which will provide each weight circuit with the indication of the sign of the programmed weight. in this weight circuit. More generally, this CTRL circuit is programmed from the values ​​of the weights of the K weight vectors Wk, and is configured to control summations and quantifications in the reconfigurable device so as to implement, at each cycle C[n], the operation described in relation to figures 6 and 7, i.e. the calculations of the vectors Qk[n].

[0269] Timing diagrams of the control signals, in an example where each of the control signals is active high and where the device is programmed with a sized encoder model in which D is equal to Dmax and K is equal to Kmax, are shown at the bottom of Figure 12. More particularly, these timing diagrams illustrate a reset phase Reset and a first cycle C[l] of a conversion over N cycles C[n].

[0270] The implementation of the CTRL circuit of the device 12 so that the latter provides, once programmed from the values ​​of the weights of the trained encoder model, the control signals to the inputs rd and wr of the circuits implementing the weights, the indication of the sign of the weight programmed in each weight circuit, the Kmax signals Cmpk, the Kmax signals Rstk and the signal Rst to the Kmax cell circuits Cellk of the device 12, so as to obtain the operation described in relation to figures 5, 6 and 7 is within the scope of the person skilled in the art from the present description.In particular, when it is indicated that the CTRL circuit is programmed from the values ​​of the weights of the dimensioned encoder model, in the embodiment of figures 11 and 12, this does not necessarily mean that the CTRL circuit receives the values ​​of these weights during the programming of the device 12, but that it can receive programming data obtained from these weight values, for example by means of a circuit of the device 12 (not shown in the figure. 11 and 12) or an electronic system external to the device 12.

[0271] In the embodiment of Figures 11 and 12, each weight circuit, for example each pair of capacitance C of a weight circuit implemented by two circuits Cpos and Cneg or each capacitance C of a weight circuit implemented by a single circuit comprising only one capacitance C, corresponds to a point or memory element of a programmable memory of the device 12, each memory element being configured to store a value that is not necessarily binary. The programming of this memory and of the CTRL control circuit from weight values ​​makes it possible to reconfigure the device so that it implements an encoder corresponding to these weight values. For example, the CTRL circuit is also programmed from the values ​​of the weights of the dimensioned model to generate the control signals and the sequencing between these control signals, so as to implement the operation described above of the device 12.For example, the CTRL circuit is programmed with a file generated from the weight values ​​of the dimensioned model, this file indicating the control signals to be generated and their sequencing.

[0272] In the example above, the device 12 therefore allows, thanks to a step of programming its memory and its CTRL circuit from weight values ​​of a sized encoder model, the implementation of any recurrent encoder sized from the generic model in which K is less than or equal to Kmax and D is less than or equal to Dmax.

[0273] Figures 13, 14, 15, 16 and 17 illustrate another embodiment of a programmatically reconfigurable device 17 for the hardware implementation of a sized converter model. More particularly, these Figures illustrate an example of implementation where the weights are implemented by programmable resistors (or resistive components).

[0274] More particularly, as illustrated in Figures 13 and 17, each weight of a cell Cellk, i.e., any one of the cell's weights Wpx, Wapkd, or Wbpkd, is implemented by a weight circuit Rw. The circuit Rw includes a programmable resistor R. When programming the device, the resistor R will be programmed to a value equal to the value of a unit resistor RO divided by the value of the weight. The resistor R is connected between two nodes 1200 and 1202, with the node 1202 being connected to an output Out of the circuit Rw. Furthermore, each circuit Rw comprises two inputs Inl and In2 and a multiplexer MUX having its two inputs connected to the respective inputs Inl and In2, and its output connected to node 1200. When the weight programmed in the circuit Rw is negative, the multiplexer couples the input Inl to node 1200, and, conversely, when the weight programmed in the circuit Rw is positive, the multiplexer couples the input In2 to node 1200.Although not illustrated in Figure 12, the multiplexer MUX receives a binary control signal whose state is determined by the sign of the programmed weight. As an example, this control signal is provided by a CTRL control circuit shown in block form in Figure 17, for example a CTRL control circuit providing a control signal to each of the multiplexers MUX of the circuits Rw.

[0275] Figure 17 represents the device 17, in the case where Kmax is equal to 3 and Dmax is equal to 2.

[0276] In this figure, each circuit Rw implementing a corresponding weight is represented by a block having the same reference as the weight it implements. Furthermore, the device 17 includes Kmax corresponding cell circuits each to a cell Cellk of the encoder model. In Figure 17, as in Figure 12, each cell circuit is designated by the same reference as the cell Cellk it implements. In each cell circuit Cellk, each Rw circuit has its output Out connected to a node 1201k of the cell. For example, in Figure 17, the Rw circuits of the cell circuit Celll all have their outputs connected to node 12011. In addition, each Rw circuit receives on its inputs Inl and In2 a pair of signals corresponding to an output signal of one of the cell circuits Cellk to which the weight implemented by this circuit is to be applied.

[0277] Each cell circuit Cellk comprises a SUMk circuit as shown in Figure 17, an implementation of a SUMk circuit being illustrated in Figure 14.

[0278] Each SUMk circuit comprises an operational amplifier AOP and a switch IT15 coupling the inverting input (-) of the AOP amplifier to the input In of the SUMk circuit, this input In being connected to the node 1201k of the cell circuit Cellk to which the SUMk circuit belongs. The AOP amplifier has its non-inverting input (+) connected to the reference potential. A unit capacitor C0 is connected between the output and the inverting input of the AOP amplifier. A series association of a switch IT16 and a unit resistor R0 is connected in parallel with the capacitor C0. The output of the amplifier is connected to the output Out of the SUMk circuit.

[0279] Each SUMk circuit receives a control signal rdk, for example supplied by the CTRL circuit (figure 17). Switch IT15 is closed when the rdk signal is active, open otherwise. Switch IT16 is closed when the rdk signal is active, open otherwise.

[0280] Furthermore, although not shown in Figure 14, each SUMk circuit may include an input of reset controlling a reset switch connected in parallel with the CO capacitor. The reset switch is closed, respectively open, when a reset signal received by this reset input is active, respectively inactive. In this case, this reset input receives a Rst-Cycle signal which has a pulse in the active state at the beginning of each cycle C[n], before any other signal is set to the active state during this cycle.

[0281] As shown in Figure 17, each cell circuit Cellk comprises a Quantk circuit having its input In connected to the output Out of the corresponding SUMk circuit, and an output Out. An implementation of a Quantk circuit is illustrated in Figure 15.

[0282] For example, for a two-level quantization, each Quantk circuit includes a threshold comparator COMP whose one input, for example non-inverting (+), is connected to its input In, and whose other input, for example inverting (-), is connected to the reference potential. The comparator COMP of each Quantk circuit is clocked by a control signal Cmpk received by this circuit. For example, the output of the COMPk circuit is updated when its timing signal is active.

[0283] As shown in Figure 17, each Cellk cell circuit further comprises several SH circuits, each providing an output signal corresponding to an output of the Cellk cell. Each SH circuit is a memory circuit configured to sample (or store) an output voltage of a Quantk or SUMk circuit. An implementation of an SH circuit is illustrated in Figure 16. In this implementation, each output signal of an SH circuit, corresponding to an output signal of a Cellk cell, corresponds to a pair of signals provided to the inputs Inl and In2 of a circuit Rw corresponding to a weight to be applied to this cell output signal, and only one of the signals of the pair of signals is selected by the multiplexer of the circuit Rw according to the sign of the weight.

[0284] Each SH circuit comprises an input In and two outputs Outl and Out2 and is configured to store on capacitors an image of the voltage received on its input In. Furthermore, depending on how each SH circuit is controlled by a control signal received on its input rst and a control signal received on its input wr, each SH circuit allows to implement or not a delay of one cycle C[n] between its input and its output. Each SH circuit also allows, when its outputs Outl and Out2 are connected to the respective inputs Inl and In2 of a circuit Rw, to implement the sign of the weight corresponding to this circuit Rw, by selecting with the multiplexer MUX of the circuit Rw one or the other of the two inputs Inl and In2.

[0285] More particularly, as shown at the bottom of Figure 16, each SH circuit comprises a circuit A coupling the input In of the SH circuit to the output Out1, and a circuit B coupling the input In of the SH circuit to the output Out2.

[0286] Circuit A comprises a unit capacitor CO connected between a node 1204 and the reference potential. A switch IT17 couples the input In to node 1204, and a switch IT18 couples the node 1204 to the reference potential. A unit analog buffer circuit Buff couples the node 1204 to a node 1206. A switch IT19 couples the node 1206 to the output Outl and a switch IT20 couples the output Outl to the reference potential.

[0287] Switch IT17 is closed when the signal received by the wr input is active, open otherwise. Switches IT18 and IT20 are closed when the signal received by the input rst is active, otherwise open, switch IT19 being closed when the rst signal is inactive, otherwise open.

[0288] Circuit B includes a unit capacitor CO connected between a node 1208 and a node 1210. A switch IT21 couples the input In to node 1208, a switch IT22 couples the node 1208 to the reference potential, a switch IT23 couples the node 1210 to a node 1212, and a switch IT24 couples the node 1210 to the reference potential. An analog unit buffer circuit Buff couples the node 1212 to a node 1214. A switch IT25 couples the node 1214 to the output Out2 and a switch IT26 couples the output Out2 to the reference potential.

[0289] Switch IT21 is controlled by a signal corresponding to the signal received by the wr input to which, preferably, a delay has been applied to avoid charge injections, and is closed when this delayed signal is active, open otherwise. Switches IT22 and IT23 are closed when the signal received by the wr input is inactive, open otherwise. Switch IT24 is closed when the signal received by the wr input is active or when a signal corresponding to the signal received by the rst input to which, preferably, a delay is applied is active, and open otherwise. Switch IT25 is closed when the signal received by the rst input is inactive, open otherwise, switch IT26 being closed when the rst signal is active, open otherwise.

[0290] In the example of Figure 17 where Dmax is equal to 2, each cell circuit Cellk comprises two SH circuits connected to the output Out of the cell's SUMk circuit, the first of the two circuits providing the cell's output signal Ak0, and the other of the two circuits providing the cell's signal Akl. In addition, each Cellk circuit comprises two other SH circuits connected to the output Out of the cell's Quantk circuit, the first of the two circuits providing the output signal BkO of the cell, and the other of the two circuits providing the signal Bkl of the cell. For example, each SH circuit provides a pair of signals having identical absolute values ​​but opposite signs, and the multiplexer of the RW circuit to which this pair of signals is provided allows one of the two signals to be selected, which is equivalent to selecting the sign of the weight.

[0291] In Figure 17, the programmable device 17 therefore comprises Kmax cell circuits Cellk. Each cell circuit Cellk comprises a set of a summing circuit SUMk and a quantization circuit Quantk and 2.Dmax.Kmax programmable weight circuits Rw each connected to the input of the SUMk circuit of the cell Cellk. Furthermore, each cell circuit Cellk comprises Dmax SH circuits connected to the output of the Quantk circuit of this cell circuit Cellk, and Dmax SH circuits connected to the output of the SUMk circuit of this cell circuit, these SH circuits providing the Dmax pairs of output signals of the Cellk cells of the model. Furthermore, in each cell circuit Cellk, the weight circuits configured to be programmed by weights Wapkd and Wbpkd are coupled to the outputs of the respective circuits SUMk and Quantk.More particularly, in each cell circuit Cellk, the weight circuits configured to be programmed by weights Wapkd and Wbpkd are connected to the respective outputs of the SH circuits of the cell circuit Cellk.

[0292] In Figure 17, the device 17 comprises a control circuit CTRL shown schematically in the form of a block. This circuit is configured to be programmed from the weight values ​​of the dimensioned encoder model, and to provide, from this programming, the control signals to the weight circuits, the SUMk circuits, the Quantk circuits and the SH circuits of the device 17. For example, it is this control circuit which will provide each weight circuit the indication of the sign of the weight programmed in this weight circuit. More generally, this CTRL circuit is programmed from the values ​​of the weights of the K weight vectors Wk, and is configured to control summations and quantifications in the reconfigurable device so as to implement, at each cycle C[n], the operation described in relation to figures 6 and 7, that is to say the calculations of the vectors Qk[n].

[0293] Timing diagrams of the control signals, in an example where each of the control signals is active high and the device is programmed with a sized encoder model in which D is equal to Dmax and K is equal to Kmax, are shown at the bottom of Figure 17. More particularly, these timing diagrams illustrate a reset phase Reset and a first cycle C[l] of a conversion over N cycles C[n]. For example, the CTRL circuit provides Kmax wrk control signals for the SH circuits, Kmax rdk control signals for the SUMk circuits, a signal Rst and Kmax Cmpk control signals for the Quantk circuits.In this example: the first SH circuit from the top in cell Celll receives the signals wrl and Rst on its respective inputs wr and rst; the second SH circuit from the top in cell Celll receives the signals wr3 and Rst on its respective inputs wr and rst; the third SH circuit from the top in cell Celll receives the signals wrl and Rst on its respective inputs wr and rst; the fourth SH circuit from the top in cell Celll receives the signals wr3 and Rst on its respective inputs wr and rst; the first SH circuit from the top in cell Cell2. receives the signals wr2 and Rst on its respective inputs wr and rst; the second SH circuit from the top in the cell Cell2 receives the signals wr3 and Rst on its respective inputs wr and rst; the third SH circuit from the top in the cell Cell2 receives the signals wr2 and Rst on its respective inputs wr and rst; the fourth SH circuit from the top in the cell Cell2 receives the signals wr3 and Rst on its respective inputs wr and rst; the four SH circuits in the cell Cell3 receive the signals wr3 and Rst on their respective inputs wr and rst; the circuit SUM1 receives the control signal rdl; the circuit SUM2 receives the control signal rd2; the circuit SUM3 receives the control signal rd3; the circuit Quanti receives the control signal Cmpl; the circuit Quant2 receives the control signal Cmp2; and the circuit Quant3 receives the control signal Cmp3.

[0294] Furthermore, although not shown in the figure 17, when each SUMk circuit as described in relation to figure 14 comprises a reset input, this reset input of each SUMk circuit receives a reset signal Rst-Cycle common to all the SUMk circuits, this reset signal being switched to the active state at the start of each cycle C [n], before the signal rdl.

[0295] The implementation of the CTRL circuit of the device 17 so that the latter provides, once programmed from the values ​​of the weights of the trained encoder model, the control signals to the rdk inputs of the circuits implementing the weights, the indication of the sign of the weight programmed in each weight circuit, the Kmax signals Cmpk, the Rst signal and the Kmax signals wrk to the Kmax cell circuits Cellk of the device 17, so as to obtain the operation described in relation to Figures 5, 6 and 7 is within the scope of the person skilled in the art from the present description. In particular, when it is indicated that the CTRL circuit is programmed from the values ​​of the weights of the dimensioned encoder model, in the embodiment of Figures 13 to 17, this does not necessarily mean that the CTRL circuit receives the values ​​of these weights during the programming of the device 17, but that it can receive programming data obtained from these weight values, for example by means of a circuit of the device 17 (not shown in Figure 17) or an electronic system external to the device 17.

[0296] In the embodiment of Figures 13 to 17, each weight circuit, for example the resistor R of the corresponding weight circuit, implements a memory point (or memory element) of a programmable memory of the device 17, each memory element being configured to store a value that is not necessarily binary. The programming of this memory and of the CTRL control circuit from weight values ​​makes it possible to reconfigure the device so that it implements an encoder corresponding to these weight values. For example, the CTRL circuit is also programmed from the values ​​of the weights of the dimensioned model to generate the control signals and the sequencing between these control signals so as to implement the operation described above of the device 17.For example, the CTRL circuit is programmed with a file generated from the weight values ​​of the dimensioned model, this file indicating the control signals to be generated and their sequencing.

[0297] In the example above, the device 17 therefore allows, thanks to a step of programming its memory and its CTRL circuit from weight values ​​of a model sized encoder, the implementation of any sized recurrent encoder from the generic model in which K is less than or equal to Kmax and D is less than or equal to Dmax .

[0298] The devices 12 and 17 allow the implementation of different trained models of K-cell modulators Cellk. This can allow, for example, the rapid testing of a hardware implementation of a trained modulator model, without having to design a dedicated circuit. More generally, a programmable modulator topology of the type shown in Figure 12 or 17, with a given value of Kmax and a given value of Dmax can be programmed with trained models of modulators in which K is less than or equal to Kmax and / or D is less than or equal to Dmax. In other words, this programmable topology is like an FPGA (Field Programmable Gate Array), but is dedicated to being programmed from the trained modulator model based on a succession of Cellk cells.

[0299] Two exemplary embodiments of a programmable and reconfigurable device for implementing a sized encoder model have been described above, in which the signals used in the device are of the "common mode" type ("single ended" in English), that is to say that a signal is transmitted by a single conductive line, the signal comprising a common mode DC component and an AC component.

[0300] However, it is also possible to adapt the above embodiments to differential type signals, i.e. a signal is transmitted by two conductive lines (or paths) between which the signal is available.

[0301] Figures 18, 19, 20, 21 and 22 illustrate another embodiment of the reconfigurable device 17 where the weights are implemented by programmable resistors (or resistive components). More particularly, these figures illustrate the case where the implementation of the device 17 is of the differential type.

[0302] Compared to a common-mode implementation where the signals were sampled by the SH circuit in a positive and negative manner to manage the signs of the weights, in a differential-type implementation, the sign of a weight can advantageously be managed by inverting or not the two paths (components) of the differential signal received by the corresponding weight circuit. The sample-and-hold circuit then no longer needs to sample a positive and a negative version of the signal.

[0303] Figure 18 illustrates a differential type implementation of a circuit Rw of the device 17.

[0304] Compared to Figure 13, the circuit Rw receives a differential signal at its input In. The two signal paths are supplied to two multiplexers MUX1 and MUX2. When the weight programmed in the circuit Rw is negative, the multiplexer MUX1 supplies the first of the two signal paths at its output and the multiplexer MUX2 supplies the second of the two signal paths at its output. Conversely, when the weight programmed in the circuit Rw is positive, the multiplexer MUX1 supplies the second of the two signal paths at its output and the multiplexer MUX2 supplies the first of the two signal paths at its output. Although this is not illustrated in Figure 18, the multiplexers MUX1 and MUX2 receive the same binary control signal whose state is determined by the sign of the programmed weight. As an example, this control signal is supplied by the control circuit CTRL supplying, for example, a control signal to each of the Rw circuits. Each multiplexer MUX1 and MUX2 is coupled to the Out output of the Rw circuit by a programmable resistor R. When programming the device, the resistors R will each be programmed to a value equal to the value of a unit resistor RO divided by the value of the weight. Each resistor R provides one of the two output signal channels available on the Out output of the circuit.

[0305] Figure 19 illustrates a differential type implementation of a SUMk circuit of the device 17.

[0306] While in Figure 14 the SUMk circuit corresponds to a common mode resistive transimpedance amplifier (RTIA), in Figure 18 the SUMK circuit corresponds to a differential type resistive transimpedance amplifier.

[0307] With respect to Figure 14, the SUMk circuit comprises a differential operational amplifier AOP. A switch IT25 couples a first channel of the differential input In of the SUMk circuit to a first input, for example the inverting input (-), of the AOP amplifier. Symmetrically, a switch IT26 couples a second channel of the differential input In of the SUMk circuit to a second input, for example the non-inverting input (+), of the AOP amplifier. A first unit capacitor C0 is connected between a first output, for example non-inverting (+), of the AOP amplifier and its first input, a second unit capacitor C0 being connected between a second output, for example inverting (-), of the AOP amplifier and its second input.A series combination of a switch IT27 and a unit resistor R0 is connected in parallel to the first capacitor C0, a series combination of a switch IT28 and a unit resistor R0 being connected in parallel to the second capacitor C0. The two outputs of the AOP amplifier. constitute the two channels of the output signal available on the Out output of the SUMk circuit.

[0308] The SUMk circuit receives a control signal rdk, for example supplied by the CTRL circuit (figure 17). The switches IT25 and IT26 are closed when the rdk signal is active, open otherwise. The switches IT27 and IT28 are closed when the rdk signal is active, open otherwise.

[0309] Furthermore, although not shown in Figure 19, each SUMk circuit may further comprise a reset input controlling two reset switches connected in parallel with the CO capacitors. Each reset switch is closed, respectively open, when a reset signal received by this reset input is active, respectively inactive. In this case, this reset input receives a signal Rst-Cycle which has a pulse in the active state at the start of each cycle C[n], before any other signal is set to the active state during this cycle.

[0310] Figure 20 illustrates a differential type implementation of an SH circuit of the device 17. More particularly, in the example of Figures 18 to 22, the SH circuits are not all implemented in the same way, depending on whether they receive an output signal from a SUMk circuit (unquantized) or from a Quantk circuit (quantized).

[0311] Figure 20 illustrates more particularly an example of differential type implementation of an SH circuit receiving the output signal of a SUMk circuit, this SH circuit being referenced SHa in figure 20.

[0312] The SHa circuit includes a differential operational amplifier AOP. A switch IT29 and a resistor Rh in series with the switch IT29 couple a first channel of the differential input In of the SHa circuit to a first input, for example the inverting (-) input, of the AOP amplifier. Symmetrically, a switch IT30 and a resistor Rh in series with the switch IT30 couple a second channel of the differential input In of the circuit SHa to a second input, for example the non-inverting (+) input, of the AOP amplifier. A first capacitor Ch is connected between a first output, for example non-inverting (+) , of the AOP amplifier and its first input, a second capacitor Ch being connected between a second output, for example inverting (-) , of the AOP amplifier and its second input. A switch IT31 is connected in parallel with the first capacitor Ch, a switch IT32 being connected in parallel with the second capacitor Ch.A switch IT33 couples the first output of the AOP amplifier, for example the non-inverting output (+), to a first channel of the Out output of the SHa circuit, a switch IT35 further coupling the first Out output channel to a reference potential. A switch IT34 couples the second output of the AOP amplifier, for example the inverting output (-), to a second channel of the Out output of the SHa circuit, a switch IT36 further coupling the second Out output channel to the reference potential.

[0313] The SHa circuit is controlled by control signals received on inputs wr and rst of the SHa circuit. The switches IT29 and IT30 are closed, respectively open, when the signal received by the wr input is active, respectively inactive. The switches IT31, IT32, IT35 and IT36 are closed, respectively open, when the signal received by the rst input is active, respectively inactive. The switches IT33 and IT34 are closed, respectively open, when the signal received by the rst input is inactive, respectively active.

[0314] Figure 21 illustrates a differential type implementation of the Quantk circuit of device 17.

[0315] For example, for two-level quantization, each Quantk circuit includes a threshold comparator COMP . The two inputs of the comparator COMP receive the two channels of the input In of the circuit COMP. The output of the comparator COMP provides a binary signal Out. For example, the notion of binary signal designates a signal that can take two analog voltage values ​​corresponding to the two voltage values ​​that can be available at the output of a DAC circuit. These two analog voltage values ​​are, for example, defined by the high and low terminals and the analog signal to be quantized. The output Out is updated when a signal received by an input Cmpk of the Quantk circuit is active, and is then stored as long as this signal is inactive.

[0316] Figure 22 illustrates a differential type implementation of an SH circuit of the device 17. More particularly, in the example of Figures 18 to 22 where the SH circuits are not all implemented in the same way, Figure 22 illustrates an example of implementation of an SH circuit receiving the quantized output signal of a Quantk circuit, this SH circuit being referenced SHn in Figure 22.

[0317] The circuit comprises two inverters mounted in antiparallel to form a first memory, this first memory being coupled to the quantized input In by a switch IT37 and coupled to a first channel of the differential output Out of the circuit by a switch IT38. Symmetrically, the circuit comprises two other inverters mounted in antiparallel to form a second memory, this second memory being coupled to the quantized input In by the switch IT37 and coupled to a second channel of the differential output Out of the circuit by a series connection of an IT39 switch and an inverter. An IT40 switch, respectively IT41, couples the first output channel, respectively the second output channel, to the reference potential.

[0318] Switch IT37 is controlled by a signal corresponding to the signal received by the wr input of the SHn circuit, and is closed, respectively open, when this signal is active, respectively inactive. Switches IT38 and IT39 are controlled by a signal corresponding to the signal received by the rst input of the SHn circuit, and are open, respectively closed, when this signal is active, respectively inactive. Switches IT40 and IT41 are controlled by the signal received by the rst input of the SHn circuit, and are closed, respectively open, when this signal is active, respectively inactive.

[0319] The device 17 of Figure 17 can therefore be implemented differentially by replacing its circuits Rw, SUMk, Quantk and SH described in relation to the respective Figures 13, 14, 15 and 16 with the differential versions of these circuits described above in relation to Figures 18 to 22. In particular, in the example of Figure 17 where Dmax is equal to 2, each cell circuit Cellk comprises two SH (SHa) circuits connected to the output Out of the SUMk circuit of the cell, a first of the two circuits providing the output signal Ak0 of the cell, and the other of the two circuits providing the signal Akl of the cell. Furthermore, each circuit of Cellk comprises two other SH (SHn) circuits connected to the output Out of the Quantk circuit of the cell, a first of the two circuits providing the output signal BkO of the cell, and the other of the two circuits providing the signal Bkl of the cell.In the example of Figure 17, the input signal x is differential in nature.

[0320] The timing diagrams of the control signals supplied to the circuits of the device 17 in a differential implementation are similar to those described in relation to FIG. 17 for the common mode implementation. However, in this differential implementation, additional reset signals Rstk are provided, for example supplied by the circuit CTRL. Each circuit SHa of a cell Cellk of index k equal to i receives the signal Rsti (or Rstk with k equal to i). These signals Rstk are preferably set to the active state during the initialization phase Reset. Furthermore, at each intra-cycle of each cycle C[n], the signal Rsti corresponding to this intra-cycle has a pulse in the active state between the active state of the signal rdi and the active state of the signal wri. For example, taking Figure 17, the signal Rsti provides the SHa circuits of the cell Celll with an active state pulse between the active state of the signal rdl and the active state of the signal wrl.

[0321] It should be noted that, usually, the output voltage of a SHa circuit is given by -Vsumk.t / (Rh.Ch) with Vsumk the output voltage of the SUMk circuit providing the input signal of the SHa circuit, Rh and Ch the values ​​of the Rh and Ch components of the SHa circuit, and t the active state duration of the signal received by the wr input of the SHa circuit. By choosing a duration t equal to Ch.Rh, the output of the SHa circuit is equal to the Vsumk output with a polarity inversion. The polarity inversion introduced by the SHa circuit between its input and its output makes it possible to compensate for the polarity inversion introduced by the SUMk circuit.

[0322] Although not illustrated and described in detail herein, just as the resistive programmable weight device 17 having a common mode implementation can be modified to have a differential implementation, one skilled in the art will be able to adapt the description of the device 12 having a common mode type implementation to a differential type implementation.

[0323] In the programmable device architectures 12 and 17 described above, programming (or reconfiguring) the device with the weights of a sized encoder model is done by programming the values ​​of the programmable resistors R or capacitors C, and the CTRL circuit so that it provides the control signals for the summing, quantizing and intra-cycle transfer stages.

[0324] In other words, in the programmable device architectures 12 and 17 described above, the devices 12 and 17 each comprise a memory (the programmable capacitive or resistive components) programmed from the value of the weights of the sized encoder model, and a CTRL circuit programmed from the values ​​of the weights of the sized encoder model so as to implement the operation described above. For example, the programming of the CTRL circuit may correspond to a programming of a memory of the CTRL circuit with a file indicating the control signals to be generated and the sequencing between these control signals, this configuration file of the CTRL circuit being generated from the weight values ​​of the sized model, for example outside the device.

[0325] However, these architectures require having programmable value C or R components, which can be cumbersome.

[0326] As an alternative implementation, a programmable and reconfigurable device can be provided in which the CTRL circuit provides control signals so as to implement a time weighting, and no longer based on the programming, for each weight, of a corresponding capacitance value C or resistance R.

[0327] Indeed, by using, to implement the SUMk circuits, integrator circuits comprising capacitive transimpedance amplifiers (CTIA) in which a feedback capacitor is loaded, it is possible to implement a corresponding weight by controlling the integration time of a current on this capacitor or by controlling the quantity of charges transferred to this capacitor.

[0328] More particularly, this implementation of the weights in the time domain can correspond, for a given weight: either to a discrete implementation corresponding to Nint transfers of unit packets of charges, with Nint a number determined by the absolute value of the weight, and, preferably, an integer, the size of the packet of charges being, for example, the result of a product of a capacity and a signal (a voltage) considered, or to a continuous implementation corresponding to a transfer of charges during a duration T equal to Nint times a unit duration Tint, that is to say to an integration of duration T of a current determined by a voltage difference across an input resistance of the CTIA assembly, and Nint a number determined by the absolute value of the weight, and, preferably, an integer.

[0329] The two time-domain implementations introduced above are best applied to a dimensional encoder model in which the weights are quantized weights.

[0330] An advantage of implementing time-domain weightings using summing circuits based on capacitive transimpedance amplifiers having either an input resistor or an input sampling capacitance is that it is possible to pool the SUMk and Quantk circuits. For example, it is possible to have only one SUMk circuit, then referenced SUM, and one Quantk circuit then referenced Quant for K stages (or Cellk cells). Although this is not detailed below, it is also possible to keep one SUMk circuit and one Quantk circuit per Cellk cell and to cascade these cells in a similar way to what is illustrated in figures 12 and 17. It is also possible to plan to pool one SUMk circuit and one Quantk circuit for M Cellk cells, and to cascade F blocks of M Cellk cells, with F an integer greater than or equal to 2. In this case, each block of M Cellk cells includes a single SUMk circuit, referenced SUMf with f an integer index ranging from 1 to F and corresponding to the index f of the block of M cells among the F blocks of M cells, and a single Quantk circuit, then referenced Quantf.

[0331] Figure 23 illustrates an embodiment of a programmatically reconfigurable device 23 for implementing a sized encoder model. In this embodiment, the implementation of the device 23 is of the differential type.

[0332] In this embodiment, the device 23 is based on a single summing SUM circuit implemented by a capacitive transimpedance amplifier having its two inputs coupled to resistors RI and R2. The SUM circuit comprises a capacitor Cl having a first electrode connected to a first input, for example inverting (-), of an AOP amplifier and a second electrode coupled to a first output, for example non-inverting (+), of the amplifier, a switch ITlrst being connected in parallel with the capacitor Cl. Symmetrically, the SUM circuit comprises a capacitor C2 having a first input connected to a second input, for example non-inverting (+) , of the AOP amplifier and a second electrode coupled to a second output, for example inverting (-) , of the AOP amplifier, a switch IT2rst being connected in parallel with the capacitor 02. The capacitors Cl and C2 have the same value. The switches ITlrst and IT2rst are controlled by a control circuit CTRL of the device 23. The inputs of the AOP amplifier constitute, for example, the two channels of the differential input of the SUM circuit, the outputs of the AOP amplifier constituting, for example, the two channels of the differential output of the SUM circuit.

[0333] The device 23 further comprises a single quantization circuit Quant. The differential input of the Quant circuit receives the differential output of the SUM circuit. In this example where the quantization of the signals is done on two levels only, the output signal of the Quant circuit is a binary signal. As an example, the notion of binary signal designates a signal that can take two analog voltage values ​​corresponding to the two voltage values ​​that can be available at the output of a DAC circuit. These two analog voltage values ​​are, for example, defined by the high and low terminals and the analog signal to be quantized. The updating of the output of the Quant circuit is controlled by a signal Cmp provided by the circuit CTRL.

[0334] To store the output signals of the Cellk cells of an encoder model comprising up to Kmax Cellk cells and in which D can at most be equal to Dmax, the device 23 comprises Dmax. Kmax analog memories BC1 for storing the delayed or unquantized signals, with 1 an index ranging from 0 to Dmax.Kmax-1, and Dmax. Kmax digital memories DACm for storing the delayed or unquantized signals, with m an index ranging from 0 to Kmax. Dmax-1.

[0335] In this example where the implementation of the device 23 is of differential type, each memory BC1, respectively DACm, is configured to store the two components of a differential signal. For example, each memory BC1 comprises a memory circuit BC1_1 and a memory circuit BC1_2, configured to store the two respective components of the differential signal stored by this memory BC1.

[0336] Each memory BC1, respectively DACm, is selectively coupled to the inputs of the SUM circuit by a corresponding data path, each data path comprising at least one switch ITarl, respectively ITnrm. Each switch ITarl, respectively ITnrm, is controlled by the control circuit CTRL of the device 23. Each switch ITarl, respectively ITnrm, is closed to read the voltage stored in the corresponding memory BC1, respectively DACm, and open otherwise. The device 23 therefore comprises 2.Kmax.Dmax data paths between the memories BC1, DACm and the SUM circuit, each data path here comprising two wires.

[0337] In this example of differential type implementation, each data path coupling a memory BC1 to the SUM circuit comprises a first switch ITarl coupling a first channel of the output of the memory BC1, i.e. the output of the memory circuit BC1_1, to a node N2 coupled to the input of the SUM circuit and a second switch ITarl coupling a second channel of the output of the memory BC1, i.e. the output of the memory circuit BC1_2, to a node NI coupled to the input of the SUM circuit. In addition, each data path coupling a memory DACm to the SUM circuit comprises a first switch ITnrm coupling a first channel of the output of the memory DACm to the node NI and a second switch ITnrm coupling a second channel of the output of the memory DACm to the node N2.

[0338] Furthermore, the device 23 comprises a data path comprising two ITx switches. One of the two ITx switches is connected to the node NI, and the other of the two ITx switches is connected to the node N2. The two ITx switches receive, on their terminals which are not connected to the nodes NI and N2, the two respective components of the differential input signal x. In other words, this data path is configured to apply the input signal x between the nodes NI and N2.

[0339] More particularly, in the example of Figure 23, the input resistors RI and R2 of the capacitive transimpedance amplifier of the SUM circuit are shared for all data paths. Furthermore, to compensate for the sign inversion introduced by the capacitive transimpedance amplifier of the SUM circuit and to manage the polarity of the weights programmed in the device 23, the device 23 comprises a circuit SW controlled by a signal sign. The signal sign is provided by the circuit CTRL. The circuit SW is configured to couple, depending on the signal sign, either the nodes NI and N2 respectively to the first and second channels of the input of the SUM circuit (via the respective resistors RI and R2), or the nodes NI and N2 respectively to the second and first channels of the input of the SUM circuit (via the respective resistors R2 and RI). This circuit SW is, like the resistors RI and R2, shared for all data paths.The SW circuit and resistors RI and R2 couple each of the data paths to the inputs of the SUM circuit. The differential input of the SW circuit is connected to nodes NI and N2, and the differential output of the SW circuit is coupled, via resistors RI and R2, to the differential input of the SUM circuit, i.e., to the first and second inputs of the AOP circuit. In other words, the SW circuit is configured to selectively cross or not cross the two paths. of a differential data path, depending on the state of the signal it receives.

[0340] Each memory BC1 is selectively coupled to the output of the SUM circuit by at least one corresponding ITawl switch. The ITawl switch is controlled by the CTRL control circuit of the device 17. The ITawl switch is closed to write the output voltage of the SUM circuit into the corresponding memory BC1, and open otherwise.

[0341] In the example of Figure 23, each memory BC1 has its first input channel, i.e. the input of the memory circuit BC1_1, coupled to the first channel of the output of the SUM circuit by a first switch ITawl, its second input channel, i.e. the input of the memory circuit BC1_2, coupled to the second channel of the output of the SUM circuit by a second switch ITawl, its first output channel, i.e. the output of the memory circuit BC1_1, coupled to the first channel of the input of the SUM circuit, for example connected to the second electrode of the capacitor C1, by a third switch ITawl, and its second output channel, i.e. the output of the memory circuit BC1_2, coupled to the second channel of the input of the SUM circuit, for example connected to the second electrode of the capacitor C2, by a fourth switch ITawl. The first and second output channels of the SUM circuit provide the two components of the differential output signal of the SUM circuit.In other words, each memory BC1 has its differential input coupled to the two output channels of the SUM circuit by two respective switches ITawl, and has its differential output coupled to the respective capacitors Cl and C2 by two respective switches ITawl.

[0342] Each DACm memory is selectively coupled to the output of the Quant circuit by at least one corresponding ITnwm switch. The ITnwm switch is controlled by the CTRL control circuit of device 17. The switch ITnwm is closed to write the output voltage of the Quant circuit into the corresponding memory DACm, and open otherwise.

[0343] In the example of Figure 23 where the Quant circuit provides a binary signal, each DACm memory has its single input coupled to the single output of the Quant circuit by a single switch ITnwm. For example, the logic state stored in these memories has high and low levels defined by the voltage domain of the input signal, for example the terminals of the input signal.

[0344] For example, each memory circuit of each memory BC1 comprises a source-follower MOS transistor having its source connected to the output of the memory circuit and its gate connected to the input of the memory circuit, and a capacitor Ch connected between the gate and a reference potential to store a voltage present on the input of this memory circuit.

[0345] For example, each DACm memory comprises two inverters connected in antiparallel between two nodes. A first of the two nodes is connected to the input of the memory, the other of the two nodes is connected to the first channel of the output of the memory, and is coupled to the second channel of the output of the memory by an inverter.

[0346] In the device 23, at each intracycle corresponding to a cell Cellk of index k of the encoder model, the differential input signal x is applied to the differential input of the SUM circuit, consequently controlling the switches ITx, for a duration determined by the value of the weight Wkx of this cell Cellk of the model. More particularly, this duration is determined by the product of a unit time period Tu by a factor, for example Nint, the value of which is determined by the weight Wkx.

[0347] For example, in the device 23 based on a summation SUM circuit implemented by a differential capacitive transimpedance amplifier having its two inputs coupled to resistors RI and R2, the two resistors have the same value Rin, and the two integration capacitors Cl and C2 have the same value Cint. When a signal (or voltage) Vin (corresponding to a data item to which a weight W is to be applied) is available at the output of the circuit SW, or, in other words, is present between the terminals of the resistors which are not coupled to the AOP circuit, the signal (or voltage) Vout available between the outputs of the AOP circuit is defined by Vout = - (Vin . T ) / (Rin . Cint ), with T the time during which the voltage Vin is present between the resistors RI and R2. In a quantized weight matrix, each weight W is equal to Wq.Wu, with Wq an integer factor and Wu a common weight for all weights in the matrix, the weight Wu being, for example, a rational number.By choosing a unit integration time Tu equal to Wu. Rin. Cint, the weight W is applied to the data corresponding to the voltage Vin by implementing an integration of duration Wq.Tu. Thus, Vout = (Vin . Wq . Tu) / (Rin . Cint ) = - (Vin . Wq . Wu . Rin . Cint ) / (Rin . Cint ) = -Vin. Wq.Wu = -Vin.W, from which it follows that the voltage Vout is representative of the data corresponding to the voltage Vin to which the weight W has been applied. Note that the sign of the weight is managed here using the circuit SW. For example, if the weight W is positive, the input channels of the SUM circuit are crossed to compensate for the polarity inversion introduced by the SUM circuit, and, conversely, if the weight W is negative, the input channels of the SUM circuit are not crossed so that the polarity inversion introduced by the SUM circuit implements the negative polarity of the weight W.

[0348] The person skilled in the art will be able to adapt the above example to the case of a SUM circuit implemented by a single-ended capacitive transimpedance amplifier having its input coupled to a single resistor of value Rin.

[0349] In the device 23, at the beginning of a cycle C[n] the signals Akd[n] of the cells CellK of the encoder model have been stored in the memories BC1, and the signals Bkd of the cells CellK of the encoder model have been stored in the memories DACm. In the device 23, at each intracycle of a cycle C[n], that is to say at each update of the output signals of a cell Cellk of the encoder model, a single analog memory BC1 is updated by reading, sequentially, the other analog and digital memories of the device 23, each for a duration determined by the absolute value of the weight associated with the signal recorded in the read memory, the polarity of the weight determining the value of the signal sign when reading this memory.During this sequential reading of the other memories, the memory is updated by storing therein the output value of the SUM circuit and, at the end of this sequential reading, the corresponding digital memory is updated with the output value of the Quant circuit. More particularly, the duration during which each memory is read is determined by the product of the unit time period Tu by a factor whose value is determined by the weight applied to the signal stored in the memory read.

[0350] More specifically, for each index value k, Dmax memories BC1 among the Kmax . Dmax memories allow to memorize, at each cycle C[n] , the Dmax signals Akd[n] . At each cycle C[n] , for the intra-cycle of the cell Cellk, only the memory BC1 in which the signal Akd[n-1] of index d is memorized is the largest is updated with the signal Ak0 [n] , by sequentially reading all the other analog and digital memories. Thus, at the end of 1' intracycle associated with this index k, the Dmax memories BC1 associated with this index k include the signals Ak0 [n] and Ak0[nl] to Akd-l [nl], that is to say the Ak0 [n] and Akl [n] to Akd[n]. In addition, during the sequential reading of the other memories to calculate the signal Ak0 [n] before its storage in a corresponding memory BC1, the reading duration of each memory is determined by the weight applied to the signal stored in this memory.

[0351] In the case where Dmax is equal to 2, for each index value k, in the encoder model the signals Ak0 [n] and Akl [n] are identical at the start of a cycle C[n] and remain so until the update of these signals during the intracycle corresponding to this index k. It follows that, when updating the memory BC1 to store there the update of the signal Ak0 [n] of the cell Cellk (k ranging from 1 to K) of the model, for each cell Celli of index i>k, the reading of the memories comprising the corresponding signals AiO [n] and Ail [n] can be implemented by reading only the memory comprising the signal still not updated Ail [n], for a duration determined by a weighting or sum of the weights applying to the signals AiO [n] and Ail [n]. This is also true for the BkO[n] and Bkl[n] signals and the memories storing these signals.

[0352] For example, in the device 23, the intra-cycle operations associated with each of the K stages of the encoder are sequentially executed by updating the memories BC1 and DAC1 (from the sequential readings of the memories BCO, DACO, BC2, DAC2, and finally BC4 and DAC4), then BC3 and DAC3 (from the sequential readings of the memories BCO, DACO, BC1, DAC1, BC2, DAC2, and finally BC4 and DAC4), and finally BC5 and DAC5 (from the sequential readings of the memories BCO, DACO, BC1, DAC1, BC2, DAC2, BC3, DAC3, and finally BC4 and DAC4). For each intra-cycle, the updating of a analog memory is performed by sequentially reading the other memories during respectively a number of periods corresponding to the absolute value of the associated weight(s) as will be explained below. Preferably, the reading of each analog memory is done by crossing the outputs of the memory with respect to the inputs of the SUM circuit, in order to compensate for the polarity inversion introduced by the SUM circuit, and the management of the sign of the weight is performed by crossing or not the differential channels at the input of the CTIA with the control signal sign. For example, if the sign of the weight is positive, then the SW circuit does not cross the differential channels, and, conversely, if the sign is negative, the SW circuit operates a crossing of the differential channels.

[0353] As described in general above, in the particular case where Dmax is equal to 2, for example, from one cycle C[n] to the next, the BC1 memories associated with the signals Ak0 and Akl of a given stage k are reversed. Indeed, at the end of each cycle C[n], the data Ak0 and Akl are equivalent in the high-level model. In the proposed implementation, in cycle C[n], we will associate, for example, the BCO memory with the signal A10[n], and the BC1 memory with the signal Ail[n], and, in the following cycle C[n+1], we will associate the BC1 memory with the signal A10[n+1], and the BCO memory with the signal All[n+1]. Therefore, in cycle C[n+1], we will update the memory BC1 from the reading of the current state A10[n] of the previous cycle (stored on BCO) and BC1 therefore contains the current state A10[n+1] of cycle C[n+1], and the value A10[n] contained in BCO becomes the value All [n+1] of cycle [C[n+1].Therefore, for each cell Cellk (k ranging from 1 to K), only one of the two analog memories BC1 associated with this cell Cellk is updated, at each intra-cycle. For example, at each cycle C[n],. the weighting of the read memories will therefore correspond to the sum of the weightings of the signals Ak0 and Akl as long as the current states have not been updated (hence the sequencing proposed previously). In other words, at each cycle C[n], when updating the memories corresponding to the output signals of the cell Cellk (k ranging from 1 to K) of the model, the weights of the signals AiO and Ail of the stages i>k are pooled and these pooled weights apply respectively to the signals of the memories storing the current state of the previous cycle. Furthermore, for the intra-cycle update of the signals AiO and Ail, the current state and the previous state of the upstream stage are permanently available, which are read in this case with their respective weights.

[0354] For example, as previously described in general, in this example where Dmax is equal to 2, the quantization of the quantities Ak0 and Akl, making it possible to obtain the corresponding values ​​BkO and Bkl, is carried out at the end of the integrations achieving the desired weighting of each intra-cycle. The associated digital memories DACm will be updated at the end of this quantization (for example, we could use the same ping-pong system as for the analog memories, or a ping-pong-free approach if the comparator is a locked comparator making it possible to temporarily store a state, thus allowing the disconnection of the input memories and the updating of the latter from the value stored at the comparator level). In the case of ping-pong management of the memories, we will also ensure that the weightings of the signals BkO and Bkl are shared as indicated above as an example for the analog memories.

[0355] In the device 23, the CTRL circuit includes a memory. When programming the device 23, the memory of the CTRL circuit is programmed from the weights of the K weight vectors of the dimensioned encoder model, and the CTRL circuit is configured to control summations and quantifications in the device 23, so as to implement the operation described above. The programming of the memory, therefore of the CTRL circuit, may correspond to a programming of the memory with the values ​​of the weights of the dimensioned model, and the CTRL circuit then comprises, for example, a processing circuit configured to determine, from the values ​​of the weights programmed in the memory, the control signals that the CTRL circuit must generate and the sequencing between these control signals.Alternatively, this programming of the CTRL circuit may correspond to a programming of the memory of the CTRL circuit, therefore of the CTRL circuit, directly with a file indicating the control signals to be generated and the sequencing between these control signals, this configuration file of the CTRL circuit being generated outside the device 23 from the weight values ​​of the dimensioned model. In both cases above, the device 23 comprises a memory forming part of the CTRL circuit, and this memory is programmed from the values ​​of the weights of the dimensioned model. Because the CTRL circuit comprises this memory, the CTRL circuit is also programmed from the values ​​of the weights of the dimensioned model.

[0356] The device 23 therefore allows, thanks to a step of programming its memory from weight values ​​of a sized encoder model and, therefore, from its CTRL circuit which includes this memory, the implementation of any recurrent encoder sized from the generic model, in which K is less than or equal to Kmax and D is less than or equal to Dmax.

[0357] In device 23, the advantage of sharing a single pair of resistors RI, R2 and a single circuit SW for the whole device 23 makes it possible to reduce dispersions, to the detriment of the execution time of each cycle C[n] since the memories are read sequentially.

[0358] In the device 23, each cycle C[n] is divided into K intracycles, and each intracycle is divided into unit time periods Tu.

[0359] In an alternative implementation of the device 23, a pair of resistors RI, R2 and a SW circuit are provided in each data path coupling a differential output of a memory BC1, DACm to the differential input of the SUM circuit. A pair of resistors RI, R2 and a SW circuit are also provided in the path coupling the input signal x to the differential input of the SUM signal. Furthermore, the resistors RI, R2 and the SW circuit coupling the nodes NI and N2 to the SUM circuit are removed, the nodes NI and N2 then being directly connected to the two channels of the differential input of the SUM circuit. In other words, in each data path, a SW circuit is connected after the switches of the two channels of the data path and a pair of resistors RI, R2 is connected between the two channels of the differential output of the SW circuit and the nodes NI and N2, the latter being directly connected to the two channels of the differential input of the SUM circuit.In each data path, the SW circuit is controlled by a sign signal dedicated to this path.

[0360] In such a variant, when updating a memory BC1, the other memories and the input signal x can be read simultaneously.

[0361] In such a variant, the time required to implement a cycle C[n] can be reduced compared to the embodiment of figure 23, but the device 23 is then more cumbersome because it comprises a circuit SW and a pair of resistors RI, R2 per data path. It can furthermore result in manufacturing dispersions between the pairs of resistors RI, R2 of each path.

[0362] Figure 24 illustrates an example of control signals provided by the CTRL circuit of the device 23, after its memory has been programmed from the values ​​of the weights of a sized encoder model. In this example, K is equal to 3 and D is equal to 2 in the sized encoder model with which the CTRL circuit was programmed. In Figure 24, a device 23 is considered comprising a SW circuit and a pair of resistors RI, R2 per data path, and the readings are therefore done in parallel.

[0363] In Figure 24, the signals are active at high level, and a switch is conducting when the control signal it receives is active. In Figure 24, each signal applied to a switch is arranged to the right of the reference of this switch. Furthermore, in Figure 24, the active state durations of the signals are not adapted to the values ​​of the weights programmed in the CTRL circuit, and the signals of the SW circuits are not represented either.

[0364] In Figure 24, dotted lines delimit a cycle C[n].

[0365] In Figure 24, the control signal for the ITx switches is not shown, but these switches are controlled jointly with the ITarl and ITnrm switches, depending on the weight values ​​associated with the x input.

[0366] In Figure 24, the signals are illustrated in the case where the memories are used in ping-pong, in the manner described previously, by pooling the weights for the stages of index i greater than or equal to k when updating the memories corresponding to the output signals of the cell Cellk of index k.

[0367] 23 and 24, examples of embodiments and alternative embodiments of differential type implementations of a device 23 comprising a single SUM circuit implemented by a capacitive transimpedance amplifier having its two inputs coupled to resistors RI and R2, these two resistors being either shared for all the data paths, or provided in each data path. In the devices 23 described, the weights are implemented by controlling the reading time durations of the memories of the device 23.

[0368] As previously indicated, an implementation of the weights in the time domain can also be provided with one or more SUM circuits each implemented by a capacitive transimpedance amplifier having its input coupled to one or more sampling capacitors. In this case, the weights are implemented by controlling, via capacitive sampling circuits, a number of unit packets of charges transferred from memories of the device to the SUM circuit. In practice, although we speak of unit packets of charges, this unit packet depends on the signal (voltage) that we want to weight, and is therefore specific to each signal value.

[0369] Figure 25 illustrates a programmatically reconfigurable device 25 for implementing a sized encoder model. In this embodiment, the implementation of the device 25 is of the common mode type. In this embodiment, the device 25 is based on a single SUM summing circuit implemented by a capacitive transimpedance amplifier, its input coupled to a sampling circuit shared between all the data paths of the device.

[0370] Device 25 is similar to device 23 of Figure 23, and only the differences between these two devices are detailed here.

[0371] In particular, with respect to the device 23 corresponding to a differential type implementation, in the device 25 corresponding to a common mode type implementation: - each BC1 memory includes only one input channel and one output channel and therefore only includes one BC1_1 memory circuit, - each data path has only one channel, so there is no NI node; - each DACm memory comprises only one input channel and one output channel, and therefore does not comprise the inverter coupling the two inverters connected in antiparallel to a second output channel of the DACm memory; - the AOP amplifier of the SUM circuit comprises only one output (or output channel), and one input channel (or input channel) corresponding, in this example, to the inverting input (-) of the AOP circuit, the other input, the non-inverting input (+) in this example, being connected to the reference potential. The SUM circuit is therefore devoid of the switch IT2rst and the capacitor C2; and - the Quant circuit only includes one input channel and one output channel.

[0372] Furthermore, in the device 25, the circuit SW and the pair of resistors RI, R2 are replaced by a capacitive sampling circuit Ech. The input In of the circuit Ech is connected to the node N2, the output Out of the circuit Ech being connected to the input of the circuit SUM, that is to say here to one of the inputs of the amplifier AOP, for example to the inverting input (-) of the circuit AOP.

[0373] This Ech circuit is configured to sample the signal it receives differently depending on the polarity, i.e. the sign, of the weight to be applied to this signal.

[0374] For example, in the device 24 based on a summation circuit SUM implemented by a single-ended capacitive transimpedance amplifier having its input coupled to a capacitive sampling circuit Ech comprising a sampling capacitor Cs, Cin is called the value of the capacitor Cs and Cint is the value of the integration capacitor Cl. When a signal (or voltage) Vin (corresponding to a data item to which a weight W is to be applied) is sampled on the capacitor Cs and the circuit Ech is controlled to provide this sampled voltage on the input of the circuit AOP with an inversion of the sign of the voltage, the signal (or voltage) Vout available on the output of the circuit AOP is defined by Vout = (Vin . Cin) / Cint . In a matrix of quantized weights, each weight W is equal to Wq.Wu, with Wq a factor and Wu a common weight identical for all the weights of the matrix.By choosing Cin / Cint equal to Wu, and repeating Wq times the two successive operations of sampling the voltage Vin then supplying the sampled voltage to the AOP circuit with a sign inversion, that is to say by carrying out Wq transfers of unit charge packets (without resetting the integration capacity of the AOP circuit), then Vout = Wq .Vin . Cin / Cint = Vin. Wq.Wu = Vin.W, from which it follows that the voltage Vout is representative of the data corresponding to the voltage Vin to which the weight W has been applied. Note that the sign of the weight is managed here thanks to the Ech circuit. For example, if the weight W is positive, a sign inversion is carried out between the sampled voltage and the voltage supplied to the AOP circuit to compensate for the polarity inversion introduced by the circuit. AOP . Conversely, if the weight W is negative, no sign inversion is performed between the sampled voltage and the voltage supplied to the AOP circuit, so the polarity inversion introduced by the AOP circuit implements the negative polarity of the weight.

[0375] The person skilled in the art will be able to adapt the above example to the case of a SUM circuit implemented by a differential capacitive transimpedance amplifier.

[0376] Figure 26 illustrates an example of implementation of a sampling circuit Ech of the device 25 (on the left in figure 26) and timing diagrams of the control signals of the switches of the circuit Ech depending on whether the weight to be applied to the signal sampled by the circuit Ech is of a first polarity, for example positive, (in the middle in figure 26), or of a second polarity, for example negative, (on the right in figure 26).

[0377] The Ech circuit includes a capacitor Os. The capacitor Os is connected between two nodes 26000 and 26002. A switch IT44 connects node 26000 to the input In of the Ech circuit, and a switch IT45 connects node 26002 to the output Out of the Ech circuit. A switch IT42, respectively IT43, connects node 26000, respectively 26002, to the reference potential, and a switch IT46 connects node 26000 to the output Out of the Ech circuit.

[0378] The Ech circuit receives wrl, wr2 and rdl and rd2 signals for controlling the switches.

[0379] Switch IT42 is controlled by the rdl signal and is closed when the rdl signal is active, open otherwise. Switch IT45 is controlled by the rdl signal, preferably by a delayed rdld version of the rdl signal, and is closed when the rdl (or rdld) signal is active, open otherwise. Switch IT46 is controlled by the rd2 signal and is closed when the rd2 signal is active, open otherwise. Switch IT43 is controlled by the wrl signal and is closed when the wrl signal is active, open otherwise. Switch IT44 is controlled by the wr2 signal and is closed when the wr2 signal is active, open otherwise.

[0380] In the timing diagrams, the control signals wr2, wrl, rdld, rdl and rd2 are active at high level.

[0381] The timing diagrams in the center of Figure 26 illustrate a control of the Ech circuit when the weight is of a first polarity, for example positive. A voltage is sampled in the capacitor Cs during a step of writing to the capacitor Cs comprising setting the signal wrl to the active state and setting the signal wr2 to the active state, the signal wr2 being, preferably, switched to the active state after the switching to the active state of the signal wrl. This writing step is delimited by dotted lines in the timing diagrams. Then, to transfer charges from the capacitor Cs to the SUM circuit during a step of reading the capacitor Cs (delimited by dotted lines in the timing diagrams), the signal rdl is switched to the active state, and the signal rdld switches to the active state with a delay relative to the switching to the active state of the signal rdl.

[0382] The timing diagrams on the right of Figure 26 illustrate a control of the Ech circuit when the weight is of a second polarity, for example negative. A voltage is sampled in the capacitor Cs during a writing step on the capacitor Cs comprising the setting to the active state of the signal wrl and the setting to the active state of the signal wr2, the signal wr2 being switched to the active state, preferably, after the switching to the active state of the signal wrl. This writing step is delimited by dotted lines in the timing diagrams. Then, to transfer charges from the capacitor Cs to the SUM circuit during a reading step Ill of the capacity Cs (delimited by dotted lines in the timing diagrams), the signal wrl is switched to the active state, and the signal rd2 switches to the active state, preferably with a delay compared to the switching to the active state of the signal wrl.

[0383] In the device 25 of figure 25, the updating of a memory is done by reading the other memories sequentially, each reading of a memory comprising Nint succession of a write in the circuit Ech and a read of the circuit Ech, that is to say Nint successions of a write on the capacitor Cs and a read of this capacitor Cs. The number Nint of reading / writing is determined by the absolute value of the weight to be applied to the signal stored in the memory which is read. The sequences of reading / writing of the memories can be done in ping-pong, in the same way as that described in relation to the device of figure 23.

[0384] In the device 23 described above, the entire circuit SW and the pair of resistors RI, R2 can be shared for all the data paths, resulting in a sequential reading of the memories, or can be provided in each data path, resulting in a parallel reading of the memories can be implemented.

[0385] Similarly, the device 25 of figure 25 where the Ech circuit is shared for all the data paths, can be modified so that each data path includes its own Ech circuit, from which it follows that a parallel reading of the memories can be implemented.

[0386] An example of such a device 25 is illustrated in Figure 27. In this device, each circuit Ech has its output connected to node N2 which is directly connected to the input of the SUM circuit.

[0387] In the device 25 of Figure 27, each circuit Ech receives its own signals wrl, wr2, rdl, rd2, and, for example, rdld.

[0388] Examples of embodiments and variant embodiments of the device 25 have been described above in the case where the implementation of the device 25 is of the common mode type. These devices 25 can be adapted to a differential type implementation.

[0389] Figure 28 shows a programmatically reconfigurable device 28 for implementing a sized encoder model. In this embodiment, the implementation of the device 28 is of the differential type. Furthermore, in this embodiment, the device 28 is based on a single summing SUM circuit implemented by a capacitive transimpedance amplifier having its two inputs coupled to identical capacitive sampling circuits Echl and Ech2.

[0390] The device 28 of Figure 28 includes many elements in common with the device 23 of Figure 23, and only the differences between these two devices are detailed here.

[0391] In particular, compared to device 23, in device 28, the respective resistors RI and R2 are replaced by respective circuits Echl and Ech2.

[0392] Figure 29 illustrates an example of implementation of the Echl circuit, the Ech2 circuit being identical to the Echl circuit.

[0393] The Echl circuit includes a capacitor Cs . The capacitor Cs is connected between two nodes 29000 and 29002. A switch IT47 connects the node 29000 to the input In of the Echl circuit, and a switch IT48 connects the node 29002 to the output Out of the Echl circuit. A switch IT49, respectively IT50, connects node 29000, respectively 29002, to the reference potential.

[0394] The Echl circuit receives wr and rd control signals from the switches.

[0395] Switch IT50 is controlled by the wr signal and is closed when the wr signal is active, open otherwise. Switch IT47 is controlled by the wr signal, preferably by a delayed version of the wr signal, and is closed when this signal is active, open otherwise. Switch IT49 is controlled by the rd signal and is closed when the rd signal is active, open otherwise. Switch IT48 is controlled by the rd signal, preferably by a delayed version of the rd signal, and is closed when this signal is active, open otherwise.

[0396] The Echl and Ech2 circuits each introduce a polarity inversion, which compensates for the polarity inversion introduced by the SUM circuit. The SW circuit is then controlled by the sign signal, the state of which depends solely on the polarity of the weight in question.

[0397] As an alternative embodiment not shown, the circuits Echl and Ech2 are each implemented in the same way as the previously described circuit Ech. In this case, the sign of the weight and the compensation for the polarity inversion introduced by the SUM circuit can be managed directly in the circuits Echl and Ech2, by controlling them in the manner described in relation to the timing diagram in the center of Figure 26 or in the manner described in relation to the timing diagram on the right of Figure 26. In this case, the SW circuit can be omitted.

[0398] In device 28, the circuits Echl and Ech2, and, when provided, the circuit SW, are shared for all data paths. As a result, the reading of the memories will be done sequentially.

[0399] However, although this is not illustrated by a figure, this device 28 can be adapted to the case where the reading of the memories can be carried out in parallel. For this, a set of an Echl circuit, an Ech2 circuit and, when the polarity inversions are not managed by these Echl and Ech2 circuits, an SW circuit, is provided in each data path.

[0400] In this case, in each data path, the Echl and Ech2 circuits will receive control signals dedicated to this data path.

[0401] In devices 25 and 28, the CTRL circuit comprises a memory. When programming the device, the memory of the CTRL circuit is programmed from the weights of the K weight vectors of the sized encoder model, and the CTRL circuit is configured to control summations and quantizations in the device, so as to implement the operation described above. The programming of the memory, therefore of the CTRL circuit, may correspond to a programming of the memory with the values ​​of the weights of the sized model, and the CTRL circuit then comprises, for example, a processing circuit configured to determine, from the values ​​of the weights programmed in the memory, the control signals that the CTRL circuit must generate and the sequencing between these control signals.Alternatively, this programming of the CTRL circuit can correspond to a programming of the memory of the CTRL circuit, therefore of the CTRL circuit, directly with a file indicating the control signals to be generated and the sequencing between these control signals, this configuration file of the CTRL circuit being, for example, generated outside the device from the weight values ​​of the dimensioned model In the two cases above, the device 25 or 28 comprises a memory forming part of the CTRL circuit, and this memory. is programmed from the weight values ​​of the dimensioned model. Because the CTRL circuit includes this memory, the CTRL circuit is also programmed from the weight values ​​of the dimensioned model.

[0402] Each of the devices 25 and 28 therefore allows, thanks to a step of programming its memory from weight values ​​of a sized encoder model and, therefore, its CTRL circuit which includes this memory, the implementation of any recurrent encoder sized from the generic model, in which K is less than or equal to Kmax and D is less than or equal to Dmax.

[0403] An example of sizing a generic sigma-delta converter model based on targeted functional and / or hardware characteristics has been described above, when this sizing is implemented by supervised deep learning. The weights of the model obtained after this sizing step by supervised deep learning are then used to program the reconfigurable electronic device, and more particularly a memory and a control circuit of this reconfigurable device, for example for validation purposes on a hardware platform of the sizing. However, although this is not always possible in practice, in particular when D and / or K increase, sizing the generic model "by hand", i.e. by successions of tests, is also possible.The model weights obtained after this "by hand" dimensioning step can also be used to program the reconfigurable electronic device.

[0404] Furthermore, although the exemplary embodiments and variants of reconfigurable devices have been described for Kmax equal to 3 and Dmax equal to 2, the person skilled in the art will be able to design, from the present description, programmatically reconfigurable devices in which Kmax and Dmax are different from the respective values ​​3 and 2.

[0405] Furthermore, although timing diagrams of control signals have been described in relation to figures 12, 17 and 24 in the case of reconfigurable devices where Kmax equals 3 and Dmax equals 2, programmed with a sized encoder model in which K equals Kmax and D equals Dmax, as already indicated, these devices can also be programmed with sized encoder models in which D has any integer value between 0 (inclusive) and Dmax (inclusive) and K has any value between 1 (inclusive) and Kmax (inclusive). In particular, in the case where a reconfigurable device is programmed with a sized encoder model in which K is strictly less than Kmax and / or D is strictly less than Dmax, the control signals associated with the weights that are not used are kept in the inactive state, in the same way as the control signals associated with unused weights are kept in the inactive state.Indeed, in a weight matrix of dimensions determined by Kmax and Dmax, the unused weights correspond to nuisance weights. In other words, it is sufficient not to use (or activate) the data paths which are not used in the dimensioned encoder model.

[0406] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0407] In particular, in architectures with a single resistor or pair of resistors or with a single capacitor or pair of capacitors coupled at the input of the AOP circuit, for example as is the case in figures 23 and 25, the memories are addressed sequentially. The addressing of the different signals at the input of the SUM circuit is then carried out according to a given order. This addressing order can be determined in several ways: - Either by addressing the feedback signals first (negative weights); - Either by carrying out a first rotation on all the signals with non-zero weightings during a single unit period (or a single charge transfer cycle), then by repeating this sequence until the weightings associated with the different addressed inputs are reached (this technique however has the limitation of increasing the number of commutations); Either by learning: to simplify the exploration in this case, we could for example first carry out learning corresponding to a parallel addressing of the different inputs (model learned by default like this), then explore with the learned weights the addressing sequence allowing to avoid saturations. We can also learn the addressing sequences and the weights at the same time (but the size of the search space increases significantly in this case).

[0408] Furthermore, to improve the bandwidth of the encoders proposed in Figures 23, 25, 27 and 28, the following solutions can be considered: - Several encoders can be connected in parallel, each encoder being synchronized to a sampling period of the input signal shifted by a time less than this period compared to the other encoders (method of "time interleaving"). This makes it possible to observe a signal with a frequency higher than the sampling frequency of a single encoder, thus relaxing the bandwidth constraints of the encoders. The reconstruction is then carried out from the pooling of the BOk and / or Blk data from the different encoders; - In order to carry out only one charge transfer or one integration period, the input capacitance or resistance associated with a particular weight is sized from a local bank of unit elements allowing the desired weight to be formed (grouping of capacitances to transfer a larger quantity of charges, or paralleling of resistors to integrate a higher current). The size of this bank will depend on the level of quantification of the weights. Generally speaking, providing a plurality of values ​​for the input capacitances or resistances of the adders in Figures 23, 25, 27 or 28 makes it possible to reduce the duration of a cycle. For example, in the case of Figure 23, the integration duration T associated with each input is expressed according to the relation T / (Rin.Cint), with T = Wq.Tu = Nint.Tu with Nint = Wq and Wq the quantized weight applied to the input.Nint then represents the number of unit durations Tu during which the input must be integrated so that the corresponding weight W = Wq.Wu is applied to it. To divide this number Nint by X, one can either divide the input resistance (or the integration capacitance) by X, and the final result will be preserved because (Nint / X).Tu / ((Rin / X).Cint) is equal to Nint.Tu / (Rin.Cint). The person skilled in the art will be able to adapt this example corresponding to the case of an AOP circuit having a single input resistance (in common mode - "single ended") or a single pair of input resistances (in differential mode) to the case of an AOP circuit having a single input capacitance (in common mode - "single ended") or a single pair of input capacitances (in differential mode);. - Multi-bit quantization of the BOk and Blk signals, each digital value being associated with a voltage particular analog with, for example, a uniform distribution of these voltages between the terminals of the signal to be converted, makes it possible to reduce the total number of cycles; - Increased quantization of weights (weights take on an increasingly limited number of possible values) will also reduce the overall conversion time, by reducing the number of charge transfers or the number of integration periods. It is important to note here that the values ​​of resistances, capacitances or unit periods will depend on the desired quantization (encoder design parameter); - Compared to the case of figures 23, 25, 27 and 28 where the Cellk cells are shared on a single assembly, it can be planned to cascade structures where each cell is implemented with a structure of the same type, but comprising only 2. Dmax memories for the Akd and Bkd signals of the Cellk cell considered. By carrying out learning without intra-cycles, we would then approach a pipelined structure with increased bandwidth.

[0409] Furthermore, in the devices described, there are in practice dispersions on the values ​​of the capacitive and resistive passive components, on the input offset (or common mode offset) of the amplifiers, on the gain value of the amplifiers, or on the value of the unit period Tu of integration. It may be planned to compensate for all or part of these dispersions. Taking the example of a CTIA type summing circuit with input resistance, the expression linking the output Vout of the summing circuit to the input voltage Vin over an integration time of Nint periods Tu (i.e. Nint. Tu), is the following in an ideal case without dispersion: Vout = - (Nint . Tu / (Rin . Cint ) ) . Vin . Considering a dispersion 5Tu over the duration of the unit period Tu, a dispersion 5RC on the product Rin. Cint, a common mode voltage offset Voff, and a finite gain A of the amplifier, this relationship becomes: Vout = -Nint . A. ( Tu+5Tu) . ( Vin+Vof f ) / (A. (Rin . Cint+5RC ) + ( Tu + 5Tu) ) . Since the absolute value Wabs of a weight W applied to this input Vin is equal to Nint. Tu / (Rin.Cint) , this expression therefore deviates: Wabs = Nint. A. (Tu+ 5Tu) / (A. (Rin. Cint+ 5RC) + (Tu +5Tu)) Now, after quantization, each weight W of a quantized weight matrix can be written Wq.Wu, with Wq an integer and Wu a weight common to all the weights of the matrix being, preferably, a rational number. By choosing Wu = Tu / (Rin . Oint ) , the above expression can therefore be written: Wabs = Wq.A. (Wu+51) / (A. (1 + 52) + (Wu+51) ) with 51=5Tu / (Rin.Cint) and 52=5RC / (Rin.Cint) . The output voltage Vout, which is equal to -Wabs. (Vin+Voff ) , therefore no longer corresponds to a direct scalar multiplication, as represented in the model figure 5, where Ak0 [n] is equal to X[n] .Wk. We now have an expression of type Ak0 [n] = (X [n] +of f ) xWabs, with Wabs described previously. This expression including non-idealities can be taken into account in the model with additional dedicated layers allowing these non-idealities to be represented.Thus, if we have a characterization of the non-idealities A, Voff, 5RC and 5Tu, we can perform training of the encoder and decoder to be robust to the effects of these non-idealities. If these non-idealities are learned parameters of the model, we can also determine by training the implementation specifications for these elements. In such a case, we can for example learn the different weights and the minimum gain value of the amplifier necessary to achieve the desired performance.

[0410] It is further possible to provide calibration and time compensation. For example, in the device 27 of Figure 27 with multiple input capacitors (one Ech circuit per data path) or an equivalent resistive version, the resistive and capacitive components may have dispersions that can be determined, for example by looking at the deviation of the integration of a reference signal during a defined number of integration cycles or periods. In order to correct these dispersions during operation, the number Nint of unit integration periods or the number of integration cycles specific respectively to each resistor or to each addressed capacitor can be adjusted according to the previously measured dispersion so as to compensate for this dispersion.When the resistive and capacitive components are programmable, this approach can be used by taking advantage of the fact that these resistive and capacitive elements are programmable components. For example, in the case of a programmable resistor, the value of the resistance is programmed to the expected value (i.e. according to the desired weight). The value actually obtained after programming is then equal to R+5R, with 5R being the value of the dispersion. In the ideal case, a voltage is then stored after integration at the level of the memories which allows, after rereading, to obtain the voltage: Vout=-. Vin.Nint.Tu / (Rin.Cint) , with Nint=l since it is the value programmed in the resistor Rin which modulates the weight, and Tu common to all the weights. In the dispersed case, this voltage becomes (still with Nint=l): Vout=-Vin . Tu / ( (Rin+δR) .Cint) , with 5R the dispersion on the value programmed in Rin. To obtain the corrected weight, we can then introduce an integration time which we will modulate as follows: Vout=- Vin. (Tu+Ncor . Tcor) / ( (Rin+δR) .Cint) , where Tcor is a period sub-multiple of Tu and Ncor a parameter allowing to adjust the correction of the weight according to the dispersion of the addressed component, such that Vin. (Tu+Ncor . Tcor) / ( (Rin+δR) .Cint) = Vin . Tu / (Rin . Cint ) . In the case where Nint is not equal to 1, that is to say a case where the implementation of a weight W is done both by programming a resistive component to a value determined by the value of this weight W and by carrying out Nint integration periods with Nint also determined by the value of this weight W, the formula above becomes: Wine. (Nint . Tu+Ncor . Tcor ) / ( (Rin+δR) .Cint) = Vin. Nint. Tu / (Rin. Cint) .

[0411] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

CLAIMS 1. Electronic device (12, 17, 23, 25, 28) reconfigurable by programming to implement an encoder of a sigma delta type converter operating at an oversampling rate N, with N an integer greater than or equal to 1, and implementing N cycles C[n] at each conversion, with n an integer index ranging from 1 to N, the encoder being based on a generic model comprising a succession of K identical generic cells Cellk (Celll, Cell2, Cell3), with K an integer parameter and greater than or equal to 1 and less than or equal to Kmax, and k an integer index ranging from 1 to K, each cell Cellk of the generic model corresponding to a recurrent neural network which, at each cycle C[n], is configured to calculate a product of an input vector X[n] by a weight vector Wk of the cell Cellk and to provide an output vector Qk[n] comprising D pairs of outputs Akd[n] and Bkd[n] , with D integer greater than or equal to 1 and less than or equal to Dmax,d an integer index ranging from 0 to Dl, Akd[n] the result of the product calculated by the cell Cellk delayed by d cycles, Bkd[n] a quantification of the result of the product calculated by the cell Cellk delayed by d cycles, the generic model being further configured so that the vector X[n] is the same for all the cells Cellk at the start of each cycle C[n] and is equal to the concatenation of the K vectors Qk[n] and a sample x[n], for the cycle C[n], of a signal x to be converted, and to calculate, at each cycle C[n], the K vectors Qk[n] sequentially and in order of increasing index k, the device comprising: a programmable memory configured to be programmed from the values ​​of the weights of the K vectors of weight Wk, and a programmable control circuit (CTRL) configured to, be programmed from the values ​​of the weights of the K weight vectors Wk to control summations (SUMI, SUM2, SUM3, SUM) and quantifications (Quanti, Quant2, QuantS, Quant) in the reconfigurable device so as to implement, at each cycle C[n], the calculations of the vectors Qk[n] of the encoder.

2. Device according to claim 1, wherein: the device comprises Kmax cell circuits (Celll, Cell2, CellS), each cell circuit corresponds to a cell Cellk of the generic model; each cell circuit comprises 1+2. Dmax . Kmax weight circuits; each weight circuit corresponds to a weight of the generic model; each weight circuit comprises at least one programmable value element of resistive (R) or capacitive (C) type; and each weight circuit corresponds to a memory point of the programmable memory of the device.

3. Device according to claim 2, wherein: each cell circuit comprises a summing circuit (SUMI, SUM2, SUM3), each weight circuit of the cell circuit having its output coupled to an input of the summing circuit of the cell circuit; each cell circuit comprises a quantization circuit (Quanti, Quant2, Quant3) having an input connected to an output of the summing circuit of the cell circuit; and in each cell circuit, an input of one of the weight circuits is configured to receive a signal determined by the signal x to be converted and inputs of the other weight circuits are coupled to outputs of the summing circuits and quantization circuits of the device.

4. Device according to claim 3, wherein: the at least one programmable element of each weight circuit is of capacitive type (C), each weight circuit comprises switches (IT1, IT2, IT3, IT4, IT5, IT6, IT7) configured to implement a sampling of a voltage on the at least one programmable element of the weight circuit; the output of each summing circuit is connected to Dmax weight circuits in each cell circuit, and an output of each quantization circuit is connected to Dmax weight circuits in each cell circuit.

5. Device according to claim 3, wherein: the at least one programmable value element of each weight circuit is of resistive type (R); each cell circuit comprises Dmax storage circuits (SH) each having an input connected to the output of the summing circuit of the cell circuit and an output connected to an input of one of said other weight circuits of each cell circuit; and each cell circuit comprises Dmax other storage circuits (SH) each having an input connected to the output of the quantization circuit of the cell circuit and an output connected to an input of one of said other weight circuits of each cell circuit.

6. Device according to claim 1, in which the control circuit (CTRL) comprises the programmable memory.

7. Device according to claim 1 or 6, wherein the device comprises: a summing circuit (SUM); a quantization circuit (Quant) connected to an output of the summing circuit; Dmax.Kmax first memories (BCO) each coupled to an output of the summing circuit; Dmax.Kmax second memories (DACO, DAC5) each coupled to an output of the quantization circuit; 1+2. Dmax . Kmax data paths, one of the data paths being configured to receive the signal x to be converted and being coupled to an input of the summing circuit, the other 2. Dmax. Kmax data paths comprising Dmax.Kmax data paths coupling the first Dmax.Kmax memories to the input of the summing circuit and Dmax.Kmax data paths coupling the first Dmax.Kmax memories to the input of the summing circuit.

8. Device according to claim 7, wherein: the summing circuit comprises a capacitive transimpedance amplifier (AOP); and the device comprises at least one resistive element (RI, R2) coupled to an input of the summing circuit (SUM).

9. Device according to claim 8, wherein said at least one resistive element (RI, R2) is shared for all the data paths and couples each data path to the input of the summing circuit.

10. The device of claim 8, wherein said at least one resistive element comprises a resistive element in each data path.

11. Device according to claim 7, wherein: the summing circuit comprises a capacitive transimpedance amplifier (AOP); and the device comprises at least one capacitive sampling circuit (Ech, Echl, Ech2) coupled to an input of the summing circuit (SUM).

12. Device according to claim 11, in which the at least one capacitive sampling circuit (Ech, Echl, Ech2) is shared for all the data paths and couples each data path to the input of the summing circuit.

13. Device according to claim 9 or 11, in which the control circuit (CTRL) is configured to control switches of the device, the control circuit and said switches being adapted, at each update of a first memory or a second memory, to implement sequential readings of the other first and second memories.

14. Device according to claim 8, in which the at least one capacitive sampling circuit (Ech) comprises a sampling circuit in each data path.

15. Device according to claim 10 or 14, wherein the control circuit is configured to control switches of the device, the control circuit and said switches being adapted, at each update of a first memory or a second memory, to implement a parallel reading of the other first and second memories.

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