Self-calibration circuit, power management chip, and display apparatus

Abstract

A self-calibration circuit, a power management chip, and a display apparatus. The self-calibration circuit is configured to adjust a driving voltage generated by a voltage generation circuit in a power management chip; the self-calibration circuit comprises a sampling sub-circuit (1), a comparison sub-circuit (2), and a compensation sub-circuit (3); the sampling sub-circuit (1) is configured to collect a driving voltage and generate a sampling voltage; on the basis of a time node of a display frame in which a display panel is located, the comparison sub-circuit (2) is configured to compare the sampling voltage with a reference voltage and output a comparison voltage; the compensation sub-circuit (3) is configured to adjust the current driving voltage on the basis of the comparison voltage.

Description

Self-calibration circuit, power management chip, and display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a self-calibration circuit, a power management chip, and a display device. Background Technology

[0002] Existing TV / MNT / NB display products all suffer from a howling (noise) problem. When the display panel switches between the display and blanking phases, the voltage across the capacitor plates in the circuit changes. When subjected to an AC signal of a certain frequency and amplitude, the dielectric material constituting the capacitor's dielectric layer—BaTiO3 (barium titanate), which has a piezoelectric effect—will experience elastic strain. When the elastic strain reaches a certain intensity, vibration will occur. The capacitor is soldered onto the PCB (printed circuit board), and the capacitor's vibration causes the PCB to resonate. When the vibration frequency falls within the range that the human ear can perceive (20Hz~20KHz), and the sound is loud enough, it will be distinguishable by the human ear, resulting in PCB capacitor howling or current noise. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a self-calibration circuit, a power management chip, and a display device.

[0004] This disclosure provides a self-calibration circuit configured to adjust the drive voltage generated by the voltage generation circuit in a power management chip; the self-calibration circuit includes a sampling sub-circuit, a comparison sub-circuit, and a compensation sub-circuit.

[0005] The sampling sub-circuit is configured to acquire the driving voltage and generate a sampling voltage;

[0006] Based on the time node of the display frame in which the display panel is located, the comparison sub-circuit is configured to compare the sampled voltage and the reference voltage and output a comparison voltage; the compensation sub-circuit is configured to adjust the current driving voltage based on the comparison voltage.

[0007] The comparator sub-circuit includes a reference voltage generation module and a comparison module;

[0008] The reference voltage generation module is configured to output the corresponding reference voltage based on the time node of the display frame in which the display panel is located;

[0009] The comparison module is configured to output a corresponding comparison voltage based on the acquired voltage and the reference voltage.

[0010] The display frame includes a display phase and a blanking phase;

[0011] When the time node of the display frame in which the display panel is located is the first preset time, the reference voltage output by the reference voltage generation module is switched from the currently output first reference voltage to the second reference voltage; the difference between the first preset time and the start time of the blanking phase is a preset time;

[0012] When the time node of the display frame in which the display panel is located is the second preset time, the reference voltage output by the reference voltage generation module is switched from the currently output second reference voltage to the third reference voltage; the difference between the second preset time and the end time of the blanking phase is a preset time;

[0013] The second reference voltage is less than the first reference voltage, and the third reference voltage is greater than the first reference voltage; the difference between the first preset time and the second preset time is the duration of the blanking phase.

[0014] Wherein, the first preset time is earlier than the start time of the blanking phase.

[0015] The preset time is 30µs.

[0016] The comparison module includes an error amplifier; the non-inverting input of the error amplifier is connected to the reference voltage generation module, the inverting input is connected to the acquisition sub-circuit, and the output is connected to the compensation sub-circuit.

[0017] The compensation sub-circuit includes a logic operation module and an output module; the output module includes an input filter capacitor, an energy storage inductor, a switching transistor, and a third resistor.

[0018] The signal input terminal of the logic operation module is connected to the signal output terminal of the comparator circuit, and the signal output terminal of the logic operation module is connected to the control terminal of the switching transistor; the first terminal of the switching transistor is connected to the output signal terminal that outputs the driving voltage, the second terminal is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the reference ground; the first terminal of the input filter capacitor is connected to the first terminal of the energy storage inductor and the input voltage terminal, and the second terminal of the energy storage inductor is connected to the output signal terminal of the driving voltage.

[0019] The compensation sub-circuit includes a first compensation module and a second compensation module;

[0020] The first compensation module is configured to make an initial adjustment to the current driving voltage based on the comparison voltage;

[0021] The second compensation module is configured to readjust the driving voltage after the initial adjustment based on the time node of the display frame in which the display panel is located.

[0022] The display frame includes a display phase and a blanking phase;

[0023] When the time node of the display frame in which the display panel is located is the first preset time, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to the second driving voltage; the difference between the first preset time and the start time of the blanking stage is a preset time;

[0024] When the time node of the display frame in which the display panel is located is the second preset time, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to the third driving voltage; the difference between the second preset time and the end time of the blanking stage is a preset time;

[0025] The difference between the first preset time and the second preset time is the duration of the blanking phase.

[0026] Wherein, the first preset time is earlier than the start time of the blanking phase.

[0027] The comparison module includes an error amplifier; the non-inverting input of the error amplifier is connected to the reference voltage signal terminal, the inverting input is connected to the acquisition sub-circuit, and the output is connected to the first compensation module.

[0028] The first compensation module includes a logic operation module and an output module; the output module includes a switching transistor and a third resistor.

[0029] The signal input terminal of the logic operation module is connected to the signal output terminal of the comparator circuit, and the signal output terminal of the logic operation module is connected to the control terminal of the switching transistor; the first terminal of the switching transistor is connected to the signal terminal that outputs the driving voltage, the second terminal is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the reference ground.

[0030] The acquisition sub-circuit includes a first resistor and a second resistor;

[0031] The first end of the first resistor is connected to the signal terminal that outputs the driving voltage, the second end of the first resistor and the first end of the second resistor are both connected to the comparator circuit, and the second end of the second resistor is connected to the reference ground.

[0032] The self-calibration circuit further includes a stage identification sub-circuit, configured to receive the number of rows of system data decoded by the timing controller and determine the time node of the display frame in which the display panel is located.

[0033] The self-calibration circuit further includes a stage identification sub-circuit, configured to detect the current magnitude of the voltage generation circuit and determine the time node of the display frame in which the display panel is located.

[0034] This disclosure provides a power management chip, including any of the self-calibration circuits described above; and a voltage generation circuit.

[0035] The voltage generation circuit is configured to output a drive voltage in response to a first voltage and a modulation signal output by a timing controller; the signal output terminal of the voltage generation circuit is multiplexed as the signal input terminal of the self-calibration circuit.

[0036] This disclosure provides a display device including the power management chip and timing controller described above; the timing controller is configured to generate a first voltage and a modulation signal for a voltage generation circuit to generate a drive voltage.

[0037] This disclosure provides a display device including a power management chip, a timing controller, and a display panel. The display panel includes multiple gate lines and multiple data lines, with the gate lines and data lines intersecting to define multiple pixel units. A gate driving circuit provides gate driving signals to the gate lines, and a source driving circuit provides data voltages to the data lines. The power management chip is configured to generate a driving voltage based on a first voltage provided by the timing controller and a modulation signal, to be applied to the source driver.

[0038] The gate driving circuit includes multiple shift registers and at least one redundant shift register; among the multiple gate lines, those connected to the redundant shift register are redundant gate lines, and the pixel units connected to the redundant gate lines are redundant pixel units.

[0039] The timing controller is configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the source drive circuit to provide data voltage to the data lines.

[0040] The blanking phase is divided into a first time period, a second time period, and a third time period from its start time to its end time.

[0041] The timing controller is specifically configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the drive current of the operational amplifier of the source drive circuit to decrease in a stepwise manner in the first time period, have no current output in the second time period, and increase in a stepwise manner in the third time period.

[0042] The blanking phase is divided into a first time period, a second time period, and a third time period from its start time to its end time.

[0043] The timing controller is specifically configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the data voltage written by the source drive circuit to decrease in a stepwise manner in the first time period, be a first data voltage in the second time period, and increase in a stepwise manner in the third time period; the first data voltage is not greater than the minimum voltage written by the source drive circuit in the first time period and the third time period.

[0044] The blanking phase is divided into a first time period, a second time period, and a third time period from its start time to its end time.

[0045] The timing controller is specifically configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the number of output channels of the source drive circuit to be turned on in a stepwise manner during the first time period, to be completely turned off during the second time period, and to be stepped up during the third time period. Attached Figure Description

[0046] Figure 1 is a circuit structure diagram of a voltage generation circuit according to an embodiment of the present disclosure.

[0047] Figure 2 is a structural block diagram of the self-calibration circuit according to an embodiment of this disclosure.

[0048] Figure 3 is a schematic diagram of the structure of a self-calibration circuit according to an embodiment of this disclosure.

[0049] Figures 4a-4b are timing diagrams of the reference voltage generation module generating the reference voltage according to an embodiment of the present disclosure.

[0050] Figure 5 is a schematic diagram of another self-calibration circuit according to an embodiment of this disclosure.

[0051] Figure 6 shows the output waveform of the self-calibration circuit shown in Figure 5.

[0052] Figure 7 is a schematic diagram of the power management chip according to an embodiment of this disclosure.

[0053] Figure 8 is a schematic diagram of the structure of the display panel according to an embodiment of the present disclosure.

[0054] Figure 9 is a timing diagram of the display panel according to an embodiment of the present disclosure.

[0055] Figure 10 is a timing diagram of the gate drive signal provided by the gate drive circuit corresponding to Figure 8.

[0056] Figure 11 is a diagram showing the drive current data of the operational amplifier in the source drive circuit when the display panel is in the blanking stage according to an embodiment of the present disclosure.

[0057] Figure 12 is a grayscale data diagram of the data signal written when the display panel is in the blanking stage according to an embodiment of the present disclosure.

[0058] Figure 13 is a data diagram of the output channel of the time-division multiplexing source drive circuit when the display panel is in the blanking stage according to an embodiment of the present disclosure.

[0059] Figure 14 is a waveform diagram of the time-division multiplexing of the data signal written to the display panel during the blanking phase provided in this disclosure. Detailed Implementation

[0060] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates an "or" relationship between related objects. The terms "first," "second," and "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," and "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0062] In related technologies, a power management chip (PMIC) is a chip that integrates multiple voltage generation circuits. When applied in display products, it is mainly responsible for providing various driving voltages to the display panel, such as driving voltage (AVDD) and digital voltage (DVDD). Taking AVDD voltage as an example, it is generated by the voltage generation circuit in the power management chip (specifically, a BOOST boost circuit), and the specific circuit structure is shown in Figure 1. It should be noted that the control logic of this disclosure is only described using the Boost loop architecture below. Other types of loops, such as the Buck boost circuit that generates the digital signal DVDD and the charge pump circuit that generates the shutdown voltage Vgh, can also use the dynamically adjusted control logic of this disclosure to control the voltage.

[0063] As shown in Figure 1, a boost circuit is a DC-DC converter that transforms the electrical energy of an input signal into the electrical energy of an output signal. Here, the input signal Vi is the first voltage V1 provided by the timing controller, and the output signal Vo is the driving voltage AVDD. The boost circuit specifically includes a switching transistor Q, a diode D, an energy storage inductor L, an input filter capacitor C1, an output filter capacitor C2, and a load R. The first terminal of the input filter capacitor C1 is connected to the signal terminal of the first input signal, and the second terminal is connected to ground. The first terminal of the energy storage inductor L is connected to the signal input terminal, and the second terminal is connected to the first terminal of the switching transistor Q. The switching transistor Q is an N-type transistor, and its control terminal is connected to the PWM pulse signal provided by the timing controller. The PWM pulse signal is a square wave alternating between high and low levels. The second terminal of the switching transistor Q is connected to ground. The anode of the diode D is connected to the first terminal of the switching transistor Q, and its cathode is connected to the first terminal of the output filter capacitor C2. The second terminal of the output filter capacitor C2 is connected to ground. The first terminal of the load R is connected to the signal output terminal, and the second terminal is connected to ground. It is understandable that the output filter capacitor C2 and the load R are connected in parallel. The voltage difference between the two plates of the output filter capacitor C2, or the voltage across the load R, is the output voltage Vo.

[0064] The specific working process of the boost circuit includes: When the PWM wave is high, the switching transistor Q is turned on, which can be equivalent to a short circuit. At this time, the first voltage V1 charges the energy storage inductor L, and the current in the energy storage inductor L increases continuously with time. The diode D is reverse-biased and cut off, which is equivalent to an open circuit. The output filter capacitor C2 discharges to the load R, and the voltage across the output filter capacitor C2 (i.e., the output voltage Vo) decreases continuously with time. When the PWM wave is low, the switching transistor Q is turned off, which can be equivalent to an open circuit. At this time, the voltage across the energy storage inductor L is positive on the right and negative on the left. The diode D is turned on, and the energy storage inductor L begins to discharge. As time increases, the current in the energy storage inductor decreases continuously. At this time, the first voltage V1 and the voltage across the energy storage inductor L are superimposed, charging the output filter capacitor C2 together and supplying power to the load R. As time increases, the voltage across the output filter capacitor C2 (i.e., the output voltage Vo) increases continuously. By inputting a PWM pulse signal to the switching transistor Q, the switching state of the transistor changes continuously, repeating the above process, ultimately making the circuit's output voltage greater than the input voltage.

[0065] It is understandable that during the operation of the above boost circuit, the output filter capacitor and the load are connected in parallel. The load R can be equivalent to a resistor, which has the function of blocking the current. In other words, the presence of the load can slow down the rate of increase of the voltage difference between the two plates of the output filter capacitor, prevent the capacitor from making a whistling sound due to drastic changes in the voltage difference between the two plates, thereby extending the service life of the capacitor and improving the user experience.

[0066] In practical use, the display panel's display process is divided into two stages: the display stage and the blanking stage. The display stage refers to the scanning phase of the frame image, while the blanking stage is the time interval between scanning two frames. In other words, the display process of the display panel alternates between the display stage and the blanking stage. The load driven by the display panel differs depending on the stage it is in; this load specifically includes the gate drive circuitry and pixel units within the display panel. The drastic change in load during the switching between the display and blanking stages causes ripple in the drive voltage, which in turn causes the filter capacitors to whistle.

[0067] To address the aforementioned issues, this disclosure provides a self-calibration circuit for adjusting the driving voltage AVDD generated by the voltage generation circuit. The signal output terminal of the voltage generation circuit is multiplexed as the signal input terminal of the self-calibration circuit. Referring to Figure 2, the self-calibration circuit includes a sampling sub-circuit 1, a comparison sub-circuit 2, and a compensation sub-circuit 3. The sampling sub-circuit 1 is configured to acquire the driving voltage AVDD and generate a sampling voltage Vs; the comparison sub-circuit 2 is configured to compare the sampling voltage Vs with a reference voltage Vref and output a comparison voltage ΔV; the compensation sub-circuit 3 is configured to adjust the current driving voltage AVDD based on the comparison voltage ΔV. Through the above sampling, comparison, and compensation process, the driving voltage can be kept within a relatively stable range, thereby ensuring sufficient driving force and improving the lifespan of the display panel.

[0068] In some examples, the display frame of the display panel includes a display phase AA and a blanking phase. The display phase AA and blanking phase are determined by the valid data strobe signal DE provided by the timing controller Tcon, as shown in Figure 4. The valid data strobe signal DE is a high-level active signal. When the valid data strobe signal is high, the display panel is in the display phase AA; when the valid data strobe signal is low, the display panel is in the blanking phase. That is, the self-calibration circuit can include a phase identification sub-circuit. Specifically, the phase identification sub-circuit can determine whether the display panel is in the display phase AA or the blanking phase based on the received valid data strobe signal DE provided by the timing controller Tcon. Simultaneously, it can also determine the time node of the display frame in which the display panel is located based on the number of rows of display data obtained by decoding the display frame data by the timing controller Tcon (i.e., the number of rows of pixel units currently written to the display data).

[0069] In some examples, the stage identification sub-circuit can also determine the time node of the display frame in which the display panel is located by detecting the current magnitude of the voltage generation circuit. Specifically, since the blanking stage has a smaller load, the corresponding current value of the voltage generation circuit decreases, while the display stage has a larger AA load, and the corresponding current value of the voltage generation circuit decreases.

[0070] In some examples, the time point of the display frame in which the display panel is located can be related to the start time T3 or the end time T4 of the blanking phase. Specifically, the time that differs from the start time T3 of the blanking phase by a preset time t is the first preset time T1, and the time that differs from the end time T4 of the blanking phase by a preset time t is the second preset time T2. Preferably, the preset time t can be 5us or 10us (determined based on the ripple amplitude generated by the drive voltage during phase switching). The first preset time T1 can be earlier than the start time T3 of the blanking phase (at which time the first preset time T1 is in display phase AA), or the first preset time T1 can be later than the start time T3 of the blanking phase (at which time the first preset time T1 is in the blanking phase), but the difference between the first preset time T1 and the second preset time T2 must be equal to the duration of the blanking phase. In other words, if the first preset time T1 is earlier than the start time T3 of the Blanking phase, the second preset time T2 is also earlier than the end time T4 of the Blanking phase; if the first preset time T1 is later than the end time T4 of the Blanking phase, the second preset time T2 is also later than the end time T4 of the Blanking phase.

[0071] The self-calibration circuit of this disclosure embodiment will be described in detail below with reference to specific examples.

[0072] The first example: The self-calibration circuit includes a sampling sub-circuit, a comparison sub-circuit, and a compensation sub-circuit. The comparison sub-circuit 2 includes a reference voltage generation module 201 and a comparison module 202, as shown in Figure 3. The reference voltage generation module 201 is configured to output a corresponding reference voltage based on the time node of the display frame in which the display panel is located. The comparison module 202 is configured to output a corresponding comparison voltage ΔV based on the sampled voltage Vs acquired by the sampling sub-circuit 1 and the reference voltage Vref generated by the reference voltage generation module 201.

[0073] Specifically, when the time node of the display frame in which the display panel is located is the first preset time T1, the reference voltage Vref output by the reference voltage generation module 201 switches from the first reference voltage Vref1 output during the display phase AA to the second reference voltage Vref2. Correspondingly, the comparison voltage ΔV output by the comparison module 202 switches from the first comparison voltage ΔV1 output during the display phase AA to the second comparison voltage ΔV2. When the time node of the display frame in which the display panel is located is the second preset time T2, the reference voltage Vref output by the reference voltage generation module 201 switches from the second reference voltage Vref2 output during the blanking phase to the third reference voltage Vref3. Correspondingly, the comparison voltage ΔV output by the comparison module 202 switches from the second comparison voltage ΔV2 output during the blanking phase to the third comparison voltage ΔV3. In this example, the second reference voltage Vref2 is less than the first reference voltage Vref1, and the third reference voltage Vref3 is greater than the first reference voltage Vref1; the second comparison voltage ΔV2 is less than the first comparison voltage ΔV1, and the third comparison voltage ΔV3 is greater than the first comparison voltage ΔV1. In this example, setting the first preset time T1 earlier than the start time T3 of the blanking phase—that is, detecting changes in the valid data strobe signal DE earlier and adjusting the reference voltage value in advance—and further adjusting the comparison voltage value in advance, can prevent the drive voltage AVDD from changing drastically during phase switching, thereby preventing howling issues.

[0074] As shown in Figure 4a, the voltage of Vo' is the driving voltage output by the voltage generation circuit without the self-calibration circuit of this disclosure. It exhibits drastic changes during the switching between the display and blanking phases. After adding the self-calibration circuit of this disclosure, the voltage of the output signal terminal Vo, i.e., the driving voltage AVDD, only shows a small change during phase switching, resulting in higher reliability. Alternatively, the first preset time T1 can be set later than the start time T3 of the blanking phase. In this case, the change in the reference voltage and comparison voltage can compensate for the ripple in the driving voltage AVDD, reducing the impact of the ripple. It should be noted that the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2, and the voltage difference between the first reference voltage Vref1 and the third reference voltage Vref3, can be set according to the amplitude of the ripple generated when Vo' switches between the display phase AA and the blanking phase. For example, when the ripple amplitude is 1000mV, the voltage difference between the first reference voltage Vref1 and the third reference voltage Vref3 can be set to 500mV; as another example, when the ripple amplitude is 500mV, the voltage difference between the first reference voltage Vref1 and the third reference voltage Vref3 can be set to 300mV.

[0075] It should also be noted that in the above embodiments, the reference voltage generation module 201 switches from the first reference voltage Vref1 to the second reference voltage Vref2 at a first preset time T1, and maintains it until a second preset time T2. At the second preset time T2, it switches from the second reference voltage Vref2 to the third reference voltage Vref3. Optionally, in some other examples, referring to Figure 4b, after the reference voltage switches from the first reference voltage Vref1 to the second reference voltage Vref2, the second reference voltage Vref2 will only be maintained for a period of time t1. After that, the power management chip (PMIC) will automatically switch it back to the first reference voltage Vref1. At this time, the first reference voltage Vref1 will be maintained for a period of time t2 until the second preset time T2 switches to the third reference voltage Vref3. Here, t1 and t2 can be adjusted in the power management chip (PMIC) to improve the flexibility of the circuit.

[0076] Referring again to Figure 3, in some examples, the acquisition sub-circuit 1 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the signal terminal of the output drive voltage AVDD, and the second end is connected to the first end of the second resistor R2. The connection node serves as the signal output terminal of the acquisition sub-circuit 1, which is connected to the comparator sub-circuit 2. The second end of the second resistor R2 is connected to the reference ground. According to the voltage divider formula, the sampling voltage Vs acquired by the acquisition sub-circuit 1 is Vs = R2 / (R1+R2)*Vo.

[0077] In some examples, the comparator sub-circuit 2 includes a reference voltage generation module 201 and a comparison module 202. The comparison module 202 includes an error amplifier OP, wherein the non-inverting input of the error amplifier OP is connected to the signal output of the reference voltage generation module 201, the inverting input is connected to the signal output of the acquisition sub-circuit 1, and the output is connected to the compensation sub-circuit 3. The error amplifier OP compares the reference voltage Vref and the sampled voltage Vs and outputs the corresponding comparison voltage to the compensation sub-circuit 3.

[0078] In some examples, the compensation sub-circuit 3 includes a logic operation module 301 and an output module 302. The output module 302 specifically includes an input filter capacitor C1, an energy storage inductor L, a switching transistor Q, and a third resistor R3. The signal input terminal of the logic operation module 301 is connected to the signal output terminal of the comparator sub-circuit 2, and the signal output terminal of the logic operation module 301 is connected to the control electrode of the switching transistor Q. The first electrode of the switching transistor Q is connected to the signal terminal of the output driving voltage AVDD, and the second electrode is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the reference ground. The first terminal of the input filter capacitor C1 is connected to the first terminal of the energy storage inductor L and the input voltage terminal Vi, and the second terminal of the energy storage inductor L is connected to the output signal terminal V0 of the driving voltage AVDD.

[0079] Specifically, after receiving the comparison voltage, the logic operation module 301 performs a series of logic operations to generate a switch control signal to adjust the duty cycle of the effective and ineffective levels of the switch Q. When the switch Q is turned on, the voltage written to the input voltage terminal Vi charges the energy storage inductor L; when the switch Q is turned off, the energy storage inductor L charges the input filter capacitor C1, thereby adjusting the magnitude of the drive voltage AVDD output by the output signal terminal V0. In other words, by detecting the magnitude of the drive voltage AVDD output by the output signal terminal V0 and comparing it with the reference voltage Vref, the magnitude of the comparison voltage ΔV is controlled, thereby controlling the duty cycle of the effective and ineffective levels of the switch Q, and thus controlling the amount of energy stored in the energy storage inductor in one cycle, thereby adjusting the drive voltage AVDD.

[0080] Specifically, taking the self-calibration circuit shown in Figure 3 as an example, when the display panel is at the first preset time T1 of the display frame, the sampling voltage Vs collected by the sampling sub-circuit 1 is R2 / (R1+R2)*Vo. The sampling voltage Vs is transmitted to the inverting input of the error amplifier OP. The reference voltage generation module 201 switches from the first reference voltage Vref1 to the second reference voltage Vref2. The comparison module 202 compares the sampling voltage Vs and the second reference voltage Vref2, and switches from the first comparison voltage ΔV1 to the second comparison voltage ΔV2. The compensation sub-circuit 3 generates a compensation signal that can pull down the driving voltage AVDD based on the second comparison voltage ΔV2.

[0081] When the display panel is at the second preset time T2 of the display frame, the sampling voltage Vs collected by the sampling sub-circuit 1 is R2 / (R1+R2)*Vo. The sampling voltage Vs is transmitted to the inverting input of the error amplifier OP. The reference voltage generation module 201 switches from the second reference voltage Vref2 to the third reference voltage Vref3. The comparison module 202 compares the sampling voltage Vs and the third reference voltage Vref3, and switches from the second comparison voltage ΔV2 to the third comparison voltage ΔV3. The compensation sub-circuit 3 generates a compensation signal that can pull up the drive voltage AVDD based on the third comparison voltage ΔV3.

[0082] It should be noted that the second reference voltage Vref2 is less than the first reference voltage Vref1, and the third reference voltage Vref3 is greater than the first reference voltage Vref1. Here, the relationship between the first reference voltage Vref1, the second reference voltage Vref2, and the third reference voltage Vref3 only applies to the self-calibration circuit shown in Figure 3. It should be understood that when the circuit structure changes, the relationship between the three reference voltages will also change accordingly. For example, when the inverting input of the error amplifier OP is connected to the signal output of the reference voltage generation module 201, and the non-inverting input is connected to the signal output of the acquisition sub-circuit 1, the second reference voltage Vref2 is greater than the first reference voltage Vref1, and the third reference voltage Vref3 is less than the first reference voltage Vref1.

[0083] When the display panel switches from the display stage AA to the blanking stage, the driving voltage AVDD increases rapidly due to the reduced load. The compensation signal generated by the self-calibration circuit of this disclosure at the first preset time T1 can pre-pull down the driving voltage AVDD, thereby reducing the increase in AVDD and controlling its value within a relatively small range to avoid capacitor howling. Similarly, when the display panel switches from the blanking stage to the display stage AA, the compensation signal can pre-pull up the driving voltage AVDD, controlling its value within a relatively small range.

[0084] The second example is largely the same as the first, except that the reference voltage Vref connected to the comparator sub-circuit is a fixed voltage. The compensation sub-circuit in this example specifically includes a first sub-compensation module and a second sub-compensation module. The first compensation module is configured to initially adjust the current driving voltage AVDD based on the comparator voltage ΔV; the second compensation module is configured to further adjust the initially adjusted driving voltage AVDD based on the time node of the display frame in which the display panel is located. In other words, not only is the driving voltage AVDD initially adjusted based on the comparator voltage ΔV, but it is also adjusted again based on the time node of the display frame in which the display panel is located, thus reducing the impact of ripple.

[0085] Specifically, when the time node of the display frame in which the display panel is located is the first preset time T1, the second compensation module adjusts the driving voltage AVDD, which was initially adjusted by the first compensation module, switching it from the first driving voltage AVDD1 output during the display phase AA to the second driving voltage AVDD2. When the time node of the display frame in which the display panel is located is the second preset time T2, the second compensation module adjusts the driving voltage AVDD, which was initially adjusted by the first compensation module, switching it from the second driving voltage AVDD2 output during the blanking phase to the third driving voltage AVDD3. The second driving voltage AVDD2 is less than the first driving voltage AVDD1, and the third driving voltage AVDD3 is greater than the first driving voltage AVDD1.

[0086] In this example, setting the first preset time T1 earlier than the start time T3 of the Blanking phase—that is, detecting changes in the valid data strobe signal earlier and adjusting the drive voltage AVDD in advance—prevents drastic changes in the drive voltage AVDD during phase switching, thus preventing howling issues. Alternatively, the first preset time T1 can be set earlier than or later than the start time T3 of the Blanking phase. In this case, the change in the comparison voltage can compensate for ripples in the drive voltage AVDD, reducing the impact of the ripples.

[0087] In this example, the first compensation sub-circuit has the same architecture as the compensation circuit in the first example, that is, the first compensation sub-circuit includes a logic operation module 301 and an output module 302.

[0088] The output module 302 specifically includes an input filter capacitor C1, an energy storage inductor L, a switching transistor Q, and a third resistor R3. The signal input terminal of the logic operation module 301 is connected to the signal output terminal of the comparator circuit 2, and the signal output terminal of the logic operation module 301 is connected to the control electrode of the switching transistor Q. The first electrode of the switching transistor Q is connected to the signal terminal of the output drive voltage AVDD, and the second electrode is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to reference ground. The first terminal of the input filter capacitor C1 is connected to the first terminal of the energy storage inductor L and the input voltage terminal Vi, and the second terminal of the energy storage inductor L is connected to the output signal terminal V0 of the drive voltage AVDD.

[0089] Specifically, after receiving the comparison voltage, the logic operation module 301 performs a series of logic operations to obtain a switch control signal, which adjusts the duty cycle of the effective and ineffective levels of the switch transistor Q. When the switch transistor Q is turned on, the voltage written to the input voltage terminal Vi charges the energy storage inductor L; when the switch transistor Q is turned off, the energy storage inductor L charges the input filter capacitor C1, thereby adjusting the magnitude of the drive voltage AVDD output by the output signal terminal V0. In other words, by detecting the magnitude of the drive voltage AVDD output by the output signal terminal V0 and comparing it with the reference voltage Vref, the magnitude of the comparison voltage ΔV is controlled, thereby controlling the on and off duty cycles of the switch transistor Q, and thus controlling the amount of energy in the energy storage inductor in one cycle, to achieve the adjustment of the drive voltage AVDD. The comparison sub-circuit in this embodiment has the same structure as the comparison module in the first example above, and the sampling sub-circuit 1 is the same as the sampling sub-circuit 1 in the first example above, so it will not be repeated here.

[0090] Specifically, taking the self-calibration circuit shown in Figure 5 as an example, when the display panel is at the first preset time T1 of the display frame, the sampling sub-circuit 1 collects the sampling voltage Vs = R2 / (R1+R2)*Vo. The sampling voltage Vs is transmitted to the inverting input of the error amplifier OP. The comparison module 202 compares the sampling voltage with the reference voltage and outputs a comparison voltage. The first compensation module 303 is configured to make an initial adjustment to the current driving voltage AVDD based on the comparison voltage ΔV. The second compensation module 304 is configured to make a further adjustment to the driving voltage AVDD after the initial adjustment based on the time node of the display frame in which the display panel is located.

[0091] When the display panel is at the second preset time T2 of the display frame, the acquisition voltage Vs = R2 / (R1+R2)*Vo acquired by the acquisition sub-circuit 1 is transmitted to the inverting input of the error amplifier OP. The comparison module 202 compares the acquired voltage with the reference voltage and outputs a comparison voltage. The first compensation module 303 adjusts the driving voltage AVDD for the first time according to the comparison voltage. After the first compensation module 303 adjusts the driving voltage AVDD for the first time, the second compensation module 304 switches from the second driving voltage AVDD2 output when it is in the display stage AA to the third driving voltage AVDD3. The second compensation module 304 generates a compensation signal that can pull down the driving voltage AVDD based on the third driving voltage AVDD3.

[0092] As shown in Figure 6, the second driving voltage AVDD2 is less than the first driving voltage AVDD1, and the third driving voltage AVDD3 is greater than the first driving voltage AVDD1. When the display panel switches from the display stage AA to the blanking stage, the driving voltage AVDD increases rapidly due to the reduced load. The compensation signal generated by the self-calibration circuit of this disclosure at the first preset time T1 can pre-pull down the driving voltage AVDD, thereby reducing the increase in the driving voltage AVDD and controlling its value within a relatively small range to avoid capacitor howling. Similarly, when the display panel switches from the blanking stage to the display stage AA, the compensation signal can pre-pull up the driving voltage AVDD, controlling its value within a relatively small range.

[0093] It should be noted that in the first example, the power management chip (PMIC) pre-adjusts the reference voltage Vref, and consequently pre-adjusts the comparison voltage. In the second example, the drive voltage AVDD is pre-adjusted directly. By pre-adjusting the drive voltage AVDD, and consequently pre-adjusting the logic control signal output by the logic operation module, the response speed of the self-calibration circuit can be accelerated, thereby reducing the ripple amplitude generated when the drive voltage AVDD switches at different stages. This controls the drive voltage AVDD to fluctuate within a small range, preventing the filter capacitor from whistling and affecting its lifespan. It should be understood that adjusting other parameters in the self-calibration circuit can achieve the same effect and is also within the scope of this disclosure. For example, the acquisition voltage acquired by the acquisition sub-circuit can be pre-adjusted, the tail current (gm) of the error amplifier can be pre-adjusted, and the logic control signal output by the logic operation module can be pre-adjusted directly.

[0094] As shown in Figure 7, this disclosure also provides a power management chip (PMIC) that includes the self-calibration circuit of any of the above embodiments. The PMIC further includes the voltage generation circuit described above (taking the boost circuit as an example). The signal output terminal of the boost circuit is multiplexed as the signal input terminal of the self-calibration circuit.

[0095] This disclosure also provides a display device including the aforementioned power management chip PMIC, timing controller Tcon, and display panel. The timing controller Tcon is configured to generate a first voltage and a modulation signal for a voltage generation circuit to generate a drive voltage. The power management chip PMIC provides an operating voltage to the source drive circuit of the display panel based on the drive voltage generated by the timing controller Tcon.

[0096] As shown in Figure 8, this disclosure also provides a display device, which includes a power management chip (PMIC), a timing controller (Tcon), and a display panel. The display panel includes multiple gate lines (Gates) and multiple data lines (Data). Multiple pixel units are defined by the intersection of the gate lines and data lines. A gate driver circuit (Gate Driver) provides gate drive signals to the gate lines, and a source driver circuit (Source Driver IC) provides data voltages (DATA) to the data lines. The PMIC is configured to generate a drive voltage (AVDD) based on a first voltage provided by the timing controller (Tcon) and a modulation signal, and to apply this voltage to the source driver IC. The gate driver circuit includes multiple shift registers (GOAs) and at least one redundant shift register (Dummy GOA). The gate lines connected to the redundant shift registers (Dummy GOA) are redundant gate lines, and the pixel units connected to the redundant gate lines are redundant pixel units. The timing controller Tcon is configured to control the redundant shift register Dummy GOA to provide gate drive signals for redundant gate lines to drive redundant pixel units when the display panel is in the blanking stage, and to control the source driver IC to provide data voltage DATA for the data line Data.

[0097] The display panel can be divided into a display area and a peripheral area surrounding the display area. Referring to Figure 8, the timing controller Tcon, power management chip PMIC, source driver circuit, gate driver circuit, redundant pixel units, and redundant gate lines are arranged in the peripheral area.

[0098] Specifically, the shift registers are cascaded sequentially. Referring to Figure 9, the rising edges of the clock signals transmitted by the clock signal lines connected to each shift register GOA are sequentially 1H apart, where H is the unit scan time. Redundant shift registers (Dummy GOAs) are also cascaded sequentially, with the rising edges of the clock signals transmitted by the clock signal lines connected to each Dummy GOA sequentially 1H apart. Furthermore, the first Dummy GOA is cascaded with the last shift register GOA; that is, the signal output of the last shift register GOA is connected to the signal input of the first Dummy GOA, and the signal output of the first Dummy GOA is connected to the reset signal of the last shift register GOA. The rising edge of the clock signal transmitted by the clock signal line connected to the first Dummy GOA is also 1H apart from the rising edge of the clock signal transmitted by the clock signal line connected to the last shift register GOA.

[0099] Referring again to Figure 9, exemplarily, the display panel includes 1200 rows of pixel units connected one-to-one with 1200 shift registers GOA, and 6 rows of redundant pixel units connected one-to-one with 6 redundant shift registers Dummy GOA. The clock signals corresponding to the 1200 shift registers GOA are all within the display phase, so that during the display phase, the AA drives the shift registers GOA to output gate drive signals to display the pixel units. The clock signals corresponding to the 6 redundant shift registers Dummy GOA are all within the blanking phase, so that during the blanking phase, the blanking drives the redundant shift registers Dummy GOA to ensure that the load of the drive voltage is not zero. Figure 10 shows the gate drive signals output by the 1206 shift registers GOA corresponding to Figure 9. The rising edges of the 1206 gate drive signals are sequentially separated by 1H, where H is the unit scan time.

[0100] In this embodiment of the disclosure, the timing controller Tcon is configured to control the redundant shift register Dummy GOA to provide gate drive signals for redundant gate lines during the blanking phase, so as to drive redundant pixel units to work, and to control the source driver IC to provide data voltage for the data lines, so as to adjust the load of the power management chip PMIC output signal terminal Vo during the blanking phase, thereby reducing the jitter of the drive voltage AVDD output by the output signal terminal Vo.

[0101] The following explanation uses specific examples.

[0102] Example 1: As shown in Figure 11, the timing controller controls the power management chip (PMIC) to generate a driving voltage AVDD. During the display phase, the AA controls the gate drive circuit to scan the gate lines line by line, and controls the operational amplifier AMPB in the source driver IC to write the corresponding data voltage to the data lines through the driving voltage AVDD with a first preset driving current, thereby charging the corresponding pixel units. Specifically, the blanking phase is divided into three periods: T1, T2, and T3, from its start to its end. During the blanking phase, the timing controller controls the redundant shift register Dummy GOA in the gate drive circuit (Tcon) to operate, i.e., increases the timing control signal CLK to scan the redundant gate lines, enabling the redundant pixel units to operate. Simultaneously, the timing controller Tcon controls the driving current of the operational amplifier AMPB in the source driver IC, which decreases stepwise in the first period T1, has no current output in the second period T2, and increases stepwise in the third period T3. It should be noted that the maximum drive current of the operational amplifier AMPB in both the first time period T1 and the third time period T3 is no greater than the first preset drive current of the display stage. For example, as shown in Figure 11, the first preset drive current in the display stage AA is 100% of the drive current. In the first time period T1, the drive current changes at a ratio of 75%→50%→25%, and in the third time period T3, the drive current changes at a ratio of 25%→50%→75%. This method can effectively alleviate the problem of jitter in the drive voltage AVDD caused by the large load change during the transition from the display stage AA to the blanking stage. In the blanking stage, there is no data voltage signal output load, meaning the drive current is 0%, which is significantly different from the large load (255 grayscale) of the display stage AA.

[0103] It should be noted that the reason why adjusting the drive current of the operational amplifier AMPB of the source driver IC can alleviate the jitter of the drive voltage AVDD is that the operational amplifier AMPB of the source driver IC is connected to the output signal terminal Vo of the power management chip PMIC, and is therefore affected by the drive voltage AVDD. Thus, when the drive current of the operational amplifier AMPB of the source driver IC changes, the load connected to the output signal terminal Vo of the power management chip PMIC can be adjusted, thereby regulating the fluctuation of the drive voltage AVDD.

[0104] The second example: As shown in Figure 12, the timing controller Tcon controls the power management chip (PMIC) to generate the driving voltage AVDD. During the display phase, the AA controls the gate drive circuit to scan the gate lines line by line, and controls the source driver IC to write the corresponding data voltage to the data lines according to the driving voltage AVDD, so as to charge the corresponding pixel units. In particular, the blanking phase is divided into three periods: the first period T1, the second period T2, and the third period T3, from its start time to its end time. During the blanking phase, the timing controller Tcon controls the redundant shift register (Dummy GOA) in the gate drive circuit to work, that is, to increase the timing control signal CLK to scan the redundant gate lines so that the redundant pixel units can work. At the same time, the timing controller Tcon controls the data voltage written by the source driver circuit in the blanking phase to decrease stepwise in the first period T1, be the first data voltage in the second period T2, and increase stepwise in the third period T3. The first data voltage is not greater than the minimum voltage written by the source driver IC in the first period T1 and the third period T3. This method can effectively alleviate the problem of jitter in the drive voltage AVDD caused by the transition of the display panel from the display stage AA to the blanking stage. During the blanking stage, there is no data voltage signal output load and the load is minimal.

[0105] In some examples, during the display phase AA, the data signal written to the pixel unit connected to the shift register is a valid data signal that needs to be displayed. During the blanking phase, the data signal written to the pixel unit connected to the redundant shift register Dummy GOA is an invalid data signal. For example, the invalid data signal may include a full black display that causes the display panel to display a grayscale of 0.

[0106] In other examples, invalid data signals can be determined based on the grayscale voltage corresponding to the data signal written to the last row of pixel units at the end of the display phase, as shown in Table 1. As shown in Table 1, when the grayscale value corresponding to the data signal written to the last row of pixel units is between 192 and 255, a grayscale value of 192 can be selected as the grayscale for invalid display; when the grayscale value corresponding to the data signal written to the last row of pixel units is between 128 and 192, a grayscale value of 128 can be selected as the grayscale for invalid display; and so on.

[0107] Table 1

[0108] Optionally, during the aforementioned invalid display process, the grayscale value corresponding to the written data signal can change in a stepwise manner. Referring to Figure 10, when a grayscale value of 192 is selected as the grayscale value during invalid display, it can first decrease to 0 in a stepwise manner and then increase to 255 in a stepwise manner, facilitating the writing of the data signal in the next display stage AA. Specifically, the blanking stage is divided into three time periods: the first time period T1, the second time period T2, and the third time period T3. The grayscale value change in the first time period T1 can be: 192→128→64, the grayscale value in the second time period T2 can be 0, and the grayscale value change in the third time period T3 can be: 64→128→192→255.

[0109] In some examples, when the display panel is in the blanking phase, at least some of the data lines provide the same data signal. It should be noted that the data voltages provided during the blanking phase are all invalid display signals. By grouping and writing multiple data signals provided by the source driver IC into the data lines, the number of loads driven by the drive voltage AVDD can be reduced in a stepwise manner. For example, for a display panel with 960 columns of pixel units, the 960 columns of pixel units can be divided into three groups, and data signals can be written sequentially. At the first moment, the first data signal DATA1 is written to the first group of pixel units; at the second moment, the second data signal DATA2 is written to the second group of pixel units; and at the third moment, the third data signal DATA3 is written to the third group of pixel units. Referring to Figure 11, the drive voltage AVDD will show three small increases without drastic changes that would cause the filter capacitor to squeal.

[0110] The third example: As shown in Figure 13, the timing controller controls the power management chip to generate the driving voltage AVDD, and during the display phase, the AA controls the gate driving circuit to scan the gate lines line by line, and controls the source driver IC to write the corresponding data voltage to the data lines according to the driving voltage AVDD, so as to charge the corresponding pixel units. In particular, the blanking phase is divided into three periods: the first period T1, the second period T2, and the third period T3, from its start time to its end time. During the blanking phase, the timing controller Tcon controls the redundant shift register Dummy GOA in the gate driving circuit to work, that is, to increase the timing control signal CLK, scan the redundant gate lines, so that the redundant pixel units work. At the same time, the timing controller Tcon controls the number of output channels of the source driver circuit to be turned on, which decreases stepwise in the first period T1, is completely turned off in the second period T2, and increases stepwise in the third period T3. This method can effectively alleviate the problem of jitter in the drive voltage AVDD caused by the transition of the display panel from the display stage AA to the blanking stage. During the blanking stage, there is no data voltage signal output load and the output load is minimal, as shown in Figure 14.

[0111] In some examples, the duration of the blanking phase is t, divided into 5 equal parts, t / 5. In this case, the first time period T1 of the blanking phase is the first and second t / 5, the second time period T2 is the third t / 5, and the third time period T3 is the fourth and fifth t / 5. At the first t / 5, 2 / 3 of the output channel of the source driver IC is turned on. At the second t / 5, 1 / 3 of the output channel of the source driver IC is turned on. At the second t / 5, the output channel of the source driver IC is turned off. At the fourth t / 5, 1 / 3 of the output channel of the source driver IC is turned on. At the fifth t / 5, 2 / 3 of the output channel of the source driver IC is turned on.

[0112] In some examples, the power management chip (PMIC) includes a voltage generation circuit and a self-calibration circuit. The self-calibration circuit may include a sampling sub-circuit, a comparator sub-circuit, and a compensation sub-circuit. The sampling sub-circuit and the compensation sub-circuit can both adopt the structure shown in Figure 3, and the comparator sub-circuit can adopt the comparator sub-circuit shown in Figure 5. Therefore, they will not be described again here.

[0113] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A self-calibration circuit configured to adjust a drive voltage generated by a voltage generation circuit in a power management chip; The self-calibration circuit includes a sampling sub-circuit, a comparison sub-circuit, and a compensation sub-circuit. The sampling sub-circuit is configured to acquire the driving voltage and generate a sampling voltage; Based on the time node of the display frame in which the display panel is located, the comparison sub-circuit is configured to compare the sampled voltage and the reference voltage and output a comparison voltage; the compensation sub-circuit is configured to adjust the current driving voltage based on the comparison voltage.

2. The self-calibration circuit according to claim 1, wherein, The comparator sub-circuit includes a reference voltage generation module and a comparison module; The reference voltage generation module is configured to output the corresponding reference voltage based on the time node of the display frame in which the display panel is located; The comparison module is configured to output a corresponding comparison voltage based on the acquired voltage and the reference voltage.

3. The self-calibration circuit according to claim 2, wherein, The display frame includes a display phase and a blanking phase; When the time node of the display frame in which the display panel is located is the first preset time, the reference voltage output by the reference voltage generation module is switched from the currently output first reference voltage to the second reference voltage; the difference between the first preset time and the start time of the blanking phase is a preset time; When the time node of the display frame in which the display panel is located is the second preset time, the reference voltage output by the reference voltage generation module is switched from the currently output second reference voltage to the third reference voltage; the difference between the second preset time and the end time of the blanking phase is a preset time; The second reference voltage is less than the first reference voltage, and the third reference voltage is greater than the first reference voltage; the difference between the first preset time and the second preset time is the duration of the blanking phase.

4. The self-calibration circuit according to claim 3, wherein, The first preset time is earlier than the start time of the blanking phase.

5. The self-calibration circuit according to claim 3, wherein, The preset time is 30us.

6. The self-calibration circuit according to claim 2, wherein the comparison module includes an error amplifier; the non-inverting input terminal of the error amplifier is connected to the reference voltage generation module, the inverting input terminal is connected to the acquisition sub-circuit, and the output terminal is connected to the compensation sub-circuit.

7. The self-calibration circuit according to claim 2, wherein, The compensation sub-circuit includes a logic operation module and an output module; the output module includes an input filter capacitor, an energy storage inductor, a switching transistor, and a third resistor; The signal input terminal of the logic operation module is connected to the signal output terminal of the comparator circuit, and the signal output terminal of the logic operation module is connected to the control terminal of the switching transistor; the first terminal of the switching transistor is connected to the output signal terminal that outputs the driving voltage, the second terminal is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the reference ground; the first terminal of the input filter capacitor is connected to the first terminal of the energy storage inductor and the input voltage terminal, and the second terminal of the energy storage inductor is connected to the output signal terminal of the driving voltage.

8. The self-calibration circuit according to claim 1, wherein, The compensation sub-circuit includes a first compensation module and a second compensation module; The first compensation module is configured to make an initial adjustment to the current driving voltage based on the comparison voltage; The second compensation module is configured to readjust the driving voltage after the initial adjustment based on the time node of the display frame in which the display panel is located.

9. The self-calibration circuit according to claim 8, wherein, The display frame includes a display phase and a blanking phase; When the time node of the display frame in which the display panel is located is the first preset time, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to the second driving voltage; the difference between the first preset time and the start time of the blanking stage is a preset time; When the time node of the display frame in which the display panel is located is the second preset time, the second compensation module adjusts the driving voltage after the initial adjustment from the first driving voltage to the third driving voltage; the difference between the second preset time and the end time of the blanking stage is a preset time; The difference between the first preset time and the second preset time is the duration of the blanking phase.

10. The self-calibration circuit according to claim 9, wherein, The first preset time is earlier than the start time of the blanking phase.

11. The self-calibration circuit according to claim 8, wherein, The comparison module includes an error amplifier; the non-inverting input of the error amplifier is connected to the reference voltage signal terminal, the inverting input is connected to the acquisition sub-circuit, and the output is connected to the first compensation module.

12. The self-calibration circuit according to claim 8, wherein, The first compensation module includes a logic operation module and an output module; the output module includes a switching transistor and a third resistor; The signal input terminal of the logic operation module is connected to the signal output terminal of the comparator circuit, and the signal output terminal of the logic operation module is connected to the control terminal of the switching transistor; the first terminal of the switching transistor is connected to the signal terminal that outputs the driving voltage, the second terminal is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to the reference ground.

13. The self-calibration circuit according to claim 1, wherein, The acquisition sub-circuit includes a first resistor and a second resistor; The first end of the first resistor is connected to the signal terminal that outputs the driving voltage, the second end of the first resistor and the first end of the second resistor are both connected to the comparator circuit, and the second end of the second resistor is connected to the reference ground.

14. The self-calibration circuit according to claim 1, wherein, Also includes: The stage identification sub-circuit is configured to receive the number of rows of system data decoded by the timing controller and determine the time node of the display frame in which the display panel is located.

15. The self-calibration circuit according to claim 1, wherein, Also includes: The stage identification sub-circuit is configured to detect the current magnitude of the voltage generation circuit and determine the time node of the display frame in which the display panel is located.

16. A power management chip, comprising a self-calibration circuit as described in any one of claims 1-15, and a voltage generation circuit; The voltage generation circuit is configured to output a drive voltage in response to a first voltage and a modulation signal output by a timing controller; the signal output terminal of the voltage generation circuit is multiplexed as the signal input terminal of the self-calibration circuit.

17. A display device comprising a power management chip and a timing controller as described in claim 16; the timing controller being configured to generate a first voltage and a modulation signal for a voltage generation circuit to generate a drive voltage.

18. A display device comprising a power management chip, a timing controller, and a display panel; the display panel comprising a plurality of gate lines and a plurality of data lines, wherein the gate lines and the data lines intersect to define a plurality of pixel units, a gate driving circuit providing gate driving signals to the gate lines, and a source driving circuit providing data voltages to the data lines; the power management chip being configured to generate a driving voltage based on a first voltage provided by the timing controller and a modulation signal, to be applied to the source driver; wherein, The gate driving circuit includes multiple shift registers and at least one redundant shift register; among the multiple gate lines, those connected to the redundant shift register are redundant gate lines, and the pixel units connected to the redundant gate lines are redundant pixel units. The timing controller is configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the source drive circuit to provide data voltage to the data lines.

19. The display device according to claim 18, wherein, The blanking phase is divided into a first time period, a second time period, and a third time period from its start time to its end time. The timing controller is specifically configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the drive current of the operational amplifier of the source drive circuit to decrease in a stepwise manner in the first time period, have no current output in the second time period, and increase in a stepwise manner in the third time period.

20. The display device according to claim 18, wherein, The blanking phase is divided into a first time period, a second time period, and a third time period from its start time to its end time. The timing controller is specifically configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the data voltage written by the source drive circuit to decrease in a stepwise manner in the first time period, be a first data voltage in the second time period, and increase in a stepwise manner in the third time period; the first data voltage is not greater than the minimum voltage written by the source drive circuit in the first time period and the third time period.

21. The display device according to claim 18, wherein, The blanking phase is divided into a first time period, a second time period, and a third time period from its start time to its end time. The timing controller is specifically configured to, when the display panel is in the blanking phase, control the redundant shift register to provide gate drive signals to the redundant gate lines to drive the redundant pixel units to work, and control the number of output channels of the source drive circuit to be turned on in a stepwise manner during the first time period, to be completely turned off during the second time period, and to be stepped up during the third time period.

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