Printed wiring board substrate and printed wiring board

Abstract

This printed wiring board substrate comprises a base film and a base layer. The base film has a main surface. The base layer is in contact with the main surface. A direction perpendicular to the main surface is defined as a first direction. After an electrolytic plating layer is formed on the base layer so that the total thickness together with the base layer is 1 μm or greater, when a cross-section of the base layer and the electrolytic plating layer is measured through electron backscatter diffraction, crystal grains oriented on the {111} plane viewed from the first direction in a region up to 1 μm from the main surface are defined as first crystal grains. The crystal grains oriented on the {111} plane are oriented on a plane within 10° of the measurement tolerance from the {111} plane. When crystal grains other than the crystal grains oriented on the {111} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

Description

Substrate for printed wiring board and printed wiring board

[0001] The present disclosure relates to a substrate for a printed wiring board and a printed wiring board.

[0002] International Publication No. 2019 / 208077 (Patent Document 1) discloses a substrate for a printed wiring board including a base film and an electroless plating layer.

[0003] International Publication No. 2019 / 208077

[0004] The substrate for a printed wiring board according to the present disclosure comprises a base film and an underlayer. The base film has a main surface. The underlayer is in contact with the main surface. A direction perpendicular to the main surface is defined as a first direction. After forming an electroplated layer on the underlayer so that the total thickness of the underlayer and the electroplated layer is 1 μm or more, a cross section of the underlayer and the electroplated layer is measured by electron backscatter diffraction. When the cross section is measured from 1 μm from the main surface, crystal grains oriented in the {111} plane as viewed from the first direction are defined as first crystal grains. The {111} plane-oriented crystal grains are crystal grains oriented in a plane within a measurement tolerance of 10° from the {111} plane. When crystal grains other than the {111} plane-oriented crystal grains are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

[0005] FIG. 1 is a cross-sectional view showing the configuration of a substrate for printed wiring boards according to the first embodiment. FIG. 2 is a flowchart showing a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 3 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 4 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 5 is a cross-sectional view showing a configuration of a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 6 is a flowchart showing a method for manufacturing a modified example of a substrate for printed wiring boards according to the first embodiment. FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 8 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 9 is a schematic configuration diagram of a plating apparatus. FIG. 10 is a cross-sectional view showing one step of a method for manufacturing a substrate for printed wiring boards according to the first embodiment. FIG. 11 is a cross-sectional view showing the configuration of a printed wiring board according to the second embodiment. FIG. 12 is a flowchart showing a method for manufacturing a printed wiring board according to the second embodiment. FIG. 13 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 14 is a cross-sectional view showing one step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 15 is a cross-sectional view showing a step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 16 is a cross-sectional view showing a step of a method for manufacturing a printed wiring board according to the second embodiment. FIG. 17 is a schematic cross-sectional view of a laminate shown in region XVII of FIG. 11. FIG. 18 is a cross-sectional view of a printed wiring board substrate showing an object for measuring crystal orientation distribution. FIG. 19 is a crystal orientation distribution in a laminate of sample 1. FIG. 20 is a crystal orientation distribution in a laminate of sample 7. FIG. 21 is a crystal orientation distribution in a laminate of sample 1. FIG. 22 is a crystal orientation distribution in a laminate of sample 7. FIG. 23 is a plan view of an evaluation TEG (Test Element Group).

[0006] [Problem to be Solved by the Present Disclosure] There is a demand for finer circuits on printed wiring boards. In a semi-additive process suitable for forming finer circuits, a circuit composed of a laminate including an underlayer and an electroplated layer is formed on the surface of a base film on which an underlayer has been formed by undergoing the steps of resist pattern formation, electroplating, resist removal, and underlayer etching. In the step of etching the underlayer, it is difficult to uniformly etch the underlayer and the electroplated layer, which may impair the rectangularity of the circuit.

[0007] An object of the present disclosure is to provide a printed wiring board having a circuit with excellent rectangularity.

[0008] Effect of the Present Disclosure According to the present disclosure, it is possible to provide a printed wiring board including a circuit with excellent rectangularity.

[0009] [Outline of the embodiment] First, the embodiments of the present disclosure will be listed and described.

[0010] (1) A substrate for a printed wiring board according to the present disclosure includes a base film and an underlayer. The base film has a main surface. The underlayer is in contact with the main surface. A direction perpendicular to the main surface is defined as a first direction. After forming an electroplated layer on the underlayer so that the total thickness of the underlayer and the electroplated layer is 1 μm or more, a cross section of the underlayer and the electroplated layer is measured by electron backscatter diffraction. Crystal grains oriented in the {111} plane as viewed from the first direction in a region up to 1 μm from the main surface are defined as first crystal grains. Crystal grains oriented in the {111} plane are crystal grains oriented in a plane within a measurement tolerance of 10° from the {111} plane. When crystal grains other than the crystal grains oriented in the {111} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

[0011] (2) The printed wiring board according to the present disclosure may include a base film and a laminate portion. The base film may have a main surface. The laminate portion may be disposed on the main surface. The laminate portion may include an underlayer and an electroplated layer. The underlayer may contact the main surface. The electroplated layer may contact the underlayer. A direction perpendicular to the main surface may be defined as the first direction. When a cross section of the laminate portion is measured by electron backscatter diffraction, crystal grains oriented in the {111} plane as viewed from the first direction in a region up to 1 μm from the main surface may be defined as first crystal grains. The crystal grains oriented in the {111} plane may be crystal grains oriented in a plane within a measurement tolerance of 10° from the {111} plane. When crystal grains other than the crystal grains oriented in the {111} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

[0012] (3) In the printed wiring board of (2) above, a direction perpendicular to the first direction may be the second direction. A direction perpendicular to the first direction and the second direction may be the third direction. The laminated portion may be formed to extend linearly along the second direction. The laminated portion may include adjacent first and second laminated portions. The width of each of the first and second laminated portions may be 15 μm or less. The shortest distance in the third direction from the first laminated portion to the second laminated portion may be 15 μm or less.

[0013] (4) In the printed wiring board of (3), the width of each of the first laminate portion and the second laminate portion may be 10 μm or less, and the shortest distance from the first laminate portion to the second laminate portion in the third direction may be 10 μm or less.

[0014] (5) In the printed wiring board of (3) or (4), the width of each of the first laminate portion and the second laminate portion may be 2 μm or more, and the shortest distance from the first laminate portion to the second laminate portion in the third direction may be 2 μm or more.

[0015] (6) In the printed wiring boards of (3) to (5) above, the laminated portions may each have a maximum width and a minimum width in cross section, and the value obtained by dividing the minimum width by the maximum width may be 0.8 or more.

[0016] (7) In the printed wiring boards of (3) to (6) above, the laminate portion may have a first surface and two side surfaces in a cross section. The first surface may be the surface farthest from the main surface in the first direction. The two side surfaces may connect the first surface and the main surface. At least one of the two side surfaces may include a first point and a first recessed point. The first point may be a point where the side surface and the first surface intersect. The first recessed point may be located at a position that is farthest from the first point in the third direction. The distance from the first point to the first recessed point in the third direction may be 0.15 times or less the height from the main surface to the first surface.

[0017] (8) In the printed wiring boards of (3) to (7) above, the laminate portion may have a first surface, a second surface, and two side surfaces in a cross section. The first surface may be the surface farthest from the main surface in the first direction. The two side surfaces may contact the first surface and the main surface. The laminate portion may contact the main surface at the second surface. At least one of the two side surfaces may include a second point and a second recessed point. The second point may be a point where the side surface and the second surface intersect. The second recessed point may be located at a position that is farthest from the second point in the third direction. The distance from the second point to the second recessed point in the third direction may be 0.15 times or less the height from the main surface to the first surface.

[0018] (9) In the printed wiring boards of (2) to (8) above, the thickness of the underlayer may be 1 μm or less.

[0019] [Details of the embodiment] The details of the embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated. The substrate for a printed wiring board and the printed wiring board according to the embodiment are referred to as a substrate for a printed wiring board 100 (100a, 100b) and a printed wiring board 200, respectively.

[0020] (Configuration of Substrate for Printed Wiring Board) The configuration of the substrate for printed wiring board 100a will be described below.

[0021] 1 is a cross-sectional view of a substrate 100a for a printed wiring board. As shown in FIG. 1, the substrate 100a for a printed wiring board includes a base film 1 and an underlayer 2.

[0022] The base film 1 has a main surface 1s. The base film 1 is made of a flexible insulating material, such as polyimide.

[0023] The base layer 2 is in contact with the main surface 1s. The base layer 2 is composed of either a sputtered copper layer or a nano-copper sintered body layer. In the case of a nano-copper sintered body layer, the nano-copper sintered body layer is formed of a plurality of sintered copper particles. Therefore, the nano-copper sintered body layer is porous. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 1 nm or more or 30 nm or more. The average particle size of the copper particles contained in the nano-copper sintered body layer may be 100 nm or less or 500 nm or less. That is, the copper particles contained in the nano-copper sintered body layer may be nano-copper particles. In addition, in the particle size distribution of the copper particles contained in the nano-copper sintered body layer, the value obtained by dividing the first particle diameter D10 by the second particle diameter D50 is less than 0.5. In the particle size distribution of the copper particles contained in the nano-copper sintered body layer, the value obtained by dividing the third particle diameter D90 by the second particle diameter D50 is greater than 2.0. Note that the particle size distribution is the distribution of the particle sizes of the copper particles contained in the nano-copper sintered body layer. The first particle diameter D10 is the diameter of the copper particles at which the integrated value of the frequency of the copper particle diameters up to the first particle diameter D10 in the particle size distribution of the copper particles contained in the nanocopper sintered body layer is 0.1 times the integrated value of the frequency of the copper particle diameters for all copper particle diameters in the particle size distribution. The second particle diameter D50 is the diameter of the copper particles at which the integrated value of the frequency of the copper particle diameters up to the second particle diameter D50 in the particle size distribution of the copper particles contained in the nanocopper sintered body layer is 0.5 times the integrated value of the frequency of the copper particle diameters for all copper particle diameters in the particle size distribution. In other words, the second particle diameter D50 is the median diameter of the copper particles in the particle size distribution (the median value of the diameters of the copper particles in the particle size distribution). The third particle diameter D90 is the diameter of the copper particles at which the cumulative frequency of the copper particle diameters up to the third particle diameter D90 in the particle size distribution of the copper particles contained in the nanocopper sintered layer is 0.9 times the cumulative frequency of the copper particle diameters for all copper particles in the particle size distribution. By controlling the diameter of the copper particles as described above, copper can be laminated without distortion of the crystal grains when copper is laminated in a subsequent process.The average particle size and particle size distribution of the copper particles contained in the paste used to form the nanocopper sintered body layer are measured using a particle size distribution measuring device (for example, a Microtrac particle size distribution meter UPA-150EX manufactured by Nikkiso Co., Ltd.) As will be described later, an electroless copper plating layer (not shown) may be formed on the main surface 1s.

[0024] As shown in FIG. 1 , the direction perpendicular to the main surface 1s is defined as the first direction X. The base layer 2 has a base layer surface 2s. The base layer surface 2s is the surface opposite to the surface of the base layer 2 that is in contact with the main surface 1s. The distance H in the first direction from the main surface 1s to the base layer surface 2s (thickness H of the base layer 2) may be 1 μm or less or 0.5 μm or less. As will be described later, if the thickness H of the base layer 2 is 1 μm or less, the fine line formability of the laminate portion 20 is improved. As a result, the circuit of the printed wiring board 200 can be miniaturized.

[0025] (Method for manufacturing substrate for printed wiring board) A method for manufacturing the substrate for printed wiring board 100a will be described below. Fig. 2 is a flowchart illustrating the method for manufacturing the substrate for printed wiring board 100a. As shown in Fig. 2, the method for manufacturing the substrate for printed wiring board 100a includes a step S1a of preparing a base film 1 and a step S2a of forming an underlayer 2.

[0026] The step S2a of forming the underlayer is performed after the step S1a of preparing the base film 1.

[0027] 3 is a cross-sectional view illustrating step S1a of preparing the base film 1. In step S1a of preparing the base film 1, the base film 1 is prepared as shown in Fig. 3. In step S1a of preparing the base film 1, the underlayer 2 is not disposed on the main surface 1s of the prepared base film 1.

[0028] Before the underlayer 2 is disposed on the principal surface 1s, the principal surface 1s is subjected to, for example, an alkali treatment and an excimer treatment. If the base film 1 is made of, for example, polyimide, the alkali treatment causes the polyimide to hydrolyze. As a result, carboxyl groups are formed on the principal surface 1s, making the base film 1 hydrophilic. If the principal surface 1s is then copper-metallized by applying a paste or electroless plating, copper is layered on the principal surface 1s without distortion of the crystal grains.

[0029] To further enhance the hydrophilicity of the principal surface 1s, the principal surface 1s may be subjected to an excimer treatment after the alkali treatment. Specifically, the principal surface 1s is irradiated with excimer light. The wavelength of the excimer light is, for example, 172 nm. In this way, distortion of the crystal grains is further suppressed.

[0030] FIG. 4 is a cross-sectional view illustrating step S2a of forming the underlayer 2. In step S2a of forming the underlayer 2, as shown in FIG. 4, the underlayer 2 is formed on the main surface 1s. In this step S2a, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to form the underlayer 2. The underlayer 2 may be formed by sputtering. The underlayer 2 may be formed using a plating apparatus 300 described below. After the underlayer 2 is formed using the plating apparatus 300, the printed wiring board substrate 100a is annealed for 1 hour at an annealing temperature of 300°C in an inert gas atmosphere such as nitrogen.

[0031] As described above, the printed wiring board substrate 100a shown in FIG. 1 is manufactured. In the printed wiring board substrate 100a manufactured in this manner, the segregation rate of the {111} plane as viewed from the first direction X in the base layer 2 is suppressed. The electroplated layer 3 grows at a high rate. Therefore, as shown in FIG. 18 , when the electroplated layer 3 is formed on the base layer surface 2s, the electroplated layer 3 grows uniformly regardless of the segregation rate of the {111} plane of the printed wiring board substrate 100a. As described below, the etching solution used in the semi-additive process is generally a sulfuric acid-hydrogen peroxide etching solution. In a sulfuric acid-hydrogen peroxide etching solution, the etching rate of the {111} plane is slower than the etching rates of other crystal orientations. Therefore, when manufacturing the printed wiring board 200, if the {111} plane is segregated in the laminate portion 20, the rectangularity of the laminate portion 20 will be deteriorated. The laminate portion 20 consists of the electroplated layer 3 and the base layer 2. However, when manufacturing the printed wiring board 200 using the printed wiring board substrate 100a according to the first embodiment, the etching rate of the laminate portion 20 in the first direction X is uniform because the segregation rate of the {111} plane of the printed wiring board substrate 100a is suppressed. As a result, the laminate portion 20 is formed with excellent rectangularity. In this way, the printed wiring board 200 according to the second embodiment, which will be described later, is obtained.

[0032] As described below, the {111} plane segregation rate of the printed wiring board substrate 100 is measured by electron backscattered diffraction (EBSD). Specifically, for example, as shown in FIG. 18 , when a laminate 20 is formed to include an electrolytic plated layer 3 and an underlayer 2, the electrolytic plated layer 3 contacts the underlayer 2. The laminate 20 has a first surface 21s. The first surface 21s is positioned so that the height Ht of the laminate from the main surface 1s to the first surface 21s is 1 μm or more. Before measuring the {111} plane segregation rate by EBSD, the printed wiring board substrate 500 having the laminate 20 formed thereon is cross-sectionally processed by argon ion polishing. The ion beam acceleration voltage is set to, for example, 6 kV. Next, the segregation rate of the {111} plane as viewed from the first direction X in region V1 shown in FIG. 18 is measured by EBSD. The segregation rate of the {111} plane is measured using a Germini 450 manufactured by ZEISS and a Symmetry manufactured by Oxford. The EBSD measurement conditions are as follows: the acceleration voltage is 15 kV; the electron beam irradiation current is 20 nA; the electron beam integration time is 0.8 ms; the tilt angle of the SEM stage is 70°; and the SEM working distance (WD) is 15 mm. In a region V1 in the cross section of the laminated portion 20, from the main surface 1 s to 1 μm, the first value A1 and the second value A2 satisfy the following formula E1. Region V1 is the region surrounded by the dotted line shown in FIG. 18. Formula E1 is A1 / A2≦0.15. The first value A1 is the area occupied by the {111} plane when viewed from the first direction X in region V1. The second value A2 is the area obtained by subtracting the area occupied by the {111} plane when viewed from the first direction X in region V1 (first value A1) from the area of ​​region V1. The formula E1 may be A1 / A2≦0.15. From a different perspective, crystal grains oriented in the {111} plane when viewed from the first direction are defined as first crystal grains. The crystal grains oriented in the {111} plane are crystal grains oriented in a plane within a measurement tolerance of 10° from the {111} plane.When the crystal grains other than the crystal grains oriented in the {111} plane are defined as second crystal grains, the ratio (A1 / A2) of the occupied area of ​​the first crystal grains to the occupied area of ​​the second crystal grains is 0.15 or less. The second crystal grains include randomly oriented crystal grains.

[0033] (Configuration of a Modified Printed Wiring Board Substrate) FIG. 5 is a cross-sectional view of a modified printed wiring board substrate 100a according to embodiment 1. FIG. 5 corresponds to FIG. 1. The printed wiring board substrate 100b shown in FIG. 5 has a configuration similar to that of the printed wiring board substrate 100a shown in FIG. 1, but differs in that the base layer 2 includes an electroless copper plating layer. Specifically, the base layer 2 includes a first base layer 2a and a second base layer 2b. The first base layer 2a is specifically composed of either a sputtered copper layer or a nano-copper sintered body layer. The first base layer 2a has an intermediate base layer surface s. In the first base layer 2a, the intermediate base layer surface s is the surface opposite the main surface 1s. The second base layer 2b is in contact with the first base layer 2a at the intermediate base layer surface s. The second base layer 2b is, for example, a copper layer formed by electroless plating. In this manner, the base layer 2 is formed.

[0034] The distance Ha in the first direction X from the main surface 1s to the intermediate underlayer surface s (thickness Ha of the first underlayer 2a) may be 0.5 μm or less, or 0.1 μm or less.

[0035] The underlayer 2 does not necessarily have to include the first underlayer 2a. Specifically, the underlayer 2 may be composed of only the second underlayer 2b made of an electroless copper plating layer.

[0036] (Method for Manufacturing a Substrate for a Printed Wiring Board) A method for manufacturing the substrate for a printed wiring board 100b will be described below.

[0037] Fig. 6 is a flowchart illustrating a method for manufacturing the substrate 100b for printed wiring boards. Fig. 6 corresponds to Fig. 2. As shown in Fig. 6, the method for manufacturing the substrate 100b for printed wiring boards includes a step S1b of preparing a base film 1, a step S2b of forming a first underlayer 2a, a step S3b of forming a second underlayer 2b, and a step S4b of annealing the substrate 100b for printed wiring boards.

[0038] Step S2b of forming the first underlayer 2a is performed after step S1b of preparing the base film 1. Step S3b of forming the second underlayer 2b is performed after step S2b of forming the first underlayer 2a. Step S4b of annealing the printed wiring board substrate 100b is performed after step S3b of forming the second underlayer 2b.

[0039] 7 is a cross-sectional view illustrating step S1b of preparing a base film 1. In step S1b of preparing a base film 1, the base film 1 is prepared as shown in FIG. The base film 1 prepared in step S1b of preparing a base film 1 does not have an underlayer 2 disposed on the main surface 1s. Before disposing the underlayer 2, the main surface 1s is subjected to an alkali treatment and an excimer treatment.

[0040] 8 is a cross-sectional view illustrating step S2b of forming the first underlayer 2a. In step S2b of forming the first underlayer 2a, as shown in FIG. 8, the first underlayer 2a is formed on the main surface 1s. In this step S2b, first, a paste containing copper particles is applied to the main surface 1s. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to each other, and the first underlayer 2a is formed. The first underlayer 2a may be formed by sputtering. Note that step S2b of forming the first underlayer 2a does not necessarily have to be performed.

[0041] The step S3b of forming the second underlayer 2b is performed using a plating apparatus 300. Fig. 9 is a schematic diagram of the plating apparatus 300 used in the step S3b of forming the second underlayer 2b. As shown in Fig. 9, the plating apparatus 300 includes a plating treatment tank 310, a plurality of rollers 320, electrode rollers 331 and 332, and a power source 340.

[0042] A plating solution is stored in the plating tank 310. The plating solution contains copper. The plating solution may also contain nickel. An electrode 311 is disposed inside the plating tank 310. The electrode 311 is made of a conductive material. The electrode 311 is made of titanium, for example. The electrode 311 is immersed in the plating solution.

[0043] The rollers 320 are aligned along the transport direction (see the arrow in FIG. 9 ) of the base film 1. The base film 1 is transported along the transport direction by rotating the rollers 320. During the transport process, the base film 1 passes through a plating solution stored in a plating treatment tank 310.

[0044] The electrode rollers 331 and 332 are disposed at positions where they come into contact with the base film 1 before it passes through the plating solution. At least one of the electrode rollers 331 and 332 comes into contact with the first underlayer 2 a. The electrode rollers 331 and 332 are made of, for example, stainless steel.

[0045] The power supply 340 is electrically connected to the electrode 311 and the electrode rollers 331 and 332. More specifically, the positive pole of the power supply 340 is electrically connected to the electrode 311, and the negative pole of the power supply 340 is electrically connected to the electrode rollers 331 and 332.

[0046] 10 is a cross-sectional view illustrating step S3b of forming the second underlayer 2b. In step S3b of forming the second underlayer 2b, a power source 340 applies current between the electrode 311 and the electrode rollers 331 and 332. As shown in FIG. 10 , driven by the electrical energy generated by this current application, the second underlayer 2b is rapidly formed on the surface (intermediate underlayer surface s) of the first underlayer 2a. Thereafter, the current application between the electrode 311 and the electrode rollers 331 and 332 is stopped.

[0047] Next, step S4b is performed to anneal the printed wiring board substrate 100b. Specifically, the printed wiring board substrate 100b is annealed at an annealing temperature of 300° C. for 1 hour in an inert gas atmosphere such as nitrogen. As a result, the underlayer 2 is fixed to the base film 1.

[0048] 5 is manufactured. In the printed wiring board substrate 100b manufactured in this manner, similar to the printed wiring board substrate 100a, the base layer 2 is formed with a suppressed segregation rate of the {111} plane as viewed from the first direction X.

[0049] (Effects) A printed wiring board substrate 100 according to the present disclosure includes a base film 1 and an underlayer 2. The base film 1 has a main surface 1s. The underlayer 2 is in contact with the main surface 1s. The direction perpendicular to the main surface 1s is defined as a first direction X. An electrolytic plating layer 3 is formed on the underlayer 2 so that the total thickness of the underlayer 2 and the electrolytic plating layer 3 is 1 μm or more. When a cross section of the underlayer 2 and the electrolytic plating layer 3 is measured by electron backscatter diffraction, crystal grains oriented in the {111} plane as viewed from the first direction in a region V1 extending 1 μm from the main surface 1s are defined as first crystal grains. The crystal grains oriented in the {111} plane are crystal grains oriented in a plane within a measurement tolerance of 10° from the {111} plane. When the crystal grains other than the crystal grains oriented in the {111} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

[0050] In this way, the segregation rate of the {111} plane of the printed wiring board substrate 100b is suppressed, and therefore the etching rate of the laminate portion 20 in the first direction X becomes uniform when the electrolytic plating layer 3 is formed. As a result, it is possible to obtain the printed wiring board substrate 100 in which the laminate portion 20 having excellent rectangularity is formed.

[0051] (Configuration of Printed Wiring Board) The following describes the configuration of printed wiring board 200. Fig. 11 is a cross-sectional view of printed wiring board 200. As shown in Fig. 11, printed wiring board 200 includes base film 1 and a plurality of laminated portions 20.

[0052] The direction perpendicular to the main surface 1s is defined as a first direction X. The direction perpendicular to the first direction X is defined as a second direction Y. The direction perpendicular to the first direction X and the second direction Y is defined as a third direction Z.

[0053] The plurality of laminated portions 20 are arranged on the main surface 1s. The plurality of laminated portions 20 are formed so as to extend linearly along the second direction Y. The plurality of laminated portions 20 are arranged at equal intervals in the third direction Z. If the shortest distance S between two adjacent laminated portions 20 in the third direction Z and the width L of each of the plurality of laminated portions 20 are less than 2 μm, it will take a long time to form the resist pattern 4 in the step S5 of forming the resist pattern 4, which will be described later. Therefore, as shown in FIG. 11 , the shortest distance S between two adjacent laminated portions 20 in the third direction Z may be 2 μm or more. The width L of each of the plurality of laminated portions 20 may be 2 μm or more.

[0054] Specifically, the plurality of laminated units 20 include adjacent first laminated units 20 a and second laminated units 20 b. The shortest distance S in the third direction Z from the first laminated unit 20 a to the second laminated unit 20 b may be 2 μm or more. The shortest distance S in the third direction Z from the first laminated unit 20 a to the second laminated unit 20 b may be 15 μm or less, or may be 10 μm or less.

[0055] The width L of each of the plurality of laminated portions 20 may be 15 μm or less, or may be 10 μm or less. Specifically, the width L of each of the first laminated portion 20 a and the second laminated portion 20 b may be 15 μm or less, or may be 10 μm or less.

[0056] The laminated portion 20 includes an underlayer 2 and an electrolytically plated layer 3. The underlayer 2 is in contact with the main surface 1s. The electrolytically plated layer 3 is in contact with the underlayer 2. The electrolytically plated layer 3 is a copper layer formed by electrolytic plating.

[0057] (Method for Manufacturing Printed Wiring Board) A method for manufacturing the printed wiring board 200 will be described below.

[0058] 12 is a flowchart illustrating a method for manufacturing the printed wiring board 200. The printed wiring board 200 is basically manufactured using a semi-additive process. Specifically, as shown in FIG. 12 , the method for manufacturing the printed wiring board 200 includes a step S5 of forming a resist pattern 4, a step S6 of forming an electrolytic plating layer 3, a step S7 of removing the resist pattern 4, and a step S8 of removing the base layer 2.

[0059] First, step S5 of forming a resist pattern 4 is carried out. In step S5, the resist pattern 4 is formed on the base layer 2. Any method such as photolithography can be used to form the resist pattern 4. Step S6 of forming an electrolytic plated layer 3 is carried out after step S5 of forming the resist pattern 4. Step S7 of removing the resist pattern 4 is carried out after step S6 of forming the electrolytic plated layer 3. Step S8 of removing the base layer 2 is carried out after step S7 of removing the resist pattern 4. The printed wiring board 200 is manufactured using the printed wiring board substrate 100a or the printed wiring board substrate 100b according to the first embodiment.

[0060] 13 is a cross-sectional view illustrating step S5 of forming a resist pattern 4. In step S5 of forming a resist pattern 4, the resist pattern 4 is formed on the underlayer 2 as shown in FIG.

[0061] The resist pattern 4 has openings 4a. The openings 4a are regions where the resist pattern 4 is not formed. The underlying layer 2 is exposed from the openings 4a.

[0062] In step S5 of forming the resist pattern 4, first, a resist in the form of, for example, a film is applied onto the underlayer 2. Second, the resist placed on the underlayer 2 is exposed and developed. As a result, the remaining part of the resist that has not been removed becomes the resist pattern 4, and the removed part of the resist becomes the opening 4a.

[0063] 14 is a cross-sectional view illustrating step S6 of forming the electrolytic plated layer 3. In step S6 of forming the electrolytic plated layer 3, the electrolytic plated layer 3 is formed on the base layer 2 exposed from the opening 4a, as shown in FIG. 14. The electrolytic plated layer 3 is formed by passing a current through the base layer 2 in a plating solution containing copper.

[0064] 15 is a cross-sectional view illustrating step S7 of removing resist pattern 4. In step S7 of removing resist pattern 4, as shown in Fig. 15, resist pattern 4 is removed from underlayer 2. As a result, underlayer 2 is exposed between two adjacent electroplated layers 3.

[0065] In step S8 of removing the underlayer 2, the portion of the underlayer 2 exposed between two adjacent electroplated layers 3 is removed by etching. Specifically, the underlayer 2 is removed using a sulfuric acid-hydrogen peroxide etching solution. The etching rate varies depending on the crystal orientation segregated in the underlayer 2. Specifically, the closer to the {111} crystal orientation, the slower the etching rate. On the other hand, the closer to the {001} crystal orientation, the faster the etching rate. Therefore, if the {111} crystal orientation is segregated in the underlayer 2, etching will also progress on the side surface 20s of the laminate 20 before the underlayer 2 is etched down to the main surface 1s. As a result, the laminate 20 will have poor rectangularity. By using the printed wiring board substrate 100 according to embodiment 1, the segregation rate of the {111} crystal orientation in the underlayer 2 is suppressed. Therefore, the underlayer 2 is quickly etched, resulting in a laminate 20 with excellent rectangularity.

[0066] As a result of the above, a printed wiring board 200 having the structure shown in FIG. 11 is formed.

[0067] As described below, the segregation rate of the {111} plane of the printed wiring board 200 is measured by EBSD. Specifically, the laminate 20 includes an underlayer 2 and an electrolytic plated layer 3. The underlayer 2 is in contact with the main surface 1s. The electrolytic plated layer 3 is in contact with the underlayer 2. In a cross section of the laminate 20, in a region V1 extending 1 μm from the main surface 1s, a first value A1 and a second value A2 satisfy the following formula E1. Formula E1 satisfies A1 / A2≦0.15. The first value A1 is the area occupied by the {111} plane in the region V1 as viewed from the first direction X. The second value A2 is the area obtained by subtracting the area occupied by the {111} plane in the region V1 as viewed from the first direction X (first value A1) from the area in the region V1 (specifically, the area of ​​the laminate 20 in the region V1). Formula E1 may also satisfy A1 / A2≦0.05. Region V1 is the region shown in Figure 16. From a different perspective, crystal grains oriented in the {111} plane when viewed from a first direction are defined as first crystal grains. Crystal grains oriented in the {111} plane are crystal grains oriented in a plane within a measurement tolerance of 10° from the {111} plane. When crystal grains other than those oriented in the {111} plane are defined as second crystal grains, the ratio (A1 / A2) of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less. The second crystal grains include randomly oriented crystal grains.

[0068] FIG. 17 is a schematic cross-sectional view of the laminate 20 shown in region XVII of FIG. 11 . The width of the laminate 20 may vary in the first direction X depending on the segregation rate of the {111} plane in the underlayer 2. The rectangularity of the laminate 20 is evaluated using a rectangularity evaluation index Et. Specifically, in a cross section of the laminate 20 perpendicular to the second direction Y, the laminate 20 has a first surface 21s, a second surface 22s, a minimum surface 23s, a maximum surface 24s, and two side surfaces 20s. The first surface 21s is the surface of the laminate 20 farthest from the main surface 1s in the first direction X. The second surface 22s is the surface of the laminate 20 in contact with the main surface 1s. The two side surfaces 20s connect the first surface 21s and the second surface 22s. The minimum surface 23s and the maximum surface 24s may be surfaces located between the first surface 21s and the second surface 22s. The minimum surface 23s and the maximum surface 24s may be surfaces along the main surface 1s. The minimum surface 23s has a minimum width W3. The minimum width W3 is the smallest width in the third direction Z of the stacked portion 20 in the third direction Z. Depending on the etching conditions, the first surface 21s may become the minimum surface 23s. The maximum surface 24s has a maximum width W4. The maximum width W4 is the largest width in the third direction Z of the stacked portion 20 in the third direction Z. Depending on the etching conditions, the second surface 22s may become the maximum surface 24s. In this case, if the rectangularity evaluation index is Et, then Et = W3 / W4.

[0069] The value obtained by dividing the maximum width W4 from the minimum width W3 (i.e., rectangularity evaluation index Et) is 0.8 or more. The rectangularity evaluation index Et may be 0.9 or more. In this manner, the rectangularity of the laminated portion 20 is evaluated.

[0070] The rectangularity of the laminated unit 20 may be evaluated from another perspective. Specifically, the rectangularity of the laminated unit 20 may be evaluated by either the recess amount L1 or the protrusion amount L2. Depending on the segregation rate of the {111} plane in the underlayer 2, the shape of the side surface 20s of the laminated unit 20 may be a V-shape that protrudes inward. Specifically, at least one of the two side surfaces 20s may include a first point p1 and a first recessed point p3a. The first point p1 is the point where the side surface 20s and the first surface 21s intersect. On the side surface 20s, the first recessed point p3a is located on the side where the first surface 21s is located in the third direction Z, as viewed from the first point p1. The first recessed point p3a is located at a position that is the longest distance from the first point p1 in the third direction Z. From a different perspective, the first recessed point p3a is located at a position that overlaps with the first surface 21s in a plan view viewed from the first direction X. At this time, the recess amount L1 is expressed as L1=l1 / Ht, where l1 is the distance in the third direction Z from the first point p1 to the first recessed point p3a.

[0071] The distance l1 in the third direction Z from the first point p1 to the first recessed point p3a may be 0.15 times or less, 0.10 times or less, or 0.05 times or less of the height Ht of the stacked portion 20 from the main surface 1s to the first surface 21s. Specifically, the recess depth L1 is 0.15 or less. The recess depth L1 may be 0.10 times or less, or 0.05 times or less.

[0072] At least one of the two side surfaces 20s may include a second point p2 and a second recessed point p3b. The second point p2 is the point where the side surface 20s and the second surface 22s intersect. On the side surface 20s, the second recessed point p3b is located on the side where the second surface 22s is located in the third direction Z as viewed from the second point p2. The second recessed point p3b is located at the position that is the longest distance from the second point p2 in the third direction Z. In this case, the protrusion amount L2 is L2 = l2 / Ht. The distance l2 is the distance in the third direction Z from the second point p2 to the second recessed point p3b. The first recessed point p3a is a point for evaluating the recess amount L1, and the second recessed point p3b is a point for evaluating the protrusion amount L2. Furthermore, when the shape of the laminated portion 20 is symmetrical, the first recessed point p3a and the second recessed point p3b on the two side surfaces 20s are arranged at positions that are linearly symmetrical about the central axis (axis of symmetry) of the laminated portion 20.

[0073] The distance l2 in the third direction Z from the second point p2 to the second recessed point p3b may be 0.15 times or less, 0.10 times or less, or 0.05 times or less the height Ht of the stacked portion 20 from the main surface 1s to the first surface 21s. Specifically, the protrusion amount L2 is 0.15 or less. The protrusion amount L2 may be 0.10 or less, or 0.05 or less.

[0074] (Effects) A printed wiring board 200 according to the present disclosure includes a base film 1 and a laminate portion 20. The base film 1 has a main surface 1s. The laminate portion 20 is disposed on the main surface 1s. The laminate portion 20 includes an underlayer 2 and an electroplated layer 3. The underlayer 2 is in contact with the main surface 1s. The electroplated layer 3 is in contact with the underlayer 2. A direction perpendicular to the main surface 1s is defined as a first direction X. When a cross section of the laminate portion 20 is measured by electron backscatter diffraction, crystal grains oriented in the {111} plane as viewed from the first direction in a region V1 1 μm from the main surface 1s are defined as first crystal grains. Crystal grains oriented in the {111} plane are crystal grains oriented in a plane within a measurement tolerance of 10° from the {111} plane. When the crystal grains other than the crystal grains oriented in the {111} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

[0075] In this way, the segregation rate of the {111} plane is suppressed when the electrolytic plating layer 3 is formed on the base layer 2. As a result, the laminated portion 20 has excellent rectangularity. In other words, the printed wiring board 200 having a fine circuit can be obtained.

[0076] In the printed wiring board 200, the direction perpendicular to the first direction X is defined as the second direction Y. The direction perpendicular to the first direction X and the second direction Y is defined as the third direction Z. The laminated portion 20 is formed to extend linearly along the second direction Y. The laminated portion 20 includes adjacent first laminated portions 20a and second laminated portions 20b. The widths of the first laminated portion 20a and the second laminated portion 20b are each 15 μm or less. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 15 μm or less.

[0077] In this way, a printed wiring board 200 having a fine circuit can be obtained.

[0078] In the printed wiring board 200, the width of each of the first laminated portion 20a and the second laminated portion 20b is 10 μm or less. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 10 μm or less. The width of each of the first laminated portion 20a and the second laminated portion 20b may be 6 μm or less. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b may be 6 μm or less.

[0079] In this way, a printed wiring board 200 having a fine circuit can be obtained.

[0080] In the printed wiring board 200, the width of each of the first laminated portion 20a and the second laminated portion 20b is 2 μm or more. The shortest distance S in the third direction Z from the first laminated portion 20a to the second laminated portion 20b is 2 μm or more.

[0081] In this way, a printed wiring board 200 having a fine circuit can be obtained.

[0082] In the cross section of the printed wiring board 200, the laminated portion 20 has a maximum width W4 and a minimum width W3. The value obtained by dividing the minimum width W3 by the maximum width W4 is 0.8 or more.

[0083] In this manner, a laminated portion 20 having excellent rectangularity is formed. In the printed wiring board 200, the laminated portion 20 has a first surface 21s and two side surfaces 20s in a cross section. The first surface 21s is the surface farthest from the main surface 1s in the first direction X. The two side surfaces 20s connect the first surface 21s and the main surface 1s. At least one of the two side surfaces 20s includes a first point p1 and a first recessed point p3a. The first point p1 is the point where the side surface 20s and the first surface 21s intersect. The first recessed point p3a is located at a position where the distance l1 from the first point p1 in the third direction Z is the longest. The distance l1 from the first point p1 to the first recessed point p3a in the third direction Z is 0.15 times or less of the height Ht from the main surface 1s to the first surface 21s. The distance l1 may be equal to or less than 0.10 times the height Ht, or may be equal to or less than 0.05 times the height Ht.

[0084] In this manner, a laminated portion 20 having excellent rectangularity is formed. In the printed wiring board 200, the laminated portion 20 has, in cross section, a first surface 21s, a second surface 22s, and two side surfaces 20s. The first surface 21s is the surface farthest from the main surface 1s in the first direction X. The two side surfaces 20s connect the first surface 21s and the main surface 1s. The laminated portion 20 contacts the main surface 1s at the second surface 22s. At least one of the two side surfaces 20s includes a second point p2 and a second recessed point p3b. The second point p2 is the point where the side surface 20s and the second surface 22s intersect. The second recessed point p3b is located at a position where the distance l2 from the second point p2 in the third direction Z is longest. The distance l2 in the third direction Z from the second point p2 to the second recessed point p3b is 0.15 times or less the height Ht from the main surface 1s to the first surface 21s. The distance l2 may be 0.10 times or less, or 0.05 times or less, the height Ht.

[0085] In this way, laminated portion 20 having excellent rectangularity is formed. In printed wiring board 200, thickness H of base layer 2 is 1 μm or less.

[0086] In this way, a printed wiring board 200 can be obtained in which the thin line formability of the laminated portion 20 can be improved.

[0087] In order to verify the effects of the above-described substrate 100 for a printed wiring board and the printed wiring board 200 manufactured from the substrate 100 for a printed wiring board, the following measurements were carried out.

[0088] (Sample Preparation) First, a substrate 500 for printed wiring boards is prepared, in which the material constituting the base film 1 is polyimide. The substrates 500 for printed wiring boards in Samples 1 to 6 are comparative examples. The substrates 500 for printed wiring boards in Samples 7 to 11 are examples. The manufacturing conditions and evaluation results of the substrates 500 for printed wiring boards shown in Samples 1 to 11 are shown in Tables 1 to 3.

[0089]

[0090]

[0091]

[0092] The printed wiring board substrate 500 in Sample 1 was not subjected to alkali treatment or excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a Ni—Cr seed layer and a sputtered copper layer as the first base layer 2a, and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.006 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.355 μm. The thickness H of the base layer 2 was 0.361 μm. The thickness of the second base layer 2b was the thickness H of the base layer 2 minus the thickness Ha of the first base layer 2a. After the electroless copper plating layer was formed, annealing was not performed.

[0093] The printed wiring board substrate 500 in Sample 2 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.034 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.225 μm. The thickness H of the base layer 2 was 0.259 μm. After the electroless copper plating layer was formed, annealing was not performed.

[0094] The printed wiring board substrate 500 of Sample 3 was subjected to excimer treatment as a pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.041 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.223 μm. The thickness H of the base layer 2 was 0.264 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0095] The printed wiring board substrate 500 in Sample 4 was subjected to alkali treatment as a pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.026 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.185 μm. The thickness H of the base layer 2 was 0.211 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0096] The printed wiring board substrate 500 of Sample 5 was subjected to excimer treatment as a pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of an electroless copper plating layer. The thickness H of the base layer 2 was 1.150 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300° C. for 1 hour.

[0097] The printed wiring board substrate 500 in Sample 6 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.400 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 2.180 μm. The thickness H of the base layer 2 was 2.580 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0098] The printed wiring board substrate 500 of Sample 7 was subjected to alkali treatment and excimer treatment as pretreatment. The base layer 2 of the printed wiring board substrate 500 was composed of an electroless copper plating layer. The thickness H of the base layer 2 was 0.452 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300° C. for 1 hour.

[0099] The printed wiring board substrate 500 of Sample 8 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a sputtered copper layer. The thickness H of the base layer 2 was 0.070 μm. After the base layer 2 was formed, annealing was not performed.

[0100] The printed wiring board substrate 500 of Sample 9 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer. The thickness H of the base layer 2 was 0.155 μm. Because an electroless copper plating layer was not formed, annealing was not performed after the formation of the base layer 2.

[0101] The printed wiring board substrate 500 in Sample 10 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.156 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.130 μm. The thickness H of the base layer 2 was 0.286 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0102] The printed wiring board substrate 500 in Sample 11 was subjected to alkali treatment and excimer treatment as pretreatments. The base layer 2 of the printed wiring board substrate 500 was composed of a nano-copper sintered body layer as the first base layer 2a and an electroless copper plating layer as the second base layer 2b. The thickness Ha of the first base layer 2a was 0.195 μm. The electroless copper plating layer as the second base layer 2b was formed to a thickness of 0.672 μm. The thickness H of the base layer 2 was 0.867 μm. After the electroless copper plating layer was formed, annealing was performed. Specifically, annealing was performed in an inert gas atmosphere such as nitrogen at an annealing temperature of 300°C for 1 hour.

[0103] By forming an electrolytic plating layer 3 on each of the samples 1 to 11 prepared as described above, a printed wiring board substrate 500 having a laminated portion 20 formed thereon as shown in FIG. 18 is prepared.

[0104] <Evaluation of the Segregation Ratio of the {111} Plane> The segregation ratio of the {111} plane as viewed from the first direction X was evaluated using printed wiring board substrates 500 of Samples 1 to 11. Fig. 18 is a cross-sectional view of printed wiring board substrate 500 on which electrolytic plating layer 3 is formed, showing measurement area V1 of the crystal orientation distribution. The segregation ratio of the {111} plane of printed wiring board substrate 500 was measured by EBSD.

[0105] Before measuring the segregation rate of the {111} plane by EBSD, the cross section of the printed wiring board substrate 500 having the electrolytic plating layer 3 formed thereon is processed by argon ion polishing. The acceleration voltage of the ion beam is set to, for example, 6 kV.

[0106] Next, the segregation rate of the {111} plane as viewed from the first direction X in region V1 shown in FIG. 18 is measured by EBSD. The segregation rate of the {111} plane is measured using a Germini 450 manufactured by ZEISS and a Symmetry manufactured by Oxford. The EBSD measurement conditions are as follows: the acceleration voltage is 15 kV; the electron beam irradiation current is 20 nA; the electron beam integration time is 0.8 ms; the tilt angle of the SEM stage is 70°; and the working distance (WD) of the SEM is 15 mm.

[0107] The first value A1 is the area occupied by the {111} plane as viewed from the first direction X in region V1. Deviations of up to 10° from the {111} plane are considered to be errors, and orientation distributions within 10° from the {111} plane are determined as {111} planes. The second value A2 is the area obtained by subtracting the area occupied by the {111} plane as viewed from the first direction X in region V1 (first value A1) from the area of ​​stacked portion 20 in region V1 in the cross section shown in FIG. 18 . When the first value A1 and the second value A2 satisfy the formula (A1 / A2≦0.05) for the segregation rate of the {111} plane as viewed from the first direction X in region V1, the evaluation of the segregation rate of the {111} plane in Table 1 is recorded as A. When the first value A1 and the second value A2 satisfy the formula (0.05<A1 / A2≦0.15), the segregation rate of the {111} plane is evaluated as B in Table 1. When the first value A1 and the second value A2 satisfy the formula (0.15<A1 / A2≦0.35), the segregation rate of the {111} plane is evaluated as C in Table 1. When the first value A1 and the second value A2 satisfy the formula (0.35<A1 / A2), the segregation rate of the {111} plane is evaluated as D in Table 1.

[0108] In Sample 1, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.61. In Sample 1, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.32. In Sample 3, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.28. In Sample 4, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.19. In Sample 5, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.22. In Sample 6, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.39.

[0109] In Sample 7, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.14. In Sample 8, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.12. In Sample 9, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.04. In Sample 10, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.02. In Sample 11, the ratio of the occupied area of ​​the {111} plane (A1 / A2) was 0.07.

[0110] From the ratio (A1 / A2) of the occupied area of ​​the {111} plane in Samples 1 to 11, as shown in Tables 1 to 3, the segregation rate of the {111} plane in Samples 1 to 6 is evaluated as C or D. On the other hand, the segregation rate of the {111} plane in Samples 7 to 11 is evaluated as A or B. In particular, the segregation rate of the {111} plane in Samples 9 and 10 is evaluated as A.

[0111] That is, when an electroless copper plating layer is not formed on the underlayer 2, the segregation rate of the {111} plane is suppressed if the pretreatment involves alkali treatment and excimer treatment, and the thickness H of the underlayer 2 is 1 μm or less. Alternatively, when the underlayer 2 includes an electroless copper plating layer, the pretreatment involves alkali treatment and excimer treatment, and after the electroless copper plating layer is formed, annealing is performed under certain conditions, and the thickness H of the underlayer 2 is 1 μm or less, the segregation rate of the {111} plane is suppressed.

[0112] When neither alkali treatment nor excimer treatment was performed in the pretreatment, the segregation rate of the {111} plane was evaluated as D, as in Sample 1. When only either alkali treatment or excimer treatment was performed in the pretreatment, the segregation rate of the {111} plane was evaluated as C, as in Samples 3 and 4. When the base layer 2 includes an electroless copper plating layer and annealing is not performed on the printed wiring board substrate 500 after forming the electroless copper plating layer, the segregation rate of the {111} plane was evaluated as C, as in Sample 2. When the thickness H of the base layer 2 exceeds 1 μm, the segregation rate of the {111} plane was evaluated as C or D, as in Samples 5 and 6.

[0113] As will be described later, when evaluating the segregation rate of the {111} plane for printed wiring board 200 on which wiring is formed, the target region for the above-described measurement is region V1 shown in FIG.

[0114] FIG. 19 shows the crystal orientation distribution in the laminated portion 20 of Sample 1. FIG. 20 shows the crystal orientation distribution in the laminated portion 20 of Sample 7. The orientation distributions shown in FIGS. 19 and 20 are inverse pole figure orientation maps (IPF maps) measured by EBSD. In FIGS. 19 and 20, the images are binarized with black and gray. Specifically, the black areas correspond to the {111} planes. As shown in FIG. 19, it can be seen that there are many {111} planes near the underlayer 2 in Sample 1. On the other hand, as shown in FIG. 20, it can be seen that there is no particular plane that is more prevalent near the underlayer 2 in Sample 7.

[0115] <Evaluation of Rectangularity of Laminated Portion> When printed wiring boards 200 were manufactured using printed wiring board substrates 500 of Samples 1 to 11, the rectangularity of laminated portion 20 was evaluated.

[0116] The rectangularity of the laminated portion 20 is evaluated using a rectangularity evaluation index Et. As shown in FIG. 17 , the minimum surface 23s and the maximum surface 24s may be surfaces located between the first surface 21s and the second surface 22s. The minimum surface 23s has a minimum width W3. The minimum width W3 is the smallest width of the laminated portion 20 in the third direction Z. The maximum surface 24s has a maximum width W4. The maximum width W4 is the largest width of the laminated portion 20 in the third direction Z. Depending on the etching conditions, the first surface 21s may become the minimum surface 23s. Depending on the etching conditions, the second surface 22s may become the maximum surface 24s. In this case, when the rectangularity evaluation index is Et, Et = W3 / W4.

[0117] When the rectangularity evaluation index Et is 0.9 or more, the rectangularity of the laminated portion is evaluated as A. When the rectangularity evaluation index Et is 0.8 or more and less than 0.9, the rectangularity of the laminated portion is evaluated as B. When the rectangularity evaluation index Et is 0.7 or more and less than 0.8, the rectangularity of the laminated portion is evaluated as C. When the rectangularity evaluation index Et is less than 0.7, the rectangularity of the laminated portion is evaluated as D.

[0118] As shown in Tables 1 to 3, in Samples 1 to 6, the rectangularity of the laminated portion 20 was evaluated as C or D. On the other hand, in Samples 7 to 11, the rectangularity of the laminated portion 20 was evaluated as A or B. In particular, in Samples 9 and 10, the rectangularity of the laminated portion 20 was evaluated as A. This is largely due to the influence of the segregation rate of the {111} plane, as will be described later.

[0119] FIG. 21 shows the crystal orientation distribution in the laminate 20 of Sample 1. FIG. 22 shows the crystal orientation distribution in the laminate 20 of Sample 7. In FIGS. 21 and 22, the diagrams are binarized with black and gray. Specifically, the black areas correspond to the {111} planes. As shown in FIG. 21, in Sample 1, the width of the laminate 20 in the third direction Z is not uniform in the first direction X. In particular, the width of the laminate 20 in the third direction Z on the main surface 1s side is larger than the width in the third direction Z on the opposite side of the main surface 1s. This is because, as shown in FIG. 21, there are many {111} planes near the underlayer 2 in Sample 1. That is, the etching rate decreases in the region where the {111} planes are segregated, and as the etching time passes, the first surface 21s side (see FIG. 17), which is the top surface side of the laminate 20, is etched. On the other hand, in sample 7, the base layer 2 does not have a large number of specific surfaces, so the base layer 2 and the electroplated layer 3 are uniformly etched, improving the rectangularity of the laminated portion 20. Therefore, as shown in Fig. 22, the width of the laminated portion 20 is substantially uniform in the first direction X.

[0120] <Evaluation of Fine Wire Formability in Laminated Portion> The fine wire formability in laminated portion 20 of printed wiring board 200 manufactured using printed wiring board substrate 500 of Samples 1 to 11 was evaluated.

[0121] An evaluation TEG was used to evaluate the fine line formability of the laminated portion 20. FIG. 23 is a plan view of the evaluation TEG. As shown in FIG. 23, the evaluation TEG has a base film 1 and a plurality of laminated portions 20. In the evaluation TEG, the main surface 1s has 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3. The 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3 are arranged in a row along the left-right direction.

[0122] A plurality of laminated portions 20 are formed on the wiring formation regions R1, R2, and R3. The laminated portion 20 formed on the wiring formation region R1 extends in the vertical direction (second direction Y in FIG. 23). The laminated portion 20 formed on the wiring formation region R2 and the laminated portion 20 formed on the wiring formation region R3 extend in directions inclined at 45° and −45° with respect to the vertical direction, respectively.

[0123] The L / S of the laminated portion 20 formed on the nth (n is a natural number equal to or less than 20) interconnect formation region R1 from the right is n μm / 100 μm. L is the width of each of the plurality of laminated portions 20. S is the shortest distance between two adjacent laminated portions 20. The L / S of the laminated portions 20 formed on the interconnect formation region R2 and the laminated portions 20 formed on the interconnect formation region R3 is n μm / 100 μm, similar to the L / S formed on the interconnect formation region R1. The aspect ratio of the laminated portion 20 (the value obtained by dividing the height Ht of the laminated portion 20 by the width L of the laminated portion 20) is set to 1 or more and 2 or less.

[0124] For each of the 20 wiring formation regions R1, each of the 20 wiring formation regions R2, and each of the 20 wiring formation regions R3, the stacked portion 20 was observed using a SEM (Scanning Electron Microscope) to determine whether the fine lines had been formed properly.

[0125] In Tables 1 to 3, when the minimum value of the width L of the laminated portion 20 that can be properly formed is 6 μm or less, the evaluation was given as A. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 6 μm and not more than 10 μm, the evaluation was given as B. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 10 μm and not more than 15 μm, the evaluation was given as C. When the minimum value of the width L of the laminated portion 20 that can be properly formed is more than 15 μm, the evaluation was given as D.

[0126] As shown in Tables 1 to 3, in Samples 5 and 6, the thin-line formability of the laminated portion 20 was evaluated as C or D. On the other hand, in Samples 1 to 4 and Samples 7 to 11, the thin-line formability of the laminated portion 20 was evaluated as A or B. From these results, it is considered that the thin-line formability of the laminated portion 20 is significantly affected by the thickness H of the base layer 2. In Samples 5 and 6, the thickness H of the base layer 2 is greater than 1 μm. On the other hand, in Samples 1 to 4 and Samples 7 to 11, the thickness H of the base layer 2 is less than 1 μm, and therefore the thin-line formability of the laminated portion 20 is good.

[0127] <Overall Evaluation> From the above, by suppressing the segregation rate of the {111} plane of the base layer 2 of the printed wiring board substrate, the rectangularity of the laminated portion 20 is improved. Furthermore, by improving the fine line formability of the laminated portion 20, it is possible to obtain a printed wiring board 200 having a fine circuit. In particular, the printed wiring boards manufactured using the printed wiring board substrates of Samples 9 and 10 have good rectangularity of the laminated portion 20 and good fine line formability.

[0128] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present disclosure is defined by the claims, not by the above-described embodiments, and is intended to include any modifications within the scope of the claims and meanings equivalent to the claims.

[0129] 1 base film, 1s main surface, 2 underlayer, 2a first underlayer, 2b second underlayer, 2s underlayer surface, 3 electrolytic plating layer, 4 resist pattern, 4a opening, 20 laminated portion, 20a first laminated portion, 20b second laminated portion, 20s side, 21s first surface, 22s second surface, 23s smallest surface, 24s largest surface, 100, 100a, 100b, 500 printed wiring board substrate, 200 printed wiring board, 300 plating apparatus, 310 plating treatment tank, 311 electrode, 320 roller, 331, 332 electrode roller, 340 power supply, A1 first value, A2 second value, Et rectangularity evaluation index, H, Ha, l1, l2 distance, H, Ha thickness, Ht height, L width, L1 recess amount, L2 Projection amount, R1, R2, R3 wiring formation area, S shortest distance, V1 area, W3 minimum width, W4 maximum width, X first direction, Y second direction, Z third direction, p1 first point, p2 second point, p3a first recessed point, p3b second recessed point, s intermediate base layer surface.

Claims

1. A substrate for a printed wiring board comprising a base film having a principal surface and an underlayer in contact with the principal surface, wherein an electrolytic plating layer is formed on the underlayer so that the total thickness of the underlayer and the electrolytic plating layer is 1 μm or more, and then a direction perpendicular to the principal surface is defined as a first direction. When a cross section of the underlayer and the electrolytic plating layer is measured by electron backscatter diffraction, in a region up to 1 μm from the principal surface, crystal grains oriented in the {111} plane as viewed from the first direction are defined as first crystal grains, and the crystal grains oriented in the {111} plane are crystal grains oriented in a plane with a measurement tolerance of 10° or less from the {111} plane, and when crystal grains other than the crystal grains oriented in the {111} plane are defined as second crystal grains, the ratio of the area occupied by the first crystal grains to the area occupied by the second crystal grains is 0.15 or less.

2. A printed wiring board comprising: a base film having a principal surface; and a laminate portion disposed on said principal surface, said laminate portion including an underlayer and an electrolytically plated layer, said underlayer being in contact with said principal surface, and said electrolytically plated layer being in contact with said underlayer; a direction perpendicular to said principal surface being a first direction; and when a cross section of said laminate portion is measured by electron backscatter diffraction, in a region up to 1 μm from said principal surface, first crystal grains are crystal grains oriented in the {111} plane as viewed from said first direction, and said {111}-oriented crystal grains are crystal grains oriented in a plane with a measurement tolerance of 10° or less from said {111} plane, and when crystal grains other than said {111}-oriented crystal grains are defined as second crystal grains, the ratio of the area occupied by said first crystal grains to the area occupied by said second crystal grains is 0.15 or less.

3. The printed wiring board according to claim 2, wherein a direction perpendicular to the first direction is defined as a second direction, and a direction perpendicular to the first direction and the second direction is defined as a third direction, the laminate portion is formed to extend linearly along the second direction, and further, the laminate portion includes adjacent first and second laminate portions, the width of each of the first and second laminate portions is 15 μm or less, and the shortest distance in the third direction from the first laminate portion to the second laminate portion is 15 μm or less.

4. The printed wiring board according to claim 3, wherein the width of each of the first laminated portion and the second laminated portion is 10 μm or less, and the shortest distance in the third direction from the first laminated portion to the second laminated portion is 10 μm or less.

5. A printed wiring board as set forth in claim 3 or claim 4, wherein the width of each of the first laminated portion and the second laminated portion is 2 μm or more, and the shortest distance in the third direction from the first laminated portion to the second laminated portion is 2 μm or more.

6. A printed wiring board according to any one of claims 3 to 5, wherein in the cross section, the laminated portions each have a maximum width and a minimum width, and the value obtained by dividing the minimum width by the maximum width is 0.8 or more.

7. The printed wiring board according to any one of claims 3 to 6, wherein, in the cross section, the laminate portion has a first surface and two side surfaces connecting the first surface and the main surface, the first surface being the surface farthest from the main surface in the first direction, at least one of the two side surfaces includes a first point and a first recessed point, the first point being a point where the side surface and the first surface intersect, the first recessed point being located at a position where the distance from the first point in the third direction is the longest, and the distance in the third direction from the first point to the first recessed point is 0.15 times or less the height from the main surface to the first surface.

8. The printed wiring board according to any one of claims 3 to 7, wherein, in the cross section, the laminate portion has a first surface, a second surface, and two side surfaces connecting the first surface and the main surface, the first surface being the surface farthest from the main surface in the first direction, the laminate portion contacting the main surface at the second surface, at least one of the two side surfaces including a second point and a second recessed point, the second point being a point where the side surface and the second surface intersect, the second recessed point being located at a position where the distance from the second point in the third direction is the longest, and the distance in the third direction from the second point to the second recessed point is 0.15 times or less the height from the main surface to the first surface.

9. The printed wiring board according to any one of claims 2 to 8, wherein the thickness of the underlayer is 1 μm or less.

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