Low insertion synchronizer

Abstract

A low-insertion synchronous circuit (10) providing data transfers across clock domains (14, 16) comprises a complementary waveform sampler (12) receiving clock inputs (gclka, gclkb) from both a first clock domain and a second clock domain to determine a phase relationship between domain clocks, A set of edge detectors (18, 19) identify clock edges (r1...r16, f1...f16) in sampled waveform outputs (ws(n)). A set of programmable delay circuits (20, 21) supply a specified delay to a clock of the first clock domain and a set of flying registers (22, 23) can then receive data from either of the clock domains, because those registers are clocked by a clock-specified programmable delay through precision pulse generators (24, 25).

Description

[0001] Description

[0002] LOW-INSERTION SYNCHRONIZER

[0003] TECHNICAL FIELD

[0004] The present invention relates to electrical digital data processing circuits, such as those used in multi-core, multithreading processors with adaptive clocks, that can provide transfers (transmission and reception) of data across distinct clock domains with timing of the domain-crossing data insertions arranged to minimize potential metastability events.

[0005] BACKGROUND ART

[0006] Multi-core and heterogeneous computing very-large-scale integration (VLSI) systems have a global clock problem. To maintain clock and power supply tolerances, synchronous compute domains are necessarily bounded in size even when they use best-practices

[0007] H-tree / grid distributions, such as the clock distribution network described in U. S. Patent 6, 532, 963. Data that crosses between multiple clock domains, as in U. S. Patent 6, 532, 544, frequently suffers large phase errors that cause flip-flop setup / hold violations that in turn cause fatal metastability events. Such crossing errors are exacerbated by various adaptive clock techniques that dynamically and continuously adjust the clock frequency of each clock domain to minimize power usage while maximizing performance, such as the use of asymmetric frequency-locked loops in the L3 cache of the SPARC M7 processor and as described in U. S. Patent 8, 269, 544.

[0008] Classical asynchronous interface architectures (queues, register files, gray code pointers, and metastability resolution of the pointer values to indicate safe transfer) impose many-cycle data latency to deal withthese problems, as in U. S. Patent 9, 509, 317 and as described by G. K. Konstadinidis et al. in " SPARC M7:

[0009] A 20nm 32-core 64MB L3 Cache Processor", Sec. IIIB:

[0010] " Voltage Shift Module (VSM)", IEEE Journal of Solid-State Circuits, Vol. 51, No. 1, January 2016, pp. 82-83.

[0011] All-digital clock alignment has been previously attempted, as in the phase alignment circuit described in U. S. Patent 9, 136, 850. A coarse grain alignment (CGA) circuit delays a data signal to within a specified amount of a clock period (e.g., one-half cycle of a clock) and a fine grain alignment (FGA) circuit delays a clock signal to align data and clock edges so that the skew or phase difference therebetween is negligible. The CGA circuit features a shift register with a serially coupled chain of storage elements (preferably being alternating instances of negative-edge triggered and positive-edge triggered elements) such that a data signal input into a first storage element propagates through the chain in response to changes in the clock signal input into each storage element. The CGA circuit also has a waveform capture register that loads all data samples in parallel from the shift register whenever an initialization signal is asserted. The FGA circuit is similar but has a delay unit comprising serially coupled delay elements that can be in the form of a dual-rail delay chain in which each delay element includes two cross-coupled inverters that transfer signals between two rails arranged in a feedforward configuration. The clock signal is received by the first delay element and propagates through the chain. A waveform capture register samples the clock signal in parallel at the various stages of the delay unit.

[0012] However, this arrangement is designed to restore clock alignment with its own data rather thanaligning clock and data from different clock domains. The function is unidirectional only within a given clock domain. The response time is slow because it is designed for correcting static phase errors created, for example, by wiring delays of chip, package, and board routes, rather than the dynamic phase errors that are created in ever-shifting clock domains. To avoid metastability errors, the circuit requires simultaneous dual clock input, such as that available in clock-source-synchronous signal systems (e.g., in U. S. Patent 8, 898, 365), and provides no means to avoid a lethally time-consuming delay chain initialization like U. S. Patent 8, 242, 823. Both the CGA and FGA circuits create additional delays from encoding, decoding, and multiplexing the detected bits, which would be lethal in any dynamic clocking systems. " Lethal" here means too slow to keep up with the dynamic changes. The computed answer becomes wrong by the time the calculation is completed.

[0013] Another attempt at all-digital clock alignment is a synchronous mirror delay (SMD) circuit described by Vince DiPuccio in CMOSedu.com ECG721 Memory Circuit Design - Spring 2017 class on " The Use and Design of Synchronous Mirror Delays", cf. Alternative Topology D Flip-flop, pp. 11-14, May 2017 (https: / / cmosedu. com / videos / sl7 / ecg721 / SMD.pdf ). The SMD includes a measurement delay line, mirror control circuit, and variable delay line (VDL). As in the '850, this attempt also restores clock alignment with its own data rather than aligning clock and data in different clock domains and is a unidirectional data transfer function only. Use of simple D flip-flops cause metastability-induced functional errors in edge detection in the form of false edges and multi-bit position errors in detected edgelocations. Because DiPuccio' s VDL in this circuit is not a priority delay line, detection of multiple clock edges will cause multiple signals to propagate to the VDL output, producing erroneous behavior whenever the receiving domain is operating at a higher frequency than the sending domain. The VDL one fan-in per stage also presents a large load that detracts from speed and therefore accuracy and operating range.

[0014] Therefore, direct bidirectional data transfers between different clock domains using a fully digital circuit with faultless reception on every source clock cycle has yet to be successfully achieved. Achieving reliable cross-domain transfers in 1.5 cycles or less is sought.

[0015] SUMMARY DISCLOSURE

[0016] A low-insertion synchronizer (LISA) achieves these objectives by continuously comparing two domain clocks to find the current phase error, then creating a sub-cycle insertion delay that aligns clock and data of a first domain with the clock and data of a second domain. Data transfers via this synchronizer are bidirectional, that is, can be made either from f irst-to-second domains or from second-to-f irst domains. It can successfully handle dynamic phase differences between ever-shifting clock domains with programmable delay lines that correctly allow for multiple edge detections.

[0017] To implement LISA, a family of simultaneous dual CMOS of clock, logic, timing, state, and metastability elements are provided, including a low-latency (2 inversion delays) complement clock generator, a complementary delay chain for waveform detection, and a replica delay chain for delay insertion. The waveformdetection chain is fully oversampled, with every stage monitored by a complementary flop. The chains and flops are specifically designed and clocked for metastability avoidance and resolution. Sampled bits from the waveform detector feed edge detection logic, which provides fully decoded control of the replica delay chain. As a result, the replica delay chain provides an appropriately delayed clock to a flying register, where the delay is chosen so that both clock domains can safely read from and write to the flying register via data connections with ordinary clocked registers in their respective domains. The flying register in LISA can be configured to read and write in phase with either rising or falling edge of the target clock domain (at the cycle boundary for rising edge configurations and at the mid cycle for falling edge configurations).

[0018] Accordingly, a synchronous circuit providing data transfers across clock domains per the present invention (LISA) comprises a complementary waveform sampler receiving clock inputs from both a first clock domain and a second clock domain to determine a phase relationship between domain clocks. A set of edge detectors identify clock edges. A set of programmable delay circuits supply a specified delay to a clock of the first clock domain and a set of flying registers can then receive data from either of the clock domains, because those registers are clocked by a clock-specified programmable delay through precision pulse generators.

[0019] BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Fig. 1 is a schematic block diagram of a low-insertion synchronizer circuit (LISA) in accordance with the present invention.Fig. 2 is a schematic illustrating the crossdomain data transfer safe timing strategy employed by LISA for loading data into and reading data from LISA's flying registers.

[0021] Figs. 3A and 3B are respective circuit and timing diagrams for a prior art rising-edge clock pulse generator used by LISA.

[0022] Figs. 4A and 4B are respective circuit and timing diagrams for a prior art falling-edge clock pulse generator used by LISA.

[0023] Figs. 5A-5E are schematic circuit diagrams of various prior art buffers and inverters used by LISA.

[0024] Figs. 6A and 6B are schematic circuit diagrams of respective prior art rising-edge and falling-edge pulse flip-flops used by LISA.

[0025] Figs. 7A, 7B, and 7C are schematic circuit diagrams of respective positive-edge, negative-edge, and dual complementary flip-flops used by LISA.

[0026] Figs. 8A and 8B are respective circuit and timing diagrams of an inventive, precisely complementary clock generator used by LISA.

[0027] Fig. 9 is a schematic circuit diagram of an embodiment of an inventive, priority delay line (PDL) used by LISA

[0028] Fig. 10 is a schematic circuit diagram of an embodiment of an inventive, complementary waveform sampler (WS) used by LISA.

[0029] Figs. 11 through 13 are schematic circuit diagrams of additional inventive embodiments of waveform samplers that may be used by LISA, illustrating a capacitor alternative, metastability hardening and shifting to falling edge operation.Fig. 14 is a schematic circuit diagram of an edge detector (EDGE) as used by LISA to set the PDL and with novel complementary flip-flops from the WS.

[0030] Fig. 15A and 15B are schematic timing diagrams used to assign programmable delay amounts according to a neutral setting.

[0031] Fig. 16 is a schematic circuit diagram of an edge detector as in Fig. 14 with PDL connection assignments according to the timing of Fig. 15A.

[0032] Fig. 17 is a waveform timing diagram for the various signals in the LISA circuit of Fig. 1.

[0033] Figs. 18 and 19 are respective circuit and waveform timing diagrams using a modified EDGE-PDL delay assignment that are balanced for frequency.

[0034] Fig. 20 is a further modified waveform timing diagram using a further metastability hardened EDGE-PDL delay assignment.

[0035] Figs. 21 and 22 are schematic circuit diagrams of embodiments of pulse clock header and waveform sampler modified to allow post-silicon meta-tuning.

[0036] Figs. 23-28 are a set of schematic circuit diagrams for an embodiment of LISA with reversed phase.

[0037] Fig. 29 is a corresponding waveform diagram for this reverse-phase embodiment of LISA.

[0038] Figs. 30 through 32 are schematic circuit diagrams of alternative complementary clock generator, waveform sampler, and programmable delay line allowing for stuck fault testing of those components.

[0039] DETAILED DESCRIPTION

[0040] With reference to Fig. 1, a low-insertion synchronizer circuit 10 in accordance with the present invention includes a complementary waveform sampler (WS)12 receiving clock inputs (gclka and gclkb) from both a first clock domain 14 and a second clock domain 16 to continuously compare the domain clocks (gclka and gclkb) and determine the current phase relation therebetween. The second domain clock (gclkb) waveform is sampled in a complementary delay chain monitored at each stage by a complementary flop as waveform outputs ws (n) using the first domain clock (gclka) which are fed to a set of edge detectors (EDGE) 18 and 19 to find the current position of the rising and falling edges ri (n), ra (n), fi (n), and f2(n) of the sampled clock. The identified clock edge outputs are supplied to a set of programmable delay circuits (PDL1 and PDL2) 20 and 21 in the form of a replica delay chain that creates a sub-cycle insertion delay that correctly aligns clock and data of a first domain with the clock and data of a second domain. First domain data in a first clock domain register 26 clocked by a first domain clock rising edge is fed on first domain data lines 27 to either flying register 22 or 23 and loaded therein in response to pulse edges generated via precision pulse generators 24 and 25 from the respective programmable delay circuits 20 and 21. The loaded first domain data can then be read on data lines 28 from its flying register 22 or 23 by respective falling-edge registers 30 and 31 in the second clock domain through a voltage level shifter 29. Likewise, second domain data in a falling-edge register 32 or 33 in the second clock domain can be fed through a voltage level shifter 34 on data lines 35 into a corresponding flying register 22 or 23 and loaded therein in response to pulse edges generated via precision pulse generators 24 and 25 from the respective programmable delay circuits 20 and 21. The loaded second domain data can then beread by a first clock domain register 37 clocked by a first domain clock falling edge from its flying register 22 or 23 on data lines 36 via 2: 1 multiplexer 38 (that selects via toggle control 39 which flying register to access).

[0041] With reference to Fig. 2, in the first clock (clka) domain 14, a variable clock delay places a flying register 22 (or 23) so that it can be safely read and written by ordinary domain registers 30 and 32 in the second clock (clkb) domain 16. Both the first domain registers 26 and 37 and the second domain registers 30 and 32 hold their data for one cycle in their respective clock domains. Register 26 loads on a rising clock edge (positive-edge active), while the other registers 30, 32 and 37 load on a falling clock edge (negative-edge active). The flying register 22 (and 23) load on a variably delayed first domain clock rising edge and hold data for two full cycles. This two-cycle hold ensures a good read (of second domain data by first domain register 37 and of first domain data by second domain register 30) for all possible phase alignments of the two clock domains and consequently for all possible delays of the flying register. The second domain registers 30 and 32 are negative-edge active so they operate at mid-cycle of the second domain clock (clkb). This arrangement is chosen so the rise of the variably delayed first domain clock rise gets aligned with the rise of the second domain clock for maximum clarity of loading and reading of data in the flying register 32.

[0042] Thus, data transfers via this synchronizer are fully bidirectional, that is, can be made either from first-to-second domains or from second-to-f irst domains. Because of the waveform sampler 12 with edge detectorcircuits 18 and 19 and programmable delay circuits 20 and 21, this synchronizer circuit 10 can successfully handle dynamic phase differences between ever-shifting clock domains with programmable delay lines that correctly allow for multiple edge detections. The programmable delay circuits 20 and 21 provides an appropriate delayed clock to flying registers 22 and 23, where the delay is chosen so that both clock domains can safely read from and write to the flying registers with ordinary clocked registers 26 and 37, and 30-33 in their respective domains.

[0043] Building Blocks:

[0044] The low-insertion synchronizer circuit (LISA) 10 has multiple circuit building blocks which will now be described. These in turn are used to construct phase circuits, a next higher level of building blocks that make up the components of LISA.

[0045] Figs. 3A-3B and 4A-4B show respective prior art rising-edge and falling-edge clock pulse generators 40 and 50 and their associated timing relating the distributed grid clock (gclk) to the resulting positive pulse (rpclk) and negative pulse (Afpclk) generated by those circuits. These circuits are employed at clock headers, i.e. at the final, local buffer stages of a clock distribution, and are organized to have a clock signal distributed on a clock rail to local clock loads with only about Ips RC while driving a 64-bit wide datapath register. The low RC values cause the 50 or so transistor devices in the clock buffers to statistically average their delays to produce a delay with a 7× smaller deviation o than a single device. Statistical suppression of process variation is obtained for a totalsame-die error of 3ps. Fig. 3A emits a positive pulse (rpclk) on the rising edge of the grid clock (gclk), as seen in Fig. 3B. The precharge-on-gclk-low feedback circuit 42 prevents oscillation while the gclk is high. Setting the enable (en) high enables the clock header. Fig. 4A emits a negative pulse (Afpclk) on the falling edge of the grid clock (gclk), as seen in Fig. 4B. The predischarge-on-gclk-high feedback circuit 52 prevents oscillation while gclk is low. The enable (Aen) low enables the clock header. In both circuits, at 5ps FO4, the pulse width is 25ps with a 2ps same-die error range. Note that the relationship ofAfpclk to gclk fall is precisely the same as rpclk to gclk rise.Afpclk and rpclk are polarity / phase duals, a feature that will be advantageously exploited in the application at hand.

[0046] Figs. 5A-5E show various prior art buffers and inverters that are used in LISA. Fig. 5A is a stacked inverter, Fig. 5B is a stacked buffer, Fig. 5C is a tri¬ state inverter, Fig. 5D is an OR-controlled tri-state inverter (OTI), and Fig. 5E is an AND-controlled tri- state inverter (ATI). For the stacked inverter and buffer, min-time pads and other delay chains formed with stacked devices have advantages over simple unstacked inverters. They readily approximate FO4 delay per stage (due to ¼ drive and 2× load). They better approximate logic gate delay sensitivity to voltage. They mitigate process variation by raising the device count per stage. And they leak less. For the tristate inverter (used in constructing flip-flops), the gating g input must always be the complement of theAg input, but a one-stage phase error between g andAg is acceptable. The high-impedance state is achieved when the gating g input is driven low; otherwise, the circuit is an inverter. OTI and ATIcircuits are defined for use in specialized state elements. As in the tri-state inverter, the g andAg inputs must be complements of one another. Likewise, the h andAh inputs must be complements. Again, one-stage phase error is acceptable. For the OTI, the high-impedance state is achieved when both g and h gate inputs are driven low; otherwise, asserting either gate input (g OR h) makes the circuit an inverter. For the ATI, the high-impedance state is achieved when either gate input (g or h) is driven low; otherwise, asserting both gate inputs (g AND h) makes the circuit an inverter. In contrast to multi-inversion-stage designs, these tristates are single-inversion designs that needfully and beneficially minimize in-to-out delay.

[0047] Figs. 6A and 6B are respective prior art rising edge and falling edge pulse flops (PF). Flip-flop function can be implemented by driving a single latch with a pulse generator. These use accurate pulse clocks received from the rising-edge and falling-edge clock pulse generators 40 and 50 of Figs. 3A and 4A as inputs. In Fig. 6A, data d loaded into the flop updates during a rising pulse and holds otherwise. In Fig. 6B, data d loaded into the flop updates during a falling pulse and holds otherwise. With precision pulse generators (Figs.

[0048] 3A and 4A), a stacked buffer min-delay pad (Fig. 5B) is sufficient to ensure safe back-to-back operation.

[0049] Fig. 7A, 7B, and 7C are believed to be novel. They show respective positive-edge and negative-edge complementary flip-flops (CF) and finally a dual-clock complementary flip-flop (DCF). Complementary flip-flops have superb metastability performance. The CFs in Figs.

[0050] 7A and 7B are triggered by a single clock edge (either rising or falling), while the DCF in Fig. 7C updates oneither edge (i.e., twice per cycle). The latch technologies operate as flip-flops because rpclk andAfpclk are pulsed clocks, which are generated by the pulsed clock generators 40 and 50 in Figs. 3A and 4A. In Fig. 7A, the flop holds while rpclk is low and updates when rpclk is high. In Fig. 7B, the flop holds whileAfpclk is high and updates whenAfpclk is low.

[0051] In Fig. 7A, the rising edge complementary flipflop 60 includes respective first and second tristate inverters 61 and 62 that receive complementary data inputs d andAd. Their respective outputs 63 and 64 are coupled into a latch made up of third and fourth tristate inverters 65 and 66 and are output through respective inverters 67 and 68 to form outputs q andAq. The tristate inverters 61, 62, 65, and 66 are driven by a rising edge pulse rpclk and its inverseArpclk (via an inverter 69). Zero phase error between data inputs d andAd is desirable to reduce the incidence of metastability. In modern processes, a conventional flop has a setup+hold window of about 20ps. Encroachment on this window expands the settling time of the flop and ultimately incites metastable flop behavior. But this complementary flip-flop is fully responsive to d andAd even within 5ps of an impending rpclk fall because there is still sufficient time to completely transition both storage nodes 63 and 64. After that, q andAq push-out begins. Metastable behavior only occurs as the data transitions coincide with rpclk fall, which is therefore the final moment of data sampling. The metastability window for this flop is only about 0.2ps, a dramatic improvement over conventional flops. The fully complementary structure reduces the duration of metastability because both storage nodes are driven to the same point.Minimizing the layout parasitic capacitance of the state loop is also desirable for speeding metastability resolution. Maximizing the hold portion of the rpclk waveform maximizes the fraction of the cycle for metastability resolution. Fig. 7B is essentially identical except for its tristate inverters being driven by falling edge pulseAfpclk and its inverse fpclk.

[0052] In Fig. 7C, the dual-clock complementary flipflop (DCF) 70 updates when either rpclk orAfpclk pulses. The first and second tristate inverters are replaced by OR-controlled tristate inverters 71 and 72, and the latch made up of third and fourth tristate inverters replaced by AND-controlled tristate inverters 75 and 76 on storage nodes 73 and 74. These OTI and ATI circuits are driven by both rising edge and falling edge pulses rpclk andAfpclk and their inversionsArpclk and fpclk (via inverters 79 and 80) and the storage nodes 73 and 74 proceed to outputs q andAq through respective inverters 77 and 78. This DCF operates as a flip-flop because rpclk andAfpclk are pulsed clocks (generated by pulse generators in Figs. 3A and 4A). Updates begin, proceed, and complete relative to their respective clock edges. Upon pulse start, a single control field-effect transistor (FET) turns on in each of the OTIs 71 and 72. Forward propagation begins. Simultaneously, a single control FET turns off in each of the ATIs 75 and 76. The latch feedback loop inhibit begins. One inversion later, the opposing control FET turns on in each of the OTIs. Forward propagation completes. Simultaneously, the opposing control FET shuts off in each of the ATIs. The latch feedback loop is inhibited and write completes. The outputs q and ^q update precisely simultaneously. Finally, clock pulse completion re-enables the ATIs,restores the latch feedback loop, and puts the OTIs back in tri-state. Needfully and beneficially, these complementary flip-flops in Figs. 7A-7C use the tri-state circuits in Figs. 5C-5E so that d / Ad and q / Aq are only two inversion stages.

[0053] Level shifter considerations:

[0054] Voltage variation during a cycle alters the clock propagation delay as the clock moves through the clock distribution. It is expected that the " Vdda" power grid region associated with the first clock domain will vary differently than the " Vddb" power grid region associated with the second clock domain. Minimizing voltage-induced clock skew therefore requires that all "clka" clock buffers must reside in the " Vdda" power grid region and, likewise, all "clkb" clock buffers must reside in the " Vddb" power grid region. Further only Gnd and its grid are shared and continuous between adjacent power domains. Vdda and its grid are not shared and are not continuous between adjacent power domains. The same is true for Vddb and its grid. Therefore, all clocks and signals that cross between power domains require ground-referenced level shifters. Clock level shifters should provide crisp transitions comparable to FO4 design.

[0055] Clock level shifters should avoid duty cycle distortion (DCD). Designs that use two local wires (elk andAclk) to cross a voltage boundary are an acceptable expense. Therefore, clock level shifters should be placed as late as practicable in the clock distribution trees.

[0056] Returning to the LISA circuit building blocks, with reference to Figs. 8A and 8B, a precisely complementary clock generator (CC) 80 generates a precisely simultaneous, complementary clock pair (cclk,Acclk) in a first domain from an input clock (gclk) in a second domain. The input clock (gclk) is fed to an inverter 82, a rising edge pulse generator 84 (as in Fig.

[0057] 3A), and a falling edge pulse generator 86 (as in Fig. 4A), thereby yielding four clock signals gclk,Agclk, rpclk andAfpclk. These four signals pass through respective ground-referenced level shifters (LS) 88 as they cross the domain boundary. A dual-clock complementary flip-flop (DCF) 90 (as in Fig. 7C) receives the complementary clocks gclk andAgclk as data inputs and are driven by complementary pulse clocks rpclk andAfpclk to yield precisely complementary outputs cclk andAcclk in the first domain. Fig. 8E shows the timing. Operation is at gclk frequency. Initialization and polarity of the output clock pair cclk andAcclk is forced by applying gclk andAgclk as data to the DCF data inputs. Note that the phase alignment of gclk andAgclk is poor (Agclk is always slightly offset by one inversion 82 delay) but unimportant, because the pulse inputs rpclk andAfpclk occur well after gclk andAgclk. The clocks' level shifter delay will be matched by the level shifters 88. The precisely complementary pair (cclk andAcclk) is available just two inversion delays after the clock inputs (gclk andAglck) at the DCF. No lengthy initialization or symmetrization is required. This complementary clock generator 80 is also, of course, a complementary wave generator that converts ordinary CMOS logic signals into simultaneous dual signals. But unlike analog differential signals that operate in the linear transistor region, these are full-swing signal pairs. So the simultaneous dual signals are deliberately and beneficially readily ported between semiconductor technology nodes and fabs.Phase Circuits

[0058] Phase circuits represent the next higher level of building blocks.

[0059] From this point forward, circuit schematics will be left-right inverted from the usual or classical notation to present them in a time order that places oldest information ("past") on the left and the newest information ("present") on the right to match waveform notation time order.

[0060] With reference to Fig. 9, a first embodiment of a priority delay line (PDL) 100 is a circuit that controls a programmable amount of delay selected by dla,b... dl6a,b inputs. Each delay increment (x stage) comprises an inverter chain 102i... 10216 (the first "inverter" 102i is in the form of an AND gate with an enable input en) and a delay chain of 2-2 AND-OR-inverter (A0I22) gates with logic function

[0061] Q = -.[ (A A -iB) v (C D) ].

[0062] The inverter chain receives an input signal in (such as a clock input) at the first inverter 102i. Branching outputs from each inverter supply both an A input to the AOI22 gate of the same stage and an inverter input to the next stage. The AOI22 gates of each stage but last have an output feeding a D input from the preceding stage. The minimum delay is two inversion delays, and each stage is two inversions, so the overall line is non-inverting.

[0063] The small diamond symbol on the AOI22 gates represents the fastest input D.

[0064] The complementary -> B and C inputs to each AOI22 gate 104i... 10416 receive delay select signals from corresponding OR gates 106i... 10616. The smallmultiplexers (-> B and C inputs to the AOI22 gates) in each stage expand or contract the chain delay after the fashion of a slide trombone. No large-fan-in multiplexer is required. The lowest delay value of the set of delay select signals dla,b... dl6a,b sets the specified delay between input in and output out (at the last AOI22 gate 104i in the chain). Therefore, if multiple delay values are asserted, the lowest delay value takes priority. If no selections are asserted, the maximum delay occurs between in and out. Two input selects are provided to the delay select OR gates 106i... 10616. Either can select that stage. Either, having achieved a stable "1" detecting and edge, can suppress a metastable value of the other select.

[0065] An enable input en to the first delay inverter 102i taken low defeats "in" immediately. This resets all delay stages eventually (after propagation). No matter what the various select settings are, "en" propagates through the entire chain and sets a "home" condition of alternating ones and zeros stage by stage. Once "home" is achieved, subsequent changes to any selects (beneficially, any due to metastability resolution) will cause no output glitches. This is because any mux has a choice only between two signals that are either both en & en or both en &Aen. When "home" is only partially achieved (the inverters have reached home but not all the AOI22 gates), the changes in the select inputs will only accelerate homing the AOI22 inputs. Taking the enable signal en high activates all functions immediately.

[0066] The PDL 100 is intended to have chains with lOps delay per stage and 16 stages long to cover an entire cycle time (160ps) of an imagined 6.25GHz machine.(Note that a select dl7 would be unneeded because it is phase equivalent to dl. )

[0067] With reference to Fig. 10, a complementary waveform sampler (WS) 110 is used to compare relative clock phases between two domains. A complementary clock generator (CC) 116 as in Fig. 8A serves as an input stage for a second domain clock gclkb. The chained AOI design of the PDL 100 serves here as a stage in a complementary delay line. Inverters 113o... 11315, 115o - 11515 between each AOI stage 112o... 11215, 114o... 11415 ensure the same delay between stages as the PDL. Positive-edge complementary flip-flops (CF) 118o... 11816, as in Fig. 7A, serve to sample the gclkb waveform propagating down the complementary delay chain. These flip-flops are clocked via by a rising clock pulse rpclk of the first domain clock gclka by means of rising edge pulse generator 120, as in Fig. 3A. The resulting register ws(n) is a 17-bit digital image of the clkb waveform as seen in reference frame clka. A "1" in the ws (n) vector indicates that the clkb waveform is high at that point in the clka cycle, while a "0" in the ws (n) vector indicates clkb is low at that point. CF 118o output wsO is the oldest information; and CF 11816 output wsl6 is the newest information. An inverse of each output ''ws (n) is also provided by the complementary flip-flops 118o - 11816. The waveform is oversampled at 100 Gb / s: 6.25 GHz operation with one metaflop 118o... 11816 monitoring each of the 16 delay elements (lOps / stage @ 5ps FO4).

[0068] The stage delay is lOps, stage transition time lOps, and the metastability window ~0.2ps, so any transition can, incite metastability in at most one bit and get that bit wrong. For a 160ps cycle (6.25GHz), transitions are 80ps apart, so a string of Is (or 0s) in the ws (n) vector willbe 8 bits long. A wrong bit will never create the digital illusion of an extra false transition; it will merely shift the digital position of a real transition.

[0069] Capacitors 111 maintain the beneficial crosscoupling between the complementary waves to maintain a simultaneous dual relationship in each stage. A tristate inverter as in Fig. 5C withAg set to the power rail and g set to GRD is one way to implement such a capacitor. SPICE simulation should set the capacitance value to provide sufficient cross-coupling (evaluate skew of cclk versusAcclk and observe the down-chain rejection of the skew).

[0070] Other waveform sampler (WS) chains are possible. Fig. 11 replaces the capacitors with feedforward cross-coupled inverters 122 to speed up the sampling chain, if deemed necessary. Fig. 12 employs stacked buffers 124 and a second complementary flip-flop (CF) register 126o... 12616 at the output of the first complementary flip-flop (CF) register to harden against the incidence of metastability. The metastability failure rate on all synchronizers is non-zero (it is their nature), but this failure rate can be conveniently set as low as desired by adding one or more of these pipelined resolution stages. The complementary flip¬ flops (CF) are beneficial because their small metastability window decreases the incidence of metastability, their complementary structure increases the latch loop gain, thereby accelerating resolution, and their pulse maximizes the fraction of the cycle used for resolution and minimizes the fraction wasted for update. And finally, Fig. 13 takes consideration of setup and hold requirements on the output word by relocating the waveform data to the falling edge of the sampling clockgclka by having the second set of complementary flip-flop (CF) register elements be clocked with a falling edge pulse clockAfpclk via falling edge pulse generator 128 as in Fig. 4A.

[0071] With reference to Fig. 14, an edge detector (EDGE) 130 is used to establish the amount of delay to be used with the priority delay line (PDL) in Fig. 9. It receives the waveform sampler bits wsO through wsl6 andAws0 throughAwsl6 found in any of the waveform sampler (WS) circuits in Figs. 10-13. Other than the novel use of the waveform sampler results as an input, edge detectors per se are known. However, this EDGE detector 130 also employs novel complementary flip-flops (CF) 132 rather than ordinary flip-flops. This edge detector has two rows of OR gates 134 and 136 receiving respective complementary outputs from adjacent complementary flipflops. The outputs of OR gates 134 indicate the current sampled location of the rising clock edge rl... rl6 received from the waveform sampler, while the outputs of OR gates 136 indicate the current sampled location of the falling clock edge fl... fl6 received from the waveform sampler. A "0" followed by a "1" in the waveform register 132 indicates a rising edge. So, r (n) =Aws (n) AND ws (n+l) =A[ws (n) ORAws (n+1) ]. A "1" followed by a "0" in the waveform register indicates a falling edge. So, f (n) = ws (n) ANDAws (n+1) =A[Aws (n) OR ws (n+l) ]. Multiple rising and multiple falling edges may be detected. The Is in the r and f vectors are the locations of every rising and falling edge in the sampled waveform. These are used to set the PDL delays.Gross

[0072]

[0073] and ass

[0074]

[0075] With reference to Figs. 15A and 15B, the "neutral" (zero-added delay) setting of LISA (Fig. 1) is determined as follows. Compare the overall relative timing of LISA for the two clock domains gclka and gclkb. Assume gclka and gclkb are aligned as desired. In that case we can select rise to match rise and set the programmable delay PDL to minimum. Discover which waveform sampler (WS) stage contains the gclkb rising transition when the sampling window closes for WS complementary sampling flops (i.e., rpclka fall). This is the "neutral" stage. Here, this occurs in the first WS stage after DCF. The edge detector asserts a rising edge signal r for this stage (here, rl6). Therefore, connect rl6 to PDL dl so the PDL has its minimum delay. Finally, connect the other r (n) and f (n) signals according to Fig. 16. This rise and fall logic calculates the correct delay insertion required to safely transfer data between clock domains. The gross timing assigns dl to rl6 and the other assignments progress incrementally. As the location of the rising edge moves to the right, a larger delay is required to create alignment. (dl7 doesn' t exist because it is phase equivalent to dl. ) Falling f (n) assignments are always ^-cycle (8 stage settings) away from the associated rising r (n) assignments (e.g., assign d9 to fl6).

[0076] All the delay selections are passed to the priority delay line (Fig. 9). If multiple edges are detected, the delay line' s design inherently operates on only the shortest one. Since clka and clkb are approximately the same frequency, there will always be either a rise or fall edge detected.In each case, a clock-source-synchronous transfer is achieved every clka cycle. Every transfer arrives at a time such that a clkb read of this data will not create a metastable event in the clkb domain.

[0077] Beneficially, all rise, fall, and delay information is deliberately created, stored, and used in fully decoded form. Edge detection is a local calculation using only adjacent bits, oblivious to other edges. This detection, calculation, and control approach minimizes LISA phase finding latency and maximizes the time available for metastability resolution. Both enhance performance.

[0078] Finally, note that all delay assignments in the edge detector of Fig. 16 can, with judicious layout, be reprogrammed during manufacturing by a metal-only mask revision. Simply bring all ri (n), fi (n), rz (n), fz (n),... output signals and all di (n) a, di (n) b, dz (n) a, d2 (n)b,... input signals up to the desired metal layer and leave room to rearrange them.

[0079] As illustrated in Fig. 15A, the gclkb transition is beneficially centered in a WS stage; it simplifies the delay setting calculation. However, there might be LISA implementations where this is not true. Such cases can be addressed by adding a carefully designed 5ps non-inverting delay stage to one of the clock headers (the D5 implementation shown in Fig. 15B) First, a stacked inverter (loaded to FO4) creates an actual 5ps delay. Parallel copies of this inverter reduce process variation effects. Second, the logical inversion is undone by flipping the rising pulse generator to its complement falling pulse generator, replacing the positive-edge complementary flop to a negative-edge version, and replacing the positive edge pulse flop with its negative edge complement.Error Terms

[0080] LISA deliberately and beneficially has long chains of circuits, "ensembles", that average their process variation errors. The following table indicates the error terms from each component.

[0081] Table 1

[0082] A A

[0083] Component ARC Delay Total N JT** -% +% delay delay (ps) (ps) (PS)

[0084] % (ps) Single 1 1 29 41 100

[0085] device

[0086] D55 8 2.8 10 15 28 1 1 CF & DCF 10 12 3.5 8.4 12 22 2 2 PF 10 6 2.4 12 17 33 3 3 LS 10 12 3.5 8.4 12 22 2 2 PDLtuii 160 160 12.6 2.3 3.3 5.7 9 9 PDLhalf 80 80 8.9 3.2 4.6 8.1 6 6 PDFbit 10 10 3.2 9.3 13 25 2 2 WSfuii 160 320 17.9 1.6 2.3 4.0 6 6 WShalf 80 160 12.6 2.3 3.3 5.7 5 5 wsbit10 20 4.5 6.6 9.3 17 2 2 WShalf PDLfuii 265 346 18.6 1.6 2.2 3.9 10 10 WSfUn PDLtuii 345 506 22.5 1.3 1.8 3.1 10 10 Long 340 504 22.4 1.3 1.8 3.1 11 11 ensemble

[0087] Long 345 512 22.6 1.3 1.8 3.1 11 11 ensemble'

[0088] gclk wire 1 1 1 elk header 1 20 50 7.1 4.1 5.8 10 2 3 elk pulse 25 50 7.1 4.1 5.8 10 2 2 WSLSB 10 10

[0089]

[0090] Total LISA 27

[0091] Total LISA error is the sum of long ensemble, gclk wire, elk header, elk pulse, and WSLSB. Therefore, the flying register clock may be as much as 14ps early or 14ps late.Waveform

[0092] With reference to Fig. 17, the clock and logic waveforms are shown.

[0093] (1) For the second (b) domain grid clock gclkb, the highlighted pulse marks when gclkb must be available for detection. It drives HDR+LS+DCF to produce cclkb 4 Ops later. It also drives HDR+PF to produceAfpclk 30ps later.

[0094] (2) For the second (b) domain clock cclkb delivered (with its complement '"cclkb) to the first (a) domain, the wave is sampled into 16 time bins or "bits" (the tiny, highlighted boxes) by 17 CFs clocked by rpclka. cclkb rise occurs here during WS bit 8. r8 therefore will become 1 (and so will fl6).

[0095] (3) For the first (a) domain grid clock gclka, LISA operates in 4 / 4 time: the four numbered phases (1, 2, 3, 4) of two successive gclka cycles.

[0096] (4) clka is the standard clock header output (for reference only).

[0097] (5) The rising pulse clock header in domain a, rpclka, samples the cclk / Acclk waves into ws (n), holds ws (n) while rpclka is low and begins metastability resolution. It is the clock for a togglel2 state machine. The highlighted pulse is the LISA entry point for a-domain data.

[0098] (6) The falling pulse clock header in domain a,Afpclka, is the clock for the toggle23 state machine. The highlighted pulse is the LISA exit point for a-domain data.

[0099] (7) The output togglel2a of the clka state machine togglel2 is high during gclka 1 and 2. It controls the receiver mux: togglel2a = 1 selects first flying register 22 (in Fig. 1), while togglel2a = 0 selects second flyingregister 23. Togglel2a also controls the clocks for the first and second edge detectors 18 and 19.

[0100] (8)Afpclkla is produced by togglel2a gating the enable of theAfpclkla header. It pipes and long holds ws (n) whileAfpclkla is high to continue metastability resolution and so first edge detector 18 (in Fig. 1) can create and hold r (n) and f (n) for the first programmable delay line (PDL1) 20. Here r8 = 1 and fl6 = 1. r8 and fl6 drive d9a and d9b.

[0101] (9) The output toggle23a of the clka state machine toggle23 is high during gclka 2 and 3.

[0102] (10) glkinpdlsla is the gclka input to the first PDL 20 as enabled by toggle23a. This is the gclk that is picked out to propagate through the PDL1. glkinpdlsla low produces the home condition. High runs the programmed delay, here, d9.

[0103] (11) fpclk2a is produced by togglel2a gating the enable of theAfpclk2a header. It pipes and long holds ws (n) whileAfpclkla is high to continue metastability resolution and so second edge detector 19 can create and hold r(n) and f (n) for the second programmable delay line (PDL2) 21.

[0104] (12) gclkinpdls2a is the gclka input to the second PDL 21 as enabled byAtoggle23a. gclkinpdls2a low produces the home condition. High runs the programmed delay; here, d9.

[0105] (13) flyclkla is the output of a rpclk header driven by the first PDL 20. The highlighted waves are the earliest and latest excursions of flyclkl. The rising edges are 30ps apart.

[0106] (14) flyclk2a is the output of a rpclk header driven by the second PDL 21. The highlighted waves are theearliest and latest excursions of flyclk2. The rising edges are 30ps apart.

[0107] (15)Afpclkb, included for reference, is the falling pulse clock that drives the b-domain registers 30 through 33 (in Fig. 1) that border the flying registers 22 and 23. Note that flyclk waves are perfectly centered inAfpclkb. ±65ps margin remains. The highlighted pulses are the LISA entry and exit points for b-domain data.

[0108] (16)Afpclkblo is the earliest b-domain clock time that barely makes a correct data transfer. The b clock "moved" from where it was "last seen" asAfpclkb. 65ps of movement can be tolerated.

[0109] (17)Afpclkbhi is the latest b-domain clock time that barely makes a correct data transfer. The b clock "moved" from where it was "last seen" asAfpclkb. 65ps of movement can be tolerated.

[0110] Delay Assignments Balanced for Frequency

[0111] With reference to Figs. 18 and 19, a modification from Fig. 16 of the edge detector (EDGE) delay assignments for the programmable delay lines (PDL) of Fig. 9 is shown together with revised waveforms for this balanced frequency case. Instead of rising edge rl6 being assigned to a programmable delay dl, as in Fig. 16, it is now assigned to delay dl6 (a shift of one delay increment, since the delay' s modulus is 16). And instead of falling edge fl6 being assigned to programmable delay d9, it is now assigned to delay d8 (again a shift of one delay increment). It can be seen in the waveforms in Fig. 19 (see especially (13) - (17) ) that the tolerances of the movement of the b clock is now -55ps and +75ps. The middle frequency is now within 1% of the geometric mean of LISA's synchronization range.Metastability Hardening and Post-Silicon Meta-tuning With reference to Fig. 20, a further revised waveform shows the effect of one additional cycle of metastability resolution time. Since metastability resolution proceeds as an exponential decay, where the time constant is the loop time of the storage element, each added increment of time produces geometrically improved results. Additional resolution time can be added in 4 cycle steps. The hardened waveform sampler in Fig. 12 adds a full cycle of resolution time, and Fig. 20 shows the result. The increased robustness comes at a price: lower frequency tolerance range between waveforms (16) and (17) is reduced by about 40% from that in Fig.

[0112] 17. The added computation time allows more time for the b-domain cloak to drift from where it was "last seen". Since 2.5 cycles of clkb low frequency and 3.5 cycles of clkb high frequency have elapsed since sampling, this design is rebalanced for equal time margins rather than the geometric mean of frequency. Still, this is a particularly good choice if the two domains are known to be at the same frequency and only their relative phase is unknown.

[0113] The time allocated to metastability resolution can be adjusted in post-production hardware. This is beneficial for product optimization, debug, and especially applying a single physical implementation across multiple product platforms. Post-silicon meta-tuning is implemented with a modified pulse clock header, as shown in Fig. 21, which is equivalent to the unmodified version in Fig. 3A, coupled with a modified waveform sampler, as shown in Fig. 22, which isequivalent to the unmodified hardened sampler version in Fig. 12.

[0114] As seen in Fig. 22, the number of pipelined resolution stages 140i, 1402, 140s of the waveform sampler can be varied, wherein the middle resolution stage 1402 can be made transparent at will by using the modified clock pulse header of Fig. 21. The 3-input NAND gate in the Fig. 3A unmodified version has been replaced with an AND-OR-invert (AOI) gate with a meta-tuning input m to one of the AND gates of the AOI. (The other AND gate of the AOI receives the prior gclk, en, and latch feedback inputs. ) Setting m = 1 unconditionally drives the clock high. This will render any rising-edge pulse flop transparent (its output q will always equal input d), as with the flops in the middle resolution stage 1402 in Fig.

[0115] 22. With m = 0, the meta-tune pipeline will act as another series of metastability-resolving SD flops, and here two full cycles of metastability resolution will be provided instead of one. Meta-tuning can be extended as desired with additional resolution stages. Likewise, assorted combinations of both rising and falling edge flop pipeline stages are possible. The meta-tuning enable input m can be logically controlled in postproduction hardware (using fuses, mode bits, scan latches, etc. ) Beneficially, this allows for postproduction product optimization across fabs and operating conditions, debug and margin characterization of test and production hardware, and leveraging a single physical design across multiple product platforms.

[0116] Reversing the Phase

[0117] With reference to Figs. 23-29, many clock phase arrangements can be chosen for LISA for the convenienceand needs of specific implementations. LISA can be modified (with the same capabilities) to reverse the phase, where domain input data arrives on a falling clock and all other ports operate on a clock rise. The circuit modifications in Figs. 23-29 must be used as a set so that results are consistent.

[0118] Fig. 23 is the phase reversal modification of Fig. 1 (LISA circuit as a whole). Reverse clock header and their enables are shown, and toggle enable signals are inverted so they remain compatible with the clock circuits they control. However, the receiver mux handles data, not clock, so mux controls are not inverted (an added inverter compensates for this effect). Fig. 24 is the corresponding timing for flying register safe transfer, modifying Fig. 2. Note that the basic transfer strategy remains unchanged except that the registers move to the opposite clock edges. Three of the four ports are now cycle-boundary latches. Fig. 25 is the modified version of the complementary waveform sampler in Fig. 10, which now operates on a falling clock edge (note the falling clock pulse generator 142 as in Fig. 4A in place of the former rising clock pulse generator). The end of the sampling window continues to be the trailing edge of the clock pulse. Fig. 26 is the modified version of the priority delay line (PDL) of Fig. 9, where the PDL input in is a clock, so that reversing the phase requires complementing the enable logic. Figs. 27 and 28 show the modifications to the EDGE delay assignments of Figs. 15A and 16. The neutral stage assignment reverses from rl6— dl to fl6-dl and fl6-d9 to rl6-d9. The PDL complementary flip-flops reverse in phase from falling pulse activated to rising pulse activated. Fig. 29 shows the resulting waveforms.Stuck fault testability modifications

[0119] With reference again to Fig. 1, nearly all of LISA's components are stuck-fault testable bounded by scannable flip-flops. These can be stuck fault tested by conventional scan-chain-based automated test pattern generation. However, the precisely complementary clock generator (CC) in Fig. 8A, the waveform sampler (WS) in Fig. 10 and the programmable delay line (PDL) in Fig. 9 may require manual patterns.

[0120] The CC of Fig. 8A is re-entrant. To break reentry and test control over all four input paths independently, test-controlled enable logic needs to be added to the two data inputs. Mission-mode requires the delay of this logic to be 3 F04 or less. The rising-edge and falling-edge pulse generators enables enl and en2 need to be test controllable. Fig. 30 shows these modifications. The added AOI mux allows testdata andAtest to control gclk andAgclk. Depending on the chipwide test methodology, in test mode it may be desirable to split the two enables to enable rpclk (via enl) and disableAfpclk (via en2) to test DCF as a rising edge pulse flop, or vice versa.

[0121] The WS of Fig. 10 and PDL of Fig. 9 are both re-entrant. The WS is also capacitance sensitive. To break the reentrant paths, we need to give test control over the tied mux inputs. To break the PDL reentry, add a 17thstage at position "minus 1" whose outputs can be used to listen to forced patterns of rising and falling edge positions to exercise both EDGE and PDL. Do and don't set and hold these patterns in the complementary flip-flops, then observe what comes out of the PDL.

[0122] Figs. 31 and 32 show the necessary modifications to eachdelay stage of the WS of Fig. 10 and the PDL of Fig. 9. An idle mux input to each AOI chain of the WS is instead fed with the signal testdata to give the test scan register complete control over the WS itself and over the "waveform" that is fed to the rest of the EDGE_PDL flow. Adding a 17thstage breaks PDL re-entry. In "run" mode, stage 17 loops the inverter chain output back to the mux chain as required; but in test mode, stage 17 listens to the output of the inverter chain and forces the input to the mux chain. Test datal and test data2 allow each mux to be sensitized with all four input data possibilities. Then, test observel and test observe2 see whether each select can successfully direct its mux.

Claims

Claims1. A synchronous circuit providing data transfers across clock domains, comprising:a complementary waveform sampler receiving clock inputs from a first clock domain and a second clock domain that determines a phase relationship between domain clocks;a set of edge detectors coupled to sampled second domain clock waveform outputs from the waveform sampler to identify present rising and falling clock edge locations in the first clock domain of the sampled second domain clock waveform outputs;a set of programmable delay circuits responsive to the identified rising and falling clock edge locations to supply a specified delay to a clock of the first clock domain; anda set of flying registers receiving data from either of two clock domains and clocked by a clock-specified programmable delay through precision pulse generators.

2. The synchronous circuit as in claim 1, wherein the complementary waveform sampler comprises:a complementary clock generator receiving a clock input from the second clock domain and outputting precisely complementary versions of its clock input;multiple stages of complementary delay elements with cross-coupling capacitors between stages, a first stage of the complementary delay elements receiving the complementary versions of the second domain clock input,a second domain clock waveform propagating through the multiple stages; anda clock pulse input in a first clock domain for clocking a set of complementary flip-flops attached to each stage of delay elements for monitoring propagation of the second domain clock waveform, the set of complementary flip-flops outputting sampled second domain clock waveform outputs.

3. The synchronous circuit as in claim 2, wherein the complementary clock generator comprises:a clock input;an inverter coupled to the clock input; a rising-edge clock pulse generator coupled to the clock input;a falling-edge clock pulse generator coupled to the clock input;a set of four cross-domain voltage level shifters coupled to the respective clock input, inverter, rising-edge clock pulse generator, and falling-edge clock pulse generator; anddual clock complementary flip-flop coupled to the respective cross-domain voltage level shifters such that a level-shifted clock input and level-shifted inverted clock input are received as data inputs and level-shifted rising-edge and falling-edge clock pulses are received as clock inputs to the flip-flop, the dual clock complementary flip-flop outputting precisely complementary versions of the clock input.

4. The synchronous circuit as in claim 3, wherein reentrant paths of the complementary clock generator are constructed with added AND-OR-invert gates having test mode inputs that allow stuck fault test coverage.

5. The synchronous circuit as in claim 1, wherein each edge detector comprises:a set of replica complementary flip-flops attached to corresponding complementary flip-flops associated with adjacent delay stages of the complementary waveform sampler, the set of complementary flip-flops being clocked by a first domain clock falling edge;a first set of NOR gates with inputs coupled to adjacent complementary flip-flop first outputs to indicate rising edges for each adjacent amount of delay; anda second set of NOR gates with inputs coupled to adjacent complementary flip-flop second outputs to indicate falling edges for each adjacent amount of delay.

6. The synchronous circuit as in claim 5, further comprising at least one additional layer of replica complementary flip-flops attached to corresponding complementary flip-flops associated with a preceding layer of replica complementary flip-flops, each additional layer being transparent when not enabled and being enablable by a modified clock pulse header receiving a metastability hardening enable input and with a clock pulse output clocking that layer of replica complementary flip-flops.

7. The synchronous circuit as in claim 6, wherein the metastability hardening enable input is programmable in post-production hardware.

8. The synchronous circuit as in claim 1, wherein each programmable delay circuit comprises:an inverter chain receiving a clock input in the first clock domain at a first inverter and with branching clock outputs from each inverter in the inverter chain;a delay chain of 2-2 AND-OR-invert (AOI22) gates each with a truth function of Q = not [ (A A not-B) v (C A D) ], an output Q from one stage feeding into a D input of a next stage, an A input of each stage receiving a corresponding branching data output from the inverter chain; anda set of delay selects received from an edge detector and coupled to not-B and C inputs of corresponding stages of the delay chain, whereby a lowest delay value of the set of delay selects sets a specified clock delay at an output of the delay chain.

9. The synchronous circuit as in claim 8, wherein the set of delay selects assign a unit delay dl to a bit 16 rising edge rl6 and a bit 8 falling edge f8, and additional unit increments of delay to subsequent rising edge and falling edge bits up to 16 units of delay.

10. The synchronous circuit as in claim 8, wherein the set of delay selects assign a unit delay dl to a bit 1 rising edge rl and a bit 9 falling edge f9, and additional unit increments of delay to subsequent rising edge and falling edge bits up to 16 units of delay for a frequency balanced assignment.

11. The synchronous circuit as in claim 8, wherein the not-B and C inputs of corresponding stages of the delay chain in the programmable delay circuit are received from corresponding OR gates each having two select inputs a and b, wherein either of the two select inputs when asserted can select that stage and either of which having achieved a stable assertion value suppresses any metastable value of the other select input.

12. The synchronous circuit as in claim 8, wherein definitions of phase are reversed and the set of delay selects assign a unit delay dl to a bit 16 falling edge fl6 and a bit 8 rising edge r8, and additional unit increments of delay to subsequent falling edge and rising edge bits up to 16 units of delay.

13. The synchronous circuit as in claim 1, wherein reentrant paths of the waveform sampler and programmable delay circuit are constructed with added AND-OR-invert gates having test mode inputs that allow stuck fault test coverage.

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