Display panel, driving method for pixel circuit in display panel, and display device

Abstract

Provided are a display panel, a driving method for a pixel circuit in a display panel, and a display device, relating to the technical field of display. In the pixel circuit, a switching circuit, a control circuit and a driving circuit can cooperate with each other to transmit a light-emitting driving signal to a light-emitting element on the basis of different signals such as a switching control signal, a reference power supply signal, a gate driving signal, and a light-emitting control signal, to drive the light-emitting element to emit light. Therefore, by flexibly configuring a switching control signal, when the light-emitting element is driven to emit light, the switching circuit can control a reference power line to be decoupled from a first node, so that the potential variations at a control end and an output end of the driving circuit are equal, thereby avoiding offset of a light-emitting driving signal transmitted by the driving circuit, and ensuring that the light-emitting element is reliably driven to emit light.

Description

Methods for driving display panels and their pixel circuits, and display devices

[0001] This application claims priority to Chinese Patent Application No. 202410644826.5, filed on May 23, 2024, entitled “Driving method and display device for display panel and pixel circuit thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a display panel and a driving method and display device for its pixel circuits. Background Technology

[0003] A display panel typically includes a substrate and multiple pixels located on the substrate. Each pixel includes pixel circuitry and a light-emitting element. The pixel circuitry is coupled to the light-emitting element and is used to drive the light-emitting element to emit light, thereby enabling the display panel to display an image.

[0004] In related technologies, pixel circuits generally include a control circuit and a driving circuit, with the control circuit comprising two capacitors. The control circuit, based on the gate driving signal provided by the gate line, controls the data line to transmit data signals to the control terminal of the driving circuit; it, based on the light emission control signal provided by the light emission control line, controls the output terminal of the driving circuit to conduct with the light-emitting element; and it, based on the driving power signal provided by the driving power line, adjusts the potentials of the output terminal and the control terminal of the driving circuit. The driving circuit, based on the data signal received at the control terminal and the driving power signal received at the input terminal, transmits a light emission driving signal to the light-emitting element via its output terminal, thereby driving the light-emitting element to emit light. Summary of the Invention

[0005] This application provides a driving method and display device for a display panel and its pixel circuits. The technical solution is as follows:

[0006] On one hand, a display panel is provided, the display panel comprising: a substrate, and a plurality of pixels located on one side of the substrate, each pixel comprising: a pixel circuit and a light-emitting element, the pixel circuit comprising:

[0007] A switching circuit is coupled to a switch control line, a reference power line and a first node, respectively, and is used to control the connection and disconnection of the reference power line and the first node in response to a switch control signal provided by the switch control line.

[0008] A control circuit is coupled to a gate line, a data line, a first light-emitting control line, a first node, a second node, a third node, and a fourth node, respectively. When the reference power line is connected to the first node, it adjusts the potential of the third node based on a reference power signal provided by the reference power line, and also adjusts the potential of the second node. It is used to control the connection and disconnection of the data line and the second node in response to a gate drive signal provided by the gate line, and to control the connection and disconnection of the third node and the fourth node in response to a first light-emitting control signal provided by the first light-emitting control line. The fourth node is coupled to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is coupled to a pull-down power line.

[0009] The driving circuit has a control terminal coupled to the second node, an input terminal coupled to the driving power line, and an output terminal coupled to the third node. It is used to transmit a light-emitting driving signal to the third node based on the driving power signal provided by the driving power line and the potential of the second node.

[0010] In this configuration, the pixel circuits of at least two pixels share the same switching circuit.

[0011] Optionally, the plurality of pixel arrays are arranged such that at least two pixels in at least one row of pixels share the same switching circuit.

[0012] Optionally, in a row of pixels, the pixel circuits of some pixels and the pixel circuits of other pixels share different switching circuits, and the different switching circuits are located on both sides of the row of pixels in the pixel row direction.

[0013] Optionally, the substrate has a display area and an edge area that at least partially surrounds the display area;

[0014] The switching circuit shared by the pixel circuits of at least two pixels is located in the edge region or in the display area.

[0015] Optionally, the display panel further includes: a gate driving circuit located on one side of the substrate and in the edge region, the gate driving circuit being coupled to the gate line and used to provide the gate driving signal to the gate line;

[0016] The switching circuit shared by the pixel circuits of at least two pixels is located in the edge region, and is located on the side of the gate driving circuit closer to the display area, or on the side of the gate driving circuit farther away from the display area.

[0017] Optionally, the switching circuit includes: a switching transistor;

[0018] The gate of the switching transistor is coupled to the switching control line, the first terminal of the switching transistor is coupled to the reference power supply line, and the second terminal of the switching transistor is coupled to the first node.

[0019] Optionally, the switching circuit includes: a first switching transistor and a second switching transistor; the switching control line includes: a first switching control line and a second switching control line;

[0020] The gates of the first switching transistor and the second switching transistor are coupled to the first switching control line and the second switching control line, respectively. The first terminals of the first switching transistor and the second switching transistor are both coupled to the reference power line. The second terminals of the first switching transistor and the second switching transistor are both coupled to the first node.

[0021] Optionally, the control circuit is further coupled between the driving power line and the input terminal of the driving circuit, and also coupled to the second light-emitting control line, and is used to control the on / off state of the driving power line and the input terminal of the driving circuit in response to the second light-emitting control signal provided by the second light-emitting control line; the control circuit includes:

[0022] An adjustment sub-circuit is coupled to the first node, the second node and the third node respectively, and is used to adjust the potential of the third node based on the reference power signal when the reference power line is turned on with the first node, and to adjust the potential of the second node.

[0023] A data writing sub-circuit is coupled to the gate line, the data line and the second node respectively, and is used to control the on / off state of the data line and the second node in response to the gate drive signal;

[0024] The first light-emitting control sub-circuit is coupled to the first light-emitting control line, the third node and the fourth node respectively, and is used to control the on / off state of the third node and the fourth node in response to the first light-emitting control signal.

[0025] The second light-emitting control sub-circuit is coupled to the second light-emitting control line, the driving power line, and the input terminal of the driving circuit, respectively, and is used to control the on / off state of the driving power line and the input terminal of the driving circuit in response to the second light-emitting control signal.

[0026] Optionally, the adjustment sub-circuit includes: a first capacitor and a second capacitor; the data writing sub-circuit includes: a data writing transistor; the first light emission control sub-circuit includes: a first light emission control transistor; and the second light emission control sub-circuit includes: a second light emission control transistor.

[0027] The first plate of the first capacitor is coupled to the second node, and the second plate of the first capacitor is coupled to the third node;

[0028] The first plate of the second capacitor is coupled to the first node, and the second plate of the second capacitor is coupled to the third node;

[0029] The gate of the data writing transistor is coupled to the gate line, the first terminal of the data writing transistor is coupled to the data line, and the second terminal of the data writing transistor is coupled to the second node.

[0030] The gate of the first light-emitting control transistor is coupled to the first light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to the third node, and the second electrode of the first light-emitting control transistor is coupled to the fourth node.

[0031] The gate of the second light-emitting control transistor is coupled to the second light-emitting control line, the first terminal of the second light-emitting control transistor is coupled to the driving power supply line, and the second terminal of the second light-emitting control transistor is coupled to the input terminal of the driving circuit.

[0032] Optionally, the pixel circuit further includes:

[0033] A first reset circuit is coupled to a first reset line, a first initial power line, and at least one target node among the third node and the fourth node, and is used to control the connection and disconnection of the first initial power line and the at least one target node in response to a first reset signal provided by the first reset line.

[0034] The second reset circuit is coupled to the second reset line, the reference power line and the second node respectively, and is used to control the on / off state of the reference power line and the second node in response to the second reset signal provided by the second reset line.

[0035] Optionally, the first reset circuit includes a first reset transistor; the second reset circuit includes a second reset transistor.

[0036] The gate of the first reset transistor is coupled to the first reset line, the first terminal of the first reset transistor is coupled to the first initial power line, and the second terminal of the first reset transistor is coupled to the at least one target node.

[0037] The gate of the second reset transistor is coupled to the second reset line, the first terminal of the second reset transistor is coupled to the reference power line, and the second terminal of the second reset transistor is coupled to the second node.

[0038] Optionally, if the target node is the fourth node, the pixel circuit further includes:

[0039] The third reset circuit is coupled to the first reset line, the second initial power line and the third node respectively, and is used to control the connection and disconnection of the second initial power line and the third node in response to the first reset signal.

[0040] Optionally, the third reset circuit includes: a third reset transistor;

[0041] The gate of the third reset transistor is coupled to the first reset line, the first terminal of the third reset transistor is coupled to the second initial power line, and the second terminal of the third reset transistor is coupled to the third node.

[0042] Optionally, the switch control line is shared with the gate line, the first reset line, or the second reset line;

[0043] The reference power line is shared with the drive power line, the reference power line, the first initial power line, or the second initial power line.

[0044] Optionally, the driving circuit includes: a driving transistor;

[0045] The gate of the driving transistor is coupled to the second node as the control terminal of the driving circuit, the first terminal of the driving transistor is coupled to the driving power line as the input terminal of the driving circuit, and the second terminal of the driving transistor is coupled to the third node as the output terminal of the driving circuit.

[0046] On the other hand, a driving method for pixel circuits in a display panel is provided, applied to the pixel circuits of the display panel as described in the above aspect; the method includes:

[0047] During the non-light-emitting phase, the potential of the switch control signal provided by the switch control line is the first potential. The switch circuit responds to the switch control signal at the first potential, controls the reference power line to conduct with the first node, and the control circuit adjusts the potential of the third node based on the reference power signal provided by the reference power line, and also adjusts the potential of the second node.

[0048] During the light-emitting phase, the potential of the switch control signal provided by the switch control line is the second potential. The switch circuit responds to the switch control signal at the second potential and controls the reference power line to disconnect from the first node.

[0049] In another aspect, a display device is provided, the display device comprising: a power supply component, and a display panel as described in the preceding aspect;

[0050] The power supply component is coupled to the display panel and is used to supply power to the display panel. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0053] Figure 2 is a schematic diagram of the structure of pixels in a display panel provided in an embodiment of this application;

[0054] Figure 3 is a schematic diagram of the structure of pixels in another display panel provided in an embodiment of this application;

[0055] Figure 4 is a schematic diagram of the structure of pixels in another display panel provided in an embodiment of this application;

[0056] Figure 5 is a schematic diagram of the structure of pixels in another display panel provided in an embodiment of this application;

[0057] Figure 6 is a schematic diagram of the structure of pixels in another display panel provided in an embodiment of this application;

[0058] Figure 7 is a schematic diagram of the circuit structure of a pixel in a display panel provided in an embodiment of this application;

[0059] Figure 8 is a schematic diagram of the circuit structure of a pixel in another display panel provided in an embodiment of this application;

[0060] Figure 9 is a schematic diagram of the circuit structure of a pixel in a display panel according to another embodiment of this application;

[0061] Figure 10 is a schematic diagram of the circuit structure of a pixel in a display panel according to another embodiment of this application;

[0062] Figure 11 is a schematic diagram of the circuit structure of a pixel in a display panel according to another embodiment of this application;

[0063] Figure 12 is a schematic diagram of the circuit structure of a pixel in another display panel provided in an embodiment of this application;

[0064] Figure 13 is a schematic flowchart of a pixel circuit driving method provided in an embodiment of this application;

[0065] Figure 14 is a signal timing diagram of a pixel circuit provided in an embodiment of this application;

[0066] Figure 15 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0068] It is understood that the transistors used in all embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. The source is referred to as the first terminal, and the drain as the second terminal, or vice versa. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this application can include any one or a combination of P-type and N-type transistors. Specifically, a P-type transistor conducts when the gate voltage is low and is cut off when the gate voltage is high, while an N-type transistor conducts when the gate voltage is high and is cut off when the gate voltage is low. Additionally, the multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential only represent two different states of the signal's potential and do not represent specific numerical values ​​for either the first potential or the second potential.

[0069] For pixel circuits, due to the capacitive coupling, the potentials at the control and output terminals of the driving circuit change unequally when the light-emitting element is driven to emit light. This causes a shift in the light-emitting driving signal transmitted by the driving circuit, making it unreliable to drive the light-emitting element and degrading the display quality of the display panel.

[0070] Based on this, this application provides a display panel that can solve the problem of degraded display quality caused by the offset of the light-emitting driving signal transmitted by the driving circuit in related technologies. Figure 1 is a schematic diagram of the structure of a display panel provided in this application. As shown in Figure 1, the display panel includes a substrate 10 and a plurality of pixels 00 located on one side of the substrate 10. Based on Figure 1, and referring to the schematic diagram of a pixel structure shown in Figure 2, it can be seen that each pixel 00 includes a pixel circuit 01 and a light-emitting element 02, and the pixel circuit 01 includes a switching circuit 011, a control circuit 012, and a driving circuit 013.

[0071] The switching circuit 011 is coupled (i.e., electrically connected) to the switch control line VC(k), the reference power supply line V1, and the first node N1, respectively. The switching circuit 011 is used to control the on / off state of the reference power supply line V1 and the first node N1 in response to the switch control signal provided by the switch control line VC(k).

[0072] For example, the switching circuit 011 can control the reference power line V1 to conduct with the first node N1 when the potential of the switching control signal provided by the switching control line VC(k) is a first potential, so that the reference power signal provided by the reference power line V1 can be transmitted to the first node N1. Furthermore, the switching circuit 011 can control the reference power line V1 to decouple from the first node N1 when the potential of the switching control signal provided by the switching control line VC(k) is a second potential, so that the first node N1 is in a floating state.

[0073] Optionally, the first potential can be an active potential, and the second potential can be an inactive potential, with the first potential being higher than the second potential. Therefore, the transistor in the pixel circuit provided in this application can be a high-potential active N-type transistor. Of course, in some other embodiments, the first potential can be lower than the second potential, and the corresponding transistor can be a low-potential active P-type transistor. The following embodiments are similar and will not be described in detail again.

[0074] The control circuit 012 is coupled to the gate line Gate(k), the data line Dj, the first light-emitting control line EM1(k), the first node N1, the second node N2, the third node N3, and the fourth node N4, respectively. The control circuit 012 is used to adjust the potential of the third node N3 and the potential of the second node N2 based on the reference power signal provided by the reference power line V1 when the reference power line V1 is on. It is also used to control the on / off state of the data line Dj and the second node N2 in response to the gate drive signal provided by the gate line Gate(k), and to control the on / off state of the third node N3 and the fourth node N4 in response to the first light-emitting control signal provided by the first light-emitting control line EM1(k).

[0075] In this configuration, the fourth node N4 is coupled to the first electrode of the light-emitting element 02, and the second electrode of the light-emitting element 02 is coupled to the pull-down power line ELVSS. Optionally, the light-emitting element 02 can be an organic light-emitting diode (OLED), the first electrode of the light-emitting element 02 can be the anode, and the second electrode of the light-emitting element 02 can be the cathode. Of course, the anode and cathode can be interchanged.

[0076] For example, control circuit 012 can control data line Dj to be connected to the second node N2 when the potential of the gate drive signal provided by gate line Gate(k) is a first potential, so that the data signal provided by data line Dj can be transmitted to the second node N2. Also, control circuit 012 can control data line Dj to be disconnected from the second node N2 when the potential of the gate drive signal provided by gate line Gate(k) is a second potential.

[0077] Similarly, when the potential of the first light-emitting control signal provided by the first light-emitting control line EM1(k) is the first potential, the control circuit 012 can control the third node N3 and the fourth node N4 to conduct, so that the signal transmitted to the third node N3 can be further transmitted to the fourth node N4. Since the fourth node N4 is coupled to the first electrode of the light-emitting element 02, this also means that the signal transmitted to the third node N3 can be further transmitted to the first electrode of the light-emitting element 02. Furthermore, when the potential of the first light-emitting control signal provided by the first light-emitting control line EM1(k) is the second potential, the control circuit 012 can control the third node N3 and the fourth node N4 to disconnect.

[0078] In addition, the control circuit 012 can also adjust the potential of the third node N3 and the potential of the second node N2 based on the reference power signal provided by the reference power line V1 when the reference power line V1 is connected to the first node N1.

[0079] The control terminal of the drive circuit 013 is coupled to the second node N2, the input terminal of the drive circuit 013 is coupled to the drive power line ELVDD, and the output terminal of the drive circuit 013 is coupled to the third node N3. The drive circuit 013 is used to transmit a light-emitting drive signal to the third node N3 based on the drive power signal provided by the drive power line ELVDD and the potential of the second node N2.

[0080] Based on this, when the control circuit 012 controls the third node N3 and the fourth node N4 (i.e., the first electrode of the light-emitting element 02) to be turned on, the light-emitting driving signal transmitted by the driving circuit 013 to the third node N3 can be further transmitted to the first electrode of the light-emitting element 02. Then, the light-emitting element 02 can emit light under the voltage difference between the light-emitting driving signal received at its first electrode and the pull-down power signal provided by the pull-down power line ELVSS received at its second electrode. At this time, it can be considered that a path is formed between the driving power line ELVDD and the pull-down power line ELVSS. It is understood that, in the case where the light-emitting element 02 is an OLED, the light-emitting driving signal can refer to the driving current. The driving circuit 013 generally includes a driving transistor.

[0081] Optionally, the drive power signal provided by the drive power line ELVDD can be at a high potential, and the pull-down power signal provided by the pull-down power line ELVSS can be at a low potential. Here, high and low potentials are relative. Furthermore, the reference power line V1 and the drive power line ELVDD can be shared.

[0082] In some embodiments, the pixel circuit 01 does not include a switching circuit 011, meaning that the control circuit 012 adjusts the potential of the third node N3 at any given time based on a reference power signal provided by the reference power line V1 (such as a drive power signal provided by the drive power line ELVDD). However, during the light-emitting phase when the drive circuit 013 drives the light-emitting element 02 to emit light, the voltage on the signal line (e.g., the data line Dj) is coupled to the second node N2, while the potential of the third node N3 does not change by the same amount. This causes the potential difference between the control terminal and the output terminal of the drive circuit 013 to be unmaintained, meaning the gate-source voltage difference Vgs of the drive transistors included in the drive circuit 013 cannot be maintained. Consequently, the drive current transmitted by the drive circuit 013 to the light-emitting element 02 will shift or drift, failing to reliably drive the light-emitting element 02 to emit light, thus degrading the display quality of the display panel.

[0083] In this embodiment, the pixel circuit 01 includes a switching circuit 011, which responds to the switching control signal provided by the switching control line VC(k) to control the connection and disconnection between the reference power line V1 and the first node N1. Therefore, by flexibly setting the switching control signal, such as setting the potential of the switching control signal to a second potential during the light-emitting stage, the switching circuit 011 can control the reference power line V1 to disconnect from the first node N1, thus ensuring that the first node N1 is in a floating state. This ensures that the potential changes of the second node N2 and the third node N3 are equal, thereby keeping the driving current transmitted from the driving circuit 013 to the light-emitting element 02 stable, reliably driving the light-emitting element 02 to emit light, and resulting in better display quality of the display panel.

[0084] Furthermore, in this embodiment, as shown in FIG2, at least two pixel circuits 01 can share the same switching circuit 011. For example, referring to FIG2, it schematically shows two adjacent pixel circuits 01 located in the same row sharing the same switching circuit 011. This simplifies the structure and facilitates an increase in the PPI of the display panel. PPI refers to the number of pixels per inch (Pixels Per Inch) of the display panel, used to characterize the resolution of the display panel. That is, the display panel provided in this embodiment not only has better display quality but also a significantly improved PPI.

[0085] It is understood that multiple pixels 00 can be arranged in an array as shown in Figure 1. Accordingly, in this embodiment, k can refer to the k-th row, and k can be greater than or equal to 1 and less than or equal to the total number of pixel rows. For example, assuming the display panel includes 1000 rows of pixels, then k can be greater than or equal to 1 and less than or equal to 1000. j can refer to the j-th column, and j can be greater than or equal to 1 and less than or equal to the total number of pixel columns. For example, assuming the display panel includes 2000 columns of pixels, then j can be greater than or equal to 1 and less than or equal to 2000.

[0086] In summary, this application provides a display panel. The display panel includes multiple pixels, and each pixel's pixel circuit includes a switching circuit, a control circuit, and a driving circuit. The switching circuit, under the control of a switching control signal, controls the connection and disconnection of a reference power line and a first node. When the switching circuit controls the reference power line to be connected to the first node, the control circuit adjusts the potential of a third node based on the reference power signal provided by the reference power line, and also adjusts the potential of a second node. Furthermore, the control circuit can cooperate with the driving circuit to transmit a light-emitting driving signal to the light-emitting element to drive it to emit light. Thus, by flexibly setting the switching control signal, when driving the light-emitting element to emit light, the switching circuit can control the reference power line to disconnect from the first node, thereby ensuring that the potential changes at the control and output terminals of the driving circuit are equal, preventing the light-emitting driving signal transmitted by the driving circuit from deviating, and ensuring reliable driving of the light-emitting element to emit light. That is, it can ensure a better display effect of the display panel.

[0087] Furthermore, in this embodiment, since the pixel circuits of at least two pixels share the same switching circuit, the pixel circuit structure can be simplified, so as to ensure that the display panel has a good display effect while also ensuring that the resolution of the display panel can be high, that is, the resolution of the display panel can be greatly improved.

[0088] Optionally, as can be seen from Figure 1, the plurality of pixels 00 described in the embodiments of this application can be arranged in an array. That is, the display panel may include multiple rows and columns of pixels 00.

[0089] Based on this, and referring to Figure 2, it can be seen that in this embodiment, at least two pixels 00 in at least one row of pixels 00 may share the same switching circuit 011. Of course, in some other embodiments, pixel circuits 01 in two or more rows of pixels 00 may share the same switching circuit 011, or pixel circuits 01 in two or more columns of pixels 00 may share the same switching circuit 011.

[0090] Optionally, in a row of pixels 00, the pixel circuits 01 of some pixels 00 and the pixel circuits 01 of other pixels 00 can share different switching circuits 011, and the different switching circuits 011 can be located on both sides of the row of pixels 00 in the pixel row direction. That is, referring to Figure 1, for a row of pixels 00, a switching circuit 011 can be provided on both the left and right edges of the substrate 10 in the display panel, so that some pixels 00 and other pixels 00 in the row of pixels 00 can share it. In this way, compared to the pixel circuits 01 in a row of pixels 00 all sharing a switching circuit 011 located on one side, the problem of large parasitic capacitance and poor signal transmission accuracy caused by excessively long wiring can be avoided.

[0091] It is understandable that a row of pixels 00 can be divided into a left half of pixels 00 near the left edge and a right half of pixels 00 near the right edge. The pixel circuits 01 of the left half of pixels 00 can share the switch circuit 011 located on the left edge, and the pixel circuits 01 of the right half of pixels 00 can share the switch circuit 011 located on the right edge. This simplifies the wiring.

[0092] Optionally, within a row of pixels 00, the number of pixels 00 sharing different switching circuits 011 can be the same for one group and another group of pixels 00. That is, assuming a row of pixels 00 includes 1000 pixels, the 500 pixels in the left half can be considered as a group of pixels 00, and their pixel circuits 01 can share the switching circuit 011 located on the left edge; the 500 pixels in the right half can be considered as another group of pixels 00, and their pixel circuits 01 can share the switching circuit 011 located on the right edge.

[0093] Optionally, referring to FIG2, the substrate 10 may have a display area A1 and an edge area A2 that at least partially surrounds the display area A1.

[0094] In this embodiment, the switching circuit 011 shared by the pixel circuits 01 of at least two pixels 00 can be located in the edge region A2. This ensures that the display area A1 will not contain the switching circuit 011 and its connected switch control line VC(k), further improving the PPI of the display area A1 in the display panel. Of course, in some embodiments, the shared switching circuit 011 may also be located in the display area A1.

[0095] It is understandable that the edge area A2 here does not mean that there is no light-emitting element 02.

[0096] Optionally, the display panel may further include a gate driving circuit, also known as a GOA circuit, located on one side of the substrate 10 and in the edge region A2. This GOA circuit can be coupled to the gate line (k) and can be used to provide a gate driving signal to the gate line (k). Here, GOA refers to gate driver on array (GOA) technology.

[0097] A switching circuit 011 shared by pixel circuits 01 of at least two pixels 00 can be located in the edge region A2, and can be located on the side of the GOA circuit closer to the display area A1, or on the side of the GOA circuit farther from the display area A1. That is, the edge region A2 where the switching circuit 011 is located can refer to the area between the GOA circuit and the display area A1, or it can refer to any area between the display area A1 and the outermost edge of the display panel, such as the area between the GOA circuit and the side farther from the display area A1.

[0098] Optionally, the control circuit 012 described in this application embodiment can also be coupled between the driving power line ELVDD and the input terminal of the driving circuit 013, and can also be coupled to the second light emission control line EM2(k), and can be used to control the on / off state of the driving power line ELVDD and the input terminal of the driving circuit 013 in response to the second light emission control signal provided by the second light emission control line EM2(k).

[0099] For example, when the potential of the second light-emitting control signal provided by the second light-emitting control line EM2(k) is a first potential, the control circuit 012 can control the drive power line ELVDD to conduct with the input terminal of the drive circuit 013, so that the drive power signal provided by the drive power line ELVDD can be transmitted to the input terminal of the drive circuit 013. Also, the control circuit 012 can control the drive power line ELVDD to decouple from the input terminal of the drive circuit 013 when the potential of the second light-emitting control signal provided by the second light-emitting control line EM2(k) is a second potential.

[0100] Based on this, Figure 3 shows a schematic diagram of another pixel structure. As shown in Figure 3, the control circuit 012 may include: an adjustment sub-circuit 0121, a data writing sub-circuit 0122, a first light emission control sub-circuit 0123, and a second light emission control sub-circuit 0124.

[0101] The regulating sub-circuit 0121 can be coupled to the first node N1, the second node N2, and the third node N3, respectively. The regulating sub-circuit 0121 can be used to adjust the potential of the third node N3 and the potential of the second node N2 based on the reference power signal when the reference power line V1 is turned on with the first node N1.

[0102] It is understood that the two adjustment sub-circuits 0121 shown in Figure 3 only represent the parts of the adjustment sub-circuit 0121 at different locations, and do not represent that the pixel circuit includes two adjustment sub-circuits 0121.

[0103] The data writing sub-circuit 0122 can be coupled to the gate line Gate(k), the data line Dj, and the second node N2, respectively. The data writing sub-circuit 0122 can be used to control the on / off state of the data line Dj and the second node N2 in response to the gate drive signal.

[0104] For example, the data writing sub-circuit 0122 can control the data line Dj to be turned on and the second node N2 to be turned on when the gate drive signal potential is the first potential, and can control the data line Dj to be decoupled from the second node N2 when the gate drive signal potential is the second potential.

[0105] The first light-emitting control sub-circuit 0123 can be coupled to the first light-emitting control line EM1(k), the third node N3, and the fourth node N4, respectively. The first light-emitting control sub-circuit 0123 can be used to control the on / off state of the third node N3 and the fourth node N4 in response to the first light-emitting control signal.

[0106] For example, the first light-emitting control sub-circuit 0123 can control the third node N3 and the fourth node N4 to be turned on when the potential of the first light-emitting control signal is the first potential, and can control the third node N3 and the fourth node N4 to be disconnected when the potential of the first light-emitting control signal is the second potential.

[0107] The second light-emitting control sub-circuit 0124 can be coupled to the second light-emitting control line EM2(k), the driving power line ELVDD, and the input terminal of the driving circuit 013, respectively. The second light-emitting control sub-circuit 0124 can be used to control the on / off state of the driving power line ELVDD and the input terminal of the driving circuit 013 in response to the second light-emitting control signal.

[0108] For example, the second light-emitting control sub-circuit 0124 can control the drive power line ELVDD to be connected to the input terminal of the drive circuit 013 when the potential of the second light-emitting control signal is the first potential, and can control the drive power line ELVDD to be disconnected from the input terminal of the drive circuit 013 when the potential of the second light-emitting control signal is the second potential.

[0109] Of course, in some other embodiments, the control circuit 012 may not include the second light-emitting control sub-circuit 0124. That is, as shown in FIG2, the input terminal of the driving circuit 013 can be directly coupled to the driving power line ELVDD.

[0110] Optionally, Figure 4 is a schematic diagram of another pixel structure provided in an embodiment of this application. Figure 5 is a schematic diagram of yet another pixel structure provided in an embodiment of this application. Referring to Figures 4 and 5, it can be seen that the pixel circuit 01 provided in the embodiment of this application may further include: a first reset circuit 014 and a second reset circuit 015.

[0111] The first reset circuit 014 can be coupled to at least one of the first reset line Reset1(k), the first initial power line Vint1, and the third node N3 and the fourth node N4. The first reset circuit 014 can be used to control the on / off state of the first initial power line Vint1 and at least one target node in response to the first reset signal provided by the first reset line Reset1(k).

[0112] For example, the first reset circuit 014 can control the first initial power line Vint1 to be connected to at least one target node when the potential of the first reset signal provided by the first reset line Reset1(k) is a first potential, so that the first initial power signal provided by the first initial power line Vint1 can be transmitted to the at least one target node to reset the at least one target node. Furthermore, the first reset circuit 014 can control the first initial power line Vint1 to be disconnected from the at least one target node when the potential of the first reset signal provided by the first reset line Reset1(k) is a second potential.

[0113] Optionally, referring to FIG4, in the pixel shown therein, the first reset circuit 014 is coupled to the third node N3, that is, the target node is the third node N3 among the third node N3 and the fourth node N4. Referring to FIG5, in the pixel shown therein, the first reset circuit 014 is coupled to the fourth node N4, that is, the target node is the fourth node N4 among the third node N3 and the fourth node N4. Of course, in some embodiments, the first reset circuit 014 may be coupled to both the third node N3 and the fourth node N4, that is, the target node may include both the third node N3 and the fourth node N4.

[0114] The second reset circuit 015 can be coupled to the second reset line Reset2(k), the reference power line Vref, and the second node N2, respectively. The second reset circuit 015 can be used to control the on / off state of the reference power line Vref and the second node N2 in response to the second reset signal provided by the second reset line Reset2(k).

[0115] For example, the second reset circuit 015 can control the reference power line Vref to conduct with the second node N2 when the potential of the second reset signal provided by the second reset line Reset2(k) is the first potential, so that the reference power signal provided by the reference power line Vref can be transmitted to the second node N2 to reset the second node N2. Also, the second reset circuit 015 can control the reference power line Vref to decouple from the second node N2 when the potential of the second reset signal provided by the second reset line Reset2(k) is the second potential.

[0116] Optionally, based on FIG5, when the target node is the fourth node N4, in some embodiments, as can be seen from the schematic diagram of another pixel structure shown in FIG6, the pixel circuit 01 may further include: a third reset circuit 016.

[0117] The third reset circuit 016 can be coupled to the first reset line Reset1(k), the second initial power line Vint2, and the third node N3, respectively. The third reset circuit 016 can be used to control the on / off state of the second initial power line Vint2 and the third node N3 in response to the first reset signal.

[0118] For example, the third reset circuit 016 can control the second initial power line Vint2 to conduct with the third node N3 when the potential of the first reset signal is the first potential, so that the second initial power signal provided by the second initial power line Vint2 can be transmitted to the third node N3 to reset the third node N3. Also, the third reset circuit 016 can control the second initial power line Vint2 to disconnect from the third node N3 when the potential of the first reset signal is the second potential.

[0119] Of course, in some other embodiments, the pixel circuit 01 may not include the third reset circuit 016.

[0120] It is understandable that by setting the first reset circuit 014, the second reset circuit 015 and the third reset circuit 016, the corresponding nodes can be reset, so that each frame scan can be started at the same potential, ensuring good display uniformity of the display panel.

[0121] Optionally, based on Figure 4, Figure 7 shows a schematic diagram of the circuit structure of one pixel. Based on Figure 5, Figure 8 shows a schematic diagram of the circuit structure of another pixel. And, based on Figure 6, Figure 9 shows a schematic diagram of yet another pixel's circuit structure.

[0122] Referring to Figures 7 to 9, it can be seen that the switching circuit 011 may include: a switching transistor Tvc.

[0123] The gate of the switching transistor Tvc can be coupled to the switching control line VC(k), the first terminal of the switching transistor Tvc can be coupled to the reference power supply line V1, and the second terminal of the switching transistor Tvc can be coupled to the first node N1.

[0124] Referring again to Figures 7 through 9, it can be seen that the adjustment sub-circuit 0121 may include: a first capacitor C1 and a second capacitor C2. The data writing sub-circuit 0122 may include: a data writing transistor T1. The first light-emitting control sub-circuit 0123 may include: a first light-emitting control transistor T2. The second light-emitting control sub-circuit 0124 may include: a second light-emitting control transistor T3.

[0125] The first plate of the first capacitor C1 can be coupled to the second node N2, and the second plate of the first capacitor C1 can be coupled to the third node N3.

[0126] The first plate of the second capacitor C2 can be coupled to the first node N1, and the second plate of the second capacitor C2 can be coupled to the third node N3.

[0127] That is, in this embodiment, the first plates of the second capacitors C2 in the pixel circuits 01 of at least two pixels 00 can be connected together, i.e., connected to the first node N1. Meanwhile, the switching transistor Tvc responsible for disconnecting the reference power line V1 can be located in the edge region A2.

[0128] The gate of the data writing transistor T1 can be coupled to the gate line Gate(k), the first terminal of the data writing transistor T1 can be coupled to the data line Dj, and the second terminal of the data writing transistor T1 can be coupled to the second node N2.

[0129] The gate of the first light-emitting control transistor T2 can be coupled to the first light-emitting control line EM1(k), the first electrode of the first light-emitting control transistor T2 can be coupled to the third node N3, and the second electrode of the first light-emitting control transistor T2 can be coupled to the fourth node N4.

[0130] The gate of the second light-emitting control transistor T3 can be coupled to the second light-emitting control line EM2(k), the first terminal of the second light-emitting control transistor T3 can be coupled to the driving power line ELVDD, and the second terminal of the second light-emitting control transistor T3 can be coupled to the input terminal of the driving circuit 013.

[0131] Referring to Figures 7 through 9, it can be seen that the first reset circuit 014 may include: a first reset transistor T4. The second reset circuit 015 may include: a second reset transistor T5.

[0132] The gate of the first reset transistor T4 can be coupled to the first reset line Reset1(k), the first terminal of the first reset transistor T4 can be coupled to the first initial power line Vint1, and the second terminal of the first reset transistor T4 can be coupled to at least one target node.

[0133] It is understandable that, for the structure shown in Figure 4 where the target node is the third node N3, referring to Figure 7, the second terminal of the first reset transistor T4 can be coupled to the third node N3. For the structures shown in Figures 5 and 6 where the target node is the fourth node N4, referring to Figures 8 and 9, the second terminal of the first reset transistor T4 can be coupled to the fourth node N4.

[0134] The gate of the second reset transistor T5 can be coupled to the second reset line Reset2(k), the first terminal of the second reset transistor T5 can be coupled to the reference power line Vref, and the second terminal of the second reset transistor T5 can be coupled to the second node N2.

[0135] Referring to Figure 9, the third reset circuit 016 may include: the third reset transistor T6.

[0136] The gate of the third reset transistor T6 can be coupled to the first reset line Reset1(k), the first terminal of the third reset transistor T6 can be coupled to the second initial power line Vint2, and the second terminal of the third reset transistor T6 can be coupled to the third node N3.

[0137] Referring to Figures 7 to 9, it can be seen that the driving circuit 013 may include: driving transistor T7.

[0138] The gate of the driving transistor T7 can be used as the control terminal of the driving circuit 013 and coupled to the second node N2. The first terminal of the driving transistor T7 can be used as the input terminal of the driving circuit 013 and coupled to the driving power line ELVDD. The second terminal of the driving transistor T7 can be used as the output terminal of the driving circuit 013 and coupled to the third node N3.

[0139] It is understood that since the pixels shown in Figures 4 to 6 all include a second light-emitting control transistor T3, as shown in Figures 7 to 9, the first terminal of the driving transistor T7 can be coupled to the second terminal of the second light-emitting control transistor T3, so as to be indirectly coupled to the driving power line ELVDD through the second light-emitting control transistor T3. Furthermore, as described above, in some embodiments, the second light-emitting control transistor T3 may not be included.

[0140] Optionally, based on Figure 5, Figure 10 shows a schematic diagram of another pixel's circuit structure. As shown in Figure 10, the switching circuit 011 may include: a first switching transistor Tvc1 and a second switching transistor Tvc2. Correspondingly, the switching control line VC(k) may include: a first switching control line VC(k)1 and a second switching control line VC(k)2.

[0141] The gate of the first switching transistor Tvc1 and the gate of the second switching transistor Tvc2 can be coupled to the first switching control line VC(k)1 and the second switching control line VC(k)2, respectively. The first terminal of the first switching transistor Tvc1 and the first terminal of the second switching transistor Tvc2 can both be coupled to the reference power supply line V1. The second terminal of the first switching transistor Tvc1 and the second terminal of the second switching transistor Tvc2 can both be coupled to the first node N1.

[0142] That is, as an optional implementation, as shown in Figures 7 to 9, the switching circuit 011 may include a switching transistor Tvc; as another optional implementation, as shown in Figure 10, the switching circuit 011 may include a group of switching transistors Tvc connected in parallel.

[0143] It is understood that Figures 7 to 10 are circuit diagrams illustrating the case where the switching circuit 011 is located in the edge region A2. However, as described above, in some embodiments, the switching circuit 011 may also be located in the display region A1. Therefore, taking one alternative implementation and the structure shown in Figure 8 as an example, Figure 11 also schematically shows a circuit structure diagram of the switching transistor Tvc included in the switching circuit 011 located in a pixel in the display region A1. Furthermore, taking another alternative implementation and the structure shown in Figure 8 as an example, Figure 12 also schematically shows a circuit structure diagram of the first switching transistor Tvc1 and the second switching transistor Tvc2 included in the switching circuit 011 located in a pixel in the display region A1.

[0144] Optionally, in the embodiments of this application, the switch control line VC(k) can be shared with the gate line Gate(k), the first reset line Reset1(k), or the second reset line Reset2(k).

[0145] For example, referring to Figure 10, the first switch control line VC(k)1 is shared with the gate line Gate(k), and the second switch control line VC(k)2 is shared with the second reset line Reset2(k).

[0146] Also, referring to Figures 7 to 12, the reference power line V1 can be shared with the drive power line ELVDD, the reference power line Vref, the first initial power line Vint1, or the second initial power line Vint2.

[0147] By setting up shared signal lines, the number of signal supply circuits that need to be set up can be reduced, as can the number of signal lines that need to be set up, thereby reducing the bezel size of the display panel and facilitating the design of narrow bezels.

[0148] As can be seen from the accompanying drawings, apart from the switching circuit 011, the pixel circuit provided in this embodiment can be a 7T2C (i.e., 7 transistors and 2 capacitors) structure. Of course, in some embodiments, the pixel circuit can also be other structures, such as 9T2C, provided that it includes the 7T2C structure.

[0149] Optionally, as shown in Figures 7 to 12, the transistors in the pixel circuit can all be N-type transistors. Furthermore, the transistor can be, for example, a metal-oxide-semiconductor (MOS) field-effect transistor, also known as a MOS transistor. An N-type transistor can be called an NMOS transistor, and a pixel circuit including such an NMOS transistor can also be called an NMOS pixel circuit. Correspondingly, the first potential of the effective potential can be a lower potential relative to the second potential of the ineffective potential. Of course, in some other embodiments, the transistors in the pixel circuit can all be N-type transistors, or it can include both P-type and N-type transistors.

[0150] Optionally, the active layer of a P-type transistor can be made of low-temperature polysilicon (LTPS). The active layer of an N-type transistor can be made of oxide.

[0151] It is understandable that, referring to Figure 9, there is a first capacitor C1 between the second node N2 and the third node N3, and a second capacitor C2 between the third node N3 and the first node N1. When the driving transistor T7 transmits driving current to the light-emitting element O2 to drive it to emit light, the potential change on the signal line will couple to the second node N2. However, due to the voltage division effect of the second capacitor C2, the potential on the third node N3 will not change by the same amount. Consequently, the gate-source voltage difference Vgs = VN2 - VN3 of the driving transistor T7 cannot be maintained, where VN2 refers to the potential on the second node N2 and VN3 refers to the potential on the third node N3. This causes a change in the driving current, resulting in a deterioration in the display quality of the display panel.

[0152] In this embodiment, since a switching transistor Tvc is additionally provided between the second capacitor C2 and the driving power line ELVDD, when the light-emitting element O2 emits light, the switching transistor Tvc can control the second capacitor C2 to disconnect from the driving power line ELVDD, thus ensuring that the first plate of the second capacitor C2 is in a floating state, guaranteeing that the potential changes on the second node N2 and the third node N3 are equal, thereby keeping the driving current stable and improving the problem of deterioration in the display quality of the display panel.

[0153] Furthermore, since the switching transistor Tvc and its coupled switching control line VC(k) provided in this application embodiment can be located in the edge region A2 of the substrate 10, and multiple pixel circuits can share the same switching transistor Tvc, the structure can be simplified, which is beneficial to the improvement of the PPI of the display panel and the narrow bezel design of the display panel.

[0154] In summary, this application provides a display panel. The display panel includes multiple pixels, and each pixel's pixel circuit includes a switching circuit, a control circuit, and a driving circuit. The switching circuit, under the control of a switching control signal, controls the connection and disconnection of a reference power line and a first node. When the switching circuit controls the reference power line to be connected to the first node, the control circuit adjusts the potential of a third node based on the reference power signal provided by the reference power line, and also adjusts the potential of a second node. Furthermore, the control circuit can cooperate with the driving circuit to transmit a light-emitting driving signal to the light-emitting element to drive it to emit light. Thus, by flexibly setting the switching control signal, when driving the light-emitting element to emit light, the switching circuit can control the reference power line to disconnect from the first node, thereby ensuring that the potential changes at the control and output terminals of the driving circuit are equal, preventing the light-emitting driving signal transmitted by the driving circuit from deviating, and ensuring reliable driving of the light-emitting element to emit light. That is, it can ensure a better display effect of the display panel.

[0155] Furthermore, in this embodiment, since the pixel circuits of at least two pixels share the same switching circuit, the pixel circuit structure can be simplified, so as to ensure that the display panel has a good display effect while also ensuring that the resolution of the display panel can be high, that is, the resolution of the display panel can be greatly improved.

[0156] This application also provides a driving method for pixel circuits in a display panel, which can be applied to pixel circuits in a display panel as described in the above embodiments. As shown in FIG13, the method includes:

[0157] Step 1301, Non-light-emitting stage: The potential of the switch control signal provided by the switch control line is the first potential. The switch circuit responds to the switch control signal at the first potential, controls the reference power line to conduct with the first node, and adjusts the potential of the third node based on the reference power signal provided by the reference power line, and also adjusts the potential of the second node.

[0158] Step 1302, Light-emitting stage: The potential of the switch control signal provided by the switch control line is the second potential. The switch circuit responds to the switch control signal at the second potential and controls the reference power line to disconnect from the first node.

[0159] Optionally, taking the pixel circuit structure shown in Figure 9, where all transistors in the pixel circuit are NMOS transistors, as an example, and referring to the signal timing diagram shown in Figure 14, the driving method of the pixel circuit provided in this application embodiment is described as follows:

[0160] (1) In the non-light-emitting stage t01, the potentials of the first reset signal provided by the first reset line Reset1(k), the second reset signal provided by the second reset line Reset2(k), and the switch control signal provided by the switch control line VC(k) can all be high; while the potentials of the first light-emitting control signal provided by the first light-emitting control line EM1(k), the second light-emitting control signal provided by the second light-emitting control line EM2(k), and the gate drive signal provided by the gate line Gate(k) can all be low. Accordingly, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, and the switch transistor Tvc can all be turned on; and the data write transistor T1, the first light-emitting control transistor T2, and the second light-emitting control transistor T3 can all be turned off. Furthermore, it is possible to make the first initial power line Vint1 conduct with the fourth node N4, the reference power line Vref conduct with the second node N2, the second initial power line Vint2 conduct with the third node N3, and the reference power line V1 conduct with the first node N1; and it is possible to make the data line Dj decoupled from the second node N2, the drive power line ELVDD decoupled from the first terminal of the drive transistor T7, and the third node N3 decoupled from the fourth node N4.

[0161] Based on this, the first initial power signal provided by the first initial power line Vint1 can be transmitted to the fourth node N4 via the turned-on first reset transistor T4 to reset or initialize the fourth node N4; the reference power signal provided by the reference power line Vref can be transmitted to the second node N2 via the turned-on second reset transistor T5 to reset the second node N2, thereby initially turning on the driving transistor T7; the second initial power signal provided by the second initial power line Vint2 can be transmitted to the third node N3 via the turned-on third reset transistor T6 to reset the third node N3; and the reference power signal provided by the reference power line V1 can be transmitted to the first node N1 via the turned-on switching transistor Tvc. Correspondingly, this t01 stage can also be called the initialization stage.

[0162] (2) In the non-light-emitting stage t02, the potentials of the second reset signal provided by the second reset line Reset2(k), the second light-emitting control signal provided by the second light-emitting control line EM2(k), and the switch control signal provided by the switch control line VC(k) can all be high; while the potentials of the first light-emitting control signal provided by the first light-emitting control line EM1(k), the first reset signal provided by the first reset line Reset1(k), and the gate drive signal provided by the gate line Gate(k) can all be low. Accordingly, the second light-emitting control transistor T3, the second reset transistor T5, and the switch transistor Tvc can all be turned on; and the data write transistor T1, the first light-emitting control transistor T2, the first reset transistor T4, and the third reset transistor T6 can all be turned off. Furthermore, this allows the drive power line ELVDD to conduct with the first terminal of the drive transistor T7, the reference power line Vref to conduct with the second node N2, and the reference power line V1 to conduct with the first node N1; it also allows the data line Dj to be decoupled from the second node N2, the third node N3 from the fourth node N4, the first initial power line Vint1 from the fourth node N4, and the second initial power line Vint2 from the third node N3. Additionally, due to the storage effect of the first capacitor C1, the potential of the second node N2 can be maintained at the potential of stage t01, thereby keeping the drive transistor T7 on.

[0163] Based on this, the drive power signal provided by the drive power line ELVDD can be further transmitted to the drive transistor T7 via the activated second light-emitting control transistor T3, and then to the second node N2 via the activated drive transistor T7. Therefore, the threshold voltage Vth of the drive transistor T7 can be written into the second node N2, making the drive current ultimately transmitted from the drive transistor T7 to the light-emitting element O2 independent of the threshold voltage Vth, thus achieving compensation for the threshold voltage Vth. Furthermore, the reference power signal provided by the reference power line Vref can continue to be transmitted to the second node N2 via the activated second reset transistor T5, and the reference power signal provided by the reference power line V1 can be transmitted to the first node N1 via the activated switching transistor Tvc. Correspondingly, this t02 stage can also be called the Vth compensation stage.

[0164] (3) In the non-light-emitting stage t03, the potential of the gate drive signal provided by the gate line Gate(k) and the potential of the switch control signal provided by the switch control line VC(k) can both be high; while the potential of the first light-emitting control signal provided by the first light-emitting control line EM1(k), the potential of the second reset signal provided by the second reset line Reset2(k), the potential of the second light-emitting control signal provided by the second light-emitting control line EM2(k), and the potential of the first reset signal provided by the first reset line Reset1(k) can all be low. Accordingly, the data writing transistor T1 and the switch transistor Tvc can both be turned on; and the first light-emitting control transistor T2, the second light-emitting control transistor T3, the first reset transistor T4, the second reset transistor T5, and the third reset transistor T6 can all be turned off. Furthermore, this allows the data line Dj to be connected to the second node N2, and the reference power line V1 to be connected to the first node N1; it also allows the third node N3 to be decoupled from the fourth node N4, the drive power line ELVDD to be decoupled from the first terminal of the drive transistor T7, the first initial power line Vint1 to be decoupled from the fourth node N4, the reference power line Vref to be decoupled from the second node N2, and the second initial power line Vint2 to be decoupled from the third node N3. Additionally, due to the storage effect of the first capacitor C1, the potential of the second node N2 can be maintained at the potential of stage t02, thereby keeping the drive transistor T7 on.

[0165] Based on this, the data signal provided by the data line Dj can be further transmitted to the second node N2 via the enabled data writing transistor T1, and the reference power signal provided by the reference power line V1 can be transmitted to the first node N1 via the enabled switching transistor Tvc. Accordingly, this t03 stage can also be called the signal writing stage.

[0166] (4) During the light-emitting stage, the potentials of the first light-emitting control signal provided by the first light-emitting control line EM1(k) and the second light-emitting control signal provided by the second light-emitting control line EM2(k) can both be high; while the potentials of the second reset signal provided by the second reset line Reset2(k), the first reset signal provided by the first reset line Reset1(k), the gate drive signal provided by the gate line Gate(k), and the switch control signal provided by the switch control line VC(k) can all be low. Accordingly, the first light-emitting control transistor T2 and the second light-emitting control transistor T3 can both be turned on; and the data write transistor T1, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, and the switch transistor Tvc can all be turned off. Furthermore, this allows the drive power line ELVDD to conduct with the first terminal of the drive transistor T7, and the third node N3 to conduct with the fourth node N4; it also decouples the data line Dj from the second node N2, the first initial power line Vint1 from the fourth node N4, the reference power line Vref from the second node N2, the second initial power line Vint2 from the third node N3, and the reference power line V1 from the first node N1. Additionally, under the coupling effect of the first capacitor C1, the potential of the second node N2 can rise, thereby fully turning on the drive transistor T7.

[0167] Based on this, the drive power signal provided by the drive power line ELVDD can be further transmitted to the first terminal of the drive transistor T7 via the activated second light-emitting control transistor T3. This allows the drive transistor T7 to transmit a light-emitting drive signal to the third node N3 based on the drive power signal and the potential of the second node N2. Furthermore, the light-emitting drive signal transmitted to the third node N3 is transmitted to the fourth node N4 via the activated first light-emitting control transistor T2, i.e., to the first terminal of the light-emitting element O2. This drives the light-emitting element O2 to emit light, where the light-emitting element O2 can emit light based on the light-emitting drive signal transmitted to the fourth node N4 and the pull-down power signal provided by the pull-down power line ELVSS.

[0168] It is understandable that, since the driving method of the pixel circuit has essentially the same technical effect as the aforementioned display panel, for the sake of brevity, the technical effect of this driving method will not be described again here.

[0169] This application also provides a display device. As shown in FIG15, the display device includes: a power supply component 100, and a display panel 000 as described in the above embodiments.

[0170] The power supply component 100 is coupled to the display panel 000 and is used to supply power to the display panel 000.

[0171] Optionally, the display device can be an OLED display device or an active-matrix organic light-emitting diode (AMOLED) display device, etc. Among them, OLED display technology has gained widespread market acceptance due to its advantages such as high resolution and high contrast.

[0172] Optionally, the display device may also include any product or component with display functionality, such as a mobile phone, tablet computer, television, or monitor.

[0173] It is understandable that, since the display device has essentially the same technical effect as the aforementioned display panel, for the sake of brevity, the technical effect of the display device will not be described again here.

[0174] It is understood that the terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0175] For example, the words “first,” “second,” or “third,” and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0176] When we say that a component is "coupled" or "coupled" to another component, it can be directly coupled or coupled to other components, or there may be intermediate components. In addition, the term "coupled" or "coupled" as used here can include wireless coupling or wireless coupling.

[0177] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0178] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0179] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0180] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, the display panel comprising: A substrate, and a plurality of pixels located on one side of the substrate, each pixel comprising: a pixel circuit and a light-emitting element, the pixel circuit comprising: A switching circuit is coupled to a switch control line, a reference power line and a first node, respectively, and is used to control the connection and disconnection of the reference power line and the first node in response to a switch control signal provided by the switch control line. A control circuit is coupled to a gate line, a data line, a first light-emitting control line, a first node, a second node, a third node, and a fourth node, respectively. When the reference power line is connected to the first node, it adjusts the potential of the third node based on a reference power signal provided by the reference power line, and also adjusts the potential of the second node. It is used to control the connection and disconnection of the data line and the second node in response to a gate drive signal provided by the gate line, and to control the connection and disconnection of the third node and the fourth node in response to a first light-emitting control signal provided by the first light-emitting control line. The fourth node is coupled to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is coupled to a pull-down power line. The driving circuit has a control terminal coupled to the second node, an input terminal coupled to the driving power line, and an output terminal coupled to the third node. It is used to transmit a light-emitting driving signal to the third node based on the driving power signal provided by the driving power line and the potential of the second node. In this configuration, the pixel circuits of at least two pixels share the same switching circuit.

2. The display panel of claim 1, wherein, The plurality of pixel arrays are arranged such that at least two pixels in at least one row share the same switching circuit.

3. The display panel of claim 2, wherein, In a row of pixels, the pixel circuits of some pixels and the pixel circuits of other pixels share different switching circuits, and the different switching circuits are located on both sides of the row of pixels in the pixel row direction.

4. The display panel of claim 3, wherein, In a row of pixels, the number of pixels in one group and the number of pixels in another group that share different switching circuits are the same.

5. The display panel according to any one of claims 1 to 4, wherein, The substrate has a display area and an edge area that at least partially surrounds the display area; The switching circuit shared by the pixel circuits of at least two pixels is located in the edge region or in the display area.

6. The display panel of claim 5, wherein, The display panel further includes: a gate driving circuit located on one side of the substrate and in the edge region, the gate driving circuit being coupled to the gate line and used to provide the gate driving signal to the gate line; The switching circuit shared by the pixel circuits of at least two pixels is located in the edge region, and is located on the side of the gate driving circuit closer to the display area, or on the side of the gate driving circuit farther away from the display area.

7. The display panel according to any one of claims 1 to 6, wherein, The switching circuit includes: a switching transistor; The gate of the switching transistor is coupled to the switching control line, the first terminal of the switching transistor is coupled to the reference power supply line, and the second terminal of the switching transistor is coupled to the first node.

8. The display panel according to any one of claims 1 to 6, wherein, The switching circuit includes: a first switching transistor and a second switching transistor; the switching control line includes: a first switching control line and a second switching control line. The gates of the first switching transistor and the second switching transistor are coupled to the first switching control line and the second switching control line, respectively. The first terminals of the first switching transistor and the second switching transistor are both coupled to the reference power line. The second terminals of the first switching transistor and the second switching transistor are both coupled to the first node.

9. The display panel according to any one of claims 1 to 8, wherein The control circuit is also coupled between the driving power line and the input terminal of the driving circuit, and is also coupled to the second light emission control line, and is used to control the on / off state of the driving power line and the input terminal of the driving circuit in response to the second light emission control signal provided by the second light emission control line. The control circuit includes: An adjustment sub-circuit is coupled to the first node, the second node and the third node respectively, and is used to adjust the potential of the third node based on the reference power signal when the reference power line is turned on with the first node, and to adjust the potential of the second node. A data writing sub-circuit is coupled to the gate line, the data line and the second node respectively, and is used to control the on / off state of the data line and the second node in response to the gate drive signal; The first light-emitting control sub-circuit is coupled to the first light-emitting control line, the third node and the fourth node respectively, and is used to control the on / off state of the third node and the fourth node in response to the first light-emitting control signal. The second light-emitting control sub-circuit is coupled to the second light-emitting control line, the driving power line, and the input terminal of the driving circuit, respectively, and is used to control the on / off state of the driving power line and the input terminal of the driving circuit in response to the second light-emitting control signal.

10. The display panel of claim 9, wherein, The regulating sub-circuit includes a first capacitor and a second capacitor; the data writing sub-circuit includes a data writing transistor; the first light-emitting control sub-circuit includes a first light-emitting control transistor; the second light-emitting control sub-circuit includes a second light-emitting control transistor. The first plate of the first capacitor is coupled to the second node, and the second plate of the first capacitor is coupled to the third node; The first plate of the second capacitor is coupled to the first node, and the second plate of the second capacitor is coupled to the third node; The gate of the data writing transistor is coupled to the gate line, the first terminal of the data writing transistor is coupled to the data line, and the second terminal of the data writing transistor is coupled to the second node. The gate of the first light-emitting control transistor is coupled to the first light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to the third node, and the second electrode of the first light-emitting control transistor is coupled to the fourth node. The gate of the second light-emitting control transistor is coupled to the second light-emitting control line, the first terminal of the second light-emitting control transistor is coupled to the driving power supply line, and the second terminal of the second light-emitting control transistor is coupled to the input terminal of the driving circuit.

11. The display panel according to any one of claims 1 to 10, wherein, The pixel circuit also includes: A first reset circuit is coupled to a first reset line, a first initial power line, and at least one target node among the third node and the fourth node, and is used to control the connection and disconnection of the first initial power line and the at least one target node in response to a first reset signal provided by the first reset line. The second reset circuit is coupled to the second reset line, the reference power line and the second node respectively, and is used to control the on / off state of the reference power line and the second node in response to the second reset signal provided by the second reset line.

12. The display panel of claim 11, wherein, The first reset circuit includes a first reset transistor; the second reset circuit includes a second reset transistor. The gate of the first reset transistor is coupled to the first reset line, the first terminal of the first reset transistor is coupled to the first initial power line, and the second terminal of the first reset transistor is coupled to the at least one target node. The gate of the second reset transistor is coupled to the second reset line, the first terminal of the second reset transistor is coupled to the reference power line, and the second terminal of the second reset transistor is coupled to the second node.

13. The display panel of claim 11 or 12, wherein, When the target node is the fourth node, the pixel circuit further includes: The third reset circuit is coupled to the first reset line, the second initial power line and the third node respectively, and is used to control the connection and disconnection of the second initial power line and the third node in response to the first reset signal.

14. The display panel of claim 13, wherein, The third reset circuit includes: a third reset transistor; The gate of the third reset transistor is coupled to the first reset line, the first terminal of the third reset transistor is coupled to the second initial power line, and the second terminal of the third reset transistor is coupled to the third node.

15. The display panel of any of claims 11 to 14, wherein, The switch control line is shared with the gate line, the first reset line, or the second reset line.

16. The display panel of any of claims 11 to 15, wherein, The reference power line is shared with the drive power line, the reference power line, the first initial power line, or the second initial power line.

17. The display panel of any of claims 1 to 16, wherein, The driving circuit includes: a driving transistor; The gate of the driving transistor is coupled to the second node as the control terminal of the driving circuit, the first terminal of the driving transistor is coupled to the driving power line as the input terminal of the driving circuit, and the second terminal of the driving transistor is coupled to the third node as the output terminal of the driving circuit.

18. The display panel of any of claims 1 to 17, wherein, The pixel circuit includes N-type transistors.

19. A driving method for a pixel circuit in a display panel, applied to the pixel circuit of a display panel as described in any one of claims 1 to 18; the method comprising: During the non-light-emitting phase, the potential of the switch control signal provided by the switch control line is the first potential. The switch circuit responds to the switch control signal at the first potential, controls the reference power line to conduct with the first node, and the control circuit adjusts the potential of the third node based on the reference power signal provided by the reference power line, and also adjusts the potential of the second node. During the light-emitting phase, the potential of the switch control signal provided by the switch control line is the second potential. The switch circuit responds to the switch control signal at the second potential and controls the reference power line to disconnect from the first node.

20. A display device comprising: A power supply assembly, and a display panel as claimed in any one of claims 1 to 18. The power supply assembly is coupled to the display panel and configured to supply power to the display panel.

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