Semiconductor device

Abstract

The present invention provides a semiconductor device that has a novel configuration. A p-channel transistor and one n-channel transistor have a first semiconductor layer that contains silicon. A second n-channel transistor has a second semiconductor layer that contains indium oxide. One of either the source or the drain of the second n-channel transistor is electrically connected to one of either the source or the drain of the first n-channel transistor. The other of either the source or the drain of the second n-channel transistor is electrically connected to a second power line. A signal line electrically connected to the gate of the second n-channel transistor has a function of conveying a signal for turning off the second n-channel transistor during a period in which a logic circuit is inactive. A first power line is provided in a layer below the layer in which the logic circuit is provided. The second power line is provided in a layer above the layer in which the logic circuit is provided.

Description

Semiconductor Devices

[0001] This specification describes semiconductor devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, efforts to combat global warming have become increasingly important. Energy consumption continues to increase, and carbon dioxide emissions, one of the causes of global warming, have yet to be reduced. Simply reducing energy consumption may actually result in a loss of convenience. To reduce energy consumption without sacrificing convenience, low-power consumption technologies are becoming extremely important.

[0004] In logic circuits that perform arithmetic processing, such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units), transistors are becoming increasingly miniaturized and integrated to improve performance. Logic circuits have a circuit structure (also called CMOS (Complementary Metal-Oxide-Semiconductor)) that combines n-channel transistors (also called nMOS) and p-channel transistors (also called pMOS). In CMOS, power consumption increases due to factors such as leakage currents that accompany miniaturization of transistors and through currents that accompany switching between the on and off states of transistors.

[0005] As a countermeasure against leakage current due to miniaturization, transistors such as FinFET structure and GAA (Gate All Around) structure are being put into practical use. Furthermore, as an integration technology to further improve performance, three-dimensional packaging technology for stacking transistors is being considered. For example, a complementary field-effect transistor (CFET) has been proposed, in which transistors with a GAA nanosheet structure are stacked vertically on a silicon substrate (see, for example, Patent Document 1 and Non-Patent Document 1).

[0006] International Publication No. 2019 / 112952

[0007] J. Park et al., "First demonstration of 3-dimensional stacked FET with top / bottom source-drain isolation and stacked n / p metal gate," IEDM2023. Takashi Koida, "High-mobility transparent conductive film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] Technologies such as FinFET, GAA nanosheet, and CFET are important for miniaturizing transistors and achieving high integration. However, in the case of CMOS, a circuit structure that combines nMOS and pMOS, leakage current increases as the number of transistors increases. To prevent this leakage current, power gating, which cuts off leakage current when the logic circuit is inactive, is effective.

[0009] However, when power gating transistors are arranged in units of logic circuits, there is a risk that the integration level will decrease as the number of transistors increases. Alternatively, there is a risk that power consumption will increase due to leakage current from the power gating transistors themselves. Alternatively, there is a risk that the operating speed will decrease if the current supply capacity of the power gating switches is low. Alternatively, there is a risk that the number of signal lines for controlling the power gating transistors will increase in addition to the signal lines for transmitting input and output signals for controlling the logic circuit and the signal lines for transmitting the power supply potential for operating the logic circuit, and the number of signal lines for transmitting signals for controlling the power gating transistors will increase, resulting in complex wiring between the signal lines and the transistors.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which transistors for power gating can be arranged in units of logic circuits without reducing the degree of integration of the transistors. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which power gating transistors themselves can consume less power due to leakage current. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which a decrease in operating speed is suppressed by increasing the current supply capability of a transistor for power gating. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which wiring between a signal line and a transistor can be efficiently arranged.

[0011] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0012] One embodiment of the present invention includes a logic circuit including a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line for supplying a control signal to the logic circuit; a first power supply line for supplying a high power supply potential; and a second power supply line for supplying a low power supply potential. The p-channel transistor and the first n-channel transistor have a first semiconductor layer containing silicon, the second n-channel transistor has a second semiconductor layer containing indium oxide, and one of a source and a drain of the second n-channel transistor is connected to the source of the first n-channel transistor. a first signal line electrically connected to the gate of the second n-channel transistor, the first signal line having a function of supplying a signal for turning off the second n-channel transistor during a period when the logic circuit is inactive; the first power supply line being provided below a layer in which the logic circuit is provided; and the second power supply line being provided above a layer in which the logic circuit is provided.

[0013] One embodiment of the present invention includes a logic circuit including a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line for supplying a control signal to the logic circuit; a first power supply line for supplying a high power supply potential; and a second power supply line for supplying a low power supply potential. The p-channel transistor and the first n-channel transistor have a first semiconductor layer containing silicon. The second n-channel transistor has a second semiconductor layer containing indium oxide. One of a source or a drain of the second n-channel transistor is connected to one of a source or a drain of the first n-channel transistor. a first signal line electrically connected to the gate of the second n-channel transistor, one of the source and drain of the p-channel transistor electrically connected to a first power supply line, one of the source and drain of the second n-channel transistor electrically connected to a second power supply line, and a first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal for turning off the second n-channel transistor during a period when the logic circuit is not operating, the first power supply line being provided in a layer below the layer in which the p-channel transistor is provided, and the second power supply line being provided in a layer above the layer in which the second n-channel transistor is provided.

[0014] One embodiment of the present invention includes a logic circuit including a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line for supplying a control signal to the logic circuit; a first power supply line for supplying a high power supply potential; and a second power supply line for supplying a low power supply potential. The p-channel transistor and the first n-channel transistor have a first semiconductor layer containing silicon. The second n-channel transistor has a second semiconductor layer containing indium oxide. One of a source and a drain of the second n-channel transistor is electrically connected to one of a source and a drain of the first n-channel transistor. one of the source and drain of the p-channel transistor is electrically connected to a first power supply line, the other of the source and drain of the second n-channel transistor is electrically connected to a second power supply line, a first signal line electrically connected to a gate of the second n-channel transistor has a function of supplying a signal to turn off the second n-channel transistor during a period when the logic circuit is not operating, the first power supply line and the second power supply line are each provided in a layer below the layer in which the p-channel transistor is provided, and the signal lines are each provided in a layer above the layer in which the second n-channel transistor is provided.

[0015] In one embodiment of the present invention, the semiconductor device preferably has a structure in which the first semiconductor layer is surrounded by the gate of a p-channel transistor and the gate of one n-channel transistor.

[0016] In one embodiment of the present invention, the semiconductor device preferably includes a first power supply line and a second power supply line, each of which includes a third power supply line that supplies a high power supply potential and a fourth power supply line that supplies a low power supply potential, the third power supply line being provided in a layer below a layer in which a p-channel transistor is provided, and the fourth power supply line being provided in a layer above a layer in which a second n-channel transistor is provided.

[0017] In one embodiment of the present invention, a semiconductor device preferably includes a third n-channel transistor, and a second signal line electrically connected to the gate of the first n-channel transistor and the gate of the p-channel transistor is electrically connected to one of the source and the drain of the third n-channel transistor, and has a function of holding the potential of the second signal line by turning off the third n-channel transistor.

[0018] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0019] According to one embodiment of the present invention, a semiconductor device with a novel structure can be provided. According to another embodiment of the present invention, a semiconductor device with a novel structure in which a transistor for power gating is provided for each logic circuit without reducing the integration density of the transistor can be provided. According to one embodiment of the present invention, a semiconductor device with a novel structure in which power consumption due to leakage current of the transistor for power gating itself is reduced can be provided. According to one embodiment of the present invention, a semiconductor device with a novel structure in which a decrease in operating speed is suppressed by increasing the current supply capability of the transistor for power gating can be provided. According to one embodiment of the present invention, a semiconductor device with a novel structure in which wiring between a signal line and a transistor can be efficiently arranged can be provided.

[0020] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings in this specification.

[0021] FIG. 1A is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 1B is a timing chart illustrating a semiconductor device of one embodiment of the present invention. FIG. 2 is a schematic diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 4 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 5 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 7 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 8A is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 8B is a timing chart illustrating a semiconductor device of one embodiment of the present invention. FIG. 9A is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 9B is a timing chart illustrating a semiconductor device of one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 11 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIGS. 12A to 12C are circuit diagrams illustrating a semiconductor device of one embodiment of the present invention. FIG. 13 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 14 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention. FIG. 15A is a plan view showing an example of a semiconductor device. FIGS. 15B to 15D are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIGS. 16B to 16D are cross-sectional views showing an example of a semiconductor device. FIG. 17A is a plan view showing an example of a semiconductor device. FIGS. 17B to 17D are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing an example of a semiconductor device. FIGS. 19A and 19B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 19C is a cross-sectional view illustrating an indium oxide film. FIGS. 20A to 20D are cross-sectional views showing an example of a semiconductor device. FIG. 21 is a cross-sectional view showing an example of a semiconductor device. FIG. 22 is a cross-sectional view showing an example of a semiconductor device. FIGS. 23A and 23B are diagrams illustrating an example of an electronic component. FIGS. 24A to 24C are diagrams illustrating an example of a mainframe computer. FIG. 24D is a diagram illustrating an example of space equipment.FIG. 24E is a diagram illustrating an example of a storage system applicable to a data center.

[0022] Hereinafter, embodiments of the present invention will be described. However, one aspect of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one aspect of the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0023] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0024] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0025] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0026] Furthermore, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", or "[m, n]" may be added to the reference numeral. For example, the second wiring GL is described as wiring GL[2].

[0027] Embodiment 1 A structure, operation, and the like of a semiconductor device that is one embodiment of the present invention will be described.

[0028] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor and a logic circuit including the semiconductor element are one embodiment of a semiconductor device.

[0029] One embodiment of the present invention can be applied to a logic circuit having a CMOS circuit configuration, such as a basic logic gate such as a NOT (also referred to as an inverter or a NOT circuit), a NAND (also referred to as a NAND circuit), a NOR (also referred to as a NOR circuit), an AND (also referred to as an AND circuit), or an OR (also referred to as a NAND circuit). The present invention can also be applied to circuits such as a flip-flop, a register, or a shift register, which are combinations of these logic gates. Furthermore, the present invention can also be applied to a large-scale arithmetic circuit, which is a combination of a plurality of these circuits.

[0030] <Configuration Example and Operation Example of Semiconductor Device> Figure 1A shows an example of a semiconductor device that functions as a NOT circuit. The NOT circuit 100 shown in Figure 1A includes transistors 101, 102, and 106. As shown in Figure 1A, the transistor 101 is a p-channel transistor (pMOS), and the transistors 102 and 106 are n-channel transistors (nMOS). The transistor 102 is also referred to as a first n-channel transistor, and the transistor 106 is also referred to as a second n-channel transistor. Figure 1A also shows power supply lines VHL and VLL, and signal lines INL1, INL2, and OUTL.

[0031] The transistors of the NOT circuit 100 and the power supply lines VHL and VLL, and the transistors of the NOT circuit 100 and the signal lines INL1, INL2, and OUTL are connected as shown in FIG. 1A.

[0032] Specifically, the gate of transistor 101 and the gate of transistor 102 are connected to signal line INL2. The gate of transistor 106 is connected to signal line INL1. One of the source or drain of transistor 101 is connected to signal line OUTL. One of the source or drain of transistor 102 is connected to signal line OUTL. The other of the source or drain of transistor 101 is connected to power supply line VHL. The other of the source or drain of transistor 102 is connected to one of the source or drain of transistor 106. The other of the source or drain of transistor 106 is connected to power supply line VLL.

[0033] The power supply line VHL is a power supply line that transmits a high power supply potential and is also referred to as a first power supply line. The power supply line VLL is a power supply line that transmits a low power supply potential and is also referred to as a second power supply line.

[0034] The signal line INL1 is a wiring that transmits a signal that controls the on state (conducting state) or off state (non-conducting state) of the transistor 106. The transistor 106 functions as a switch. The transistor 106 is turned on when the potential of the signal line INL1 is at H (High) level and turned off when the potential is at L (Low) level. One of the source or drain of the transistor 106 is directly connected to the other of the source or drain of the transistor 102.

[0035] By controlling the signal line INL1, the current flowing between the power supply line VHL and the power supply line VLL is cut off, enabling power gating of each logic circuit such as the NOT circuit 100. When the potential of the signal line INL1 is at H level, the NOT circuit 100 functions as a NOT circuit, and when the potential of the signal line INL1 is at L level, the NOT circuit 100 functions as a circuit that outputs the logic of the immediately preceding state. Note that power gating here refers to the operation of cutting off leakage current that flows from the signal line OUTL that transmits the output signal to the power supply line VLL.

[0036] The signal line INL2 is a wiring that transmits an input signal to the NOT circuit, which is a logic circuit. The signal line OUTL is a wiring that transmits an output signal from the NOT circuit, which is a logic circuit.

[0037] The potential of the signal line INL1 is preferably set to the L level during a period when the input signal to the logic circuit is at the L level and the input signal is not switched. The potential of the signal line INL1 is preferably kept at the H level during other periods. This configuration can reduce leakage current flowing through the transistor 102 when the input signal is at the L level and the output signal is continuously at the H level.

[0038] Depending on the type of logic circuit, there may be a plurality of transistors corresponding to the transistor 102. In this case, a plurality of transistors 106 are also provided in accordance with the number of the transistors 102. The signal line INL1 is connected to the plurality of transistors 106.

[0039] 1A, when the potential of the signal line INL1 is at H level and the signal line INL2 is at H level, the transistor 101 is in the OFF state and the transistor 102 is in the ON state, and when the signal line INL2 is at L level, the transistor 102 is in the OFF state. As a result, when the signal line INL2 is at H level, the signal line OUTL is at L level, and when the signal line INL2 is at L level, the signal line OUTL is at H level.

[0040] As described above, when the NOT circuit 100 shown in FIG. 1A is power-gated, that is, when the potential of the signal line INL2 is continuously at the L level, the signal line INL1 is set to the L level. The transistor 101 is turned on, and the transistors 102 and 106 are turned off. As a result, the signal line INL2 is at the L level, and the signal line OUTL is at the H level. Since the transistor 106 is also turned off in addition to the transistor 102, the leakage current in the transistor 102 can be reduced. As a result, fluctuations in the H level potential of the signal line OUTL can be reduced.

[0041] 1A does not perform power gating. Therefore, the signal line INL1 remains at the H level. The transistor 101 is in the OFF state, and the transistors 102 and 106 are in the ON state. As a result, the signal line INL2 becomes the H level and the signal line OUTL becomes the L level.

[0042] A NOT circuit is a logic gate with one input and one output, but some logic gates may have multiple inputs and multiple outputs. In this case, the logic gate has multiple transistors corresponding to the transistors 101 and 102. The signal line INL2 is configured to have multiple transistors corresponding to the multiple transistors 101 and 102.

[0043] 1B is a timing chart illustrating the operation of the NOT circuit of FIG. 1A. This diagram illustrates the potential of a signal transmitted through a signal line INL1 that switches the transistor 106 between an on state and an off state, the potential of an input signal of the NOT circuit 100 transmitted through a signal line INL2, and the potential of an output signal of the NOT circuit 100 transmitted through a signal line OUTL.

[0044] 1B, period T0 is the non-operating period of the NOT circuit (before operation), period T1 is the operating period of the NOT circuit, and period T2 is the non-operating period of the NOT circuit (after operation). The non-operating period is a period during which the input signal to the logic circuit is not switched. The operating period is a period during which the input signal to the logic circuit is switched.

[0045] During the non-operating period of the period T0, the potential of the signal line INL2 remains at the L level (L in the figure) and the potential is not switched. Therefore, power gating of the NOT circuit 100 can be performed, and the potential of the signal line INL1 is set to the L level (L in the figure) during the period T0. The transistor 106 is turned off. The current flowing between the signal line OUTL and the power supply line VLL is cut off, and power gating of each logic circuit such as the NOT circuit 100 can be achieved.

[0046] During the operation period of period T1, the potential of the signal line INL2 is switched. Therefore, power gating of the NOT circuit 100 is not performed, and the potential of the signal line INL1 is set to the H level (H in the figure). The transistor 106 is turned on. It is possible to change the potential of the output signal of the signal line OUTL in response to a change in the potential of the input signal of the signal line INL2. In the example of FIG. 1B, the logic circuit is a NOT circuit, and in this case, the logic of the input signal of the signal line INL2 can be inverted to produce the output signal of the signal line OUT.

[0047] During the non-operating period of the period T2, the potential of the signal line INL2 remains at the L level (L in the figure) and the potential is not switched. Therefore, power gating of the NOT circuit 100 can be performed, and the potential of the signal line INL1 is set to the L level during the period T2. The transistor 106 is turned off. The current flowing between the signal line OUTL and the power supply line VLL is cut off, and power gating of each logic circuit such as the NOT circuit 100 can be achieved.

[0048] In one embodiment of the present invention, when the signal line INL2, which is an input signal, is at an L level and the signal line OUTL outputs an H level during a non-operation period in which power gating is performed for each logic circuit, leakage current flowing through the transistor 102 can be reduced. Therefore, power consumption due to leakage current flowing through the transistor 102 can be reduced. Furthermore, the potential of the signal line OUTL can be easily maintained at an H level. Therefore, the capacitance value of a storage capacitor connected to the signal line OUT can be reduced in order to maintain the potential. As a result, high-speed operation of the logic circuit can be achieved.

[0049] In addition, during a period in which the signal line INL2 maintains the L level, the signal for controlling power gating transmitted to the signal line INL1 is switched to the L level. Also, during a period in which the signal line INL2, which is an input signal, is at the H level and a period in which the signal line IHL2, which is an input signal, is frequently switched between the H level and the L level, the signal for controlling power gating transmitted to the signal line INL1 is switched to the H level. This configuration makes it easier to maintain the H level potential of the signal line OUTL, and reduces the frequency of switching the signal for controlling power gating, thereby enabling lower power consumption.

[0050] In the case of a multi-input, multi-output logic circuit, there may be a plurality of wirings corresponding to the signal line INL2 and the signal line OUTL. In this case, when the plurality of signal lines INL2 are all at the L level and the plurality of signal lines OUTL are all at the H level, the signal for controlling power gating transmitted to the signal line INL1 is set to the L level. This configuration makes it easier to maintain the H level potential of the signal line OUTL, reduces the frequency of switching the signal for controlling power gating, and reduces power consumption.

[0051] 2 is a diagram schematically illustrating a three-dimensional structure of the logic circuit exemplified by the NOT circuit 100 in Fig. 1A. Fig. 3 is a circuit diagram illustrating the connection relationship between transistors 101, 102, and 106, signal lines INL1, INL2, and OUTL, and power supply lines VHL and VLL, which are stacked in the Z direction in accordance with the three-dimensional structure of the NOT circuit 100 in Fig. 2.

[0052] In the three-dimensional structure of the logic circuit illustrated in Fig. 2, insulating layers around the conductive layers and semiconductor layers are omitted for simplicity of illustration. Also, some semiconductor layers in Fig. 2 are illustrated with dotted lines to show that they are surrounded by conductive layers via insulating layers.

[0053] 2 and 3, in order to explain the arrangement of each component, the direction perpendicular to the surface of the substrate on which the NOT circuit 100 is provided is defined as the Z-axis direction. For ease of understanding, the Z-axis direction may be referred to as the direction perpendicular to the surface of the substrate in the specification. Note that "perpendicular" refers to a state in which the circuit is arranged at an angle of 85 degrees or more and 95 degrees or less.

[0054] In this specification and drawings, the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element. For example, in the schematic diagrams and circuit diagrams shown in Figures 2 and 3, the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the semiconductor device. The X direction, Y direction, and Z direction are perpendicular to each other.

[0055] 2, conductive layers functioning as a signal line INL2, a power supply line VHL, and a signal line OUTL are shown on the substrate side. The conductive layers functioning as the signal line INL2, the power supply line VHL, and the signal line OUTL are wirings provided on layer L1 in the schematic diagram shown in FIG.

[0056] The wiring provided in layer L1 corresponds to a conductive layer provided in a semiconductor substrate containing silicon, germanium, silicon-germanium, etc., or a Si-On-Insulator (SOI) substrate. The wiring provided in layer L1 can be formed, for example, by processing a silicon substrate and filling a trench with a conductor. When forming the power supply lines VHL and VLL by processing a silicon substrate, the width and depth of the wiring can be made larger than when the power supply lines VHL and VLL are provided in the upper layer, layer L5. This reduces the voltage drop associated with the placement of the power supply lines VHL and VLL.

[0057] In the schematic diagram shown in FIG. 2 , a conductive layer 101S, a semiconductor layer 101I, a conductive layer 101D, and a conductive layer 101G of the transistor 101 are illustrated above the conductive layers functioning as the signal line INL2, the power supply line VHL, and the signal line OUTL (insulating layers around the conductive layer 101S, the semiconductor layer 101I, the conductive layer 101D, and the conductive layer 101G are not shown). The conductive layer 101S and the conductive layer 101D are electrodes functioning as the source or drain of the transistor 101. The conductive layer 101G is an electrode functioning as the gate of the transistor 101. The semiconductor layer 101I is a semiconductor layer having a channel formation region of the transistor 101. The transistor 101 including the conductive layer 101S, the semiconductor layer 101I, the conductive layer 101D, and the conductive layer 101G is a transistor provided in layer L2 in the schematic diagram shown in FIG. 3 .

[0058] 2 and 3, the transistor 101 is connected to a signal line INL2 via, for example, conductive layers 101G and 101L. As shown in Figures 2 and 3, the transistor 101 is connected to a power supply line VHL via, for example, conductive layers 101S. As shown in Figures 2 and 3, the transistor 101 is connected to a signal line OUTL via, for example, conductive layers 101D and 101M.

[0059] In the schematic diagram shown in FIG. 2 , the conductive layer 102S, the semiconductor layer 102I, the conductive layer 102D, and the conductive layer 102G of the transistor 102 are shown above the transistor 101 having the conductive layer 101S, the semiconductor layer 101I, the conductive layer 101D, and the conductive layer 101G (insulating layers around the conductive layer 102S, the semiconductor layer 102I, the conductive layer 102D, and the conductive layer 102G are not shown). The conductive layer 102S and the conductive layer 102D are electrodes functioning as a source or a drain of the transistor 102. The conductive layer 102G is an electrode functioning as a gate of the transistor 102. The semiconductor layer 102I is a semiconductor layer having a channel formation region of the transistor 102. The transistor 102 having the conductive layer 102S, the semiconductor layer 102I, the conductive layer 102D, and the conductive layer 102G is a transistor provided in layer L3 of the schematic diagram shown in FIG. 3 .

[0060] 2 and 3, the transistor 102 is connected to the signal line INL2 via, for example, conductive layers 102G, 101G, and 101L. Since the conductive layer 102G is connected to the conductive layer 101G, the conductive layers can be shared. As shown in FIGS. 2 and 3, the transistor 102 is connected to the transistor 106 via the conductive layers 102S and 102L. As shown in FIGS. 2 and 3, the transistor 102 is connected to the signal line OUTL via the conductive layers 101D, 102N, 102M, and 101M.

[0061] 2 illustrates a configuration in which the layer L2 having the pMOS transistor 101 and the layer L3 having the nMOS transistor 102 are driven by the same conductive layer functioning as a gate. Alternatively, the layer L2 having the pMOS transistor 101 and the layer L3 having the nMOS transistor 102 may be formed on separate substrates and bonded together.

[0062] 2, transistors 101 and 102 are shown as having a GAA nanosheet structure. The GAA nanosheet structure allows the semiconductor layer to be surrounded by a conductive layer that functions as a gate, which allows for miniaturization and high integration of transistors.

[0063] The semiconductor layers 101I and 102I are preferably made of silicon. The transistors 101 and 102 having silicon in the semiconductor layers 101I and 102I are also referred to as Si transistors. When the semiconductor layers 101I and 102I are made of silicon, silicon and silicon germanium can be alternately stacked, and the silicon germanium can be used as a sacrificial layer that is selectively etched. Therefore, the semiconductor layers 101I and 102I can be surrounded by conductive layers 101G and 102G that function as gates.

[0064] The transistor 101 can be made a pMOS by selectively doping the semiconductor layer 101I with p-type impurities. The transistor 102 can be made an nMOS by selectively doping the semiconductor layer 102I with n-type impurities. As shown in Figure 2, a CFET can be formed by stacking the transistor 101, which is a pMOS with a GAA nanosheet structure, and the transistor 102, which is an nMOS with a GAA nanosheet structure, in the Z direction.

[0065] The conductive layers 101L, 101M, 102L, 102M, 102N, 101G, and 102G are preferably made of a material containing a metal element such as titanium or aluminum. The conductive layers 101S and 101D, as well as the conductive layers 102S and 102D, are preferably made of conductive silicon. When the semiconductor layers 101I and 102I are made of silicon, the conductive silicon can be formed by epitaxially growing the semiconductor layers 101I and 102I and adding an element that imparts conductivity to the silicon.

[0066] 2 shows the transistors 101 and 102 as having a GAA nanosheet structure, but other structures are also possible. The transistors 101 and 102 may have any structure that allows miniaturization and high integration, such as a FinFET structure or a planar structure.

[0067] In the schematic diagram shown in FIG. 2 , the conductive layer 106S, the semiconductor layer 106I, the conductive layer 106D, and the conductive layer 106G of the transistor 106 are shown above the transistor 102 having the conductive layer 102S, the semiconductor layer 102I, the conductive layer 102D, and the conductive layer 102G (insulating layers around the conductive layer 106S, the semiconductor layer 106I, the conductive layer 106D, and the conductive layer 106G are not shown). The conductive layer 106S and the conductive layer 106D are electrodes functioning as a source or a drain of the transistor 106. The conductive layer 106G is an electrode functioning as a gate of the transistor 106. The semiconductor layer 106I is a semiconductor layer having a channel formation region of the transistor 106. The transistor 106 having the conductive layer 106S, the semiconductor layer 106I, the conductive layer 106D, and the conductive layer 106G is a transistor provided in layer L4 in the schematic diagram shown in FIG. 3 .

[0068] 2 and 3, the transistor 106 is connected to the signal line INL1 via, for example, the conductive layer 106G and the conductive layer 102L. As shown in Figures 2 and 3, the transistor 106 is connected to the transistor 102 via the conductive layer 106S and the conductive layer 102L. As shown in Figures 2 and 3, the transistor 106 is connected to the power supply line VLL via the conductive layer 101D.

[0069] 2, the transistor 106 is illustrated as having a planar structure. A conductive layer functioning as a back gate may be provided in a region overlapping the conductive layer 106G across the semiconductor layer 106I. The transistor 106 may have any structure that allows for miniaturization and high integration of the transistor, and may have, for example, a planar structure, a vertical transistor, or a GAA nanosheet structure.

[0070] The conductive layers 106L, 106G, 106S, and 106D are preferably made of a material containing a metal element such as titanium or aluminum. The semiconductor layer 106I is preferably made of indium oxide. The transistor 106 having indium oxide in the semiconductor layer 106I is also referred to as an IO transistor. For a structural example of the IO transistor, refer to Embodiment 2 described later.

[0071] Alternatively, an oxide semiconductor such as In—Ga—Zn oxide (IGZO) can be used for the semiconductor layer 106I. A transistor including IGZO in the semiconductor layer 106I is called an IGZO transistor. The above-described transistor including indium oxide in the semiconductor layer 106I and the transistor including IGZO in the semiconductor layer 106I are collectively referred to as OS transistors.

[0072] Here, indium oxide used in the semiconductor layer of the IO transistor will be described.

[0073] An indium oxide film that can be used for the semiconductor layer 106I of the transistor 106 is a film through which one or both of hydrogen and oxygen move more easily than, for example, an In—Ga—Zn oxide film (IGZO film). Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. It can be said that an indium oxide film is a film that is more permeable to one or both of hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film that has a lower barrier property against one or both of hydrogen and oxygen than, for example, an IGZO film.

[0074] The indium oxide film is formed by heat treatment at a heating temperature of 400° C. for 8 hours, and the oxygen concentration is 1×10 ２０ atoms / cm ３ 2 x 10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm ３ 1x10 or more ２１ atoms / cm ３ The indium oxide film has a property of transmitting, for example, 1×10 ２０ atoms / cm ３ 2 x 10 or more ２１ atoms / cm ３ Below 2 × 10, preferably ２０ atoms / cm３ 1x10 or more ２１ atoms / cm ３ The following oxygen has the property of diffusing within the crystal grains.

[0075] Oxygen in the indium oxide film diffuses through the crystal grains and grain boundaries, and V present in the crystal grains or grain boundaries is removed. Ｏ Therefore, the electrical characteristics and reliability of the transistor can be improved.

[0076] The content of the first element in the semiconductor layer of the IO transistor is preferably low. Furthermore, the concentration of the first element in the semiconductor layer is preferably low. In particular, the concentration of the first element in the channel formation region is preferably low. Here, the first element is at least one of boron, carbon, aluminum, silicon, zinc, and gallium. That is, in the semiconductor layer, the concentration of any one of boron, carbon, aluminum, silicon, zinc, and gallium is preferably low, the concentrations of two selected from boron, carbon, aluminum, silicon, zinc, and gallium are more preferably low, and the concentrations of all of boron, carbon, aluminum, silicon, zinc, and gallium are even more preferably low. The concentration of the first element in the semiconductor layer is, for example, preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Note that the preferable concentration of the first element in the semiconductor layer can also be said to be the preferable concentration of the first element in the channel formation region.

[0077] By reducing the concentrations of boron, carbon, aluminum, and silicon in the semiconductor layer, the crystallinity of the semiconductor layer can be improved.

[0078] When the semiconductor layer of an IO transistor contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga-O structure. The Ga-O structure functions as an acceptor that traps electrons. Therefore, an IO transistor containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, by lowering the gallium concentration in the semiconductor layer, the variation in threshold voltage in the PBTS test can be reduced. This results in a transistor with high reliability against positive bias application. Note that when the semiconductor layer of an IO transistor contains zinc atoms, the same phenomenon as when the semiconductor layer contains gallium atoms may occur.

[0079] Furthermore, aluminum atoms, gallium atoms, and zinc atoms have stronger bonding strength with oxygen atoms than indium atoms, so that by reducing the concentrations of aluminum, gallium, and zinc in the indium oxide film, it is possible to prevent the oxygen permeability from decreasing.

[0080] Furthermore, impurities such as the first element contained in the indium oxide film can become crystal nuclei. Reducing the impurities in the indium oxide film as much as possible can reduce the number of crystal nuclei and promote the growth of large crystal grains.

[0081] Furthermore, when the indium oxide film is a polycrystalline film, the first element segregates at the grain boundaries to form an oxide containing the first element. Since the oxide has insulating properties, the on-state current or field-effect mobility of the transistor may be reduced. By reducing the first element in the indium oxide film as much as possible, the on-state current or field-effect mobility of the transistor can be increased.

[0082] Furthermore, by reducing the impurities in the indium oxide film, impurity scattering can be suppressed. Therefore, a transistor with high field-effect mobility can be realized. For example, by setting the concentration of the first element in the semiconductor layer in the above preferred range, the field-effect mobility of the transistor can be increased to 100 cm ２ / (V·s) or more, preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more. Therefore, an OS transistor including an IO transistor can have excellent field-effect mobility.

[0083] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide with a wide band gap for a semiconductor layer, the off-state current of a transistor can be reduced, and the power consumption of a semiconductor device can be sufficiently reduced.

[0084] An IO transistor is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in an IO transistor are electrons. Assuming that the carrier relaxation time is a constant value, the smaller the effective mass of the electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide with a small effective mass of electrons in the semiconductor layer of a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0085] The effective mass of electrons in indium oxide is small. Therefore, by using indium oxide, which has a small effective mass of electrons, for a semiconductor layer, it is possible to realize a transistor with a large on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also called f characteristics). Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in, for example, silicon. Therefore, from the viewpoint of the effective mass of electrons, the f characteristics of a transistor using indium oxide in a channel formation region are higher than the f characteristics of a Si transistor.

[0086] Indium oxide has a large effective mass of holes. Therefore, by using indium oxide, which has a large effective mass of holes, for a semiconductor layer, a transistor with extremely small off-state current can be realized. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, from the viewpoint of the effective mass of holes, the off-state current of an IO transistor is sufficiently smaller than the off-state current of a Si transistor.

[0087] In the IO transistor, the off-state current value per 1 μm of channel width at room temperature is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８ Therefore, an OS transistor including an IO transistor can have an extremely low off-state current per 1 μm of channel width at 85° C.

[0088] As described above, the transistor 106 can be an OS transistor, which has both field-effect mobility comparable to that of a Si transistor and extremely low leakage current. Therefore, when a CMOS logic circuit is configured using a pMOS Si transistor and an nMOS OS transistor, the transistor sizes can be approximately the same. By using a combination of an OS transistor and a Si transistor, a CMOS logic circuit that consumes low power and operates at high speed can be realized.

[0089] In addition, since the IO transistor has a semiconductor layer with excellent crystallinity, it can be a highly reliable transistor. By using the IO transistor in combination with a Si transistor, a highly reliable CMOS logic circuit capable of high-speed operation can be realized.

[0090] The above is a description of the transistor including indium oxide in the semiconductor layer.

[0091] 2, conductive layers functioning as a signal line INL1 and a power supply line VLL are illustrated above the transistor 106, which includes the conductive layer 106S, the semiconductor layer 106I, the conductive layer 106D, and the conductive layer 106G. The conductive layers functioning as the signal line INL1 and the power supply line VLL are wirings provided in the layer L5 in the schematic diagram shown in FIG.

[0092] The circuit diagram shown in Figure 3 illustrates a configuration in which transistors 101, 102, and 106 included in a logic circuit such as a NOT circuit are provided in layers L2 to L4, and a power supply line VHL for transmitting a high power supply potential is provided in layer L1. The circuit diagram shown in Figure 3 illustrates a configuration in which transistors 101, 102, and 106 included in a logic circuit such as a NOT circuit are provided in layers L2 to L4, and a power supply line VLL for transmitting a low power supply potential is provided in layer L5. This configuration allows the power supply line, logic circuit, and signal line to be arranged so that they overlap in the Z direction. This allows for shorter wiring between the logic circuit and the signal line, and between the logic circuit and the power supply line. Furthermore, even when a transistor for controlling power gating and a wiring for controlling the transistor are added, it is possible to suppress a decrease in integration density and an increase in layout area.

[0093] 3 illustrates a configuration in which a pMOS transistor 101 is provided in layer L2, and a power supply line VHL that transmits a high power supply potential is provided in layer L1. The circuit diagram in FIG. 3 illustrates a configuration in which an nMOS transistor 106 is provided in layer L4, and a power supply line VLL that transmits a low power supply potential is provided in layer L5. The circuit diagram in FIG. 3 illustrates a configuration in which the transistor 106 is provided in layer L4, and a signal line INL1 that transmits a signal that controls the transistor 106 is provided in layer L5. This configuration can shorten the length of the wiring between the signal line and the transistor, and the length of the wiring between the power supply line and the transistor.

[0094] The figure also illustrates a configuration in which transistor 101, which is controlled by the same signal, is provided on layer L2, and transistor 102, which is provided on layer L3. This configuration allows the wiring connecting transistor 101 and transistor 102, which are provided on layers adjacent in the Z direction, to be short. The figure also illustrates a configuration in which signal line INL1, which transmits a signal controlling transistors 101 and 102, is provided on layer L1. This configuration allows the length of the wiring between the signal line and the transistor to be shorter than when signal line INL1 is provided on an upper layer, for example, layer L5.

[0095] As described above, by providing the transistor 106 that functions as a switch for controlling power gating on a logic circuit including the transistors 101 and 102, transistors for power gating can be arranged in units of logic circuits without reducing the degree of integration of the transistors. Furthermore, by using an OS transistor that has both field-effect mobility comparable to that of a Si transistor and extremely low leakage current as the transistor 106, power consumption due to leakage current during power gating can be reduced and a decrease in operating speed during normal operation can be suppressed.

[0096] <Configuration Example of Connection Between Transistor and Signal Line> Although an example of a semiconductor device to which one embodiment of the present invention is applied has been described above in which a power supply line and a signal line are arranged in a layer below a logic circuit, one embodiment of the present invention is not limited to this. Hereinafter, a configuration example of connection between a transistor and a signal line according to one embodiment of the present invention, which is different from the configuration example shown in FIG. 3, will be described. Note that the above description will be used for the same configuration as that shown in FIG. 3, and repeated description may be omitted.

[0097] FIG. 4 is a circuit diagram in which signal lines INL1, INL2, and OUTL are arranged in layer L5, which is an upper layer of layers L2 to L4 in which transistors 101, 102, and 106 constituting the logic circuit exemplified by the NOT circuit 100 in FIG. 3 are provided, and power supply lines VHL and VLL are arranged in layer L1, which is a lower layer.

[0098] The signal lines INL1, INL2, and OUTL provided on the layer L5 can be more easily connected to the wirings provided on the multiple layers above the layer L5 than the wirings provided on the layers L1 to L4. Therefore, by arranging the signal lines INL1, INL2, and OUTL that transmit signals of the logic circuit on the layer L5, the degree of freedom in arranging the wirings for connection within the logic circuit can be increased.

[0099] By arranging the signal lines INL1, INL2, and OUTL in a multi-layer structure in multiple layers above the layer L5, it is possible to reduce the influence of noise between wirings that transmit signals. Furthermore, by arranging the signal lines INL1, INL2, and OUTL in a multi-layer structure in multiple layers above the layer L5, it is possible to reduce the influence on the signal lines INL1, INL2, and OUT caused by switching the on / off states of the transistors provided in the layers L2 to L4.

[0100] Furthermore, the power supply lines VHL and VLL that transmit the power supply potential are arranged across the region in which the logic circuit is provided. When the power supply lines VHL and VLL that transmit the power supply potential are formed by processing a silicon substrate or the like corresponding to the lower layer L1, the width and depth of the power supply lines VHL and VLL can be made wider than when they are provided in the upper layer L5. This makes it possible to reduce the voltage drop associated with the arrangement of the power supply lines VHL and VLL.

[0101] FIG. 5 is a circuit diagram in which power supply lines VHL and VLL are arranged both in layer L5, which is an upper layer of layers L2 to L4 in which transistors 101, 102, and 106 constituting the logic circuit exemplified by the NOT circuit in FIG. 4 are provided, and in layer L1, which is a lower layer.

[0102] By arranging the power supply lines VHL and VLL not only in the layer L1 but also in the upper layer L5, the voltage drop due to the arrangement of the power supply lines VHL and VLL can be further reduced. In addition, because the power supply lines VHL and VLL are arranged in multiple layers, such as the layers L1 and L5, transistors in layers close to the layer L5 can be connected to the power supply lines VHL and VLL of the layer L5, and transistors close to the layer L1 can be connected to the power supply lines VHL and VLL of the layer L1. This makes it easier to connect the transistors 101, 102, and 106 that constitute the logic circuit.

[0103] 6 is a circuit diagram in which the transistor 106 of the layer L4 in which the transistor 106 constituting the logic circuit exemplified as the NOT circuit 100 in FIG. 3 is provided is omitted in the logic circuit that functions as another NOT circuit 103.

[0104] Depending on the logic circuit, there may be cases where power gating is performed infrequently. In this case, a configuration is provided that includes a NOT circuit 100 having a transistor 106 and a NOT circuit 103 not having the transistor 106. In this configuration, compared to a case where the transistor 106 is provided as in the NOT circuit 100, the transistor 106 and the signal line INL1 can be partially omitted as in the NOT circuit 103. It is effective to apply this configuration to logic circuits in which power gating is not expected to reduce power consumption.

[0105] FIG. 7 is a circuit diagram in which the transistor 106 constituting the logic circuit exemplified by the NOT circuit 100 in FIG. 6 is provided in the layer L3.

[0106] 3 and 4, the case where two layers, L3 and L4, in which nMOS transistors are provided, are provided and different types of semiconductor layers are arranged has been described. However, when different types of semiconductor layers are arranged, they may be arranged in the same layer. For example, if the transistors 102 and 106 are both OS transistors, they may be arranged side by side in the same layer, L3 or L4. Furthermore, the layer having the nMOS Si transistor may be omitted.

[0107] In addition, one embodiment of the present invention can have a structure in which a function is added by connecting a transistor to a signal line of a logic circuit.

[0108] 8A illustrates a circuit diagram of a semiconductor device that functions as a NOT circuit described in FIG. 1A, to which a transistor 104A and a capacitor CS are added. Note that, in the configuration illustrated in FIG. 8A, the above description is applicable to the same configuration as in FIG. 1A, and repeated description may be omitted.

[0109] One of the source and drain of the transistor 104A is connected to a signal line INL2. The other of the source and drain of the transistor 104A is connected to one electrode of a capacitance element CS. The gate of the transistor 104A is connected to a signal line INS1. The other end of the capacitance element CS is connected to a constant potential line, for example, a ground line.

[0110] The signal line INS1 is a wiring that transmits a signal that controls the on / off state of the transistor 104A. The transistor 104A functions as a switch. The transistor 104A is turned on when the potential of the signal line INS1 is at an H level and turned off when the potential of the signal line INS1 is at an L level.

[0111] The transistor 104A is preferably an n-channel transistor, particularly an OS transistor. An OS transistor can have both field-effect mobility comparable to that of a Si transistor and extremely low leakage current. Therefore, by turning off the transistor 104A, a charge corresponding to the potential of a signal transmitted to the signal line INL2 can be held in the capacitor CS.

[0112] 8B is a timing chart illustrating the operation of the circuit including the transistor 104A and the capacitor CS in FIG. 8A. The timing chart illustrates the potential of a signal transmitted to the signal line INS1 for switching the on / off state of the transistor 104A, the input signal of the NOT circuit 100 transmitted to the signal line INL2, and an input signal corresponding to the potential held in the capacitor CS.

[0113] In FIG. 8B , at time T11, the signal on the signal line INS1 is set to H level to turn on the transistor 104A. The signal line INL2 and the capacitance element CS are brought into a conductive state. Therefore, the potential V1 of the input signal can be applied to the capacitance element CS. Thereafter, the signal on the signal line INS1 is set to L level to turn off the transistor 104A. The signal line INL2 and the capacitance element CS are brought into a non-conductive state. Therefore, the potential V1 of the input signal is held in the capacitance element CS. The potential V1 held in the capacitance element CS can continue to be held even after the potential of the signal line INL2 changes.

[0114] 8B, at time T12, the signal on the signal line INS1 is again set to H level, turning on the transistor 104A. The signal line INL2 and the capacitance element CS are brought into a conductive state. Therefore, the potential V2 of the input signal can be applied to the capacitance element CS. Thereafter, the signal on the signal line INS1 is set to L level, turning off the transistor 104A. The signal line INL2 and the capacitance element CS are brought into a non-conductive state. Therefore, the potential V1 of the input signal is held in the capacitance element CS. The potential V2 held in the capacitance element CS can continue to be held even after the potential of the signal line INL2 changes.

[0115] As shown in FIG. 8B , the circuit including the transistor 104A and the capacitor CS in FIG. 8A can hold a potential corresponding to an input signal on the signal line INL2 at any timing. Therefore, the potential corresponding to the input signal held in the capacitor CS can be used as backup data for the input signal. By using the backup data, a semiconductor device functioning as a NOT circuit can quickly restore a state using the backup data. Furthermore, since the signal line INL2 and the capacitor CS are electrically disconnected during the period when the transistor 104A is in the off state, the addition of the capacitor CS can reduce the effect on charging and discharging of the signal supplied to the signal line INL2 during normal operation.

[0116] 9A illustrates a configuration example different from that illustrated in FIG. 8A in a semiconductor device functioning as the NOT circuit described in FIG. 1A. In FIG. 9A, a circuit diagram in which a transistor 104B is added is illustrated. Note that, in the configuration illustrated in FIG. 9A, the above description is used for the same configuration as that in FIG. 1A, and repeated description may be omitted.

[0117] One of the source and the drain of the transistor 104B is connected to the signal line INL0, the other of the source and the drain of the transistor 104B is connected to the signal line INL2, and the gate of the transistor 104B is connected to the signal line INS2.

[0118] The signal line INS2 is a wiring that transmits a signal that controls the on / off state of the transistor 104B. The transistor 104B functions as a switch. The transistor 104B is turned on when the potential of the signal line INS2 is at an H level and turned off when the potential of the signal line INS2 is at an L level.

[0119] The transistor 104B is preferably an n-channel transistor, particularly an OS transistor. An OS transistor can have both field-effect mobility comparable to that of a Si transistor and extremely low leakage current. Therefore, by turning off the transistor 104B, charge corresponding to the potential of a signal transmitted to the signal line INL0 can be held in the signal line INL2.

[0120] 9B is a timing chart illustrating the operation of the circuit including the transistor 104B in FIG. 9A. The timing chart illustrates the potential of the signal transmitted to the signal line INS2 for switching the on / off state of the transistor 104B, and the potential of the input signal of the NOT circuit 100 transmitted to the signal lines INL0 and INL2.

[0121] 9B, at time T21, the signal on signal line INS2 is set to an L level, turning off transistor 104B. Signal lines INL0 and INL2 are brought into a non-conductive state. Signal line INL2 can hold the signal D21 most recently supplied from signal line INL0, specifically, a charge corresponding to the potential of signal D21. The signal D21 held in signal line INL2 can continue to be held even if the supply of the signal to signal line INL0 is stopped.

[0122] 9B, at time T22, the signal on the signal line INS2 is set to H level to turn on the transistor 104B. The signal lines INL0 and INL2 are brought into a conductive state. The signal D22 on the signal line INL0 can be transmitted to the signal line INL2.

[0123] 9B, the circuit including the transistor 104B in FIG. 9A can maintain a potential corresponding to the signal on the signal line INL2 at any timing. Therefore, the circuit can continue to operate even when the supply of a signal to the signal line INL0 is stopped. Furthermore, as described above, the OS transistor 104B can maintain a potential corresponding to the signal on the signal line INL2 by turning it off, so the signal immediately before the transistor 104B is turned off can be maintained.

[0124] <Configuration Example of Logic Circuit> Although the NOT circuit has been described above as an example of a semiconductor device to which one embodiment of the present invention is applied, one embodiment of the present invention is not limited thereto. Hereinafter, a semiconductor device that functions as a logic circuit of one embodiment of the present invention, which is different from a NOT circuit, will be described.

[0125] [NAND Circuit] Fig. 10 shows an example of a semiconductor device that functions as a NAND circuit. A NAND circuit 111 shown in Fig. 10 includes transistors 101a, 101b, 102a, 102b, and 106. The transistors 101a, 101b, 102a, 102b, and the transistor 106 are connected as shown in Fig. 10.

[0126] 10, the NAND circuit 111 is connected to power supply lines VHL and VLL. A signal line INL1 is connected to the gate of the transistor 106. A signal line INL2_A is connected to the gates of the transistors 101a and 102a. A signal line INL2_B is connected to the gates of the transistors 101b and 102b. A signal line OUTL is connected to one of the sources or drains of the transistors 101a, 101b, and 102a.

[0127] 10, transistors 101a and 101b correspond to the above-described transistor 101, and transistors 102a and 102b correspond to the above-described transistor 102. Signal lines INL2_A and INL2_B correspond to the above-described signal line INL2.

[0128] 10 , by providing the transistor 106 between the transistor 102b and the power supply line VLL, power gating can be performed by turning off the transistor 106 during non-operation, thereby reducing the power consumption of the NAND circuit 111. Specifically, by turning off the transistor 106 during a period in which there is no change in the potentials input to the signal lines INL2_A and INL2_B, it is possible to prevent leakage current from flowing through the transistors 102a and 102b.

[0129] [NOR Circuit] Fig. 11 shows an example of a semiconductor device that functions as a NOR circuit. A NOR circuit 112 shown in Fig. 11 includes transistors 101a, 101b, 102a, 102b, 106a, and 106b. The transistors 101a, 101b, 102a, 102b, 106a, and 106b are connected as shown in Fig. 11.

[0130] 11, the NOR circuit 112 is connected to the power supply lines VHL and VLL. A signal line INL1 is connected to the gates of the transistors 106a and 106b. A signal line INL2_A is connected to the gates of the transistors 101a and 102a. A signal line INL2_B is connected to the gates of the transistors 101b and 102b. A signal line OUTL is connected to one of the sources or drains of the transistors 101a, 102a, and 102b.

[0131] 11, transistors 101a and 101b correspond to the above-described transistor 101, transistors 102a and 102b correspond to the above-described transistor 102, and transistors 106a and 106b correspond to the above-described transistor 106. Signal lines INL2_A and INL2_B correspond to the above-described signal line INL2.

[0132] 11 , by providing the transistor 106a between the transistor 102a and the power supply line VLL and the transistor 106b between the transistor 102b and the power supply line VLL, the transistors 106a and 106b can be turned off during non-operation, thereby achieving power gating. As a result, the power consumption of the NOR circuit 112 can be reduced. Specifically, by turning off the transistors 106a and 106b during a period in which there is no change in the potentials input to the signal lines INL2_A and INL2_B, it is possible to prevent leakage current from flowing through the transistors 102a and 102b.

[0133] [Flip-Flop] As described above, since leakage current can be suppressed in NOT circuits, NOR circuits, and NAND circuits, it is possible to suppress the occurrence of leakage current in various logic circuits such as flip-flops, frequency dividers, and ring oscillators.

[0134] 12A shows a D flip-flop as an example of a semiconductor device that functions as a flip-flop. In a D flip-flop 113 shown in FIG. 12A, an input signal is input to a terminal D, and a clock signal is input to a terminal CLK. A first output signal is output from a terminal Q, and a second output signal is output from a terminal Qb.

[0135] 12B shows an example of a specific circuit configuration of the D flip-flop 113. The D flip-flop 113 includes NAND circuits 111a to 111d. The terminals of the NAND circuits 111a to 111d and the D flip-flop 113 are connected as shown in FIG.

[0136] 10 as the NAND circuits 111a to 111d, it is possible to reduce leakage current in the NAND circuits 111a to 111d. This makes it possible to reduce power consumption in the D flip-flop 113 when it is not operating. Note that it is sufficient that at least a portion of the NAND circuits 111a to 111d included in the D flip-flop 113 is configured to be able to reduce off-state current when it is not operating.

[0137] Note that, although this embodiment mode shows an example of forming a D flip-flop as a flip-flop, this is not limited thereto, and leakage current can be reduced by using the structure shown in this embodiment mode in various flip-flops such as an RS flip-flop, a JK flip-flop, and a T flip-flop.

[0138] 12C shows an example of a frequency divider circuit formed using the configuration described in this embodiment. The frequency divider circuit 114 shown in FIG. 12C includes D flip-flops 113a to 113c. The D flip-flops 113a to 113c have the same configuration as the D flip-flop 113 shown in FIG. 12A. The D flip-flop 113a has a terminal CLK that functions as an input terminal of the frequency divider circuit 114, a terminal Qb that is connected to the terminal D, and a terminal Q that is connected to the terminal CLK of the D flip-flop 113b. The D flip-flop 113b has a terminal Qb that is connected to the terminal D, and a terminal Q that is connected to the terminal CLK of the D flip-flop 113c. The D flip-flop 113c has a terminal Qb that is connected to the terminal D, and a terminal Q that functions as an output terminal of the frequency divider circuit 114.

[0139] Here, since the D flip-flops 113a to 113c are D flip-flops with reduced leakage current, it is possible to reduce the leakage current in the D flip-flops 113a to 113c. This makes it possible to suppress an increase in leakage current in the frequency divider circuit 114 and reduce power consumption when the frequency divider circuit 114 is not in operation. Note that although the frequency divider circuit 114 shown in FIG. 12C uses three D flip-flops, the number of D flip-flops is not limited to three, and may be set as appropriate.

[0140] [Register] Fig. 13 shows an example of a semiconductor device that functions as a register. The register 115 shown in Fig. 13 includes NOT circuits 100a and 100b and switches 161 and 162. The NOT circuit 100a includes transistors 101a, 102a, and 106a. The NOT circuit 100b includes transistors 101b, 102b, and 106b. The transistors 101a, 102a, 106a, 101b, 102b, and 106b and the switches 161 and 162 are connected as shown in Fig. 13.

[0141] The register 115 is connected to the power supply lines VHL and VLL as shown in FIG. 13. A signal line INL1 is connected to the gates of the transistors 106a and 106b. A signal line INL1 is connected to the gates of the transistors 101a and 102a via a switch 161. One of the sources or drains of the transistors 101a and 102a is connected to the gates of the transistors 101b and 102b and a signal line OUTL. One of the sources or drains of the transistors 101b and 102b is connected to the gates of the transistors 101a and 102a via a switch 162.

[0142] 13, NOT circuits 100a and 100b correspond to the NOT circuit 100 described above, transistors 101a and 101b correspond to the transistor 101 described above, transistors 102a and 102b correspond to the transistor 102 described above, and transistors 106a and 106b correspond to the transistor 106 described above. Switches 161 and 162 can be transistors fabricated in the same layer as any of the above-described transistors.

[0143] By turning on the switch 161 and turning off the switch 162, the input signal of the register 115 given to the signal line INL2 is taken into the register 115. In addition, by turning off the switch 161 and turning on the switch 162, the input signal taken into the register 115 is held.

[0144] 13 , a transistor 106a is provided between the transistor 102a and the power supply line VLL, and a transistor 106b is provided between the transistor 102b and the power supply line VLL. With this configuration, power gating can be achieved by turning off the transistors 106a and 106b when the register 115 is not in operation, thereby reducing the power consumption of the register 115. Specifically, by turning off the transistors 106a and 106b during a period when the input signal to the signal line INL2 remains at an L level, leakage current from the transistors 102a and 102b can be suppressed.

[0145] [Ring Oscillator] An example of a semiconductor device that functions as a ring oscillator is shown in Fig. 14. The ring oscillator 116 shown in Fig. 13 has NOT circuits 100a to 100e. The NOT circuits 100a to 100e are connected as shown in Fig. 14.

[0146] Here, since the NOT circuit 100 with reduced leakage current is used as each of the NOT circuits 100a to 100e, the leakage current can be reduced in the NOT circuits 100a to 100e. This suppresses an increase in leakage current in the ring oscillator 116, thereby reducing power consumption when the ring oscillator 116 is not in operation. Note that although the ring oscillator shown in FIG. 14 uses five NOT circuits, the number is not limited to five and may be set as appropriate.

[0147] As described above, in a semiconductor device, a transistor with a low off-state current, such as an OS transistor, is provided between power supply lines used in a CMOS logic circuit that is connected in series with a pMOS and an nMOS, and the transistor with a low off-state current is turned off when the nMOS Si transistor is off. This suppresses leakage current generated in the CMOS logic circuit provided in the semiconductor device, thereby reducing power consumption during operation.

[0148] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0149] Embodiment 2 In this embodiment, a structural example of a transistor applicable to the IO transistor described in Embodiment 1 and a structural example of a transistor applicable to a Si transistor will be described.

[0150] <Configuration Example 1 of IO Transistor> FIGS. 15A and 15D show examples of cross-sectional configurations of transistors applicable to the IO transistor of the first embodiment.

[0151] FIG. 15A is a plan view of a transistor 200 applicable to the IO transistor of the first embodiment. FIG. 15B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 15A , and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 15C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 15A , and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 15D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 15A . Note that some elements are omitted in the plan view of FIG. 15A for clarity. Some elements may also be omitted in the subsequent plan views.

[0152] The transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a layer 229 on the insulating layer 224, a semiconductor layer 230 covering the layer 229, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0153] In the transistor 200, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode, a bottom gate electrode, or a back gate), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0154] An insulating layer 275 is provided over the conductive layer 242a and the conductive layer 242b, and an insulating layer 280 is provided over the insulating layer 275. An opening 289 reaching the insulating layer 222 and the semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275, and the opening 289 overlaps with the region between the conductive layer 242a and the conductive layer 242b. In a plan view, the side surface of the insulating layer 280 in the opening 289 coincides or substantially coincides with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b.

[0155] The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the top end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided on the insulating layer 282. An insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212 is provided over a substrate (not shown). The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0156] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243a and 241a are provided in the openings. The insulating layer 241a is provided in contact with the sidewalls of the openings, and the conductive layer 243a is provided inside the insulating layer 241a. Openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243b and 241b are provided in the openings. The insulating layer 241b is provided in contact with the sidewalls of the openings, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias that connect a wiring or the like provided over the transistor 200 to the source or drain of the transistor 200.

[0157] In the semiconductor layer 230, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed, as in the transistor 200. That is, the semiconductor layer 230 has a channel formation region, a source region, and a drain region. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0158] The semiconductor layer 230 is physically separated between the transistors 200 adjacent to each other in the channel length direction. This configuration can prevent the Row Hammer effect and the Passing Gate effect when the transistor 200 is used in a memory cell. The Row Hammer effect refers to a phenomenon in which, in a configuration in which the word lines (conductive layers 260) of two transistors are adjacent to each other and the channel formation regions of the two transistors are connected, accumulated charge leaks to the adjacent word line, causing malfunction. The Passing Gate effect refers to a phenomenon in which charge moves to a floating gate or gate insulating layer, resulting in the formation of an unintended current path or a change in characteristics such as a threshold voltage fluctuation.

[0159] 15A to 15D , the opening where the conductive layer 243a is provided is located so as not to overlap with the layer 229. Furthermore, the conductive layer 243a is provided so as to be located between the layer 229 and the conductive layer 260 in a plan view. This configuration allows the opening to have a good shape. Therefore, contact defects can be suppressed, and a highly reliable semiconductor device can be provided.

[0160] Here, the layer 229 capable of increasing the crystallinity of the semiconductor layer 230 will be described.

[0161] The layer 229 has crystals. The layer 229 functions as a seed or a nucleus when a treatment for increasing the crystallinity of the semiconductor layer 230 is performed. In other words, the layer 229 functions as a seed or a nucleus when crystals of the semiconductor layer 230 grow. In this specification and the like, the layer 229 or the crystals of the layer 229 can be referred to as a seed crystal or a crystal nucleus. Furthermore, since the layer 229 has crystals, the layer 229 can be referred to as a crystalline portion.

[0162] Note that a step of removing the layer 229 may be performed after performing treatment to increase the crystallinity of the semiconductor layer 230. In this case, although the layer 229 illustrated in FIGS. 15A and 15B and the semiconductor layer 230 around the layer 229 are removed, the transistor 200 can be formed using the semiconductor layer 230 with increased crystallinity. Therefore, even if the layer 229 is not illustrated in the transistors 200A to 200C described later, the transistors 200A to 200C can be formed using the semiconductor layer 230 with increased crystallinity.

[0163] Indium oxide crystals have a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 230, the layer 229 preferably has, for example, a hexagonal or trigonal crystal structure. In this case, the layer 229 has crystals whose crystal orientation with respect to the surface or the surface where the layer 229 is to be formed is <001>, so that the semiconductor layer 230 can be formed having crystals whose crystal orientation is <111>. When the crystals of the layer 229 have a <001> crystal orientation with respect to the surface or the surface where the layer 229 is to be formed, the c-axis of the crystals is perpendicular to the surface or the surface where the layer 229 is to be formed. Note that a crystal with a hexagonal or trigonal crystal structure can sometimes be referred to as a crystal with a layered structure. Therefore, the above structure can be regarded as a structure in which the semiconductor layer 230 having crystals with a cubic crystal structure is formed on the layer 229 having crystals with a layered structure. That is, it can be thought of as a layered structure fabricated using heteroepitaxial growth techniques or heteroepitaxial growth-like techniques.

[0164] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0165] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of a film containing the crystal or the surface on which the crystal is formed. For example, a crystal with a crystal orientation of <100> is said to be a crystal whose (100) plane is parallel to the surface of a film containing the crystal or the surface on which the crystal is formed.

[0166] Specifically, zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide can be used for the layer 229. In—Ga—Zn oxide is preferably used for the layer 229. In this case, the layer 229 contains indium, gallium, zinc, and oxygen. Specifically, the composition is preferably In:Ga:Zn=1:1:1 [atomic ratio] or a composition therearound, or In:Ga:Zn=1:3:2 [atomic ratio] or a composition therearound. Metal oxides with these compositions are suitable for the layer 229 because they easily form a layered structure.

[0167] In—Ga—Zn oxide, In—Sn—Zn oxide, and the like are likely to have a CAAC structure. When an oxide having a CAAC structure is used for the layer 229, the c-axis of the crystal nuclei is perpendicular to the surface of the layer 229 or a surface on which the layer 229 is formed. In other words, by using an oxide that is likely to have a CAAC structure for the layer 229, it is possible to improve the controllability of the crystal orientation of the crystal nuclei.

[0168] When an oxide that easily has a CAAC structure is used for the layer 229, the semiconductor layer 230 can be formed having crystals with a <111> crystal orientation.

[0169] The layer 229 can also be made of an oxide having a cubic crystal structure. When the crystal of the layer 229 has the same crystal structure as the crystal of the semiconductor layer 230, the semiconductor layer 230 can be epitaxially grown using the layer 229 as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. Note that crystals of oxides containing Group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, the Group 3 elements in the crystals are primarily present as trivalent cations. Therefore, the layer 229 preferably contains at least one element that can become a trivalent cation. The element that can become a trivalent cation contained in the layer 229 is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0170] For example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. can be used for the layer 229. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0171] It is preferable that the difference (also referred to as lattice mismatch) between the lattice constant or unit lattice vector of the crystal nucleus and the lattice constant or unit lattice vector of the crystal of the semiconductor layer 230 be small. By using an oxide that reduces the lattice mismatch for the layer 229, the crystallinity of the semiconductor layer 230 can be improved.

[0172] One method for evaluating the degree of lattice mismatch is the lattice mismatch. The lattice mismatch Δa [%] of the crystals of the forming film with respect to the crystals of the forming film is calculated by the following formula (1). Hereinafter, the lattice mismatch Δa of the crystals of the forming film with respect to the crystals of the forming film may be simply referred to as the lattice mismatch Δa of the forming film with respect to the forming film.

[0173]

[0174] In formula (1), L １ is the lattice constant or unit lattice vector of the crystal of the formed film, and L ２ is the lattice constant or unit lattice vector of the crystal of the film to be formed.

[0175] The lattice mismatch Δa of the crystal grains in the semiconductor layer 230 with respect to the crystal nuclei is preferably −10% to 10%, more preferably −5% to 5%, and even more preferably −3% to 3%. By using a material that reduces the lattice mismatch with the semiconductor layer 230 for the layer 229, the crystallinity of the semiconductor layer 230 can be improved.

[0176] For example, the lattice constant of indium oxide crystal (bixbyite type) is said to be 1.01194 nm. The lattice constant of yttrium oxide crystal (bixbyite type) is said to be 1.05976 nm. Therefore, the lattice mismatch of indium oxide crystal with respect to yttrium oxide crystal is −4.5%. Therefore, when indium oxide is used for the semiconductor layer 230, yttrium oxide can be used for the layer 229.

[0177] For example, the lattice constant of erbium oxide crystal (bixbyite type) is said to be 1.0582 nm. Therefore, the lattice mismatch between the crystal of erbium oxide and the crystal of indium oxide is −4.4%. Therefore, when indium oxide is used for the semiconductor layer 230, erbium oxide can be used for the layer 229.

[0178] For example, Zr, which is an example of yttrium zirconium oxide, ０．９ Y ０．１ O １．９５ The lattice constant of the crystal (fluorite type) is 0.51481 nm (see ICSD coll.code.248790). ０．９ Y ０．１ O １．９５ The lattice mismatch of indium oxide with the crystal of indium oxynitride is −1.7%. Therefore, when indium oxide is used for the semiconductor layer 230, yttrium zirconium oxide can be suitably used for the layer 229. Note that yttrium zirconium oxide contains yttrium, zirconium, and oxygen.

[0179] Adding yttrium or yttrium oxide to zirconium oxide, that is, increasing the yttrium content in yttrium zirconium oxide to greater than 0 atomic%, can stabilize the crystalline structure of zirconium oxide. However, if the content is too high, the crystalline structure of yttrium zirconium oxide may change from a cubic system to another system, so it is preferable that the content is not too high. Therefore, for example, the yttrium content in yttrium zirconium oxide is preferably 2 atomic% or more and 15 atomic% or less, and more preferably 5 atomic% or more and 10 atomic% or less.

[0180] Alternatively, indium oxide may be used for the layer 229. By using indium oxide for the layer 229, the semiconductor layer 230 can be homoepitaxially grown using the layer 229 as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. In this case, the crystal orientation of the crystals in the layer 229 and the crystal orientation of the crystals in the semiconductor layer 230 are the same or substantially the same.

[0181] There is no particular limitation on the material that can be used for the layer 229. An insulating material, a semiconductor material, or a conductive material may be used for the layer 229. When a semiconductor material is used for the layer 229, the layer 229 may be considered as part of the semiconductor layer 230.

[0182] 15A shows an example in which the layer 229 is circular in plan view. However, the present invention is not limited to this. In plan view, the layer 229 can be, for example, a circle or a substantially circular shape such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. Furthermore, when sputtered particles are used as the layer 229, the layer 229 may be triangular or hexagonal in plan view.

[0183] The above is the description of the layer 229. Note that in the structural examples of the IO transistor described hereinafter in this specification and the like, a structure corresponding to the layer 229 can be applied to improve the crystallinity of a structure corresponding to the semiconductor layer 230.

[0184] <Structure Example 2 of IO Transistor> FIGS. 16A to 16D show examples of cross-sectional structures of transistors that can be used as the IO transistor of Embodiment 1. FIG.

[0185] Fig. 16A is a plan view of a transistor 200A applicable to the IO transistor of the first embodiment. Fig. 16B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 16A. Fig. 16C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 16A. Fig. 16D is a cross-sectional view taken along dashed dotted line A5-A6 in Figs. 16B and 16C.

[0186] The transistor 200A includes a conductive layer 220 , a conductive layer 240 , a semiconductor layer 230 , an insulating layer 250 on the semiconductor layer 230 , and a conductive layer 260 on the insulating layer 250 .

[0187] The conductive layer 220 is provided on the insulating layer 210, an insulating layer 280 is provided on the conductive layer 220, and a conductive layer 240 is provided on the insulating layer 280. An opening 290 reaching the conductive layer 220 is formed in the conductive layer 240 and the insulating layer 280, and the semiconductor layer 230 is provided along the bottom and sidewalls of the opening 290. The semiconductor layer 230 has a portion in contact with the conductive layer 240 and a portion in contact with the conductive layer 220.

[0188] In the transistor 200A, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode.

[0189] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 200A. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0190] The semiconductor layer 230 is provided inside the opening 290. The transistor 200A has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 in this example) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 in this example) is located above, allowing current to flow vertically. That is, a channel is formed along the side surface of the opening 290. This allows the transistor 200A to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. This allows for a higher integration of the semiconductor device. Furthermore, when the transistor 200A is used in a memory device, the memory capacity per unit area can be increased. Since the channel length direction of the transistor 200A can be said to have a component in the height direction (vertical direction), the transistor 200A can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0191] 16D , by forming the opening 290 so as to have a circular shape in a plan view, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. Therefore, the distance between the conductive layer 260 and the semiconductor layer 230 becomes approximately uniform, and therefore a gate electric field can be applied to the semiconductor layer 230 approximately uniformly.

[0192] In addition, in this embodiment, an example is shown in which the opening 290 is circular in plan view. By making the opening circular, the processing accuracy when forming the opening can be improved, and an opening of a fine size can be formed. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circle such as an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners.

[0193] <Configuration Example 3 of IO Transistor> FIGS. 17A to 17D show examples of cross-sectional configurations of transistors that can be used as the IO transistor of Embodiment 1. FIG.

[0194] Fig. 17A is a plan view of a transistor 200B applicable to the IO transistor of the first embodiment. Fig. 17B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in Fig. 17A, and is also a cross-sectional view of the transistor 200B in the channel length direction. Fig. 17C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in Fig. 17A, and is also a cross-sectional view of the transistor 200B in the channel width direction. Fig. 17D is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in Fig. 17A.

[0195] The transistor 200B includes a conductive layer 220, conductive layers 240a and 240b over an insulating layer 280, a layer 229a over the conductive layer 240a, a layer 229b over the conductive layer 240b, a semiconductor layer 230 over the layers 229a and 229b, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is located over the conductive layer 220.

[0196] The conductive layer 220 is provided over the insulating layer 210, an insulating layer 280 is provided over the conductive layer 220, and conductive layers 240a and 240b are provided over the insulating layer 280. A groove 291 reaching the conductive layer 220 is formed in the conductive layers 240a and 240b and the insulating layer 280, and the semiconductor layer 230 is provided along the bottom and sidewalls of the groove 291. The semiconductor layer 230 has a portion in contact with the layers 229a and 229b and the conductive layers 240a and 240b, and a portion in contact with the conductive layer 220. An insulating layer 283 is provided over the insulating layer 250. An insulating layer 285 is provided over the insulating layer 283. Moreover, a conductive layer 243a and a conductive layer 243b having portions in contact with the layers 229a and 229b and the conductive layers 240a and 240b are provided over the layers 229a and 229b and the conductive layers 240a and 240b. Moreover, a conductive layer 246 in contact with the conductive layers 243a and 243b is provided over the conductive layers 243a and 243b.

[0197] In the transistor 200B, the conductive layer 260 functions as a gate wiring, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layers 240a and 240b function as the other of the source electrode and the drain electrode.

[0198] The semiconductor layer 230 has a region that overlaps with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of this region functions as a channel formation region of the transistor 200B. One of the region of the semiconductor layer 230 near the conductive layer 220 and the region of the semiconductor layer 230 near the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0199] The semiconductor layer 230 is provided inside the groove 291. Therefore, the conductive layer 260 is provided to extend in the direction in which the groove 291 extends. Furthermore, the transistor 200B has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located below and the other of the source electrode and the drain electrode (here, the conductive layers 240a and 240b) is located above, so that current flows vertically. That is, a channel is formed along the side surface of the groove 291. As a result, the transistor 200B can occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. This allows for a higher integration of the semiconductor device. Furthermore, when the transistor 200B is used in a memory device, the memory capacity per unit area can be increased.

[0200] The semiconductor layer 230 contacts the bottom and side surfaces of the recessed portion of the conductive layer 220. The conductive layer 220 has a recessed portion, which increases the area where the semiconductor layer 230 and the conductive layer 220 contact each other. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220 can be reduced.

[0201] The width D1 of the groove 291 is set by the film thickness of each of the semiconductor layer 230, insulating layer 250, and conductive layer 260 provided in the groove 291. In a plan view, the side surface of the conductive layer 260 provided in the groove 291 has a portion that faces the side surface of the semiconductor layer 230 with the insulating layer 250 interposed therebetween. Therefore, the channel width of the transistor 200B is determined by the width D2 of the semiconductor layer 230 (see FIG. 17D ). The channel width of the transistor 200B can be calculated as "2×D2".

[0202] Increasing the width D2 of the semiconductor layer 230 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200B, for example, the area of ​​the transistor 200B in a plan view, is roughly determined by the width D1 of the groove 291 and the width D2 of the semiconductor layer 230. Reducing the width D1 of the groove 291 and the width D2 of the semiconductor layer 230 reduces the area occupied by the transistor 200B, thereby enabling a higher integration of the semiconductor device.

[0203] The channel length of the transistor 200B is the distance between the source region and the drain region. In other words, the channel length of the transistor 200B is determined by the thickness of the insulating layer 280 on the conductive layer 220. Therefore, the channel length of the transistor 200B does not affect the area occupied by the transistor 200B, for example, the area of ​​the transistor 200B in a planar view. This can improve productivity and yield in forming the insulating layer 280 and forming the groove 291 in the insulating layer 280. Furthermore, the on-current of the transistor 200B can be increased, thereby improving frequency characteristics.

[0204] <Configuration Example 4 of IO Transistor> FIGS. 18A to 18C show examples of cross-sectional configurations of transistors that can be used as the IO transistors in Embodiment 1. FIG.

[0205] 18A is a plan view of a transistor 200C applicable to the IO transistor of the first embodiment. FIG. 18B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 18A , which is also a cross-sectional view of the transistor 200C in the channel length direction. FIG. 18C is a cross-sectional view of the portion indicated by the dashed-dotted line B1-B2 in FIG. 18A , which is also a cross-sectional view of the transistor 200B in the channel width direction. Note that some components (such as the insulating layer 280) are omitted in FIG. 18A .

[0206] The transistor 200C includes a plurality of semiconductor layers (semiconductor layers 230_1 to 230_3), an insulating layer 250, a conductive layer 260, a pair of conductive layers 220 (conductive layer 220a and conductive layer 220b), a pair of conductive layers 240 (conductive layer 240a and conductive layer 240b), and a plurality of pairs of buffer layers 231 (buffer layers 231_1 to 231_4). Here, a transistor including three semiconductor layers will be described. Part of the insulating layer 250 functions as a gate insulating layer, and part of the conductive layer 260 functions as a gate electrode. The conductive layer 220a and the conductive layer 220b function as a source electrode and a drain electrode, respectively. The conductive layer 240a and the conductive layer 240b also function as a source electrode and a drain electrode, respectively.

[0207] The transistor 200C is provided over an insulating layer 210 provided over a substrate (not shown). The insulating layer 210 functions as a base insulating layer.

[0208] A pair of buffer layers 231_1 is provided over the insulating layer 210, and a semiconductor layer 230_1 is provided over the buffer layers 231_1. The pair of buffer layers 231_1 are provided to be spaced apart from each other, and the semiconductor layer 230_1 has a region between a portion located over one buffer layer 231_1 and a portion located over the other buffer layer 231_1 that does not overlap with either buffer layer 231_1.

[0209] The pair of buffer layers 231_2 are provided over the semiconductor layer 230_1. Each of the pair of buffer layers 231_2 is provided to overlap with the buffer layer 231_1. The semiconductor layer 230_1 has a region between the pair of buffer layers 231_2 that does not overlap with either of the buffer layers 231_2.

[0210] Similarly to the above, a semiconductor layer 230_2, a buffer layer 231_3, a semiconductor layer 230_3, and a buffer layer 231_4 are stacked in this order over the buffer layer 231_2. Furthermore, a conductive layer 240a and a conductive layer 240b are provided over the buffer layer 231_4.

[0211] Of the semiconductor layer 230, regions that are located between a pair of buffer layers 231 located below the semiconductor layer 230 and between a pair of buffer layers 231 located above the semiconductor layer 230 and that do not overlap with either of the buffer layers 231 function as channel formation regions.

[0212] The conductive layer 220a and the conductive layer 220b are provided in contact with the side surface of each semiconductor layer 230, the outer side surface (the side opposite to the conductive layer 260) of each buffer layer 231, and the outer side surface of the conductive layer 240a or the conductive layer 240b, respectively. The conductive layer 220 can connect each semiconductor layer 230 and the conductive layer 240.

[0213] 18B and other figures, each semiconductor layer 230 preferably has a protruding portion 21t that protrudes outward beyond the side surface of the buffer layer 231 that is in contact with the semiconductor layer 230. Furthermore, the conductive layer 220 is preferably provided in contact with not only the side surface of the protruding portion 21t of each semiconductor layer 230 but also the upper and lower surfaces of the protruding portion 21t. This increases the contact area between the conductive layer 220 and the semiconductor layer 230, thereby reducing the contact resistance therebetween.

[0214] The insulating layer 250 is provided so as to surround the region of the semiconductor layer 230 that does not overlap with the buffer layer 231. The insulating layer 250 is provided in contact with the upper and lower surfaces of each semiconductor layer 230 in the region that does not overlap with each pair of buffer layers 231. Furthermore, as shown in Fig. 18C, the insulating layer 250 is provided so as to surround the upper surface, lower surface, and both side surfaces of the semiconductor layer 230 in the channel width direction.

[0215] The conductive layer 260 is provided to surround the top, side, and bottom surfaces of each semiconductor layer 230 with the insulating layer 250 interposed therebetween. This allows an electric field from the conductive layer 260 to be applied to the channel formation region of the semiconductor layer 230 from above and below, thereby increasing the on-current per semiconductor layer 230. Furthermore, by providing a plurality of semiconductor layers 230, the on-current of the transistor 200C can be made extremely high.

[0216] Furthermore, the insulating layer 250 is provided between each buffer layer 231 and the conductive layer 260, and between each conductive layer 240 and the conductive layer 260, to insulate them from each other. This makes it possible to prevent electrical short circuits between the buffer layer 231 and the conductive layer 260, and between the conductive layer 240 and the conductive layer 260.

[0217] An insulating layer 280 is provided to cover the conductive layer 220 and the conductive layer 240. A slit is provided in the insulating layer 280, and an insulating layer 250 and a conductive layer 260 are formed inside the slit. The insulating layer 250 is provided along the side surface within the slit of the insulating layer 280, and the conductive layer 260 is provided so as to fill the slit of the insulating layer 250. A portion of the conductive layer 260 functions as wiring that follows the shape of the slit.

[0218] Here, a metal oxide (oxide semiconductor) exhibiting semiconductor properties is preferably used for the semiconductor layer 230. In this case, a conductive metal oxide (oxide conductor) is preferably used for the conductive layer 220 in contact with the semiconductor layer 230. By using a metal oxide for the conductive film in contact with the semiconductor layer 230 containing a metal oxide, the contact resistance therebetween can be reduced, the load on the wiring can be reduced, and the on-current of the transistor 200C can be increased.

[0219] The conductive layer 220 preferably contains a metal oxide containing the same metal element as the semiconductor layer 230. In particular, it is preferable that both the conductive layer 220 and the semiconductor layer 230 contain a metal oxide containing indium. This can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220. Furthermore, when processing the conductive layer 220 and the semiconductor layer 230, etching can be performed under the same conditions, which simplifies the manufacturing process and improves yield and productivity. It is preferable to use a metal oxide containing indium and tin for the conductive layer 220, as this can increase conductivity.

[0220] Furthermore, it is preferable to use a metal oxide for the buffer layer 231. By using a metal oxide for the buffer layer 231, the buffer layer 231 itself can function as a source electrode or a drain electrode. Furthermore, by using a metal oxide for both the buffer layer 231 and the conductive layer 220, not only can the contact resistance between them be reduced, but also the current path from the semiconductor layer 230 to the conductive layer 240 can be expanded, thereby further reducing the load on the wiring.

[0221] Although the above description has been given of a structure in which three semiconductor layers 230 are stacked, the number of semiconductor layers 230 included in the transistor 200C is not limited to this. The more semiconductor layers 230 there are, the greater the on-state current of the transistor 200C can be, which is preferable. On the other hand, the fewer the number of semiconductor layers 230 there are, the more simplified the manufacturing process of the transistor 200C can be, and the higher the yield can be.

[0222] <Constituent Materials of Semiconductor Device> Materials that can be used for the IO transistor of this embodiment will be described below. Note that each layer constituting the IO transistor of this embodiment may have a single-layer structure or a stacked-layer structure.

[0223] [Semiconductor Layer] Indium oxide is preferably used for the semiconductor layer 230 of the semiconductor device. By using indium oxide for the semiconductor layer, the transistor can have large on-state current and high frequency characteristics.

[0224] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0225] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0226] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 19A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 19B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0227] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 19B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 19A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 19A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 19A.

[0228] 19A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0229] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0230] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0231] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0232] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 19A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0233] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0234] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 19B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei is finally achieved, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and the transistor may no longer function. On the other hand, in indium oxide, as shown in FIG. 19A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei is finally achieved, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0235] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0236] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0237] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0238] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0239] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0240] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0241] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0242] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0243] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0244] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0245] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0246] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0247] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 19C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0248] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0249] Furthermore, as shown in FIG. 19C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the membrane and is released as water molecules.

[0250] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0251] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0252]

[0253] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0254] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0255] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0256] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0257] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0258] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 241a, insulating layer 241b, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0259] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0260] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0261] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0262] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0263] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0264] Furthermore, examples of materials that can have ferroelectricity include metal nitrides containing at least one of element M1 and element M2 and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Note that element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0265] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiOＸ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0266] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0267] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0268] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0269] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0270] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0271] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a metal nitride such as aluminum nitride or silicon nitride; or a metal nitride oxide such as silicon nitride oxide.

[0272] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Other examples include metal nitride oxides such as silicon nitride oxide. Other examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0273] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. For an insulating layer in which a region containing excess oxygen is easily formed, the description in <Structure of Semiconductor Device> can be referred to.

[0274] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0275] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0276] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0277] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0278] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0279] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0280] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0281] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0282] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 246, conductive layer 260, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0283] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0284] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0285] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0286] [Substrate] Substrates on which transistors are formed include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates having an insulating region within the semiconductor substrate, such as an SOI substrate, are also available. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Other examples include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0287] 20A and 20B show examples of cross-sectional structures of a transistor applicable to the Si transistor of Embodiment 1. Fig. 20A shows an example of a cross-sectional structure of a planar Si transistor in the channel length direction. Fig. 20B shows an example of a cross-sectional structure of a planar Si transistor in the channel width direction.

[0288] The transistor 130 includes a first semiconductor material. Examples of semiconductors that can be used as the first semiconductor material include silicon, germanium, silicon germanium, etc. The transistor 130 is provided on a semiconductor substrate 131 and includes a semiconductor layer 132 made of part of the semiconductor substrate 131, a gate insulating film 134, a gate electrode 135, and low-resistance layers 133 a and 133 b that function as source and drain regions.

[0289] The transistor 130 can be applied to either a pMOS or an nMOS depending on the impurity element added. The transistor 130 can be a transistor of an appropriate conductivity type depending on the circuit configuration, driving method, and the like.

[0290] It is preferable that the region where the channel of the semiconductor layer 132 is formed, the region nearby, the low resistance layers 133a and 133b that become the source and drain regions, and the like contain a semiconductor such as a silicon-based semiconductor.

[0291] The transistor 130 can also have regions 176a and 176b that are lightly doped drain (LDD) regions.

[0292] The low resistance layers 133a and 133b contain, in addition to the semiconductor material used in the semiconductor layer 132, an element that imparts n-type conductivity, such as phosphorus, or an element that imparts p-type conductivity, such as boron.

[0293] The gate electrode 135 can be formed using a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as phosphorus, or an element that imparts p-type conductivity, such as boron, a metal material, an alloy material, or a metal oxide material. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable.

[0294] 20C and 20D may be used instead of the transistor 130. Fig. 20C shows an example of a cross-sectional configuration in the channel length direction of a Si transistor having a FinFET structure. Fig. 20D shows an example of a cross-sectional configuration in the channel length direction of a Si transistor having a FinFET structure.

[0295] The transistor 190 has a semiconductor layer 132 (a part of a semiconductor substrate) in which a channel is formed, which has a convex shape, and a gate insulating film 134 and a gate electrode 135 are provided along the side surface and top surface of the semiconductor layer 132. An element isolation layer 181 is also provided between the transistors. Note that the transistor 190 may have an insulating film that is in contact with the upper part of the convex portion of the semiconductor substrate and functions as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor layer having a convex shape may also be formed by processing an SOI substrate.

[0296] 21 shows a cross-sectional structure in which the transistor 200, which is an example of an IO transistor, is stacked over the transistor 130, which is an example of a Si transistor. In the cross-sectional structure shown in FIG. 21, a wiring layer 902 having a conductive layer is provided over an element layer 901 having the transistor 130, and an element layer 903 having the transistor 200 is provided over the wiring layer 902 having the conductive layer.

[0297] The element layer 901 is a layer including Si transistors. The wiring layer 902 is a layer including conductive layers for connecting elements such as upper and lower transistors and capacitors. The element layer 903 is a layer including IO transistors.

[0298] In the element layer 901 illustrated in FIG. 21, an insulating film 136, an insulating film 137, and an insulating film 138 are stacked in this order to cover the transistor 130.

[0299] The insulating film 136 functions as a protective film when an element that provides conductivity and is added to the low-resistance layers 133 a and 133 b is activated in the manufacturing process of the semiconductor device. The insulating film 136 does not have to be provided if it is not necessary.

[0300] When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By providing the insulating film 137 containing hydrogen over the transistor 130 and performing heat treatment, dangling bonds in the semiconductor layer 132 are terminated by hydrogen in the insulating film 137, and the reliability of the transistor 130 can be improved.

[0301] The insulating film 138 functions as a planarizing layer that flattens steps caused by the transistor 130 and the like provided below the insulating film 138. The top surface of the insulating film 138 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like in order to improve the flatness of the top surface.

[0302] Furthermore, plugs 140 connected to the low resistance layers 133 a, 133 b, etc., and plugs 139 connected to the gate electrode 135 of the transistor 130, etc. are buried in the insulating films 136, 137, and 138. A conductive layer 251 is provided on the plug 140, and a conductive layer 151 is provided on the plug 139.

[0303] 21 includes a conductive layer 252. The conductive layer 252 functions as a wiring that connects a conductive layer provided in an upper element layer 903, a conductive layer provided in a lower element layer 901, and the like. The wiring layer 902 can be formed by stacking the conductive layers 252 over a plurality of layers (multilayering).

[0304] 21 includes a transistor 200 provided above the transistor 130. The transistor 200 includes insulating layers 241a and 241b, and conductive layers 243a and 243b, as well as an insulating layer 241c and a conductive layer 243c. The transistor 200 can be connected to the transistor 130 through the insulating layer 241c, the conductive layer 243c, the conductive layer 251, and the plug 140.

[0305] Figure 22 also illustrates a cross-sectional structure different from that of Figure 21, in which a wiring layer 902 having a conductive layer is provided over an element layer 901 having a transistor 190, an element layer 903 having a transistor 200 is provided over the wiring layer 902 having the conductive layer, and a memory element 950 having a capacitor element 930 and a transistor 940 is further provided over the wiring layer 902, across element layers 904_1 to 904_3.

[0306] 22 illustrates a transistor 190, which is a Si transistor with a FinFET structure, in an element layer 901. The transistor 190 has a semiconductor layer 132 in which an element isolation layer 181 and a low-resistance layer 133 are provided on a semiconductor substrate 131. The transistor 190 also has a gate insulating film 134 and a gate electrode 135.

[0307] In the wiring layer 902 shown in FIG. 22, the conductive layer 252 is provided, similarly to FIG.

[0308] 22 includes a transistor 200, similar to that in FIG. 21. In FIG. 22, the transistor 200 includes a semiconductor layer 230, a conductive layer 242 over the semiconductor layer 230, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0309] 22 is a 1T (transistor) 1C (capacitor) dynamic oxide semiconductor random access memory (DOSRAM) memory element. The DOSRAM is a memory that utilizes the low off-state current of a transistor, and by using an IO transistor as the transistor 940, both high-speed operation and low power consumption can be achieved.

[0310] 22 illustrates a state in which a capacitor 930 and a memory element 950 including a transistor 940 are stacked in the element layers 904_1 to 904_3. The transistor 940 can be manufactured in a manner similar to that of the transistor 200. The capacitor 930 can be manufactured by stacking a conductive layer 932 and a conductive layer 933 with an insulating layer 931 sandwiched therebetween. The memory elements 950 illustrated in FIG. 22 are connected to each other through a conductive layer, for example, the conductive layer 934, illustrated in the element layers 904_1 to 904_3.

[0311] By stacking a memory circuit having a plurality of memory elements 950 on the element layers 901 and 903 on which the logic circuit is provided, the semiconductor device can have an on-chip memory configuration. The on-chip memory configuration can shorten the signal propagation distance and increase the speed of the operation of the interface between the logic circuit and the memory circuit. Furthermore, the on-chip memory configuration can increase the number of wirings between the logic circuit and the memory circuit, thereby improving the bandwidth (also referred to as memory bandwidth) of the memory circuit. Therefore, the memory circuit provided on the logic circuit can be used for applications such as a high bandwidth memory (HBM).

[0312] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0313] Embodiment 3 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 23A to 24E.

[0314] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance of the electronic components, mainframes, space equipment, data centers, and various electronic devices can be achieved.

[0315] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0316] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0317] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0318] [Electronic Component] FIG. 23A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 23A has a semiconductor device 981 inside a mold 984. FIG. 23A omits some parts in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are connected to electrode pads 986, and the electrode pads 986 are connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and connected on the printed circuit board 988 to complete the mounting substrate 989.

[0319] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0320] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0321] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0322] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0323] 23B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0324] The electronic component 990 shows an example in which the semiconductor device 981 is used as a wideband memory. The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0325] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0326] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0327] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0328] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0329] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0330] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0331] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 23B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0332] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0333] 24A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 24A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0334] The computer 5620 can have the configuration shown in the perspective view in Fig. 24B, for example. In Fig. 24B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0335] PC card 5621 shown in Figure 24C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 24C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referred to.

[0336] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCI Express (Tokiriki trademark).

[0337] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0338] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0339] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0340] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0341] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0342] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0343] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0344] Fig. 24D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 24D illustrates a planet 6804 in space.

[0345] 24D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0346] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0347] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0348] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0349] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0350] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0351] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0352] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0353] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0354] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0355] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0356] Fig. 24E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 24E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0357] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0358] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0359] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0360] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0361] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0362] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0363] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0364] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0365] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0366] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0367] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0368] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0369] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0370] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0371] In this specification and the like, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0372] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0373] In this specification, the channel length of a planar transistor refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a plan view of the transistor, or a distance between a source and a drain in a region where a channel is formed.

[0374] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0375] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0376] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0377] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0378] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0379] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0380] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0381] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0382] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0383] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0384] 100: NOT circuit, 101: transistor, 102: transistor, 106: transistor

Claims

a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line for supplying a signal for controlling the logic circuit; a first power supply line for supplying a high power supply potential and a second power supply line for supplying a low power supply potential; the p-channel transistor and the first n-channel transistor each have a first semiconductor layer including silicon; the second n-channel transistor has a second semiconductor layer containing indium oxide; one of a source and a drain of the second n-channel transistor is electrically connected to one of a source and a drain of the first n-channel transistor; one of the source and the drain of the p-channel transistor is electrically connected to the first power supply line; the other of the source and the drain of the second n-channel transistor is electrically connected to the second power supply line; the first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal for turning off the second n-channel transistor during a period in which the logic circuit is inactive; the first power supply line is provided in a layer below the layer in which the logic circuit is provided; the second power supply line is provided in a layer above the layer in which the logic circuit is provided; Semiconductor device. 　 a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line for supplying a control signal to the logic circuit; a first power supply line for supplying a high power supply potential and a second power supply line for supplying a low power supply potential; the p-channel transistor and the first n-channel transistor each have a first semiconductor layer including silicon; the second n-channel transistor has a second semiconductor layer containing indium oxide; one of a source and a drain of the second n-channel transistor is electrically connected to one of a source and a drain of the first n-channel transistor; one of the source and the drain of the p-channel transistor is electrically connected to the first power supply line; the other of the source and the drain of the second n-channel transistor is electrically connected to the second power supply line; the first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal for turning off the second n-channel transistor during a period in which the logic circuit is inactive; the first power supply line is provided in a layer below a layer in which the p-channel transistor is provided; the second power supply line is provided in a layer above a layer in which the second n-channel transistor is provided; Semiconductor device. 　 In claim 1 or claim 2, the first semiconductor layer has a structure surrounded by the gate of the p-channel transistor and the gate of the first n-channel transistor; Semiconductor device. 　 In claim 1 or claim 2, a third power supply line that supplies a high power supply potential and a fourth power supply line that supplies a low power supply potential; the third power supply line is provided in a layer below a layer in which the p-channel transistor is provided, the fourth power supply line is provided in a layer above a layer in which the second n-channel transistor is provided; Semiconductor device. 　 In claim 1 or claim 2, a third n-channel transistor; a second signal line electrically connected to the gate of the first n-channel transistor and the gate of the p-channel transistor is electrically connected to one of the source and the drain of the third n-channel transistor; a third n-channel transistor being turned off to hold the potential of the second signal line; Semiconductor device. 　 a logic circuit having a p-channel transistor, a first n-channel transistor, and a second n-channel transistor; a first signal line for supplying a control signal to the logic circuit; a first power supply line for supplying a high power supply potential and a second power supply line for supplying a low power supply potential; the p-channel transistor and the first n-channel transistor each have a first semiconductor layer including silicon; the second n-channel transistor has a second semiconductor layer containing indium oxide; one of a source and a drain of the second n-channel transistor is electrically connected to one of a source and a drain of the first n-channel transistor; one of the source and the drain of the p-channel transistor is electrically connected to the first power supply line; the other of the source and the drain of the second n-channel transistor is electrically connected to the second power supply line; the first signal line electrically connected to the gate of the second n-channel transistor has a function of supplying a signal for turning off the second n-channel transistor during a period in which the logic circuit is inactive; the first power supply line and the second power supply line are provided in a layer below a layer in which the p-channel transistor is provided; the first signal lines are provided in a layer above a layer in which the second n-channel transistors are provided; Semiconductor device. 　 In claim 6, the first semiconductor layer has a structure surrounded by the gate of the p-channel transistor and the gate of the first n-channel transistor; Semiconductor device. 　 In claim 6, a third n-channel transistor; a second signal line electrically connected to the gate of the first n-channel transistor and the gate of the p-channel transistor is electrically connected to one of the source and the drain of the third n-channel transistor; a third n-channel transistor being turned off to hold the potential of the second signal line; Semiconductor device.

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