Re-rounding in integrated circuit for variance reduction in ai operations
The AI-accelerating processor system addresses inefficiencies in conventional processors by employing a systolic array with rounding circuits to perform matrix multiplication at lower precision levels, enhancing computational efficiency and speed for AI tasks.
WO2025244945A1PCT designated stage Publication Date: 2025-11-27MATX INC
Patent Information
- Application Number
- PCT/US2025/029721
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-08-20
- Filing Date
- 2025-05-16
- Publication Date
- 2025-11-27
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Figure US2025029721_27112025_PF_FP_ABST
Abstract
An AI-accelerating processor system may include memory that stores a value at a first precision level. The system may include a systolic array configured to perform computation. The systolic array may include rounding circuits. Each rounding circuit may round the value at the first precision level to a second precision level that is lower than the first precision level. At least a first rounding circuit and a second rounding circuit are configured to round the same value differently to respectively generate at least a first rounded value and a second rounded value. The systolic array may also include processing elements that are configured to receive a version of the value in one or more collective operations. At least a first processing element and a second processing element are configured to perform computations involving the value by respectively using the first rounded value and the second rounded value.
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Citation Information
Patent Citations
Data structure descriptors for deep learning acceleration
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System and method for implementing variable-precision matrix multiplication using low-precision digit matrix multiplier
US20230359694A1