Solar cell and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics. Provided are a solar cell and a photovoltaic module. The solar cell comprises: a silicon substrate, which comprises a first side and a second side; a first semiconductor layer, which is located on the first side; and a first conductive layer, which is located on the side of the first semiconductor layer facing away from the silicon substrate. The roughness of the interface between the first semiconductor layer and the silicon substrate is less than the roughness of the interface between the first semiconductor layer and the first conductive layer. The interface between the first semiconductor layer and the silicon substrate is relatively flat, such that interfacial recombination losses can be reduced, and the interfacial passivation effect can be enhanced, thereby increasing an open-circuit voltage and lowering the requirements for the thickness of the first semiconductor layer, and thus reducing light absorption by the first semiconductor layer and increasing a short-circuit current of the cell. The interface between the first semiconductor layer and the first conductive layer is relatively rough, such that the contact therebetween can be enhanced, and the transportation of charge carriers to the first conductive layer can be improved, thereby helping to increase the fill factor.

Description

A solar cell and a photovoltaic module

[0001] The present application claims priority to the Chinese patent application No. 202410718318.7, filed on June 4, 2024, and entitled "A solar cell and a photovoltaic module", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. BACKGROUND

[0003] Solar cells can convert solar energy into electrical energy, and they use clean energy, so they have a wide application prospect.

[0004] A thicker semiconductor layer in a solar cell can effectively improve its passivation performance. However, a thicker semiconductor layer is beneficial to passivation, but is not conducive to the transmission of photo-generated carriers and the improvement of fill factor, that is, there is a contradiction between the improvement of passivation performance and the improvement of fill factor of the semiconductor layer, resulting in poor performance of the solar cell.

[0005] SUMMARY

[0006] The present application provides a solar cell and a photovoltaic module, aiming to solve the problem of the contradiction between the improvement of passivation performance and the improvement of fill factor of the semiconductor layer of the existing solar cell.

[0007] In a first aspect, the present application provides a solar cell, comprising:

[0008] a silicon substrate, the silicon substrate comprising: opposite first and second sides;

[0009] a first semiconductor layer on the first side;

[0010] a first conductive layer on a side of the first semiconductor layer away from the silicon substrate;

[0011] In a cross-section of the solar cell, the roughness of the interface line between the first semiconductor layer and the silicon substrate is less than the roughness of the interface line between the first semiconductor layer and the first conductive layer.

[0012] In the embodiments of the present application, the roughness of the interface between the first semiconductor layer and the silicon substrate is less than the roughness of the interface between the first semiconductor layer and the first conductive layer, that is, the interface between the first semiconductor layer and the silicon substrate is relatively smooth, or the first semiconductor layer and the silicon substrate have a relatively smooth contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the absorption of light by the first semiconductor layer, and further improving the short circuit current of the battery. At the same time, the interface between the first semiconductor layer and the first conductive layer is relatively rough, or the first semiconductor layer and the first conductive layer have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell battery. Moreover, the interface between the first semiconductor layer and the first conductive layer is relatively rough, and the rough interface can further reduce the reflection of light, which is beneficial to improve the short circuit current. In summary, the present application solves the problem of contradiction between the improvement of the passivation performance of the first semiconductor layer of the existing solar cell and the improvement of the fill factor by the smooth interface between the first semiconductor layer and the silicon substrate and the rough interface between the first semiconductor layer and the first conductive layer. Not only the passivation effect of the interface is improved, thereby improving the open circuit voltage, but also the fill factor and the short circuit current of the solar cell battery are improved.

[0013] In some possible embodiments, the first semiconductor layer comprises: a first surface close to the first conductive layer; the first surface comprises a plurality of concave-convex structures; at least part of the concave-convex structures in the first surface are arranged in order.

[0014] In some possible embodiments, the surface roughness of the interface between the first semiconductor layer and the first conductive layer is greater than the surface roughness of the silicon substrate.

[0015] In some possible embodiments, the roughness of the interface between the first semiconductor layer and the silicon substrate is less than or equal to 1.5 nm; and / or,

[0016] The roughness of the interface between the first semiconductor layer and the first conductive layer is greater than 1.5 nm.

[0017] In some possible embodiments, the first semiconductor layer is composed of an intrinsic amorphous silicon layer and a doped amorphous silicon layer arranged in layers; the intrinsic amorphous silicon layer is arranged immediately adjacent to the silicon substrate.

[0018] In some possible embodiments, the solar cell further includes: a second semiconductor layer and a second conductive layer disposed on the second side of the silicon substrate; the first semiconductor layer and the second semiconductor layer are of different doping types, and a roughness of an interface between the second semiconductor layer and the silicon substrate on the second side of the solar cell is less than a roughness of an interface between the second semiconductor layer and the second conductive layer in a cross section of the solar cell.

[0019] In some possible embodiments, the silicon substrate and the first semiconductor layer are of the same doping type, and a roughness of an interface between the first semiconductor layer and the first conductive layer is greater than a roughness of an interface between the second semiconductor layer and the second conductive layer.

[0020] In some possible embodiments, the solar cell further includes: a tunneling oxide layer and a doped polysilicon layer disposed on the second side of the silicon substrate in a stack; the tunneling oxide layer is immediately adjacent to the silicon substrate; and the doped amorphous silicon layer and the doped polysilicon layer are of different doping types.

[0021] In some possible embodiments, the first side surface of the silicon substrate includes: first conductive regions and second conductive regions distributed at intervals;

[0022] the first semiconductor layer is located on the first conductive regions and the second conductive regions; portions of the first semiconductor layer located on the first conductive regions and portions of the first semiconductor layer located on the second conductive regions are of different doping types; or,

[0023] the first side surface of the silicon substrate includes: first conductive regions and second conductive regions distributed at intervals;

[0024] the first semiconductor layer is located on the first conductive regions;

[0025] the solar cell further includes: a tunneling oxide layer and a doped polysilicon layer disposed on the second conductive regions in a stack; the tunneling oxide layer is immediately adjacent to the silicon substrate; and the first semiconductor layer and the doped polysilicon layer are of different doping types.

[0026] In some possible embodiments, a roughness of an interface between the doped polysilicon layer on the second conductive regions and the first conductive layer is greater than a roughness of an interface between the first semiconductor layer and the first conductive layer.

[0027] In some possible embodiments, a doping concentration of a side of the first semiconductor layer close to the first conductive layer is greater than a doping concentration of a side of the first semiconductor layer close to the silicon substrate.

[0028] In a second aspect of the present application, a photovoltaic module is provided, comprising a plurality of any of the solar cells described above.

[0029] The solar cell and the photovoltaic module described above have the same or similar beneficial effects, and for the sake of brevity, the description will not be repeated here.

[0030] The above description is only a summary of the technical solutions of the present application, in order to enable the technical means of the present application to be more clearly understood, and to be implemented according to the content of the description, and in order to enable the above and other purposes, features and advantages of the present application to be more apparent and easy to understand, the following specific embodiments of the present application will be described. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative labor.

[0032] Fig. 1 shows a partial transmission electron microscope image of a solar cell in an embodiment of the present application;

[0033] Fig. 2 shows a partial transmission electron microscope image of a first semiconductor layer close to a first surface of a first conductive layer in an embodiment of the present application;

[0034] Fig. 3 shows a partial transmission electron microscope image of a first semiconductor layer close to a second surface of a silicon substrate in an embodiment of the present application;

[0035] Fig. 4 shows a structural schematic diagram of a solar cell in an embodiment of the present application.

[0036] Fig. 4 shows a structural schematic diagram of a solar cell in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative labor fall within the scope of protection of the present application.

[0038] It should be understood by those skilled in the art that in the disclosure of the present application, the terms "first", "second", "third", "fourth", "fifth" and the like are only used to distinguish different structures, without limiting the number, connection relationship and the like of the specific structures; in addition, the orientation or position relationship indicated by "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the above terms cannot be understood as a limitation on the present application.

[0039] Transmission electron microscope is abbreviated as TEM (Transmission Electron Microscope), TEM in the present application can also be replaced by SEM (Scanning Electron Microscope) and the like, which is not specifically limited.

[0040] The present application provides a solar cell, referring to FIG. 1, the solar cell can include: a silicon substrate e, the doping type, structure form and the like of the silicon substrate here are not specifically limited. The silicon substrate includes: opposite first side and second side, among the first side and the second side, one is a light receiving side and the other is a back light side, in the process of normal operation of the solar cell, the side of the silicon substrate mainly receiving light is the light receiving side, and the back light side is opposite to the light receiving side. In FIG. 1, the surface of the silicon substrate e can have a textured structure, and the protruding corner of the silicon substrate e in FIG. 1 is a textured structure.

[0041] The solar cell further includes: a first semiconductor layer d located on the first side of the silicon substrate e, that is, the first semiconductor layer d is only located on the first side of the silicon substrate e. The first side of the silicon substrate e here can be the back light side or the light receiving side, which is not specifically limited. Referring to FIG. 1, the silicon substrate e and the first semiconductor layer d are in direct contact. The inventor found that the first semiconductor layer d in the solar cell can effectively passivate the dangling bond defects of the silicon substrate, reduce the activity, thereby reducing the rate of minority carrier recombination, obtaining a longer minority carrier lifetime, improving the open circuit voltage of the solar cell, and enhancing the performance of the solar cell. However, although the thicker first semiconductor layer d is beneficial to the passivation of the silicon substrate defects, it is not conducive to the transmission of photo-generated carriers and the improvement of the fill factor and short circuit current, that is, there is a contradiction between the improvement of the passivation performance and the improvement of the fill factor of the first semiconductor layer d, resulting in poor performance of the solar cell.

[0042] The solar cell further includes a first conductive layer c on a side of the first semiconductor layer d facing away from the silicon substrate e, the first conductive layer c is also on the first side of the silicon substrate e in the case where the first semiconductor layer d is on the first side of the silicon substrate e, and the silicon substrate e, the first semiconductor layer d and the first conductive layer c are sequentially stacked and in contact with each other. The boundary between the first semiconductor layer d and the silicon substrate e refers to the boundary of the part where the outline of the first semiconductor layer d and the outline of the silicon substrate e overlap each other in the cross section of the solar cell. In FIG. 1, the boundary between the first semiconductor layer d and the silicon substrate e is a clear and straight boundary at the junction of the first semiconductor layer d and the silicon substrate e. The boundary between the first semiconductor layer d and the first conductive layer c refers to the boundary of the part where the outline of the first semiconductor layer d and the outline of the first conductive layer c overlap each other, and the edges of the first semiconductor layer d and the first conductive layer c are in contact with each other. In FIG. 1, the boundary between the first semiconductor layer d and the first conductive layer c is a rough and unclear boundary at the junction of the first semiconductor layer d and the first conductive layer c.

[0043] The roughness of the interface line refers to the degree of concave-convex of the interface line, or the degree of unevenness caused by the micro-convex or micro-concave in the interface line, which can be the degree of fluctuation of the interface line. To solve the above technical problems, in the solar cell, the roughness of the interface line between the first semiconductor layer d and the silicon substrate e is less than the roughness of the interface line between the first semiconductor layer d and the first conductive layer c. For example, the number of convexities and / or concavities of the interface line between the first semiconductor layer d and the silicon substrate e can be less than the number of convexities and / or concavities of the interface line between the first semiconductor layer d and the first conductive layer c; or the degree of convexity and / or concavity of the interface line between the first semiconductor layer d and the silicon substrate e can be less than the degree of convexity and / or concavity of the interface line between the first semiconductor layer d and the first conductive layer c; or the arrangement of convexities and / or concavities of the interface line between the first semiconductor layer d and the silicon substrate e can be more orderly than the arrangement of convexities and / or concavities of the interface line between the first semiconductor layer d and the first conductive layer c; or the depth of convexities and / or concavities of the interface line between the first semiconductor layer d and the silicon substrate e can be less than the depth of convexities and / or concavities of the interface line between the first semiconductor layer d and the first conductive layer c. Specifically, that is to say, the interface line between the first semiconductor layer and the silicon substrate is relatively flat, or the first semiconductor layer and the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the absorption of light by the first semiconductor layer, and further improving the short-circuit current of the cell. At the same time, the interface line between the first semiconductor layer and the first conductive layer is relatively rough, or the first semiconductor layer and the first conductive layer have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the interface line between the first semiconductor layer and the first conductive layer is relatively rough, and the rough interface line can further reduce light reflection, which is beneficial to improve the short-circuit current. In summary, the present application solves the problem of the contradiction between the improvement of the passivation performance of the first semiconductor layer and the improvement of the fill factor of the existing solar cell by the flat interface line between the first semiconductor layer and the silicon substrate, and the rough interface line between the first semiconductor layer and the first conductive layer. Not only does it improve the passivation effect of the interface, thereby improving the open circuit voltage, but also it improves the fill factor and short-circuit current of the solar cell. The difference between the roughness of the interface line between the first semiconductor layer d and the first conductive layer c and the roughness of the interface line between the first semiconductor layer d and the silicon substrate e is not specifically limited.

[0044] The roughness of the interface line can be the arithmetic mean value Ra of the absolute value of the distance between each point in the sampling length of the interface line and a reference straight line, wherein the reference straight line passes at least one point in the sampling length of the interface line and is located between a wave crest and a wave trough in the sampling length of the interface line, or the roughness of the interface line can be the distance between a wave crest and a wave trough in the interface line, wherein the highest point of the protrusion in the interface line can be the wave crest and the lowest point of the depression can be the wave trough. Specifically, in the present application, the actual sampling length of the roughness of the interface line between the first semiconductor layer d and the first conductive layer c is within 500 nm, which is not affected by the observation of the concave-convex of the silicon substrate roughening surface in the range of the sampling length, and the tested roughness of the interface line can accurately represent the morphology (roughness) of the interface line between the first semiconductor layer d and the silicon substrate e and the interface line between the first semiconductor layer d and the first conductive layer c formed by the growth of the first semiconductor layer on the silicon substrate. Further, the roughness Ra (nm) of the interface line between the conductive layer d and the silicon substrate e is less than or equal to 1.5, and the roughness Ra (nm) of the interface line between the first semiconductor layer d and the first conductive layer c is greater than 1.5. In the present application, the roughness Ra (nm) of the interface line between the conductive layer d and the silicon substrate e is less than or equal to 1.5, which is verified to find that the structure surface of the roughened surface produced after the anisotropic growth in the process of the silicon substrate roughening is the roughened surface after the sufficient chemical solution etching, and is not the surface of the silicon substrate cutting. After sufficient chemical etching, the surface of the roughened surface, that is, the sidewall surface of the pyramid, is smoother, and the surface defects of the silicon substrate are reduced. In the present application, the roughness Ra (nm) of the interface line between the first semiconductor layer d and the first conductive layer c is greater than 1.5, which matches the roughness of the interface line between the silicon substrate e and the first conductive layer d, avoids the formation of 100% amorphous silicon, increases the number and size of crystal grains in the formation process of the first semiconductor layer, thereby achieving a larger roughness between the silicon substrate e and the first semiconductor layer d, which is beneficial to the current transmission effect of the first semiconductor layer, reduces the square resistance, and increases the light trapping effect.

[0045] It should be noted that a in FIG. 1 is ion beam deposition of platinum, a is located on the upper side and the outer side of b, b is electron beam deposition of platinum, and a and b in FIG. 1 are auxiliary settings with better conductive performance added to make the TEM imaging clearer, and are not the actual structure in the solar cell.

[0046] The first semiconductor layer d comprises a first surface close to the first conductive layer c and a second surface close to the silicon substrate e, that is, in the solar cell, one of the first surface and the second surface of the first semiconductor layer is a light-receiving surface of the first semiconductor layer and the other is a back light-receiving surface of the first semiconductor layer. In some possible embodiments, referring to FIG. 2, the first surface of the first semiconductor layer close to the first conductive layer comprises a plurality of concave-convex structures, and at least part of the concave-convex structures in the first surface are arranged in an ordered manner, such as the concave-convex structures circled by the white dashed line in FIG. 2. The concave-convex structures arranged in an ordered manner can be considered as crystallized parts, and the concave-convex structures outside the concave-convex structures arranged in an ordered manner in FIG. 2 can be understood as amorphous parts, that is, at least part of the first surface has a higher degree of crystallization, and the concave-convex structures of the crystallized parts are columnar structures extending along the thickness direction of the semiconductor. However, due to the different heights of the columnar structures, the first surface has a relatively large roughness, which leads to a relatively large roughness of the junction line between the first semiconductor layer and the first conductive layer, or a relatively large surface roughness of the interface between the first semiconductor layer and the first conductive layer, thereby enhancing the contact between the first semiconductor layer and the first conductive layer and the transmission of carriers to the first conductive layer, and being beneficial to improving the fill factor of the solar cell. Moreover, the junction line between the first semiconductor layer and the first conductive layer is relatively rough, and the rough junction line can further reduce the reflection of light, which is beneficial to improving the short-circuit current. The above structure can be realized by only partial crystallization, and therefore the solar cell is easy to obtain. More specifically, the first semiconductor layer is composed of a intrinsic amorphous silicon layer and a doped amorphous silicon layer arranged in a stack, and the intrinsic amorphous silicon layer is close to the silicon substrate. Therefore, the first surface of the first semiconductor layer close to the first conductive layer is the surface of the doped amorphous silicon layer. In the present application, the intrinsic amorphous silicon layer can be first subjected to plasma treatment, and then the doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer subjected to the plasma treatment. Because the intrinsic amorphous silicon layer is induced by the plasma treatment, the surface of the intrinsic amorphous silicon layer is dehydrogenated and partially crystallized, and then the doped amorphous silicon layer formed on the intrinsic amorphous silicon layer subjected to the plasma treatment is more ordered, so that the first surface with at least part of the concave-convex structures arranged in an ordered manner can be formed. The doped amorphous silicon layer in the present application is relative to the doped polycrystalline silicon, and the doped amorphous silicon can be one or a mixture of several of doped amorphous silicon, doped nanocrystalline silicon and doped microcrystalline silicon.

[0047] In some possible embodiments, referring to FIG. 3, the second surface of the first semiconductor layer close to the silicon substrate includes a plurality of concave-convex structures, referring to FIG. 2 and FIG. 3, the arrangement of at least part of the concave-convex structures in the first surface of the first semiconductor layer close to the first conductive layer is more ordered than the arrangement of the concave-convex structures in the second surface, as shown by the white dotted line in FIG. 2, the concave-convex structures arranged in order are crystallized parts, the concave-convex structures outside the part arranged in order in FIG. 2 and the concave-convex structures in FIG. 3 can be understood as amorphous parts, the arrangement of the concave-convex structures circled by the white dotted line in FIG. 2 in the first surface is more ordered than the arrangement of the concave-convex structures shown in FIG. 3 in the second surface, or in other words, the crystallization degree of at least part of the region of the first surface is higher, the concave-convex structures circled by the white dotted line in FIG. 2 in the first surface are crystallized parts, the concave-convex structures of the crystallized parts form columnar structures along the thickness direction of the first semiconductor layer, but due to the different heights of the columnar structures, it leads to a large roughness of the first surface, which in turn leads to a large roughness of the junction line between the first semiconductor layer and the first conductive layer observed on the cell interface, or in other words, the surface roughness of the interface between the first semiconductor layer and the first conductive layer is large, which can enhance the contact between the first semiconductor layer and the first conductive layer and enhance the carrier transmission to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the junction line between the first semiconductor layer and the first conductive layer is relatively rough, and the rough junction line can further reduce the reflection of light, which is beneficial to improve the short-circuit current. The above structure can be realized by partial crystallization assistance, so the solar cell is easy to obtain. More specifically, the first semiconductor layer is composed of a stacked intrinsic amorphous silicon layer and a doped microcrystalline silicon layer, the intrinsic amorphous silicon layer is adjacent to the silicon substrate, so the second surface close to the silicon substrate in the first semiconductor layer is the surface of the intrinsic amorphous silicon layer, and the first surface close to the first conductive layer in the first semiconductor layer is the surface of the doped microcrystalline silicon layer. In this application, the intrinsic amorphous silicon layer is first subjected to plasma treatment, and then the doped microcrystalline silicon layer is formed on the intrinsic amorphous silicon layer after plasma treatment. Because the intrinsic amorphous silicon layer is induced by plasma treatment, it plays a role in surface dehydrogenation and partial crystallization, and further makes the doped microcrystalline silicon layer formed on the intrinsic amorphous silicon layer after plasma treatment more ordered, so that the first surface with at least part of the concave-convex structures arranged in order can be formed, so the arrangement of at least part of the concave-convex structures in the first surface is more ordered than the arrangement of the concave-convex structures in the second surface.

[0048] In some possible embodiments, the first semiconductor layer includes microcrystalline silicon, the crystallized concave-convex structures or the concave-convex structures arranged in order as mentioned above are microcrystalline silicon parts, also known as nanocrystalline silicon, the film thickness of the microcrystalline silicon is grown to 5-35 nm (nanometers), and the microcrystalline silicon is easy to crystallize, so the first semiconductor layer is easy to obtain, and therefore the solar cell is easy to obtain.

[0049] The surface roughness refers to the degree of concave-convex of the surface, or the degree of unevenness caused by the micro-convex or micro-concave in the surface, or the degree of fluctuation of the surface. In some possible embodiments, the surface roughness of the interface between the first semiconductor layer d and the first conductive layer c in the solar cell is greater than the surface roughness of the silicon substrate e. For example, the number of convexities and / or concavities in the surface of the silicon substrate e can be less than the number of convexities and / or concavities in the interface between the first semiconductor layer d and the first conductive layer c; in another case, the degree of convexity and / or concavity in the surface of the silicon substrate e can be less than the degree of convexity and / or concavity in the interface between the first semiconductor layer d and the first conductive layer c; or, the arrangement of convexities and / or concavities in the surface of the silicon substrate e can be more ordered than the arrangement of convexities and / or concavities in the interface between the first semiconductor layer d and the first conductive layer c; or, the depth of convexities and / or concavities in the surface of the silicon substrate e can be less than the depth of convexities and / or concavities in the interface between the first semiconductor layer d and the first conductive layer c. Specifically, that is, the silicon substrate e has a relatively flat surface, so that the first semiconductor layer has a relatively flat contact surface with the silicon substrate, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer, and further improving the short-circuit current of the cell. At the same time, the first semiconductor layer has a relatively rough contact surface with the first conductive layer, which can enhance the contact between the first semiconductor layer and the first conductive layer, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer is relatively rough, and the rough interface can further reduce the reflection of light, which is beneficial to improve the short-circuit current. In summary, the present application solves the problem of the contradiction between the improvement of the passivation performance of the first semiconductor layer and the improvement of the fill factor of the solar cell by the relatively flat surface of the silicon substrate and the rough contact interface between the first semiconductor layer and the first conductive layer, which not only improves the passivation effect of the interface, thereby improving the open circuit voltage, but also improves the fill factor and short-circuit current of the solar cell.

[0050] The surface roughness can be the arithmetic mean of the profile deviation within a sampling length in the surface or interface (i.e., Ra), or the surface roughness can be the distance between the peak top line and the valley bottom line in the interface or surface (i.e., Rz).

[0051] In some possible embodiments, referring to FIG. 4, the first semiconductor layer d is composed of a layer-stacked intrinsic amorphous silicon layer 11 and a doped amorphous silicon layer 12, and the intrinsic amorphous silicon layer 11 is adjacent to the silicon substrate e. The intrinsic amorphous silicon layer 11 herein can play a good passivation role, can reduce the silicon substrate interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage. In combination with the structure of the first semiconductor layer d described above, the application can reduce the requirement for the thickness of the intrinsic amorphous silicon layer 11, thereby reducing the light absorption of the intrinsic amorphous silicon layer 11, and further improving the short circuit current of the cell. The doped amorphous silicon layer 12 herein can participate in forming a pn junction and play a role in separating carriers.

[0052] In some possible embodiments, referring to FIG. 4, the first semiconductor layer is located on the first side of the silicon substrate e, and the solar cell further comprises: a second semiconductor layer 13 and a second conductive layer 14 arranged on the second side of the silicon substrate e. The first semiconductor layer and the second semiconductor layer are of different doping types, one of which is of n-type and the other of which is of p-type, the first conductive layer is located on the first side of the silicon substrate e, the second conductive layer is located on the second side of the silicon substrate e, and the first semiconductor layer and the first conductive layer located on the first side of the silicon substrate e are sequentially stacked on the silicon substrate, and the second semiconductor layer and the second conductive layer located on the second side of the silicon substrate e are sequentially stacked on the silicon substrate, so that the solar cell is a bifacial solar cell. In the cross section of the solar cell, the surface roughness of the interface between the first semiconductor layer and the silicon substrate is less than the surface roughness of the interface between the first semiconductor layer and the first conductive layer, and the surface roughness of the interface between the second semiconductor layer and the silicon substrate is less than the surface roughness of the interface between the second semiconductor layer and the second conductive layer. In addition, the roughness of the interface between the first semiconductor layer and the silicon substrate is less than the roughness of the interface between the first semiconductor layer and the first conductive layer, and the roughness of the interface between the second semiconductor layer and the silicon substrate is less than the roughness of the interface between the second semiconductor layer and the second conductive layer. On the first side of the silicon substrate, the first semiconductor layer and the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the absorption of light by the first semiconductor layer, and further improving the short-circuit current of the cell. On the second side of the silicon substrate, the second semiconductor layer and the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the second semiconductor layer, thereby reducing the absorption of light by the second semiconductor layer, and further improving the short-circuit current of the cell. At the same time, the semiconductor layer and the conductive layer located on the same side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the semiconductor layer and the conductive layer located on the same side of the silicon substrate, and enhance the transmission of carriers to the conductive layer, which is conducive to improving the fill factor of the solar cell. That is, the first semiconductor layer and the first conductive layer located on the first side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer located on the first side of the silicon substrate, and enhance the transmission of carriers to the conductive layer, which is conducive to improving the fill factor of the solar cell. The second semiconductor layer and the second conductive layer located on the second side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the second semiconductor layer and the second conductive layer located on the second side of the silicon substrate, and enhance the transmission of carriers to the conductive layer, which is conducive to improving the fill factor of the solar cell.Moreover, the interface between the first semiconductor layer on the first side of the silicon substrate and the first conductive layer is rough, and the rough interface can further reduce the reflection of light, which is conducive to improving the short-circuit current. The interface between the second semiconductor layer on the second side of the silicon substrate and the second conductive layer is rough, and the rough interface can further reduce the reflection of light, which is conducive to improving the short-circuit current. In addition, the bifacial solar cell generally has the advantages of low process temperature, high conversion efficiency, good high-temperature characteristics, etc. It should be noted that the first conductive layer on the light side of the silicon substrate needs to have good light transmittance.

[0053] In some possible embodiments, referring to FIG. 4, the silicon substrate and the first semiconductor layer have the same doping type, and the roughness of the interface between the first semiconductor layer and the first conductive layer is greater than the roughness of the interface between the second semiconductor layer and the second conductive layer. Here, whether the first semiconductor layer is located on the light side or the back side of the silicon substrate is not specifically limited, the silicon substrate and the first semiconductor layer form a high-low junction, the silicon substrate and the second semiconductor layer 13 form a pn junction, and whether the first semiconductor layer and the second semiconductor layer have the same or different crystal types is not specifically limited. In the first conductive layer and the second conductive layer, the conductive layer located on the light side of the silicon substrate has better light transmittance.

[0054] For example, the silicon substrate is n-type, the first semiconductor layer includes an n-type doped microcrystalline silicon layer, the first semiconductor layer is located on the light side of the silicon substrate, the second semiconductor layer is located on the back side of the silicon substrate, the second semiconductor layer includes a p-type doped microcrystalline silicon layer, and the surface roughness of the interface between the first semiconductor layer with the n-type doping on the light side of the silicon substrate and the first conductive layer (light Ra) is greater than the surface roughness of the interface between the second semiconductor layer with the p-type doping on the back side of the silicon substrate and the second conductive layer (back Ra), which can improve the light trapping effect. For example, the light Ra (nm) is 3.68, and the back Ra is 2.30 (nm). The above structure is set by adjusting the nucleation crystallinity in the first semiconductor layer on the front side or the light side, so that the front side has higher grain crystallinity and larger nucleation size, thereby forming better light transmittance on the front side of the cell and improving the photoelectric conversion efficiency. Moreover, the pn junction formed by the second semiconductor layer and the silicon substrate is located on the back side of the silicon substrate, which can further improve the efficiency of the solar cell. The bifacial solar cell can further include a first electrode 2 located on the first conductive layer and a second electrode 3 located on the second conductive layer, and the first electrode 2 and the second electrode 3 are used to conduct current outward.

[0055] In some possible embodiments, the first semiconductor layer is located on a first side of the silicon substrate, and the solar cell further comprises a tunneling oxide layer and a doped polysilicon layer which are sequentially located on a second side of the silicon substrate, the tunneling oxide layer is adjacent to the silicon substrate, the doped polysilicon layer and the doped amorphous silicon layer are different in doping type, one of the two is n-type and the other is p-type, one of the first side and the second side of the silicon substrate is a light-receiving side of the silicon substrate and the other is a back-light side of the silicon substrate, and the first side and the second side can be referred to the foregoing description, which will not be repeated here. The solar cell can be considered as a high-low temperature hybrid bifacial cell, for example, the first semiconductor layer can be located on the back-light side of the silicon substrate, the tunneling oxide layer and the doped polysilicon layer are sequentially located on the light-receiving side of the silicon substrate, and the first semiconductor layer is composed of the intrinsic amorphous silicon layer and the doped amorphous silicon layer which are sequentially located. Since the light-receiving side is provided with the tunneling oxide layer instead of the intrinsic amorphous silicon layer, the short-circuit current of the solar cell is further improved. The pn junction of the solar cell can be formed on the back-light side of the silicon substrate, which is not specifically limited.

[0056] In some possible embodiments, the first side surface of the silicon substrate comprises: first conductive regions and second conductive regions which are spaced apart, the spacing between the first conductive regions and the second conductive regions is used to avoid electric leakage, the first side surface can be a back-light side surface of the silicon substrate, the first semiconductor layer is located on the first side of the silicon substrate, or the first semiconductor layer is located on the back-light side of the silicon substrate, and the first semiconductor layer is located on the first conductive regions and the second conductive regions, the doping type of the part of the first semiconductor layer located on the first conductive regions is different from the doping type of the part of the first semiconductor layer located on the second conductive regions, one of the two is n-type and the other is p-type, the first conductive layer is located on the first side of the silicon substrate, and the first conductive layer is located on the side of the first semiconductor layer away from the silicon substrate, the projection of the first conductive layer on the first side surface of the silicon substrate also falls within the first conductive regions and the second conductive regions, that is, the solar cell is a back contact solar cell, the pn junction and the metal contact in the solar cell are both arranged on the back of the solar cell, so that the front surface is not shielded by the electrode grid lines, the area of the solar cell for absorbing the sunlight is larger, thereby improving the conversion efficiency and emitting more electric quantity.

[0057] In the back contact solar cell, the roughness of the interface between the part of the first semiconductor layer on the first conductive region and the first conductive region of the silicon substrate is less than the roughness of the interface between the part of the first semiconductor layer on the first conductive region and the part of the first conductive layer on the first conductive region, the roughness of the interface between the part of the first semiconductor layer on the second conductive region and the second conductive region of the silicon substrate is less than the roughness of the interface between the part of the first semiconductor layer on the second conductive region and the part of the first conductive layer on the second conductive region, and the first semiconductor layer and the back light side of the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer, and further improving the short circuit current of the cell. At the same time, the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate is relatively rough, and the rough interface can further reduce the reflection of light, which is beneficial to improve the short circuit current. The difference between the roughness of the interface between the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate and the roughness of the interface between the first semiconductor layer and the silicon substrate on the same conductive region of the back light side of the silicon substrate is not specifically limited.

[0058] In some possible embodiments, the first side surface of the silicon substrate comprises: a first conductive region and a second conductive region distributed at intervals, the intervals between the first conductive region and the second conductive region being used to avoid electric leakage, the first side surface can be a backside surface of the silicon substrate, the first semiconductor layer is located only on the first side of the silicon substrate, or the first semiconductor layer is located only on the backside of the silicon substrate, the first semiconductor layer is located only on the first conductive region, and the solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer which are sequentially arranged on the second conductive region, the tunneling oxide layer is adjacent to the silicon substrate, the first conductive layer is also located on the first side of the silicon substrate, the first conductive layer is located on a side of the doped polysilicon layer and the first semiconductor layer away from the silicon substrate, a projection of the first conductive layer on the first side surface of the silicon substrate also falls within the first conductive region and the second conductive region, the doped polysilicon layer and the first semiconductor layer are different in doping type, one of the doping types is n-type and the other is p-type, the solar cell is a hybrid back contact solar cell, the pn junction and the metal contact are both arranged on the back of the cell, so that the front surface is not blocked by electrode grid lines, the area of the cell for absorbing solar radiation is larger, the doped polysilicon layer has better conductivity, and the reflectivity of the doped polysilicon layer on the back of the silicon substrate is better, thereby improving the conversion efficiency and enabling the cell to generate more electric power.

[0059] In the hybrid back contact solar cell, the roughness of the interface between the first semiconductor layer and the first conductive region of the silicon substrate is smaller than the roughness of the interface between the first semiconductor layer and the first conductive layer, the first semiconductor layer and the first conductive region on the backside of the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer and further improving the short circuit current of the cell. Meanwhile, the first semiconductor layer and the first conductive layer on the first conductive region on the backside of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer on the first conductive region on the backside of the silicon substrate and enhance the transmission of carriers to the first conductive layer, which is conducive to improving the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer on the first conductive region on the backside of the silicon substrate is relatively rough, and the rough interface can further reduce the reflection of light, which is conducive to improving the short circuit current. The difference between the roughness of the interface between the first semiconductor layer and the first conductive layer on the first conductive region on the backside of the silicon substrate and the roughness of the interface between the first semiconductor layer and the silicon substrate on the first conductive region on the backside of the silicon substrate is not specifically limited.

[0060] In some possible embodiments, the roughness of the junction line between the doped polysilicon layer on the second conductive region and the first conductive layer is greater than the roughness of the junction line between the first semiconductor layer and the first conductive layer, specifically, the grain size of the doped polysilicon layer is greater, and the reflectivity of the doped polysilicon layer on the back surface of the silicon substrate is better, thereby improving the conversion efficiency and enabling more electric energy to be emitted.

[0061] In some possible embodiments, the doping concentration of the conductive element in the first semiconductor layer close to the first conductive layer is greater than the doping concentration of the conductive element in the first semiconductor layer close to the silicon substrate, that is, a certain concentration gradient can be formed, and the performance of the solar cell can be improved. For example, the first semiconductor layer is composed of a stacked intrinsic amorphous silicon layer and a doped microcrystalline silicon layer, the intrinsic amorphous silicon layer is arranged close to the silicon substrate, and therefore the side of the first semiconductor layer close to the silicon substrate is the side of the intrinsic amorphous silicon close to the silicon substrate. The doped element in the doped microcrystalline silicon layer can diffuse into the intrinsic amorphous silicon, and the doping concentration in the silicon substrate can also diffuse into the intrinsic amorphous silicon, causing the side of the intrinsic amorphous silicon close to the silicon substrate to have a certain doping concentration. However, the doping concentration of the side of the intrinsic amorphous silicon close to the silicon substrate is less than the doping concentration of the side of the doped microcrystalline silicon layer close to the first conductive layer.

[0062] In some possible embodiments, to further illustrate the implementation method of the solar cell, the first semiconductor layer can be deposited on the silicon substrate after texturing or polishing, and then the surface of the first semiconductor layer is etched. The etching solution can be selected according to the prior art. After etching, the surface roughness of the first semiconductor layer can be changed. For example, after etching, the amorphous state or smaller nanocrystals on the surface of the first semiconductor layer are etched away, thereby leaving larger nanocrystal particles on the surface, thereby forming a larger rough surface structure. After the transparent first conductive layer is deposited, the roughness of the junction interface between the first semiconductor layer and the transparent first conductive layer is increased, thereby forming better light trapping and contact performance between the first semiconductor layer and the first conductive layer, and thereby improving the collection effect of the carriers.

[0063] In some possible embodiments, to further illustrate the implementation method of the solar cell, the first semiconductor layer can be deposited on the silicon substrate after texturing or polishing, and then the surface of the first semiconductor layer is etched. The etching solution can be selected according to the prior art. After etching, the surface roughness of the first semiconductor layer can be changed. For example, after etching, the amorphous state or smaller nanocrystals on the surface of the first semiconductor layer are etched away, thereby leaving larger nanocrystal particles on the surface, thereby forming a larger rough surface structure. After the transparent first conductive layer is deposited, the roughness of the junction interface between the first semiconductor layer and the transparent first conductive layer is increased, thereby forming better light trapping and contact performance between the first semiconductor layer and the first conductive layer, and thereby improving the collection effect of the carriers.

[0064] In some possible embodiments, to further illustrate the implementation method of the above solar cell, the first semiconductor deposition can be performed on a silicon substrate after texturing or polishing, wherein an intrinsic amorphous silicon layer is first deposited in the process of depositing the first semiconductor layer, then plasma treatment is performed, and then deposition of doped microcrystalline silicon is performed. The plasma treatment increases the grain size and deposition order of the doped microcrystalline silicon layer, thereby forming a larger roughness. Subsequently, after the transparent first conductive layer is deposited, the roughness of the interface between the first semiconductor layer and the transparent first conductive layer is increased, thereby forming better light trapping and contact performance between the first semiconductor layer and the transparent first conductive layer, and thus improving the collection effect of the carriers.

[0065] The following provides a method for preparing the above solar cell by taking plasma treatment as an example, and specifically includes the following steps:

[0066] Step 101, providing a silicon substrate after texturing; the silicon substrate includes: a first side and a second side opposite to each other.

[0067] Step 102, preparing an intrinsic amorphous silicon layer on at least one of the first side and the second side.

[0068] The formation mode of the intrinsic amorphous silicon layer is not specifically limited, for example, plasma chemical vapor deposition can be used for deposition. The main function of the intrinsic amorphous silicon layer is to passivate the dangling bonds on the surface of the crystalline silicon, reduce surface recombination, and improve the electrical performance of the cell.

[0069] Step 103, performing plasma treatment on the intrinsic amorphous silicon layer by using a first reaction gas containing hydrogen, carbon dioxide and silane.

[0070] By using the first reaction gas containing hydrogen, carbon dioxide and silane, the intrinsic amorphous silicon layer is mainly subjected to surface dehydrogenation and partial crystallization by plasma chemical vapor deposition. The carbon dioxide in the first reaction gas combines with the dehydrogenation effect of hydrogen plasma to promote the original amorphous state of the surface of the intrinsic amorphous silicon layer to be converted into a partially nanocrystallized state, that is, partial nanocrystallization is achieved, so that the surface nucleation point is larger and more, and “self-repairing nucleation” is achieved.

[0071] In some possible embodiments, in the plasma processing process herein, the pressure in the reaction chamber can be 2 mbar-3.5 mbar (millibar), for example, it can be 2 mbar, 2.21 mbar, 2.5 mbar, 2.84 mbar, 3 mbar, 3.17 mbar, 3.5 mbar, etc., the dilution ratio of hydrogen to silane in the first reaction gas is greater than or equal to 600, for example, it can be 600, 650, 700, 7470, 800, 862, 900, 930, 1000, etc., the flow ratio of carbon dioxide and silane can be 30%-100%, for example, it can be 30%, 38%, 40%, 46%, 50%, 60%, 65%, 72%, 80%, 84.2%, 100%, etc., the power density can be 2000W / m 2 -2600W / m 2 , for example, it can be 2000W / m 2 , 2100W / m 2 , 2145W / m 2 , 2200W / m 2 , 2300W / m 2 , 2400W / m 2 , 2406W / m 2 , 2500W / m 2 , 2600W / m 2 , etc., the glow time can be 3s-10s, for example, it can be 3s, 4s, 5s, 6s, 7s, 8s, 9s, 10s, etc. Under the above larger hydrogen dilution ratio (H2 / SiH4≥600), by optimizing the flow rate of carbon dioxide and matching the pressure and power settings of the reaction chamber, it is more conducive to effectively inducing the growth of the doped microcrystalline silicon layer, such as the doped nanocrystalline silicon layer, into a generally columnar structure along its thickness direction, and the columnar structure has different degrees of concave-convex.

[0072] Step 104, preparing a doped microcrystalline silicon layer on the intrinsic amorphous silicon layer after plasma processing.

[0073] The doping type of the doped microcrystalline silicon layer herein can be n-type doping or p-type doping. Due to the aforementioned plasma processing of the intrinsic amorphous silicon layer, at least part of the doped microcrystalline silicon layer away from the silicon substrate in the doped microcrystalline silicon layer grows into a concave-convex columnar structure along its thickness direction, and further makes the surface roughness of at least part of the doped microcrystalline silicon layer away from the silicon substrate in the doped microcrystalline silicon layer larger.

[0074] In some possible embodiments, the doped microcrystalline silicon layer is formed on the side of the aforementioned intrinsic amorphous silicon layer after plasma treatment away from the silicon substrate by plasma chemical vapor deposition, and the doped microcrystalline silicon layer is also formed by plasma chemical vapor deposition, which continues the aforementioned plasma treatment, and the process is simple and the production efficiency is high. The second reaction gas used in the process of forming the doped microcrystalline silicon layer includes hydrogen and silane, wherein the dilution ratio of hydrogen to silane is greater than or equal to 200 and less than or equal to 700, for example, it can be 200, 260, 300, 340, 350, 400, 440, 500, 600, 700, etc. In the process of forming the doped microcrystalline silicon layer, the pressure of the reaction chamber is greater than or equal to 1.5 mbar and less than or equal to 4 mbar, for example, it can be 1.5 mbar, 1.92 mbar, 2 mbar, 2.5 mbar, 2.75 mbar, 3 mbar, 3.5 mbar, 4 mbar, etc. The thickness of the formed doped microcrystalline silicon layer is greater than or equal to 11 nm and less than or equal to 38 nm, for example, it can be 11 nm, 13.4 nm, 15 nm, 19.1 nm, 19.5 nm, 20 nm, 22.5 nm, 25.8 nm, 28 nm, 30 nm, 33 nm, 35.2 nm, 37 nm, 38 nm, etc.

[0075] In some possible embodiments, in the case of the doped microcrystalline silicon layer being an n-type doped microcrystalline silicon layer, a second reaction gas including phosphine (PH3), hydrogen and silane can be used in the process of preparing the doped microcrystalline silicon layer. The aforementioned step 104 can include: using a second reaction gas containing silane, hydrogen and phosphine to prepare an n-type doped microcrystalline silicon layer on the intrinsic amorphous silicon layer after plasma treatment by plasma chemical vapor deposition, wherein the flow ratio of phosphine to silane in the second reaction gas is 3%-20%, for example, it can be 3%, 3.9%, 4.3%, 5.7%, 6.9%, 8.4%, 9.5%, 10%, 11.5%, 13%, 15.3%, 18%, 19.2%, 20%, etc. The dilution ratio of hydrogen to silane in the second reaction gas can be 200-500, for example, it can be 200, 260, 300, 340, 350, 400, 440, 500, etc. In the process of preparing the n-type doped microcrystalline silicon layer, the pressure of the reaction chamber is 1.5 mbar-4 mbar, for example, it can be 1.5 mbar, 1.92 mbar, 2 mbar, 2.5 mbar, 2.75 mbar, 3 mbar, 3.5 mbar, 4 mbar, etc. The power density can be 950 W / m 2 -2400 W / m 2 , for example, it can be 950 W / m 2 , 1000 W / m 2 , 1007 W / m2 , 1233W / m 2 , 1500W / m 2 , 1675W / m 2 , 1780W / m 2 , 1950W / m 2 , 2000W / m 2 , 2200W / m 2 , 2400W / m 2 , etc. The deposition thickness can be 11 nm-18 nm, for example, 11 nm, 11.4 nm, 12 nm, 13.1 nm, 14 nm, 14.7 nm, 15 nm, 15.8 nm, 16 nm, 17 nm, 18 nm, etc. Since the n-type doping gas, i.e. phosphine, will inhibit crystallization, the gas doping ratio (PH3 / SiH4) needs to be controlled within a suitable range. By optimizing the gas doping ratio (PH3 / SiH4), the conductivity of the nanocrystalline or microcrystalline can be adjusted, and the defect density is controlled within a suitable range. At the same time, the n-type doped microcrystalline silicon layer prepared under the above process conditions is rough on the side away from the silicon substrate.

[0076] In some possible embodiments, when the doped microcrystalline silicon layer is a p-type doped microcrystalline silicon layer, a second reaction gas including a p-type doping gas, hydrogen and silane can be used in the process of preparing the doped microcrystalline silicon layer. The foregoing step 104 can include: using a second reaction gas containing silane, hydrogen and a p-type doping gas to prepare a p-type doped microcrystalline silicon layer on the plasma-treated intrinsic amorphous silicon layer by plasma chemical vapor deposition, wherein the p-type doping gas in the second reaction gas includes: diborane (B2H6) and / or trimethylborane (TMB), and the flow ratio of the p-type doping gas to silane can be 0.5%-10%, for example, 0.5%, 0.97%, 1%, 2.7%, 2.25%, 3%, 3.9%, 4.1%, 4.9%, 5%, 6%, 7.5%, 8.3%, 10%, etc. In the process of preparing the p-type doped microcrystalline silicon layer, the dilution ratio of hydrogen to silane in the second reaction gas can be 200-700, for example, 200, 240, 300, 340, 400, 450, 500, 600, 700, etc. In the process of preparing the p-type doped microcrystalline silicon layer, the reaction cavity pressure can be 1.5 mbar-4 mbar, for example, 1.5 mbar, 2 mbar, 2.25 mbar, 2.5 mbar, 3 mbar, 3.3 mbar, 3.5 mbar, 4 mbar, etc. The power density can be 950W / m 2 -2400W / m 2 , for example, 950W / m 2 , 1000W / m 2, 1200 W / m 2 , 1500 W / m 2 , 1720 W / m 2 , 1675 W / m 2 , 2000 W / m 2 , 2200 W / m 2 , 2400 W / m 2 etc. The thickness of the deposited p-type doped microcrystalline silicon layer can be 13 nm-38 nm, for example, 13 nm, 14.2 nm, 15 nm, 16 nm, 17.3 nm, 20 nm, 25 nm, 25.5 nm, 30 nm, 32 nm, 38 nm, etc. Since the p-type doping gas, i.e. diborane and / or trimethylborane, will inhibit crystallization, it is necessary to control the gas doping ratio ((B2H6 and / or TMB) / SiH4) within a suitable range. By optimizing the gas doping ratio ((B2H6 and / or TMB) / SiH4), the conductivity of the nanocrystals can be adjusted, the defect density is controlled within a suitable range, and the p-type doped microcrystalline silicon layer prepared under the above process conditions is relatively rough on the side away from the silicon substrate.

[0077] Based on the above plasma treatment and the deposition conditions of the doped microcrystalline silicon layer, the deposition rate of the n-type or p-type doped microcrystalline silicon layer can be greatly improved. Moreover, the above plasma treatment can effectively induce the growth of the doped microcrystalline silicon layer along the thickness direction, and at least part of the doped microcrystalline silicon is in a columnar structure. Compared with the case without the above surface dehydrogenation and partial crystallization, the number of columnar structures can be greatly increased.

[0078] The doped microcrystalline silicon layer formed in the above steps 102-104 and its immediately adjacent intrinsic amorphous silicon layer together form the aforementioned first semiconductor layer.

[0079] Step 105: preparing a first conductive layer on the doped microcrystalline silicon layer.

[0080] The first conductive layer herein can be prepared by deposition or the like, which is not specifically limited.

[0081] The prepared doped microcrystalline silicon layer is also subjected to performance testing. Specifically, the prepared doped microcrystalline silicon layer is placed in a Raman spectrometer for crystallization rate testing, and then subjected to peak fitting calculation of the crystallization rate. Two metal electrodes are prepared on the prepared doped microcrystalline silicon layer by evaporation, and then a semiconductor tester is used to test the dark state IV curve to calculate the conductivity. The prepared doped microcrystalline silicon layer is made into a sample cell, which is tested by an IV tester to obtain the energy conversion efficiency. Compared with the preparation of the doped microcrystalline silicon layer without plasma treatment on the intrinsic amorphous silicon layer, the crystallization rate and conductivity of the doped microcrystalline silicon layer formed on the intrinsic amorphous silicon layer subjected to plasma treatment are obviously improved.

[0082] The roughness of different layers in the battery structure is also measured. Specifically, a textured silicon substrate is provided, and the surface roughness Ra of the silicon substrate is measured to be 0.602 nm. An amorphous p-type doped layer is prepared on the silicon substrate, and the roughness Ra of the surface of the amorphous p-type doped layer away from the glass is measured to be 0.457 nm. An intrinsic amorphous silicon layer is prepared on the silicon substrate by the aforementioned preparation method, and then the intrinsic amorphous silicon layer is subjected to plasma treatment. Then, an n-type doped microcrystalline silicon layer is prepared on the intrinsic amorphous silicon layer subjected to plasma treatment, and the roughness Ra of the surface of the n-type doped microcrystalline silicon layer away from the glass is measured to be 3.68 nm. An intrinsic amorphous silicon layer is prepared on the silicon substrate by the aforementioned preparation method, and then the intrinsic amorphous silicon layer is subjected to plasma treatment. Then, a p-type doped microcrystalline silicon layer is prepared on the intrinsic amorphous silicon layer subjected to plasma treatment, and the roughness Ra of the surface of the p-type doped microcrystalline silicon layer away from the glass is measured to be 2.30 nm. It can be seen that the roughness of the surface of the n-type doped microcrystalline silicon layer and the p-type doped microcrystalline silicon layer away from the glass can indeed be improved by the aforementioned method.

[0083] The application also provides a photovoltaic module, which comprises any one of the aforementioned solar cells. The photovoltaic module can further comprise encapsulation adhesive films or other structures on the first and second sides of the solar cells, and other structures of the photovoltaic module are not specifically limited.

[0084] It should be noted that the preparation method of the solar cell, the solar cell and the photovoltaic module have the same or similar beneficial effects, and to avoid repetition, they will not be described here.

[0085] It should be noted that, for the method embodiments, the acts performed as part of the methods are combinable by way of a machine, such as a computer processed, or the like, under the control of (and based at least in part on instructions from) an application specific integrated circuit, or the like. The reader should understand that these are only illustrative of the possible uses available to those of ordinary skill in the art. Further, it should be recognized that the scope of the application encompasses combinations of the above embodiments. The actions performed as part of the computer-implemented methods can be ordered in an manner according to this detailed description; however, this should not be interpreted as a limitation on the scope of the application.

Claims

1. A solar cell, wherein, Comprising: a silicon substrate; the silicon substrate comprises: opposite first and second sides; a first semiconductor layer on the first side; a first conductive layer on a side of the first semiconductor layer facing away from the silicon substrate; in a cross-section of the solar cell, a roughness of an interface between the first semiconductor layer and the silicon substrate is less than a roughness of an interface between the first semiconductor layer and the first conductive layer.

2. The solar cell of claim 1, wherein, The roughness of the interface is a degree of fluctuation of the interface within an optional 500nm between a tower top and a tower bottom of a silicon substrate texturing structure.

3. The solar cell of claim 1, wherein, The first semiconductor layer comprises: a first surface close to the first conductive layer; the first surface comprises a plurality of concave-convex structures; at least part of the concave-convex structures in the first surface are arranged in order.

4. The solar cell of claim 1, wherein, A surface roughness of an interface between the first semiconductor layer and the first conductive layer is greater than a surface roughness of the silicon substrate.

5. The solar cell of claim 1, wherein, a roughness of an interface between the first semiconductor layer and the silicon substrate is less than or equal to 1.5nm; and / or, a roughness of an interface between the first semiconductor layer and the first conductive layer is greater than 1.5nm.

6. The solar cell of claim 1, wherein, The first semiconductor layer is composed of an intrinsic amorphous silicon layer and a doped amorphous silicon layer arranged in a stack; the intrinsic amorphous silicon layer is arranged immediately adjacent to the silicon substrate.

7. The solar cell according to any one of claims 1 to 5, wherein, The solar cell further comprises: a second semiconductor layer and a second conductive layer arranged on the second side of the silicon substrate; a doping type of the first semiconductor layer and the second semiconductor layer is different; in a cross-section of the solar cell, a roughness of an interface between the second semiconductor layer on the second side of the silicon substrate and the silicon substrate is less than a roughness of an interface between the second semiconductor layer and the second conductive layer.

8. The solar cell of claim 7, wherein, The silicon substrate and the first semiconductor layer have the same doping type; a roughness of an interface between the first semiconductor layer and the first conductive layer is greater than a roughness of an interface between the second semiconductor layer and the second conductive layer.

9. The solar cell of claim 6, wherein, The solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer arranged in a stack on the second side of the silicon substrate; the tunneling oxide layer is arranged immediately adjacent to the silicon substrate; a doping type of the doped amorphous silicon layer and the doped polysilicon layer is different.

10. The solar cell according to any one of claims 1 to 6, wherein, The first side surface of the silicon substrate comprises: a first conductive region and a second conductive region distributed at intervals; The first semiconductor layer is located on the first conductive region and on the second conductive region; a doping type of a portion of the first semiconductor layer located on the first conductive region and a portion of the first semiconductor layer located on the second conductive region is different; or, The first side surface of the silicon substrate comprises: a first conductive region and a second conductive region distributed at intervals; The first semiconductor layer is located on the first conductive region; The solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer arranged in a stack on the second conductive region; the tunneling oxide layer is arranged immediately adjacent to the silicon substrate; a doping type of the first semiconductor layer and the doped polysilicon layer is different.

11. The solar cell of claim 10, wherein, The roughness of the junction line between the doped polysilicon layer on the second conductive region and the first conductive layer is greater than the roughness of the junction line between the first semiconductor layer and the first conductive layer.

12. The solar cell according to any one of claims 1 to 6, wherein, The doping concentration of the first semiconductor layer near the side of the first conductive layer is greater than the doping concentration of the first semiconductor layer near the side of the silicon substrate.

13. A photovoltaic module, wherein, Comprise: A plurality of solar cells according to any one of claims 1 to 12.

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