Drive circuit, display panel and drive method

Abstract

A drive circuit, a display panel and a drive method, which can achieve refresh display of any row. The drive circuit comprises a node control circuit (11), a first node charging circuit (12), a first energy storage circuit (13), and an input circuit (14), wherein under the control of a scan control signal, the node control circuit (11) controls the connection or disconnection between an input node (NI) and a middle node (NZ), and controls the connection or disconnection between the middle node (NZ) and a control node (M), and under the control of the potential of the control node (M), the node control circuit (11) controls the connection or disconnection between a voltage supply node (NT) and the middle node (NZ); and under the control of the potential of the control node (M) and a set control signal, the first node charging circuit (12) controls the connection or disconnection between a first node (PU) and the voltage supply node (NT).

Description

Driving circuit, display panel and driving method

[0001] Cross-reference to Related Applications

[0002] This application claims priority to PCT application No. PCT / CN2024 / 101222 filed on June 25, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a driving circuit, a display panel and a driving method. BACKGROUND

[0004] If a related driving module wants to realize partial display by starting refreshing from a middle row of driving circuits included in the driving module, the driving circuits in the front non-display area also need to be opened row by row for cascading transmission, and thus the real arbitrary row refreshing display cannot be realized. SUMMARY

[0005] In one aspect, the present disclosure provides a driving circuit, comprising a node control circuit, a first node charging circuit, a first energy storage circuit and an input circuit.

[0006] The node control circuit is electrically connected with a scan control end, an input node, an intermediate node, a voltage supply node and a control node, respectively, for controlling the input node and the intermediate node to be connected or disconnected under the control of a scan control signal provided by the scan control end, controlling the intermediate node and the control node to be connected or disconnected, and controlling the voltage supply node and the intermediate node to be connected or disconnected under the control of the potential of the control node.

[0007] The first node charging circuit is electrically connected with the control node, a set control end, a first node and the voltage supply node, respectively, for controlling the first node and the voltage supply node to be connected or disconnected under the control of the potential of the control node and a set control signal provided by the set control end.

[0008] The first energy storage circuit is electrically connected with the control node.

[0009] The input circuit is electrically connected with an input end and the first node, respectively, for controlling the potential of the first node under the control of an input signal provided by the input end.

[0010] Optionally, the input node is electrically connected with the input end, and the driving circuit further comprises a control node reset circuit.

[0011] The control node reset circuit is electrically connected with the control reset end, the control node and the second voltage end respectively, and is used for controlling the connection or disconnection between the control node and the second voltage end under the control of a control reset signal provided by the control reset end.

[0012] Optionally, the voltage providing node is electrically connected with the first voltage end.

[0013] The input control circuit is electrically connected with the first voltage end, the input end and the input node respectively, and is used for controlling the connection or disconnection between the input end and the input node under the control of a first voltage signal provided by the first voltage end.

[0014] Optionally, the voltage providing node is electrically connected with the first voltage end.

[0015] Optionally, the driving circuit further comprises a control voltage input circuit.

[0016] The control voltage input circuit is electrically connected with a first control voltage end, a second control voltage end, an access node, the intermediate node and the voltage providing node respectively, and is used for controlling the connection or disconnection between the first control voltage end and the access node under the control of a first control voltage provided by the first control voltage end, controlling the connection or disconnection between the second control voltage end and the access node under the control of a second control voltage provided by the second control voltage end, and controlling the connection or disconnection between the access node and the voltage providing node under the control of the potential of the intermediate node.

[0017] Optionally, the node control circuit comprises a first transistor, a second transistor and a third transistor.

[0018] The gate of the first transistor is electrically connected with the scan control end, the first pole of the first transistor is electrically connected with the input node, and the second pole of the first transistor is electrically connected with the intermediate node.

[0019] The gate of the second transistor is electrically connected with the scan control end, the first pole of the second transistor is electrically connected with the intermediate node, and the second pole of the second transistor is electrically connected with the control node.

[0020] The gate of the third transistor is electrically connected with the control node, the first pole of the third transistor is electrically connected with the voltage providing node, and the second pole of the third transistor is electrically connected with the intermediate node.

[0021] The first node charging circuit comprises a fourth transistor and a fifth transistor, and the first energy storage circuit comprises a first capacitor.

[0022] a gate of the fourth transistor is electrically connected with the control node, a first electrode of the fourth transistor is electrically connected with the voltage supply node, and a second electrode of the fourth transistor is electrically connected with a first electrode of the fifth transistor;

[0023] a gate of the fifth transistor is electrically connected with the set control terminal, and a second electrode of the fifth transistor is electrically connected with the first node;

[0024] a first end of the first capacitor is electrically connected with the control node, and a second end of the first capacitor is electrically connected with the voltage supply node;

[0025] the input circuit comprises a sixth transistor;

[0026] a gate of the sixth transistor is electrically connected with a first electrode of the sixth transistor and the input terminal, and a second electrode of the sixth transistor is electrically connected with the first node.

[0027] Optionally, the control node reset circuit comprises a reset transistor;

[0028] a gate of the reset transistor is electrically connected with the control reset terminal, a first electrode of the reset transistor is electrically connected with the control node, and a second electrode of the reset transistor is electrically connected with the second voltage terminal.

[0029] Optionally, the input control circuit comprises an input control transistor;

[0030] a gate of the input control transistor is electrically connected with the first voltage terminal, a first electrode of the input control transistor is electrically connected with the input terminal, and a second electrode of the input control transistor is electrically connected with the input node.

[0031] Optionally, the control voltage input circuit comprises a first input transistor, a second input transistor and a third input transistor;

[0032] a gate of the first input transistor and a first electrode of the first input transistor are both electrically connected with the first control voltage terminal, and a second electrode of the first input transistor is electrically connected with the access node;

[0033] a gate of the second input transistor and a first electrode of the second input transistor are both electrically connected with the second control voltage terminal, and a second electrode of the second input transistor is electrically connected with the access node;

[0034] a gate of the third input transistor is electrically connected with the intermediate node, a first electrode of the third input transistor is electrically connected with the access node, and a second electrode of the third input transistor is electrically connected with the voltage supply node.

[0035] Optionally, the driving circuit further comprises a reset circuit.

[0036] The reset circuit is electrically connected with the reset control end, the first node and the second voltage end respectively, and is configured to control the first node and the second voltage end to be connected or disconnected under the control of a reset control signal provided by the reset control end.

[0037] Optionally, the driving circuit further comprises a first node reset circuit, a pull-up node control circuit, a carry signal output circuit, a driving signal output circuit and a second energy storage circuit.

[0038] The first node reset circuit is electrically connected with the pull-up reset end, the first node and the second voltage end respectively, and is configured to control the first node and the second voltage end to be connected or disconnected under the control of a pull-up reset signal provided by the pull-up reset end.

[0039] The pull-up node control circuit is electrically connected with the first second node, the second second node, the first node and the second voltage end respectively, and is configured to control the first node and the second voltage end to be connected or disconnected under the control of the potential of the first second node, and control the first node and the second voltage end to be connected or disconnected under the control of the potential of the second second node.

[0040] The carry signal output circuit is electrically connected with the first node, the first second node, the second second node, the carry signal output end, the output clock signal end and the second voltage end respectively, and is configured to control the carry signal output end and the output clock signal end to be connected or disconnected under the control of the potential of the first node, control the carry signal output end and the second voltage end to be connected or disconnected under the control of the potential of the first second node, and control the carry signal output end and the second voltage end to be connected or disconnected under the control of the potential of the second second node.

[0041] The driving signal output circuit is electrically connected with the first node, the first second node, the second second node, the driving signal output end, the output clock signal end and the third voltage end respectively, and is configured to control the driving signal output end and the output clock signal end to be connected or disconnected under the control of the potential of the first node, control the driving signal output end and the third voltage end to be connected or disconnected under the control of the potential of the first second node, and control the driving signal output end and the third voltage end to be connected or disconnected under the control of the potential of the second second node.

[0042] The first end of the second energy storage circuit is electrically connected with the first node, and the second end of the second energy storage circuit is electrically connected with the driving signal output end, and the second energy storage circuit is used for storing electric energy.

[0043] Optionally, the driving circuit further comprises a first second node control circuit and a second second node control circuit.

[0044] The first second node control circuit is electrically connected with the first control voltage end, the first intermediate control node, the first node, the first second node and the second voltage end respectively, and is used for controlling the electric potential of the first intermediate control node under the control of the first control voltage provided by the first control voltage end, controlling the first intermediate control node and the second voltage end to be connected or disconnected under the control of the electric potential of the first node, controlling the first control voltage end and the first second node to be connected or disconnected under the control of the electric potential of the first intermediate control node, and controlling the first second node and the second voltage end to be connected or disconnected under the control of the electric potential of the first node; the second second node control circuit is electrically connected with the second control voltage end, the second intermediate control node, the first node, the second second node and the second voltage end respectively, and is used for controlling the electric potential of the second intermediate control node under the control of the second control voltage provided by the second control voltage end, controlling the second intermediate control node and the second voltage end to be connected or disconnected under the control of the electric potential of the first node, controlling the second control voltage end and the second second node to be connected or disconnected under the control of the electric potential of the second intermediate control node, and controlling the second second node and the second voltage end to be connected or disconnected under the control of the electric potential of the first node; or,

[0045] The first second node control circuit is electrically connected with the first control voltage end, the first node, the first second node and the second voltage end respectively, and is used for controlling the electric potential of the first second node under the control of the first control voltage provided by the first control voltage end, and controlling the first second node and the second voltage end to be connected or disconnected under the control of the electric potential of the first node; the second second node control circuit is electrically connected with the second control voltage end, the first node, the second second node and the second voltage end respectively, and is used for controlling the electric potential of the second second node under the control of the second control voltage provided by the second control voltage end, and controlling the second second node and the second voltage end to be connected or disconnected under the control of the electric potential of the first node.

[0046] Optionally, the driving circuit further comprises a second node reset circuit.

[0047] The second node reset circuit is electrically connected with the input end, the first second node, the second second node and the second voltage end respectively, and is used for controlling the first second node and the second voltage end to be connected or disconnected and controlling the second second node and the second voltage end to be connected or disconnected under the control of an input signal provided by the input end.

[0048] Optionally, the reset circuit comprises a seventh transistor.

[0049] The gate of the seventh transistor is electrically connected with the reset control end, the first pole of the seventh transistor is electrically connected with the first node, and the second pole of the seventh transistor is electrically connected with the second voltage end.

[0050] Optionally, the first node reset circuit comprises an eighth transistor, and the pull-up node control circuit comprises a ninth transistor and a tenth transistor.

[0051] The gate of the eighth transistor is electrically connected with the pull-up reset end, the first pole of the eighth transistor is electrically connected with the first node, and the second pole of the eighth transistor is electrically connected with the second voltage end.

[0052] The gate of the ninth transistor is electrically connected with the first second node, the first pole of the ninth transistor is electrically connected with the first node, and the second pole of the ninth transistor is electrically connected with the second voltage end.

[0053] The gate of the tenth transistor is electrically connected with the second second node, the first pole of the tenth transistor is electrically connected with the first node, and the second pole of the tenth transistor is electrically connected with the second voltage end.

[0054] The carry signal output circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor.

[0055] The gate of the eleventh transistor is electrically connected with the first node, the first pole of the eleventh transistor is electrically connected with the output clock signal end, and the second pole of the eleventh transistor is electrically connected with the carry signal output end.

[0056] The gate of the twelfth transistor is electrically connected with the first second node, the first pole of the twelfth transistor is electrically connected with the carry signal output end, and the second pole of the twelfth transistor is electrically connected with the second voltage end.

[0057] The gate of the thirteenth transistor is electrically connected with the second second node, the first pole of the thirteenth transistor is electrically connected with the carry signal output end, and the second pole of the thirteenth transistor is electrically connected with the second voltage end.

[0058] The driving signal output circuit comprises a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;

[0059] The gate of the fourteenth transistor is electrically connected with the first node, the first pole of the fourteenth transistor is electrically connected with the output clock signal end, and the second pole of the fourteenth transistor is electrically connected with the driving signal output end;

[0060] The gate of the fifteenth transistor is electrically connected with the first second node, the first pole of the fifteenth transistor is electrically connected with the driving signal output end, and the second pole of the fifteenth transistor is electrically connected with the third voltage end;

[0061] The gate of the sixteenth transistor is electrically connected with the second second node, the first pole of the sixteenth transistor is electrically connected with the driving signal output end, and the second pole of the sixteenth transistor is electrically connected with the third voltage end;

[0062] The second energy storage circuit comprises a second capacitor;

[0063] The first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with the driving signal output end.

[0064] Optionally, the first second node control circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; the second second node control circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a twenty-fourth transistor; a gate of the seventeenth transistor and a first electrode of the seventeenth transistor are electrically connected with the first control voltage terminal, a second electrode of the seventeenth transistor is electrically connected with the first intermediate control node; a gate of the eighteenth transistor is electrically connected with the first node, a first electrode of the eighteenth transistor is electrically connected with the first intermediate control node, and a second electrode of the eighteenth transistor is electrically connected with the second voltage terminal; a gate of the nineteenth transistor is electrically connected with the first intermediate control node, a first electrode of the nineteenth transistor is electrically connected with the first control voltage terminal, and a second electrode of the nineteenth transistor is electrically connected with the first second node; a gate of the twentieth transistor is electrically connected with the first node, a first electrode of the twentieth transistor is electrically connected with the first second node, and a second electrode of the twentieth transistor is electrically connected with the second voltage terminal; a gate of the twenty-first transistor and a first electrode of the twenty-first transistor are electrically connected with the second control voltage terminal, a second electrode of the twenty-first transistor is electrically connected with the second intermediate control node; a gate of the twenty-second transistor is electrically connected with the first node, a first electrode of the twenty-second transistor is electrically connected with the second intermediate control node, and a second electrode of the twenty-second transistor is electrically connected with the second voltage terminal; a gate of the twenty-third transistor is electrically connected with the second intermediate control node, a first electrode of the twenty-third transistor is electrically connected with the second control voltage terminal, and a second electrode of the twenty-second transistor is electrically connected with the second second node; a gate of the twenty-fourth transistor is electrically connected with the first node, a first electrode of the twenty-fourth transistor is electrically connected with the second second node, and a second electrode of the twenty-fourth transistor is electrically connected with the second voltage terminal; or,

[0065] The first second node control circuit comprises a twenty-fifth transistor and a twenty-sixth transistor; the second second node control circuit comprises a twenty-seventh transistor and a twenty-eighth transistor; the gate of the twenty-fifth transistor and the first pole of the twenty-fifth transistor are electrically connected with a first control voltage terminal, the second pole of the twenty-fifth transistor is electrically connected with the first second node; the gate of the twenty-sixth transistor is electrically connected with the first node, the first pole of the twenty-sixth transistor is electrically connected with the first second node, and the second pole of the twenty-sixth transistor is electrically connected with the second voltage terminal; the gate of the twenty-seventh transistor and the first pole of the twenty-seventh transistor are electrically connected with a second control voltage terminal, the second pole of the twenty-seventh transistor is electrically connected with the second second node; the gate of the twenty-eighth transistor is electrically connected with the first node, the first pole of the twenty-eighth transistor is electrically connected with the second second node, and the second pole of the twenty-eighth transistor is electrically connected with the second voltage terminal.

[0066] Optionally, the second node reset circuit comprises a twenty-ninth transistor and a thirtieth transistor.

[0067] The gate of the twenty-ninth transistor is electrically connected with the input terminal, the first pole of the twenty-ninth transistor is electrically connected with the first second node, and the second pole of the twenty-ninth transistor is electrically connected with the second voltage terminal.

[0068] The gate of the thirtieth transistor is electrically connected with the input terminal, the first pole of the thirtieth transistor is electrically connected with the second second node, and the second pole of the thirtieth transistor is electrically connected with the second voltage terminal.

[0069] In a second aspect, the display panel comprises a driving module, wherein the driving module comprises a plurality of driving circuits as described above.

[0070] The input terminal of the driving circuit is electrically connected with the carry signal output terminal of the adjacent m-level driving circuit.

[0071] m is a positive integer.

[0072] Optionally, the display panel comprises a display area, and the display area comprises a first sub-display area and a second sub-display area, and the refresh rates of the first sub-display area and the second sub-display area are different.

[0073] Optionally, the display area further comprises a third sub-display area.

[0074] The refresh rates of the first sub-display area, the second sub-display area and the third sub-display area gradually increase.

[0075] In a third aspect, the display panel is driven by a driving method. The display panel comprises a display stage including a (j-1)th frame and a jth frame. The (j-1)th frame is arranged before the jth frame and is adjacent to the jth frame. The (j-1)th frame is a global display frame, and the jth frame is a local display frame. j is a positive integer greater than 1. The driving method comprises:

[0076] In the global display frame, the driving circuit of each level outputs a corresponding driving signal in sequence. The global display frame is used to charge the control node of the driving circuit of the local display frame.

[0077] Optionally, the driving method further comprises:

[0078] In the jth frame, when the (n-1)th driving circuit starts local display, in the (n-1)th driving stage included in the global display frame, the (n-1)th input end included in the (n-1)th driving circuit is connected to the effective voltage signal. The node control circuit in the (n-1)th driving circuit controls the communication between the (n-1)th input node and the (n-1)th intermediate node, controls the communication between the (n-1)th intermediate node and the (n-1)th control node, and controls the communication or disconnection between the first voltage end and the (n-1)th intermediate node under the control of the potential of the (n-1)th control node. The first energy storage circuit in the (n-1)th driving circuit maintains the potential of the (n-1)th first node.

[0079] In the (n-1)th driving stage included in the local display frame, the set control end provides an effective set control signal. The first node charging circuit in the (n-1)th driving circuit controls the communication between the (n-1)th first node and the (n-1)th voltage providing node under the control of the potential of the (n-1)th control node and the set control signal. n is a positive integer.

[0080] Optionally, the input node is electrically connected to the input end. The driving circuit further comprises a control node reset circuit. The (j+p-1)th frame is a global refresh frame. When p is greater than 2, the frames between the jth frame and the (j+p-1)th frame are global display frames, or are local display frames started by the (n-1)th driving circuit. The driving method further comprises:

[0081] In the j+p-1 frame, in the control node reset stage, the control reset end provides a valid control reset signal, and the control node reset circuit controls the communication between the control node and the second voltage end in each stage of the driving circuit under the control of the control reset signal; then, when scanning to the qth driving circuit, the node control circuit in the qth driving circuit controls the communication between the qth input node and the qth intermediate node, controls the communication between the qth intermediate node and the qth control node, and controls the communication between the qth voltage providing node and the qth intermediate node under the control of the potential of the qth control node; the first energy storage circuit in the qth driving circuit maintains the potential of the qth first node;

[0082] p is an integer greater than 1, q is a positive integer, and q is not equal to n.

[0083] Optionally, the input node is electrically connected with the input end; the driving circuit further comprises a control node reset circuit; the j+p-1 frame is a local display frame started from the nth driving circuit; when p is greater than 2, the frames between the jth frame and the j+p-1 frame are local display frames started from the nth driving circuit, or when the frames are local display frames started from the nth driving circuit, the driving method further comprises:

[0084] In the j+p-1 frame, in the control node reset stage, the control reset end provides a valid control reset signal, and the control node reset circuit controls the communication between the control node and the second voltage end in each stage of the driving circuit under the control of the control reset signal; then, when scanning to the qth driving circuit, the node control circuit in the qth driving circuit controls the communication between the qth input node and the qth intermediate node, controls the communication between the qth intermediate node and the qth control node, and controls the communication between the qth voltage providing node and the qth intermediate node under the control of the potential of the qth control node; the first energy storage circuit in the qth driving circuit maintains the potential of the qth first node;

[0085] p is a positive integer, q is a positive integer, and q is greater than n.

[0086] Optionally, the voltage providing node is electrically connected with the first voltage end; the driving circuit further comprises an input control circuit; the display stage comprises the j+r frame; the j+r-1 frame is a global refresh frame; when r is greater than 2, the frames between the jth frame and the j+r-1 frame are global display frames, or when the frames are local display frames started from the nth driving circuit, the driving method further comprises:

[0087] In the j+r-1th frame, in the control node reset stage, the first voltage terminal provides an invalid first voltage signal, the scan control terminal provides a valid scan control signal, the input control circuit in each stage of the driving circuit controls the disconnection between the input terminal and the input node in each stage under the control of the first voltage signal, the node control circuit in each stage of the driving circuit controls the communication between the intermediate node and the control node in each stage under the control of the scan control signal, and controls the communication between the voltage supply node and the intermediate node in each stage under the control of the potential of the control node in each stage; then, when scanning to the qth stage of the driving circuit, the node control circuit in the qth stage of the driving circuit controls the communication between the qth stage of the input node and the qth stage of the intermediate node, controls the communication between the qth stage of the intermediate node and the qth stage of the control node, and controls the communication between the qth stage of the voltage supply node and the qth stage of the intermediate node under the control of the potential of the qth stage of the control node; the first energy storage circuit in the qth stage of the driving circuit maintains the potential of the qth stage of the first node;

[0088] r is an integer greater than 1, and q is a positive integer.

[0089] Optionally, the input node is electrically connected with the input terminal; the driving circuit further comprises an input control circuit; the display stage comprises the j+rth frame; the j+r-1th frame is a local display frame started from the nth stage of the driving circuit; when r is greater than 2, the frames between the jth frame and the j+r-1th frame are local display frames started from the nth stage of the driving circuit, or, when the local display frame is started from the nth stage of the driving circuit, the driving method further comprises:

[0090] In the j+r-1th frame, in the control node reset stage, the first voltage terminal provides an invalid first voltage signal, the scan control terminal provides a valid scan control signal, the input control circuit in each stage of the driving circuit controls the disconnection between the input terminal and the input node in each stage under the control of the first voltage signal, the node control circuit in each stage of the driving circuit controls the communication between the intermediate node and the control node in each stage under the control of the scan control signal, and controls the communication between the voltage supply node and the intermediate node in each stage under the control of the potential of the control node in each stage; then, when scanning to the qth stage of the driving circuit, the node control circuit in the qth stage of the driving circuit controls the communication between the qth stage of the input node and the qth stage of the intermediate node, controls the communication between the qth stage of the intermediate node and the qth stage of the control node, and controls the communication between the qth stage of the voltage supply node and the qth stage of the intermediate node under the control of the potential of the qth stage of the control node; the first energy storage circuit in the qth stage of the driving circuit maintains the potential of the qth stage of the first node;

[0091] r is a positive integer, and q is a positive integer greater than n.

[0092] Optionally, the nth-stage driving circuit is cascaded with the n-kth-stage driving circuit, and the timing of the scanning control signal accessed by the nth-stage driving circuit is the same as the timing of the output clock signal accessed by the n-kth-stage driving circuit.

[0093] k is a positive integer.

[0094] Optionally, the input node is electrically connected with the input terminal; the driving circuit further comprises a reset circuit; and the driving method further comprises:

[0095] In the a-th-stage driving phase included in the local display frame, the reset circuit in the a-th driving circuit in the display device controls the communication between the a-th first node and the second voltage terminal under the control of the reset control signal;

[0096] a is a positive integer, and a is greater than n.

[0097] Optionally, when the s-th frame and the s+1-th frame are both local display frames, in the s-th frame, the termination stage of the local display is the v-th driving circuit, the driving method comprises:

[0098] In the s-th frame, after scanning the v-th driving circuit, the s+1-th frame is entered; at the beginning of the s+1-th frame, the active set control signal is provided by the set control terminal. s and v are positive integers.

[0099] Optionally, the display panel comprises a display area, the display area comprises a first sub-display area, a second sub-display area and a third sub-display area; the refresh rate of the first sub-display area, the refresh rate of the second sub-display area and the refresh rate of the third sub-display area gradually increase; the u-th frame is a global display frame, the u+1-th frame and the u+2-th frame are local display frames; u is a positive integer; and the driving method comprises:

[0100] In the u-th frame, the starting stage driving circuit corresponding to the second sub-display area is positioned;

[0101] In the u+1-th frame, the starting stage driving circuit corresponding to the third sub-display area is positioned;

[0102] In the u+1-th frame, the driving circuits corresponding to the second sub-display area and the third sub-display area are scanned, and in the u+2-th frame, the driving circuit corresponding to the third sub-display area is scanned. BRIEF DESCRIPTION OF DRAWINGS

[0103] FIG. 1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0104] FIG. 2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0105] FIG. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0106] FIG. 4 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0107] FIG. 5 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0108] FIG. 6 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0109] FIG. 7 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0110] FIG. 8 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0111] FIG. 9A is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0112] FIG. 9B is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0113] FIG. 9C is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0114] FIG. 9D is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0115] FIG. 10 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0116] FIG. 11 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0117] FIG. 12 is a structure diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0118] FIG. 13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0119] FIG. 14 is a working timing diagram of a driving module including at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure;

[0120] FIG. 15 is a simulation working timing diagram of a driving module including at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure;

[0121] FIG. 16 is a working timing diagram of a driving module including at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure;

[0122] FIG. 17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0123] FIG. 18 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0124] FIG. 19 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0125] FIG. 20 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0126] FIG. 21 is a timing diagram of operation of at least one embodiment of the driving circuit of FIG. 20;

[0127] FIG. 22A is a diagram of the operation of M1-M5 in at least one embodiment of the driving circuit of FIG. 20;

[0128] FIG. 22B is a diagram of the operation of M1-M5 in at least one embodiment of the driving circuit of FIG. 20;

[0129] FIG. 22C is a diagram of the operation of M1-M5 in at least one embodiment of the driving circuit of FIG. 20;

[0130] FIG. 22D is a diagram of the operation of M1-M5, MR in at least one embodiment of the driving circuit of FIG. 20;

[0131] FIG. 23 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0132] FIG. 24 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0133] FIG. 25 is a diagram of a division of a display area;

[0134] FIG. 26 is a timing diagram corresponding to different refresh rate application scenarios for a two-part screen;

[0135] FIG. 27 is a diagram of a division of a display area;

[0136] FIG. 28 is a timing diagram corresponding to an application scenario corresponding to FIG. 27;

[0137] FIG. 29 is a diagram of a division of a display area;

[0138] FIG. 30 is a timing diagram corresponding to an application scenario corresponding to FIG. 29 at an Nth frame;

[0139] FIG. 31 is a timing diagram corresponding to an application scenario corresponding to FIG. 29 at an N+1th frame;

[0140] FIG. 32 is a timing diagram corresponding to an application scenario corresponding to FIG. 29 at an N+2th frame and an N+3th frame;

[0141] FIG. 33 is a timing diagram corresponding to an application scenario corresponding to FIG. 29 at an N+2th frame;

[0142] FIG. 34A is a diagram of a display area;

[0143] FIG. 34B is a schematic diagram of a display region;

[0144] FIG. 34C is a schematic diagram of a display region;

[0145] FIG. 34D is a schematic diagram of a display region;

[0146] FIG. 34E is a schematic diagram of a display region;

[0147] FIG. 34F is a schematic diagram of a display region;

[0148] FIG. 35A is a structural diagram of at least one embodiment of a driving module in at least one embodiment of the present disclosure;

[0149] FIG. 35B is a structural diagram of at least one embodiment of a driving module in at least one embodiment of the present disclosure;

[0150] FIG. 36 is a structural diagram of at least one embodiment of a driving module in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0151] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0152] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one pole is called the first pole and the other pole is called the second pole.

[0153] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0154] As shown in FIG. 1, the driving circuit described in the embodiments of the present disclosure includes a node control circuit 11, a first node charging circuit 12, a first energy storage circuit 13 and an input circuit 14.

[0155] The node control circuit 11 is electrically connected with the scan control end LSP, the input node NI, the intermediate node NZ, the voltage supply node NT and the control node M respectively, for controlling the communication or disconnection between the input node NI and the intermediate node NZ under the control of the scan control signal provided by the scan control end LSP, controlling the communication or disconnection between the intermediate node NZ and the control node M, and controlling the communication or disconnection between the voltage supply node NT and the intermediate node NZ under the control of the potential of the control node M;

[0156] The first node charging circuit 12 is electrically connected with the control node M, the set control end GSET, the first node PU and the voltage supply node NT respectively, for controlling the communication or disconnection between the first node PU and the voltage supply node NT under the control of the potential of the control node M and the set control signal provided by the set control end GSET;

[0157] The first energy storage circuit 13 is electrically connected with the control node M, for maintaining the potential of the control node M;

[0158] The input circuit 14 is electrically connected with the input end I1 and the first node PU respectively, for controlling the potential of the first node PU under the control of the input signal provided by the input end I1.

[0159] In at least one embodiment of the present disclosure, the driving module comprises at least one embodiment of the driving circuit shown in Figure 1, and before a local display frame, a global display frame is provided, which is adjacent to the local display frame. When the local display frame starts to display from the nth row of driving circuit (n is a positive integer) in the local display frame, in the global display frame, when the input node NI of the nth row of driving circuit accesses the effective voltage signal, the node control circuit 11 controls the communication between the input node NI and the intermediate node NZ under the control of the scan control signal provided by the scan control end LSP, controls the communication between the intermediate node NZ and the control node M, charges the control node M through the signal provided by the input node NI, and after the potential of the control node M is raised, the node control circuit 11 controls the communication between the voltage providing node NT and the intermediate node NZ under the control of the potential of the control node M, and the control node M is further charged by the signal provided by the voltage providing node NT, which raises the potential of the control node M, and the first energy storage circuit 13 maintains the potential of the control node M; when the input node NI connected to the nth row of driving circuit accesses the invalid voltage signal, the scan control signal provided by LSP is switched to the invalid voltage signal, and at this time the high potential of the control node M is maintained by the first energy storage circuit 13; when switching from the global display frame to the local display frame, when the set control end GSET provides an effective set control signal, the first node charging circuit controls the communication between the first node PU and the voltage providing node NT under the control of the potential of the control node M and the set control signal provided by the set control end GSET, and the first node PU is charged by the signal provided by the voltage providing node NT; when the output clock signal accessed by the nth row of driving circuit is an effective voltage signal, the driving signal output circuit in the nth row of driving circuit controls the effective nth row driving signal provided by the driving signal output end under the control of the potential of the first node PU, and normally cascades to the subsequent driving circuit to realize the local display function starting from the nth row of driving circuit; if the next frame is still a local display frame starting from the nth row, no global display frame is needed, and the nth row local display function can be repeatedly realized by repeatedly inputting the set control signal.

[0160] In at least one embodiment of the present disclosure, the input node can be electrically connected to the input end, and the voltage providing node can be electrically connected to the first voltage end V1.

[0161] In at least one embodiment of the present disclosure, the input node is electrically connected to the input end; the driving circuit further comprises a control node reset circuit.

[0162] The control node reset circuit is electrically connected with the control reset end, the control node and the second voltage end respectively, and is used for controlling the communication or disconnection between the control node and the second voltage end under the control of a control reset signal provided by the control reset end.

[0163] In a specific implementation, the input node can be electrically connected with the input end; the driving circuit can further include a control node reset circuit; and the control node reset circuit controls the communication or disconnection between the control node and the second voltage end under the control of the control reset signal.

[0164] Optionally, the voltage providing node can be electrically connected with the first voltage end.

[0165] In a specific implementation, the driving circuit can further include a control node reset circuit; and a control reset signal provided by a control reset end can reset the potential of the control node, so that the driving circuit has no risk of abnormal output.

[0166] As shown in FIG. 2, based on at least one embodiment of the driving circuit shown in FIG. 1, the input node NI is electrically connected with the input end I1, and the voltage providing node is electrically connected with the first voltage end V1; the driving circuit further includes a control node reset circuit 15.

[0167] The control node reset circuit 15 is electrically connected with the control reset end LSTV0, the control node M and the second voltage end V2 respectively, and is used for controlling the communication or disconnection between the control node M and the second voltage end V2 under the control of a control reset signal provided by the control reset end LSTV0.

[0168] The first end of the first energy storage circuit 13 is electrically connected with the control node M, and the second end of the first energy storage circuit 13 is electrically connected with the first voltage end V1.

[0169] In a specific implementation, the input node can be electrically connected with the input end; the driving circuit can further include a control node reset circuit; and the control node reset circuit controls the communication or disconnection between the control node and the second voltage end under the control of the control reset signal.

[0170] Optionally, the first voltage end can be a power supply voltage end, and the second voltage end can be a first low voltage end.

[0171] In at least one embodiment of the present disclosure, the voltage providing node is electrically connected with the first voltage end; the driving circuit further includes an input control circuit;

[0172] The input control circuit is electrically connected with the first voltage terminal, the input terminal and the input node respectively, and is used for controlling the communication or disconnection between the input terminal and the input node under the control of the first voltage signal provided by the first voltage terminal.

[0173] As shown in FIG. 3, on the basis of at least one embodiment of the driving circuit shown in FIG. 1, the voltage providing node is electrically connected with the first voltage terminal V1; the driving circuit can further include an input control circuit 16;

[0174] The input control circuit 16 is electrically connected with the first voltage terminal V1, the input terminal I1 and the input node NI respectively, and is used for controlling the communication or disconnection between the input terminal I1 and the input node NI under the control of the first voltage signal provided by the first voltage terminal V1.

[0175] The first end of the first energy storage circuit 13 is electrically connected with the control node M, and the second end of the first energy storage circuit 13 is electrically connected with the second voltage terminal V2.

[0176] In at least one embodiment of the driving circuit shown in FIG. 3, when the potential of the control node M needs to be reset, the electric position of the first voltage signal provided by the first voltage terminal V1 is low, the LSP provides an effective scanning control signal, the charge stored in the first energy storage circuit 13 is released to the first voltage terminal V1 through the node control circuit 11, and the transistor included in the input control circuit 16 is closed to ensure that the charge released by the first energy storage circuit 13 does not affect the input signal, so as to avoid abnormal display.

[0177] In the input stage, the first voltage terminal V1 provides a high voltage signal, and the input control circuit 16 controls the communication between the input terminal I1 and the input node NI, so as to provide the input signal provided by the input terminal I1 to the input node NI.

[0178] As shown in FIG. 4, on the basis of at least one embodiment of the driving circuit shown in FIG. 1, the input node is electrically connected with the input terminal; the driving circuit further includes a control node reset circuit 15 and a control voltage input circuit 17.

[0179] The control node reset circuit 15 is electrically connected with the control reset terminal LSTV0, the control node M and the second voltage terminal V2 respectively, and is used for controlling the communication or disconnection between the control node M and the second voltage terminal V2 under the control of the control reset signal provided by the control reset terminal LSTV0.

[0180] The first end of the first energy storage circuit 13 is electrically connected with the control node M, and the second end of the first energy storage circuit 13 is electrically connected with the voltage providing node NT.

[0181] The control voltage input circuit 17 is electrically connected with the first control voltage terminal VDDO, the second control voltage terminal VDDE, the access node NJ, the intermediate node NZ and the voltage supply node NT, for controlling the communication or disconnection between the first control voltage terminal VDDO and the access node NJ under the control of the first control voltage provided by the first control voltage terminal VDDO, controlling the communication or disconnection between the second control voltage terminal VDDE and the access node NJ under the control of the second control voltage provided by the second control voltage terminal VDDE, and controlling the communication or disconnection between the access node NJ and the voltage supply node NT under the control of the potential of the intermediate node NZ.

[0182] In at least one embodiment of the driving circuit shown in FIG. 4 of the present disclosure, the existing first control voltage terminal VDDO and the second control voltage terminal VDDE are used to replace the function of the first voltage terminal, thereby reducing the complexity of IC (integrated circuit) design.

[0183] Optionally, the node control circuit comprises a first transistor, a second transistor and a third transistor.

[0184] The gate of the first transistor is electrically connected with the scan control terminal, the first pole of the first transistor is electrically connected with the input node, and the second pole of the first transistor is electrically connected with the intermediate node.

[0185] The gate of the second transistor is electrically connected with the scan control terminal, the first pole of the second transistor is electrically connected with the intermediate node, and the second pole of the second transistor is electrically connected with the control node.

[0186] The gate of the third transistor is electrically connected with the control node, the first pole of the third transistor is electrically connected with the voltage supply node, and the second pole of the third transistor is electrically connected with the intermediate node.

[0187] The first node charging circuit comprises a fourth transistor and a fifth transistor, and the first energy storage circuit comprises a first capacitor.

[0188] The gate of the fourth transistor is electrically connected with the control node, the first pole of the fourth transistor is electrically connected with the voltage supply node, and the second pole of the fourth transistor is electrically connected with the first pole of the fifth transistor.

[0189] The gate of the fifth transistor is electrically connected with the set control terminal, and the second pole of the fifth transistor is electrically connected with the first node.

[0190] The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the voltage supply node.

[0191] The input circuit comprises a sixth transistor;

[0192] The gate of the sixth transistor is electrically connected with the first pole of the sixth transistor and the input end, and the second pole of the sixth transistor is electrically connected with the first node.

[0193] Optionally, the control node reset circuit comprises a reset transistor;

[0194] The gate of the reset transistor is electrically connected with the control reset end, the first pole of the reset transistor is electrically connected with the control node, and the second pole of the reset transistor is electrically connected with the second voltage end.

[0195] Optionally, the input control circuit comprises an input control transistor;

[0196] The gate of the input control transistor is electrically connected with the first voltage end, the first pole of the input control transistor is electrically connected with the input end, and the second pole of the input control transistor is electrically connected with the input node.

[0197] Optionally, the control voltage input circuit comprises a first input transistor, a second input transistor and a third input transistor;

[0198] The gate of the first input transistor is electrically connected with the first pole of the first input transistor, and both are electrically connected with the first control voltage end, and the second pole of the first input transistor is electrically connected with the access node;

[0199] The gate of the second input transistor is electrically connected with the first pole of the second input transistor, and both are electrically connected with the second control voltage end, and the second pole of the second input transistor is electrically connected with the access node;

[0200] The gate of the third input transistor is electrically connected with the intermediate node, the first pole of the third input transistor is electrically connected with the access node, and the second pole of the third input transistor is electrically connected with the voltage providing node.

[0201] The driving circuit in at least one embodiment of the present disclosure further comprises a reset circuit;

[0202] The reset circuit is electrically connected with a reset control end, the first node and a second voltage end respectively, and is used for controlling the first node and the second voltage end to be connected or disconnected under the control of a reset control signal provided by the reset control end.

[0203] In specific implementation, the driving circuit can further comprise a reset circuit, which controls the first node and the second voltage end to be connected or disconnected under the control of a reset control signal.

[0204] Optionally, the second voltage terminal can be a first low voltage terminal.

[0205] As shown in FIG. 5, on the basis of at least one embodiment of the driving circuit shown in FIG. 1, the driving circuit described in at least one embodiment of the present disclosure further comprises a reset circuit 21.

[0206] The reset circuit 21 is electrically connected with a reset control terminal STV, the first node PU and a second voltage terminal V2 respectively, and is configured to control the first node PU and the second voltage terminal V2 to be in communication or disconnected under the control of a reset control signal provided by the reset control terminal STV.

[0207] When the reset control signal is a valid voltage signal, the reset circuit 21 controls the first node PU and the second voltage terminal V2 to be in communication under the control of the reset control signal provided by the reset control terminal STV, so as to reset the potential of PU, so that the corresponding row driving circuit outputs an invalid driving signal, the corresponding row driving circuit is closed, and it can be determined which row the display stops at. The reset control signal is used as a local display stop control signal, and in global scanning, the reset control signal is used as a frame reset signal, so as to reset the PU node before a frame starts.

[0208] As shown in FIG. 6, on the basis of at least one embodiment of the driving circuit shown in FIG. 2, the driving circuit described in at least one embodiment of the present disclosure further comprises a reset circuit 21.

[0209] The reset circuit 21 is electrically connected with a reset control terminal STV, the first node PU and a second voltage terminal V2 respectively, and is configured to control the first node PU and the second voltage terminal V2 to be in communication or disconnected under the control of a reset control signal provided by the reset control terminal STV.

[0210] As shown in FIG. 7, on the basis of at least one embodiment of the driving circuit shown in FIG. 3, the driving circuit described in at least one embodiment of the present disclosure further comprises a reset circuit 21.

[0211] The reset circuit 21 is electrically connected with a reset control terminal STV, the first node PU and a second voltage terminal V2 respectively, and is configured to control the first node PU and the second voltage terminal V2 to be in communication or disconnected under the control of a reset control signal provided by the reset control terminal STV.

[0212] As shown in FIG. 8, on the basis of at least one embodiment of the driving circuit shown in FIG. 4, the driving circuit described in at least one embodiment of the present disclosure further comprises a reset circuit 21.

[0213] The reset circuit 21 is electrically connected with a reset control end STV, the first node PU and a second voltage end V2 respectively, and is used for controlling the first node PU and the second voltage end V2 to be connected or disconnected under the control of a reset control signal provided by the reset control end STV.

[0214] The driving circuit further comprises a first node reset circuit, a pull-up node control circuit, a carry signal output circuit, a driving signal output circuit and a second energy storage circuit.

[0215] The first node reset circuit is electrically connected with a pull-up reset end, the first node and the second voltage end respectively, and is used for controlling the first node and the second voltage end to be connected or disconnected under the control of a pull-up reset signal provided by the pull-up reset end.

[0216] The pull-up node control circuit is electrically connected with a first second node, a second second node, the first node and the second voltage end respectively, and is used for controlling the first node and the second voltage end to be connected or disconnected under the control of the potential of the first second node, and controlling the first node and the second voltage end to be connected or disconnected under the control of the potential of the second second node.

[0217] The carry signal output circuit is electrically connected with the first node, the first second node, the second second node, a carry signal output end, an output clock signal end and the second voltage end respectively, and is used for controlling the carry signal output end and the output clock signal end to be connected or disconnected under the control of the potential of the first node, controlling the carry signal output end and the second voltage end to be connected or disconnected under the control of the potential of the first second node, and controlling the carry signal output end and the second voltage end to be connected or disconnected under the control of the potential of the second second node.

[0218] The driving signal output circuit is electrically connected with the first node, the first second node, the second second node, a driving signal output end, an output clock signal end and a third voltage end respectively, and is used for controlling the driving signal output end and the output clock signal end to be connected or disconnected under the control of the potential of the first node, controlling the driving signal output end and the third voltage end to be connected or disconnected under the control of the potential of the first second node, and controlling the driving signal output end and the third voltage end to be connected or disconnected under the control of the potential of the second second node.

[0219] The first end of the second energy storage circuit is electrically connected with the first node, the second end of the second energy storage circuit is electrically connected with the driving signal output end, and the second energy storage circuit is used for storing electric energy.

[0220] In a specific implementation, the driving circuit can further include a first node reset circuit, a pull-up node control circuit, a carry signal output circuit, a driving signal output circuit, and a second energy storage circuit. The first node reset circuit is controlled by a pull-up reset signal to control the communication or disconnection between the first node and the second voltage terminal. The pull-up node control circuit is controlled by the potential of the first second node to control the communication or disconnection between the first node and the second voltage terminal, and is controlled by the potential of the second second node to control the communication or disconnection between the first node and the second voltage terminal. The carry signal output circuit is controlled by the potential of the first node to control the communication or disconnection between the carry signal output terminal and the output clock signal terminal, is controlled by the potential of the first second node to control the communication or disconnection between the carry signal output terminal and the second voltage terminal, and is controlled by the potential of the second second node to control the communication or disconnection between the carry signal output terminal and the second voltage terminal. The driving signal output circuit is controlled by the potential of the first node to control the communication or disconnection between the driving signal output terminal and the output clock signal terminal, is controlled by the potential of the first second node to control the communication or disconnection between the driving signal output terminal and the third voltage terminal, and is controlled by the potential of the second second node to control the communication or disconnection between the driving signal output terminal and the third voltage terminal. The carry signal output circuit outputs a carry signal for cascading through the carry signal. The driving signal output circuit outputs a driving signal for driving a corresponding row scanning line. The driving circuit can further include a second energy storage circuit, which can control the potential of the first node according to the driving signal.

[0221] In at least one embodiment of the present disclosure, the driving circuit uses two second nodes as an example for illustration. In a specific implementation, the driving circuit can also use only one second node.

[0222] Optionally, the second voltage terminal can be a first low voltage terminal, and the third voltage terminal can be a second low voltage terminal.

[0223] The driving circuit described in at least one embodiment of the present disclosure can further include a first second node control circuit and a second second node control circuit.

[0224] The first second node control circuit is electrically connected with the first control voltage terminal, the first node, the first second node and the second voltage terminal respectively, and is used for controlling the electric potential of the first intermediate control node under the control of the first control voltage provided by the first control voltage terminal, controlling the communication or disconnection between the first intermediate control node and the second voltage terminal under the control of the electric potential of the first node, controlling the communication or disconnection between the first control voltage terminal and the first second node under the control of the electric potential of the first intermediate control node, and controlling the communication or disconnection between the first second node and the second voltage terminal under the control of the electric potential of the first node; and the second second node control circuit is electrically connected with the second control voltage terminal, the second node, the second second node and the second voltage terminal respectively, and is used for controlling the electric potential of the second intermediate control node under the control of the second control voltage provided by the second control voltage terminal, controlling the communication or disconnection between the second intermediate control node and the second voltage terminal under the control of the electric potential of the first node, controlling the communication or disconnection between the second control voltage terminal and the second second node under the control of the electric potential of the second intermediate control node, and controlling the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node.

[0225] The first second node control circuit is electrically connected with the first control voltage terminal, the first node, the first second node and the second voltage terminal respectively, and is used for controlling the electric potential of the first second node under the control of the first control voltage provided by the first control voltage terminal, and controlling the communication or disconnection between the first second node and the second voltage terminal under the control of the electric potential of the first node; and the second second node control circuit is electrically connected with the second control voltage terminal, the first node, the second second node and the second voltage terminal respectively, and is used for controlling the electric potential of the second second node under the control of the second control voltage provided by the second control voltage terminal, and controlling the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node.

[0226] As shown in FIG. 9A, on the basis of at least one embodiment of the driving circuit shown in FIG. 5, the driving circuit provided by at least one embodiment of the present disclosure further comprises a first node reset circuit 31, an upper pull node control circuit 32, a carry signal output circuit 41, a driving signal output circuit 42, a second energy storage circuit 43, a first second node control circuit 51 and a second second node control circuit 52.

[0227] The first node reset circuit 31 is electrically connected with the pull-up reset end RSTP, the first node PU and the second voltage end V2 respectively, and is used for controlling the first node PU to be connected or disconnected with the second voltage end V2 under the control of a pull-up reset signal provided by the pull-up reset end RSTP;

[0228] The pull-up node control circuit 32 is electrically connected with the first second node PD1, the second second node PD2, the first node PU and the second voltage end V2 respectively, and is used for controlling the first node PU to be connected or disconnected with the second voltage end V2 under the control of the potential of the first second node PD1, and controlling the first node PU to be connected or disconnected with the second voltage end V2 under the control of the potential of the second second node PD2;

[0229] The carry signal output circuit 41 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, the carry signal output end OC, the output clock signal end CLK and the second voltage end V2 respectively, and is used for controlling the carry signal output end OC to be connected or disconnected with the output clock signal end CLK under the control of the potential of the first node PU, controlling the carry signal output end OC to be connected or disconnected with the second voltage end V2 under the control of the potential of the first second node PD1, and controlling the carry signal output end OC to be connected or disconnected with the second voltage end V2 under the control of the potential of the second second node PD2;

[0230] The drive signal output circuit 42 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, the drive signal output end GT, the output clock signal end CLK and the third voltage end V3 respectively, and is used for controlling the drive signal output end GT to be connected or disconnected with the output clock signal end CLK under the control of the potential of the first node PU, controlling the drive signal output end GT to be connected or disconnected with the third voltage end V3 under the control of the potential of the first second node PD1, and controlling the drive signal output end GT to be connected or disconnected with the third voltage end V3 under the control of the potential of the second second node PD2;

[0231] The first end of the second energy storage circuit 43 is electrically connected with the first node PU, the second end of the second energy storage circuit 43 is electrically connected with the drive signal output end GT, and the second energy storage circuit 43 is used for storing electric energy;

[0232] The first second node control circuit 51 is electrically connected with the first control voltage terminal VDDO, the first intermediate control node PD CN1, the first node PU, the first second node PD1 and the second voltage terminal V2 respectively, and is configured to control the potential of the first intermediate control node PD CN1 under the control of the first control voltage provided by the first control voltage terminal VDDO, control the communication or disconnection between the first intermediate control node PD CN1 and the second voltage terminal V2 under the control of the potential of the first node PU, control the communication or disconnection between the first control voltage terminal VDDO and the first second node PD1 under the control of the potential of the first intermediate control node PD CN1, and control the communication or disconnection between the first second node PD2 and the second voltage terminal V2 under the control of the potential of the first node PU.

[0233] The second second node control circuit 52 is electrically connected with the second control voltage terminal VDDE, the second intermediate control node PD CN2, the first node PU, the second second node PD2 and the second voltage terminal V2 respectively, and is configured to control the potential of the second intermediate control node PD CN2 under the control of the second control voltage provided by the second control voltage terminal VDD3, control the communication or disconnection between the second intermediate control node PD CN2 and the second voltage terminal V2 under the control of the potential of the first node PU, control the communication or disconnection between the second control voltage terminal VDDE and the second second node PD2 under the control of the potential of the second intermediate control node PD CN2, and control the communication or disconnection between the second second node PD2 and the second voltage terminal V2 under the control of the potential of the first node PU.

[0234] As shown in FIG. 9B, on the basis of at least one embodiment of the driving circuit shown in FIG. 9A, the input node is electrically connected with the input terminal, and the voltage providing node is electrically connected with the first voltage terminal V1; the driving circuit further comprises a control node reset circuit 15.

[0235] The control node reset circuit 15 is electrically connected with the control reset terminal LSTV0, the control node M and the second voltage terminal V2 respectively, and is configured to control the communication or disconnection between the control node M and the second voltage terminal V2 under the control of the control reset signal provided by the control reset terminal LSTV0.

[0236] The first end of the first energy storage circuit 13 is electrically connected with the control node M, and the second end of the first energy storage circuit 13 is electrically connected with the first voltage terminal V1.

[0237] As shown in FIG. 9C, on the basis of at least one embodiment of the driving circuit shown in FIG. 9A, the voltage providing node is electrically connected with the first voltage terminal V1; the driving circuit can further include an input control circuit 16;

[0238] The input control circuit 16 is electrically connected with the first voltage terminal V1, the input terminal I1 and the input node NI respectively, for controlling the communication or disconnection between the input terminal I1 and the input node NI under the control of the first voltage signal provided by the first voltage terminal V1.

[0239] The first end of the first energy storage circuit 13 is electrically connected with the control node M, and the second end of the first energy storage circuit 13 is electrically connected with the second voltage terminal V2.

[0240] As shown in FIG. 9D, on the basis of at least one embodiment of the driving circuit shown in FIG. 9A, the input node is electrically connected with the input terminal; the driving circuit further includes a control node reset circuit 15 and a control voltage input circuit 17;

[0241] The control node reset circuit 15 is electrically connected with the control reset terminal LSTV0, the control node M and the second voltage terminal V2 respectively, for controlling the communication or disconnection between the control node M and the second voltage terminal V2 under the control of the control reset signal provided by the control reset terminal LSTV0.

[0242] The first end of the first energy storage circuit 13 is electrically connected with the control node M, and the second end of the first energy storage circuit 13 is electrically connected with the voltage providing node NT.

[0243] The control voltage input circuit 17 is electrically connected with the first control voltage terminal VDDO, the second control voltage terminal VDDE, the access node NJ, the intermediate node NZ and the voltage providing node NT respectively, for controlling the communication or disconnection between the first control voltage terminal VDDO and the access node NJ under the control of the first control voltage provided by the first control voltage terminal VDDO, controlling the communication or disconnection between the second control voltage terminal VDDE and the access node NJ under the control of the second control voltage provided by the second control voltage terminal VDDE, and controlling the communication or disconnection between the access node NJ and the voltage providing node NT under the control of the potential of the intermediate node NZ.

[0244] In at least one embodiment of the present disclosure, VDDO and VDDE work alternately, for example, every predetermined time, VDDO and VDDE work alternately; optionally, the predetermined time can be greater than or equal to 2s, for example, the predetermined time can be 5s, VDDO works for 5s, and then switches to VDDE; VDDE works for 5s, and then switches to VDDO.

[0245] As shown in FIG. 10, on the basis of at least one embodiment of the driving circuit shown in FIG. 5, the driving circuit described in at least one embodiment of the present disclosure further comprises a first node reset circuit 31, a pull-up node control circuit 32, a carry signal output circuit 41, a driving signal output circuit 42, a second energy storage circuit 43, a first second node control circuit 51 and a second second node control circuit 52;

[0246] The first node reset circuit 31 is electrically connected with a pull-up reset end RSTP, the first node PU and a second voltage end V2 respectively, and is used for controlling the first node PU to be connected or disconnected with the second voltage end V2 under the control of a pull-up reset signal provided by the pull-up reset end RSTP;

[0247] The pull-up node control circuit 32 is electrically connected with a first second node PD1, a second second node PD2, the first node PU and the second voltage end V2 respectively, and is used for controlling the first node PU to be connected or disconnected with the second voltage end V2 under the control of the potential of the first second node PD1, and controlling the first node PU to be connected or disconnected with the second voltage end V2 under the control of the potential of the second second node PD2;

[0248] The carry signal output circuit 41 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, a carry signal output end OC, an output clock signal end CLK and the second voltage end V2 respectively, and is used for controlling the carry signal output end OC to be connected or disconnected with the output clock signal end CLK under the control of the potential of the first node PU, controlling the carry signal output end OC to be connected or disconnected with the second voltage end V2 under the control of the potential of the first second node PD1, and controlling the carry signal output end OC to be connected or disconnected with the second voltage end V2 under the control of the potential of the second second node PD2;

[0249] The driving signal output circuit 42 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, a driving signal output end GT, the output clock signal end CLK and a third voltage end V3 respectively, and is used for controlling the driving signal output end GT to be connected or disconnected with the output clock signal end CLK under the control of the potential of the first node PU, controlling the driving signal output end GT to be connected or disconnected with the third voltage end V3 under the control of the potential of the first second node PD1, and controlling the driving signal output end GT to be connected or disconnected with the third voltage end V3 under the control of the potential of the second second node PD2;

[0250] The first end of the second energy storage circuit 43 is electrically connected with the first node PU, and the second end of the second energy storage circuit 43 is electrically connected with the driving signal output end GT, and the second energy storage circuit 43 is used for storing electric energy.

[0251] The first second node control circuit 51 is electrically connected with the first control voltage end VDDO, the first node PU, the first second node PD1 and the second voltage end V2 respectively, and is used for controlling the electric potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage end VDDO and controlling the communication or disconnection between the first second node PD1 and the second voltage end V2 under the control of the electric potential of the first node PU.

[0252] The second second node control circuit 52 is electrically connected with the second control voltage end VDDE, the first node PU, the second second node PD2 and the second voltage end V2 respectively, and is used for controlling the electric potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage end VDDE and controlling the communication or disconnection between the second second node PD2 and the second voltage end V2 under the control of the electric potential of the first node PU.

[0253] The driving circuit in at least one embodiment of the present disclosure further comprises a second node reset circuit.

[0254] The second node reset circuit is electrically connected with the input end, the first second node, the second second node and the second voltage end respectively, and is used for controlling the communication or disconnection between the first second node and the second voltage end and controlling the communication or disconnection between the second second node and the second voltage end under the control of the input signal provided by the input end.

[0255] In specific implementation, the driving circuit can further comprise a second node reset circuit, which controls the communication or disconnection between the first second node and the second voltage end and controls the communication or disconnection between the second second node and the second voltage end under the control of the input signal.

[0256] As shown in FIG. 11, on the basis of at least one embodiment of the driving circuit shown in FIG. 9A, the driving circuit in at least one embodiment of the present disclosure further comprises a second node reset circuit 71.

[0257] The second node reset circuit 71 is electrically connected with the input end I1, the first second node PD1, the second second node PD2 and the second voltage end V2 respectively, and is used for controlling the first second node PD1 and the second voltage end V2 to be connected or disconnected and controlling the second second node PD2 and the second voltage end V2 to be connected or disconnected under the control of the input signal provided by the input end I1.

[0258] As shown in FIG. 12, on the basis of at least one embodiment of the driving circuit shown in FIG. 10, the driving circuit described in at least one embodiment of the present disclosure further comprises a second node reset circuit 71;

[0259] The second node reset circuit 71 is electrically connected with the input end I1, the first second node PD1, the second second node PD2 and the second voltage end V2 respectively, and is used for controlling the first second node PD1 and the second voltage end V2 to be connected or disconnected and controlling the second second node PD2 and the second voltage end V2 to be connected or disconnected under the control of the input signal provided by the input end I1.

[0260] Optionally, the reset circuit comprises a seventh transistor;

[0261] The gate of the seventh transistor is electrically connected with the reset control end, the first pole of the seventh transistor is electrically connected with the first node, and the second pole of the seventh transistor is electrically connected with the second voltage end.

[0262] Optionally, the first node reset circuit comprises an eighth transistor, and the pull-up node control circuit comprises a ninth transistor and a tenth transistor;

[0263] The gate of the eighth transistor is electrically connected with the pull-up reset end, the first pole of the eighth transistor is electrically connected with the first node, and the second pole of the eighth transistor is electrically connected with the second voltage end;

[0264] The gate of the ninth transistor is electrically connected with the first second node, the first pole of the ninth transistor is electrically connected with the first node, and the second pole of the ninth transistor is electrically connected with the second voltage end;

[0265] The gate of the tenth transistor is electrically connected with the second second node, the first pole of the tenth transistor is electrically connected with the first node, and the second pole of the tenth transistor is electrically connected with the second voltage end.

[0266] Optionally, the carry signal output circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0267] The gate of the eleventh transistor is electrically connected with the first node, the first pole of the eleventh transistor is electrically connected with the output clock signal end, and the second pole of the eleventh transistor is electrically connected with the carry signal output end;

[0268] The gate of the twelfth transistor is electrically connected with the first second node, the first pole of the twelfth transistor is electrically connected with the carry signal output end, and the second pole of the twelfth transistor is electrically connected with the second voltage end;

[0269] The gate of the thirteenth transistor is electrically connected with the second second node, the first pole of the thirteenth transistor is electrically connected with the carry signal output end, and the second pole of the thirteenth transistor is electrically connected with the second voltage end;

[0270] The driving signal output circuit comprises a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;

[0271] The gate of the fourteenth transistor is electrically connected with the first node, the first pole of the fourteenth transistor is electrically connected with the output clock signal end, and the second pole of the fourteenth transistor is electrically connected with the driving signal output end;

[0272] The gate of the fifteenth transistor is electrically connected with the first second node, the first pole of the fifteenth transistor is electrically connected with the driving signal output end, and the second pole of the fifteenth transistor is electrically connected with the third voltage end;

[0273] The gate of the sixteenth transistor is electrically connected with the second second node, the first pole of the sixteenth transistor is electrically connected with the driving signal output end, and the second pole of the sixteenth transistor is electrically connected with the third voltage end.

[0274] Optionally, the second energy storage circuit comprises a second capacitor;

[0275] The first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with the driving signal output end.

[0276] Optionally, the first second node control circuit comprises a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor;

[0277] The gate of the seventeenth transistor and the first pole of the seventeenth transistor are electrically connected with the first control voltage end, and the second pole of the seventeenth transistor is electrically connected with the first intermediate control node;

[0278] The gate of the eighteenth transistor is electrically connected with the first node, the first pole of the eighteenth transistor is electrically connected with the first intermediate control node, and the second pole of the eighteenth transistor is electrically connected with the second voltage end;

[0279] The gate of the nineteenth transistor is electrically connected with the first intermediate control node, the first pole of the nineteenth transistor is electrically connected with the first control voltage end, and the second pole of the nineteenth transistor is electrically connected with the first second node;

[0280] The gate of the twentieth transistor is electrically connected with the first node, the first pole of the twentieth transistor is electrically connected with the first second node, and the second pole of the twentieth transistor is electrically connected with the second voltage end;

[0281] The second second node control circuit includes twenty-first, twenty-second, twenty-third and twenty-fourth transistors;

[0282] The gate of the twenty-first transistor and the first pole of the twenty-first transistor are electrically connected with the second control voltage end, and the second pole of the twenty-first transistor is electrically connected with the second intermediate control node;

[0283] The gate of the twenty-second transistor is electrically connected with the first node, the first pole of the twenty-second transistor is electrically connected with the second intermediate control node, and the second pole of the twenty-second transistor is electrically connected with the second voltage end;

[0284] The gate of the twenty-third transistor is electrically connected with the second intermediate control node, the first pole of the twenty-third transistor is electrically connected with the second control voltage end, and the second pole of the twenty-second transistor is electrically connected with the second second node;

[0285] The gate of the twenty-fourth transistor is electrically connected with the first node, the first pole of the twenty-fourth transistor is electrically connected with the second second node, and the second pole of the twenty-fourth transistor is electrically connected with the second voltage end.

[0286] Optionally, the first second node control circuit includes twenty-fifth and twenty-sixth transistors;

[0287] The gate of the twenty-fifth transistor and the first pole of the twenty-fifth transistor are electrically connected with the first control voltage end, and the second pole of the twenty-fifth transistor is electrically connected with the first second node;

[0288] The gate of the twenty-sixth transistor is electrically connected with the first node, the first pole of the twenty-sixth transistor is electrically connected with the first second node, and the second pole of the twenty-sixth transistor is electrically connected with the second voltage terminal;

[0289] The second second node control circuit comprises a twenty-seventh transistor and a twenty-eighth transistor;

[0290] The gate of the twenty-seventh transistor is electrically connected with the first pole of the twenty-seventh transistor, and the second pole of the twenty-seventh transistor is electrically connected with the second second node;

[0291] The gate of the twenty-eighth transistor is electrically connected with the first node, the first pole of the twenty-eighth transistor is electrically connected with the second second node, and the second pole of the twenty-eighth transistor is electrically connected with the second voltage terminal.

[0292] Optionally, the second node reset circuit comprises a twenty-ninth transistor and a thirtieth transistor;

[0293] The gate of the twenty-ninth transistor is electrically connected with the input terminal, the first pole of the twenty-ninth transistor is electrically connected with the first second node, and the second pole of the twenty-ninth transistor is electrically connected with the second voltage terminal.

[0294] The gate of the thirtieth transistor is electrically connected with the input terminal, the first pole of the thirtieth transistor is electrically connected with the second second node, and the second pole of the thirtieth transistor is electrically connected with the second voltage terminal.

[0295] As shown in FIG. 13, on the basis of at least one embodiment of the driving circuit shown in FIG. 9A, the input node is electrically connected with the input terminal I1, and the voltage supply node is electrically connected with the power voltage terminal VDD;

[0296] The node control circuit comprises a first transistor M1, a second transistor M2 and a third transistor M3;

[0297] The gate of the first transistor M1 is electrically connected with the scan control terminal LSP, the drain of the first transistor M1 is electrically connected with the input terminal I1, and the source of the first transistor M1 is electrically connected with the intermediate node NZ;

[0298] The gate of the second transistor M2 is electrically connected with the scan control terminal LSP, the drain of the second transistor M2 is electrically connected with the intermediate node NZ, and the second pole of the second transistor M2 is electrically connected with the control node M;

[0299] A gate of the third transistor M3 is electrically connected with the control node M, a drain of the third transistor M3 is electrically connected with the power voltage terminal VDD, and a source of the third transistor M3 is electrically connected with the intermediate node NZ;

[0300] The first node charging circuit comprises a fourth transistor M4 and a fifth transistor M5, and the first energy storage circuit comprises a first capacitor C1;

[0301] A gate of the fourth transistor M4 is electrically connected with the control node M, a drain of the fourth transistor M4 is electrically connected with the power voltage terminal VDD, and a source of the fourth transistor M4 is electrically connected with a drain of the fifth transistor M5;

[0302] A gate of the fifth transistor M5 is electrically connected with the setting control terminal GSET, and a source of the fifth transistor M5 is electrically connected with the first node PU;

[0303] A first end of the first capacitor C1 is electrically connected with the control node M, and a second end of the first capacitor C1 is electrically connected with the power voltage terminal VDD;

[0304] The input circuit comprises a sixth transistor M6;

[0305] A gate of the sixth transistor M6 is electrically connected with a drain of the sixth transistor M6 and the input terminal I1, and a source of the sixth transistor M6 is electrically connected with the first node PU;

[0306] The reset circuit comprises a seventh transistor M7;

[0307] A gate of the seventh transistor M7 is electrically connected with the reset control terminal STV, a drain of the seventh transistor M7 is electrically connected with the first node PU, and a source of the seventh transistor M7 is electrically connected with the first low voltage terminal LVSS;

[0308] The first node reset circuit comprises an eighth transistor M8, and the pull-up node control circuit comprises a ninth transistor M9 and a tenth transistor M10;

[0309] A gate of the eighth transistor M8 is electrically connected with the pull-up reset terminal RSTP, a drain of the eighth transistor M8 is electrically connected with the first node PU, and a source of the eighth transistor M8 is electrically connected with the first low voltage terminal LVSS;

[0310] A gate of the ninth transistor M9 is electrically connected with the first second node PD1, a drain of the ninth transistor M9 is electrically connected with the first node PU, and a source of the ninth transistor M9 is electrically connected with the first low voltage terminal LVSS;

[0311] The gate of the tenth transistor M10 is electrically connected with the second node PD2, the drain of the tenth transistor is electrically connected with the first node PU, and the source of the tenth transistor M9 is electrically connected with the first low voltage terminal LVSS;

[0312] The carry signal output circuit comprises an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13;

[0313] The gate of the eleventh transistor M11 is electrically connected with the first node PU, the drain of the eleventh transistor M11 is electrically connected with the output clock signal terminal CLK, and the source of the eleventh transistor M11 is electrically connected with the carry signal output terminal OC;

[0314] The gate of the twelfth transistor M12 is electrically connected with the first node PD1, the drain of the twelfth transistor M12 is electrically connected with the carry signal output terminal OC, and the source of the twelfth transistor M12 is electrically connected with the first low voltage terminal LVSS;

[0315] The gate of the thirteenth transistor M13 is electrically connected with the second node PD2, the drain of the thirteenth transistor M13 is electrically connected with the carry signal output terminal OC, and the source of the thirteenth transistor M13 is electrically connected with the first low voltage terminal LVSS;

[0316] The drive signal output circuit comprises a fourteenth transistor M14, a fifteenth transistor M15 and a sixteenth transistor M16;

[0317] The gate of the fourteenth transistor M14 is electrically connected with the first node PU, the drain of the fourteenth transistor M14 is electrically connected with the output clock signal terminal CLK, and the source of the fourteenth transistor M14 is electrically connected with the drive signal output terminal GT;

[0318] The gate of the fifteenth transistor M15 is electrically connected with the first node PD1, the drain of the fifteenth transistor M15 is electrically connected with the drive signal output terminal GT, and the source of the fifteenth transistor M15 is electrically connected with the second low voltage terminal VSS;

[0319] The gate of the sixteenth transistor M16 is electrically connected with the second node PD2, the drain of the sixteenth transistor M16 is electrically connected with the drive signal output terminal GT, and the source of the sixteenth transistor M16 is electrically connected with the second low voltage terminal VSS;

[0320] The second energy storage circuit comprises a second capacitor C2;

[0321] A first end of the second capacitor C2 is electrically connected with the first node PU, and a second end of the second capacitor C2 is electrically connected with the driving signal output end GT.

[0322] The first second node control circuit comprises a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20.

[0323] The gate of the seventeenth transistor M17 and the drain of the seventeenth transistor M17 are electrically connected with the first control voltage end VDDO, and the source of the seventeenth transistor M17 is electrically connected with the first intermediate control node PD_CN1.

[0324] The gate of the eighteenth transistor M18 is electrically connected with the first node PU, the drain of the eighteenth transistor M18 is electrically connected with the first intermediate control node PD_CN1, and the source of the eighteenth transistor M18 is electrically connected with the first low voltage end LVSS.

[0325] The gate of the nineteenth transistor M19 is electrically connected with the first intermediate control node PD_CN1, the drain of the nineteenth transistor M19 is electrically connected with the first control voltage end VDDO, and the source of the nineteenth transistor M19 is electrically connected with the first second node PD1.

[0326] The gate of the twentieth transistor M20 is electrically connected with the first node PU, the drain of the twentieth transistor M20 is electrically connected with the first second node PD1, and the source of the twentieth transistor M20 is electrically connected with the first low voltage end LVSS.

[0327] The second second node control circuit comprises a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23 and a twenty-fourth transistor M24.

[0328] The gate of the twenty-first transistor M21 and the drain of the twenty-first transistor M21 are electrically connected with the second control voltage end VDDE, and the source of the twenty-first transistor M21 is electrically connected with the second intermediate control node PD_CN2.

[0329] The gate of the twenty-second transistor M22 is electrically connected with the first node PU, the drain of the twenty-second transistor M22 is electrically connected with the second intermediate control node PD_CN2, and the source of the twenty-second transistor M22 is electrically connected with the first low voltage end LVSS.

[0330] The gate of the twenty-third transistor M23 is electrically connected with the second intermediate control node PD CN2, the drain of the twenty-third transistor M23 is electrically connected with the second control voltage terminal VDDE, and the source of the twenty-third transistor M23 is electrically connected with the second second node PD2;

[0331] The gate of the twenty-fourth transistor M24 is electrically connected with the first node PU, the drain of the twenty-fourth transistor M24 is electrically connected with the second second node PD2, and the source of the twenty-fourth transistor M24 is electrically connected with the first low voltage terminal LVSS.

[0332] The second node reset circuit includes a twenty-ninth transistor M29 and a thirtieth transistor M30.

[0333] The gate of the twenty-ninth transistor M29 is electrically connected with the input terminal I1, the drain of the twenty-ninth transistor M29 is electrically connected with the first second node PD1, and the source of the twenty-ninth transistor M29 is electrically connected with the first low voltage terminal LVSS.

[0334] The gate of the thirtieth transistor M30 is electrically connected with the input terminal I1, the drain of the thirtieth transistor M30 is electrically connected with the second second node PD2, and the source of the thirtieth transistor M30 is electrically connected with the first low voltage terminal LVSS.

[0335] In at least one embodiment of the driving circuit shown in FIG. 13, all the transistors are n-type transistors, and the first voltage terminal is a power voltage terminal.

[0336] In at least one embodiment of the driving circuit shown in FIG. 13, the node marked as NT is a voltage supply node, the source of M3 and the source of M4 are electrically connected with the voltage supply node NT, and the voltage supply node NT is electrically connected with the power voltage terminal VDD.

[0337] At least one embodiment of the present disclosure proposes a driving circuit supporting an arbitrary row display function, which can realize arbitrary row display corresponding to a matching driving signal, and has the following advantages compared with related driving circuits:

[0338] 1. Compatible with existing process, no additional circuit cost, and mass production;

[0339] 2. Better flexibility, can support single row opening in frame;

[0340] 3. Stronger reliability, the introduction of a 5T1C unit (the 5T1C unit includes M1-M5 and C1) makes the potential of the first node in the driving circuit of the non-display area not need to be high, avoids the risk of abnormal display due to leakage, and the transistor has a long service life.

[0341] In the working process of the driving module including at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure, the last frame before switching to the partial display mode is a global display frame, and each row of driving circuits included in the driving module is opened in turn.

[0342] If the display starts from the nth row of driving circuit in the partial display mode, when the input end I1 of the nth row of driving circuit is connected to the high voltage signal in the global display frame, the LSP provides the high voltage signal, at this time, M1 and M2 are opened, the input signal provided by I1 charges the control node M through M1 and M2, when the potential of the control node M rises, M3 is opened, the high voltage signal provided by VDD further charges the control node M through M3, the potential of the control node M is lifted, M4 is opened, and C1 plays a role of potential maintaining; when the input signal of the nth row of driving circuit becomes a low voltage signal, the LSP provides a low voltage signal, and due to the potential maintaining role of C1, the high potential of the control node M is maintained; when switching to the partial display mode, the frame start signal stops inputting, the signal provided by GSET is switched to a high voltage signal, M5 is opened, at this time, the high voltage signal provided by VDD charges the first node PU in the nth row of driving circuit through M4 and M5, M14 is opened, when the output clock signal end CLK connected to the nth row of driving circuit outputs a high voltage signal, the nth row of driving circuit outputs a high voltage signal through its driving signal output end, and normally cascades and opens the subsequent driving circuit, in the partial display area, M6, M14 and M11 normally open / close according to the cascade signal, to realize the partial display function starting from the nth row of driving circuit; if the next frame is still partial display starting from the nth row of driving circuit, the global display frame is not needed, and the partial display function starting from the nth row of driving circuit can be repeatedly realized by repeatedly inputting the set control signal;

[0343] In the partial display, the reset control signal provided by STV is used as a partial display stop signal, so that it can be determined which row the display stops at; when the reset control signal provided by STV is a high voltage signal, M7 is opened, the potential of PU is pulled down to a low level, M14 is closed, and the row of driving circuit is closed. In the non-local display, i.e. the display is performed in turn row by row, STV provides a frame reset signal, i.e. before the start of a frame, or between adjacent frames, the pull-up node PU is reset.

[0344] In at least one embodiment of the present disclosure, the input end of the first stage driving circuit included in the driving module can be connected to the frame start signal.

[0345] The driving module comprising the driving circuit described in at least one embodiment of the present disclosure works when starting any row display function, the first node in the driving circuit in the non-display area will not be pulled high, M14 and M11 are always in the off state, only the driving circuit in the display area can normally start cascading, and the effect of single-row display in a frame can be achieved, reaching the real meaning of any row display. In addition, with the timing adjustment of the driving signal, only the set control signal is started without the cascade signal in the non-display area being started, the refresh rate can be improved in the local display mode.

[0346] In the driving module comprising the driving circuit shown in FIG. 13 of the present disclosure, referring to FIGS. 35A and 16 simultaneously, when 12 clock signal lines (the specific number is not limited) are adopted, the first row driving circuit inputs for the seventh row driving circuit (the z+q row driving circuit is given by the z row driving circuit), and the ninth row driving circuit resets the first row driving circuit. If local display is performed from the ninth row of the jth frame, in order to charge the M point in the ninth row driving circuit of the jth frame, the scan control signal provided by the scan control end LSP in the ninth row driving circuit of the j-1th frame needs to be in phase with the input signal in the ninth row driving circuit of the j-1th frame, that is, in phase with the cascade signal provided by the cascade signal output end in the third row driving circuit of the j-1th frame (the selection of the third row is based on the cascade carry relationship, for example, the third row gives the ninth row carry in the present case, that is, the third row is obtained from the local display row-q, that is, 9-6=3), and the control node in the ninth row driving circuit of the j-1th frame is pulled high to the high potential. The jth frame is switched to the local display mode started by the ninth row driving circuit, the reset control signal provided by the STV stops input, and the set control signal provided by the GSET is used to start display. When the GSET provides a high voltage signal, the potential of the first node in the driving circuit with the high potential of the control node M will be pulled high, the M14 in the driving circuit is opened, and when the output clock signal end connected to the driving circuit provides a high voltage signal, the driving circuit can be opened and normally output the cascade signal.

[0347] The driving module comprising the driving circuit shown in FIG. 13 of the present disclosure works, M7 in all driving circuits is electrically connected with the STV, when local display is performed, for example, scanning from the ninth row driving circuit to the twentieth row driving circuit, and the twenty-first row pixel circuit does not display, after scanning the twentieth row driving circuit, the STV provides a high voltage signal to make M7 open and stop scanning.

[0348] In FIG. 14, the first clock signal line is marked as CLK1, the second clock signal line is marked as CLK2, and so on, and the twelfth clock signal line is marked as CLK12.

[0349] The 12th row of the driving circuit is electrically connected with CLK1, the 12th row of the driving circuit is electrically connected with CLK2, and the 12th row of the driving circuit is electrically connected with CLK1 in turn, the 12th row of the driving circuit is electrically connected with CLK2, and c is a positive integer.

[0350] As shown in FIG. 14, at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is in operation, the (j-1)th frame Fj-1 is a global display frame, and the jth frame Fj is a local display frame.

[0351] In the (j-1)th frame Fj-1, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10, CLK11 and CLK12 respectively provide corresponding clock signals, and the first row of the driving circuit to the twelfth row of the driving circuit sequentially outputs a high voltage signal.

[0352] In the jth frame Fj, when CLK9 first outputs a high voltage signal, the ninth row of the driving circuit outputs a high voltage signal, when CLK1 first outputs a high voltage signal, the thirteenth row of the driving circuit outputs a high voltage signal, and local display starts from the ninth row of the driving circuit.

[0353] In operation, when the ninth row of the driving circuit is reset as the first row of the driving circuit, in order to charge the control node of the ninth row of the driving circuit, the scan control signal provided by the LSP needs to be in phase with the input signal accessed by the ninth row of the driving circuit, that is, in phase with the carry signal output by the third row of the driving circuit (the third row of the driving circuit provides an input signal for the ninth row of the driving circuit), and the potential of the control node of the ninth row of the driving circuit is pulled to a high potential. In the (j+1)th frame, the local display mode starting from the ninth row is switched, the frame start signal stops inputting, and the signal provided by GSET is used to start display instead. When the signal provided by GSET is a high voltage signal, the potential of the first node in the driving circuit with a high voltage potential of the control node will be pulled high, M11 in the driving circuit will be opened, and when the output clock signal is a high voltage signal, the driving circuit can be opened and normally output the carry signal.

[0354] FIG. 15 is a simulation timing diagram of the driving module comprising at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure.

[0355] In FIG. 15, the label PU_G9 is a first node in the ninth row driving circuit, the label M_G9 is a control node in the ninth row driving circuit, the label G9 is a driving signal output end of the ninth row driving circuit, the label G10 is a driving signal output end of the tenth row driving circuit, the label G11 is a driving signal output end of the eleventh row driving circuit, the label G12 is a driving signal output end of the twelfth row driving circuit, the label G13 is a driving signal output end of the thirteenth row driving circuit, the label G14 is a driving signal output end of the fourteenth row driving circuit, the label G15 is a driving signal output end of the fifteenth row driving circuit, the label G16 is a driving signal output end of the sixteenth row driving circuit, the label G17 is a driving signal output end of the seventeenth row driving circuit, the label G18 is a driving signal output end of the eighteenth row driving circuit, and the label G19 is a driving signal output end of the nineteenth row driving circuit.

[0356] In FIG. 15, the label Fj-1 is a j-1 frame, the label Fj is a j frame, and the label Fj+1 is a j+1 frame; j is a positive integer.

[0357] The j-1 frame Fj-1 is a global display frame, the j frame Fj is a partial display frame, and the j+1 frame Fj+1 is a partial display frame.

[0358] In the j frame Fj, partial scanning is performed starting from the ninth row driving circuit.

[0359] In the j+1 frame Fj+1, only the ninth row driving circuit performs scanning.

[0360] In the j-1 frame Fj-1, each row driving circuit outputs a high voltage signal in turn.

[0361] In the j+1 frame Fj+1, after the ninth row driving circuit is turned on, the STV connected to each row driving circuit provides a high voltage signal to pull down the potential of the first node in all row driving circuits, and the clock signal provided by each clock signal line is all set to low, thereby realizing the ninth row partial display.

[0362] FIG. 16 is a working timing diagram of a driving module comprising at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure.

[0363] In FIG. 16, the label Fj is a j frame, and the label Fj+1 is a j+1 frame.

[0364] The j frame Fj and the j+1 frame Fj+1 are partial display frames.

[0365] In the jth frame Fj and the j+1th frame Fj+1, the local scanning is started from the same row driving circuit, for example, the local scanning is started from the ninth row driving circuit; before the j+1th frame Fj+1, the global refresh frame does not need to be set, and the reset control signal is repeatedly input to repeatedly realize the local display function started from the ninth row driving circuit.

[0366] As shown in FIG. 16, when the driving module comprising at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is working, the 5T1C unit (the 5T1C unit comprises M1-M5 and C1) can independently raise the potential of the first node of the corresponding row driving circuit, without the input signal from the previous driving circuit, so the driving circuit of the previous display row does not need to be opened. When the local display starts from a certain row in the middle, the frame start signal STV1 is an invalid signal, and the continuous frame local display mode is performed, the CLK1-CLK8 are skipped at the beginning of each frame, and the input directly starts from CLK9.

[0367] If the opening time of each row is 1H, there are 2160 rows, the time for global scanning in one frame is 2160H, and the refresh rate is 1 / (2160H); the time required for scanning one frame in the local scanning mode starting from the ninth row is (2160-8)H, and the refresh rate is 1 / (2152H). The fewer the number of rows displayed in the local scanning mode, the more obvious the refresh rate is provided, and the data voltage signal timing needs to be adjusted accordingly.

[0368] The difference between at least one embodiment of the driving circuit shown in FIG. 17 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is that:

[0369] The twenty-ninth transistor M29 and the thirtieth transistor M30 are not included.

[0370] In specific implementation, when the driving circuit comprises the seventh transistor M7, the reset control signal can be used as a local display stop control signal to determine the display stop row.

[0371] The difference between at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure is that:

[0372] The first second node control circuit comprises a twenty-fifth transistor M25 and a twenty-sixth transistor M26;

[0373] The gate of the twenty-fifth transistor M25 and the drain of the twenty-fifth transistor M25 are electrically connected with a first control voltage terminal VDDO, and the source of the twenty-fifth transistor M25 is electrically connected with the first second node PD1.

[0374] The gate of the twenty-sixth transistor M26 is electrically connected with the first node PU, the drain of the twenty-sixth transistor M26 is electrically connected with the first second node PD1, and the source of the twenty-sixth transistor M26 is electrically connected with the first low voltage end LVSS.

[0375] The second second node control circuit includes a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0376] The gate and the drain of the twenty-seventh transistor M27 are electrically connected with the second control voltage end VDDE, and the source of the twenty-seventh transistor M27 is electrically connected with the second second node PD2.

[0377] The gate of the twenty-eighth transistor M28 is electrically connected with the first node PU, the drain of the twenty-eighth transistor M28 is electrically connected with the second second node PD2, and the source of the twenty-eighth transistor M28 is electrically connected with the first low voltage end LVSS.

[0378] At least one embodiment of the driving circuit shown in FIG. 19 is different from at least one embodiment of the driving circuit shown in FIG. 13 in that:

[0379] The seventh transistor M7 is not included.

[0380] The twenty-ninth transistor M29 and the thirtieth transistor M30 are not included.

[0381] At least one embodiment of the driving circuit shown in FIG. 20 is different from at least one embodiment of the driving circuit shown in FIG. 13 in that it further includes a control node reset circuit.

[0382] The control node reset circuit includes a reset transistor MR.

[0383] The gate of the reset transistor MR is electrically connected with the control reset end LSTV0, the drain of the reset transistor MR is electrically connected with the control node M, and the source of the reset transistor MR is electrically connected with the first low voltage end LVSS.

[0384] In at least one embodiment of the driving circuit shown in FIG. 20, a high voltage signal is provided through LSTV0 when in operation, so that M4 is opened, and the control node M is in communication with the first low voltage end LVSS, so as to reset the potential of the control node M.

[0385] In at least one embodiment shown in FIG. 20, the second voltage end is the first low voltage end LVSS, and the first voltage end is the power voltage end VDD.

[0386] In at least one embodiment of the present disclosure, the first low voltage signal provided by the first low voltage terminal LVSS has a voltage value smaller than the second low voltage signal provided by the second low voltage terminal VSS.

[0387] In at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure, when the potential of the control node M needs to be reset, the low voltage signal needs to be provided by VDD, the high voltage signal needs to be provided by LSP, M3 and M2 are opened to lower the potential of the control node M, but abnormal output may occur due to the influence on I1. Based on this, in at least one embodiment of the driving circuit shown in FIG. 20 of the present disclosure, the reset transistor MR is used to reset the potential of the control node M, so as to avoid the risk of abnormal output of the driving circuit.

[0388] In at least one embodiment of the driving circuit shown in FIG. 20 of the present disclosure, when the potential of the control node M needs to be reset, the low voltage signal needs to be provided by VDD, the high voltage signal needs to be provided by LSP, M3 and M2 are opened to lower the potential of the control node M, but abnormal output may occur due to the influence on I1. Based on this, in at least one embodiment of the driving circuit shown in FIG. 20 of the present disclosure, the reset transistor MR is used to reset the potential of the control node M, so as to avoid the risk of abnormal output of the driving circuit.

[0389] In the starting stage P1 included in the Nth frame, as shown in FIGS. 21 and 22A, when the input end I1 of the nth level driving circuit provides a high voltage signal, LSP provides a high voltage signal, in the nth level driving circuit, M1 and M2 are opened, C1 is charged to M, the potential of the control node M is pulled up, then M3 is opened, the high voltage signal provided by VDD continues to charge M through M3, and M4 is opened.

[0390] In the first node pre-charging stage P2, as shown in FIGS. 21 and 22B, LSP provides a low voltage signal, the input end I1 of the nth level driving circuit provides a low voltage signal, M1 and M2 are closed, C1 maintains the potential of M, and M4 is kept open.

[0391] In the local display starting output stage P3 included in the N+1th frame, as shown in FIGS. 21 and 22C, STV provides a low voltage signal, GSET provides a high voltage signal, in the mth level driving circuit, M4 and M5 are opened, the first node PU is charged, the potential of PU is pulled up, CLK provides a high voltage signal, M14 in the nth level driving circuit is opened, and the driving signal output end of the nth level driving circuit provides a high voltage signal.

[0392] In the global refresh recovery stage P4 included in the N+1th frame, as shown in FIGS. 21 and 22D, LSP provides a low voltage signal, the input end I1 in the nth level driving circuit is connected to a low voltage signal, LSTV0 provides a high voltage signal, MR is opened, C1 is discharged through MR, the potential of the control node M is pulled down, M3 and M4 are closed, and the initial state is restored.

[0393] The driving circuit in at least one embodiment of the present disclosure can support single-row opening in a frame, the duty cycle of the clock signal is not compressed, and can support local high-frequency refresh display; the driving circuit in at least one embodiment of the present disclosure is more reliable, the potential of the first node in the corresponding stage driving circuit of the non-display area cannot be pulled up, the risk of abnormal display caused by leakage is avoided, and the transistor has a longer service life.

[0394] The driving circuit in at least one embodiment of the present disclosure can support single-row opening in a frame, the duty cycle of the clock signal is not compressed, and can support local high-frequency refresh display; the driving circuit in at least one embodiment of the present disclosure is more reliable, the potential of the first node in the corresponding stage driving circuit of the non-display area cannot be pulled up, the risk of abnormal display caused by leakage is avoided, and the transistor has a longer service life.

[0395] The driving circuit in at least one embodiment of the present disclosure shown in FIG. 23 is different from the driving circuit in at least one embodiment of the present disclosure shown in FIG. 20 as follows: no reset transistor MR is included;

[0396] The input control circuit includes an input control transistor MC;

[0397] The gate of the input control transistor MC is electrically connected to the power supply voltage terminal VDD, the drain of the input control transistor MC is electrically connected to the input terminal I1, and the source of the input control transistor MC is electrically connected to the input node NI;

[0398] The drain of M1 is electrically connected to the input node NI;

[0399] The second end of C1 is electrically connected to the first low-voltage terminal LVSS.

[0400] Compared with at least one embodiment of the driving circuit shown in FIG. 20 of the present disclosure, at least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure reduces the use of LSTV0, has lower requirements for circuit driving, and adjusts the connection mode of the second end of C1, avoids abnormal output of the driving circuit caused by resetting the control node M, ensures that the charge in C1 is released through LVSS and cannot flow to I1 and the corresponding stage carry signal output terminal.

[0401] When the potential of the control node M needs to be reset, the driving circuit in at least one embodiment of the present disclosure shown in FIG. 23 lowers the potential of the power supply voltage signal provided by VDD, provides a high-voltage signal by LSP, releases the charge in C1 through M2 and M3 to VDD, and closes MC, so as to ensure that the charge released by C1 cannot affect the input signal and cause abnormal display.

[0402] At least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure works as follows: when the Nth frame is a global display frame and the N+1th frame is a local display frame, at the N+1th frame, the starting stage of the local display is the 9th stage driving circuit,

[0403] At the starting stage selection stage included in the Nth frame, when the input end I1 of the 9th stage driving circuit provides a high voltage signal, the LSP provides a high voltage signal, in the 9th stage driving circuit, M1 and M2 are opened, C1 is charged, the potential of the control node M is pulled high, and then M3 is opened, the high voltage signal provided by VDD continues to charge the control node M through M3, and M4 is opened;

[0404] At the first node pre-charging stage included in the Nth frame, the LSP provides a low voltage signal, in the 9th stage driving circuit, the input end I1 provides a low voltage signal, M1 and M2 are closed, C1 maintains the potential of the control node M, and M4 is kept open;

[0405] At the local display starting output stage included in the N+1th frame, the STV provides a low voltage signal, the GSET provides a high voltage signal, in the 9th stage driving circuit, M4 and M5 are opened, the first node PU is charged, the potential of PU is pulled high, CLK provides a high voltage signal, M14 in the mth stage driving circuit is opened, and the driving signal output end of the 9th stage driving circuit provides a high voltage signal;

[0406] At the global refresh recovery stage included in the N+1th frame, the LSP provides a high voltage signal, the signal of the power voltage provided by VDD is pulled low, in the 9th stage driving circuit, the input end I1 is connected to a low voltage signal, M1 is closed and will not discharge I1 to cause abnormal output of the driving circuit, M2 and M3 are opened, the charge in C1 is discharged to VDD, so that the potential of the control node M is pulled low and the initial state is restored.

[0407] At least one embodiment of the driving circuit shown in FIG. 24 of the present disclosure is different from at least one embodiment of the driving circuit shown in FIG. 20 of the present disclosure as follows: a control voltage input circuit is further included;

[0408] The control voltage input circuit includes a first input transistor MI1, a second input transistor MI2 and a third input transistor MI3;

[0409] The gate of the first input transistor MI1 and the drain of the first input transistor MI1 are electrically connected to the first control voltage end VDDO, and the source of the first input transistor MI1 is electrically connected to the connection node NJ;

[0410] The gate of the second input transistor MI2 is electrically connected with the drain of the second input transistor MI2, and the source of the second input transistor MI2 is electrically connected with the access node NJ.

[0411] The gate of the third input transistor MI3 is electrically connected with the intermediate node NZ, the drain of the third input transistor MI3 is electrically connected with the access node NJ, and the source of the third input transistor MI3 is electrically connected with the voltage supply node NT.

[0412] The drain of M3 and the second end of C1 are electrically connected with the voltage supply node NT.

[0413] At least one embodiment of the driving circuit shown in FIG. 24 works as follows. When the Nth frame is a global display frame and the N+1th frame is a local display frame, at the N+1th frame, the starting stage of local display is the 9th stage of driving circuit,

[0414] In the starting stage selection phase included in the Nth frame, when the input end I1 of the 9th stage of driving circuit provides a high voltage signal, the LSP provides a high voltage signal, in the 9th stage of driving circuit, M1 and M2 are opened, C1 charges the control node M, and the potential of the control node M is pulled high, then M3 is opened, the high voltage signal provided by VDD continues to charge the control node M through M3, and M4 is opened.

[0415] In the first node pre-charging phase included in the Nth frame, the LSP provides a low voltage signal, in the 9th stage of driving circuit, the input end I1 provides a low voltage signal, M1 and M2 are closed, C1 maintains the potential of the control node M, and M4 is kept open.

[0416] In the local display starting output phase included in the N+1th frame, the STV provides a low voltage signal, the GSET provides a high voltage signal, in the 9th stage of driving circuit, M4 and M5 are opened, the first node PU is charged, the potential of PU is pulled high, CLK provides a high voltage signal, M14 in the mth stage of driving circuit is opened, and the driving signal output end of the 9th stage of driving circuit provides a high voltage signal.

[0417] In the global refresh recovery phase included in the N+1th frame, the LSP provides a low voltage signal, the LSTV0 provides a high voltage signal, in the 9th stage of driving circuit, I1 provides a low voltage signal, MR is opened, the charge in C1 is discharged through MR, the potential of the control node M is pulled low, and the initial state is recovered.

[0418] Taking a 4K resolution two-split screen different refresh rate application scenario as an example, as shown in FIG. 25, a first sub-display region is labeled as A1, and a second sub-display region is labeled as A2. The first sub-display region A1 corresponds to the first-stage driving circuit GA1 to the 1080th-stage driving circuit GA1080, and the second sub-display region A2 corresponds to the 1081th-stage driving circuit GA1081 to the 2160th-stage driving circuit GA2160.

[0419] The first-stage driving circuit GA1 to the 1080th-stage driving circuit GA1080 is of a first refresh rate, and the 1081th-stage driving circuit GA1081 to the 2160th-stage driving circuit GA2160 is of a second refresh rate. If the first refresh rate is less than the second refresh rate, for example, the first refresh rate is 30 Hz, and the second refresh rate is 60 Hz, then the refresh is performed at the refresh rate of 60 Hz. In the Nth frame, GA1-GA2160 is refreshed, in the N+1th frame, GA1081-GA2160 is refreshed, in the N+2th frame, GA1-GA2160 is refreshed, and in the N+3th frame, GA1081-GA2160 is refreshed. The refresh is performed in a cycle, and the lower screen is refreshed at the refresh rate of 60 Hz, and the upper screen is refreshed only once in two frames, which is equivalent to a refresh rate of 30 Hz.

[0420] It should be noted that alternatively, the first refresh rate can be greater than the second refresh rate, for example, the first refresh rate is 60 Hz, and the second refresh rate is 30 Hz. In the Nth frame, GA1-GA2160 is refreshed, in the N+1th frame, GA1-GA1081 is refreshed, in the N+2th frame, GA1-GA2160 is refreshed, and in the N+3th frame, GA1-GA1081 is refreshed. The refresh is performed in a cycle.

[0421] FIG. 26 is a timing diagram corresponding to the two-split screen different refresh rate application scenario. The first-stage driving circuit GA1 to the 1080th-stage driving circuit GA1080 is of a first refresh rate, and the 1081th-stage driving circuit GA1081 to the 2160th-stage driving circuit GA2160 is of a second refresh rate. The first refresh rate is 30 Hz, and the second refresh rate is 60 Hz.

[0422] In FIG. 26, the Nth frame is labeled as FN, the N+1th frame is labeled as FN+1, and the frame start signal is labeled as STV1. The input end of the first-stage driving circuit GA1 is connected to the frame start signal STV1.

[0423] The first clock signal line is labeled as CLK1, the second clock signal line is labeled as CLK2, the third clock signal line is labeled as CLK3, and so on, the eleventh clock signal line is labeled as CLK11, and the twelfth clock signal line is labeled as CLK12; the driving signal output end of the first stage driving circuit is labeled as GT1, the driving signal output end of the second stage driving circuit is labeled as GT2, the driving signal output end of the 1081st stage driving circuit is labeled as GT1081, and the driving signal output end of the 1082nd stage driving circuit is labeled as GT1082.

[0424] As shown in FIG. 26, the Nth frame is a global display frame, and the N+1th frame is a local display frame. In the Nth frame, when the input end of the 1081st stage driving circuit is connected to a high voltage signal, the LSP provides a high voltage signal, so that the potential of the control node in the 1081st stage driving circuit is set high to mark the 1081st stage driving circuit. In the N+1th frame, when the GSET provides a high voltage signal, the potential of the first node in the 1081st stage driving circuit is set to a high voltage, and scanning starts from the 1081st stage driving circuit.

[0425] As shown in FIG. 27, taking the 721st stage driving circuit GA721 to the 1440th stage driving circuit GA1440 for local display as an example at a 4K resolution, the display area includes a first sub-display area A1, a second sub-display area A2, and a third sub-display area A3 arranged from top to bottom;

[0426] The first sub-display area A1 corresponds to the first stage driving circuit GA1 to the 720th stage driving circuit GA720, the second sub-display area A2 corresponds to the 721st stage driving circuit GA721 to the 1440th stage driving circuit GA1440, and the third sub-display area A3 corresponds to the 1441st stage driving circuit GA1441 to the 2160th stage driving circuit GA2160.

[0427] The display refresh rate corresponding to A1 and A3 is 120Hz, and the display refresh rate corresponding to A2 is 360Hz, that is, the display refresh rate corresponding to A1 and A3 is the same and less than the display refresh rate corresponding to A2.

[0428] FIG. 28 is a timing diagram corresponding to the application scenario of FIG. 27.

[0429] In FIG. 28, the Nth frame is labeled as FN, the N+1th frame is labeled as FN+1, the frame start signal is labeled as STV1, and the input end of the first stage driving circuit GA1 is connected to the frame start signal STV1.

[0430] The first clock signal line is labeled as CLK1, the second clock signal line is labeled as CLK2, the third clock signal line is labeled as CLK3, and so on, the eleventh clock signal line is labeled as CLK11, and the twelfth clock signal line is labeled as CLK12; the driving signal output end of the first stage driving circuit is labeled as GT1, the driving signal output end of the second stage driving circuit is labeled as GT2, the driving signal output end of the 721st stage driving circuit is labeled as GT721, the driving signal output end of the 722nd stage driving circuit is labeled as GT722, and the driving signal output end of the 1440th stage driving circuit is labeled as GT1440.

[0431] As shown in FIG. 28, in the Nth frame FN, from GA1 to GA2160, when the input end in the 721st stage driving circuit is connected to a high voltage signal, the LSP provides a high voltage signal to pull the potential of the control node in the 721st stage driving circuit high;

[0432] At the beginning of the N+1th frame FN+1, the GSET provides a high voltage signal to pull the potential of the first node in the 721st stage driving circuit high, and the scanning starts from the 721st stage driving circuit and continues to the 1440th stage driving circuit. After the scanning of the 1440th stage driving circuit is completed, the STV provides a high voltage signal to reset the potential of the first node in each stage driving circuit to a low voltage, and the scanning is ended.

[0433] As shown in FIG. 29, taking a three-split screen display application scenario as an example, the three-split screen display has two different refresh rate dividing points, and the display area includes a first sub-display area A1, a second sub-display area A2 and a third sub-display area A3 arranged from top to bottom. The first sub-display area A1 corresponds to the first stage driving circuit GA1 to the 720th stage driving circuit GA720, the second sub-display area A2 corresponds to the 721st stage driving circuit GA721 to the 1440th stage driving circuit GA1440, and the third sub-display area A3 corresponds to the 1441st stage driving circuit GA1441 to the 2160th stage driving circuit GA2160.

[0434] The refresh rate of the first sub-display area A1 is 30 Hz, the refresh rate of the second sub-display area A2 is 60 Hz, and the refresh rate of the third sub-display area A3 is 120 Hz, that is, the refresh rate of the first sub-display area A1 is less than the refresh rate of the second sub-display area A2, and the refresh rate of the second sub-display area A2 is less than the refresh rate of the third sub-display area A3. Optionally, the ratio between the refresh rates of the three is an optional positive integer; the whole is refreshed at 120 Hz, in the Nth frame, GA1-GA2160 is refreshed, in the N+1th frame, GA721-GA1440 is refreshed, and during the N+1th frame refresh, the reset of the control node in the 721st driving circuit GA721 and the pre-charging of the control node in the 1440th driving circuit GA1440 need to be completed, in the N+2th frame and the N+3th frame, the 1441st driving circuit to the 2160th driving circuit is refreshed, that is, three-screen 30 Hz-60 Hz-120 Hz refresh display can be realized.

[0435] The Nth frame is a 120 Hz refresh rate, and the opening time H of each row is 3.7 μs, and the frame refresh time is 3.7*2160 μs.

[0436] In at least one embodiment of the present disclosure, when the display area includes the first sub-display area A1, the second sub-display area A2 and the third sub-display area A3 arranged in order from top to bottom, the display refresh rate corresponding to A1 and A3 can be 120 Hz, and the display refresh rate corresponding to A2 can be 360 Hz, that is, the display refresh rate of the second sub-display area A2 in the middle is three times that of the first sub-display area A1, in the Nth frame, GA1-GA2160 is refreshed, in the N+1th frame and the N+2th frame, GA721-GA1550 is refreshed; the N+3th frame operation is the same as the Nth frame operation, the N+4th frame operation is the same as the N+1th frame operation, and the N+5th frame operation is the same as the N+2th frame operation, that is, the potential of the control node M can be maintained for at least 2 frames.

[0437] FIG. 30 is a timing diagram corresponding to the Nth frame of the application scenario corresponding to FIG. 29.

[0438] As shown in FIG. 30, in the Nth frame FN, when the input end of the 721st driving circuit is connected to a high-voltage signal, the LSP provides a high-voltage signal to raise the potential of the control node in the 721st driving circuit.

[0439] FIG. 31 is a timing diagram corresponding to the N+1th frame of the application scenario corresponding to FIG. 29.

[0440] After the end of the Nth frame, the (N+1)th frame FN+1 is entered, after the first blank time period TB1 of 720H, the GSET provides a high voltage signal to pull the potential of the first node in the 721st level driving circuit high, and the refreshing of the 721st level driving circuit is started, and the signal provided by the GSET plays the role of an input signal; when the 721st level driving circuit normally cascades and outputs, the potential of the signal provided by the LSTV0 is pulled high, and the potential of the control node in the 721st level driving circuit is reset; when the input end in the 1441st level driving circuit is connected to a high voltage signal, the LSP provides a high voltage signal to pull the potential of the control node in the 1441st level driving circuit high.

[0441] FIG. 32 is a timing diagram of the (N+2)th frame and the (N+3)th frame corresponding to the application scenario of FIG. 29.

[0442] The (N+2)th frame is a 120Hz refresh rate, after the end of the (N+1)th frame, the (N+2)th frame FN+2 is entered, after the second blank time period TB2 of 1440H, the GSET provides a high voltage signal, and the potential of the first node in the 1441st level driving circuit is pulled high, and the refreshing of the 1441st level driving circuit is started;

[0443] The scanning operation of the (N+3)th frame FN+3 is the same as that of the (N+2)th frame FN+2, and the scanning operation of the (N+4)th frame is the same as that of the Nth frame, and every four frames form a cycle.

[0444] In FIG. 32, the third blank time period TB3 is indicated by a label.

[0445] In specific implementation, in the (N+1)th frame, the (N+2)th frame and the (N+3)th frame, the blank time period included in the partial refresh frame can be removed, the potential of the signal provided by the GSET can be immediately pulled high after the end of the last frame, the partial display is started, the refreshing time of each frame is unchanged, the total number of refreshing lines is reduced, the refresh rate can be improved or the charging time can be increased.

[0446] FIG. 33 is a timing diagram of the (N+2)th frame corresponding to the application scenario of FIG. 29.

[0447] As shown in FIG. 33, compared with FIG. 32, the second blank time period TB included in the (N+2)th frame FN+2 is removed, and the potential of the signal provided by the GSET is immediately pulled high when the (N+2)th frame FN+2 starts after the end of the (N+1)th frame.

[0448] In specific implementation, in the (N+2)th frame, the charging time can be controlled to be unchanged, the refreshing area of the (N+1)th frame is greater than half of the display area, and the refresh rate cannot be improved; the refresh rate of the (N+2)th frame and the (N+3)th frame can be improved to 360Hz; or,

[0449] In the N+2th frame, the charging time can be controlled to be variable, the 1H time of the N+1th frame can be increased by 1.5 times, and the 1H time of the N+2th frame and the N+3th frame can be increased to 3 times.

[0450] As shown in FIGS. 34A-34F, the display area can include a first sub-display area A1, a second sub-display area A2, and a third sub-display area A3 arranged from top to bottom; the first sub-display area A1 corresponds to the first to 720th level driving circuits, the second sub-display area A2 corresponds to the 721st to 1440th level driving circuits, and the third sub-display area A3 corresponds to the 1441st to 2160th level driving circuits;

[0451] As shown in FIG. 34A, the refresh rate of the first sub-display area A1 is 30 Hz, the refresh rate of the second sub-display area A2 is 60 Hz, and the refresh rate of the third sub-display area A3 is 120 Hz; in the Nth and N+4th frames, the first to 2160th level driving circuits are scanned, in the N+1th frame, the 721st to 2160th level driving circuits are scanned, and in the N+2th and N+3th frames, the 1441st to 2160th level driving circuits are scanned;

[0452] As shown in FIG. 34B, the refresh rate of the first sub-display area A1 is 60 Hz, the refresh rate of the second sub-display area A2 is 30 Hz, and the refresh rate of the third sub-display area A3 is 120 Hz; in the Nth and N+4th frames, the first to 2160th level driving circuits are scanned, in the N+2th frame, the first to 720th level driving circuits are scanned, and in the N+1th and N+3th frames, the 1441st to 2160th level driving circuits are scanned;

[0453] As shown in FIG. 34C, the refresh rate of the first sub-display area A1 is 120 Hz, the refresh rate of the second sub-display area A2 is 60 Hz, and the refresh rate of the third sub-display area A3 is 30 Hz; in the Nth and N+4th frames, the first to 2160th level driving circuits are scanned, in the N+2th frame, the first to 1440th level driving circuits are scanned, and in the N+1th and N+3th frames, the first to 720th level driving circuits are scanned;

[0454] As shown in FIG. 34D, the refresh rate of the first sub-display area A1 is 30 Hz, the refresh rate of the second sub-display area A2 is 120 Hz, and the refresh rate of the third sub-display area A3 is 60 Hz; in the Nth and N+4th frames, the first to 2160th level driving circuits are scanned, in the N+2th frame, the 721st to 1440th level driving circuits are scanned, and in the N+1th and N+3th frames, the 721st to 1440th level driving circuits are scanned;

[0455] As shown in FIG. 34E, the refresh rate of the first sub-display area A1 is 60 Hz, the refresh rate of the second sub-display area A2 is 120 Hz, and the refresh rate of the third sub-display area A3 is 30 Hz; in the Nth frame and the N+4th frame, the first-level driving circuit to the 2160th driving circuit are scanned, in the N+2th frame, the first-level driving circuit to the 1440th driving circuit are scanned, in the N+1th frame and the N+3th frame, the 721st driving circuit to the 1440th driving circuit are scanned;

[0456] As shown in FIG. 34F, the refresh rate of the first sub-display area A1 is 120 Hz, the refresh rate of the second sub-display area A2 is 30 Hz, and the refresh rate of the third sub-display area A3 is 60 Hz; in the Nth frame and the N+4th frame, the first-level driving circuit to the 2160th driving circuit are scanned, in the N+2th frame, the first-level driving circuit to the 720th driving circuit are scanned, and the 1441st driving circuit to the 2160th driving circuit are scanned, in the N+1th frame and the N+3th frame, the first-level driving circuit to the 720th driving circuit are scanned.

[0457] The display panel disclosed in the embodiments of the present disclosure comprises a driving module, and the driving module comprises a plurality of driving circuits as described above;

[0458] The input end of the driving circuit is electrically connected with the carry signal output end of the adjacent m-level driving circuit.

[0459] m is a positive integer.

[0460] In at least one embodiment of the present disclosure, the first row of driving circuits in the driving module, or the first few rows of driving circuits included in the driving module are connected with the frame start signal.

[0461] In at least one embodiment of the present disclosure, the display panel can comprise a display area, and the display area comprises a first sub-display area and a second sub-display area, and the refresh rates of the first sub-display area and the second sub-display area are different.

[0462] In at least one embodiment of the present disclosure, the display area can further comprise a third sub-display area.

[0463] The refresh rate of the first sub-display area, the refresh rate of the second sub-display area, and the refresh rate of the third sub-display area gradually increase.

[0464] In at least one embodiment of the present disclosure, each level of driving circuit in the driving module can be electrically connected with the reset control end STV.

[0465] As shown in FIG. 35A, in at least one embodiment of the present disclosure, at least one embodiment of the driving module includes a first-stage driving circuit GA1, a second-stage driving circuit GA2, a third-stage driving circuit GA3, a fourth-stage driving circuit GA4, and so on to a twelfth-stage driving circuit GA12;

[0466] The GA1 is electrically connected with a first clock signal line CLK1, the GA2 is electrically connected with a second clock signal line CLK2, and so on to the GA11 being electrically connected with an eleventh clock signal line CLK11, and the GA12 being electrically connected with a twelfth clock signal line CLK12;

[0467] Each stage of the driving circuit is electrically connected with the VDDO, the VDDE, the LSP, the GSET and the STV;

[0468] The input end of the GA1, the input end of the GA3 and the input end of the GA5 are connected with a first frame start signal STV1A, and the input end of the GA2, the input end of the GA4 and the input end of the GA6 are connected with a second frame start signal STV1B;

[0469] The carry signal output end of the GA1 is electrically connected with the input end of the GA7 (the z-th row driving circuit gives the z+q-th row driving circuit a carry, that is, the input end of the GAz is electrically connected with the input end of the GAz+q, and in the present case, q=6), the carry signal output end of the GA2 is electrically connected with the input end of the GA8, the carry signal output end of the GA3 is electrically connected with the input end of the GA9, the carry signal output end of the GA4 is electrically connected with the input end of the GA10, the carry signal output end of the GA5 is electrically connected with the input end of the GA11, and the carry signal output end of the GA6 is electrically connected with the input end of the GA12;

[0470] The carry output end of the GA9 is electrically connected with the pull-up reset end of the GA1, the carry output end of the GA10 is electrically connected with the pull-up reset end of the GA2 (the carry output end of the GAf is electrically connected with the pull-up reset end of the Gaf-m, and in the present case, m=8), the carry output end of the GA11 is electrically connected with the pull-up reset end of the GA3, and the carry output end of the GA12 is electrically connected with the pull-up reset end of the GA4;

[0471] The pull-up reset end of the GA5 is electrically connected with the carry signal output end OC13 of the thirteenth row driving circuit, the pull-up reset end of the GA6 is electrically connected with the carry signal output end OC14 of the fourteenth row driving circuit, the pull-up reset end of the GA7 is electrically connected with the carry signal output end OC15 of the fifteenth row driving circuit, the pull-up reset end of the GA8 is electrically connected with the carry signal output end OC16 of the sixteenth row driving circuit, the pull-up reset end of the GA9 is electrically connected with the carry signal output end OC17 of the seventeenth row driving circuit, the pull-up reset end of the GA10 is electrically connected with the carry signal output end OC18 of the eighteenth row driving circuit, the pull-up reset end of the GA11 is electrically connected with the carry signal output end OC19 of the nineteenth row driving circuit, and the pull-up reset end of the GA12 is electrically connected with the carry signal output end OC20 of the twentieth row driving circuit.

[0472] In at least one embodiment of the driving module shown in FIG. 35A, all stage driving circuits are electrically connected with the STV.

[0473] The difference between at least one embodiment of the driving module shown in FIG. 35B and at least one embodiment of the driving module shown in FIG. 35A is that each row driving circuit is not electrically connected with the STV.

[0474] In specific implementation, when the reset control signal provided by the STV is not needed to be used as the local display stop control signal, each row driving circuit can not be electrically connected with the STV.

[0475] As shown in FIG. 36, at least one embodiment of the driving module according to at least one embodiment of the present disclosure can include 8 row virtual driving circuits.

[0476] In FIG. 36, the GAm-7 is the m-7th row driving circuit, the GAm-6 is the m-6th row driving circuit, the GAm-5 is the m-5th row driving circuit, the GAm-4 is the m-4th row driving circuit, the GAm-3 is the m-3rd row driving circuit, the GAm-2 is the m-2nd row driving circuit, the GAm-1 is the m-1st row driving circuit, and the GAm is the mth row driving circuit; m is a positive integer.

[0477] The GAm-7, the GAm-6, the GAm-5, the GAm-4, the GAm-3, the GAm-2, the GAm-1 and the GAm are all virtual driving circuits.

[0478] GAm-7 is electrically connected with the first clock signal line CLK1, GAm-6 is electrically connected with the second clock signal line CLK2, GAm-5 is electrically connected with the third clock signal line CLK3, GAm-4 is electrically connected with the fourth clock signal line CLK4, GAm-3 is electrically connected with the fifth clock signal line CLK5, GAm-2 is electrically connected with the sixth clock signal line CLK6, GAm-1 is electrically connected with the seventh clock signal line CLK7, and GAm is electrically connected with the eighth clock signal line CLK8;

[0479] Each row driving circuit is electrically connected with VDDO, VDDE, LSP, GSET and STV;

[0480] The pull-up reset end of each row driving circuit is electrically connected with STV, and STV provides a pull-up reset signal for each virtual driving circuit;

[0481] OCm-7 is a carry signal output end of GAm-7, OCm-6 is a carry signal output end of GAm-6, OCm-5 is a carry signal output end of GAm-5, OCm-4 is a carry signal output end of GAm-4, OCm-3 is a carry signal output end of GAm-3, OCm-2 is a carry signal output end of GAm-2, OCm-1 is a carry signal output end of GAm-1, and OCm is a carry signal output end of GAm;

[0482] OCm-7, OCm-6, OCm-5, OCm-4, OCm-3, OCm-2, OCm-1 and OCm are respectively set on the upper level of each virtual driving circuit, and reset the eight-level driving circuit of the virtual driving circuit.

[0483] In at least one embodiment of the driving module shown in FIG. 36, all level driving circuits are electrically connected with the reset control end STV.

[0484] The driving method described in the embodiments of the present disclosure is applied to the display device described above; the display stage includes the j-1th frame and the jth frame, the j-1th frame is set before the jth frame and is adjacent to the jth frame; the j-1th frame is a global display frame, and the jth frame is a local display frame; j is a positive integer greater than 1; the driving method includes:

[0485] In the global display frame, each level driving circuit outputs a corresponding driving signal in turn; the global display frame is used to charge the control nodes of the driving circuits of the local display frame.

[0486] The driving method described in at least one embodiment of the present disclosure further includes:

[0487] When the jth frame, the n-level driving circuit starts local display, in the n-level driving stage included in the global display frame, the n-level input terminal included in the n-level driving circuit is connected to the effective voltage signal, the node control circuit in the n-level driving circuit is controlled by the scanning control signal, the communication between the n-level input terminal and the n-level intermediate node is controlled, the communication between the n-level intermediate node and the n-level control node is controlled, the communication or disconnection between the first voltage terminal and the n-level intermediate node is controlled by the potential of the n-level control node; the first energy storage circuit in the n-level driving circuit maintains the potential of the n-level first node.

[0488] In the n-level driving stage included in the local display frame, the first node charging circuit in the n-level driving circuit is controlled by the potential of the n-level control node and the set control signal, the communication between the n-level first node and the first voltage terminal is controlled; n is a positive integer.

[0489] In at least one embodiment of the present disclosure, a global display frame is provided before the local display frame, and the global display frame is adjacent to the local display frame. When the n-row driving circuit starts to display in the local display frame, when the input terminal of the n-row driving circuit is connected to the effective voltage signal, the node control circuit is controlled by the scanning control signal provided by the scanning control terminal, the communication between the input terminal and the intermediate node is controlled, the communication between the intermediate node and the control node is controlled, the control node is charged by the input signal provided by the input terminal, and the potential of the control node is raised. After the potential of the control node is raised, the node control circuit is controlled by the potential of the control node, the communication between the first voltage terminal and the intermediate node is controlled, the first voltage signal provided by the first voltage terminal further charges the control node, and the potential of the control node is raised. The first energy storage circuit maintains the potential of the control node; when the input terminal of the n-row driving circuit is connected to the invalid voltage signal, the scanning control signal provided is switched to the invalid voltage signal, and the high potential of the control node is maintained by the first energy storage circuit at this time; when the global display frame is switched to the local display frame, when the set control terminal provides an effective set control signal, the first node charging circuit is controlled by the potential of the control node and the set control signal provided by the set control terminal, the communication between the first node and the first voltage terminal is controlled, the first voltage signal provided by the first voltage terminal charges the first node in the n-row driving circuit, and when the output clock signal connected to the n-row driving circuit is an effective voltage signal, the driving signal output circuit in the n-row driving circuit is controlled by the potential of the first node, and the effective n-row driving signal is provided by the driving signal output terminal. The cascaded opening of the subsequent stage driving circuit is realized, and the local display function starting from the n-row driving circuit is realized.

[0490] In at least one embodiment of the present disclosure, the input node is electrically connected with the input terminal; the driving circuit further comprises a control node reset circuit; the j+p-1th frame is a global refresh frame; when p is greater than 2, the frame between the jth frame and the j+p-1th frame is a global display frame, or is a local display frame initiated from the n-level driving circuit, and the driving method further comprises:

[0491] In the j+p-1th frame, in the control node reset stage, the control reset terminal provides a valid control reset signal, and the control node reset circuit controls the communication between the control node and the second voltage terminal in each level of driving circuit under the control of the control reset signal; then, when scanning to the q-level driving circuit, the node control circuit in the q-level driving circuit controls the communication between the q-level input node and the q-level intermediate node, controls the communication between the q-level intermediate node and the q-level control node, and controls the communication between the q-level voltage supply node and the q-level intermediate node under the control of the potential of the q-level control node; the first energy storage circuit in the q-level driving circuit maintains the potential of the q-level first node;

[0492] p is an integer greater than 1, and q is a positive integer, q is not equal to n.

[0493] For example, when p is equal to 4, the j+3th frame is a global refresh frame, the j+1th frame is a global display frame, or is a local display frame initiated from the n-level driving circuit, the j+2th frame is a global display frame, or is a local display frame initiated from the n-level driving circuit;

[0494] At this time, in the j+3th frame, in the control node reset stage, the potential of the control node in the n-level driving circuit is reset through the control node reset circuit; when scanning to the q-level driving circuit, that is, when the input terminal in the q-level driving circuit is connected with a valid input signal, the node control circuit in the q-level driving circuit controls the high potential of the q-level control node in the q-level driving circuit through the scanning control signal, so that in the j+4th frame, scanning can be started from the q-level driving circuit under the control of the signal provided by the GSET, and the j+4th frame is a local refresh frame initiated from the q-level driving circuit.

[0495] In at least one embodiment of the present disclosure, the input node is electrically connected with the input terminal; the driving circuit further comprises a control node reset circuit; the j+p-1th frame is a local display frame initiated from the n-level driving circuit; when p is greater than 2, the frame between the jth frame and the j+p-1th frame is a local display frame initiated from the n-level driving circuit, or is a local display frame initiated from the n-level driving circuit, and the driving method further comprises:

[0496] In the j+p-1th frame, after scanning the nth stage of the driving circuit, in the control node reset stage, the control reset end provides an effective control reset signal, the control node reset circuit controls the communication between the control node and the second voltage end in each stage of the driving circuit under the control of the control reset signal, and then, when scanning to the qth stage of the driving circuit, the node control circuit in the qth stage of the driving circuit controls the communication between the qth stage of the input node and the qth stage of the intermediate node, controls the communication between the qth stage of the intermediate node and the qth stage of the control node, and controls the communication between the qth stage of the voltage supply node and the qth stage of the intermediate node under the control of the potential of the qth stage of the control node; the first energy storage circuit in the qth stage of the driving circuit maintains the potential of the qth stage of the first node;

[0497] p is a positive integer, q is a positive integer, and q is greater than n.

[0498] In specific implementation, when p is equal to 2, the j+1th frame can be a local display frame starting from the nth stage of the driving circuit, in the j+1th frame, after scanning the nth stage of the driving circuit, in the control node reset stage, the control reset end provides an effective control reset signal, the control node reset circuit controls the communication between the control node and the second voltage end in each stage of the driving circuit under the control of the control reset signal, to reset the potential of the control node in the nth stage of the driving circuit; then, when scanning to the qth stage of the driving circuit, the node control circuit in the qth stage of the driving circuit controls the communication between the qth stage of the input node and the qth stage of the intermediate node, controls the communication between the qth stage of the intermediate node and the qth stage of the control node, and controls the communication between the qth stage of the voltage supply node and the qth stage of the intermediate node under the control of the potential of the qth stage of the control node, the first energy storage circuit in the qth stage of the driving circuit maintains the potential of the qth stage of the first node, so that the potential of the control node in the qth stage of the driving circuit is high, and the j+2th frame is a local display frame starting from the qth stage of the driving circuit.

[0499] In specific implementation, when j is N, p is 2, n is equal to 721, and q is equal to 1441, the Nth frame is a global display frame, as shown in FIG. 31, in the N+1th frame FN+1, after the 721th stage of the driving circuit normally cascades, the signal provided by the LSTV0 is high in potential, to reset the potential of the control node in the 721th stage of the driving circuit; when the input end in the 1441th stage of the driving circuit is connected to a high voltage signal, the LSP provides a high voltage signal, to pull up the potential of the control node in the 1441th stage of the driving circuit;

[0500] As shown in FIG. 32, in the N+2th frame FN+2 and the N+3th frame FN+3, both are local area scanning starting from the 1441th stage of the driving circuit.

[0501] In at least one embodiment of the present disclosure, the voltage supply node is electrically connected with the first voltage terminal; the driving circuit further comprises an input control circuit; the display stage comprises the j+rth frame; the j+r-1th frame is a global refresh frame; when r is greater than 2, the frames between the jth frame and the j+r-1th frame are global display frames, or, when the j+1th frame is a local display frame initiated from the nth driving circuit, the driving method further comprises:

[0502] In the j+r-1th frame, in the control node reset stage, the first voltage terminal provides an invalid first voltage signal, the scan control terminal provides a valid scan control signal, the input control circuit in each driving circuit controls the disconnection between the input terminal and the input node in each stage under the control of the first voltage signal, the node control circuit in each driving circuit controls the communication between the intermediate node and the control node in each stage under the control of the scan control signal, and controls the communication between the voltage supply node and the intermediate node in each stage under the control of the potential of the control node; then, when scanning to the qth driving circuit, the node control circuit in the qth driving circuit controls the communication between the qth input node and the qth intermediate node, controls the communication between the qth intermediate node and the qth control node, and controls the communication between the qth voltage supply node and the qth intermediate node under the control of the potential of the qth control node under the control of the scan control signal; the first energy storage circuit in the qth driving circuit maintains the potential of the qth first node;

[0503] r is an integer greater than 1, q is a positive integer, and q is not equal to n.

[0504] For example, when r is equal to 4, the j+3th frame is a global refresh frame, the j+1th frame is a global display frame, or a local display frame initiated from the nth driving circuit, the j+2th frame is a global display frame, or a local display frame initiated from the nth driving circuit;

[0505] At this time, in the j+3th frame, in the control node resetting stage, the first voltage terminal provides an invalid first voltage signal, the scan control terminal provides a valid scan control signal, the input control circuit in each stage of the driving circuit controls the disconnection between the input terminal and the input node in each stage under the control of the first voltage signal, the node control circuit in each stage of the driving circuit controls the communication between the intermediate node and the control node in each stage under the control of the scan control signal, controls the communication between the voltage providing node and the intermediate node in each stage under the control of the potential of the control node in each stage, and resets the potential of the control node in the nth stage of the driving circuit; when scanning to the qth stage of the driving circuit, that is, when the input terminal in the qth stage of the driving circuit is connected to a valid input signal, the node control circuit in the qth stage of the driving circuit controls the high potential of the qth stage of the control node in the qth stage of the driving circuit under the control of the scan control signal, so that in the j+4th frame, scanning can be started from the qth stage of the driving circuit under the control of the signal provided by the GSET, and the j+4th frame is a local refresh frame starting from the qth stage of the driving circuit.

[0506] In at least one embodiment of the present disclosure, the input node is electrically connected to the input terminal; the driving circuit further comprises an input control circuit; the display stage comprises a j+rth frame; the j+r-1th frame is a local display frame starting from the nth stage of the driving circuit; when r is greater than 2, the frames between the jth frame and the j+r-1th frame are local display frames starting from the nth stage of the driving circuit, or when the local display frame starting from the nth stage of the driving circuit, the driving method further comprises:

[0507] In the j+r-1th frame, in the control node resetting stage, the first voltage terminal provides an invalid first voltage signal, the scan control terminal provides a valid scan control signal, the input control circuit in each stage of the driving circuit controls the disconnection between the input terminal and the input node in each stage under the control of the first voltage signal, the node control circuit in each stage of the driving circuit controls the communication between the intermediate node and the control node in each stage under the control of the scan control signal, controls the communication between the voltage providing node and the intermediate node in each stage under the control of the potential of the control node in each stage; then, when scanning to the qth stage of the driving circuit, the node control circuit in the qth stage of the driving circuit controls the communication between the qth stage of the input node and the qth stage of the intermediate node, controls the communication between the qth stage of the intermediate node and the qth stage of the control node, controls the communication between the qth stage of the voltage providing node and the qth stage of the intermediate node under the control of the potential of the qth stage of the control node; the first energy storage circuit in the qth stage of the driving circuit maintains the potential of the qth stage of the first node;

[0508] r is a positive integer, q is a positive integer, and q is greater than n.

[0509] In a specific implementation, when r is equal to 2, the (j+1)th frame can be a local display frame starting from the nth stage driving circuit, in the (j+1)th frame, after scanning the nth stage driving circuit, in the control node reset stage, the control reset end provides a valid control reset signal, and the control node reset circuit is controlled by the control reset signal to control the communication between the control node in each stage driving circuit and the second voltage end, so as to reset the potential of the control node in the nth stage driving circuit; then, when scanning to the qth stage driving circuit, the node control circuit in the qth stage driving circuit controls the high potential of the control node in the qth stage driving circuit under the control of the scanning control signal, so that the (j+2)th frame is a local display frame starting from the qth stage driving circuit.

[0510] In a specific implementation, when r is equal to 2, the (j+1)th frame can be a local display frame starting from the nth stage driving circuit, in the (j+1)th frame, after scanning the nth stage driving circuit, in the control node reset stage, the control reset end provides a valid control reset signal, and the control node reset circuit is controlled by the control reset signal to control the communication between the control node in each stage driving circuit and the second voltage end, so as to reset the potential of the control node in the nth stage driving circuit; then, when scanning to the qth stage driving circuit, the node control circuit in the qth stage driving circuit controls the high potential of the control node in the qth stage driving circuit under the control of the scanning control signal, so that the (j+2)th frame is a local display frame starting from the qth stage driving circuit.

[0511] As shown in FIG. 32, in the (N+2)th frame FN+2 and the (N+3)th frame FN+3, both are local area scanning starting from the 1441th stage driving circuit.

[0512] In at least one embodiment of the present disclosure, the nth stage driving circuit is cascaded with the n-kth stage driving circuit, and the timing of the scanning control end of the nth stage driving circuit is the same as the timing of the output clock signal input into the n-kth stage driving circuit.

[0513] k is a positive integer.

[0514] In at least one embodiment of the present disclosure, the input node is electrically connected with the input end; the driving circuit further comprises a reset circuit; and the driving method further comprises:

[0515] In the ath stage driving stage included in the local display frame, the reset circuit in the ath driving circuit in the display device is controlled by the reset control signal to control the communication between the ath first node and the second voltage end.

[0516] a is a positive integer, and a is greater than n.

[0517] In a specific implementation, in the a-th driving circuit, when the reset control signal is a valid voltage signal, the reset circuit controls the communication between the first node and the second voltage terminal V2 under the control of the reset control signal provided at the reset control terminal, so as to reset the potential of the first node, so that the a-th driving circuit outputs an invalid driving signal, and the corresponding row driving circuit is closed, so that it can be determined which row the display stops at, and the reset control signal is used as a local display stop control signal.

[0518] In at least one embodiment of the present disclosure, the display stage further includes a j+1-th frame, which is arranged after the j-th frame and immediately adjacent to the j-th frame; the j+1-th frame is a local display frame.

[0519] The driving method includes:

[0520] In the n-th level driving stage included in the j+1-th frame, the set control terminal provides a valid set control signal, and the first node charging circuit in the n-th driving circuit controls the communication between the n-th first node and the first voltage terminal under the control of the potential of the n-th control node and the set control signal; n is a positive integer.

[0521] In a specific implementation, when the j-th frame and the immediately subsequent j+1-th frame are still local display frames starting from the n-th row, a global display frame is not needed, and the set control signal can be repeatedly input to repeatedly implement the local display function starting from the n-th row.

[0522] In at least one embodiment of the present disclosure, when the s-th frame and the s+1-th frame are both local display frames, and the termination level driving circuit of the local display in the s-th frame is the v-th driving circuit, the driving method includes:

[0523] In the s-th frame, after scanning the v-th driving circuit, the s+1-th frame is entered; at the beginning of the s+1-th frame, the set control terminal provides a valid set control signal; s and v are positive integers.

[0524] In a specific implementation, in the s-th frame, after scanning the termination level driving circuit, the s+1-th frame is directly entered, the corresponding blank time period is removed, the total refresh time per frame does not change, and the total number of refresh rows is reduced, so that the refresh rate can be improved or the charging time can be increased.

[0525] As shown in FIG. 33, compared with FIG. 32, the second blank time period TB included in the N+2-th frame FN+2 is removed, and the potential of the signal provided by the GSET is immediately set high at the beginning of the N+2-th frame FN+2 after the end of the N+1-th frame.

[0526] In at least one embodiment of the present disclosure, the display panel comprises a display area, the display area comprises a first sub-display area, a second sub-display area and a third sub-display area; the refresh rate of the first sub-display area, the refresh rate of the second sub-display area and the refresh rate of the third sub-display area gradually increase; the u-th frame is a global display frame, the u+1-th frame and the u+2-th frame are local display frames; u is a positive integer; the driving method comprises:

[0527] In the u-th frame, the starting stage driving circuit corresponding to the second sub-display area is positioned;

[0528] In the u+1-th frame, the starting stage driving circuit corresponding to the third sub-display area is positioned;

[0529] In the u+1-th frame, the driving circuit corresponding to the second sub-display area and the third sub-display area is scanned, and in the u+2-th frame, the driving circuit corresponding to the third sub-display area is scanned.

[0530] In specific implementation, three-part screen display can be performed, in the u-th frame, global display is performed, the starting stage driving circuit corresponding to the second sub-display area is positioned; in the u+1-th frame, the driving circuit corresponding to the second sub-display area and the third sub-display area is scanned, the starting stage driving circuit corresponding to the third sub-display area is positioned; in the u+2-th frame, the driving circuit corresponding to the third sub-display area is scanned.

[0531] The above is the preferred embodiment of the present disclosure, it should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A driving circuit, comprising a node control circuit, a first node charging circuit, a first energy storage circuit, and an input circuit; The node control circuit is electrically connected to the scan control terminal, the input node, the intermediate node, the voltage supply node, and the control node, respectively. It is used to control the connection or disconnection between the input node and the intermediate node under the control of the scan control signal provided by the scan control terminal, control the connection or disconnection between the intermediate node and the control node, and control the connection or disconnection between the voltage supply node and the intermediate node under the control of the potential of the control node. The first node charging circuit is electrically connected to the control node, the set control terminal, the first node and the voltage supply node respectively, and is used to control the connection or disconnection between the first node and the voltage supply node under the control of the potential of the control node and the set control signal provided by the set control terminal; The first energy storage circuit is electrically connected to the control node; The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node under the control of the input signal provided by the input terminal.

2. The driving circuit as described in claim 1, wherein, The input node is electrically connected to the input terminal; the driving circuit also includes a control node reset circuit. The control node reset circuit is electrically connected to the control reset terminal, the control node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the control node and the second voltage terminal under the control of the control reset signal provided by the control reset terminal.

3. The driving circuit as described in claim 1, wherein, The voltage supply node is electrically connected to the first voltage terminal; the driving circuit also includes an input control circuit. The input control circuit is electrically connected to the first voltage terminal, the input terminal, and the input node, respectively, and is used to control the connection or disconnection between the input terminal and the input node under the control of the first voltage signal provided by the first voltage terminal.

4. The driving circuit as described in claim 2, wherein, The voltage supply node is electrically connected to the first voltage terminal.

5. The driving circuit as described in claim 2, wherein, It also includes a control voltage input circuit; The control voltage input circuit is electrically connected to the first control voltage terminal, the second control voltage terminal, the access node, the intermediate node, and the voltage supply node, respectively. It is used to control the connection or disconnection between the first control voltage terminal and the access node under the control of the first control voltage provided by the first control voltage terminal, to control the connection or disconnection between the second control voltage terminal and the access node under the control of the second control voltage provided by the second control voltage terminal, and to control the connection or disconnection between the access node and the voltage supply node under the control of the potential of the intermediate node.

6. The driving circuit as described in claim 1, wherein, The node control circuit includes a first transistor, a second transistor, and a third transistor; The gate of the first transistor is electrically connected to the scan control terminal, the first electrode of the first transistor is electrically connected to the input node, and the second electrode of the first transistor is electrically connected to the intermediate node. The gate of the second transistor is electrically connected to the scan control terminal, the first terminal of the second transistor is electrically connected to the intermediate node, and the second terminal of the second transistor is electrically connected to the control node. The gate of the third transistor is electrically connected to the control node, the first terminal of the third transistor is electrically connected to the voltage supply node, and the second terminal of the third transistor is electrically connected to the intermediate node. The first node charging circuit includes a fourth transistor and a fifth transistor, and the first energy storage circuit includes a first capacitor; The gate of the fourth transistor is electrically connected to the control node, the first terminal of the fourth transistor is electrically connected to the voltage supply node, and the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor. The gate of the fifth transistor is electrically connected to the set control terminal, and the second terminal of the fifth transistor is electrically connected to the first node; The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the voltage supply node. The input circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the first terminal of the sixth transistor and the input terminal, and the second terminal of the sixth transistor is electrically connected to the first node.

7. The driving circuit as described in claim 2, wherein, The control node reset circuit includes a reset transistor; The gate of the reset transistor is electrically connected to the control reset terminal, the first terminal of the reset transistor is electrically connected to the control node, and the second terminal of the reset transistor is electrically connected to the second voltage terminal.

8. The driving circuit as described in claim 3, wherein, The input control circuit includes an input control transistor; The gate of the input control transistor is electrically connected to the first voltage terminal, the first electrode of the input control transistor is electrically connected to the input terminal, and the second electrode of the input control transistor is electrically connected to the input node.

9. The driving circuit as described in claim 5, wherein, The control voltage input circuit includes a first input transistor, a second input transistor, and a third input transistor; The gate and the first terminal of the first input transistor are both electrically connected to the first control voltage terminal, and the second terminal of the first input transistor is electrically connected to the access node. The gate and the first terminal of the second input transistor are both electrically connected to the second control voltage terminal, and the second terminal of the second input transistor is electrically connected to the access node. The gate of the third input transistor is electrically connected to the intermediate node, the first terminal of the third input transistor is electrically connected to the access node, and the second terminal of the third input transistor is electrically connected to the voltage supply node.

10. The driving circuit according to any one of claims 1 to 9, wherein, It also includes a reset circuit; The reset circuit is electrically connected to the reset control terminal, the first node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second voltage terminal under the control of the reset control signal provided by the reset control terminal.

11. The driving circuit as claimed in claim 10, wherein, It also includes a first node reset circuit, a pull-up node control circuit, a carry signal output circuit, a drive signal output circuit, and a second energy storage circuit; The first node reset circuit is electrically connected to the pull-up reset terminal, the first node and the second voltage terminal respectively, and is used to control the connection or disconnection between the first node and the second voltage terminal under the control of the pull-up reset signal provided by the pull-up reset terminal; The pull-up node control circuit is electrically connected to the first second node, the second second node, the first node, and the second voltage terminal, respectively, and is used to control the first node and the second voltage terminal to be connected or disconnected under the control of the potential of the first second node, and to control the first node and the second voltage terminal to be connected or disconnected under the control of the potential of the second second node. The carry signal output circuit is electrically connected to the first node, the first second node, the second second node, the carry signal output terminal, the output clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the carry signal output terminal and the output clock signal terminal under the control of the potential of the first node, to control the connection or disconnection between the carry signal output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the carry signal output terminal and the second voltage terminal under the control of the potential of the second second node. The drive signal output circuit is electrically connected to the first node, the first second node, the second second node, the drive signal output terminal, the output clock signal terminal, and the third voltage terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the first node, to control the connection or disconnection between the drive signal output terminal and the third voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the drive signal output terminal and the third voltage terminal under the control of the potential of the second second node. The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the drive signal output terminal. The second energy storage circuit is used to store electrical energy.

12. The driving circuit as claimed in claim 10, wherein, It also includes the first second node control circuit and the second second node control circuit; The first second node control circuit is electrically connected to a first control voltage terminal, a first intermediate control node, a first node, a first second node, and a second voltage terminal, respectively. It is used to control the potential of the first intermediate control node under the control of the first control voltage provided by the first control voltage terminal; to control the connection or disconnection between the first intermediate control node and the second voltage terminal under the control of the potential of the first node; to control the connection or disconnection between the first control voltage terminal and the first second node under the control of the potential of the first intermediate control node; and to control the connection or disconnection between the first second node and the second voltage terminal under the control of the potential of the first node. Similarly, the second second node control circuit is electrically connected to a second control voltage terminal, a second intermediate control node, a first node, a second second node, and a second voltage terminal, respectively. It is used to control the potential of the second intermediate control node under the control of the second control voltage provided by the second control voltage terminal; to control the connection or disconnection between the second intermediate control node and the second voltage terminal under the control of the potential of the first node; to control the connection or disconnection between the second control voltage terminal and the second second node under the control of the potential of the second intermediate control node; and to control the connection or disconnection between the second second node and the second voltage terminal under the control of the potential of the first node. Alternatively... The first second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the second voltage terminal, respectively. It is used to control the potential of the first second node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the second voltage terminal under the control of the potential of the first node. The second second node control circuit is electrically connected to the second control voltage terminal, the first node, the second second node, and the second voltage terminal, respectively. It is used to control the potential of the second second node under the control of the second control voltage provided by the second control voltage terminal, and to control the connection or disconnection between the second second node and the second voltage terminal under the control of the potential of the first node.

13. The driving circuit as described in claim 12, wherein, It also includes a second node reset circuit; The second node reset circuit is electrically connected to the input terminal, the first second node, the second second node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the first second node and the second voltage terminal under the control of the input signal provided by the input terminal, and to control the connection or disconnection between the second second node and the second voltage terminal.

14. The driving circuit as claimed in claim 10, wherein, The reset circuit includes a seventh transistor; The gate of the seventh transistor is electrically connected to the reset control terminal, the first terminal of the seventh transistor is electrically connected to the first node, and the second terminal of the seventh transistor is electrically connected to the second voltage terminal.

15. The driving circuit as claimed in claim 11, wherein, The first node reset circuit includes an eighth transistor, and the pull-up node control circuit includes a ninth transistor and a tenth transistor; The gate of the eighth transistor is electrically connected to the pull-up reset terminal, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal. The gate of the ninth transistor is electrically connected to the first second node, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second voltage terminal. The gate of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the first node, and the second terminal of the tenth transistor is electrically connected to the second voltage terminal. The carry signal output circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The gate of the eleventh transistor is electrically connected to the first node, the first terminal of the eleventh transistor is electrically connected to the output clock signal terminal, and the second terminal of the eleventh transistor is electrically connected to the carry signal output terminal. The gate of the twelfth transistor is electrically connected to the first second node, the first terminal of the twelfth transistor is electrically connected to the carry signal output terminal, and the second terminal of the twelfth transistor is electrically connected to the second voltage terminal. The gate of the thirteenth transistor is electrically connected to the second second node, the first terminal of the thirteenth transistor is electrically connected to the carry signal output terminal, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal. The drive signal output circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; The gate of the fourteenth transistor is electrically connected to the first node, the first terminal of the fourteenth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the drive signal output terminal. The gate of the fifteenth transistor is electrically connected to the first second node, the first terminal of the fifteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the fifteenth transistor is electrically connected to the third voltage terminal. The gate of the sixteenth transistor is electrically connected to the second second node, the first terminal of the sixteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the sixteenth transistor is electrically connected to the third voltage terminal. The second energy storage circuit includes a second capacitor; The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the drive signal output terminal.

16. The driving circuit as claimed in claim 12, wherein, The first second node control circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; the second second node control circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, and a twenty-fourth transistor; the gate and first terminal of the seventeenth transistor are electrically connected to the first control voltage terminal, and the second terminal of the seventeenth transistor is electrically connected to the first intermediate control node; the gate of the eighteenth transistor is electrically connected to the first node, the first terminal of the eighteenth transistor is electrically connected to the first intermediate control node, and the second terminal of the eighteenth transistor is electrically connected to the second voltage terminal; the gate of the nineteenth transistor is electrically connected to the first intermediate control node, the first terminal of the nineteenth transistor is electrically connected to the first control voltage terminal, and the second terminal of the nineteenth transistor is electrically connected to the first second node; the gate of the twentieth transistor is electrically connected to the first node, and the first terminal of the twentieth transistor is electrically connected to the first control voltage terminal. The twentieth transistor is electrically connected to the first second node, and its second terminal is electrically connected to the second voltage terminal; the gate and first terminal of the twentieth transistor are electrically connected to the second control voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the second intermediate control node; the gate of the twentieth transistor is electrically connected to the first node, its first terminal is electrically connected to the second intermediate control node, and its second terminal is electrically connected to the second voltage terminal; the gate of the twentieth transistor is electrically connected to the second intermediate control node, its first terminal is electrically connected to the second control voltage terminal, and the second terminal of the twentieth transistor is electrically connected to the second second node; the gate of the twentieth transistor is electrically connected to the first node, its first terminal is electrically connected to the second second node, and its second terminal is electrically connected to the second voltage terminal; or... The first second node control circuit includes a twenty-fifth transistor and a twenty-sixth transistor; the second second node control circuit includes a twenty-seventh transistor and a twenty-eighth transistor; the gate and first terminal of the twenty-fifth transistor are both electrically connected to a first control voltage terminal, and the second terminal of the twenty-fifth transistor is electrically connected to the first second node; the gate of the twenty-sixth transistor is electrically connected to the first node, the first terminal of the twenty-sixth transistor is electrically connected to the first second node, and the second terminal of the twenty-sixth transistor is electrically connected to a second voltage terminal; the gate and first terminal of the twenty-seventh transistor are both electrically connected to a second control voltage terminal, and the second terminal of the twenty-seventh transistor is electrically connected to the second second node; the gate of the twenty-eighth transistor is electrically connected to the first node, the first terminal of the twenty-eighth transistor is electrically connected to the second second node, and the second terminal of the twenty-eighth transistor is electrically connected to the second voltage terminal.

17. The driving circuit as claimed in claim 13, wherein, The second node reset circuit includes the twenty-ninth transistor and the thirtieth transistor; The gate of the 29th transistor is electrically connected to the input terminal, the first terminal of the 29th transistor is electrically connected to the first second node, and the second terminal of the 29th transistor is electrically connected to the second voltage terminal. The gate of the thirtieth transistor is electrically connected to the input terminal, the first terminal of the thirtieth transistor is electrically connected to the second second node, and the second terminal of the thirtieth transistor is electrically connected to the second voltage terminal.

18. A display panel, comprising a driving module, the driving module comprising multiple levels of driving circuitry as described in any one of claims 1 to 17; The input terminal of the driving circuit is electrically connected to the carry signal output terminal of the adjacent upper m-level driving circuit. m is a positive integer.

19. The display panel as claimed in claim 18, wherein, The display panel includes a display area, which includes a first sub-display area and a second sub-display area. The first sub-display area and the second sub-display area have different refresh rates.

20. The display panel as claimed in claim 19, wherein, The display area also includes a third sub-display area; The refresh rates of the first, second, and third sub-display areas gradually increase.

21. A driving method applied to a display panel as described in any one of claims 18 to 20; the display stage includes a (j-1)th frame and a jth frame, the (j-1)th frame being positioned before and adjacent to the jth frame; the (j-1)th frame being a global display frame, and the jth frame being a local display frame; j being a positive integer greater than 1; the driving method comprising: In the global display frame, each level of the driving circuit outputs the corresponding driving signal in sequence; The global display frame is used to charge the control node of the driving circuit of the local display frame.

22. The driving method as described in claim 21, wherein, Also includes: When the nth-level driving circuit starts local display in frame j, during the nth-level driving stage included in the global display frame, an effective voltage signal is connected to the nth-level input terminal of the nth-level driving circuit in the display device. Under the control of the scanning control signal, the node control circuit in the nth-level driving circuit controls the connection between the nth-level input node and the nth-level intermediate node, and controls the connection between the nth-level intermediate node and the nth-level control node. Under the control of the potential of the nth-level control node, the first voltage terminal is controlled to connect or disconnect from the nth-level intermediate node. The first energy storage circuit in the nth-level driving circuit maintains the potential of the first node of the nth level. In the nth driving stage of the partial display frame, the set control terminal provides an effective set control signal. Under the control of the potential of the nth control node and the set control signal, the first node charging circuit in the nth driving circuit controls the connection between the nth first node and the nth voltage providing node; n is a positive integer.

23. The driving method as described in claim 22, wherein, The input node is electrically connected to the input terminal; the driving circuit further includes a control node reset circuit; the (j+p-1)th frame is a global refresh frame; when p is greater than 2, the frames between the jth frame and the (j+p-1)th frame are global display frames, or, when they are local display frames started from the nth level driving circuit, the driving method further includes: In frame j+p-1, during the control node reset phase, the control reset terminal provides a valid control reset signal. Under the control of the control reset signal, the control node reset circuit controls the connection between the control nodes and the second voltage terminal in each stage of the drive circuit. Subsequently, when scanning to the q-th stage drive circuit, the node control circuit in the q-th stage drive circuit, under the control of the scan control signal, controls the connection between the q-th stage input node and the q-th stage intermediate node, controls the connection between the q-th stage intermediate node and the q-th stage control node, and controls the connection between the q-th stage voltage supply node and the q-th stage intermediate node under the control of the potential of the q-th stage control node. The first energy storage circuit in the q-th stage drive circuit maintains the potential of the first node of the q-th stage. p is an integer greater than 1, q is a positive integer, and q is not equal to n.

24. The driving method as described in claim 22, wherein, The input node is electrically connected to the input terminal; the driving circuit further includes a control node reset circuit; the j+p-1th frame is a local display frame started from the nth level driving circuit; when p is greater than 2, the frame between the jth frame and the j+p-1th frame is a local display frame started from the nth level driving circuit, or, when it is a local display frame started from the nth level driving circuit, the driving method further includes: In frame j+p-1, after scanning the nth stage drive circuit, during the control node reset phase, the control reset terminal provides a valid control reset signal. Under the control of the control reset signal, the control node reset circuit controls the connection between the control nodes and the second voltage terminal in each stage drive circuit. Then, when scanning to the qth stage drive circuit, the node control circuit in the qth stage drive circuit, under the control of the scan control signal, controls the connection between the qth stage input node and the qth stage intermediate node, and controls the connection between the qth stage intermediate node and the qth stage control node. Under the control of the potential of the qth stage control node, it controls the connection between the qth stage voltage supply node and the qth stage intermediate node. The first energy storage circuit in the qth stage drive circuit maintains the potential of the qth stage first node. p is a positive integer, q is a positive integer, and q is greater than n.

25. The driving method as described in claim 22, wherein, The voltage supply node is electrically connected to the first voltage terminal; the driving circuit further includes an input control circuit; the display stage includes the (j+r)th frame; the (j+r-1)th frame is a global refresh frame; when r is greater than 2, the frames between the jth frame and the (j+r-1)th frame are global display frames, or, when they are local display frames started from the nth level driving circuit, the driving method further includes: In frame j+r-1, during the control node reset phase, the first voltage terminal provides an invalid first voltage signal, while the scan control terminal provides a valid scan control signal. Under the control of the first voltage signal, the input control circuits in each stage of the drive circuit disconnect the input terminals and input nodes at each stage. Under the control of the scan control signal, the node control circuits in each stage of the drive circuit connect the intermediate nodes and control nodes at each stage. Under the control of the potential of the control nodes at each stage, they connect the voltage supply nodes and intermediate nodes at each stage. Subsequently, when scanning to the q-th stage drive circuit, the node control circuit in the q-th stage drive circuit connects the q-th stage input node and the q-th stage intermediate node under the control of the scan control signal, connects the q-th stage intermediate node and the q-th stage control node, and connects the q-th stage voltage supply node and the q-th stage intermediate node under the control of the potential of the control node at the q-th stage. The first energy storage circuit in the q-th stage drive circuit maintains the potential of the first node at the q-th stage. r is an integer greater than 1, q is a positive integer, and q is not equal to n.

26. The driving method as described in claim 22, wherein, The input node is electrically connected to the input terminal; the driving circuit further includes an input control circuit; the display stage includes the (j+r)th frame; the (j+r-1)th frame is a local display frame started from the nth level driving circuit; when r is greater than 2, the frame between the jth frame and the (j+r-1)th frame is a local display frame started from the nth level driving circuit, or, when it is a local display frame started from the nth level driving circuit, the driving method further includes: In frame j+r-1, during the control node reset phase, the first voltage terminal provides an invalid first voltage signal, while the scan control terminal provides a valid scan control signal. Under the control of the first voltage signal, the input control circuits in each stage of the drive circuit disconnect the input terminals and input nodes at each stage. Under the control of the scan control signal, the node control circuits in each stage of the drive circuit connect the intermediate nodes and control nodes at each stage. Under the control of the potential of the control nodes at each stage, they connect the voltage supply nodes and intermediate nodes at each stage. Subsequently, when scanning to the q-th stage drive circuit, the node control circuit in the q-th stage drive circuit connects the q-th stage input node and the q-th stage intermediate node under the control of the scan control signal, connects the q-th stage intermediate node and the q-th stage control node, and connects the q-th stage voltage supply node and the q-th stage intermediate node under the control of the potential of the control node at the q-th stage. The first energy storage circuit in the q-th stage drive circuit maintains the potential of the first node at the q-th stage. r is a positive integer, q is a positive integer, and q is greater than n.

27. The driving method as described in claim 22, wherein, The nth stage driver circuit is cascaded with the nkth stage driver circuit. The timing of the scan control signal connected to the nth stage driver circuit is the same as the timing of the output clock signal connected to the nkth stage driver circuit. k is a positive integer.

28. The driving method as described in claim 22, wherein, The input node is electrically connected to the input terminal; the driving circuit further includes a reset circuit; the driving method further includes: During the a-level driving stage included in the partial display frame, the reset circuit in the a-level driving circuit of the display device controls the connection between the first node of the a-level and the second voltage terminal under the control of the reset control signal; a is a positive integer, and a is greater than n.

29. The driving method as described in claim 22, wherein, When both frame s and frame s+1 are partial display frames, and in frame s, the termination level driving circuit for the partial display is the v-th level driving circuit, the driving method includes: In frame s, after scanning the v-th stage drive circuit, the system enters frame s+1; at the beginning of frame s+1, the set control terminal provides a valid set control signal. s and v are positive integers.

30. The driving method as described in claim 22, wherein, The display panel includes a display area, which includes a first sub-display area, a second sub-display area, and a third sub-display area; the refresh rates of the first sub-display area, the second sub-display area, and the third sub-display area gradually increase; the u-th frame is a global display frame, and the (u+1)-th and (u+2)-th frames are local display frames; u is a positive integer; the driving method includes: In the u-th frame, the starting stage driving circuit corresponding to the second sub-display area is located; In frame u+1, the starting stage driving circuit corresponding to the third sub-display area is located; In frame u+1, the driving circuits corresponding to the second and third sub-display areas are scanned, and in frame u+2, the driving circuit corresponding to the third sub-display area is scanned.

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