Distributed ring-based interconnect for register accessibility in a system-on-chip

Abstract

A data communication interconnect or network in a system-on-chip (SoC) may include one or more routers (102), each coupled to one or more register rings (106A, 106B). A router (102) may receive (136) transaction request packets from an initiator (104) and provide (144) transaction response packets to the initiator (104). Each register ring (106A, 106B) may have an input end (130) and an output end (128), providing a unidirectional data communication path for the request and response packets. Each register ring (106A, 106B) may have one or more nodes (108A-N), each having one or more registers that may be the targets of write and read transactions associated with the request packets. The input and output ends of register rings may be coupled to ring interfaces (124, 126) of the router (102), which may provide paths for request packets and response packets.

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