Semiconductor package, semiconductor device, and method for manufacturing semiconductor package
The semiconductor package design addresses the challenge of miniaturization and heat dissipation by overlapping connectors within the cavity region, using through holes and metal plates, resulting in a compact and efficient semiconductor package with improved heat management.
WO2026018560A1PCT designated stage Publication Date: 2026-01-22SONY SEMICON SOLUTIONS CORP
Patent Information
- Application Number
- PCT/JP2025/018662
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-07-17
- Filing Date
- 2025-05-23
- Publication Date
- 2026-01-22
Smart Images
Figure JP2025018662_22012026_PF_FP_ABST
Abstract
The present invention provides a semiconductor package having a cavity, wherein reduction in size of the semiconductor package is achieved. The semiconductor package includes a substrate, glass, a semiconductor chip, a plurality of connectors, and a connection part. The glass seals the cavity between the glass and the surface of the substrate. The semiconductor chip is disposed in the cavity. The plurality of connectors are arranged so as to at least partially overlap a region of the cavity on the back surface opposite to the surface of the substrate. The connection part connects the plurality of connectors.
Need to check novelty before this filing date? Find Prior Art
Citation Information
Patent Citations
Lead frame
JP1993036848U
Lead frame
JP1994132463A
Semiconductor device
JP1996186202A
IC socket
JP2003151706A
Semiconductor device and manufacturing method of the same
JP2013033774A