Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a driving circuit layer (102), a second electrode adapter layer (13), a pixel definition layer (PDL), a light-emitting structure layer (40) and a second electrode layer (42), which are arranged in sequence on one side of a base (101), wherein the second electrode adapter layer (13) comprises a plurality of second electrode adapter structures (131); the light-emitting structure layer (40) comprises a plurality of light-emitting structures (41); the second electrode layer (42) comprises a plurality of second electrodes (420); a first opening (K21) is provided in the second electrode adapter structure (131); a first groove (W1) is provided in a side wall of the first opening (K21); the light-emitting structure layer (40) and the second electrode layer (42) are disconnected at the first groove (W1); and the second electrode (420) is electrically connected to a corresponding second electrode signal line (1021) in the driving circuit layer (102) by means of the corresponding second electrode adapter structure (131).

Description

Display substrate and its preparation method, display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and its preparation method, and a display device. Background Technology

[0002] Micro-OLEDs (Micro-Organic Light-Emitting Diodes) are microdisplays that have emerged in recent years, with silicon-based OLEDs being one type. Silicon-based OLEDs not only enable active pixel addressing but also allow for the fabrication of pixel driving circuits and other structures on silicon substrates, which helps reduce system size and achieve lightweight design. Silicon-based OLEDs are fabricated using mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology, offering advantages such as small size, high resolution (Pixels Per Inch, PPI), and high refresh rate. They are widely used in near-eye displays for Virtual Reality (VR) and Augmented Reality (AR).

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, including a substrate and a driving circuit layer, a second electrode transition layer, a pixel definition layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds one-to-one with at least one light-emitting structure and at least one second electrode, and at least a portion of the light-emitting structure and the second electrode is located in the corresponding pixel opening;

[0006] The driving circuit layer includes multiple second electrode signal lines, and the second electrode transition layer includes multiple second electrode transition structures. Each second electrode transition structure corresponds one-to-one with at least one second electrode signal line and at least one second electrode. The second electrode is electrically connected to the corresponding second electrode transition structure, and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure.

[0007] At least one second electrode adapter structure is provided with a first opening, and at least one first opening corresponds one-to-one with at least one pixel opening. The orthographic projection of the first opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the first opening is provided with a first groove. The light-emitting structure layer is disconnected at the first groove position to form a corresponding light-emitting structure. The second electrode layer is electrically connected to the corresponding second electrode adapter structure at the first groove position.

[0008] In an exemplary embodiment, the second electrode layer is connected to the corresponding second electrode transition structure at the disconnected position.

[0009] In an exemplary embodiment, the display substrate further includes a partition structure layer, which is located between the pixel definition layer and the light-emitting structure layer in a direction perpendicular to the plane of the substrate.

[0010] The partition structure layer is provided with a plurality of second openings, at least one of which corresponds to at least one pixel opening. The orthographic projection of the second opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the second opening is provided with a second groove. The light-emitting structure layer and the second electrode layer are disconnected at the position of the second groove.

[0011] The second electrode layer is broken at the second groove position to form a corresponding second electrode, or the second electrode layer is broken at the first groove position to form a corresponding second electrode.

[0012] In an exemplary embodiment, the orthographic projection of the first opening on the substrate is located within the range of the orthographic projection of the corresponding pixel opening on the substrate, and the orthographic projection of the pixel opening on the substrate is located within the range of the orthographic projection of the corresponding second opening on the substrate.

[0013] In an exemplary embodiment, the display substrate further includes an anode layer. In a direction perpendicular to the plane of the display substrate, the anode layer is located between the driving circuit layer and the second electrode transition layer. The anode layer includes a plurality of anodes, and at least one anode corresponds one-to-one with at least one pixel opening and at least one second electrode transition structure. The second electrode transition structure includes a first insulator structure and a second electrode transition substructure sequentially disposed on the side of the anode layer away from the substrate. The second electrode is overlapped and connected to the corresponding second electrode transition substructure.

[0014] In the anode and second electrode transition structure corresponding to the same pixel opening, the first insulator structure is configured to insulate the second electrode transition structure from the anode, and the overlapping area of ​​the first insulator structure and the anode projected onto the substrate covers the overlapping area of ​​the second electrode transition structure and the anode projected onto the substrate.

[0015] In an exemplary embodiment, the second electrode transition structure further includes a second insulator structure, which is located between the second electrode transition substructure and the pixel definition layer in a direction perpendicular to the plane of the display substrate.

[0016] In the second electrode adapter structure, the first groove is formed on the side of the first insulator structure away from the substrate, the sidewall of the second electrode adapter structure, and the side of the second insulator structure near the substrate.

[0017] In an exemplary embodiment, in the second electrode adapter structure, on the side near the first opening, a portion of the surface of the first insulator structure away from the substrate, the sidewall of the second electrode adapter structure, and a portion of the surface of the pixel definition layer near the substrate form the first groove.

[0018] In the anode and second electrode transition structure corresponding to the same pixel opening, the overlapping area of ​​the pixel definition layer corresponding to the pixel opening and the orthographic projection of the anode on the substrate covers the overlapping area of ​​the second electrode transition substructure and the orthographic projection of the anode on the substrate.

[0019] In an exemplary embodiment, on a plane parallel to the substrate, in the direction from the second groove to the corresponding second opening, the ratio of the size of the second groove to the size of the first groove is greater than or equal to 2:1.

[0020] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the ratio of the size of the second groove to the size of the first groove is greater than or equal to 5:1.

[0021] In an exemplary embodiment, the thickness of the second insulator structure is greater than half the thickness of the light-emitting structure layer in a direction perpendicular to the plane of the substrate.

[0022] In an exemplary embodiment, the thickness of the second electrode adapter structure is greater than half the thickness of the light-emitting structure layer in a direction perpendicular to the plane of the substrate.

[0023] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the partition structure layer includes a first partition structure layer and a second partition structure layer stacked sequentially on the side of the pixel definition layer away from the substrate. The surface of the first partition structure layer near any of the second openings is recessed into the surface of the second partition structure layer near the same second opening, forming the second groove.

[0024] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the second partition structure layer, and the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the pixel definition layer.

[0025] In an exemplary embodiment, the cross-sectional structure of the first partition structure layer between two adjacent second openings is a "T" shaped structure.

[0026] In an exemplary embodiment, the cross-sectional structure of the partition structure layer and the pixel definition layer between two adjacent second openings is an "I" shaped structure.

[0027] In an exemplary embodiment, the cross-sectional structure of the partition structure layer between two adjacent second openings is a "T" shaped structure.

[0028] In an exemplary embodiment, the light-emitting structure, the corresponding anode, and the corresponding second electrode constitute a light-emitting device. The driving circuit layer includes multiple pixel driving circuits, at least one pixel driving circuit corresponds to at least one light-emitting device, and the pixel driving circuit is electrically connected to the anode and the second electrode in the corresponding light-emitting device, configured to drive the corresponding light-emitting device to emit light.

[0029] In an exemplary embodiment, the display substrate further includes a plurality of first power lines, each first power line corresponding to one or more pixel driving circuits, and at least one pixel driving circuit including a driving transistor and a fifth transistor as a light-emitting transistor.

[0030] The first power line is located in the driving circuit layer. The second electrode is electrically connected to the first electrode of the driving transistor in the corresponding pixel driving circuit through a corresponding second electrode signal line. The anode is electrically connected to the second electrode of the fifth transistor in the corresponding pixel driving circuit. The first electrode of the fifth transistor is electrically connected to the corresponding first power line. Alternatively, the first power line is located in the anode layer. The second electrode is electrically connected to the first electrode of the fifth transistor in the corresponding pixel driving circuit through a corresponding second electrode signal line. The second electrode of the fifth transistor is electrically connected to the first electrode of the corresponding driving transistor. The first power line is multiplexed as one or more anodes.

[0031] In an exemplary embodiment, the anode layer further includes a plurality of first power lines, each first power line corresponding to one or more pixel driving circuits. The first power lines are multiplexed as one or more anodes. At least one pixel driving circuit includes a driving transistor. The second electrode is electrically connected to the first electrode of the driving transistor in the corresponding pixel driving circuit through a corresponding second electrode signal line.

[0032] In an exemplary embodiment, at least one pixel driving circuit further includes a second transistor as an initialization transistor, wherein the second terminal of the second transistor is electrically connected to the first terminal of the driving transistor.

[0033] The first electrode of the second transistor is electrically connected to the corresponding first power supply line; or the driving circuit layer further includes a plurality of second initial signal lines, one second initial signal line corresponding to at least one pixel driving circuit, and the first electrode of the second transistor is electrically connected to the corresponding second initial signal line.

[0034] In an exemplary embodiment, the driving circuit layer further includes a plurality of first power lines and a plurality of second initial signal lines. The first power lines correspond to one or more pixel driving circuits, and one second initial signal line corresponds to one or more pixel driving circuits. At least one pixel driving circuit includes a driving transistor, a fifth transistor as a light-emitting transistor, a second transistor as an initialization transistor, and a seventh transistor as an initialization transistor.

[0035] The second electrode is electrically connected to the first electrode of the driving transistor in the corresponding pixel driving circuit through the corresponding second electrode signal line. The anode is electrically connected to the second electrode of the fifth transistor in the corresponding pixel driving circuit. The first electrode of the fifth transistor is electrically connected to the corresponding first power supply line.

[0036] In the same pixel driving circuit, the first terminal of the second transistor is electrically connected to the corresponding second initial signal line, and the second terminal of the second transistor is electrically connected to the first terminal of the driving transistor; the first terminal of the seventh transistor is electrically connected to the corresponding second initial signal line, and the second terminal of the seventh transistor is electrically connected to the second terminal of the driving transistor.

[0037] In an exemplary embodiment, the pixel driving circuit includes a plurality of transistors, and the second electrode signal line is electrically connected to at least one electrode of at least one transistor, or at least one electrode of at least one transistor is multiplexed as the second electrode signal line.

[0038] Secondly, embodiments of this disclosure provide a display substrate, including a substrate and a driving circuit layer, a second electrode transition layer, a pixel definition layer, a partition structure layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds one-to-one with at least one light-emitting structure and at least one second electrode, and at least a portion of the light-emitting structure and the second electrode is located in the corresponding pixel opening;

[0039] The partition structure layer is provided with a plurality of second openings, at least one of which corresponds to at least one pixel opening. The orthographic projection of the second opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the second opening is provided with a second groove. The light-emitting structure layer is broken at the position of the second groove. The second electrode layer is broken at the position of the second groove to form a corresponding second electrode.

[0040] The driving circuit layer includes multiple second electrode signal lines, and the second electrode transition layer includes multiple second electrode transition structures. Each second electrode transition structure corresponds one-to-one with at least one second electrode signal line, at least one second electrode, and at least one pixel opening. The second electrode is electrically connected to the corresponding second electrode transition structure, and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure.

[0041] In an exemplary embodiment, the second electrode adapter structure has a first groove on the side near the corresponding pixel opening, the light-emitting structure layer is disconnected at the first groove position to form a corresponding light-emitting structure, and the second electrode layer is electrically connected to the corresponding second electrode adapter structure at the first groove position.

[0042] In an exemplary embodiment, the second electrode layer is connected to the corresponding second electrode transition structure at the disconnected position. In the pixel opening and the second electrode transition structure corresponding to the same second electrode, the pixel opening and the orthographic projection of the second electrode transition structure on the substrate at least partially overlap, and the overlapping area is smaller than the non-overlapping area.

[0043] In an exemplary embodiment, the second electrode transition layer is reused as an anode layer, the anode layer includes a plurality of anodes, at least one of the anodes corresponds one-to-one with at least one second opening and at least one second electrode transition structure, the anodes and second electrode transition structures corresponding to the same second opening are spaced apart, and the second electrode transition structure is electrically connected to the corresponding second electrode through a via.

[0044] In an exemplary embodiment, the driving circuit layer further includes a plurality of pixel driving circuits and a plurality of second electrode adapter lines. In a direction perpendicular to the plane of the display substrate, the plurality of second electrode adapter lines are located on the side of the plurality of second electrode signal lines closer to the substrate. At least one pixel driving circuit corresponds one-to-one with at least one second electrode adapter structure and at least one second electrode adapter line. The second electrode adapter structure is electrically connected to the corresponding pixel driving circuit through the corresponding second electrode adapter line.

[0045] In an exemplary embodiment, at least one pixel opening corresponds one-to-one with at least one anode and at least one second electrode adapter wire;

[0046] The second electrode adapter cable includes a first structural portion and a second structural portion. The first structural portion extends along a first direction, and the second structural portion extends along a second direction. One end of the first structural portion is electrically connected to the corresponding second electrode signal line through a via, and the other end of the first structural portion is connected to the second structural portion. One end of the second structural portion is connected to the first structural portion, and the other end of the second structural portion is electrically connected to the corresponding pixel driving circuit. The orthographic projections of the first structural portion and the corresponding pixel opening on the substrate do not overlap, and the orthographic projections of the second structural portion and the corresponding pixel opening on the substrate at least partially overlap. In the first direction, the orthographic projection of the pixel opening on the substrate is symmetrical with respect to the orthographic projection of the corresponding second structural portion on the substrate.

[0047] Alternatively, the second electrode adapter cable includes a first structural portion, a second structural portion, and a third structural portion. The first structural portion and the third structural portion extend along a first direction, and the second structural portion extends along a second direction. The first structural portion and the third structural portion are connected through the second structural portion. The first structural portion is electrically connected to the corresponding second electrode signal line through a via. The third structural portion is electrically connected to the corresponding pixel driving circuit. The orthographic projection of the second electrode adapter cable and the corresponding pixel opening on the substrate does not overlap. The orthographic projection of the second structural portion and the third structural portion on the substrate at least partially overlaps with the orthographic projection of the corresponding anode on the substrate. In the first direction, the central position of the third structural portion is electrically connected to the corresponding pixel driving circuit.

[0048] Alternatively, the second electrode adapter cable includes a first structural portion and a second structural portion. The first structural portion extends along a first direction, and the second structural portion extends along a second direction. The first structural portion and the second structural portion form a cross-shaped structure. The first structural portion is electrically connected to the corresponding second electrode signal line through a via, and the second structural portion is electrically connected to the corresponding pixel driving circuit. In the first direction, the orthographic projection of the pixel opening on the substrate is symmetrical with respect to the orthographic projection of the corresponding second structural portion on the substrate. In the second direction, the orthographic projection of the pixel opening on the substrate is symmetrical with respect to the orthographic projection of the corresponding first structural portion on the substrate.

[0049] Thirdly, embodiments of this disclosure provide a display substrate including a plurality of sub-pixels, at least one sub-pixel including a light-emitting device and a pixel driving circuit for driving the light-emitting device, and at least one pixel driving circuit including a first reset sub-circuit, a second reset sub-circuit, a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, and a storage sub-circuit.

[0050] The first reset sub-circuit is electrically connected to the first scan signal line, the first node, and the first initial signal line, respectively, and is configured to write the signal of the first initial signal line into the first node under the control of the first scan signal line;

[0051] The second reset sub-circuit is electrically connected to the second scan signal line and the second node, and is also electrically connected to the second initial signal line or the first power line. It is configured to write the signal of the second initial signal line or the signal of the first power line into the first node under the control of the second scan signal line.

[0052] The driving sub-circuit is electrically connected to the first node, the second node, and the third node, respectively, and is configured to control the potential of the third node according to the signals of the first node and the second node;

[0053] The data writing sub-circuit is connected to the fourth scan signal line, the data signal line and the first node, respectively, and is configured to write the signal of the data signal line into the first node under the control of the fourth scan signal line.

[0054] The first light-emitting control sub-circuit is electrically connected to the third node, the second light-emitting signal line, and the second power line, respectively, and is configured to form a loop between the third node and the second power line under the control of the second light-emitting signal line;

[0055] The storage sub-circuit is electrically connected to the first node and the third node respectively, and is configured to store charge under the control of the first node and the third node;

[0056] The light-emitting device is electrically connected to the first power line and the second node respectively, and is configured to emit light under the control of the pixel driving circuit.

[0057] In an exemplary embodiment, the pixel driving circuit further includes a second light emission control sub-circuit;

[0058] The second light-emitting control sub-circuit is electrically connected to the fourth node, the first light-emitting signal line, and the first power line, respectively. It is configured to provide the signal of the first power line to the fourth node under the control of the first light-emitting signal line. The light-emitting device is electrically connected to the first power line through the second light-emitting control sub-circuit.

[0059] Alternatively, the second light-emitting control sub-circuit is electrically connected to the fourth node, the first light-emitting signal line, and the second node, respectively, and is configured to provide the signal of the fourth node to the second node under the control of the first light-emitting signal line, and the light-emitting device is electrically connected to the second node through the second light-emitting control sub-circuit.

[0060] In an exemplary embodiment, the pixel driving circuit further includes a third reset circuit;

[0061] The third reset circuit is electrically connected to the third scan signal line, the third node, and the second initial signal line, respectively, and is configured to write the signal of the second initial signal line into the third node under the control of the third scan signal line.

[0062] Fourthly, embodiments of this disclosure provide a display device including any of the display substrates described above.

[0063] Fifthly, embodiments of this disclosure provide a method for preparing a display substrate, comprising:

[0064] A driving circuit layer, a second electrode transition layer, and a pixel definition layer are sequentially formed on one side of the substrate. The driving circuit layer includes multiple second electrode signal lines, the second electrode transition layer includes multiple second electrode transition structures, the pixel definition layer is provided with multiple pixel openings, at least one second electrode transition structure is provided with a first opening, at least one first opening corresponds one-to-one with at least one pixel opening, the orthographic projection of the first opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap, and the sidewall of the first opening is provided with a first groove.

[0065] A light-emitting structure layer is formed on the side of the pixel definition layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, at least one of which corresponds to at least one pixel opening. At least a portion of the light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the first groove position to form the corresponding light-emitting structure.

[0066] A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds to at least one second electrode, and at least a portion of the second electrode is located in the corresponding pixel opening. At least one second electrode adapter structure corresponds to at least one second electrode signal line and at least one second electrode. The second electrode layer is electrically connected to the corresponding second electrode signal line at the first groove position. The second electrode is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode adapter structure.

[0067] Sixthly, embodiments of this disclosure provide a method for preparing a display substrate, comprising:

[0068] A driving circuit layer, a second electrode transition layer, and a pixel definition layer are sequentially formed on one side of the substrate. The driving circuit layer includes multiple second electrode signal lines, the second electrode transition layer includes multiple second electrode transition structures, and the pixel definition layer is provided with multiple pixel openings.

[0069] A partition structure layer is formed on the side of the pixel definition layer away from the substrate. The partition structure layer is provided with a plurality of second openings. At least one second opening corresponds to at least one pixel opening. The orthographic projection of the second opening on the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening on the substrate. The sidewall of the second opening is provided with a second groove.

[0070] A light-emitting structure layer is formed on the side of the partition structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, at least one of which corresponds to at least one pixel opening. At least a portion of the light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the second groove position.

[0071] A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer includes a plurality of second electrodes, and one second electrode adapter structure corresponds one-to-one with at least one second electrode signal line, at least one second electrode, and at least one pixel opening. At least a portion of the second electrode is located in the corresponding pixel opening. The second electrode layer is disconnected at the second groove position to form a corresponding second electrode. The second electrode is electrically connected to the corresponding second electrode adapter structure, and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode adapter structure.

[0072] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0073] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0074] Figure 1 is a schematic diagram of a display device;

[0075] Figure 2 is a schematic diagram of the planar structure of a display device;

[0076] Figure 3 is a cross-sectional structural diagram of a display substrate provided in an embodiment of this disclosure;

[0077] Figure 4a is an equivalent circuit diagram of a pixel driving circuit;

[0078] Figure 4b is an equivalent circuit diagram of a pixel driving circuit;

[0079] Figure 4c is an equivalent circuit diagram of a pixel driving circuit;

[0080] Figure 5 is a schematic diagram of the sensitivity curve of the pixel driving circuit to the cathode voltage drop;

[0081] Figure 6a is a cross-sectional structural diagram of a display substrate provided in an embodiment of this disclosure;

[0082] Figure 6b is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0083] Figure 6c is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0084] Figure 6d is a schematic diagram of a planar structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0085] Figure 6e is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0086] Figure 6f is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0087] Figure 6g is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0088] Figure 6h is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0089] Figure 6i is a cross-sectional structural diagram of a display substrate provided in an embodiment of this disclosure;

[0090] Figure 6j is a schematic planar structure of at least a portion of the film layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0091] Figure 6k is a schematic planar structure of at least a portion of the film layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0092] Figure 61 is a schematic planar structure of at least a portion of the film layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0093] Figure 6m is a schematic planar structure of at least a portion of the film layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0094] Figure 6n is a schematic diagram of the planar structure of at least a portion of the film layer in a display substrate provided by an exemplary embodiment of the present disclosure;

[0095] Figure 7a is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment of the present disclosure;

[0096] Figure 7b is an equivalent circuit diagram of a pixel driving circuit provided by an exemplary embodiment of the present disclosure;

[0097] Figure 7c is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure;

[0098] Figure 7d is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure;

[0099] Figure 7e is an equivalent circuit diagram of a pixel driving circuit provided in an exemplary embodiment of the present disclosure;

[0100] Figure 7f is a cross-sectional structural diagram of a display substrate provided in an exemplary embodiment of the present disclosure;

[0101] Figure 8 shows a timing diagram of one operation of the pixel driving circuit shown in Figure 7a;

[0102] Figure 9a is a schematic diagram of a display substrate after the formation of a second insulator layer according to an exemplary embodiment of the present disclosure;

[0103] Figure 9b is a schematic diagram of a display substrate after forming a second electrode transfer structure according to an exemplary embodiment of the present disclosure;

[0104] Figure 9c is a schematic diagram of a planar structure of Figure 9b;

[0105] Figure 9d is a schematic diagram of a planar structure of Figure 9b;

[0106] Figure 9e is a schematic diagram of a display substrate after forming a pixel definition layer according to an exemplary embodiment of the present disclosure;

[0107] Figure 9f is a schematic diagram of a planar structure of Figure 9e;

[0108] Figure 9g is a schematic diagram of a display substrate after the formation of a partition structure layer according to an exemplary embodiment of the present disclosure;

[0109] Figure 9h is a schematic diagram of a display substrate after the formation of a first encapsulation layer for a first sub-pixel, provided by an exemplary embodiment of the present disclosure.

[0110] Figure 9i is a schematic diagram of a display substrate after forming a first encapsulation layer for a second sub-pixel, provided by an exemplary embodiment of the present disclosure;

[0111] Figure 9j is a schematic diagram of a display substrate after forming a first encapsulation layer for a third sub-pixel, provided by an exemplary embodiment of the present disclosure;

[0112] Figure 9k is a schematic diagram of a display substrate after forming a second encapsulation layer according to an exemplary embodiment of the present disclosure;

[0113] Figure 10 is a schematic diagram of a sub-pixel provided in an embodiment of this disclosure;

[0114] Figure 11 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0115] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0116] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0117] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0118] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0119] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0120] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0121] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0122] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0123] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0124] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0125] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0126] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0127] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij.

[0128] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, and can provide clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver. The data signal driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a sub-pixel row basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to the scan signal lines S1 to Sm. For example, a scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A sub-pixel array can include multiple sub-pixels PXij. Each sub-pixel PXij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. A sub-pixel PXij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0129] Figure 2 is a schematic diagram of a planar structure of a display device. As shown in Figure 2, the display area of ​​the display device may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is connected to a scan signal line and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of its respective sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0130] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel emitting red (R) light, the second sub-pixel P2 can be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 can be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels can be any one or more of triangles, squares, rectangles, rhombuses, trapezoids, parallelograms, pentagons, hexagons, and other polygons, and they can be arranged in horizontal parallel, vertical parallel, X-shaped, cross-shaped, triangular, square, diamond-shaped, or delta-shaped arrangements, etc., without limitation herein.

[0131] In an exemplary embodiment, the number of sub-pixels included in a pixel unit is not limited to three. For example, a pixel unit may include four sub-pixels, and this disclosure does not limit it.

[0132] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0133] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the driving force of the anode 301 and the cathode 303. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403, ensuring that external moisture cannot enter the light-emitting structure layer 103.

[0134] In an exemplary embodiment, the organic light-emitting layer 302 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0135] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 7T2C, or 8T1C structure. Figures 4a to 4c are equivalent circuit diagrams of the three pixel driving circuits.

[0136] In an exemplary embodiment, as shown in FIG4a, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit may be connected to seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS).

[0137] In an exemplary embodiment, as shown in FIG4a, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0138] In an exemplary embodiment, as shown in FIG4a, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0139] As shown in Figure 4a, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0140] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0141] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0142] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0143] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0144] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conduction level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0145] In an exemplary embodiment, as shown in FIG4a, the second electrode of the light-emitting device is connected to the second power line VSS. The signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 can be S(n), and the second scan signal line S2 can be S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize the narrow bezel of the display panel.

[0146] In an exemplary embodiment, as shown in FIG4a, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0147] In an exemplary embodiment, in the pixel driving circuit shown in FIG4a, the first scan signal line S1, the second scan signal line S2, the light emission signal line E and the initial signal line INIT extend in the horizontal direction, and the second power supply line VSS, the first power supply line VDD and the data signal line D extend in the vertical direction.

[0148] In an exemplary embodiment, in the pixel driving circuit shown in FIG4a, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer and a second electrode (cathode) stacked together.

[0149] In an exemplary embodiment, as shown in FIG4b, the pixel driving circuit may include five transistors (first transistor T1 to fifth transistor T5) and one storage capacitor C. The pixel driving circuit may be connected to nine signal lines (data signal line D, first scan signal line S1, second scan signal line S2, third scan signal line S3, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, first power supply line VDD and second power supply line VSS).

[0150] In an exemplary embodiment, as shown in FIG4b, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second terminal of the first transistor T1, the second terminal of the second transistor T2, the control terminal of the third transistor T3, and the first plate of the storage capacitor C. The second node N2 is connected to the first terminal of the third transistor T3 and the second terminal of the fifth transistor T5. The third node N3 is connected to the second terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second plate of the storage capacitor C.

[0151] In an exemplary embodiment, as shown in FIG4b, the first plate of the storage capacitor C is connected to the first node N1, and the second plate of the storage capacitor C is connected to the third node N3, that is, the first plate of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0152] As shown in Figure 4b, the control electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the data signal line D, and the second electrode of the first transistor is connected to the first node N1. When a conduction-level scan signal is applied to the first scan signal line S1, the first transistor T1 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0153] The control electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is connected to the first node N1. When a conduction-level scan signal is applied to the second scan signal line S2, the second transistor T2 transmits the initial voltage of the second initial signal line INIT2 to the control electrode of the third transistor T3, thereby initializing the charge of the control electrode of the third transistor T3.

[0154] The control electrode of the third transistor T3 is connected to the first node N1, meaning the control electrode of the third transistor T3 is connected to the first plate of the storage capacitor C. The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode. The control electrode of the fourth transistor T4 is connected to the third scan signal line S3. The first electrode of the fourth transistor T4 is connected to the first initial signal line INIT1, and the second electrode of the fourth transistor T4 is connected to the third node N3. When the on-level scan signal is applied to the third scan signal line S3, the fourth transistor T4 transmits the initial voltage of the first initial signal line INIT1 to the first electrode of the light-emitting device, thereby initializing or releasing the accumulated charge in the first electrode of the light-emitting device.

[0155] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The fifth transistor T5 can be called a light-emitting transistor. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 emits light by forming a drive current path between the first power supply line VDD and the second power supply line VSS.

[0156] In an exemplary embodiment, as shown in FIG4b, the second electrode of the light-emitting device OLED is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0157] In an exemplary embodiment, in the pixel driving circuit shown in FIG4b, the first transistor T1 to the fifth transistor T5 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the fifth transistor T5 may include both P-type and N-type transistors.

[0158] In an exemplary embodiment, in the pixel driving circuit shown in FIG4b, the first scan signal line S1, the second scan signal line S2, the light emission signal line E and the first initial signal line INIT1 can extend in the horizontal direction, and the second power supply line VSS, the first power supply line VDD, the second initial signal line INIT2 and the data signal line D can extend in the vertical direction.

[0159] In an exemplary embodiment, as shown in FIG4c, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and two storage capacitors C. The pixel driving circuit may be connected to seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, third scan signal line S3, light emission signal line E, initial signal line INIT, reference voltage power supply line Vref, first power supply line VDD and second power supply line VSS).

[0160] In an exemplary embodiment, as shown in FIG4c, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth structure N4, an anode of a light-emitting device, and a fifth node N5. The first node N1 is connected to the control electrode of the third transistor T3, the first electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the sixth transistor T6. The second node N2 is connected to the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3. The third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7, and the second terminal of the first capacitor C1. The fourth node N4 is connected to the first terminal of the first capacitor C1, the second electrode of the first transistor T1, and the second terminal of the second capacitor C2. The fifth node N4 is connected to the first terminal of the second capacitor C2, the second electrode of the fourth transistor T4, and the second electrode of the sixth transistor T6.

[0161] In an exemplary embodiment, as shown in FIG4c, the first end of the first capacitor C1 is connected to the fourth node N4, and the second end of the first capacitor C1 is connected to the third node N3; the first end of the second capacitor C2 is connected to the fifth node N5, and the second end of the second capacitor C2 is connected to the fourth node N4.

[0162] As shown in Figure 4c, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2...

[0163] The control electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the reference voltage power supply line Vref, and the second electrode of the second transistor T2 is connected to the first node N1. The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power supply line VDD and the second power supply line VSS is determined by the potential difference between its control electrode and its first electrode.

[0164] The control electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the fifth node N5. The fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction-level scan signal is applied to the third scan signal line S3, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0165] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the first node N1, and the second electrode of the sixth transistor T6 is connected to the fifth node N5. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode (i.e., the anode) of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0166] In an exemplary embodiment, as shown in FIG4c, the second electrode of the light-emitting device is connected to the second power line VSS. The signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 can be S(n), and the second scan signal line S2 can be S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize the narrow bezel of the display panel.

[0167] In an exemplary embodiment, as shown in FIG4c, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0168] In an exemplary embodiment, in the pixel driving circuit shown in FIG4c, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the light emission signal line E, and the initial signal line INIT extend in the horizontal direction, while the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in the vertical direction.

[0169] In an exemplary embodiment, in the pixel driving circuit shown in FIG4c, the light-emitting device may be an organic electroluminescent diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0170] In the pixel driving circuits shown in Figures 4a to 4c, the structure of the second power line VSS is typically the cathode 303 shown in Figure 3. The cathode 300 is an integral structure laid flat on the side of the organic light-emitting layer 302 away from the substrate 101. This integral structure of the cathode provides the second power signal to all sub-pixels in the display substrate. This results in a large cathode voltage drop, poor brightness uniformity among multiple sub-pixels in the display substrate (especially poor uniformity at high brightness levels), and poor long-range uniformity of the display substrate. Uniformity (LRU) is an indicator for evaluating brightness uniformity. Different pixel driving circuits exhibit varying sensitivities to cathode voltage drop, as shown in Figure 5. The graph shows the sensitivity curves of different pixel driving circuits to cathode voltage drop. The horizontal axis represents the actual voltage at the cathode (in volts V), and the horizontal axis represents the percentage difference in current flowing through the light-emitting device (EL). Specifically, L11 is the cathode sensitivity curve for the 7T1C pixel driving circuit (all seven transistors are polysilicon transistors) in Figure 4a; L12 is the cathode sensitivity curve for the 5T1C pixel driving circuit (all five transistors are oxide transistors) in Figure 4b; and L13 is the cathode sensitivity curve for the 7T2C pixel driving circuit (all seven transistors are oxide transistors) in Figure 4c. As can be seen from Figure 5, the 7T2C pixel driving circuit is the most sensitive to cathode voltage drop, followed by the 5T1C, and the 7T1C pixel driving circuit is the least sensitive. This demonstrates that oxide transistors are highly sensitive to cathode voltage drops and are significantly affected by them. Furthermore, in pixel driving circuits where all transistors are oxide transistors, the 7T2C pixel driving circuit is more sensitive to cathode voltage drops than the 5T1C pixel driving circuit. Generally, the more sensitive the pixel driving circuit is to cathode voltage drops, the more uneven the brightness of the display substrate. Therefore, overcoming the technical problem of poor brightness uniformity of the display substrate caused by cathode (which can be called the second electrode) voltage drops is a pressing technical issue that needs to be addressed in the display substrate field.

[0171] This disclosure provides a display substrate, which may include a substrate and a driving circuit layer, a second electrode transition layer, a pixel definition layer, a light-emitting structure layer and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds one-to-one with at least one light-emitting structure and at least one second electrode, and at least a portion of the light-emitting structure and the second electrode is located in the corresponding pixel opening.

[0172] The driving circuit layer includes multiple second electrode signal lines, and the second electrode transition layer includes multiple second electrode transition structures. Each second electrode transition structure corresponds one-to-one with at least one second electrode signal line and at least one second electrode. The second electrode is electrically connected to the corresponding second electrode transition structure, and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure.

[0173] At least one second electrode adapter structure is provided with a first opening, and at least one first opening corresponds one-to-one with at least one pixel opening. The orthographic projection of the first opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the first opening is provided with a first groove. The light-emitting structure layer is disconnected at the first groove position to form a corresponding light-emitting structure. The second electrode layer is electrically connected to the corresponding second electrode adapter structure at the first groove position.

[0174] The display substrate provided in this embodiment includes a substrate and a driving circuit layer, a second electrode transition layer, a pixel definition layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate. The driving circuit layer includes a plurality of second electrode signal lines, the second electrode transition layer includes a plurality of second electrode transition structures, the pixel definition layer has a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds one-to-one with at least one light-emitting structure and at least one second electrode, at least a portion of the light-emitting structure and the second electrode is located in the corresponding pixel opening, at least one second electrode signal line corresponds one-to-one with at least one second electrode transition structure and at least one second electrode, the second electrode is electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure, the sidewall of the first opening is provided with a first groove, the light-emitting structure layer is disconnected at the first groove position to form the corresponding light-emitting structure, and the second electrode layer is electrically connected to the corresponding second electrode transition structure at the first groove position. The technical solution provided in this disclosure embodiment is that the second electrode is electrically connected to the corresponding second electrode signal line through the corresponding second electrode adapter structure. That is, the signal of the second electrode can be provided by the corresponding second electrode signal line located in the driving circuit layer. This can avoid the problem of large voltage drop when multiple light-emitting structures share a second electrode layer, thereby avoiding the technical problem of poor brightness uniformity of the display substrate due to large voltage drop of the second electrode, and greatly improving the display uniformity of the display substrate.

[0175] Figure 6a is a cross-sectional view of a display substrate according to an embodiment of the present disclosure. As shown in Figure 6a, the display substrate may include a substrate 101 and a driving circuit layer 102, a second electrode transition layer 13, a pixel definition layer PDL, a light-emitting structure layer 40, and a second electrode layer 42 sequentially disposed on one side of the substrate 101; the pixel definition layer PDL is provided with a plurality of pixel openings K11, the light-emitting structure layer 40 includes a plurality of light-emitting structures 41, the second electrode layer 42 includes a plurality of second electrodes 420, and at least one pixel opening K11 corresponds one-to-one with at least one light-emitting structure 41 and at least one second electrode 420, and at least a portion of the light-emitting structure 41 and the second electrode 420 is located in the corresponding pixel opening K11;

[0176] The driving circuit layer 102 may include a plurality of second electrode signal lines 1021, and the second electrode transition layer 13 may include a plurality of second electrode transition structures 131, wherein one second electrode transition structure 131 corresponds one-to-one with at least one second electrode signal line 1021 and at least one second electrode 420, and the second electrode 420 is electrically connected to the corresponding second electrode transition structure 131, configured to be electrically connected to the corresponding second electrode signal line 1021 through the corresponding second electrode transition structure 131;

[0177] At least one second electrode adapter structure 131 is provided with a first opening K21, and at least one first opening K21 corresponds one-to-one with at least one pixel opening K11. The orthographic projection of the first opening on the substrate K21 and the orthographic projection of the corresponding pixel opening K11 on the substrate 101 at least partially overlap. The sidewall of the first opening K11 is provided with a first groove W1. The light-emitting structure layer 40 is disconnected at the first groove W1 to form a corresponding light-emitting structure 41. The second electrode layer 42 is electrically connected to the corresponding second electrode adapter structure 131 at the first groove W1.

[0178] In an exemplary embodiment, the second electrode layer 42 can be disconnected at the first groove W1 to form a corresponding second electrode 420, and electrically connected to the corresponding second electrode adapter structure 131 at the disconnected position. This embodiment is not limited to this; for example, the second electrode layer 42 may not be disconnected at the first groove W1, and may overlap with the corresponding second electrode adapter structure 131 at the first groove W1. The electrical connection between the second electrode layer 42 and the corresponding second electrode adapter structure 131 at the first groove W1 can avoid the problem of uneven display caused by a large voltage drop at the second electrode.

[0179] In some possible implementations, the display device may include other film layers. For example, as shown in Figures 6e to 6g, the display substrate may also include an encapsulation layer 43 disposed on the side of the second electrode layer 42 away from the substrate, a color filter structure layer and a touch structure layer disposed on the encapsulation structure layer 43 away from the substrate, and a plurality of first electrodes 11 located between the driving circuit layer 102 and the light-emitting structure layer 40. This disclosure is not limited herein. In an exemplary embodiment, the first electrode 11 (which may serve as an anode), the second electrode 420 (which may serve as a cathode), and the light-emitting structure 41 located between the first electrode 11 and the second electrode 42 constitute a light-emitting device. There are multiple first electrodes 11, and each of the multiple first electrodes 11 corresponds one-to-one with a plurality of light-emitting structures 41. At least a portion of the first electrodes 11 is located in the pixel opening K11, and the orthographic projections of the first electrodes 11 and the corresponding light-emitting structures 41 on the substrate 101 at least partially overlap. In an exemplary embodiment, the encapsulation layer 43 may include a first encapsulation layer 431 and a second encapsulation layer 432. In the direction Z perpendicular to the plane where the display substrate is located, the first encapsulation layer 431 may be located between the second encapsulation layer 432 and the second electrode layer 42. The first encapsulation layer 431 may be a pixel-level encapsulation, that is, an encapsulation performed on each sub-pixel, and the second encapsulation layer 432 may be an encapsulation of the entire display substrate.

[0180] In an exemplary embodiment, the substrate 101 may be a flexible substrate, such as polyimide (PI). The driving circuit layer 102 may be fabricated on the substrate 101 using silicon semiconductor processes (e.g., CMOS processes). The driving circuit layer 102 may include multiple pixel driving circuits, and a sub-pixel may include a light-emitting device and a pixel driving circuit that drives the light-emitting device to emit light.

[0181] In an exemplary embodiment, the second electrode layer 42 can be overlapped with the corresponding second electrode transition structure 131. In an exemplary embodiment, in the pixel opening K11 corresponding to the same second electrode 420 and the second electrode transition structure 131, the orthographic projection of the pixel opening K11 and the second electrode transition structure 131 on the substrate 101 at least partially overlaps, and the overlapping area is smaller than the non-overlapping area. On the one hand, this allows the second electrode layer 42 to overlap with the second electrode transition structure 131, and on the other hand, it ensures that there is a sufficiently large pixel opening, thereby improving the aperture ratio.

[0182] In an exemplary embodiment, as shown in Figures 6a to 6c, the display substrate may further include a partition structure layer 30, which may be located between the pixel definition layer PDL and the light-emitting structure layer 40 in the direction Z perpendicular to the plane of the substrate 101.

[0183] The partition structure layer 30 is provided with a plurality of second openings K22, at least one second opening K22 corresponds one-to-one with at least one pixel opening K11, and the orthographic projection of the second opening K22 on the substrate 101 at least partially overlaps with the orthographic projection of the corresponding pixel opening K11 on the substrate 101. The sidewall of the second opening K22 is provided with a second groove W2, and the light-emitting structure layer 40 and the second electrode layer 42 are disconnected at the position of the second groove W2. The second electrode layer 42 can be disconnected at the position of the second groove W2 to form a corresponding second electrode 420, or the second electrode layer 42 can be disconnected at the position of the first groove W1 to form a corresponding second electrode 420.

[0184] In an exemplary embodiment, as shown in FIG6d, which is a schematic diagram of a planar structure of FIG6a to FIG6c, multiple second openings K22 can be spaced apart by the partition structure layer 30 in the plane where the display substrate is located.

[0185] In an exemplary embodiment, the first groove W1 can disconnect the light-emitting structure layer 40 and the second electrode layer 42, allowing the light-emitting structure 41 and the second electrode 420 corresponding to the same pixel opening K11 to form independent structures. They will not be connected to the light-emitting structure 41 and the second electrode 42 corresponding to other pixel openings K11, thus avoiding crosstalk between adjacent light-emitting structures 41 and effectively reducing the risk of display abnormalities. In addition, by isolating the cathode (second electrode layer 42) at the pixel level, the second electrode 420 of each sub-pixel is independently powered through the corresponding second electrode signal line 1021 in the driving circuit layer 102, overcoming the technical problem of uneven brightness of the display substrate caused by the large voltage drop of the second electrode layer, and greatly improving the display uniformity of the display substrate.

[0186] In an exemplary embodiment, the second groove W2 can ensure that the second electrode layer 42 is disconnected (the first groove W1 may not completely disconnect the second electrode layer 42), ensuring that the multiple second electrodes 420 corresponding to the multiple pixel openings K11 are independent and there is no electrical connection between them. This allows the second electrode 420 of each pixel opening K11 to be set independently, without connection to the second electrodes 420 corresponding to other pixel openings K11. The corresponding second electrode 420 can be flexibly controlled independently through the second electrode signal line 1021, which can improve the flexibility of the display substrate operation.

[0187] In an exemplary embodiment, the orthographic projection of the first opening K21 on the substrate 101 is within the range of the orthographic projection of the corresponding pixel opening K11 on the substrate, and the orthographic projection of the pixel opening K11 on the substrate 101 is within the range of the orthographic projection of the corresponding second opening K22 on the substrate 101.

[0188] In an exemplary embodiment, the display substrate may further include an anode layer 110. In the direction Z perpendicular to the plane of the display substrate, the anode layer 110 may be located between the driving circuit layer 102 and the second electrode transition layer 13. The anode layer 110 may include a plurality of anodes 11, and at least one anode 11 corresponds one-to-one with at least one pixel opening K11 and at least one second electrode transition structure 131. The second electrode transition structure 131 includes a first insulator structure 1311 and a second electrode transition substructure 1310 sequentially disposed on the side of the anode layer 110 away from the substrate 101. The second electrode 420 is overlapped and connected to the corresponding second electrode transition structure 1310.

[0189] In the anode 11 and the second electrode transition structure 131 corresponding to the same pixel opening K11, the first insulator structure 1311 is set to insulate the second electrode transition substructure 1310 from the anode 11. The overlapping area of ​​the first insulator structure 1311 and the anode 11 projected onto the substrate 101 covers the overlapping area of ​​the second electrode transition substructure 1310 and the anode projected onto the substrate 101, which can prevent the second electrode transition substructure 1310 from being short-circuited with the corresponding anode.

[0190] In an exemplary embodiment, as shown in FIG6h, in the second electrode transition structure 131, on the side near the first opening K21, a portion of the surface of the first insulator structure 1311 away from the substrate 101, the sidewall of the second electrode transition structure 1310, and a portion of the surface of the pixel definition layer PDL near the substrate 101 form a first groove W1, and the light-emitting structure layer 40 is interrupted at the first groove W1.

[0191] In the anode 11 and the second electrode transition structure 131 corresponding to the same pixel opening K11, the overlapping area of ​​the pixel definition layer PDL corresponding to the pixel opening K11 and the anode 11 projected onto the substrate covers the overlapping area of ​​the second electrode transition substructure 1310 and the anode 11 projected onto the substrate, so as to form the first groove W1.

[0192] In an exemplary embodiment, the pixel opening K11 and the orthographic projection of the second electrode adapter structure 1310 on the substrate 101 at least partially overlap, and the overlapping area is smaller than the non-overlapping area. On the one hand, this allows the second electrode layer 42 to be connected to the second electrode adapter structure 1310, and on the other hand, it ensures that there is a sufficiently large pixel opening to improve the aperture ratio.

[0193] In an exemplary embodiment, as shown in Figures 6a to 6c, the second electrode transition structure 131 may further include a second insulator structure 1312, which is located between the second electrode transition substructure 1310 and the pixel definition layer PDL in the direction Z perpendicular to the plane of the display substrate.

[0194] In the second electrode transition structure 131, a first groove W1 is formed on the side of the first insulator structure 1311 away from the substrate 101, the sidewall of the second electrode transition structure 1310, and the side of the second insulator structure 1312 near the substrate 101. The light-emitting structure layer 40 is broken at the first groove W1 position to form the corresponding light-emitting structure 41.

[0195] In an exemplary embodiment, the first groove W1 forms an undercut structure to disconnect the light-emitting structure layer 40, which allows the light-emitting structure layer 40 to form multiple independent light-emitting structures 41, thereby reducing color crosstalk between adjacent sub-pixels; the second groove W2 forms an undercut structure to disconnect the second electrode layer 42, which allows the second electrode layer 42 to form multiple independent second electrodes 420, thus preventing the second electrode layer 42 from being not completely disconnected in the first groove W1.

[0196] In an exemplary embodiment, on a plane parallel to the base, in the direction from the second groove W2 to the corresponding second opening K22, the ratio of the size L2 of the second groove W2 to the size L1 of the first groove W1 is greater than or equal to 2:1.

[0197] In an exemplary embodiment, in the direction Z perpendicular to the substrate, the ratio of the size H2 of the second groove W2 to the size H1 of the first groove W1 is greater than or equal to 5:1.

[0198] In an exemplary embodiment, L2:L1 is greater than or equal to 2:1 and H2:H1 is greater than or equal to 5:1. During the fabrication of the display substrate, the second electrode layer 42 and the light-emitting structure layer 41 can be disconnected by the second groove W2, and the light-emitting structure layer 41 can be disconnected by the first groove W1. However, this disclosure is not limited to this. The dimensions and corresponding ratios of L2, L1, H2, and H1 can be set according to the thickness of the multiple film layers in the light-emitting structure layer 41 and the thickness of the second electrode layer 42, so that the second groove W2 can disconnect the second electrode layer 42 and the light-emitting structure layer 41, and the first groove W1 can disconnect the light-emitting structure layer 41.

[0199] In an exemplary embodiment, as shown in Figures 6b and 6c, in the direction Z perpendicular to the plane of the substrate, the light-emitting structure layer 40 includes at least a first light-emitting structure sublayer 411, a light-emitting layer 412, and a second light-emitting structure sublayer 413 sequentially stacked on one side of the substrate 101. In an exemplary embodiment, the first light-emitting structure sublayer 411 may include a hole injection layer and a hole transport layer sequentially stacked, and the second light-emitting structure sublayer 413 may include one or more of the following: a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), an electron injection layer (EIL), and a charge production layer (CGL). In the direction Z perpendicular to the substrate, the light-emitting structure 41 located between the first electrode 11 and the second electrode 42 can emit light under the drive of the first electrode 11 and the second electrode 42.

[0200] In an exemplary embodiment, the thickness of the second insulator structure 1312 is greater than half the thickness of the light-emitting structure layer 40 in the direction Z perpendicular to the plane of the substrate.

[0201] In an exemplary embodiment, the thickness of the second electrode transition structure 1310 in the direction Z perpendicular to the plane of the substrate is greater than half the thickness of the light-emitting structure layer 40.

[0202] In an exemplary embodiment, in the direction Z perpendicular to the plane where the substrate is located, the partition structure layer 30 may include a first partition structure layer 31 and a second partition structure layer 32 stacked sequentially on the side of the pixel definition layer PDL away from the substrate. The surface of the first partition structure layer 31 near any second opening K22 is recessed into the surface of the second partition structure layer 32 near the same second opening K22, forming a second groove W2.

[0203] In an exemplary embodiment, in the direction Z perpendicular to the plane where the substrate is located, the thickness of the first partition structure layer 31 is 1.5 to 3 times the thickness of the second partition structure layer 32, and the thickness of the first partition structure layer 31 is 1.5 to 3 times the thickness of the pixel definition layer.

[0204] In an exemplary embodiment, as shown in FIG6c, the cross-sectional structure of the first partition structure layer 31 between two adjacent second openings K22 can be a “T” shaped structure.

[0205] In an exemplary embodiment, as shown in Figures 6a to 6c, the cross-sectional structure of the partition structure layer 30 and the pixel definition layer PDL between two adjacent second openings K22 is an "I" shaped structure.

[0206] In an exemplary embodiment, as shown in Figures 6a to 6c, the cross-sectional structure of the partition structure layer 30 between two adjacent second openings K22 can be a "T" shaped structure.

[0207] In an exemplary embodiment, FIG6d shows a planar structure schematic diagram of FIG6a to FIG6c, and FIG6e and FIG6f show cross-sectional structure schematic diagrams of the display substrate forming the encapsulation layer 43.

[0208] In an exemplary embodiment, the first partition structure layer 31 may be a silicon nitride layer, and the second partition structure layer 32 may be a silicon oxide layer.

[0209] In an exemplary embodiment, the size H2 of the second groove W2 in the direction Z perpendicular to the substrate can be controlled by the thickness of the first partition structure layer 31, and the size H1 of the first groove W1 can be controlled by the thickness of the second electrode adapter structure 1310.

[0210] In an exemplary embodiment, the size L2 of the second groove W2 on a plane parallel to the substrate 101 can be controlled by the speed at which the first partition structure layer 31 and the second partition structure layer 32 are etched during the fabrication of the partition structure layer 30.

[0211] In an exemplary embodiment, the light-emitting structure 41, the corresponding anode 11, and the corresponding second electrode 420 constitute a light-emitting device. The driving circuit layer 102 may include multiple pixel driving circuits, with at least one pixel driving circuit corresponding to at least one light-emitting device. The pixel driving circuit may be electrically connected to the anode 11 and the second electrode 420 in the corresponding light-emitting device, and is configured to drive the corresponding light-emitting device to emit light. Figures 7a to 7e show equivalent circuit diagrams of several pixel driving circuits.

[0212] In an exemplary embodiment, as shown in Figures 7a to 7e, the pixel driving circuit may include a plurality of transistors, and the second electrode signal line 1021 is electrically connected to at least one electrode of at least one transistor, or at least one electrode of at least one transistor is multiplexed as the second electrode signal line 1021.

[0213] In an exemplary embodiment, the display substrate may further include a plurality of first power lines VDD, each first power line VDD corresponding to one or more pixel driving circuits. At least one pixel driving circuit includes a driving transistor (for example, a third transistor T3 may be used as a driving transistor) and a fifth transistor T5 as a light-emitting transistor.

[0214] As shown in Figures 6a to 6c and 7a to 7c, the first power line VDD can be located in the driving circuit layer 102. The second electrode 420 can be electrically connected to the first electrode of the driving transistor T3 in the corresponding pixel driving circuit through the corresponding second electrode signal line 1021. The anode 11 can be electrically connected to the second electrode of the fifth transistor T5 in the corresponding pixel driving circuit. The first electrode of the fifth transistor T5 is electrically connected to the corresponding first power line VDD. Alternatively, as shown in Figures 6f and 7e, the first power line VDD can be located in the anode layer 110. The second electrode 420 can be electrically connected to the first electrode of the fifth transistor T5 in the corresponding pixel driving circuit through the corresponding second electrode signal line 1021. The second electrode of the fifth transistor T5 is electrically connected to the first electrode of the corresponding driving transistor T3. The first power line VDD is multiplexed as one or more anodes 11.

[0215] In an exemplary embodiment, as shown in Figures 6f and 7d, the anode layer 110 may further include a plurality of first power lines VDD, each first power line VDD corresponding to one or more pixel driving circuits. The first power line VDD may be multiplexed as one or more anodes 11. At least one pixel driving circuit may include a driving transistor T3 (i.e., a third transistor T3). The second electrode 420 may be electrically connected to the first electrode of the driving transistor T3 in the corresponding pixel driving circuit through the corresponding second electrode signal line 1021.

[0216] In an exemplary embodiment, as shown in Figures 7a to 7e, at least one pixel driving circuit may further include a second transistor T2 as an initialization transistor, wherein the second terminal of the second transistor T2 is electrically connected to the first terminal of the driving transistor T3.

[0217] As shown in Figures 7c to 7e, the first terminal of the second transistor T2 can be electrically connected to the corresponding first power supply line VDD; or, as shown in Figures 7a and 7b, the driving circuit layer 102 may further include a plurality of second initial signal lines Vint2, one second initial signal line Vint2 corresponds to at least one pixel driving circuit, and the first terminal of the second transistor T2 is electrically connected to the corresponding second initial signal line Vint2.

[0218] In an exemplary embodiment, as shown in Figures 6a to 6c and 7a, the driving circuit layer 102 may further include a plurality of first power lines VDD and a plurality of second initial signal lines Vint2. The first power lines VDD correspond to one or more pixel driving circuits, and the second initial signal lines Vint2 correspond to one or more pixel driving circuits. At least one pixel driving circuit may include a driving transistor T3, a fifth transistor T5 as a light-emitting transistor, a second transistor T2 as an initialization transistor, and a seventh transistor T7 as an initialization transistor.

[0219] The second electrode 420 is electrically connected to the first electrode of the driving transistor T3 in the corresponding pixel driving circuit through the corresponding second electrode signal line 1021. The anode 11 is electrically connected to the second electrode of the fifth transistor T5 in the corresponding pixel driving circuit. The first electrode of the fifth transistor T5 is electrically connected to the corresponding first power supply line VDD.

[0220] In the same pixel driving circuit, the first terminal of the second transistor T2 is electrically connected to the corresponding second initial signal line Vint2, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the driving transistor T3; the first terminal of the seventh transistor T7 is electrically connected to the corresponding second initial signal line Vint2, and the second terminal of the seventh transistor T7 is electrically connected to the second terminal of the driving transistor T3.

[0221] The pixel driving circuit is described in detail below using Figure 7a as an example: As shown in Figure 7a, the pixel driving circuit may include seven transistors, one capacitor, a first node N1, a second node N2, a third node N3, and a fourth node N4. Specifically, the first node N1 is connected to the second terminal of the first transistor T1, the second terminal of the fourth transistor T42, the control terminal of the third transistor T3, and the first plate of the storage capacitor C. The second node N2 is connected to the first terminal of the third transistor T3, the second terminal of the fifth transistor T5, the second terminal of the second transistor T2, and the second terminal of the light-emitting device EL. The third node N3 is connected to the second terminal of the third transistor T3, the first terminal of the sixth transistor T6, the second terminal of the seventh transistor T7, and the second plate of the storage capacitor C. The fourth node N4 is connected to the anode of the light-emitting device EL and the second terminal of the fifth transistor T5.

[0222] In an exemplary embodiment, as shown in FIG7a, the first plate of the storage capacitor C is connected to the first node N1, and the second plate of the storage capacitor C is connected to the third node N3, that is, the first plate of the storage capacitor C is connected to the control electrode of the third transistor T3. The control electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first initial signal line VINIT1, and the second electrode of the first transistor is connected to the first node N1. The control electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the second transistor T2 transmits the initial voltage of the second initial signal line INIT2 to the first electrode of the third transistor T3 and the second electrode of the light-emitting device EL, so as to initialize the charge of the first electrode of the third transistor T3 and the second electrode of the light-emitting device EL. The control electrode of the third transistor T3 is connected to the first node N1, meaning the control electrode of the third transistor T3 is connected to the first plate of the storage capacitor C. The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode. The control electrode of the fourth transistor T4 is connected to the fourth scan signal line S4. The first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When a conduction level scan signal is applied to the fourth scan signal line S4, the fourth transistor T4 transmits the data signal from the data signal line D to the control electrode of the third transistor T3. The control electrode of the fifth transistor T5 is connected to the first light-emitting signal line E1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the fourth node N4. The fifth transistor T5 can be called a light-emitting transistor. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 causes the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS. The control electrode of the sixth transistor T6 is connected to the second light-emitting signal line E2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the second power supply line VSS. The sixth transistor T6 can also be called a light-emitting transistor. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the sixth transistor T6 causes the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.The control electrode of the seventh transistor T7 is connected to the third scan signal line S3, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the third node N3. When the on-level scan signal is applied to the third scan signal line S3, the seventh transistor T7 transmits the initial voltage of the second initial signal line INIT2 to the second electrode of the third transistor T3 to initialize the charge of the second electrode of the third transistor T3.

[0223] In an exemplary embodiment, as shown in FIG7a, the first electrode of the light-emitting device EL is connected to the fourth node N4, the second electrode of the light-emitting device EL is connected to the second node N2, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0224] In an exemplary embodiment, in the pixel driving circuit shown in FIG7a, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0225] Figure 7b shows an equivalent circuit diagram of another pixel driving circuit. The difference between it and Figure 7a is that the seventh transistor T7 is missing.

[0226] Figure 7c shows an equivalent circuit diagram of another pixel driving circuit. The difference from Figure 7a is that the seventh transistor T7 is missing, and the first terminal of the second transistor T2 is connected to the first power supply line VDD.

[0227] Figure 7d shows an equivalent circuit diagram of another pixel driving circuit. The difference from Figure 7a is that the fifth transistor T5 and the seventh transistor T7 are missing, and the first terminal of the second transistor T2 is connected to the first power supply line VDD.

[0228] Figure 7e shows an equivalent circuit diagram of another pixel driving circuit. The difference from Figure 7a is that the seventh transistor T7 is missing; the first terminal of the fifth transistor T5 is connected to the fourth node N4, and the second terminal of the fifth transistor T5 is connected to the second node N2; the first terminal of the light-emitting device EL is connected to the first power line VDD, and the second terminal of the light-emitting device EL is connected to the fourth node N4; the first terminal of the second transistor T2 is connected to the first power line VDD.

[0229] In an exemplary embodiment, as shown in FIG7f, which is a cross-sectional structural schematic diagram of a display substrate, the multiple transistors of the pixel driving circuit may include polysilicon transistors and oxide transistors. In the direction Z perpendicular to the plane where the display substrate is located, the driving circuit 102 may include a first insulating layer c11, a first active layer (not shown in the figure, which may be a semiconductor), a second insulating layer c12, a first gate metal layer Gate1, a third insulating layer c13, a second gate metal layer Gate2, a fourth insulating layer c14, a second active layer ATC2 (which may be IGZO), a fifth insulating layer c15, a third gate metal layer Gate3, a sixth insulating layer c16, a first source-drain metal layer SD1, a seventh insulating layer c17 (which may be called a first planarization layer PLN1), a second source-drain metal layer SD2, and an eighth insulating layer c18 (which may be called a second planarization layer PLN2) sequentially disposed on the substrate 101.

[0230] In an exemplary embodiment, the first power line VDD, the second power line VSS, and the second electrode signal line 1021 can be located in the second source / drain metal layer SD2. When the multiple transistors in the pixel driving circuit include polysilicon transistors and oxide transistors, the control electrode of the polysilicon transistor can be located in the first gate metal layer Gate1, and the active layer can be the first active layer. The control electrode of the oxide transistor can be located in the third gate metal layer Gate1, and the active layer can be located in the second active layer ATC2. The first and second electrodes of the multiple transistors can be located in the first source / drain metal layer SD1. Each of the first initial signal line INIT1, the second initial signal line INIT2, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, the first light emission signal line E1, and the second light emission signal line E2 can be located in one of the layers of the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source / drain metal layer SD1.

[0231] Figure 8 is a driving timing diagram of the pixel driving circuit shown in Figure 7a. The driving timing diagram shown in Figure 8 is illustrated using the example where the first transistor T1 to the seventh transistor T7 in Figure 7a are all oxide transistors. In an exemplary embodiment, as shown in Figure 8, the operation of the pixel driving circuit may include:

[0232] The first stage, A1, can be called the reset stage (or initialization stage). The signals of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are high-level signals, while the signals of the fourth scan signal line S4, the first light-emitting signal line E1, and the second light-emitting signal line E2 are low-level signals. The high-level signals of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 turn on the first transistor T1, the second transistor T2, and the seventh transistor T7. The signal of the first initial signal line INIT1 is written to the first node N1 (which is also the control electrode of the driving transistor T3 and the first plate of the storage capacitor C) via the first transistor T1, initializing the first node N1 (i.e., the control electrode of the driving transistor T3). The potential Vs of the first node N1 is equal to the voltage VINIT1 of the first initial signal line INIT1 (i.e., Vs = VINIT1). The signal of the second initial signal line INIT2 is written to the second node N2 via the second transistor T2, initializing the second node N2. (That is, the cathode of the light-emitting device EL, the first terminal of the driving transistor T3) is initialized. The potential Vg of the second node N2 is the voltage VINIT2 of the second initial signal line INIT2 (i.e., Vg = VINIT2). The signal of the second initial signal line INIT2 is written to the third node N3 via the seventh transistor T7 to initialize the third node N3 (that is, the second terminal of the driving transistor T3). The potential Vd of the third node N3 is VINIT2. The gate-source voltage Vgs of the third transistor T3 is VINIT2 - VINIT1, where VINIT2 - VINIT1 > |Vth|, Vth is the threshold voltage of the third transistor T3, and the storage voltage V of the storage capacitor C is V. cs =Vd-Vs=VINIT2-VINIT1. The signals of the fourth scan signal line S4, the first light-emitting signal line E1, and the second light-emitting signal line E2 are low-level signals. The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are disconnected. During this stage, the light-emitting device EL does not emit light.

[0233] The second stage, A2, can be called the threshold compensation stage. The signals of the first scan signal line S1 and the first light emission signal line E1 are high-level signals, while the signals of the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the second light emission signal line E2 are low-level signals. The signal on the first scan signal line S1 is high, turning on the first transistor T1. The signal on the first initial signal line INIT1 is written to the first node N1 (which is also the control electrode of the driving transistor T3) via the first transistor T1. The signal on the first initial signal line INIT1 is continuously written to the first node N1 (which is also the control electrode of the third transistor T3 and the first plate of the storage capacitor C). The potential of the first node N1 is Vs = VINIT1, and the third transistor T3 is turned on. The signal on the first light-emitting signal line E1 is high, turning on the fifth transistor T5. The signal on the first power supply line VDD is written to the second node N2 via the fifth transistor T5 and the light-emitting device EL. The potential of the second node N2 is ELVDD. The signal on the second node N2 charges the third node N3 until the voltage of the third node N3 is INIT1 - Vth (i.e., Vd = INIT1 - Vth, where Vth is the threshold power supply of the third transistor T3). The signals of the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the second light emission signal line E2 are low-level signals. The second transistor T2, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are disconnected. During this stage, the light emission device EL does not emit light.

[0234] The third stage, A3, can be called the data writing stage. The signals on the first scan signal line S1, the third scan signal line S3, the first light-emitting signal line E1, and the second light-emitting signal line E2 are low-level signals, while the signals on the second scan signal line S2 and the fourth scan signal line S4 are high-level signals. The low-level signals on the first scan signal line S1, the third scan signal line S3, the first light-emitting signal line E1, and the second light-emitting signal line E2 disconnect the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The signals of the second scan signal line S2 and the fourth scan signal line S4 are high-level signals, which turn on the second transistor T2 and the fourth transistor T4. The data voltage Vdata output from the data signal line D is written to the first node N1 through the turned-on fourth transistor T4. The potential of the first node N1 is Vs = Vdata. The third transistor T3 is turned on, and the signal of the second initial signal line INIT2 is written to the second node N2 through the second transistor T2. The potential of the second node N2 is Vg = VINIT2. The potential of the third node N3 is maintained at Vd = INIT1 - Vth. During this stage, the light-emitting device EL does not emit light.

[0235] The fourth stage, A4, can be called the light-emitting stage. The signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 are low-level signals, while the signals on the first light-emitting signal line E1 and the second light-emitting signal line E2 are high-level signals. The low-level signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 disconnect the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The voltage across capacitor C does not change abruptly, and the potential of the first node N1 remains Vs = Vdata. The third transistor T3 is turned on. The high-level signals on the first light-emitting signal line E1 and the second light-emitting signal line E2 turn on the fifth transistor T5 and the sixth transistor T6. The first power line VDD, the turned-on fifth transistor T5, the turned-on third transistor T3, the turned-on sixth transistor T6, and the second power line VSS form a circuit, driving the light-emitting device EL to emit light.

[0236] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and its second electrode. Since the voltage of the signal at the first node N1 satisfies Vs = Vdata, and the voltage of the signal at the third node N3 satisfies Vd = INIT1 - Vth; therefore, the driving current I of the third transistor T3 is: I = K*(Vgs - Vth). 2 =K*(Vdata-INIT1+Vth-Vth) 2 =K*(Vdata-INIT1) 2， Where I is the driving current flowing through the third transistor T3, which is also the driving current driving the light-emitting device L, K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the third transistor T3. In an exemplary embodiment, K = 1 / 2 * μ * Cox * W / L, where μ is the mobility of the third transistor, Cox is the oxide capacitance per unit area, and W / L is the aspect ratio of the channel region of the active layer of the third transistor. This disclosure provides a display substrate, as shown in Figures 6a to 6c and 6i to 6k, which may include a substrate 101 and a driving circuit layer 102, a second electrode transition layer 13, a pixel definition layer PDL, an isolation structure layer 30, a light-emitting structure layer 40, and a second electrode layer 42 sequentially disposed on one side of the substrate 101. The pixel definition layer PDL is provided with a plurality of pixel openings K11, the light-emitting structure layer 40 includes a plurality of light-emitting structures 41, and the second electrode layer 42 includes a plurality of second electrodes 420. At least one pixel opening K11 corresponds one-to-one with at least one light-emitting structure 41 and at least one second electrode 420, and at least a portion of the light-emitting structure 41 and the second electrode 420 is located in the corresponding pixel opening K11.

[0237] The partition structure layer 30 is provided with a plurality of second openings K22, at least one second opening K22 corresponds to at least one pixel opening K11, the orthographic projection of the second opening K22 on the substrate 101 at least partially overlaps with the orthographic projection of the corresponding pixel opening K11 on the substrate 101, the sidewall of the second opening K22 is provided with a second groove W2, the light-emitting structure layer 40 is broken at the second groove W2 position, and the second electrode layer 42 is broken at the second groove W2 position to form a corresponding second electrode 420;

[0238] The driving circuit layer 102 includes a plurality of second electrode signal lines 1021, and the second electrode transition layer 13 includes a plurality of second electrode transition structures 131. Each second electrode transition structure 131 corresponds one-to-one with at least one second electrode signal line 1021, at least one second electrode 420, and at least one pixel opening K11. The second electrode 420 is electrically connected to the corresponding second electrode transition structure 131, and is configured to be electrically connected to the corresponding second electrode signal line 1021 through the corresponding second electrode transition structure 131.

[0239] In an exemplary embodiment, as shown in Figures 6a to 6c, the second electrode transition structure 131 has a first groove W1 on the side near the corresponding pixel opening K11. The light-emitting structure layer 40 is disconnected at the first groove W1 to form a corresponding light-emitting structure 41. The second electrode layer 42 is electrically connected to the corresponding second electrode transition structure 131 at the first groove W1. In an exemplary embodiment, the second electrode layer 42 overlaps with the corresponding second electrode transition structure 131 at the first groove W1. In the pixel opening K11 and the second electrode transition structure 131 corresponding to the same second electrode 420, the orthographic projections of the pixel opening K11 and the second electrode transition structure 131 on the substrate 101 at least partially overlap, and the overlapping area is smaller than the non-overlapping area.

[0240] In an exemplary embodiment, the light-emitting structure layer 40 is disconnected by the first groove W1, and the second electrode layer 42 is electrically connected to the corresponding second electrode transition structure 131 at the location of the first groove W1. This allows the second electrode transition structure 131 to independently provide signals to the corresponding second electrode 420, avoiding the technical problem of poor brightness uniformity of the display substrate due to a large voltage drop at the second electrode. Disconnecting the light-emitting structure layer 40 and the second electrode layer 420 by the second groove W2 can, on the one hand, avoid crosstalk between the light-emitting structures 41 corresponding to adjacent pixel openings K11, and on the other hand, allow multiple second electrodes 420 to be controlled independently, providing flexibility in the operation of the display substrate.

[0241] In the exemplary embodiment, the structures of the second electrode transition structure 131, the pixel definition layer PDL, and the isolation structure layer 30 in Figures 6a to 6c are consistent with those described above, and will not be repeated here.

[0242] In an exemplary embodiment, as shown in Figures 6i to 6k, the second electrode transition layer 13 can be reused as an anode layer 110. The anode layer 110 may include multiple anodes 11, with at least one anode 11 corresponding to at least one second opening K22 and at least one second electrode transition structure 131. The anodes 11 and second electrode transition structures 131 corresponding to the same second opening K22 are spaced apart, and the second electrode transition structure 131 is electrically connected to the corresponding second electrode 420 through a via V11. Figure 6i is a cross-sectional view of a display substrate, Figure 6j is a planar view of the second electrode transition structure 131, pixel definition layer (PDL), and anode layer 110 in Figure 6i, and Figure 6k is a planar view of Figure 6i. In an exemplary embodiment, as shown in FIG6j, the second electrode signal line 1201 can be electrically connected to the corresponding pixel driving circuit through a via. As shown in FIG6k, the isolation structure layer 30 can be provided with a plurality of second openings K22. The orthographic projection of the second electrode 420 on the substrate can be located within the range of the orthographic projection of the corresponding second opening K22 on the substrate. Two adjacent second electrodes 420 can be separated by the isolation structure layer 30.

[0243] In an exemplary embodiment, as shown in Figures 61 to 6n, the driving circuit layer 102 may further include a plurality of pixel driving circuits and a plurality of second electrode adapter lines 14. In a direction perpendicular to the plane of the display substrate, the plurality of second electrode adapter lines 14 are located on the side of the plurality of second electrode signal lines 1201 close to the substrate. At least one pixel driving circuit corresponds one-to-one with at least one second electrode adapter structure 131 and at least one second electrode adapter line 14. The second electrode adapter structure 131 is electrically connected to the corresponding pixel driving circuit through the corresponding second electrode adapter line 14.

[0244] In an exemplary embodiment, the display substrate may include a plurality of sub-pixels, and at least one sub-pixel may include a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. The at least one light-emitting device may include an anode 11 (i.e., a second electrode 11), a light-emitting structure 41, and a cathode 420 (i.e., a second electrode 420). In an exemplary embodiment, the plurality of sub-pixels may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 may be a green sub-pixel emitting green (G) light. As shown in Figures 61 to 6n, in the first sub-pixel P1 and the third sub-pixel P3, the second electrode signal line 1201 may be electrically connected to the corresponding pixel driving circuit through a via; in the second sub-pixel P2, the second electrode signal line 1201 may be electrically connected to the second electrode adapter line 14 through a via, and the second electrode adapter line 14 may be electrically connected to the corresponding pixel driving circuit.

[0245] Taking the pixel driving circuit shown in Figure 7a as an example: In the structures shown in Figures 61 to 6n, in the same sub-pixel, the anode 11 can be electrically connected to the fourth node N4 in the corresponding pixel driving circuit through a via (for example, through a via on the planarization layer PLN); in the first sub-pixel P1 and the third sub-pixel P3, the second electrode signal line 1201 can be directly electrically connected to the second node N2 in the corresponding pixel driving circuit through a via; in the second sub-pixel P2, the second electrode signal line 1201 can be electrically connected to the second electrode adapter line 14 through a via, and the second electrode adapter line 14 can be electrically connected to the second node N2 in the corresponding pixel driving circuit through a via, that is, the second electrode signal line 1201 can be electrically connected to the second node N2 in the corresponding pixel driving circuit through the second electrode adapter line 14. In an exemplary embodiment, the second electrode signal line 1201 may be located in the second source-drain metal layer (SD2) of the driving circuit layer 102, and the second electrode adapter line 14 may be located in the first source-drain metal layer (SD1) of the driving circuit layer 102. In an exemplary embodiment, the second electrode adapter line 14 may be located in a conductive layer outside the first source-drain metal layer (SD1) and the second source-drain metal layer (SD2) of the driving circuit layer 102. In an exemplary embodiment, the first power line VDD may be a mesh structure that provides the voltage of the first power line to the fifth transistor T5. When the fifth transistor T5 is turned on, the voltage of the first power line VDD can be provided to the fourth node N4 of the pixel driving circuit.

[0246] In an exemplary embodiment, as shown in Figures 61 to 6n, at least one pixel opening K11 corresponds to at least one anode 11 and at least one second electrode adapter 14.

[0247] In an exemplary embodiment, as shown in FIG61, the second electrode adapter cable 14 may include a first structural portion 141 and a second structural portion 142. The first structural portion 141 extends along a first direction X, and the second structural portion 142 extends along a second direction Y. One end of the first structural portion 141 is electrically connected to the corresponding second electrode signal line 1201 through a via. The other end of the first structural portion 141 is connected to the second structural portion 142. One end of the second structural portion 142 is connected to the first structural portion 141, and the other end of the second structural portion 142 is electrically connected to the corresponding pixel driving circuit. The orthographic projections of the first structural portion 141 and the corresponding pixel opening K11 on the substrate do not overlap. The orthographic projections of the second structural portion 142 and the corresponding pixel opening K11 on the substrate at least partially overlap. In the first direction X, the orthographic projection of the pixel opening K11 on the substrate may be symmetrical (may be approximately symmetrical) with respect to the orthographic projection of the corresponding second structural portion 142 on the substrate. For example, the orthographic projection of the centerline of the pixel opening K11 extending along the second direction Y on the substrate may at least partially overlap with the orthographic projection of the corresponding second structural portion 142 on the substrate. In the structure shown in Figure 61, the first structural part 141 does not overlap with the pixel opening K11 and will not affect the flatness of the anode 11 in the pixel opening K11. The second structural part 142 passes through the middle of the pixel opening K11 and will also not affect the flatness of the anode.

[0248] In an exemplary embodiment, as shown in FIG6m, the second electrode adapter line 14 may include a first structural portion 141, a second structural portion 142, and a third structural portion 143. The first structural portion 141 and the third structural portion 143 extend along a first direction X, and the second structural portion 142 extends along a second direction Y. The first structural portion 141 and the third structural portion 143 are connected through the second structural portion 142. The first structural portion 141 is electrically connected to the corresponding second electrode signal line 1021 through a via. The third structural portion 143 is electrically connected to the corresponding pixel driving circuit. The orthographic projection of the second electrode adapter line 14 and the corresponding pixel opening K11 on the substrate does not overlap. The orthographic projection of the second structural portion 142 and the third structural portion 143 on the substrate at least partially overlaps with the orthographic projection of the corresponding anode. In the first direction X, the central position of the third structural portion 143 is electrically connected to the corresponding pixel driving circuit, and the size of the third structural portion 143 is not smaller than the size of the corresponding pixel opening K11. This can avoid the anode 11 being asymmetrical due to the third structural portion 143 and can improve the flatness of the anode 11.

[0249] In an exemplary embodiment, as shown in FIG6n, the second electrode adapter wire 14 may include a first structural portion 141 and a second structural portion 142. The first structural portion 141 extends along a first direction X, and the second structural portion 142 extends along a second direction Y. The first structural portion 141 and the second structural portion 142 form a "+" shaped structure. The first structural portion 141 is electrically connected to the corresponding second electrode signal line 1021 through a via, and the second structural portion 142 is electrically connected to the corresponding pixel driving circuit. In the first direction X, the orthographic projection of the pixel opening K11 on the substrate is symmetrical with respect to the orthographic projection of the corresponding second structural portion 142 on the substrate (which may be...). (Approximately symmetrical) In the second direction Y, the orthographic projection of the pixel opening K11 on the substrate is symmetrical (approximately symmetrical) with respect to the orthographic projection of the corresponding first structural part 141 on the substrate. For example, the orthographic projection of the center line of the pixel opening K11 extending along the second direction Y on the substrate can at least partially overlap with the orthographic projection of the corresponding second structural part 142 on the substrate, and the orthographic projection of the center line of the pixel opening K11 extending along the first direction X on the substrate can at least partially overlap with the orthographic projection of the corresponding first structural part 141 on the substrate, so that the anode 11 is provided with a cross-shaped support trace on the side close to the substrate, which can improve the flatness of the anode.

[0250] In the structures shown in Figures 61 to 6n, in the same row of pixel driving circuits, the points where the pixel driving circuits of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are electrically connected to their corresponding anodes 11 (the connection point of the first sub-pixel P1 is Z1, the connection point of the second sub-pixel P2 is Z2, and the connection point of the third sub-pixel P3 is Z3) can be arranged at intervals along the first direction X (for example, in the first direction X, the points where the pixel driving circuits of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are electrically connected to their corresponding anodes 11 can be located on the same straight line). In the case where the second electrode signal line 1021 in the first sub-pixel P1 and the third sub-pixel P3 can extend to the position electrically connected to the corresponding pixel driving circuit, and the second electrode signal line 1021 in the second sub-pixel P2 cannot directly extend to the position electrically connected to the corresponding pixel driving circuit (for example, avoiding other signal lines arranged in the same layer as the second electrode signal line 1021, causing the second electrode signal line 102 not to extend to the position electrically connected to the corresponding pixel driving circuit), it can be electrically connected to the corresponding pixel driving circuit through the second electrode adapter line 14.

[0251] In an exemplary embodiment, as shown in Figures 61 to 6n, multiple anodes 11 can be set independently and not connected to each other. Multiple anodes 11 can be controlled independently to achieve differentiated adjustment of each anode. The embodiments of this disclosure are not limited to this. For example, multiple anodes 11 can be connected to each other to form a grid structure.

[0252] The following description uses the fabrication process of a display substrate as an example. The terms "patterning process" and "photolithography process" used in this disclosure, for metallic, inorganic, or transparent conductive materials, include processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, they include processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. "Thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0253] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0254] (101) Form a driving circuit layer and a first electrode layer.

[0255] In an exemplary embodiment, forming the driving circuit layer and the first electrode layer may include: forming a driving circuit layer 102 on a substrate 101; depositing a first conductive film on the side of the driving circuit layer 102 away from the substrate 101; and patterning the first conductive film using a photolithography process to form a first electrode layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101. The first electrode layer 103 may include a plurality of first electrodes 11 (which may serve as anodes), as shown in FIG9a. The plurality of first electrodes 11 are spaced apart, and the driving circuit layer 102 is provided with a plurality of second electrode signal lines 1021.

[0256] In an exemplary embodiment, the first electrode 11 may be a multilayer structure of titanium (Ti), titanium nitride (TiN), aluminum (Al), titanium nitride, and indium tin oxide (ITO) stacked sequentially on the driving circuit layer 102, or the first electrode 11 may be a double-layer structure of aluminum (Al) and indium tin oxide (ITO).

[0257] (102) Form a second electrode transition layer.

[0258] In an exemplary embodiment, forming the second electrode transition layer may include: as shown in Figures 9a to 9d, depositing a first insulator layer 1301 on the substrate on which the aforementioned pattern is formed; patterning the first insulator layer 1301 using photolithography to form a plurality of first electrode vias Vm1; sequentially depositing a second electrode transition layer 1302 and a second insulator layer 1303 on the side of the first insulator layer 1301 away from the substrate 101; and patterning the first insulator layer 1301, the second electrode transition layer 1302, and the second insulator layer 1303 using photolithography to make the first insulator layer 1301... 301. A plurality of first insulator structures 1311 are formed on the side of the first electrode 11 away from the substrate 101. A plurality of second electrode transition sub-structures 1310 are formed on the side of the first insulator structure 1311 away from the substrate 101. A plurality of second insulator structures 1312 are formed on the side of the second electrode transition sub-structures 1310 away from the substrate 101. The second electrode transition sub-structures 1310 can be electrically connected to the corresponding second electrode signal line 1021 in the driving circuit layer 102 through the corresponding first electrode via Vm1. Figures 9c and 9d show schematic diagrams of the two planar structures in Figure 9b. The second electrode transition structure 131 is provided with a first opening K21. A first groove W1 is formed on the side of the first insulator structure 1311, the second insulator structure 1312, and the second electrode transition structure 1310 near the first opening K21. The first groove W1 constitutes an undercut structure, which can block the light-emitting structure layer formed subsequently. In an exemplary embodiment, the first groove W1 can be formed by controlling the etching rate of the first insulator layer 1301, the second electrode transition layer 1302, and the second insulator layer 1303.

[0259] (103) Form a pixel definition layer.

[0260] In an exemplary embodiment, forming a pixel definition layer may include: as shown in FIG9e, depositing a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film by photolithography, so that the pixel definition film forms a first pixel definition layer PDL disposed on the second electrode transition structure 131 away from the substrate 101; in an exemplary embodiment, as shown in FIG9e, the pixel definition layer PDL is provided with a plurality of pixel openings K11, as shown in FIG9f, which is a schematic diagram of a planar structure of FIG9e.

[0261] In an exemplary embodiment, the pixel definition layer (PDL) may include inorganic materials. For example, the material of the pixel definition layer (PD) may include at least one of silicon oxide (SiOx) and silicon nitride (SiNx).

[0262] (104) Forming a partition structure layer.

[0263] In an exemplary embodiment, forming the partition structure layer may include: as shown in FIG9g, on the substrate on which the aforementioned pattern is formed, a first partition structure film and a second partition structure film are sequentially deposited on the side of the pixel definition layer PDL away from the substrate 101; the first partition structure film and the second partition structure film are patterned by photolithography, so that the first partition structure film forms a plurality of first partition structures 31 disposed on the side of the pixel definition layer PDL away from the substrate 101, and the second partition structure film forms a second partition structure 32 disposed on the side of the first partition structure 31 away from the substrate 101, thereby forming a partition structure layer 30, which includes the first partition structure 31 and the second partition structure 32. In an exemplary embodiment, the partition structure layer 30 is provided with a plurality of second openings K22. The plurality of second openings K22 may correspond one-to-one with a plurality of pixel openings K11 and a plurality of first openings K21, and the orthographic projections of the second openings K22 and the corresponding pixel openings K11 and first openings K21 on the substrate 101 at least partially overlap.

[0264] In an exemplary embodiment, the first partition structure 31 and the second partition structure 32 may include inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). In an exemplary embodiment, the material of the first partition structure 31 may be silicon nitride (SiNx), and the material of the second partition structure 32 may be (SiOx). In an exemplary embodiment, different gases may be used to etch the first partition structure film and the second partition structure film; alternatively, the same gas may be used to etch the first partition structure film and the second partition structure film. In an exemplary embodiment, under the same etching conditions, the etching rate of silicon nitride (SiNx) is faster than that of silicon oxide (SiOx), resulting in the formation of a larger first isolation structure film compared to the second isolation structure film, as shown in Figure 9g. This causes the first isolation structure 31 to be recessed relative to the second isolation structure 32. The second isolation structure 32, the first isolation structure 31, and the pixel definition layer (PDL) form an I-shaped structure. A second groove W2 is formed between the second isolation structure 32, the first isolation structure 31, and the PDL, constituting an undercut structure. This undercut structure can isolate the subsequently formed light-emitting structure layer material and the second electrode material. During the etching process, because the first isolation structure film is shielded by the second isolation structure film on the side furthest from the substrate, the first isolation structure 32 formed after etching can be approximately a "T"-shaped structure or an inverted trapezoidal structure. The "T"-shaped first isolation structure 31 can provide good support for the second isolation structure 32.

[0265] (105) Forming a light-emitting structure layer, a second electrode and an encapsulation layer.

[0266] In an exemplary embodiment, forming the light-emitting structure layer, the second electrode, and the encapsulation layer may include: on the substrate on which the aforementioned pattern is formed, by a coating process, such as a thermal evaporation coating process, sequentially depositing a light-emitting structure layer material, a second electrode material, and a first encapsulation layer material on the side of the isolation structure layer 30 and the first electrode 11 away from the substrate 101, with at least a portion of the light-emitting structure layer material disposed on the surface of the first electrode 11 away from the substrate to form a light-emitting structure layer 40, with at least a portion of the second electrode material disposed on the surface of the light-emitting structure layer 40 away from the substrate to form a second electrode layer 42, and with the first encapsulation layer material disposed on the surface of the second electrode layer 42 away from the substrate to form a first encapsulation layer 431. As shown in Figures 9h to 9j, the light-emitting structure layer material, the second electrode material, and the first encapsulation layer material of the first sub-pixel R can be deposited first, and then the light-emitting structure layer material, the second electrode material, and the first encapsulation layer material of the first sub-pixel R can be deposited by a photolithography process. The light-emitting structure layer material, second electrode material, and first encapsulation layer material of the first sub-pixel R at the positions of the second sub-pixel G and the third sub-pixel B are removed to form the structure shown in Figure 9h. Then, the light-emitting structure layer material, second electrode material, and first encapsulation layer material of the second sub-pixel G are deposited, and the light-emitting structure layer material, second electrode material, and first encapsulation layer material of the second sub-pixel G at the positions of the first sub-pixel R and the third sub-pixel B are removed by photolithography to form the structure shown in Figure 9i. Then, the light-emitting structure layer material, second electrode material, and first encapsulation layer material of the third sub-pixel B are deposited, and the light-emitting structure layer material, second electrode material, and first encapsulation layer material of the third sub-pixel B at the positions of the first sub-pixel R and the second sub-pixel G are removed by photolithography to form the structure shown in Figure 9j. Then, the second encapsulation layer 432 is deposited to obtain the structure shown in Figure 9k. Among them, the first electrode 11, the light-emitting structure 41, and the second electrode 420 form the light-emitting device of the sub-pixel. The light-emitting structure layer 40 includes a plurality of spaced light-emitting structures 41, and the light-emitting structures 41 can be located in the pixel opening K11.

[0267] In an exemplary embodiment, the orthographic projections of the light-emitting structure layer 40 and the first electrode 11 on the substrate overlap, and the light-emitting structure layer 40 and the first electrode 11 can be in direct contact. Similarly, the orthographic projections of the second electrode 42 and the light-emitting structure layer 40 on the substrate overlap, and the light-emitting structure layer 40 and the second electrode 42 can be in direct contact.

[0268] In an exemplary embodiment, the light-emitting structure layer 40 may include at least one light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), an electron injection layer (EIL), and a charge generation layer (CGL).

[0269] In an exemplary embodiment, the second electrode 420 can be a single-layer structure or a multi-layer structure. For example, the second electrode 420 is a single-layer structure and can include a metal or alloy, such as aluminum, titanium, molybdenum, aluminum-neodymium alloy, copper, or other highly conductive metals. Alternatively, the second electrode 420 can be a multi-layer structure; for example, the second electrode 420 can include a first thin film, a second thin film, and a third thin film sequentially disposed therefrom. The first and third thin films can both include titanium, and the second thin film can include one of aluminum, copper, or molybdenum.

[0270] In an exemplary embodiment, as shown in Figures 9j and 9k, the undercut structure formed by the second groove W2 isolates the light-emitting structure layer 40 and the second electrode 420, effectively isolating leakage current and solving the problem of crosstalk between adjacent sub-pixels to a certain extent; the undercut structure formed by the first groove W1 isolates the light-emitting layer 40, so that the second electrode 420 can be electrically connected to the corresponding second electrode adapter substructure 1310.

[0271] In an exemplary embodiment, the first encapsulation layer 431 is a pixel-level encapsulation, encapsulating each sub-pixel individually, while the second encapsulation layer 432 encapsulates the entire display substrate.

[0272] This disclosure provides a display substrate that may include multiple sub-pixels. At least one sub-pixel includes a light-emitting device and a pixel driving circuit for driving the light-emitting device. As shown in FIG10, at least one pixel driving circuit includes a first reset sub-circuit, a second reset sub-circuit, a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, and a storage sub-circuit.

[0273] The first reset sub-circuit is electrically connected to the first scan signal line, the first node, and the first initial signal line, respectively, and is configured to write the signal of the first initial signal line into the first node under the control of the first scan signal line;

[0274] The second reset sub-circuit is electrically connected to the second scan signal line and the second node, and is also electrically connected to the second initial signal line or the first power line. It is configured to write the signal of the second initial signal line or the signal of the first power line into the first node under the control of the second scan signal line.

[0275] The driving sub-circuit is electrically connected to the first node, the second node, and the third node, respectively, and is configured to control the potential of the third node according to the signals of the first node and the second node;

[0276] The data writing sub-circuit is connected to the fourth scan signal line, the data signal line and the first node, respectively, and is configured to write the signal of the data signal line into the first node under the control of the fourth scan signal line.

[0277] The first light-emitting control sub-circuit is electrically connected to the third node, the second light-emitting signal line, and the second power line, respectively, and is configured to form a loop between the third node and the second power line under the control of the second light-emitting signal line;

[0278] The storage sub-circuit is electrically connected to the first node and the third node respectively, and is configured to store charge under the control of the first node and the third node;

[0279] The light-emitting device is electrically connected to the first power line and the second node respectively, and is configured to emit light under the control of the pixel driving circuit.

[0280] In an exemplary embodiment, as shown in FIG7d, the first reset sub-circuit may include a first transistor T1, the first terminal of the first transistor T1 being connected to the first initial signal line INIT1, the second terminal of the first transistor T1 being connected to the first node N1, and the control terminal of the first transistor T1 being connected to the first scan signal line S1; the second reset sub-circuit may include a second transistor T2, the first terminal of the second transistor T2 being connected to the first power supply line VDD, the second terminal of the second transistor T2 being connected to the second node N2, and the control terminal of the second transistor T2 being connected to the second scan signal line S2; the driving sub-circuit may include a third transistor T3, the first terminal of the third transistor T3 being connected to the second node N2, the second terminal of the third transistor T3 being connected to the third node N3, and the control terminal of the third transistor T3 being connected to the first node N1. The data writing sub-circuit may include a fourth transistor T4, the first terminal of which is connected to the data signal line D, the second terminal of which is connected to the first node N1, and the control terminal of which is connected to the fourth scan signal line S4; the first light-emitting control sub-circuit may include a sixth transistor T6, the first terminal of which is connected to the third node N3, the second terminal of which is connected to the second power supply line VSS, and the control terminal of which is connected to the second light-emitting signal line E2; the storage sub-circuit may include a storage capacitor C, the first plate of which is connected to the first node N1, and the second plate of which is connected to the third node N3; the first terminal of the light-emitting device EL is connected to the first power supply line VDD, and the second terminal of the light-emitting device EL is electrically connected to the second node N2.

[0281] In an exemplary embodiment, as shown in Figures 7a and 7b, the first terminal of the second transistor T2 can be connected to the second initial signal line INIT2.

[0282] In an exemplary embodiment, the pixel driving circuit may further include a second light emission control sub-circuit;

[0283] As shown in Figures 7a to 7c, the second light-emitting control sub-circuit is electrically connected to the fourth node N4, the first light-emitting signal line E1, and the first power line VDD, respectively. It is configured to provide the signal of the first power line VDD to the fourth node N4 under the control of the first light-emitting signal line E1. The light-emitting device EL is electrically connected to the first power line VDD through the second light-emitting control sub-circuit.

[0284] Alternatively, as shown in Figure 7e, the second light-emitting control sub-circuit is electrically connected to the fourth node N4, the first light-emitting signal line E1, and the second node N2, respectively. It is configured to provide the signal of the fourth node N4 to the second node N2 under the control of the first light-emitting signal line E1, and the light-emitting device EL is electrically connected to the second node N2 through the second light-emitting control sub-circuit.

[0285] In an exemplary embodiment, as shown in Figures 7a to 7c and 7e, the second light-emitting control sub-circuit may include a fifth transistor T5. As shown in Figures 7a to 7c, the first terminal of the fifth transistor T5 is connected to the first power supply line VDD, the second terminal of the fifth transistor T5 is connected to the fourth node N4, the control terminal of the fifth transistor T5 is connected to the first light-emitting signal line E1, and the first terminal of the light-emitting device EL is electrically connected to the first power supply line VDD through the second light-emitting control sub-circuit; or, as shown in Figure 7e, the first terminal of the fifth transistor T5 is connected to the fourth node N4, the second terminal of the fifth transistor T5 is connected to the second node N2, the control terminal of the fifth transistor T5 is connected to the first light-emitting signal line E1, and the light-emitting device EL is electrically connected to the second node N2 through the second light-emitting control sub-circuit.

[0286] In an exemplary embodiment, the pixel driving circuit may further include a third reset circuit;

[0287] The third reset circuit is electrically connected to the third scan signal line S3, the third node N3, and the second initial signal line INIT2, respectively, and is configured to write the signal of the second initial signal line INIT2 into the third node N3 under the control of the third scan signal line S3.

[0288] In an exemplary embodiment, as shown in FIG7a, the third reset sub-circuit may include a seventh transistor T7, the first terminal of the seventh transistor T7 being connected to the second initial signal line INIT2, the second terminal of the seventh transistor T7 being connected to the third node N3, and the control terminal of the seventh transistor T7 being connected to the third scan signal line S3.

[0289] This disclosure provides a method for preparing a display substrate, which may include:

[0290] A driving circuit layer, a second electrode transition layer, and a pixel definition layer are sequentially formed on one side of the substrate. The driving circuit layer includes multiple second electrode signal lines, the second electrode transition layer includes multiple second electrode transition structures, the pixel definition layer is provided with multiple pixel openings, at least one second electrode transition structure is provided with a first opening, at least one first opening corresponds one-to-one with at least one pixel opening, the orthographic projection of the first opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap, and the sidewall of the first opening is provided with a first groove.

[0291] A light-emitting structure layer is formed on the side of the pixel definition layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, at least one of which corresponds to at least one pixel opening. At least a portion of the light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the first groove position to form the corresponding light-emitting structure.

[0292] A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer includes a plurality of second electrodes. At least one pixel opening corresponds to at least one second electrode. At least a portion of the second electrode is located in the corresponding pixel opening. At least one second electrode adapter structure corresponds to at least one second electrode signal line and at least one second electrode. The second electrode layer is electrically connected to the corresponding second electrode signal line at the first groove position. The second electrode is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode adapter structure.

[0293] This disclosure provides a method for preparing a display substrate, which may include:

[0294] A driving circuit layer, a second electrode transition layer, and a pixel definition layer are sequentially formed on one side of the substrate. The driving circuit layer includes multiple second electrode signal lines, the second electrode transition layer includes multiple second electrode transition structures, and the pixel definition layer is provided with multiple pixel openings.

[0295] A partition structure layer is formed on the side of the pixel definition layer away from the substrate. The partition structure layer is provided with a plurality of second openings. At least one second opening corresponds to at least one pixel opening. The orthographic projection of the second opening on the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening on the substrate. The sidewall of the second opening is provided with a second groove.

[0296] A light-emitting structure layer is formed on the side of the partition structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, at least one of which corresponds to at least one pixel opening. At least a portion of the light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the second groove position.

[0297] A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer includes a plurality of second electrodes. One second electrode transition structure corresponds one-to-one with at least one second electrode signal line, at least one second electrode, and at least one pixel opening. At least a portion of the second electrode is located in the corresponding pixel opening. The second electrode layer is disconnected at the second groove position to form a corresponding second electrode. The second electrode is electrically connected to the corresponding second electrode transition structure and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure.

[0298] This disclosure provides a display device, as shown in FIG11. The display device may include the aforementioned display substrate. The display device may be any product or component with display function, such as a mobile phone, wearable device, AR or VR display device, in-vehicle display device, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc., and the embodiments of the present invention are not limited thereto.

[0299] The display substrate and its fabrication method and display device provided in this disclosure include a substrate and a driving circuit layer, a second electrode transition layer, a pixel definition layer, a light-emitting structure layer and a second electrode layer sequentially disposed on one side of the substrate. The driving circuit layer includes a plurality of second electrode signal lines, the second electrode transition layer includes a plurality of second electrode transition structures, the pixel definition layer has a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds one-to-one with at least one light-emitting structure and at least one second electrode, at least a portion of the light-emitting structure and the second electrode is located in the corresponding pixel opening, at least one second electrode signal line corresponds one-to-one with at least one second electrode transition structure and at least one second electrode, the second electrode is electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure, the sidewall of the first opening is provided with a first groove, the light-emitting structure layer is disconnected at the first groove position to form the corresponding light-emitting structure, and the second electrode layer is electrically connected to the corresponding second electrode transition structure at the first groove position. The technical solution provided in this disclosure embodiment is that the second electrode is electrically connected to the corresponding second electrode signal line through the corresponding second electrode adapter structure. That is, the signal of the second electrode can be provided by the corresponding second electrode signal line located in the driving circuit layer. This can avoid the problem of large voltage drop when multiple light-emitting structures share a second electrode layer, thereby avoiding the technical problem of poor brightness uniformity of the display substrate due to large voltage drop of the second electrode, and greatly improving the display uniformity of the display substrate.

[0300] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a substrate and a driving circuit layer, a second electrode transition layer, a pixel definition layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer has a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds one-to-one with at least one light-emitting structure and at least one second electrode, and at least a portion of the light-emitting structure and the second electrode is located in the corresponding pixel opening; The driving circuit layer includes multiple second electrode signal lines, and the second electrode transition layer includes multiple second electrode transition structures. Each second electrode transition structure corresponds one-to-one with at least one second electrode signal line and at least one second electrode. The second electrode is electrically connected to the corresponding second electrode transition structure, and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure. At least one second electrode adapter structure is provided with a first opening, and at least one first opening corresponds one-to-one with at least one pixel opening. The orthographic projection of the first opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the first opening is provided with a first groove. The light-emitting structure layer is disconnected at the first groove position to form a corresponding light-emitting structure. The second electrode layer is electrically connected to the corresponding second electrode adapter structure at the first groove position. 2.The display substrate of claim 1, wherein, The second electrode layer is connected to the corresponding second electrode transition structure at the disconnected position.

3. The display substrate according to claim 1 further includes a partition structure layer, wherein the partition structure layer is located between the pixel definition layer and the light-emitting structure layer in a direction perpendicular to the plane of the substrate; The partition structure layer is provided with a plurality of second openings, at least one of which corresponds to at least one pixel opening. The orthographic projection of the second opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the second opening is provided with a second groove. The light-emitting structure layer and the second electrode layer are disconnected at the position of the second groove. The second electrode layer is broken at the second groove position to form a corresponding second electrode, or the second electrode layer is broken at the first groove position to form a corresponding second electrode. 4.The display substrate of claim 3, wherein, The orthographic projection of the first opening on the substrate is within the range of the orthographic projection of the corresponding pixel opening on the substrate, and the orthographic projection of the pixel opening on the substrate is within the range of the orthographic projection of the corresponding second opening on the substrate.

5. The display substrate according to claim 3 further includes an anode layer, wherein the anode layer is located between the driving circuit layer and the second electrode transition layer in a direction perpendicular to the plane of the display substrate, the anode layer includes a plurality of anodes, at least one anode corresponds one-to-one with at least one pixel opening and at least one second electrode transition structure; the second electrode transition structure includes a first insulator structure and a second electrode transition substructure sequentially disposed on the side of the anode layer away from the substrate, and the second electrode is overlapped and connected to the corresponding second electrode transition substructure; In the anode and second electrode transition structure corresponding to the same pixel opening, the first insulator structure is configured to insulate the second electrode transition structure from the anode, and the overlapping area of ​​the first insulator structure and the anode projected onto the substrate covers the overlapping area of ​​the second electrode transition structure and the anode projected onto the substrate. 6.The display substrate of claim 5, wherein, The second electrode transition structure further includes a second insulator structure, which is located between the second electrode transition substructure and the pixel definition layer in a direction perpendicular to the plane of the display substrate. In the second electrode adapter structure, the first groove is formed on the side of the first insulator structure away from the substrate, the sidewall of the second electrode adapter structure, and the side of the second insulator structure near the substrate. 7.The display substrate of claim 5, wherein, In the second electrode transition structure, on the side near the first opening, a portion of the surface of the first insulator structure away from the substrate, the sidewall of the second electrode transition structure, and a portion of the pixel definition layer near the substrate form the first groove. In the anode and second electrode transition structure corresponding to the same pixel opening, the overlapping area of ​​the pixel definition layer corresponding to the pixel opening and the orthographic projection of the anode on the substrate covers the overlapping area of ​​the second electrode transition substructure and the orthographic projection of the anode on the substrate. 8.The display substrate according to claim 6 or 7, wherein On a plane parallel to the base, in the direction from the second groove to the corresponding second opening, the ratio of the size of the second groove to the size of the first groove is greater than or equal to 2:

1. 9.The display substrate according to claim 6 or 7, wherein In a direction perpendicular to the plane of the base, the ratio of the size of the second groove to the size of the first groove is greater than or equal to 5:

1. 10.The display substrate of claim 6, wherein, In a direction perpendicular to the plane of the substrate, the thickness of the second insulator structure is greater than half the thickness of the light-emitting structure layer. 11.The display substrate according to claim 6 or 7, wherein In a direction perpendicular to the plane of the substrate, the thickness of the second electrode adapter structure is greater than half the thickness of the light-emitting structure layer. 12.The display substrate according to any one of claims 3 to 7, wherein In a direction perpendicular to the plane of the substrate, the partition structure layer includes a first partition structure layer and a second partition structure layer stacked sequentially on the side of the pixel definition layer away from the substrate. The surface of the first partition structure layer near any of the second openings is recessed into the surface of the second partition structure layer near the same second opening, forming the second groove. 13.The display substrate of claim 12, wherein, In a direction perpendicular to the plane of the substrate, the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the second partition structure layer, and the thickness of the first partition structure layer is 1.5 to 3 times the thickness of the pixel definition layer. 14.The display substrate of claim 12, wherein, The cross-sectional structure of the first partition structure layer between two adjacent second openings is a "T" shaped structure. 15.The display substrate of claim 12, wherein, The cross-sectional structure of the partition structure layer and pixel definition layer between two adjacent second openings is an "I" shaped structure; the cross-sectional structure of the partition structure layer between two adjacent second openings is a "T" shaped structure. 16.The display substrate of claim 5, wherein, The light-emitting structure, the corresponding anode, and the corresponding second electrode constitute a light-emitting device. The driving circuit layer includes multiple pixel driving circuits, at least one pixel driving circuit corresponds to at least one light-emitting device, and the pixel driving circuit is electrically connected to the anode and the second electrode in the corresponding light-emitting device, and is configured to drive the corresponding light-emitting device to emit light.

17. The display substrate according to claim 16 further includes a plurality of first power lines, each first power line corresponding to one or more pixel driving circuits, wherein at least one pixel driving circuit includes a driving transistor and a fifth transistor as a light-emitting transistor. The first power line is located in the driving circuit layer. The second electrode is electrically connected to the first electrode of the driving transistor in the corresponding pixel driving circuit through a corresponding second electrode signal line. The anode is electrically connected to the second electrode of the fifth transistor in the corresponding pixel driving circuit. The first electrode of the fifth transistor is electrically connected to the corresponding first power line. Alternatively, the first power line is located in the anode layer. The second electrode is electrically connected to the first electrode of the fifth transistor in the corresponding pixel driving circuit through a corresponding second electrode signal line. The second electrode of the fifth transistor is electrically connected to the first electrode of the corresponding driving transistor. The first power line is multiplexed as one or more anodes. 18.The display substrate of claim 16, wherein, The anode layer further includes a plurality of first power lines, each first power line corresponding to one or more pixel driving circuits. The first power line is multiplexed as one or more anodes. At least one pixel driving circuit includes a driving transistor. The second electrode is electrically connected to the first electrode of the driving transistor in the corresponding pixel driving circuit through a corresponding second electrode signal line.

19. The display substrate of claim 17 or 18, wherein, At least one pixel driving circuit also includes a second transistor as an initialization transistor, the second terminal of the second transistor being electrically connected to the first terminal of the driving transistor; The first electrode of the second transistor is electrically connected to the corresponding first power supply line; or the driving circuit layer further includes a plurality of second initial signal lines, one second initial signal line corresponding to at least one pixel driving circuit, and the first electrode of the second transistor is electrically connected to the corresponding second initial signal line. 20.The display substrate of claim 16, wherein, The driving circuit layer further includes a plurality of first power lines and a plurality of second initial signal lines. The first power lines correspond to one or more pixel driving circuits, and one second initial signal line corresponds to one or more pixel driving circuits. At least one pixel driving circuit includes a driving transistor, a fifth transistor as a light-emitting transistor, a second transistor as an initialization transistor, and a seventh transistor as an initialization transistor. The second electrode is electrically connected to the first electrode of the driving transistor in the corresponding pixel driving circuit through the corresponding second electrode signal line. The anode is electrically connected to the second electrode of the fifth transistor in the corresponding pixel driving circuit. The first electrode of the fifth transistor is electrically connected to the corresponding first power supply line. In the same pixel driving circuit, the first terminal of the second transistor is electrically connected to the corresponding second initial signal line, and the second terminal of the second transistor is electrically connected to the first terminal of the driving transistor; the first terminal of the seventh transistor is electrically connected to the corresponding second initial signal line, and the second terminal of the seventh transistor is electrically connected to the second terminal of the driving transistor. 21.The display substrate of claim 16, wherein, The pixel driving circuit includes a plurality of transistors, wherein the second electrode signal line is electrically connected to at least one electrode of at least one transistor, or at least one electrode of at least one transistor is multiplexed as the second electrode signal line.

22. A display substrate, comprising a substrate and a driving circuit layer, a second electrode transition layer, a pixel definition layer, a partition structure layer, a light-emitting structure layer, and a second electrode layer sequentially disposed on one side of the substrate; the pixel definition layer has a plurality of pixel openings, the light-emitting structure layer includes a plurality of light-emitting structures, the second electrode layer includes a plurality of second electrodes, at least one pixel opening corresponds one-to-one with at least one light-emitting structure and at least one second electrode, and at least a portion of the light-emitting structure and the second electrode is located in the corresponding pixel opening; The partition structure layer is provided with a plurality of second openings, at least one of which corresponds to at least one pixel opening. The orthographic projection of the second opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap. The sidewall of the second opening is provided with a second groove. The light-emitting structure layer is broken at the position of the second groove. The second electrode layer is broken at the position of the second groove to form a corresponding second electrode. The driving circuit layer includes multiple second electrode signal lines, and the second electrode transition layer includes multiple second electrode transition structures. Each second electrode transition structure corresponds one-to-one with at least one second electrode signal line, at least one second electrode, and at least one pixel opening. The second electrode is electrically connected to the corresponding second electrode transition structure, and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode transition structure.

23. The display substrate of claim 22, wherein, The second electrode adapter structure has a first groove on the side near the corresponding pixel opening. The light-emitting structure layer is disconnected at the first groove position to form a corresponding light-emitting structure. The second electrode layer is electrically connected to the corresponding second electrode adapter structure at the first groove position.

24. The display substrate of claim 22, wherein, The second electrode transition layer is reused as an anode layer. The anode layer includes multiple anodes. At least one anode corresponds one-to-one with at least one second opening and at least one second electrode transition structure. Anodes and second electrode transition structures corresponding to the same second opening are spaced apart. The second electrode transition structure is electrically connected to the corresponding second electrode through a via. 25.The display substrate of claim 24, wherein, The driving circuit layer also includes multiple pixel driving circuits and multiple second electrode adapter lines. In a direction perpendicular to the plane where the display substrate is located, the multiple second electrode adapter lines are located on the side of the multiple second electrode signal lines closer to the substrate. At least one pixel driving circuit corresponds one-to-one with at least one second electrode adapter structure and at least one second electrode adapter wire. The second electrode adapter structure is electrically connected to the corresponding pixel driving circuit through the corresponding second electrode adapter wire.

26. The display substrate of claim 25, wherein, At least one pixel opening corresponds one-to-one with at least one anode and at least one second electrode adapter wire; The second electrode adapter cable includes a first structural portion and a second structural portion. The first structural portion extends along a first direction, and the second structural portion extends along a second direction. One end of the first structural portion is electrically connected to a corresponding second electrode signal line through a via, and the other end of the first structural portion is connected to the second structural portion. One end of the second structural portion is connected to the first structural portion, and the other end of the second structural portion is electrically connected to a corresponding pixel driving circuit. The orthographic projections of the first structural portion and the corresponding pixel opening on the substrate do not overlap, while the orthographic projections of the second structural portion and the corresponding pixel opening on the substrate at least partially overlap. In the first direction, the pixel opening on the substrate... The orthographic projection is symmetrical with respect to the orthographic projection of the corresponding second structural part on the substrate; Alternatively, the second electrode adapter cable includes a first structural portion, a second structural portion, and a third structural portion. The first structural portion and the third structural portion extend along a first direction, and the second structural portion extends along a second direction. The first structural portion and the third structural portion are connected through the second structural portion. The first structural portion is electrically connected to the corresponding second electrode signal line through a via. The third structural portion is electrically connected to the corresponding pixel driving circuit. The orthographic projection of the second electrode adapter cable and the corresponding pixel opening on the substrate does not overlap. The orthographic projection of the second structural portion and the third structural portion on the substrate at least partially overlaps with the orthographic projection of the corresponding anode on the substrate. In the first direction, the central position of the third structural portion is electrically connected to the corresponding pixel driving circuit. Alternatively, the second electrode adapter cable includes a first structural portion and a second structural portion. The first structural portion extends along a first direction, and the second structural portion extends along a second direction. The first structural portion and the second structural portion form a cross-shaped structure. The first structural portion is electrically connected to the corresponding second electrode signal line through a via, and the second structural portion is electrically connected to the corresponding pixel driving circuit. In the first direction, the orthographic projection of the pixel opening on the substrate is symmetrical with respect to the orthographic projection of the corresponding second structural portion on the substrate. In the second direction, the orthographic projection of the pixel opening on the substrate is symmetrical with respect to the orthographic projection of the corresponding first structural portion on the substrate.

27. A display substrate comprising a plurality of sub-pixels, at least one sub-pixel comprising a light-emitting device and a pixel driving circuit for driving the light-emitting device, wherein at least one pixel driving circuit comprises a first reset sub-circuit, a second reset sub-circuit, a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, and a storage sub-circuit. The first reset sub-circuit is electrically connected to the first scan signal line, the first node, and the first initial signal line, respectively, and is configured to write the signal of the first initial signal line into the first node under the control of the first scan signal line; The second reset sub-circuit is electrically connected to the second scan signal line and the second node, and is also electrically connected to the second initial signal line or the first power line. It is configured to write the signal of the second initial signal line or the signal of the first power line into the first node under the control of the second scan signal line. The driving sub-circuit is electrically connected to the first node, the second node, and the third node, respectively, and is configured to control the potential of the third node according to the signals of the first node and the second node; The data writing sub-circuit is connected to the fourth scan signal line, the data signal line and the first node, respectively, and is configured to write the signal of the data signal line into the first node under the control of the fourth scan signal line. The first light-emitting control sub-circuit is electrically connected to the third node, the second light-emitting signal line, and the second power line, respectively, and is configured to form a loop between the third node and the second power line under the control of the second light-emitting signal line; The storage sub-circuit is electrically connected to the first node and the third node respectively, and is configured to store charge under the control of the first node and the third node; The light-emitting device is electrically connected to the first power line and the second node respectively, and is configured to emit light under the control of the pixel driving circuit. 28.The display substrate of claim 27, wherein, The pixel driving circuit also includes a second light-emitting control sub-circuit; The second light-emitting control sub-circuit is electrically connected to the fourth node, the first light-emitting signal line, and the first power line, respectively. It is configured to provide the signal of the first power line to the fourth node under the control of the first light-emitting signal line. The light-emitting device is electrically connected to the first power line through the second light-emitting control sub-circuit. Alternatively, the second light-emitting control sub-circuit is electrically connected to the fourth node, the first light-emitting signal line, and the second node, respectively, and is configured to provide the signal of the fourth node to the second node under the control of the first light-emitting signal line, and the light-emitting device is electrically connected to the second node through the second light-emitting control sub-circuit. 29.The display substrate according to claim 27 or 28, wherein, The pixel driving circuit also includes a third reset sub-circuit; The third reset circuit is electrically connected to the third scan signal line, the third node, and the second initial signal line, respectively, and is configured to write the signal of the second initial signal line into the third node under the control of the third scan signal line.

30. A display device comprising a display substrate as claimed in any one of claims 1 to 21, or a display substrate as claimed in any one of claims 22 to 26, or a display substrate as claimed in any one of claims 27 to 29.

31. A method for preparing a display substrate, comprising: A driving circuit layer, a second electrode transition layer, and a pixel definition layer are sequentially formed on one side of the substrate. The driving circuit layer includes multiple second electrode signal lines, the second electrode transition layer includes multiple second electrode transition structures, the pixel definition layer is provided with multiple pixel openings, at least one second electrode transition structure is provided with a first opening, at least one first opening corresponds one-to-one with at least one pixel opening, the orthographic projection of the first opening on the substrate and the orthographic projection of the corresponding pixel opening on the substrate at least partially overlap, and the sidewall of the first opening is provided with a first groove. A light-emitting structure layer is formed on the side of the pixel definition layer away from the substrate, the light-emitting structure layer comprising a plurality of light-emitting... The light structure has at least one light-emitting structure corresponding to at least one pixel opening, with at least a portion of the light-emitting structure located in the corresponding pixel opening, and the light-emitting structure layer is broken at the first groove position to form the corresponding light-emitting structure. A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer includes a plurality of second electrodes, and at least one pixel opening corresponds one-to-one with at least one second electrode. At least a portion of the second electrode is located in the corresponding pixel opening. At least one second electrode adapter structure corresponds one-to-one with at least one second electrode signal line and at least one second electrode. The second electrode layer is electrically connected to the corresponding second electrode signal line at the first groove position. The second electrode is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode adapter structure.

32. A method for preparing a display substrate, comprising: A driving circuit layer, a second electrode transition layer, and a pixel definition layer are sequentially formed on one side of the substrate. The driving circuit layer includes multiple second electrode signal lines, the second electrode transition layer includes multiple second electrode transition structures, and the pixel definition layer is provided with multiple pixel openings. A partition structure layer is formed on the side of the pixel definition layer away from the substrate. The partition structure layer is provided with a plurality of second openings. At least one second opening corresponds to at least one pixel opening. The orthographic projection of the second opening on the substrate at least partially overlaps with the orthographic projection of the corresponding pixel opening on the substrate. The sidewall of the second opening is provided with a second groove. A light-emitting structure layer is formed on the side of the partition structure layer away from the substrate. The light-emitting structure layer includes a plurality of light-emitting structures, at least one of which corresponds to at least one pixel opening. At least a portion of the light-emitting structure is located in the corresponding pixel opening. The light-emitting structure layer is broken at the second groove position. A second electrode layer is formed on the side of the light-emitting structure layer away from the substrate. The second electrode layer includes a plurality of second electrodes, and one second electrode adapter structure corresponds one-to-one with at least one second electrode signal line, at least one second electrode, and at least one pixel opening. At least a portion of the second electrode is located in the corresponding pixel opening. The second electrode layer is disconnected at the second groove position to form a corresponding second electrode. The second electrode is electrically connected to the corresponding second electrode adapter structure, and is configured to be electrically connected to the corresponding second electrode signal line through the corresponding second electrode adapter structure.

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