Ceramic circuit substrate comprising unidirectional porous metal spacer, and power module equipped with same

Abstract

The present invention provides: a ceramic circuit substrate comprising a unidirectional porous metal spacer, which exhibits excellent heat dissipation performance by having a unidirectional porous metal applied thereto; and a power module equipped with the ceramic circuit substrate. The ceramic circuit substrate according to an embodiment of the present invention comprises: a ceramic substrate comprising a ceramic layer and a first substrate copper layer disposed on a first surface of the ceramic layer; and a first unidirectional porous metal spacer disposed on a portion of the first substrate copper layer and having a plurality of pores extending unidirectionally in the vertical direction from the first substrate copper layer.

Description

Ceramic circuit board including a unidirectional porous metal spacer and a power module having the same

[0001] The technical idea of ​​the present invention relates to a ceramic circuit board, and more specifically, to a ceramic circuit board including a unidirectional porous metal spacer and a power module having the same.

[0002] Higher performance, miniaturization, and weight reduction of electronic devices require higher density and integration of semiconductor packages. However, higher integration generates more heat, which degrades semiconductor device performance and can lead to defects such as substrate deterioration, thereby reducing product reliability and lifespan. In particular, high-voltage power conversion electrical components for eco-friendly automobiles are used in extremely harsh operating environments, including high-temperature heat generation and thermal shock conditions. Therefore, securing more efficient heat-dissipating materials and structures is essential. Therefore, research on heat-dissipating materials and technologies that can effectively dissipate generated heat while improving semiconductor device performance and suppressing degradation of product performance and reliability is increasingly important.

[0003] For example, power conversion semiconductors used in electric vehicles are crucial components for converting, controlling, and transmitting high-voltage and high-current electric power, and the demand for power modules made of power conversion semiconductors continues to grow. Typically, power modules generate significant heat during operation. For example, IGBT devices generate heat due to switching losses during turn-on / turn-off switching, and because they use silicon as their base material, the operating temperature at the junction must be limited to 150°C or less. Therefore, to ensure the reliability of power semiconductor devices and power modules, it is essential to address the heat generation issue of IGBTs, and a cooling method must be developed.

[0004] For example, insulated gate bipolar transistor (IGBT) devices, which are silicon (Si)-based power conversion semiconductors, must not only control the amount of heat generated by switching losses due to frequency changes when power is supplied, but also effectively control the thermal shock that creates the problem of residual stress asymmetry that causes cracks in the power module joints, while effectively controlling the parasitic inductance of the power conversion device. Thermal and electrical materials and manufacturing methods must be developed to effectively control the amount of heat generated by lowering the junction temperature to below 150℃ due to different heat generation conditions according to switching off-state losses and on-state losses.

[0005] In addition, SiC-based MOSFET (metal oxide semiconductor field effect transistor) devices with a wide bandgap compared to silicon (Si)-based devices can be miniaturized compared to IGBT devices, and the devices themselves can be operated without problems even when the operating temperature of the junction is 400℃ or higher. However, in order to secure stable operation reliability of solder and other passive and active devices used for mounting the gate driver board, the junction temperature must be controlled below 200℃, and thermal and electrical materials and manufacturing methods that can resolve the thermal shock slope that causes cracks in the power module junction due to the operation characteristic that the switching frequency is up to 10 times higher than that of the IGBT and the parasitic inductance caused by the high switching frequency must be prepared.

[0006] [Prior Art Literature]

[0007] (Patent Document 001) Korean Patent Publication No. 2014-0127228

[0008] The technical problem to be achieved by the technical idea of ​​the present invention is to provide a ceramic circuit board including a one-way porous metal spacer having excellent heat dissipation performance by applying a one-way porous metal body, and a power module having the same.

[0009] However, these tasks are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0010] According to one aspect of the present invention, a ceramic circuit board including a one-way porous metal spacer having excellent heat dissipation performance by applying a one-way porous metal body and a power module having the same are provided.

[0011] According to one embodiment of the present invention, the ceramic circuit board may include a ceramic substrate including a ceramic layer and a first substrate copper layer disposed on a first surface of the ceramic layer; and a first unidirectional porous metal spacer disposed on a portion of the first substrate copper layer and having a plurality of pores extending in one direction in a vertical direction from the first substrate copper layer.

[0012] According to one embodiment of the present invention, the first unidirectional porous metal spacer may have a porosity in the range of 1% by volume to 70% by volume.

[0013] According to one embodiment of the present invention, the first unidirectional porous metal spacer may be formed of a metal casting formed using a mold casting method, a continuous melting method, a continuous casting method, or a centrifugal casting method.

[0014] According to one embodiment of the present invention, the first unidirectional porous metal spacer may be formed as a metal molded body formed by press forming, rolling, and then perforating, laser processing, or selective etching a metal material in the shape of a sheet, plate, sheet, or foil.

[0015] According to one embodiment of the present invention, the first unidirectional porous metal spacer may include copper or a copper alloy.

[0016] According to one embodiment of the present invention, a second unidirectional porous metal spacer may be further included, which is disposed on a portion of the first substrate copper layer, has a plurality of pores extending in one direction in a vertical direction from the first substrate copper layer, and has a greater height than the first unidirectional porous metal spacer.

[0017] According to one embodiment of the present invention, the second unidirectional porous metal spacer may have a porosity in the range of 1% by volume to 70% by volume.

[0018] According to one embodiment of the present invention, the second unidirectional porous metal spacer may be formed of a metal casting formed using a mold casting method, a continuous melting zone method, a continuous casting method, or a centrifugal casting method.

[0019] According to one embodiment of the present invention, the second unidirectional porous metal spacer may be formed as a metal molded body formed by press forming, rolling, and then perforating, laser processing, or selective etching a metal material in the shape of a sheet, plate, sheet, or foil.

[0020] According to one embodiment of the present invention, the first substrate copper layer may be formed of a DBC copper layer formed by bonding copper foil on the ceramic layer through a high-temperature oxidation process, a DPC copper layer formed by forming a seed layer on the ceramic layer and then plating the seed layer with copper, or an AMB copper layer formed by bonding copper foil using an active metal foil to the ceramic layer.

[0021] According to one embodiment of the present invention, the ceramic substrate may further include a second substrate copper layer disposed on a second surface of the ceramic layer.

[0022] According to one embodiment of the present invention, the power module comprises: an upper ceramic circuit board including an upper ceramic substrate including an upper ceramic layer and an upper first substrate copper layer; an upper first unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the first substrate copper layer; and an upper second unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the upper first substrate copper layer and having a greater height than the upper first unidirectional porous metal spacer; a lower ceramic substrate including a lower ceramic layer and a lower first substrate copper layer; a first semiconductor element disposed between the upper first unidirectional porous metal spacer and the lower first substrate copper layer; a second semiconductor element disposed between the upper second unidirectional porous metal spacer and the lower first substrate copper layer and having a smaller thickness than the first semiconductor element; And it may include a mold layer that fills the space between the upper ceramic circuit board and the lower ceramic substrate and covers the first semiconductor element and the second semiconductor element.

[0023] According to one embodiment of the present invention, at least one of an upper heat sink disposed on the outside of the upper ceramic circuit board and a lower heat sink disposed on the outside of the lower ceramic circuit board may be further included.

[0024] According to one embodiment of the present invention, the upper ceramic substrate may further include an upper first active metal brazing layer interposed between the upper ceramic layer and the upper first substrate copper layer, and the lower ceramic substrate may further include a lower first active metal brazing layer interposed between the lower ceramic layer and the lower first substrate copper layer.

[0025] According to one embodiment of the present invention, the power module comprises: an upper ceramic circuit board including an upper ceramic substrate including an upper ceramic layer and an upper first substrate copper layer; an upper first unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the first substrate copper layer; and an upper second unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the upper first substrate copper layer and having a greater height than the upper first unidirectional porous metal spacer; a lower ceramic substrate including a lower ceramic layer and a lower first substrate copper layer; a lower first unidirectional porous metal spacer disposed on a portion of the lower first substrate copper layer and having a plurality of pores extending vertically in one direction from the first substrate copper layer; And a lower ceramic circuit board including a lower second unidirectional porous metal spacer disposed on a portion of the lower first substrate copper layer, the lower second unidirectional porous metal spacer having a plurality of pores extending in one direction in a vertical direction from the lower first substrate copper layer, and having a greater height than the lower first unidirectional porous metal spacer; a first semiconductor element disposed between the upper first unidirectional porous metal spacer and the lower first unidirectional porous metal spacer; a second semiconductor element disposed between the upper second unidirectional porous metal spacer and the lower second unidirectional porous metal spacer, the second semiconductor element having a smaller thickness than the first semiconductor element; and a mold layer filling a space between the upper ceramic circuit board and the lower ceramic circuit board to cover the first semiconductor element and the second semiconductor element.

[0026] According to one embodiment of the present invention, at least one of an upper heat sink disposed on the outside of the upper ceramic circuit board and a lower heat sink disposed on the outside of the lower ceramic circuit board may be further included.

[0027] According to one embodiment of the present invention, the upper ceramic substrate may further include an upper first active metal brazing layer interposed between the upper ceramic layer and the upper first substrate copper layer, and the lower ceramic substrate may further include a lower first active metal brazing layer interposed between the lower ceramic layer and the lower first substrate copper layer.

[0028] The ceramic circuit board according to the present invention can have excellent heat dissipation performance by applying a unidirectional porous metal spacer. By including the unidirectional porous metal spacer, the power module has a large heat dissipation area and low thermal resistance, and also exhibits better thermal efficiency because a heat dissipation path is added through the spacer. In addition, the overall volume of the power module, parasitic inductance, and junction temperature can be reduced. In addition, by including the unidirectional porous metal spacer, it has high thermal conductivity and a large specific surface area, so that heat dissipation performance is excellent, and lightweight due to the porous structure can be secured, so that heat dissipation performance and lightweight are secured simultaneously, and furthermore, mechanical thermal stress at the joint portion caused by a difference in thermal expansion coefficient can be reduced. In addition, since the thermal expansion coefficient of the unidirectional porous metal spacer is the same as that of copper, problems with durability against thermal shock can be fundamentally prevented. Additionally, unidirectional porosity can be controlled by methods such as press forming, perforation after rolling, laser processing, or selective etching.

[0029] The effects of the present invention described above are illustrative, and the scope of the present invention is not limited by these effects.

[0030] FIG. 1 is a top view illustrating a unidirectional porous metal body applied to a ceramic circuit board according to one embodiment of the present invention.

[0031] FIG. 2 is a cross-sectional view taken along line AA of the one-way porous metal body of FIG. 1 according to one embodiment of the present invention.

[0032] Figures 3 and 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0033] FIGS. 5 to 8 are cross-sectional views illustrating a power module according to one embodiment of the present invention.

[0034] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Embodiments of the present invention are provided to more completely explain the technical idea of ​​the present invention to those skilled in the art. The following embodiments may be modified in various different forms, and the scope of the technical idea of ​​the present invention is not limited to the following embodiments. Rather, these embodiments are provided to more faithfully and completely convey the technical idea of ​​the present invention to those skilled in the art. Like reference numerals throughout this specification denote like elements. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the technical idea of ​​the present invention is not limited by the relative sizes or intervals drawn in the attached drawings.

[0035] In this specification, a layer formed "on" another layer may refer to a layer formed directly above the other layer, or may refer to an intermediate layer or layers formed on another layer. It should be noted that the meanings of "upper" and "lower" in this specification are relative, and the direction upward from the ceramic substrate is described as "upper", and the direction downward is described as "lower."

[0036] In the rapidly growing electric vehicle market, power semiconductors are used to variably control the AC voltage and frequency required to drive a three-phase AC motor from the power source, a high-voltage DC battery. Materials and designs that ensure the reliability of power modules in power conversion semiconductors are crucial. This is because both silicon-based IGBTs and SiC-based MOSFETs require control of the junction temperature generated during variable voltage and frequency switching. Furthermore, the heat generated from power conversion semiconductors can induce thermal and mechanical stresses on the solder, passive components, and other active components that make up the package, potentially leading to joint failure and deterioration due to thermal fatigue. Furthermore, high-frequency switching to accommodate the high-speed rotation of the motor can generate thermal shock and parasitic inductance. Therefore, thermal and electrical materials and manufacturing technologies that can effectively control these factors are crucial.

[0037] Recently, with the emergence of wide bandgap power modules such as SiC or GaN, they have higher operating temperatures than conventional silicon-based power modules. To improve heat dissipation of power modules, a double-sided cooling structure has been adopted. In conventional single-sided cooling power modules, the heat dissipation path of the semiconductor device is limited to one direction, whereas a double-sided cooling power module has an upper and lower substrate placed above and below the semiconductor device, which expands the heat dissipation path in two directions and improves heat dissipation capacity. Double-sided cooling structure, planar packaging structure, plate bonded power module, and metal-post interconnected parallel plate structure (MPIPPS) are terms that refer to double-sided cooling structures.

[0038] In explaining the structure of the power module, the semiconductor element may be die-bonded to the lower substrate and bonded to the upper substrate with a spacer. Alternatively, the semiconductor element may be bonded to the lower substrate with a spacer. The lower substrate and the upper substrate may each be in contact with a heat sink on the outside to dissipate heat. The upper substrate and the lower substrate may be applied with a DBC (direct bonded copper) substrate or an AMB (active metal brazing) substrate. Solder may be used as a bonding material for bonding various components such as semiconductor elements, or, for example, a silver sintering transient liquid phase bonding method may be applied to a wide bandgap power module.

[0039] Conventional power modules typically electrically connect the upper terminals of semiconductor devices to the substrate by bonding wires. Therefore, to achieve current flow through bonding wires, the substrate requires additional bonding surface area, potentially reducing power density. Furthermore, the bonding wires increase the current path from the substrate, increasing parasitic inductance and resistance, potentially leading to switching noise and reduced power output. Furthermore, differences in thermal expansion coefficients between the bonding wires and the semiconductor devices can lead to various defects, such as breakage.

[0040] In a double-sided cooling power module, semiconductor elements and a substrate can be thermally and electrically connected using spacers instead of bonding wires. Furthermore, the spacers can be inserted between the semiconductor elements and the lower substrate or between the semiconductor elements and the upper substrate to compensate for height deviations between semiconductor elements of different heights. Power modules including spacers have a larger heat dissipation area and lower thermal resistance than those using bonding wires. Furthermore, the spacers provide an additional heat dissipation path, resulting in superior thermal efficiency. Furthermore, the overall volume, parasitic inductance, and junction temperature of the power module can be reduced.

[0041] However, these double-sided cooling power modules also present challenges. Because double-sided cooling power modules utilize spacers with larger surfaces than bonding wires, mechanical thermal stress due to differences in thermal expansion coefficients is more concentrated at the joints, increasing the risk of fracture. Therefore, reducing the mechanical thermal stress applied to the joints of double-sided cooling power modules is necessary to ensure module reliability.

[0042] In conventional double-sided cooling power modules, various methods have been proposed to reduce this mechanical thermal stress. First, using copper, which has high thermal conductivity, as a spacer has the problem of a large difference in the coefficient of thermal expansion between the ceramic layer of the substrate and the semiconductor element. While replacing copper with molybdenum can reduce mechanical thermal stress, its reduced thermal conductivity limits heat dissipation performance. Therefore, copper-molybdenum alloys are used. Another alternative is to change the rectangular spacer shape to a different shape that can alleviate mechanical thermal stress. However, this change in shape reduces the bonding area, potentially increasing thermal resistance.

[0043] The technical idea of ​​the present invention is to overcome this reliability degradation, and to apply a spacer composed of a unidirectional porous metal (UPM) to a power module instead of a conventional cuboid-shaped spacer.

[0044] The above-mentioned unidirectional porous metal spacer has high thermal conductivity and a large specific surface area, thereby exhibiting excellent heat dissipation performance and ensuring lightness due to its porous structure, thereby simultaneously securing improved heat dissipation performance and lightness. In addition, the above-mentioned unidirectional porous metal spacer can reduce mechanical thermal stress at the joint portion caused by differences in thermal expansion coefficients.

[0045] Solder or adhesive may be used as a bonding material for bonding various components such as semiconductor devices, or, for example, Ag based filler sintering or transient liquid phase bonding may be applied to wide bandgap power modules.

[0046] Hereinafter, a one-way porous metal body according to the technical idea of ​​the present invention will be described in detail.

[0047] FIG. 1 is a top view illustrating a unidirectional porous metal body applied to a ceramic circuit board according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA of the unidirectional porous metal body of FIG. 1 according to one embodiment of the present invention.

[0048] Referring to FIGS. 1 and 2, a unidirectional porous metal body (1) has a metal body (2) and a plurality of unidirectional pores (3) formed to extend along a pore extending direction within the metal body (2). The unidirectional porous metal body (1) may be referred to as a lotus structure. The unidirectional pores (3) may be formed to a depth that penetrates the metal body (2) or may be formed to a depth that does not penetrate the metal body (2).

[0049] The unidirectional porous metal body (1) can exhibit anisotropic properties, unlike conventional porous metals that include pores in an isotropic manner, since it includes unidirectional pores (3) arranged in one direction. In particular, it has excellent heat transfer performance in the pore direction and a thermal stress relief effect.

[0050] The manufacturing method for forming a one-way porous metal body (1) can be carried out in various ways. For example, in the case of a casting method, there are a mold casting method, a continuous melt zone method, a continuous casting method, a centrifugal casting method, etc., and in the case of a forming method, there are press forming, rolling, perforation, laser processing, or selective etching of a metal material in the shape of a sheet, plate, sheet, or foil.

[0051] The one-way porous metal body (1) can be formed as a metal casting body using a mold casting method, a continuous melting zone method, a continuous casting method, or a centrifugal casting method.

[0052] Alternatively, the one-way porous metal body (1) may be formed as a metal molded body formed by using press forming, rolling, and then perforating, laser processing, or selective etching of a metal material in the shape of a sheet, plate, sheet, or foil.

[0053] The pore characteristics of a unidirectional porous metal body (1) of a casting method can be controlled by the pressure of the injected hydrogen gas, the solidification speed, etc. As the hydrogen gas pressure and the solidification speed increase, the porosity and pore size can decrease. The unidirectional porous metal body (1) can have a porosity in the range of, for example, 1 vol% to 70 vol%.

[0054] A unidirectional porous metal body (1) refers to a metal in which cylindrical pores are arranged in one direction. In addition, if necessary, the unidirectional porous metal body can be utilized as a composite material composed of other materials.

[0055] A unidirectional porous metal body (1) is a form in which unidirectional pores are contained within the metal. It has the characteristic of anisotropic thermal, electrical, and mechanical properties. This anisotropic characteristic is what differentiates it from other porous metals. For example, the unidirectional porous metal body (1) may have anisotropic elastic modulus, thermal conductivity, and electrical conductivity.

[0056] The one-way porous metal body (1) may include various metals, for example, copper or a copper alloy.

[0057] Table 1 shows the anisotropic thermal, electrical, and mechanical properties of a unidirectional porous metal body (1) composed of copper according to the porosity. In Table 1, “∥” means a direction parallel to the extension direction of the pores, and “⊥” means a direction parallel to the extension direction of the pores.

[0058] Porosity (%)Elasticity modulus (GPa)Thermal conductivity (W / mK)Electrical conductivity (x10 6 Ω -1 m -1 )E ∥ E ⊥ K ∥ K ⊥ σ ∥ σ ⊥0759534034015.015.01067~7480~9430527013.512.02060~6660~7927022012.09.73052~5943~5923517010.57.84045~5130~422001409.05.25037~4420~291651207.54.06030~3613~19130806.02.27022~298~1295504.51.28015~214~760303.00.7

[0059] Referring to Table 1, the elastic modulus, thermal conductivity, and electrical conductivity of a unidirectional porous metal body (1) composed of copper decrease as the porosity increases. In addition, the elastic modulus, thermal conductivity, and electrical conductivity exhibit anisotropy in that they decrease more in the vertical direction than in the direction parallel to the extension direction of the pores as the porosity increases.

[0060] When comparing a copper structure without pores and a unidirectional porous metal body composed of copper, their coefficients of thermal expansion are almost the same. On the other hand, the thermal stress of the unidirectional porous metal body composed of copper is significantly reduced for the same strain, so that mechanical thermal stress can be alleviated. In addition, since the elastic modulus of the unidirectional porous metal body in both the vertical and horizontal directions decreases with respect to external stress, the shock absorption capacity can be improved. Although the thermal conductivity and electrical conductivity of the unidirectional porous metal body composed of copper decrease as the porosity increases, they are higher than those of molybdenum.

[0061] The unidirectional porous metal body described above can hinder the propagation path of cracks occurring at the joint through the pores provided therein. When a crack propagating along the interface encounters the pores, the direction of the path changes, thereby increasing the joint strength.

[0062] By inserting other materials into the pores of the above-mentioned one-way porous metal body, the properties of a composite material can be obtained. Accordingly, properties such as elastic modulus, thermal conductivity, electrical conductivity, and parasitic inductance can be changed, and if necessary, improved.

[0063] Figures 3 and 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.

[0064] Referring to FIG. 3, the ceramic circuit board (100) may include a ceramic substrate (110), a first unidirectional porous metal spacer (120), and a second unidirectional porous metal spacer (130).

[0065] Referring to FIG. 4, the ceramic circuit board (100a) may include a ceramic substrate (110a), a first unidirectional porous metal spacer (120), and a second unidirectional porous metal spacer (130).

[0066] Hereinafter, components of the ceramic circuit board will be described in detail with reference to FIGS. 3 and 4.

[0067] The ceramic substrate (110) may include a ceramic layer (111), a first substrate copper layer (112), and a second substrate copper layer (113).

[0068] The ceramic substrate (110a) may include a ceramic layer (111), a first substrate copper layer (112), a second substrate copper layer (113), a first active metal brazing layer (114), and a second active metal brazing layer (115). Compared to the ceramic substrate (110), the ceramic substrate (110a) has a difference in that it further includes a first active metal brazing layer (114) and a second active metal brazing layer (115).

[0069] The ceramic layer (111) may have a first surface (118) and a second surface (119) that face each other. In FIGS. 3 and 4 , the first surface (118) is illustrated as the upper surface and the second surface (119) is illustrated as the lower surface of the ceramic layer (111). The ceramic layer (111) may have excellent thermal conductivity and electrical insulation. The ceramic layer (111) may be formed of a ceramic material, and may include, for example, at least one of Al2O3, AlN, Zirconia Toughened Alumina (ZTA), and Si3N4.

[0070] A first substrate copper layer (112) may be disposed on a first surface (118) of a ceramic layer (111). The first substrate copper layer (112) may be patterned to function as a circuit structure for a semiconductor device. The first substrate copper layer (112) may be formed as a single layer or may be formed as a plurality of layers. The first substrate copper layer (112) may have a total thickness in the range of, for example, 100 μm to 1000 μm, and may have a total thickness of, for example, about 300 μm.

[0071] The second substrate copper layer (113) may be disposed on the second surface (119) opposite to the first surface (118) of the ceramic layer (111). The second substrate copper layer (113) may function as a warpage prevention layer that prevents the ceramic layer (111) from warping. In addition, the second substrate copper layer (113) may provide a path for dissipating heat generated from the semiconductor element to the outside. For this purpose, a heat dissipation structure may be attached to the second substrate copper layer (113). The second substrate copper layer (113) may be formed as a single layer or may be formed as a plurality of layers. The second substrate copper layer (113) may have a total thickness of, for example, 100 μm to 1000 μm, and may have a total thickness of, for example, about 300 μm.

[0072] The first substrate copper layer (112) and the second substrate copper layer (113) may include the same material, be formed using the same method, and be formed simultaneously. The first substrate copper layer (112) and the second substrate copper layer (113) may be formed using DBC technology, DPC technology, or AMB technology. However, this is exemplary, and the technical idea of ​​the present invention also includes cases where the first substrate copper layer (112) and the second substrate copper layer (113) include different materials, are formed using different methods, or are formed at different process points.

[0073] At least one of the first substrate copper layer (112) and the second substrate copper layer (113) may be formed as a DBC copper layer formed using a DBC (direct bonded copper) technology. The DBC technology may refer to a technology of forming a copper layer by directly attaching a copper foil to a ceramic layer. The DBC copper layer may be formed by placing a copper foil on one or both sides of a ceramic layer (111), performing a high-temperature oxidation process at a temperature in the range of 1000°C to 1080°C, and bonding the copper foil to the ceramic layer using a copper-oxygen eutectic liquid. The bonding may be performed in a nitrogen atmosphere containing about 30 ppm of oxygen at a temperature lower than 1083°C, which is the melting point of copper, and forming a copper oxide layer on the surface of the copper foil to implement bonding with the ceramic layer (111). Subsequently, if necessary, the DBC copper layer may be patterned using an etching process. Additionally, nickel (Ni), silver (Ag), gold (Au), etc. can be plated on the DBC copper layer.

[0074] At least one of the first substrate copper layer (112) and the second substrate copper layer (113) may be formed as a DPC copper layer formed using a DPC (direct plating copper) technology. The DPC technology may refer to a technology for forming a copper layer by using a thin film process, an etching process, and a plating process. The DPC copper layer may be formed by forming a seed layer of titanium (Ti), titanium-tungsten (TiW), or the like on one or both sides of a ceramic layer (111), and then plating copper (Cu) on the seed layer. In addition, a photoresist pattern may be formed on the seed layer, and then copper (Cu) may be plated on the photoresist pattern, and the photoresist pattern may be removed to form the DPC copper layer having a desired pattern. Subsequently, if necessary, the DPC copper layer may be patterned using an etching process.

[0075] At least one of the first substrate copper layer (112) and the second substrate copper layer (113) may be formed as an AMB copper layer formed using an AMB (active metal brazing) technique. The AMB technique may refer to a technique of bonding a ceramic layer and a copper layer using an active metal foil. An active metal foil and a copper foil are sequentially placed on one or both sides of a ceramic layer (111), and heated to melt the active metal foil, thereby forming a first active metal brazing layer (114) and a second active metal brazing layer (115), thereby bonding the ceramic layer (111) and the copper foil to each other.

[0076] The first active metal brazing layer (114) can serve to bond the ceramic layer (111) and the first substrate copper layer (112). The second active metal brazing layer (115) can serve to bond the ceramic layer (111) and the second substrate copper layer (113). Subsequently, if necessary, the AMB copper layer can be patterned using an etching process.

[0077] The first active metal brazing layer (114) and the second active metal brazing layer (115) may include a metal or metal alloy having a lower melting point than the copper constituting the copper foil, and may include, for example, an active metal alloy in which copper, aluminum, nickel, or silver is added to titanium, hafnium, nickel, molybdenum, or zirconium, which are active toward oxygen, to lower the melting point. The first active metal brazing layer (114) and the second active metal brazing layer (115) may include, for example, an alloy including at least one of silver (Ag), copper (Cu), and titanium (Ti). However, this is exemplary, and the first active metal brazing layer (114) and the second active metal brazing layer (115) may include at least one of aluminum (Al), titanium (Ti), nickel (Ni), niobium (Nb), and molybdenum (Mo).

[0078] As illustrated in FIG. 4, the first active metal brazing layer (114) may be disposed on the first surface (118) of the ceramic layer (111). The first substrate copper layer (112) may be disposed on the first active metal brazing layer (114). That is, the first active metal brazing layer (114) may be interposed between the ceramic layer (111) and the first substrate copper layer (112), thereby bonding the ceramic layer (111) and the first substrate copper layer (112) to each other.

[0079] The second active metal brazing layer (115) may be disposed on the second surface (119) of the ceramic layer (111). The second substrate copper layer (113) may be disposed on the second active metal brazing layer (115). That is, the second active metal brazing layer (115) is interposed between the ceramic layer (111) and the second substrate copper layer (113), thereby bonding the ceramic layer (111) and the second substrate copper layer (113) to each other.

[0080] In addition, a case where at least one of the first substrate copper layer (112) and the second substrate copper layer (113) is composed of a unidirectional porous metal body is also included in the technical idea of ​​the present invention.

[0081] Referring again to FIGS. 3 and 4, the first unidirectional porous metal spacer (120) may be disposed on a portion of the ceramic substrate (110), for example, on a portion of the first substrate copper layer (112). The first unidirectional porous metal spacer (120) may be bonded to the first substrate copper layer (112) by a first spacer adhesive layer (122).

[0082] The first unidirectional porous metal spacer (120) may have a first height. The first unidirectional porous metal spacer (120) may be arranged in multiples, and may all have substantially the same height. The first height may refer to the height from the ceramic substrate (110), for example, the height from the first substrate copper layer (112).

[0083] The second unidirectional porous metal spacer (130) may be disposed on a portion of the ceramic substrate (110), for example, on a portion of the first substrate copper layer (112). The second unidirectional porous metal spacer (130) may be bonded to the first substrate copper layer (112) by a second spacer adhesive layer (132).

[0084] The second unidirectional porous metal spacer (130) may have a greater height than the first unidirectional porous metal spacer (120), for example, may have a second height greater than the first height. The second unidirectional porous metal spacers (130) may be arranged in multiples, and may all have substantially the same height. The second height may refer to a height from the ceramic substrate (110), for example, a height from the first substrate copper layer (112).

[0085] The first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130) can provide a space in which a semiconductor element is mounted, and can function as a spacer for correcting a thickness deviation of the semiconductor element. The height at which the semiconductor element is mounted can be changed by the arrangement of the first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130). That is, since the first unidirectional porous metal spacer (120) is arranged in some areas of the ceramic substrate (110) and the second unidirectional porous metal spacer (130) is arranged in other areas of the ceramic substrate (110), the mounting height provided by the second unidirectional porous metal spacer (130) can be greater than the mounting height provided by the first unidirectional porous metal spacer (120). Accordingly, the thickness deviation of semiconductor elements of different thicknesses can be compensated. Here, the semiconductor elements disposed on the first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130) may include various semiconductor elements such as power semiconductor elements, memory semiconductor elements, switching semiconductor elements, and diode semiconductor elements.

[0086] The first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130) may have the same planar area or different planar areas, and may have various planar areas corresponding to the semiconductor elements to be mounted.

[0087] Additionally, at least one of the first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130) can additionally perform the function of wiring that provides an electrical path to the semiconductor element.

[0088] The first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130) may be formed of a unidirectional porous metal (UPM) having a plurality of unidirectional pores extending in one direction. The first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130) may be formed of a metal casting, or may be manufactured by various methods such as press forming and laser processing. The first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130) may include copper or a copper alloy. However, this is merely an example, and the technical idea of ​​the present invention is not limited thereto.

[0089] The first unidirectional porous metal spacer (120) may have a plurality of pores extending in a vertical direction from the ceramic substrate (110), for example, from the first substrate copper layer (112). The first unidirectional porous metal spacer (120) may have a porosity in the range of, for example, 1 vol% to 70 vol%.

[0090] The second unidirectional porous metal spacer (130) may have a plurality of pores extending in a vertical direction from the ceramic substrate (110), for example, from the first substrate copper layer (112). The second unidirectional porous metal spacer (130) may have a porosity in the range of, for example, 1 vol% to 70 vol%.

[0091] The conventionally widely used Mo-Cu spacer is a metal processing material that does not contain pores inside and has a porosity of approximately 0%, thus exhibiting high thermal stress and low thermal fatigue fracture characteristics. On the other hand, the unidirectional porous metal spacer according to the present invention includes unidirectional pores extending in a direction perpendicular to the ceramic substrate (110), thereby exhibiting low thermal stress, increased crack propagation resistance, and increased shock absorption capacity.

[0092] The first and second spacer adhesive layers (122, 132) may include various materials that function to adhere the first unidirectional porous metal spacer (120) and the second unidirectional porous metal spacer (130), and may be, for example, a solder layer or an adhesive layer. However, this is merely exemplary and the technical idea of ​​the present invention is not limited thereto.

[0093] Hereinafter, a power module using a ceramic circuit board according to an embodiment of the present invention will be described. The power module described below is a double-sided cooling power module, which is exemplary, and the application of a ceramic circuit board to a single-sided cooling power module is also included within the technical scope of the present invention.

[0094] FIGS. 5 to 8 are cross-sectional views illustrating a power module according to one embodiment of the present invention.

[0095] Referring to FIG. 5, the power module (1000) may include an upper ceramic circuit board (100_U), a lower ceramic board (110_D), a first semiconductor element (170), a second semiconductor element (180), and a mold layer (190).

[0096] Additionally, the power module (1000) may further include at least one of an upper heat sink (140_U), a lower heat sink (140_D), an upper base plate (150_U), and a lower base plate (150_D).

[0097] The upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first unidirectional porous metal spacer (120_U), and an upper second unidirectional porous metal spacer (130_U).

[0098] The upper ceramic substrate (110_U) may include an upper ceramic layer (111_U), an upper first substrate copper layer (112_U), and an upper second substrate copper layer (113_U).

[0099] The lower ceramic substrate (110_D) may include a lower ceramic layer (111_D), a lower first substrate copper layer (112_D), and a lower second substrate copper layer (113_D).

[0100] The upper ceramic circuit board (100_U) and the lower ceramic board (110_D) can be placed facing each other.

[0101] The upper first unidirectional porous metal spacer (120_U) can be attached to the upper first substrate copper layer (112_U) by the first spacer adhesive layer (122). The upper second unidirectional porous metal spacer (130_U) can be attached to the upper first substrate copper layer (112_U) by the second spacer adhesive layer (132).

[0102] The first semiconductor element (170) may be placed between the upper first unidirectional porous metal spacer (120_U) and the lower first substrate copper layer (112_D). The first semiconductor element (170) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower first substrate copper layer (112_D) by a first element adhesive layer (172).

[0103] The second semiconductor element (180) may be placed between the upper second unidirectional porous metal spacer (130_U) and the lower first substrate copper layer (112_D). The second semiconductor element (180) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower first substrate copper layer (112_D) by a second element adhesive layer (182).

[0104] The first semiconductor element (170) and the second semiconductor element (180) may be power semiconductor elements, for example, GTO (gate turn-off thyristor) semiconductor elements, IGBT (insulated gate bipolar mode transistor) semiconductor elements, SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor elements, GaN MOSFET semiconductor elements, etc., and may perform an operation of converting and supplying power supplied from a power supply unit such as a battery into power for driving a motor through a switching operation. In addition, the first semiconductor element (170) and the second semiconductor element (180) may include electrode members formed on the upper or lower portions.

[0105] The second semiconductor element (180) may have a smaller thickness than the first semiconductor element (170). Therefore, a first upper unidirectional porous metal spacer (120_U) having a relatively small thickness is disposed on the upper side of the first semiconductor element (170), and a second upper unidirectional porous metal spacer (130_U) having a relatively large thickness is disposed on the upper side of the second semiconductor element (180), thereby correcting the thickness difference between the second semiconductor element (180) and the first semiconductor element (170).

[0106] The first element adhesive layer (172) and the second element adhesive layer (182) may be solder layers or adhesive layers, which are exemplary and the technical idea of ​​the present invention is not limited thereto.

[0107] The mold layer (190) can fill the space between the upper ceramic circuit board (100_U) and the lower ceramic board (110_D). Accordingly, the first semiconductor element (170) and the second semiconductor element (180) can be covered by the mold layer (190). The mold layer (190) can insulate the first semiconductor element (170) and the second semiconductor element (180). The mold layer (190) can be composed of, for example, EMC (epoxy molding compound).

[0108] The power module (1000) includes an upper first unidirectional porous metal spacer (120_U) and an upper second unidirectional porous metal spacer (130_U), and does not include a spacer at the bottom, so that it can have an asymmetrical structure with respect to the first semiconductor element (170) and the second semiconductor element (180).

[0109] The upper ceramic circuit board (100_U) and the lower ceramic board (110_D) can perform the function of discharging heat generated from the first semiconductor element (170) and the second semiconductor element (180) to the outside.

[0110] For this heat dissipation, the upper first unidirectional porous metal spacer (120_U) can efficiently transfer heat generated from the first semiconductor element (170) to the upper ceramic circuit board (100_U). In addition, the upper second unidirectional porous metal spacer (130_U) can efficiently transfer heat generated from the second semiconductor element (180) to the upper ceramic circuit board (100_U).

[0111] As described above, the upper first unidirectional porous metal spacer (120_U) and the upper second unidirectional porous metal spacer (130_U) can reduce mechanical thermal stress and provide excellent shock absorption capability by including unidirectional pores along with excellent thermal conductivity and electrical conductivity.

[0112] Additionally, the upper first unidirectional porous metal spacer (120_U) can provide an electrical path to the first semiconductor element (170). The upper second unidirectional porous metal spacer (130_U) can provide an electrical path to the second semiconductor element (180).

[0113] Additionally, for efficient heat dissipation to the outside, an upper heat sink (140_U) may be placed on the outside of the upper ceramic circuit board (100_U), and a lower heat sink (140_D) may be placed on the outside of the lower ceramic circuit board (110_D). The upper heat sink (140_U) and the lower heat sink (140_D) may include a material with excellent heat transfer, such as aluminum or copper.

[0114] Optionally, the power module (1000) may further include an upper base plate (150_U) disposed between the upper ceramic circuit board (100_U) and the upper heat sink (140_U) and a lower base plate (150_D) disposed between the lower ceramic circuit board (110_D) and the lower heat sink (140_D) for structural stability. The upper base plate (150_U) and the lower base plate (150_D) may include a metal, for example, copper or a copper alloy.

[0115] The upper heat sink (140_U), the lower heat sink (140_D), the upper base plate (150_U), and the lower base plate (150_D) can be bonded by a suitable bonding material such as solder or adhesive.

[0116] Below, descriptions of components identical or similar to those in the embodiment of Fig. 5 will be omitted.

[0117] Referring to FIG. 6, the power module (1000a) may include an upper ceramic circuit board (100a_U), a lower ceramic board (110a_D), a first semiconductor element (170), a second semiconductor element (180), and a mold layer (190).

[0118] Additionally, the power module (1000a) may further include at least one of an upper heat sink (140_U), a lower heat sink (140_D), an upper base plate (150_U), and a lower base plate (150_D).

[0119] The upper ceramic circuit board (100a_U) may include an upper ceramic substrate (110a_U), an upper first unidirectional porous metal spacer (120_U), and an upper second unidirectional porous metal spacer (130_U).

[0120] The upper ceramic substrate (110a_U) may include an upper ceramic layer (111_U), an upper first substrate copper layer (112_U), an upper second substrate copper layer (113_U), an upper first active metal brazing layer (114_U), and an upper second active metal brazing layer (115_U).

[0121] The lower ceramic substrate (110a_D) may include a lower ceramic layer (111_D), a lower first substrate copper layer (112_D), a lower second substrate copper layer (113_D), a lower first active metal brazing layer (114_D), and a lower second active metal brazing layer (115_D).

[0122] The upper ceramic circuit board (100a_U) and the lower ceramic board (110a_D) can be placed facing each other.

[0123] The upper first unidirectional porous metal spacer (120_U) can be attached to the upper first substrate copper layer (112_U) by the first spacer adhesive layer (122). The upper second unidirectional porous metal spacer (130_U) can be attached to the upper first substrate copper layer (112_U) by the second spacer adhesive layer (132).

[0124] The first semiconductor element (170) may be placed between the upper first unidirectional porous metal spacer (120_U) and the lower first substrate copper layer (112_D). The first semiconductor element (170) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower first substrate copper layer (112_D) by a first element adhesive layer (172).

[0125] The second semiconductor element (180) may be placed between the upper second unidirectional porous metal spacer (130_U) and the lower first substrate copper layer (112_D). The second semiconductor element (180) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower first substrate copper layer (112_D) by a second element adhesive layer (182).

[0126] The power module (1000a) includes an upper first unidirectional porous metal spacer (120_U) and an upper second unidirectional porous metal spacer (130_U), and does not include a spacer at the bottom, so it may have an asymmetrical structure with respect to the first semiconductor element (170) and the second semiconductor element (180).

[0127] Compared with the power module (1000) of FIG. 5, the power module (1000a) of FIG. 6 has a difference in that it further includes an upper first active metal brazing layer (114_U) interposed between the upper ceramic layer (111_U) and the upper first substrate copper layer (112_U) and an upper second active metal brazing layer (115_U) interposed between the upper ceramic layer (111_U) and the upper second substrate copper layer (113_U). In addition, the power module (1000a) of FIG. 6 has a difference in that it further includes a lower first active metal brazing layer (114_D) interposed between the lower ceramic layer (111_D) and the lower first substrate copper layer (112_D) and a lower second active metal brazing layer (115_D) interposed between the lower ceramic layer (111_D) and the lower second substrate copper layer (113_D).

[0128] Referring to FIG. 7, the power module (1000b) may include an upper ceramic circuit board (100_U), a lower ceramic circuit board (100_D), a first semiconductor element (170), a second semiconductor element (180), and a mold layer (190).

[0129] Additionally, the power module (1000b) may further include at least one of an upper heat sink (140_U), a lower heat sink (140_D), an upper base plate (150_U), and a lower base plate (150_D).

[0130] The upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first unidirectional porous metal spacer (120_U), and an upper second unidirectional porous metal spacer (130_U).

[0131] The upper ceramic substrate (110_U) may include an upper ceramic layer (111_U), an upper first substrate copper layer (112_U), and an upper second substrate copper layer (113_U).

[0132] The lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first unidirectional porous metal spacer (120_D), and a lower second unidirectional porous metal spacer (130_D).

[0133] The lower ceramic substrate (110_D) may include a lower ceramic layer (111_D), a lower first substrate copper layer (112_D), and a lower second substrate copper layer (113_D).

[0134] The upper ceramic circuit board (100_U) and the lower ceramic circuit board (100_D) can be placed facing each other.

[0135] The upper first unidirectional porous metal spacer (120_U) can be attached to the upper first substrate copper layer (112_U) by the first spacer adhesive layer (122). The upper second unidirectional porous metal spacer (130_U) can be attached to the upper first substrate copper layer (112_U) by the second spacer adhesive layer (132).

[0136] The lower first unidirectional porous metal spacer (120_D) can be attached to the lower first substrate copper layer (112_D) by the first spacer adhesive layer (122). The lower second unidirectional porous metal spacer (130_D) can be attached to the lower first substrate copper layer (112_D) by the second spacer adhesive layer (132).

[0137] The first semiconductor element (170) may be placed between the upper first unidirectional porous metal spacer (120_U) and the lower first unidirectional porous metal spacer (120_D). The first semiconductor element (170) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower second unidirectional porous metal spacer (130_D) by the first element adhesive layer (172).

[0138] The second semiconductor element (180) may be placed between the upper second unidirectional porous metal spacer (130_U) and the lower second unidirectional porous metal spacer (130_D). The second semiconductor element (180) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower second unidirectional porous metal spacer (130_D) by a second element adhesive layer (182).

[0139] The second semiconductor element (180) may have a smaller thickness than the first semiconductor element (170). Therefore, an upper first unidirectional porous metal spacer (120_U) having a relatively small thickness is disposed on the upper side of the first semiconductor element (170), a lower first unidirectional porous metal spacer (120_D) is disposed on the lower side of the first semiconductor element (170), an upper second unidirectional porous metal spacer (130_U) having a relatively large thickness is disposed on the upper side of the second semiconductor element (180), and a lower second unidirectional porous metal spacer (130_D) is disposed on the lower side of the second semiconductor element (180), thereby correcting the thickness deviation between the second semiconductor element (180) and the first semiconductor element (170).

[0140] The mold layer (190) can fill the space between the upper ceramic circuit board (100_U) and the lower ceramic circuit board (100_D). Accordingly, the first semiconductor element (170) and the second semiconductor element (180) can be covered by the mold layer (190).

[0141] Compared to the power module (1000) of FIG. 5, the power module (1000b) of FIG. 7 has a difference in that it includes a lower ceramic circuit board (100_D) instead of a lower ceramic board (110_D).

[0142] The power module (1000b) may have a symmetrical structure with respect to the first semiconductor element (170) and the second semiconductor element (180). That is, the upper first unidirectional porous metal spacer (120_U), the lower first unidirectional porous metal spacer (120_D), the upper second unidirectional porous metal spacer (130_U), and the lower second unidirectional porous metal spacer (130_D) may be arranged symmetrically with respect to the first semiconductor element (170) and the second semiconductor element (180). However, this is merely exemplary, and the technical idea of ​​the present invention is not limited thereto. For example, the upper first unidirectional porous metal spacer (120_U) and the lower first unidirectional porous metal spacer (120_D) may have different heights. Additionally, the upper second unidirectional porous metal spacer (130_U) and the lower second unidirectional porous metal spacer (130_D) may have different heights.

[0143] The upper ceramic circuit board (100_U) and the lower ceramic circuit board (100_D) can perform the function of discharging heat generated from the first semiconductor element (170) and the second semiconductor element (180) to the outside.

[0144] For this heat dissipation, the upper first unidirectional porous metal spacer (120_U) and the lower first unidirectional porous metal spacer (120_D) can efficiently transfer heat generated from the first semiconductor element (170) to the upper ceramic circuit board (100_U) and the lower ceramic circuit board (100_D), respectively. In addition, the upper second unidirectional porous metal spacer (130_U) and the lower second unidirectional porous metal spacer (130_D) can efficiently transfer heat generated from the second semiconductor element (180) to the upper ceramic circuit board (100_U) and the lower ceramic circuit board (100_D), respectively.

[0145] As described above, the upper first unidirectional porous metal spacer (120_U), the lower first unidirectional porous metal spacer (120_D), the upper second unidirectional porous metal spacer (130_U), and the lower second unidirectional porous metal spacer (130_D) can reduce mechanical thermal stress and provide excellent shock absorption capability by including unidirectional pores along with excellent thermal conductivity and electrical conductivity.

[0146] Additionally, the upper first unidirectional porous metal spacer (120_U) and the lower first unidirectional porous metal spacer (120_D) can provide an electrical path to the first semiconductor element (170). The upper second unidirectional porous metal spacer (130_U) and the lower second unidirectional porous metal spacer (130_D) can provide an electrical path to the second semiconductor element (180).

[0147] Additionally, for efficient heat dissipation to the outside, an upper heat sink (140_U) may be placed on the outside of the upper ceramic circuit board (100_U), and a lower heat sink (140_D) may be placed on the outside of the lower ceramic circuit board (100_D).

[0148] Optionally, the power module (1000b) may further include an upper base plate (150_U) disposed between the upper ceramic circuit board (100_U) and the upper heat sink (140_U) for structural stability, and a lower base plate (150_D) disposed between the lower ceramic circuit board (100_D) and the lower heat sink (140_D). The upper base plate (150_U) and the lower base plate (150_D) may be formed of a metal plate, for example, a copper plate. In addition, a case where at least one of the upper base plate (150_U) and the lower base plate (150_D) is formed of a unidirectional porous metal body is also included in the technical idea of ​​the present invention.

[0149] Referring to FIG. 8, the power module (1000c) may include an upper ceramic circuit board (100a_U), a lower ceramic circuit board (100a_D), a first semiconductor element (170), a second semiconductor element (180), and a mold layer (190).

[0150] Additionally, the power module (1000c) may further include at least one of an upper heat sink (140_U), a lower heat sink (140_D), an upper base plate (150_U), and a lower base plate (150_D).

[0151] The upper ceramic circuit board (100a_U) may include an upper ceramic substrate (110a_U), an upper first unidirectional porous metal spacer (120_U), and an upper second unidirectional porous metal spacer (130_U).

[0152] The upper ceramic substrate (110a_U) may include an upper ceramic layer (111_U), an upper first substrate copper layer (112_U), an upper second substrate copper layer (113_U), an upper first active metal brazing layer (114_U), and an upper second active metal brazing layer (115_U).

[0153] The lower ceramic circuit board (100a_D) may include a lower ceramic substrate (110_D), a lower first unidirectional porous metal spacer (120_D), and a lower second unidirectional porous metal spacer (130_D).

[0154] The lower ceramic substrate (110a_D) may include a lower ceramic layer (111_D), a lower first substrate copper layer (112_D), a lower second substrate copper layer (113_D), a lower first active metal brazing layer (114_D), and a lower first active metal brazing layer (114_D).

[0155] The upper ceramic circuit board (100a_U) and the lower ceramic circuit board (100a_D) can be placed facing each other.

[0156] The upper first unidirectional porous metal spacer (120_U) can be attached to the upper first substrate copper layer (112_U) by the first spacer adhesive layer (122). The upper second unidirectional porous metal spacer (130_U) can be attached to the upper first substrate copper layer (112_U) by the second spacer adhesive layer (132).

[0157] The lower first unidirectional porous metal spacer (120_D) can be attached to the lower first substrate copper layer (112_D) by the first spacer adhesive layer (122). The lower second unidirectional porous metal spacer (130_D) can be attached to the lower first substrate copper layer (112_D) by the second spacer adhesive layer (132).

[0158] The first semiconductor element (170) may be placed between the upper first unidirectional porous metal spacer (120_U) and the lower first unidirectional porous metal spacer (120_D). The first semiconductor element (170) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower second unidirectional porous metal spacer (130_D) by the first element adhesive layer (172).

[0159] The second semiconductor element (180) may be placed between the upper second unidirectional porous metal spacer (130_U) and the lower second unidirectional porous metal spacer (130_D). The second semiconductor element (180) may be bonded to the upper first unidirectional porous metal spacer (120_U) and the lower second unidirectional porous metal spacer (130_D) by a second element adhesive layer (182).

[0160] Compared with the power module (1000b) of FIG. 7, the power module (1000c) of FIG. 8 has a difference in that it further includes an upper first active metal brazing layer (114_U) interposed between the upper ceramic layer (111_U) and the upper first substrate copper layer (112_U) and an upper second active metal brazing layer (115_U) interposed between the upper ceramic layer (111_U) and the upper second substrate copper layer (113_U). Additionally, the power module (1000c) of FIG. 8 has a difference in that it further includes a lower first active metal brazing layer (114_D) interposed between the lower ceramic layer (111_D) and the lower first substrate copper layer (112_D) and a lower second active metal brazing layer (115_D) interposed between the lower ceramic layer (111_D) and the lower second substrate copper layer (113_D).

[0161] Compared to the power module (1000a) of FIG. 6, the power module (1000c) of FIG. 8 has a difference in that it includes a lower ceramic circuit board (100a_D) instead of a lower ceramic board (110a_D). The power module (1000c) may have a symmetrical structure with respect to the first semiconductor element (170) and the second semiconductor element (180).

[0162] It can be confirmed that a double-sided cooling power module to which a one-way porous metal spacer according to the present invention is applied can reduce mechanical thermal stress by about 50% and increase the lifespan by about 40% under a thermal shock test environment compared to a double-sided cooling power module to which a commercial copper spacer is applied.

[0163] The characteristics of a double-sided cooling power module using a unidirectional porous metal spacer according to the present invention were simulated. As comparative examples, a double-sided cooling power module using a commercial copper spacer and a molybdenum spacer without pores was set up.

[0164] Table 2 shows the properties of the materials used in the above-described simulations. For reference, the E of SAC305 varies with temperature and is 45.7 (-40°C), 42.2 (-20°C), 31.7 (40°C), 24.6 (80°C), 16.7 (125°C), 12.3 (150°C), and 35.0 (200°C).

[0165] Material E(GPa)v(mm / mm)CTE(10 -6 / K)λ(W / m K)C p (J / Kg K) Density (kg / m) 3 ) Silicon 1600.232.6 148700 2330 Alumina 3400.226.8 35850 3900 Copper 1200.35 17.0400 3858900 Molybdenum 3200.324.9 130 250 10220 Epoxy 70.328 1.8800 2100 SAC305-0.35 21.85 72327400

[0166] In addition, the heat transfer coefficient on both sides is 6000 W / m at 150W chip power loss. 2K was set, and the junction temperature of the semiconductor chip (IGBT) and the thermomechanical stress at the intermediate solder standard were measured. In the example, the average diameter of the pores of the unidirectional porous metal spacer was 100 μm to 400 μm, and the pore volume was varied from 30 vol% to 50 vol%.

[0167] Table 3 shows the results of the simulation described above.

[0168] Classification Characteristics Junction Temperature (℃) Maximum Stress (MPa) Comparative Example 1 Copper Spacer 76.0 1 2 9.95 Comparative Example 2 Molybdenum Spacer 79.5 1 2 3.00 Example 1 100 μm + 30 Volume % 77.4 4 2 7.60 Example 2 100 μm + 40 Volume % 77.9 2 2 6.77 Example 3 100 μm + 50 Volume % 78.5 2 2 6.00 Example 4 200 μm + 30 Volume % 77.3 9 2 7.64 Example 5 200 μm + 40 Volume % 78.0 7 2 6.84 Example 6 200 μm + 50 Volume % 78.7 8 2 6.28 Example 7 400 μm + 30 Volume % 77.8 7 2 7.77 Example 8 400 μm + 40 Volume % 78.3327.38 Example 9 400 μm + 50 Volume % 79.0827.04

[0169] Referring to Table 3, the examples have higher junction temperatures than the copper spacer and lower junction temperatures than the molybdenum spacer. On the other hand, the examples have lower maximum stresses, by 7.85% to 13.2%, than the copper spacer and higher maximum stresses than the molybdenum spacer. Therefore, the unidirectional porous metal spacer according to the examples of the present invention is analyzed to have optimal characteristics that are balanced in terms of both junction temperature and maximum stress.

[0170] For reference, the maximum stress refers to the maximum Von-Mises stress. Furthermore, for the cross-sectional cooling power module without a spacer, the junction temperature was 132.92°C.

[0171] It will be apparent to a person skilled in the art to which the technical idea of ​​the present invention pertains that the technical idea of ​​the present invention described above is not limited to the above-described embodiments and the attached drawings, and that various substitutions, modifications, and changes are possible within a scope that does not depart from the technical idea of ​​the present invention.

[0172] [Explanation of symbols]

[0173] 1: One-way porous metal body,

[0174] 2: Metal body,

[0175] 3: One-way pores,

[0176] 100, 100a: Ceramic circuit board,

[0177] 110, 110a: Ceramic substrate,

[0178] 111: Ceramic layer,

[0179] 112: First substrate copper layer,

[0180] 113: Second substrate copper layer,

[0181] 114: First active metal brazing layer,

[0182] 115: Second active metal brazing layer,

[0183] 118: Page 1,

[0184] 119: Second page,

[0185] 120: First unidirectional porous metal spacer,

[0186] 122: First spacer adhesive layer,

[0187] 130: Second unidirectional porous metal spacer,

[0188] 132: Second spacer adhesive layer,

[0189] 140: Heat sink,

[0190] 150: Base plate,

[0191] 170: First semiconductor element,

[0192] 172: First element adhesive layer,

[0193] 180: Second semiconductor element,

[0194] 182: Second element adhesive layer,

[0195] 190: Mold layer,

[0196] 1000, 1000a, 1000b, 1000c: power modules,

Claims

1. A ceramic substrate comprising a ceramic layer and a first substrate copper layer disposed on a first surface of the ceramic layer; and A first unidirectional porous metal spacer having a plurality of pores extending in one direction in a vertical direction from the first substrate copper layer, and disposed on a portion of the first substrate copper layer. Ceramic circuit board.

2. In paragraph 1, The above first unidirectional porous metal spacer is, Having a porosity ranging from 1% by volume to 70% by volume, Ceramic circuit board.

3. In paragraph 1, The above first unidirectional porous metal spacer is, Consisting of a metal casting formed using a mold casting method, continuous melt casting method, continuous casting method, or centrifugal casting method. Ceramic circuit board.

4. In paragraph 1, The above first unidirectional porous metal spacer is, A metal body formed by pressing, rolling, and then punching, laser processing, or selective etching a metal material in the shape of a sheet, plate, sheet, or foil. Ceramic circuit board.

5. In paragraph 1, The above first unidirectional porous metal spacer is, Containing copper or copper alloy, Ceramic circuit board.

6. In paragraph 1, A second unidirectional porous metal spacer is further included, which is disposed on a portion of the first substrate copper layer, has a plurality of pores extending in one direction in a vertical direction from the first substrate copper layer, and has a greater height than the first unidirectional porous metal spacer. Ceramic circuit board.

7. In paragraph 6, The above second unidirectional porous metal spacer is, Having a porosity ranging from 1% by volume to 70% by volume, Ceramic circuit board.

8. In paragraph 6, The above second unidirectional porous metal spacer is, Consisting of a metal casting formed using a mold casting method, continuous melt casting method, continuous casting method, or centrifugal casting method. Ceramic circuit board.

9. In paragraph 6, The above second unidirectional porous metal spacer is, A metal body formed by pressing, rolling, and then punching, laser processing, or selective etching a metal material in the shape of a sheet, plate, sheet, or foil. Ceramic circuit board.

10. In paragraph 1, The first substrate copper layer is, A DBC copper layer formed by bonding copper foil on the above ceramic layer through a high-temperature oxidation process, After forming a seed layer on the above ceramic layer, a DPC copper layer formed by plating copper on the seed layer, Or, it is made of an AMB copper layer formed by a copper foil bonded using an active metal foil to the above ceramic layer. Ceramic circuit board.

11. In paragraph 1, The above ceramic substrate, Further comprising a second substrate copper layer disposed on the second surface of the ceramic layer, Ceramic circuit board.

12. An upper ceramic circuit board comprising: an upper ceramic substrate including an upper ceramic layer and an upper first substrate copper layer; an upper first unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the first substrate copper layer; and an upper second unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the upper first substrate copper layer, the upper ceramic circuit board having a greater height than the upper first unidirectional porous metal spacer. A lower ceramic substrate comprising a lower ceramic layer and a lower first substrate copper layer; A first semiconductor element disposed between the upper first unidirectional porous metal spacer and the lower first substrate copper layer; A second semiconductor element disposed between the upper second unidirectional porous metal spacer and the lower first substrate copper layer, and having a smaller thickness than the first semiconductor element; and A mold layer that fills the space between the upper ceramic circuit board and the lower ceramic substrate and covers the first semiconductor element and the second semiconductor element, Power module.

13. In paragraph 12, an upper heat sink disposed on the outside of the upper ceramic circuit board; and Further comprising at least one lower heat sink disposed on the outer side of the lower ceramic substrate; Power module.

14. In paragraph 12, The upper ceramic substrate further includes an upper first active metal brazing layer interposed between the upper ceramic layer and the upper first substrate copper layer, The lower ceramic substrate further comprises a lower first active metal brazing layer interposed between the lower ceramic layer and the lower first substrate copper layer. Power module.

15. An upper ceramic circuit board comprising: an upper ceramic substrate including an upper ceramic layer and an upper first substrate copper layer; an upper first unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the first substrate copper layer; and an upper second unidirectional porous metal spacer disposed on a portion of the upper first substrate copper layer and having a plurality of pores extending vertically in one direction from the upper first substrate copper layer, the upper ceramic circuit board having a greater height than the upper first unidirectional porous metal spacer. A lower ceramic circuit board comprising: a lower ceramic substrate including a lower ceramic layer and a lower first substrate copper layer; a lower first unidirectional porous metal spacer disposed on a portion of the lower first substrate copper layer and having a plurality of pores extending vertically in one direction from the first substrate copper layer; and a lower second unidirectional porous metal spacer disposed on a portion of the lower first substrate copper layer and having a plurality of pores extending vertically in one direction from the lower first substrate copper layer, the lower ceramic circuit board having a greater height than the lower first unidirectional porous metal spacer. A first semiconductor element disposed between the upper first unidirectional porous metal spacer and the lower first unidirectional porous metal spacer; A second semiconductor element disposed between the upper second unidirectional porous metal spacer and the lower second unidirectional porous metal spacer, and having a smaller thickness than the first semiconductor element; and A mold layer that fills the space between the upper ceramic circuit board and the lower ceramic circuit board and covers the first semiconductor element and the second semiconductor element, Power module.

16. In paragraph 15, an upper heat sink disposed on the outside of the upper ceramic circuit board; and Further comprising at least one lower heat sink disposed on the outer side of the lower ceramic circuit board; Power module.

17. In paragraph 15, The upper ceramic substrate further includes an upper first active metal brazing layer interposed between the upper ceramic layer and the upper first substrate copper layer, The lower ceramic substrate further comprises a lower first active metal brazing layer interposed between the lower ceramic layer and the lower first substrate copper layer. Power module.

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