Transistor device and manufacturing method therefor, and display substrate

Abstract

A transistor device and a manufacturing method therefor, and a display substrate. The transistor device is disposed on a substrate (30); the transistor device comprises a gate electrode (31), a gate insulating layer (35), and an active layer (32); the gate electrode (31) is located on the side of the gate insulating layer (35) close to the substrate (30); the active layer (32) is located on the side of the gate insulating layer (35) distant from the substrate (30); the gate insulating layer (35) comprises a first insulating layer (351) and a second insulating layer (352) which are stacked on the substrate (30); a via hole (VV) is formed in one of the first insulating layer (351) and the second insulating layer (352); and the orthographic projection of the via hole (VV) on the substrate (30) at least partially overlaps the orthographic projection of the active layer (32) on the substrate (30).

Description

Transistor devices and their fabrication methods, display substrates

[0001] This application claims priority to Chinese Patent Application No. PCT / CN2024 / 108632, filed on July 30, 2024, entitled “Display Substrate and Method for Preparing the Same”, the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a transistor device and its fabrication method, and a display substrate. Background Technology

[0003] In recent years, thin-film transistor (TFT) flat panel displays have been widely used in various fields of social production and daily life, including watches, mobile phones, tablets, desktop computers, automotive displays, industrial IoT displays, and televisions. With the expansion of flat panel display applications, display technologies with excellent image quality, high smoothness, high touch performance, high refresh rate, and high touch frequency have become the cutting edge in the display industry. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a transistor device, a method for fabricating the same, and a display substrate.

[0006] In a first aspect, this disclosure provides a transistor device disposed on a substrate. The transistor device includes: a gate electrode, a gate insulating layer, and an active layer. The gate electrode is located on the side of the gate insulating layer close to the substrate, and the active layer is located on the side of the gate insulating layer away from the substrate. The gate insulating layer includes: a first insulating layer and a second insulating layer stacked on the substrate, wherein one of the first insulating layer and the second insulating layer has a via.

[0007] The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

[0008] In an exemplary embodiment, the orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the via on the substrate, or the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate.

[0009] In an exemplary embodiment, it further includes: a first electrode and a second electrode disposed on the side of the active layer away from the substrate;

[0010] When the orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the via on the substrate, the minimum distance between the orthographic projection of at least one boundary of at least one of the first electrode and the second electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the active layer extending along the first direction on the substrate is greater than a first alignment deviation threshold.

[0011] In an exemplary embodiment, at least a portion of the first electrode is U-shaped, the first electrode includes an opening facing the second electrode, and the first electrode partially surrounds the second electrode, the second electrode extending at least a portion along a first direction.

[0012] In an exemplary embodiment, the orthographic projection of the first electrode on the substrate is within the range of the orthographic projection of the active layer on the substrate, the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate, and there is a non-overlapping region with the orthographic projection of the gate electrode on the substrate.

[0013] In an exemplary embodiment, when the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a plurality of boundaries, the plurality of boundaries including: a first boundary, the first boundary extending along a second direction, the first direction intersecting the second direction;

[0014] The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of at least one boundary of the via, excluding the first boundary, on the substrate; the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first boundary of the via on the substrate.

[0015] The distance between the orthographic projection of at least one boundary of the first electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the via extending along the first direction (excluding the first boundary) on the substrate is greater than the second alignment deviation threshold.

[0016] In an exemplary embodiment, the number of transistor devices is two, and the first transistor device and the second transistor device are arranged at least partially symmetrically with respect to a straight line extending along the second direction;

[0017] The second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

[0018] In an exemplary embodiment, when the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the first electrode includes: a first branch segment, a second branch segment, and a connecting segment, wherein the first branch segment and the second branch segment are respectively connected to the connecting segment, the first branch segment and the second branch segment extend along a first direction, and the connecting segment extends along a second direction;

[0019] At least one of the first branch segment and the second branch segment overlaps at least partially with the orthographic projection of the via on the substrate, and the orthographic projection of the connecting segment on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate.

[0020] In an exemplary embodiment, the via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary and the second boundary extend along a second direction and are disposed opposite to each other, and the third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other;

[0021] The orthographic projection of the first branch segment on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary, the second boundary, and the third boundary on the substrate; the orthographic projection of the second branch segment on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary, the second boundary, and the fourth boundary on the substrate; and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary and the second boundary on the substrate.

[0022] In an exemplary embodiment, the distance between the boundary of at least one of the first branch segment and the second branch segment away from the boundary of the connecting segment and the first boundary is a first distance, and the distance between the boundary of the second electrode near the boundary of the connecting segment and the second boundary is a second distance;

[0023] The first distance is equal to the second distance, and at least one of the first distance and the second distance is greater than the third alignment deviation threshold;

[0024] The distance between the orthographic projection of the first boundary on the substrate and the orthographic projection of the connecting segment on the substrate is greater than the distance between the orthographic projection of the second boundary on the substrate and the orthographic projection of the connecting segment on the substrate.

[0025] In an exemplary embodiment, at least one of the first electrode and the second electrode extends along a first direction;

[0026] The orthographic projection of at least one of the first electrode and the second electrode onto the substrate at least partially overlaps with the orthographic projection of the active layer onto the substrate, and there is a non-overlapping region with the orthographic projection of the gate electrode onto the substrate.

[0027] In an exemplary embodiment, when the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a second direction and are disposed opposite to each other. The third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other. The length of at least one of the first boundary and the second boundary is less than the length of at least one of the third boundary and the fourth boundary.

[0028] The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of at least one of the second boundary and the third boundary on the substrate, and there is no overlap with the orthographic projection of at least one of the first boundary and the fourth boundary on the substrate; the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary and the fourth boundary on the substrate, and there is no overlap with the orthographic projection of at least one of the second boundary and the third boundary on the substrate.

[0029] In an exemplary embodiment, when the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a second direction and are disposed opposite to each other. The third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other. The length of at least one of the first boundary and the second boundary is greater than or equal to the length of at least one of the third boundary and the fourth boundary.

[0030] The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projections of at least one of the first boundary, the second boundary, and the third boundary on the substrate, and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projections of at least one of the first boundary, the second boundary, and the fourth boundary on the substrate.

[0031] In an exemplary embodiment, when the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a second direction and are disposed opposite to each other. The third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other. The length of at least one of the first boundary and the second boundary is greater than the length of at least one of the third boundary and the fourth boundary.

[0032] The orthographic projection of at least one of the first and second electrodes on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second boundaries on the substrate, and there is no overlap with the orthographic projection of at least one of the third and fourth boundaries on the substrate.

[0033] In an exemplary embodiment, the via includes: a plurality of boundaries, the plurality of boundaries including: a first boundary and a second boundary, the first boundary and the second boundary extending along a second direction and disposed opposite to each other;

[0034] The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the first boundary on the substrate, and there is no overlap with the orthographic projections of the other boundaries on the substrate except for the first boundary. The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the second boundary on the substrate, and there is no overlap with the orthographic projections of the other boundaries on the substrate except for the second boundary.

[0035] In an exemplary embodiment, the distance between the orthographic projection of the target boundary of the first electrode on the substrate and the orthographic projection of the second boundary on the substrate is equal to the distance between the orthographic projection of the target boundary of the second electrode on the substrate and the orthographic projection of the first boundary on the substrate, and is greater than the third alignment deviation.

[0036] At least one of the first electrode and the second electrode overlaps with the orthographic projection of the gate electrode on the substrate, and the boundary extending along the second direction is the target boundary. The distance between the orthographic projection of the target boundary of the first electrode on the substrate and the orthographic projection of the second boundary on the substrate is less than the distance between the orthographic projection of the target boundary of the first electrode on the substrate and the orthographic projection of the first boundary on the substrate. The distance between the orthographic projection of the target boundary of the second electrode on the substrate and the orthographic projection of the first boundary on the substrate is greater than the distance between the orthographic projection of the target boundary of the second electrode on the substrate and the orthographic projection of the first boundary on the substrate.

[0037] In an exemplary embodiment, the minimum distance between the orthographic projection of the boundary of the first electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the via extending along the first direction on the substrate is equal to the minimum distance between the orthographic projection of the boundary of the second electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the via extending along the first direction on the substrate, and is greater than the second alignment deviation threshold.

[0038] In an exemplary embodiment, the second electrode extends along a first direction;

[0039] The first electrode includes: a first connecting portion, a second connecting portion, a third connecting portion, and a fourth connecting portion; the first connecting portion and the fourth connecting portion extend along a second direction, and the third connecting portion extends along a first direction; the second connecting portion is connected to the first connecting portion and the third connecting portion respectively, and is disposed at an obtuse angle to the first connecting portion and the third connecting portion respectively; the first connecting portion, the second connecting portion, and the third connecting portion at least partially surround the second electrode; the fourth connecting portion is connected to the third connecting portion and is located on the side of the third connecting portion away from at least one of the first connecting portion and the second connecting portion.

[0040] The orthographic projection of at least one of the second and third connecting portions on the substrate is within the range of the orthographic projection of the active layer on the substrate. The orthographic projections of the first connecting portion, the fourth connecting portion, and the second electrode on the substrate at least partially overlap with the orthographic projection of the active layer on the substrate, and there is a non-overlapping region with the orthographic projection of the gate electrode on the substrate.

[0041] In an exemplary embodiment, when the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the orthographic projections of the second connection portion and the third connection portion on the substrate are within the range of the orthographic projection of the via on the substrate.

[0042] The via includes multiple boundaries, wherein the orthographic projection of at least one of the structures of the second electrode, the first connection portion, and the fourth connection portion onto the substrate at least partially overlaps with the orthographic projection of at least one of the multiple boundaries of the via onto the substrate.

[0043] In an exemplary embodiment, the via includes: a first boundary, a second boundary, a third boundary, a fourth boundary, a fifth boundary, a sixth boundary, and a seventh boundary; the first boundary, the fourth boundary, and the sixth boundary extend along a second direction, and the third boundary, the fifth boundary, and the seventh boundary extend along a first direction, and the first boundary to the seventh boundary are connected sequentially;

[0044] The second boundary is set at an obtuse angle to the first boundary and the third boundary, the third boundary is set at a right angle to the fourth boundary, the fourth boundary is set at a right angle to the fifth boundary, the fifth boundary is set at a right angle to the sixth boundary, the sixth boundary is set at a right angle to the seventh boundary, the seventh boundary is set at a right angle to the first boundary, and the distance between the sixth boundary and the first boundary is less than the distance between the fourth boundary and the first boundary;

[0045] The orthographic projection of the first boundary on the substrate is within the range of the orthographic projection of the first connecting portion on the substrate, the orthographic projection of the second boundary on the substrate is within the range of the orthographic projection of the second connecting portion on the substrate, the orthographic projection of the third connecting portion on the substrate at least partially overlaps with the orthographic projection of the third boundary on the substrate, and the length of the third connecting portion is less than the length of the third boundary, and the orthographic projection of the fourth connecting portion on the substrate does not overlap with the orthographic projection of at least one of the first boundary to the seventh boundary on the substrate.

[0046] The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projections of the fourth boundary and the sixth boundary on the substrate, and covers the orthographic projection of the fifth boundary on the substrate;

[0047] The second electrode is close to the third boundary, and the distance between the boundary extending along the first direction and the fifth boundary is greater than the second alignment deviation threshold.

[0048] The distance between the second electrode near the first boundary and the boundary extending along the first direction and the seventh boundary is equal to the distance between the third connection near the fourth boundary and the boundary extending along the second direction and the fourth boundary, and is greater than the third alignment deviation threshold.

[0049] In an exemplary embodiment, the number of transistor devices is two, and the target transistor device is at least partially symmetrical with respect to the straight line extending along the second direction with respect to the first direction.

[0050] The second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

[0051] In an exemplary embodiment, the active layer includes: a first active layer and a second active layer, the second active layer being disposed on the side of the first active layer away from the substrate, and the second active layer including: a first active structure and a second active structure;

[0052] The orthographic projection of the second active layer on the substrate is within the range of the orthographic projection of the first active layer on the substrate, the orthographic projection of the first active structure on the substrate is within the range of the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second active structure on the substrate is within the range of the orthographic projection of the second electrode on the substrate.

[0053] The thickness of the first active layer is greater than the thickness of the second active layer, and the conductivity of the second active layer is greater than that of the first active layer.

[0054] At least one of the first electrode and the second electrode covers at least a portion of the sidewalls of the first active layer and the second active layer, as well as the surface of the second active layer away from the substrate;

[0055] The orthographic projection of at least one of the first electrode and the second electrode onto the substrate at least partially overlaps with the orthographic projection of the insulating layer on the substrate having the via.

[0056] In an exemplary embodiment, the maximum distance between the surface of the gate insulating layer away from the substrate and the surface of the gate electrode away from the substrate is in the range of 3800 angstroms to 4200 angstroms;

[0057] The first insulating layer is made of one of silicon oxide and silicon nitride, and the second insulating layer is made of the other of silicon oxide and silicon nitride.

[0058] Secondly, this disclosure also provides a display substrate, including: a display area and a non-display area disposed on at least one side of the display area, wherein the non-display area is provided with a gate driving circuit, the gate driving circuit including: a plurality of cascaded shift registers, at least one of the shift registers including: a plurality of transistors, wherein at least one of the plurality of transistors is the aforementioned transistor device.

[0059] In an exemplary embodiment, the display substrate includes: a substrate and a gate insulating layer disposed on the substrate, the gate insulating layer including: a first insulating layer and a second insulating layer stacked on the substrate, one of the first insulating layer and the second insulating layer being provided with a first device via.

[0060] At least one transistor includes: an input transistor, the input transistor being electrically connected to a signal input terminal and a pull-up node, respectively;

[0061] The orthographic projection of the active layer of the input transistor onto the substrate at least partially overlaps with the orthographic projection of the first device via onto the substrate.

[0062] In an exemplary embodiment, the display substrate includes: a substrate and a gate insulating layer disposed on the substrate, the gate insulating layer including: a first insulating layer and a second insulating layer stacked on the substrate, one of the first insulating layer and the second insulating layer being provided with a second device via;

[0063] At least one shift register includes an output transistor, which is electrically connected to a pull-up node, a signal output terminal, and a clock signal terminal, respectively.

[0064] The orthographic projection of the active layer of the output transistor onto the substrate at least partially overlaps with the orthographic projection of the second device via onto the substrate.

[0065] In an exemplary embodiment, at least one level shift register further includes: a capacitor, the capacitor including a first plate and a second plate;

[0066] The orthographic projection of at least one of the first and second plates of the capacitor onto the substrate at least partially overlaps with the orthographic projection of the via of the second device onto the substrate.

[0067] In an exemplary embodiment, the display substrate includes: a substrate and the circuit structure layer disposed on the substrate, the circuit structure layer including: a first conductive layer, a semiconductor layer and a second conductive layer sequentially stacked on the substrate;

[0068] The first conductive layer includes: control electrodes of a plurality of transistors located in at least one level shift register;

[0069] The semiconductor layer includes: an active layer of multiple transistors located in at least one level shift register;

[0070] The second conductive layer includes: a first electrode and a second electrode of a plurality of transistors located in at least one level shift register.

[0071] In an exemplary embodiment, it further includes: a plurality of clock signal lines, a first power line, a second power line, a third power line, and a total reset signal line disposed on the substrate; at least one of the plurality of clock signal lines, the first power line, the second power line, the third power line, and the total reset signal line extends at least partially along a third direction and is located in the first conductive layer;

[0072] At least one of the first and second electrodes of at least one transistor in at least one level shift register is electrically connected to a first power supply terminal; at least one of the first and second electrodes of at least one transistor in at least one level shift register is electrically connected to a second power supply terminal; the second electrode of at least one transistor in at least one level shift register is electrically connected to a third power supply terminal; and the control electrode of at least one transistor in at least one level shift register is electrically connected to the total reset signal line.

[0073] The clock signal terminal in at least one level shift register is electrically connected to one of the multiple clock signal lines, the clock signal terminals in adjacent shift registers are connected to different clock signal lines, the first power supply terminal in at least one level shift register is electrically connected to the first power supply terminal, the second power supply terminal in at least one level shift register is electrically connected to the second power supply terminal, and the total reset signal terminal in at least one level shift register is electrically connected to the total reset signal line.

[0074] Multiple transistors include: input transistors and output transistors;

[0075] The orthographic projection of at least one of the multiple clock signal lines, the first power supply line, the second power supply line, and the third power supply line on the substrate is located on the side of the orthographic projection of multiple transistors on the substrate in at least one level shift register that is far from the display area. The orthographic projection of the total reset signal line on the substrate is located between the orthographic projections of multiple transistors on the substrate, and between the orthographic projections of the output transistor on the substrate and the orthographic projections of the input transistor on the substrate.

[0076] Thirdly, this disclosure also provides a method for fabricating a transistor device, configured to fabricate the aforementioned transistor device, the method comprising:

[0077] The gate electrode of a transistor device is formed on the substrate;

[0078] A gate insulating layer and an active layer of a transistor device are formed on the gate electrode. The gate insulating layer includes a first insulating layer and a second insulating layer stacked on the substrate. One of the first insulating layer and the second insulating layer has a via. The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

[0079] In an exemplary embodiment, forming the gate insulating layer and active layer of the transistor device on the gate electrode includes:

[0080] A first insulating layer is formed on the gate electrode;

[0081] A primary semiconductor layer is formed on the first insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer;

[0082] A second insulating layer is formed on a substrate on which the original semiconductor layer is formed, and the second insulating layer is provided with vias;

[0083] A first electrode, a second electrode, and an active layer are formed on a substrate on which a second insulating layer is formed, wherein the active layer comprises a first active layer and a second active layer.

[0084] In an exemplary embodiment, forming the gate insulating layer and active layer of the transistor device on the gate electrode includes:

[0085] A first insulating layer is formed on the gate electrode;

[0086] A barrier layer is formed on the first insulating layer;

[0087] A second insulating layer is formed on the barrier layer, and the second insulating layer is provided with a via, the via exposing the barrier layer;

[0088] Remove the blocking layer;

[0089] A primary semiconductor layer is formed on the second insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer;

[0090] A first electrode, a second electrode, and an active layer are formed on the original semiconductor layer. The active layer includes a first active layer and a second active layer.

[0091] In an exemplary embodiment, forming the gate insulating layer and active layer of the transistor device on the gate electrode includes:

[0092] A first insulating layer is formed on the gate electrode, and the first insulating layer has a via.

[0093] A second insulating layer is formed from the first insulating layer;

[0094] A primary semiconductor layer is formed on the second insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer;

[0095] A first electrode, a second electrode, and an active layer are formed on the original semiconductor layer. The active layer includes a first active layer and a second active layer.

[0096] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood.

[0097] Overview of the attached figures

[0098] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0099] Figure 1 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0100] Figure 2 is a schematic diagram of the structure of some of the membrane layers provided in Figure 1;

[0101] Figure 3 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0102] Figure 4 is a schematic diagram of the structure of some of the membrane layers provided in Figure 3;

[0103] Figure 5 is a top view of the transistor device shown in Figures 1 and 3;

[0104] Figure 6 is a curve showing the relationship between the gate insulation layer thickness and the Ion normalization coefficient;

[0105] Figure 7 shows the curves of the voltage Vg of the gate electrode and the current Id flowing through the source electrode under different gate insulation layer thicknesses.

[0106] Figure 8 is a top view of a transistor device;

[0107] Figure 9 is a cross-sectional view along direction AA in Figure 8;

[0108] Figure 10 is a cross-sectional view along the BB direction of Figure 8;

[0109] Figure 11 is a schematic diagram of a display substrate structure;

[0110] Figure 12 is another schematic diagram of the display substrate structure;

[0111] Figure 13 is a schematic diagram after the gate electrode is formed in Figure 11;

[0112] Figure 14 is a schematic diagram after the grid insulating layer is formed in Figure 11;

[0113] Figure 15 is a schematic diagram after the formation of the original semiconductor layer in Figure 11;

[0114] Figure 16 is a schematic diagram after the first and second electrodes in Figure 11 are formed;

[0115] Figure 17 is a schematic diagram after the passivation layer is formed in Figure 11;

[0116] Figure 18 is a schematic diagram after the gate insulating layer is formed in Figure 12;

[0117] Figure 19 is a schematic diagram after the original semiconductor layer in Figure 12 has been formed;

[0118] Figure 20 is a schematic diagram after the first and second electrodes in Figure 12 are formed;

[0119] Figure 21 is a schematic diagram of the passivation layer formed in Figure 12;

[0120] Figure 22 is a cross-sectional schematic diagram of the transistor device provided in an embodiment of this disclosure;

[0121] Figure 23 is a second cross-sectional schematic diagram of the transistor device provided in the embodiments of this disclosure;

[0122] Figure 24 is a cross-sectional schematic diagram of the transistor device provided in the embodiments of this disclosure;

[0123] Figure 25 is a cross-sectional schematic diagram of the transistor device provided in the embodiments of this disclosure;

[0124] Figure 26 is a partial cross-sectional schematic diagram of the transistor device provided in Figures 22 and 23;

[0125] Figure 27 is a partial cross-sectional schematic diagram of the transistor device provided in Figures 24 and 25;

[0126] Figure 28 is a top view of a transistor device;

[0127] Figure 29 is a top view of a transistor device;

[0128] Figure 30 is a top view of a transistor device;

[0129] Figure 31 is a top view of a transistor device;

[0130] Figure 32 is a top view of a transistor device;

[0131] Figure 33 is a top view of a transistor device;

[0132] Figure 34 is a top view of a transistor device;

[0133] Figure 35 is a top view of a transistor device.

[0134] Figure 36 is a top view of a transistor device (nine).

[0135] Figure 37 is a top view of a transistor device;

[0136] Figure 38 is a top view of a transistor device;

[0137] Figure 39 is a top view of a transistor device.

[0138] Figure 40 is a top view of a transistor device.

[0139] Figures 41a to 41e are flowcharts of the fabrication method of the transistor device provided in Figure 22;

[0140] Figures 42a to 42d are flowcharts of the fabrication method of the transistor device provided in Figure 22;

[0141] Figures 43a to 43d are flowcharts of the fabrication method of the transistor device provided in Figure 24;

[0142] Figure 44 is a schematic flowchart of the fabrication method of transistor devices;

[0143] Figure 45 is a schematic diagram of the planar structure of the display substrate;

[0144] Figure 46 is the equivalent circuit diagram of at least one shift register;

[0145] Figure 47 is the timing diagram of the shift register provided in Figure 46;

[0146] Figure 48 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0147] Figure 49 is a schematic diagram of part of the film layers in Figure 48;

[0148] Figure 50 is a schematic diagram after the first conductive layer pattern is formed in Figure 48;

[0149] Figure 51 is a schematic diagram after the grid insulating layer pattern is formed in Figure 48;

[0150] Figure 52 is a schematic diagram of the semiconductor layer pattern in Figure 48;

[0151] Figure 53 is a schematic diagram after the semiconductor layer pattern is formed in Figure 48;

[0152] Figure 54 is a schematic diagram of the second conductive layer pattern in Figure 48;

[0153] Figure 55 is a schematic diagram of the second conductive layer pattern formed in Figure 48.

[0154] Detailed Explanation

[0155] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0156] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0157] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0158] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0159] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0160] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0161] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0162] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0163] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0164] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0165] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0166] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0167] Due to the limitations of transistors' semiconductor characteristics, namely the limitation of carrier mobility, it is difficult to further increase the turn-on current of transistors, thus limiting the improvement of the refresh rate of display products.

[0168] Therefore, this disclosure provides a transistor device.

[0169] Figure 1 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure; Figure 2 is a schematic diagram of the structure of a portion of the film layer provided in Figure 1; Figure 3 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure; and Figure 4 is a schematic diagram of the structure of a portion of the film layer provided in Figure 3. As shown in Figures 1 to 4, the display substrate provided in an embodiment of this disclosure may include: a substrate and a transistor device disposed on the substrate. The transistor device may include: a gate electrode 11, a gate insulating layer 21, and an active layer 12 sequentially stacked on the substrate 10. In Figures 1 to 4, the second direction Y is the direction in which the gate electrode, the gate insulating layer, and the active layer are stacked, and the first direction X may be the extension direction of the active layer. The first direction X intersects with the second direction Y.

[0170] As shown in Figures 1 to 4, a groove structure 1 is provided on the side of the gate insulating layer 21 away from the substrate 10. At least a portion of the active layer 12 is disposed within the groove structure 1, and at least two boundaries of the active layer 12 have a predetermined distance from the corresponding boundaries of the groove structure. That is, the orthographic projection of the active layer 12 on the substrate 10 in this disclosure is within the range of the orthographic projection of the groove structure 1 on the substrate 10, and the entire width of the longitudinal section of the active layer 12 falls within the groove structure 1.

[0171] In an exemplary embodiment, the substrate 10 may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and conductive foil. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0172] In an exemplary embodiment, the transistor device in this disclosure has a bottom-gate structure.

[0173] In an exemplary embodiment, the gate electrode 11 can be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the gate electrode can be made of Al / Mo or MoNb / Cu.

[0174] In an exemplary embodiment, the gate insulating layer 21 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0175] In an exemplary embodiment, the active layer material may comprise one or more of amorphous silicon (a-Si) and low-temperature polycrystalline silicon (LTPS) metal oxides. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc.

[0176] In some embodiments, the active layer material can be M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0 and b ≥ 0, O represents oxygen, and N represents nitrogen. That is, the active layer material is a metal oxide material or a metal nitride material. Suitable metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth doped oxides (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0177] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material for the channel region CH1 / CH2 / CH3 includes indium gallium zinc oxide (IGZO). The active layer material can be amorphous, partially crystalline, single-crystal, or polycrystalline, and can also be a single-layer or multi-layer structure.

[0178] In an exemplary embodiment, the transistor device further includes a first electrode 13 and a second electrode 14 located on the side of the active layer 12 away from the substrate 10, wherein the first electrode 13 and the second electrode 14 are respectively connected to the active layer 12. In an exemplary embodiment, the first electrode 13 may be one of a source electrode and a drain electrode, and the second electrode 14 may be the other of a source electrode and a drain electrode.

[0179] In an exemplary embodiment, the first electrode 13 and the second electrode 14 can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), niobium (Nb), neodymium (Nd), nickel (Ni), and molybdenum (Mo), or alloys composed of at least two of the above metals, such as aluminum-neodymium alloy (AlNd), titanium-aluminum alloy (TiAl), molybdenum-nickel-titanium alloy (Mo-Ni-Ti, MTD), or molybdenum-niobium alloy (MoNb). They can also be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. Exemplarily, the first electrode 13 and the second electrode 14 can be made of Mo / Al / Mo, MoNb / Cu, MTD / Cu / MTD, or Cu / MTD.

[0180] In an exemplary embodiment, the transistor's turn-on current Ion satisfies the following formula: Ion=(W / L)*C*[(V gs -V th )*V ds -0.5*(V ds ) 2 ]

[0181] Where W is the width of the channel region of the active layer, L is the length of the channel region of the active layer, C is the parasitic capacitance between the channel region of the active layer and the gate electrode, and V gs V is the voltage difference between the gate and source electrodes of a transistor. ds V is the voltage difference between the drain and source electrodes of a transistor. th This represents the threshold voltage of the transistor. From the above formula, it can be seen that the transistor's turn-on current Ion depends on parameters C, W, L, and V. gs V th and V ds .

[0182] This disclosure provides a groove structure on the side of the gate insulating layer away from the substrate, with at least a portion of the active layer disposed within the groove structure, and at least two boundaries of the active layer having a predetermined distance from the corresponding boundaries of the groove structure. This reduces the thickness of the gate insulating layer that overlaps with the active layer, increases the capacitance value of the parasitic capacitance between the channel region of the active layer and the gate electrode, increases the turn-on current of the transistor device, and thus improves the refresh rate of the display product.

[0183] In an exemplary embodiment, as shown in Figures 2 and 4, the gate insulating layer 21 includes a first region R1 and a second region R2, wherein the second region R2 comprises all regions except the first region R1, and the second region R2 surrounds at least one side of the first region R1.

[0184] In an exemplary embodiment, as shown in Figures 2 and 4, the groove structure 1 is located in the first region R1, and the thickness H1 of the gate insulating layer 21 located in the first region R1 is less than the thickness H2 of the gate insulating layer 21 located in the second region R2.

[0185] In an exemplary embodiment, FIG5 is a top view of the transistor device provided in FIG1 and FIG3. As shown in FIG5, the orthographic projection of the groove structure 1 on the substrate is within the range of the orthographic projection of the gate electrode 11 on the substrate.

[0186] In an exemplary embodiment, the shape of the cross-section of the groove structure along the direction parallel to the substrate can be circular, square, rectangular, or other shapes, and this disclosure does not limit it in any way. Figure 5 illustrates an example where the cross-section of the groove structure along the direction parallel to the substrate is square.

[0187] In an exemplary embodiment, as shown in Figures 1, 3, and 5, the active layer 12 may include a first active layer 121 and a second active layer 122. The second active layer 122 is disposed on the side of the first active layer 121 away from the substrate 10.

[0188] In an exemplary embodiment, as shown in FIG5, the orthographic projection of the second active layer 122 on the substrate 10 may be within the range of the orthographic projection of the first active layer 121 on the substrate 10.

[0189] In an exemplary embodiment, the thickness of the first active layer 121 is greater than the thickness of the second active layer 122.

[0190] In an exemplary embodiment, the conductivity of the second active layer 122 is greater than that of the first active layer 121.

[0191] In an exemplary embodiment, the first active layer 121 may be an amorphous silicon layer or a metal oxide layer.

[0192] In an exemplary embodiment, the second active layer 122 is an N-type semiconductor layer. Exemplarily, the second active layer 122 is an N-type doped amorphous silicon layer or a metal oxide layer.

[0193] In an exemplary embodiment, as shown in Figures 1 and 3, the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is less than or equal to the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 in the second region away from the substrate 10. Figures 1 and 3 show that the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is equal to the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 in the second region away from the substrate 10.

[0194] In an exemplary embodiment, as shown in Figures 1 and 3, the distance L3 between the surface of the second active layer 122 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is greater than the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10.

[0195] In an exemplary embodiment, as shown in Figures 1 and 3, at least a portion of the second active layer 122 is projected onto the substrate 10 within the range of the first electrode 13 projected onto the substrate 10, i.e., the first electrode 13 covers at least a portion of the second active layer.

[0196] In an exemplary embodiment, as shown in Figures 1 and 3, at least a portion of the second active layer 122 is projected onto the substrate 10 within the range of the second electrode 14 projected onto the substrate 10, i.e., the second electrode 14 covers at least a portion of the second active layer.

[0197] In an exemplary embodiment, as shown in Figures 1, 3 and 5, at least one of the first electrode 13 and the second electrode 14 partially fills the groove structure 1 and covers the sidewall of the active layer 12.

[0198] In an exemplary embodiment, as shown in Figures 1, 3, and 5, the orthographic projection of at least one of the first electrode 13 and the second electrode 14 onto the substrate 10 at least partially overlaps with the orthographic projection of the gate insulating layer 21 located in the second region onto the substrate 10. This at least partial overlap ensures that the first and second electrodes can make sufficient contact with the active layer 12.

[0199] In an exemplary embodiment, as shown in Figures 1 and 2, the gate insulating layer 21 can be a single-layer structure.

[0200] In an exemplary embodiment, as shown in FIG2, the thickness H1 of the gate insulating layer 21 located in the first region R1 is in the range of 2000 angstroms to 3500 angstroms. Exemplarily, the thickness H1 of the gate insulating layer 21 located in the first region R1 can be 2000 angstroms.

[0201] In an exemplary embodiment, when the gate insulating layer 21 is a single-layer structure, the material used to fabricate the gate insulating layer 21 may include silicon oxide or silicon nitride.

[0202] In an exemplary embodiment, as shown in FIG2, the distance H between the surface of the gate insulating layer 21 in the second region R2 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800 angstroms to 4200 angstroms. Exemplarily, the distance H between the surface of the gate insulating layer 21 in the second region R2 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 can be 4000 angstroms.

[0203] In an exemplary embodiment, when the gate insulating layer is a single-layer structure, the thickness of the gate insulating layer is the same as the thickness of the gate insulating layer located in the second region. The thickness of the gate insulating layer is in the range of 3800 angstroms to 4200 angstroms.

[0204] In an exemplary embodiment, the distance H between the surface of the gate insulating layer 21 located in the second region R2 away from the substrate 10 and the surface of the gate electrode 11 located away from the substrate 10 can be controlled by the etching time of the gate insulating layer.

[0205] In an exemplary embodiment, as shown in Figures 3 and 4, the gate insulating layer 21 may include a first gate insulating layer 22 and a second gate insulating layer 23 sequentially stacked on the substrate 10.

[0206] In an exemplary embodiment, as shown in FIG4, the second gate insulating layer 23 has a via V that exposes the first gate insulating layer 22, and the via V of the second gate insulating layer 23 and the first gate insulating layer 22 form a groove structure 1.

[0207] In an exemplary embodiment, as shown in FIG4, the orthographic projection of the active layer 12 on the substrate 10 is within the range of the orthographic projection of the via V on the substrate 10.

[0208] In an exemplary embodiment, as shown in FIG4, the thickness H2 of the first gate insulating layer 22 is in the range of 2000 angstroms to 3500 angstroms. Exemplarily, the thickness H3 of the first gate insulating layer 22 can be 2000 angstroms. In this exemplary embodiment, the thinner the first gate insulating layer, the more significant the improvement in the turn-on current of the transistor device.

[0209] In an exemplary embodiment, as shown in FIG3, the distance H between the surface of the second gate insulating layer 23 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800 angstroms to 4200 angstroms.

[0210] In an exemplary embodiment, when the gate insulating layer has a double-layer structure, the thickness of the gate insulating layer is equal to the sum of the thicknesses of the first and second gate insulating layers. The thickness of the gate insulating layer is in the range of 3800 angstroms to 4200 angstroms.

[0211] In an exemplary embodiment, the materials used to fabricate the first gate insulating layer 22 and the second gate insulating layer 23 may be different. Specifically, the material used to fabricate the first gate insulating layer 22 includes one of silicon oxide and silicon nitride, and the material used to fabricate the second gate insulating layer 23 includes the other of silicon oxide and silicon nitride.

[0212] In an exemplary embodiment, the first gate insulating layer 22 and the second gate insulating layer 23 are made of different materials, and the dry etching gases required for the first gate insulating layer 22 and the second gate insulating layer 23 are different. When forming the gate insulating layer, only the etching gas for the second gate insulating layer is used, and the etching gas for the first gate insulating layer is not used. This ensures that the second gate insulating layer can be etched while the first gate insulating layer is completely preserved, thereby avoiding changes in transistor characteristics caused by fluctuations in the etching amount.

[0213] In an exemplary embodiment, the active layer 12 is made of a metal oxide. The first gate insulating layer 22 is made of silicon oxide, and the second gate insulating layer 23 is made of silicon nitride.

[0214] In an exemplary embodiment, the active layer 12 is made of amorphous silicon. The first gate insulating layer 22 is made of silicon nitride, and the second gate insulating layer 23 is made of silicon oxide.

[0215] Figure 6 shows the curve of gate insulating layer thickness versus Ion normalization coefficient. As shown in Figure 6, the smaller the gate insulating layer thickness, the greater the increase in transistor turn-on current Ion.

[0216] Figure 7 shows the curves of the gate electrode voltage Vg and the current Id flowing through the source electrode under different gate insulating layer thicknesses. As shown in Figure 7, S1 is the curve of the gate electrode voltage and the current flowing through the source electrode when the gate insulating layer thickness is 3500 angstroms, and S2 is the curve of the gate electrode voltage and the current flowing through the source electrode when the gate insulating layer thickness is 4000 angstroms. As shown in Figure 7, the smaller the gate insulating layer thickness, the greater the increase in the transistor's turn-on current Ion.

[0217] The thinner the gate insulation layer, the higher the failure rate of the display product's load and short circuits between the data line and the gate line.

[0218] This disclosure allows for increasing the transistor's turn-on current while reducing the load on display products and the failure rate of short circuits between data lines and gate lines, by using a gate insulation layer thickness ranging from 3800 angstroms to 4200 angstroms.

[0219] In an exemplary embodiment, the thickness of the gate electrode 11 is in the range of 2000 angstroms to 5000 angstroms. The thickness of the gate electrode 11 depends on the resolution and refresh rate of the display product, and this disclosure does not limit it in any way.

[0220] In an exemplary embodiment, the thickness of at least one of the first electrode 13 and the second electrode 14 is in the range of 2000 angstroms to 5000 angstroms. The thickness of at least one of the first electrode 13 and the second electrode 14 depends on the resolution and refresh rate of the display product, and this disclosure does not limit it in any way.

[0221] In an exemplary embodiment, the thickness of the active layer 12 is in the range of 1700 angstroms to 2200 angstroms.

[0222] The subsequent process flow is shown in Figure 2. Thus, by adjusting the thickness of the GI1 deposition, the overall Ion value of the TFT can be adjusted. As can be seen from the above formula, the Ion value ratio is directly proportional to the ratio of the GI thinning value to the initial GI value, i.e., Ion / Ionref = GIref / GI. Figure 4, using a-Si as an example, illustrates the relationship between the Ion normalization coefficient and GI. Theoretically, the thinner the GI, the greater the Ion increase. However, GI thinning will increase the parasitic capacitance of the TFT gate and the parasitic capacitance of the source and drain, and the DGS defect rate will also increase. Therefore, in general industrial production, the common GI1 thickness is [value missing].

[0223] In an exemplary embodiment, the thickness of the gate electrode of the transistor is determined by the product characteristics, including resolution and refresh rate.

[0224] In an exemplary embodiment, the thickness of the first and second electrodes of the transistor is determined by the product characteristics of the product.

[0225] In an exemplary embodiment, the thickness of the gate insulation layer may be 4000 angstroms.

[0226] In an exemplary embodiment, the thickness of the first gate insulating layer can be between 2000 and 3500 angstroms. The thinner the first gate insulating layer, the more significant the improvement in the turn-on current of the transistor device.

[0227] Figure 8 is a top view of a transistor device, Figure 9 is a cross-sectional view of Figure 8 along the AA direction, and Figure 10 is a cross-sectional view of Figure 8 along the BB direction. As shown in Figures 8 to 10, the first electrode 13 may surround at least one side of the second electrode 14, and the orthographic projection of the first electrode 13 on the substrate 10 covers the sidewall of the active layer 12. The orthographic projection of the second electrode 14 on the substrate 10 at least partially overlaps with the orthographic projection of the middle part of the active layer 12 on the substrate 10. That is, the first electrode 13 in Figure 8 at least partially surrounds the second electrode 14. Figure 5 is illustrated with the example of the first and second electrodes being strip-shaped, and Figure 8 is illustrated with the example of the first electrode 13 at least partially surrounding the second electrode 14.

[0228] In an exemplary embodiment, as shown in Figures 5 and 8, the minimum width W of at least one of the first electrode 13 and the second electrode 14 along the arrangement direction of the first electrode 13 and the second electrode 14 is in the range of 2.5 micrometers to 3.5 micrometers.

[0229] In an exemplary embodiment, as shown in Figures 5 and 8, the distance W2 between the orthographic projection of the boundary of the groove structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is less than the distance W3 between the orthographic projection of the boundary of the first electrode 13 near the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10.

[0230] In an exemplary embodiment, as shown in Figures 5 and 8, the distance W3 between the orthographic projection of the boundary of the first electrode 13 near the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10.

[0231] In an exemplary embodiment, the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 onto the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 onto the substrate 10 must satisfy the overlap deviation threshold between the film layer where the gate electrode is located and the film layers where the first electrode 13 and the second electrode 14 are located. That is, the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 onto the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 onto the substrate 10 is greater than or equal to the overlap deviation threshold between the film layer where the gate electrode 11 is located and the film layers where the first electrode 13 and the second electrode 14 are located.

[0232] In an exemplary embodiment, the distance W2 between the orthographic projection of the boundary of the groove structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 must satisfy the overlap deviation threshold of the film layer where the active layer and the gate insulating layer are located. That is, the distance W1 between the orthographic projection of the boundary of the groove structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 must be greater than or equal to the overlap deviation threshold of the film layer where the active layer and the gate insulating layer are located.

[0233] In an exemplary embodiment, the distance W3 between the orthographic projection of the boundary of the first electrode 13 near the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than or equal to the overlap deviation threshold between the active layer and the first and second electrodes plus 1 micrometer, so as to ensure that the overlap area between one of the first and second electrodes and the active layer can improve the reliability of the transistor device.

[0234] In an exemplary embodiment, the distance W4 between the first electrode 13 and the second electrode 14 along the arrangement direction of the first electrode and the second electrode is determined by the resolution, process type, and product model of the exposure machine used in the process of forming the first electrode and the second electrode, and this disclosure does not limit it in any way.

[0235] In an exemplary embodiment, FIG11 is a schematic diagram of one structure of the display substrate, and FIG12 is a schematic diagram of another structure of the display substrate. As shown in FIG11 and FIG12, the transistor device further includes a passivation layer 31. The passivation layer 31 is located on the side of the transistor's first electrode 13 and second electrode 14 away from the substrate 10. In an exemplary embodiment, the passivation layer can protect the metal film layer on which the first electrode and second electrode of the transistor are located, can prevent the metal film layer on which the first electrode and second electrode of the transistor are located from being corroded, and can improve the reliability of the transistor device.

[0236] In an exemplary embodiment, the passivation layer 31 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0237] The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0238] The fabrication process of the transistor device shown in Figure 11 is illustrated below.

[0239] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film using a patterning process to form a gate electrode 11. As shown in FIG13, FIG13 is a schematic diagram of FIG11 after the gate electrode has been formed.

[0240] (2) Forming a gate insulating layer. In an exemplary embodiment, forming a gate insulating layer includes: depositing a gate insulating film on a substrate on which a gate electrode is formed, and patterning the gate insulating film using a patterning process to form a gate insulating layer 21 having a groove structure 1. As shown in FIG14, FIG14 is a schematic diagram after the gate insulating layer in FIG11 has been formed.

[0241] In an exemplary embodiment, a gate insulating film is deposited on a substrate on which the gate electrode is formed using a chemical vapor deposition process.

[0242] (3) Forming the original semiconductor layer. In an exemplary embodiment, forming the original semiconductor layer includes: depositing a semiconductor thin film on a substrate on which a gate insulating layer is formed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form an original semiconductor layer including a first active layer 121 and a third active layer 123. As shown in FIG15, FIG15 is a schematic diagram after the original semiconductor layer in FIG11 is formed.

[0243] In an exemplary embodiment, the third active layer 123 is an N-type semiconductor layer.

[0244] In an exemplary embodiment, the orthographic projection of the third active layer 123 onto the substrate coincides with the orthographic projection of the surface of the first active layer 121 away from the substrate onto the substrate.

[0245] (4) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a second metal thin film on a substrate on which the original semiconductor layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process to form a first electrode 13, a fourth electrode 14 and a second active layer 122. As shown in FIG16, FIG16 is a schematic diagram after the first electrode and the second electrode in FIG11 are formed.

[0246] In an exemplary embodiment, the active layer includes a first active layer 121 and a second active layer 122.

[0247] (5) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes forming a passivation layer on a substrate on which the first electrode and the second electrode are formed. As shown in FIG17, FIG17 is a schematic diagram after the passivation layer in FIG11 is formed.

[0248] The fabrication process of the transistor device shown in Figure 12 is illustrated below.

[0249] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film using a patterning process to form a gate electrode. Figure 12 is the same as the schematic diagram of the gate electrode after formation in Figure 9.

[0250] (2) Forming a gate insulating layer. In an exemplary embodiment, forming a gate insulating layer includes: sequentially depositing a first gate insulating film and a second gate insulating film on a substrate on which gate electrodes are formed, and patterning the second gate insulating film by a patterning process to form a gate insulating layer 21 including a first gate insulating layer 22 and a second gate insulating layer 23. As shown in FIG18, FIG18 is a schematic diagram after the gate insulating layer in FIG12 is formed.

[0251] In an exemplary embodiment, the second gate insulating layer 23 is provided with a via V that exposes the first gate insulating layer 22. The via V and the first gate insulating layer 22 form a groove structure.

[0252] In an exemplary embodiment, a first gate insulating film and a second gate insulating film are sequentially deposited on a substrate on which the gate electrode is formed using a chemical vapor deposition process.

[0253] (3) Forming the original semiconductor layer. In an exemplary embodiment, forming the original semiconductor layer includes: depositing a semiconductor thin film on a substrate on which a gate insulating layer is formed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form an original semiconductor layer including a first active layer 121 and a third active layer 123. As shown in FIG19, FIG19 is a schematic diagram after the original semiconductor layer in FIG12 is formed.

[0254] In an exemplary embodiment, the third active layer 123 is an N-type semiconductor layer.

[0255] In an exemplary embodiment, the orthographic projection of the third active layer 123 onto the substrate coincides with the orthographic projection of the surface of the first active layer 121 away from the substrate onto the substrate.

[0256] (4) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a second metal thin film on a substrate on which the original semiconductor layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process to form a first electrode 13, a fourth electrode 14 and a second active layer 122. As shown in FIG20, FIG20 is a schematic diagram after the formation of the first electrode and the second electrode in FIG12.

[0257] In an exemplary embodiment, the active layer includes a first active layer 121 and a second active layer 122.

[0258] (5) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes forming a passivation layer on a substrate on which the first electrode and the second electrode are formed. As shown in FIG21, FIG21 is a schematic diagram after the passivation layer is formed in FIG12.

[0259] This disclosure also provides a method for fabricating a transistor device, configured to fabricate the transistor device provided in any of the foregoing embodiments. The method for fabricating the transistor device includes:

[0260] Step 100: Form the gate electrode of the transistor device on the substrate.

[0261] Step 200: Form a gate insulating layer for a transistor device on the gate electrode. The gate insulating layer has a groove structure, and the groove structure is located on the side of the gate insulating layer away from the substrate.

[0262] Step 300: Form the active layer of the transistor device within the groove structure of the gate insulating layer.

[0263] The active layer has at least two boundaries that are spaced at a predetermined distance from the corresponding boundaries of the groove structure.

[0264] In an exemplary embodiment, step 200 may include: coating a gate insulating film on the gate electrode and forming grooves on the gate insulating film through a patterning process to form a gate insulating layer of the transistor device.

[0265] In an exemplary embodiment, step 200 may include: sequentially coating a first gate insulating film and a second gate insulating film on the gate electrode, and forming a gate insulating layer with a groove structure consisting of the via and the first gate insulating film by patterning process.

[0266] In an exemplary embodiment, the active layer includes a first active layer and a second active layer. Step 300 includes: depositing a semiconductor thin film on a gate insulating layer; and processing the semiconductor thin film by a hydrogenation process to form the first active layer and the third active layer.

[0267] A source / drain metal thin film is deposited on the third active layer. The source / drain metal thin film and the third active layer are then processed by a patterning process to form a second active layer, a first electrode, and a second electrode.

[0268] In an exemplary embodiment, the method for fabricating a transistor device further includes:

[0269] Step 400: Form a passivation layer on the first electrode and the second electrode.

[0270] Figure 22 is a cross-sectional schematic diagram of the transistor device provided in the embodiments of this disclosure; Figure 23 is a cross-sectional schematic diagram of the transistor device provided in the embodiments of this disclosure; Figure 24 is a cross-sectional schematic diagram of the transistor device provided in the embodiments of this disclosure; Figure 25 is a cross-sectional schematic diagram of the transistor device provided in the embodiments of this disclosure; Figure 26 is a partial cross-sectional schematic diagram of the transistor device provided in Figures 22 and 23; and Figure 27 is a partial cross-sectional schematic diagram of the transistor device provided in Figures 24 and 25. As shown in Figures 22 to 27, the transistor device provided in the embodiments of this disclosure is disposed on a substrate 30, and the transistor device includes: a gate electrode 31, a gate insulating layer 35, and an active layer 32. The gate electrode 31 is located on the side of the gate insulating layer 35 closest to the substrate 30, and the active layer 32 is located on the side of the gate insulating layer 35 away from the substrate 30. That is, the transistor device can be a bottom-gate structure.

[0271] As shown in Figures 22 to 27, the gate insulating layer 35 may include a first insulating layer 351 and a second insulating layer 352 stacked on the substrate 30, wherein one of the first insulating layer 351 and the second insulating layer 352 is provided with a via VV. Figures 22, 23, and 26 illustrate the case where the second insulating layer 352 is provided with a via VV, while Figures 24, 25, and 27 illustrate the case where the first insulating layer 351 is provided with a via VV.

[0272] As shown in Figures 22 to 27, in this disclosure, the orthographic projection of the via VV on the substrate 30 at least partially overlaps with the orthographic projection of the active layer 32 on the substrate 30. This reduces the thickness of the gate insulating layer disposed between the channel region and the gate electrode of the active layer, increases the capacitance value of the parasitic capacitance between the channel region and the gate electrode of the active layer, increases the turn-on current Ion of the transistor device, and thus improves the refresh rate of the display product.

[0273] In an exemplary embodiment, the orthographic projection of the via VV on the substrate 30 and the orthographic projection of the active layer 32 on the substrate 30 at least partially overlap. In an exemplary embodiment, the active layer can be made of metal oxide or amorphous silicon, and this disclosure does not limit it in any way.

[0274] This disclosure provides a gate insulating layer comprising a first insulating layer and a second insulating layer, and a via is provided in one of the first and second insulating layers. This ensures the etching accuracy of the gate insulating layer, improves the process stability of the transistor device, and reduces the fluctuation of the turn-on current of the transistor device.

[0275] In an exemplary embodiment, as shown in Figures 22 to 25, the transistor device may further include a first electrode 33 and a second electrode 34 disposed on the side of the active layer 32 away from the substrate 30.

[0276] In an exemplary embodiment, as shown in Figures 22 to 25, the active layer 32 includes a first active layer 321 and a second active layer 322. The second active layer 322 is disposed on the side of the first active layer 321 away from the substrate 30. The second active layer 322 includes a first active structure 3221 and a second active structure 3222.

[0277] In an exemplary embodiment, as shown in Figures 22 to 25, the orthographic projection of the second active layer 322 onto the substrate 30 is within the range of the orthographic projection of the first active layer 321 onto the substrate 30.

[0278] In an exemplary embodiment, as shown in Figures 22 to 25, the orthographic projection of the first active structure 3221 on the substrate 30 is within the range of the orthographic projection of the first electrode 33 on the substrate 30.

[0279] In an exemplary embodiment, as shown in Figures 22 to 25, the orthographic projection of the second active structure 3222 on the substrate 30 is within the range of the orthographic projection of the second electrode 34 on the substrate 30.

[0280] In an exemplary embodiment, the second active layer 3222 may be fabricated using the same mask as the first electrode 33 and the second electrode 34, and this disclosure does not limit this in any way.

[0281] In an exemplary embodiment, the thickness of the first active layer 321 is greater than the thickness of the second active layer 322.

[0282] In an exemplary embodiment, the conductivity of the second active layer 322 is greater than that of the first active layer 321. In an exemplary embodiment, the second active layer may be an N-type semiconductor layer.

[0283] In an exemplary embodiment, as shown in Figures 22 to 25, at least one of the first electrode 33 and the second electrode 34 covers at least a portion of the sidewalls of the first active layer 321 and the second active layer 322, as well as the surface of the second active layer 322 that is away from the substrate 30.

[0284] In an exemplary embodiment, as shown in Figures 22 to 25, the orthographic projection of at least one of the first electrode 33 and the second electrode 34 onto the substrate 30 at least partially overlaps with the orthographic projection of the insulating layer with the through-hole VV onto the substrate 30.

[0285] In an exemplary embodiment, the maximum distance H between the surface of the gate insulating layer 35 away from the substrate 30 and the surface of the gate electrode 31 away from the substrate 30 is in the range of 3800 angstroms to 4200 angstroms. Exemplarily, the maximum distance H between the surface of the gate insulating layer 35 away from the substrate 30 and the surface of the gate electrode 31 away from the substrate 30 can be 4000 angstroms.

[0286] In an exemplary embodiment, the first insulating layer 351 is made of one of silicon oxide and silicon nitride, and the second insulating layer 352 is made of the other of silicon oxide and silicon nitride. Exemplarily, when the first insulating layer 351 is made of silicon oxide, the second insulating layer 352 may be made of silicon nitride; or, when the first insulating layer 351 is made of silicon nitride, the second insulating layer 352 may be made of silicon oxide. This disclosure does not impose any limitations in this regard.

[0287] In an exemplary embodiment, the orthographic projection of the active layer 32 onto the substrate 30 lies within the range of the orthographic projection of the via VV onto the substrate 30, or the orthographic projection of the via VV onto the substrate 30 lies within the range of the orthographic projection of the active layer 32 onto the substrate 30. Figures 22 and 23 are illustrated with the example of the orthographic projection of the active layer 32 onto the substrate 30 lying within the range of the orthographic projection of the via VV onto the substrate 30, and Figures 24 and 25 are illustrated with the example of the orthographic projection of the via VV onto the substrate 30 lying within the range of the orthographic projection of the active layer 32 onto the substrate 30.

[0288] In an exemplary embodiment, the first electrode 33 may be U-shaped, I-shaped, or L-shaped. The second electrode 34 may be I-shaped.

[0289] In an exemplary embodiment, FIG28 is a top view of a transistor device, FIG29 is a top view of a transistor device, and FIG30 is a top view of a transistor device. FIG28 is illustrated with an example of the first electrode 33 of the transistor device being in a "U" shape, FIG29 is illustrated with an example of the first electrode 33 of the transistor device being in a "I" shape, and FIG30 is illustrated with an example of the first electrode 33 of the transistor device being in an "L" shape.

[0290] As shown in Figures 28 to 30, when the orthogonal projection of the active layer 32 on the substrate 30 is within the range of the orthogonal projection of the via VV on the substrate 30, the active layer 32 is completely settled within the via VV.

[0291] In an exemplary embodiment, the active layer of the transistor device is located in the semiconductor layer, the gate electrode of the transistor device is located in the gate metal layer, and the first electrode and the second electrode of the transistor device are located in the source and drain metal layers.

[0292] As shown in Figures 28 to 30, in an exemplary embodiment, when the orthographic projection of the active layer 32 on the substrate 30 is within the range of the orthographic projection of the via VV on the substrate 30, the minimum distance 'a' between the orthographic projection of at least one boundary of at least one of the first electrodes 33 and 34 extending along the first direction D1 on the substrate 30 and the orthographic projection of at least one boundary of the active layer 32 extending along the first direction D1 on the substrate 30 is greater than a first alignment deviation threshold. The first alignment deviation threshold is the deviation threshold along the second direction D2 when the semiconductor layer and the gate insulating layer are aligned.

[0293] In an exemplary embodiment, as shown in FIG28, when the first electrode 33 is U-shaped, the first electrode 33 includes an opening facing the second electrode 34, and the first electrode 33 partially surrounds the second electrode 34, and the second electrode 34 extends at least partially along the first direction D1.

[0294] In an exemplary embodiment, FIG31 is a top view of the transistor device, FIG32 is a top view of the transistor device, and FIG33 is a top view of the transistor device. The transistor devices shown in FIG31 to FIG33 are all illustrated with the example of at least a portion of the first electrode being "U"-shaped and the orthographic projection of the via on the substrate being within the range of the orthographic projection of the active layer on the substrate. As shown in FIG28, FIG31 and FIG32, when the first electrode 33 is "U"-shaped, the orthographic projection of the first electrode 33 on the substrate 30 is within the range of the orthographic projection of the active layer 32 on the substrate 30. The orthographic projection of the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projection of the active layer 32 on the substrate 30, and there is a non-overlapping area with the orthographic projection of the gate electrode 31 on the substrate 30.

[0295] In an exemplary embodiment, in the transistor device shown in FIG28, the insulating layer between the gate electrode 31 and the first electrode 33 consists of only one of the first insulating layer and the second insulating layer. That is, the thickness of the insulating layer between the gate electrode 31 and the first electrode 33 is relatively small, resulting in a relatively large parasitic capacitance between the gate electrode and the first electrode. Similarly, a portion of the insulating layer between the gate electrode 31 and the second electrode 34 consists of only one of the first insulating layer and the second insulating layer. This also results in a relatively small thickness of the insulating layer between the gate electrode 31 and the second electrode, leading to a relatively large parasitic capacitance between the gate electrode and the second electrode. Furthermore, since the minimum distance 'a' between the orthographic projection of at least one boundary of the first electrode 33 extending along the first direction D1 on the substrate 30 and the orthographic projection of at least one boundary of the active layer 32 extending along the first direction D1 on the substrate 30 is greater than the first alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will not fluctuate. However, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the second electrode will change, and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0296] In an exemplary embodiment, as shown in Figures 31 and 32, the via VV includes multiple boundaries, including a first boundary B1 that extends along a second direction D2 and intersects with the second direction D2. In this exemplary embodiment, the shapes of the remaining boundaries of the via, excluding the first boundary B1, are the same as the shape of the first electrode, and this disclosure does not limit this in any way.

[0297] In an exemplary embodiment, as shown in Figures 31 and 32, the orthographic projection of the first electrode 33 on the substrate 30 at least partially overlaps with the orthographic projection of at least one boundary of the via VV, excluding the first boundary B1, on the substrate 30, and the orthographic projection of the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projection of the first boundary B1 of the via VV on the substrate 30.

[0298] In an exemplary embodiment, as shown in Figures 31 and 32, the distance b1 between the orthographic projection of at least one boundary of the first electrode 33 extending along the first direction D1 onto the substrate 30 and the orthographic projection of at least one boundary of the via VV extending along the first direction D1 (excluding the first boundary) onto the substrate 30 is greater than a second alignment deviation threshold. The second alignment deviation threshold is the deviation threshold along the second direction D2 when the source / drain metal layer and the gate insulating layer are aligned.

[0299] In an exemplary embodiment, in the transistor device provided in FIG31, a portion of the insulating layer between the gate electrode 31 and the first electrode 33 comprises a first insulating layer and a second insulating layer. That is, the insulating layer between the gate electrode 31 and the first electrode 33 has a relatively large thickness, and the parasitic capacitance between the gate electrode and the first electrode is relatively small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 comprises a first insulating layer and a second insulating layer. That is, most of the insulating layer between the gate electrode 31 and the second electrode 34 has a relatively large thickness, and the parasitic capacitance between the gate electrode and the second electrode is relatively small. Furthermore, since the distance b1 between the orthographic projection of at least one boundary of the first electrode 33 extending along the first direction D1 onto the substrate 30 and the orthographic projection of at least one boundary of the via VV extending along the first direction D1 (excluding the first boundary) onto the substrate 30 is greater than the second alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode will change. Therefore, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0300] In an exemplary embodiment, as shown in FIG32, the number of transistor devices can be two, and the first transistor device and the second transistor device are at least partially symmetrically arranged with respect to a straight line extending along the second direction D2; the second electrode 34 of the first transistor device and the second electrode 34 of the second transistor device are the same electrode.

[0301] In an exemplary embodiment, the transistor device provided in FIG32 includes two transistor devices provided in FIG31. When there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, although the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode in the two transistor devices will change, the changes in the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode in the two transistor devices are complementary, so that the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate.

[0302] In an exemplary embodiment, as shown in FIG33, the first electrode 33 may include: a first branch segment 3311, a second branch segment 3312, and a connecting segment 3313. The first branch segment 3311 and the second branch segment 3312 are respectively connected to the connecting segment 3313. The first branch segment 3311 and the second branch segment 3312 extend along a first direction D1, and the connecting segment 3313 extends along a second direction D2.

[0303] In an exemplary embodiment, as shown in FIG33, at least one of the first branch segment 3311 and the second branch segment 3312 overlaps at least partially with the orthographic projection of the via VV on the substrate 30, and the orthographic projection of the connecting segment 3313 on the substrate 30 does not overlap with the orthographic projection of the gate electrode 31 on the substrate 30.

[0304] In an exemplary embodiment, as shown in FIG33, the via VV includes: a first boundary B11, a second boundary B12, a third boundary B13 and a fourth boundary B14. The first boundary B11 and the second boundary B12 extend along the second direction D2 and are disposed opposite to each other, and the third boundary B13 and the fourth boundary B14 extend along the first direction D1 and are disposed opposite to each other.

[0305] In an exemplary embodiment, as shown in FIG33, the orthographic projection of the first branch segment 3311 on the substrate 30 at least partially overlaps with the orthographic projections of at least one of the first boundary B11, the second boundary B12, and the third boundary B13 on the substrate 30. The orthographic projection of the second branch segment 3312 on the substrate 30 at least partially overlaps with the orthographic projections of at least one of the first boundary B11, the second boundary B12, and the fourth boundary B14 on the substrate 30.

[0306] In an exemplary embodiment, as shown in FIG33, the orthographic projection of the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projection of at least one of the first boundary B11 and the second boundary B12 on the substrate 30.

[0307] In an exemplary embodiment, as shown in FIG33, the distance between the boundary of at least one of the first branch segment 3311 and the second branch segment 3312 away from the connection segment 3313 and the first boundary B11 is a first distance c1, and the distance between the boundary of the second electrode 34 near the connection segment 3313 and the second boundary B12 is a second distance c2. The first distance c1 is equal to the second distance c2, and at least one of the first distance c1 and the second distance c2 is greater than a third alignment deviation threshold. The third alignment deviation threshold is a deviation threshold along the first direction D1 when the source / drain conductive layer and the gate insulating layer are aligned. The distance between the orthographic projection of the first boundary B11 on the substrate 30 and the orthographic projection of the connection segment 3313 on the substrate 30 is greater than the distance between the orthographic projection of the second boundary B12 on the substrate 30 and the orthographic projection of the connection segment 3313 on the substrate 30.

[0308] In an exemplary embodiment, in the transistor device provided in FIG33, a portion of the insulating layer between the gate electrode 31 and the first electrode 33 includes a first insulating layer and a second insulating layer. That is, the thickness of the insulating layer between the gate electrode 31 and the first electrode 33 is relatively large, and the parasitic capacitance between the gate electrode and the first electrode is relatively small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 includes a first insulating layer and a second insulating layer. That is, the thickness of most of the insulating layer between the gate electrode 31 and the second electrode 34 is relatively large, and the parasitic capacitance between the gate electrode and the second electrode is relatively small. Furthermore, since at least one of the first distance c1 and the second distance c2 is greater than the third alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the parasitic capacitance between the gate electrode and the first electrode, and the parasitic capacitance between the gate electrode and the second electrode, will not fluctuate. When there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the thickness of the insulating layer between the gate electrode and the first electrode, and the thickness of the insulating layer between the gate electrode and the second electrode, will not change. Therefore, the parasitic capacitance between the gate electrode and the first electrode, and the parasitic capacitance between the gate electrode and the second electrode, do not fluctuate.

[0309] In the transistor devices shown in Figures 32 and 33, although the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, does not fluctuate, the transistor device shown in Figure 33 occupies more space than the transistor device shown in Figure 32.

[0310] In an exemplary embodiment, FIG34 is a top view of the transistor device (Seventh), FIG35 is a top view of the transistor device (Eighth), FIG36 is a top view of the transistor device (Ninth), and FIG37 is a top view of the transistor device (Tenth). FIG34 to FIG39 are illustrated with the example of at least a portion of the first electrode being "I"-shaped and the orthographic projection of the via on the substrate being within the range of the orthographic projection of the active layer on the substrate. As shown in FIG29 and FIG34 to FIG37, at least one of the first electrode 33 and the second electrode 34 in the transistor device extends along the first direction D1.

[0311] In an exemplary embodiment, as shown in Figures 29, 34 to 37, the orthographic projection of at least one of the first electrode 33 and the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projection of the active layer 32 on the substrate 30, and there is a non-overlapping region with the orthographic projection of the gate electrode 31 on the substrate 30.

[0312] In an exemplary embodiment, in the transistor device provided in FIG29, most of the insulating layer between the gate electrode 31 and the first electrode 33 comprises one of the first insulating layer and the second insulating layer. That is, the thickness of most of the insulating layer between the gate electrode 31 and the first electrode 33 is small, and the parasitic capacitance between the gate electrode and the first electrode is large. Most of the insulating layer between the gate electrode 31 and the second electrode 34 comprises one of the first insulating layer and the second insulating layer. That is, the thickness of most of the insulating layer between the gate electrode 31 and the second electrode 34 is small, and the parasitic capacitance between the gate electrode and the second electrode is large. Furthermore, since the minimum distance 'a' between the orthographic projection of at least one boundary of the first electrode 33 extending along the first direction D1 on the substrate 30 and the orthographic projection of at least one boundary of the active layer 32 extending along the first direction D1 on the substrate 30 is greater than the first alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the parasitic capacitance between the gate electrode 31 and the first electrode 33, as well as the parasitic capacitance between the gate electrode 31 and the second electrode 34, will not fluctuate. However, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the parasitic capacitance between the gate electrode 31 and the second electrode 34, as well as the parasitic capacitance between the gate electrode 31 and the first electrode 33, will fluctuate.

[0313] In an exemplary embodiment, as shown in FIG34, the via VV includes: a first boundary B21, a second boundary B22, a third boundary B23, and a fourth boundary B24. The first boundary B21 and the second boundary B22 extend along a second direction D2 and are disposed opposite to each other, and the third boundary B23 and the fourth boundary B24 extend along a first direction D1 and are disposed opposite to each other. The length of at least one of the first boundary B21 and the second boundary B22 is less than the length of at least one of the third boundary B23 and the fourth boundary B24.

[0314] In an exemplary embodiment, as shown in FIG34, the orthographic projection of the first electrode 33 on the substrate 30 at least partially overlaps with the orthographic projections of at least one of the second boundary B22 and the third boundary B23 on the substrate 30, and has no overlap with the orthographic projections of at least one of the first boundary B21 and the fourth boundary B24 on the substrate 30. Similarly, the orthographic projection of the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projections of at least one of the first boundary B21 and the fourth boundary B24 on the substrate 30, and has no overlap with the orthographic projections of at least one of the second boundary B22 and the third boundary B23 on the substrate 30.

[0315] In an exemplary embodiment, as shown in FIG34, the minimum distance b2 between the orthographic projection of the boundary of at least one of the first electrodes 33 and 34 extending along the first direction D1 onto the substrate 30 and the orthographic projection of at least one boundary of the via VV extending along the first direction D1 onto the substrate 30 is greater than a second alignment deviation threshold. FIG34 is illustrated using the example that the minimum distance b2 between the orthographic projection of the boundaries of both the first electrode 33 and 34 extending along the first direction D1 onto the substrate 30 and the orthographic projection of at least one boundary of the via VV extending along the first direction D1 onto the substrate 30 is greater than the second alignment deviation threshold.

[0316] In an exemplary embodiment, in the transistor device provided in FIG34, most of the insulating layer between the gate electrode 31 and the first electrode 33 includes a first insulating layer and a second insulating layer. That is, the insulating layer between the gate electrode 31 and the first electrode 33 has a large thickness, and the parasitic capacitance between the gate electrode and the first electrode is small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 includes a first insulating layer and a second insulating layer. That is, most of the insulating layer between the gate electrode 31 and the second electrode 34 has a large thickness, and the parasitic capacitance between the gate electrode and the second electrode is small. Furthermore, since the minimum distance b2 between the orthographic projection of the boundary of at least one of the first electrodes 33 and 34 extending along the first direction D1 onto the substrate 30 and the orthographic projection of at least one boundary of the via VV extending along the first direction D1 onto the substrate 30 is greater than the second alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode changes, and the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0317] In an exemplary embodiment, as shown in FIG35, the via VV includes: a first boundary B31, a second boundary B32, a third boundary B33, and a fourth boundary B34. The first boundary B31 and the second boundary B32 extend along a second direction D2 and are disposed opposite to each other. The third boundary B33 and the fourth boundary B34 extend along a first direction D1 and are disposed opposite to each other. The length of at least one of the first boundary B31 and the second boundary B32 is greater than or equal to the length of at least one of the third boundary B33 and the fourth boundary B34.

[0318] In an exemplary embodiment, as shown in FIG35, the orthographic projection of the first electrode 33 on the substrate 30 at least partially overlaps with the orthographic projection of at least one of the first boundary B31, the second boundary B32 and the third boundary B33 on the substrate 30, and the orthographic projection of the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projection of at least one of the first boundary B31, the second boundary B32 and the fourth boundary B34 on the substrate 30.

[0319] In an exemplary embodiment, as shown in FIG35, the distance c31 between the orthographic projection of the target boundary of the first electrode 33 on the substrate 30 and the orthographic projection of the second boundary on the substrate 30 is equal to the distance c32 between the orthographic projection of the target boundary of the second electrode 34 on the substrate 30 and the orthographic projection of the first boundary on the substrate 30, and is greater than the third alignment deviation threshold. Wherein, at least one of the first electrode 33 and the second electrode 34 overlaps with the orthographic projection of the gate electrode 31 on the substrate 30, and the boundary extending along the second direction D2 is the target boundary. The distance between the orthographic projection of the target boundary of the first electrode 33 on the substrate 30 and the orthographic projection of the second boundary on the substrate 30 is less than the distance between the orthographic projection of the target boundary of the first electrode 33 on the substrate 30 and the orthographic projection of the first boundary on the substrate 30, and the distance between the orthographic projection of the target boundary of the second electrode 34 on the substrate 30 and the orthographic projection of the first boundary on the substrate 30 is greater than the distance between the orthographic projection of the target boundary of the second electrode 34 on the substrate 30 and the orthographic projection of the first boundary on the substrate 30.

[0320] In an exemplary embodiment, in the transistor device provided in FIG35, most of the insulating layer between the gate electrode 31 and the first electrode 33 includes a first insulating layer and a second insulating layer. That is, the insulating layer between the gate electrode 31 and the first electrode 33 has a large thickness, and the parasitic capacitance between the gate electrode and the first electrode is small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 includes a first insulating layer and a second insulating layer. That is, most of the insulating layer between the gate electrode 31 and the second electrode 34 has a large thickness, and the parasitic capacitance between the gate electrode and the second electrode is small. Furthermore, since the distance c31 between the orthographic projection of the target boundary of the first electrode 33 onto the substrate 30 and the orthographic projection of the second boundary onto the substrate 30 is equal to the distance c32 between the orthographic projection of the target boundary of the second electrode 34 onto the substrate 30 and the orthographic projection of the first boundary onto the substrate 30, and is greater than the third alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode change, and the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate. When there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode will change, and therefore, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0321] In an exemplary embodiment, as shown in FIG36, when the orthographic projection of the via VV on the substrate 30 is within the range of the orthographic projection of the active layer 32 on the substrate 30, the via VV includes: a first boundary B41, a second boundary B42, a third boundary B43, and a fourth boundary B44. The first boundary B41 and the second boundary B42 extend along a second direction D2 and are disposed opposite to each other, while the third boundary B43 and the fourth boundary B44 extend along a first direction D1 and are disposed opposite to each other. The length of at least one of the first boundary B41 and the second boundary B42 is greater than the length of at least one of the third boundary B43 and the fourth boundary B44.

[0322] In an exemplary embodiment, as shown in FIG36, the orthographic projection of at least one of the first electrode 33 and the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projection of at least one of the first boundary B41 and the second boundary B42 on the substrate 30, and there is no overlap with the orthographic projection of at least one of the third boundary B43 and the fourth boundary B44 on the substrate 30.

[0323] In an exemplary embodiment, as shown in FIG36, the distance c31 between the orthographic projection of the target boundary of the first electrode 33 on the substrate 30 and the orthographic projection of the second boundary on the substrate 30 is equal to the distance c32 between the orthographic projection of the target boundary of the second electrode 34 on the substrate 30 and the orthographic projection of the first boundary on the substrate 30, and is greater than the third alignment deviation threshold.

[0324] In an exemplary embodiment, in the transistor device provided in FIG36, most of the insulating layer between the gate electrode 31 and the first electrode 33 includes a first insulating layer and a second insulating layer. That is, the insulating layer between the gate electrode 31 and the first electrode 33 has a large thickness, and the parasitic capacitance between the gate electrode and the first electrode is small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 includes a first insulating layer and a second insulating layer. That is, most of the insulating layer between the gate electrode 31 and the second electrode 34 has a large thickness, and the parasitic capacitance between the gate electrode and the second electrode is small. Furthermore, since the distance c31 between the orthographic projection of the target boundary of the first electrode 33 onto the substrate 30 and the orthographic projection of the second boundary onto the substrate 30 is equal to the distance c32 between the orthographic projection of the target boundary of the second electrode 34 onto the substrate 30 and the orthographic projection of the first boundary onto the substrate 30, and is greater than the third alignment deviation threshold, and the minimum distance b2 between the orthographic projection of the boundary of at least one of the first electrodes 33 and 34 extending along the first direction D1 onto the substrate 30 and the orthographic projection of at least one boundary of the via VV extending along the first direction D1 onto the substrate 30 is greater than the second alignment deviation threshold, therefore, source-drain conductivity... When the layer has an alignment deviation relative to the gate insulating layer in the second direction D2, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode change, and the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate. When the source drain conductive layer has an alignment deviation relative to the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode will not change. Therefore, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate.

[0325] In an exemplary embodiment, as shown in FIG37, the via VV includes: a plurality of boundaries, the plurality of boundaries including: a first boundary B51 and a second boundary B52, the first boundary B51 and the second boundary B52 extending along a second direction D2 and being disposed opposite to each other.

[0326] In an exemplary embodiment, as shown in FIG37, the orthographic projection of the first electrode 33 on the substrate 30 at least partially overlaps with the orthographic projection of the first boundary B51 on the substrate 30, and there is no overlap with the orthographic projections of the other boundaries except the first boundary B51 on the substrate 30. The orthographic projection of the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projection of the second boundary B52 on the substrate 30, and there is no overlap with the orthographic projections of the other boundaries except the second boundary B52 on the substrate 30.

[0327] In an exemplary embodiment, as shown in FIG37, the distance c31 between the orthographic projection of the target boundary of the first electrode 33 on the substrate 30 and the orthographic projection of the second boundary on the substrate 30 is equal to the distance c32 between the orthographic projection of the target boundary of the second electrode 34 on the substrate 30 and the orthographic projection of the first boundary on the substrate 30, and is greater than the third alignment deviation threshold.

[0328] In an exemplary embodiment, in the transistor device provided in FIG37, most of the insulating layer between the gate electrode 31 and the first electrode 33 includes a first insulating layer and a second insulating layer. That is, the insulating layer between the gate electrode 31 and the first electrode 33 has a large thickness, and the parasitic capacitance between the gate electrode and the first electrode is small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 includes a first insulating layer and a second insulating layer. That is, most of the insulating layer between the gate electrode 31 and the second electrode 34 has a large thickness, and the parasitic capacitance between the gate electrode and the second electrode is small. Furthermore, since the distance c31 between the orthographic projection of the target boundary of the first electrode 33 onto the substrate 30 and the orthographic projection of the second boundary onto the substrate 30 is equal to the distance c32 between the orthographic projection of the target boundary of the second electrode 34 onto the substrate 30 and the orthographic projection of the first boundary onto the substrate 30, and is greater than the third alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode do not change, and the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. When there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode change, and therefore, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0329] In an exemplary embodiment, FIG38 is a top view eleven of a transistor device, FIG39 is a top view twelfth of a transistor device, and FIG40 is a top view thirteenth of a transistor device. FIG38 to FIG40 are illustrated with the example that at least a portion of the first electrode is "L"-shaped and the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate. As shown in FIG30, FIG38 to FIG40, the second electrode 34 extends along the first direction D1. The first electrode 33 includes: a first connecting portion 331, a second connecting portion 332, a third connecting portion 333, and a fourth connecting portion 334; the first connecting portion 331 and the fourth connecting portion 334 extend along a second direction D2, and the third connecting portion 333 extends along a first direction D1; the second connecting portion 332 is connected to the first connecting portion 331 and the third connecting portion 333 respectively, and is set at an obtuse angle to the first connecting portion 331 and the third connecting portion 333 respectively; the first connecting portion 331, the second connecting portion 332, and the third connecting portion 333 at least partially surround the second electrode 34; the fourth connecting portion 334 is connected to the third connecting portion 333 and is located on the side of the third connecting portion 333 away from at least one of the first connecting portion 331 and the second connecting portion 332.

[0330] In an exemplary embodiment, as shown in Figures 30, 38 to 40, the orthographic projection of at least one of the second connecting portion 332 and the third connecting portion 333 onto the substrate 30 lies within the range of the orthographic projection of the active layer 32 onto the substrate 30. The orthographic projections of the first connecting portion 331, the fourth connecting portion 334, and the second electrode 34 onto the substrate 30 at least partially overlap with the orthographic projection of the active layer 32 onto the substrate 30, and there is a non-overlapping region with the orthographic projection of the gate electrode 31 onto the substrate 30.

[0331] In an exemplary embodiment, in the transistor device provided in FIG30, most of the insulating layer between the gate electrode 31 and the first electrode 33 consists of only one of the first insulating layer and the second insulating layer. That is, the thickness of the insulating layer between the gate electrode 31 and the first electrode 33 is relatively small, resulting in a relatively large parasitic capacitance between the gate electrode and the first electrode. Similarly, most of the insulating layer between the gate electrode 31 and the second electrode 34 consists of only one of the first insulating layer and the second insulating layer. That is, the thickness of a portion of the insulating layer between the gate electrode 31 and the second electrode 34 is relatively small, resulting in a relatively large parasitic capacitance between the gate electrode and the second electrode. Furthermore, since the minimum distance 'a' between the orthographic projection of at least one boundary of the first electrode 33 extending along the first direction D1 on the substrate 30 and the orthographic projection of at least one boundary of the active layer 32 extending along the first direction D1 on the substrate 30 is greater than the first alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the second electrode and the thickness of the insulating layer between the gate electrode and the second electrode will change, and the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0332] In an exemplary embodiment, as shown in FIG38, when the orthographic projection of the via VV on the substrate 30 is within the range of the orthographic projection of the active layer 32 on the substrate 30, the orthographic projections of the second connection portion 332 and the third connection portion 333 on the substrate 30 are also within the range of the orthographic projection of the via VV on the substrate 30. The via VV includes multiple boundaries, and the orthographic projection of at least one structure of the second electrode 34, the first connection portion 331, and the fourth connection portion 334 on the substrate 30 at least partially overlaps with the orthographic projection of at least one boundary of the multiple boundaries in the via VV on the substrate 30.

[0333] In an exemplary embodiment, in the transistor device provided in FIG38, a portion of the insulating layer between the gate electrode 31 and the first electrode 33 includes a first insulating layer and a second insulating layer. That is, the thickness of the insulating layer between the gate electrode 31 and the first electrode 33 is relatively large, and the parasitic capacitance between the gate electrode and the first electrode is relatively small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 includes a first insulating layer and a second insulating layer. That is, the thickness of most of the insulating layer between the gate electrode 31 and the second electrode 34 is relatively large, and the parasitic capacitance between the gate electrode and the second electrode is relatively small. When there is a misalignment between the source / drain conductive layer and the gate insulating layer in the second direction D2, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will fluctuate. However, when there is a misalignment between the source / drain conductive layer and the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the first electrode, as well as the thickness of the insulating layer between the gate electrode and the second electrode, will change. Therefore, the parasitic capacitance between the gate electrode and the first electrode, and the parasitic capacitance between the gate electrode and the second electrode, will fluctuate.

[0334] In an exemplary embodiment, as shown in Figures 39 and 40, the via VV includes: a first boundary B61, a second boundary B62, a third boundary B63, a fourth boundary B64, a fifth boundary B65, a sixth boundary B66, and a seventh boundary B67; the first boundary B61, the fourth boundary B64, and the sixth boundary B66 extend along a second direction D2, and the third boundary B63, the fifth boundary B65, and the seventh boundary B67 extend along a first direction D1, with the first boundary B61 to the seventh boundary B67 connected sequentially. Specifically, the second boundary B62 is set at an obtuse angle to the first boundary B61 and the third boundary B63, the third boundary B63 is set at a right angle to the fourth boundary B64, the fourth boundary B64 is set at a right angle to the fifth boundary B65, the fifth boundary B65 is set at a right angle to the sixth boundary B66, the sixth boundary B66 is set at a right angle to the seventh boundary B67, the seventh boundary B67 is set at a right angle to the first boundary B61, and the distance between the sixth boundary B66 and the first boundary B61 is less than the distance between the fourth boundary B64 and the first boundary B61.

[0335] In an exemplary embodiment, as shown in Figures 39 and 40, the orthographic projection of the first boundary B61 on the substrate 30 lies within the range of the orthographic projection of the first connecting portion 331 on the substrate 30. The orthographic projection of the second boundary B62 on the substrate 30 lies within the range of the orthographic projection of the second connecting portion 332 on the substrate 30. The orthographic projection of the third connecting portion 333 on the substrate 30 at least partially overlaps with the orthographic projection of the third boundary B63 on the substrate 30, and the length of the third connecting portion 333 is less than the length of the third boundary B63. The orthographic projection of the fourth connecting portion 334 on the substrate 30 does not overlap with the orthographic projections of at least one of the first boundaries B61 to the seventh boundary B67 on the substrate 30. The orthographic projection of the second electrode 34 on the substrate 30 at least partially overlaps with the orthographic projections of the fourth boundary B64 and the sixth boundary B66 on the substrate 30, and covers the orthographic projection of the fifth boundary B65 on the substrate 30.

[0336] In an exemplary embodiment, as shown in Figures 39 and 40, the second electrode 34 is close to the third boundary B63, and the distance b4 between the boundary extending along the first direction D1 and the fifth boundary B65 is greater than the second alignment deviation threshold.

[0337] In an exemplary embodiment, as shown in Figures 39 and 40, the distance c41 between the second electrode 34 and the boundary extending along the first direction D1 and the seventh boundary B67 is equal to the distance c42 between the boundary extending along the second direction D2 and the fourth boundary B64 of the third connection portion 333, and is greater than the third alignment deviation threshold.

[0338] In an exemplary embodiment, in the transistor device provided in FIG39, a portion of the insulating layer between the gate electrode 31 and the first electrode 33 comprises a first insulating layer and a second insulating layer. That is, the insulating layer between the gate electrode 31 and the first electrode 33 has a relatively large thickness, and the parasitic capacitance between the gate electrode and the first electrode is relatively small. Most of the insulating layer between the gate electrode 31 and the second electrode 34 comprises a first insulating layer and a second insulating layer. That is, most of the insulating layer between the gate electrode 31 and the second electrode 34 has a relatively large thickness, and the parasitic capacitance between the gate electrode and the second electrode is relatively small. Furthermore, since the second electrode 34 is close to the first boundary B61, and the distance c41 between the boundary extending along the first direction D1 and the seventh boundary B67 is equal to the distance c42 between the boundary extending along the second direction D2 and the fourth boundary B64 of the third connection portion 333, and is greater than the third alignment deviation threshold, and the distance b4 between the second electrode 34 is close to the third boundary B63, and the boundary extending along the first direction D1 and the fifth boundary B65 is greater than the second alignment deviation threshold, when there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the second direction D2, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate. When there is an alignment deviation between the source / drain conductive layer and the gate insulating layer in the first direction D1, the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode will change. Therefore, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0339] In an exemplary embodiment, as shown in FIG40, there are two transistor devices. The target transistor device is at least partially symmetrical with respect to a straight line extending along the second direction D2, and the second transistor device is at least partially symmetrical with respect to a straight line extending along the first direction D1. The second electrode 34 of the first transistor device and the second electrode 34 of the second transistor device are the same electrode.

[0340] In an exemplary embodiment, the transistor device provided in FIG40 includes two transistor devices shown in FIG41. When the source / drain conductive layer has an alignment deviation relative to the gate insulating layer in the second direction D2, or when the source / drain conductive layer has an alignment deviation relative to the gate insulating layer in the first direction D1, although the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode in the two transistor devices will change, the changes in the thickness of the insulating layer between the gate electrode and the first electrode and the thickness of the insulating layer between the gate electrode and the second electrode in the two transistor devices are complementary, so that the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode do not fluctuate. The transistor device provided in FIG40 occupies a large space.

[0341] In the exemplary embodiment, Figures 22 and 23 are illustrated with an example of a via provided in the second insulating layer. Therefore, the transistor device provided in Figure 22 is fabricated using the same method as the transistor device provided in Figure 23. In the exemplary embodiment, Figures 24 and 25 are illustrated with an example of a via provided in the first insulating layer. Therefore, the transistor device provided in Figure 24 is fabricated using the same method as the transistor device provided in Figure 25.

[0342] The following describes by way of an exemplary fabrication process of the transistor device shown in Figure 22, illustrating the transistor device provided in the embodiments of this disclosure.

[0343] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film using a patterning process to form a gate electrode 31, as shown in FIG41a.

[0344] (2) Forming a first insulating layer. In an exemplary embodiment, forming a gate insulating layer includes depositing a first insulating film on a substrate on which a gate electrode is formed to form a first insulating layer 351, as shown in FIG41b.

[0345] In an exemplary embodiment, a first insulating film is deposited on a substrate on which a gate electrode is formed using a chemical vapor deposition process.

[0346] (3) Forming a primitive semiconductor layer. In an exemplary embodiment, forming a primitive semiconductor layer includes: depositing a semiconductor thin film on a substrate on which a first insulating layer is formed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form a primitive semiconductor layer including a first active layer 321 and a third active layer 323, as shown in FIG41c.

[0347] In an exemplary embodiment, the orthographic projection of the third active layer 323 onto the substrate coincides with the orthographic projection of the surface of the first active layer 321 away from the substrate onto the substrate.

[0348] (4) Forming a second insulating layer. In an exemplary embodiment, forming a second insulating layer includes: depositing a second insulating film on a substrate on which the original semiconductor layer is formed, and patterning the second insulating film by a patterning process to form a second insulating layer 352, as shown in FIG41d.

[0349] In an exemplary embodiment, the second insulating layer 352 is provided with a through-hole VV.

[0350] In this disclosure, when the second insulating film is patterned, the first insulating layer located below the active layer is not affected by the process of forming the second insulating film due to the obstruction of the active layer, thereby improving the reliability of the transistor device.

[0351] (5) Forming a first electrode and a second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a second metal thin film on a substrate on which a second insulating layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process to form a first electrode 33, a fourth electrode 34 and a second active layer 322, as shown in FIG41e.

[0352] (6) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes forming a passivation layer on a substrate on which a first electrode and a second electrode are formed.

[0353] The transistor device provided in the embodiments of this disclosure will be illustrated below by another fabrication process of the transistor device shown in Figure 22.

[0354] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film by a patterning process to form a gate electrode 31, as shown in FIG41a.

[0355] (2) Forming a first insulating layer. In an exemplary embodiment, forming a gate insulating layer includes depositing a first insulating film on a substrate on which a gate electrode is formed to form a first insulating layer 351, as shown in FIG41b.

[0356] In an exemplary embodiment, a first insulating film is deposited on a substrate on which a gate electrode is formed using a chemical vapor deposition process.

[0357] (3) Forming a barrier layer. In an exemplary embodiment, forming a barrier layer includes: depositing a second metal thin film on a substrate on which a first insulating layer is formed, and patterning the second metal thin film by a patterning process to form a barrier layer 36, as shown in FIG42a.

[0358] In an exemplary embodiment, the mask used in the patterning process for forming the barrier layer may be the same mask used in the patterning process for forming the original semiconductor layer.

[0359] (4) Forming a second insulating layer. In an exemplary embodiment, forming a second insulating layer includes: depositing a second insulating film on a substrate on which a barrier layer is formed, and patterning the second insulating film using a patterning process to form a second insulating layer 352, as shown in FIG42b.

[0360] In an exemplary embodiment, the second insulating layer 352 is provided with a through-hole VV.

[0361] In an exemplary embodiment, when the second insulating film is patterned in this disclosure, the first insulating layer located below the barrier layer is not affected by the process of forming the second insulating layer due to the obstruction of the barrier layer, thereby improving the reliability of the transistor device.

[0362] (5) Removing the barrier layer. In an exemplary embodiment, removing the barrier layer includes removing the barrier layer by an etching process, as shown in FIG42c.

[0363] (6) Forming a primitive semiconductor layer. In an exemplary embodiment, forming a primitive semiconductor layer includes: depositing a semiconductor thin film on a substrate with the barrier layer removed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form a primitive semiconductor layer including a first active layer 321 and a third active layer 323, as shown in FIG42d.

[0364] In an exemplary embodiment, the orthographic projection of the third active layer 323 onto the substrate coincides with the orthographic projection of the surface of the first active layer 321 away from the substrate onto the substrate.

[0365] (7) Forming a first electrode and a second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a third metal thin film on a substrate on which a second insulating layer is formed, and patterning the third metal thin film and the third active layer respectively by a patterning process to form a first electrode 33, a fourth electrode 34 and a second active layer 322, as shown in FIG41e.

[0366] (6) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes forming a passivation layer on a substrate on which a first electrode and a second electrode are formed.

[0367] The following describes the transistor device provided in the embodiments of this disclosure by way of the fabrication process of the transistor device shown in Figure 24.

[0368] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film by a patterning process to form a gate electrode 31, as shown in FIG41a.

[0369] (2) Forming a first insulating layer. In an exemplary embodiment, forming a gate insulating layer includes depositing a first insulating film on a substrate on which a gate electrode is formed to form a first insulating layer 351, as shown in FIG43a.

[0370] In an exemplary embodiment, a first insulating film is deposited on a substrate on which a gate electrode is formed using a chemical vapor deposition process.

[0371] In an exemplary embodiment, the first insulating layer 351 is provided with a via VV.

[0372] (3) Forming a second insulating layer. In an exemplary embodiment, forming a second insulating layer includes forming a second insulating layer 352 on a substrate on which a barrier layer is formed, as shown in FIG43b.

[0373] (4) Forming a primitive semiconductor layer. In an exemplary embodiment, forming a primitive semiconductor layer includes: depositing a semiconductor thin film on a substrate on which a second insulating layer is formed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form a primitive semiconductor layer including a first active layer 321 and a third active layer 323, as shown in FIG43c.

[0374] In an exemplary embodiment, the orthographic projection of the third active layer 323 onto the substrate coincides with the orthographic projection of the surface of the first active layer 321 away from the substrate onto the substrate.

[0375] (5) Forming a first electrode and a second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a second metal thin film on a substrate on which a second insulating layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process to form a first electrode 33, a fourth electrode 34 and a second active layer 322, as shown in FIG43d.

[0376] (6) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes forming a passivation layer on a substrate on which a first electrode and a second electrode are formed.

[0377] This disclosure also provides a method for fabricating a transistor device, configured to fabricate the transistor device provided in any of the embodiments shown in Figures 22 to 40. Figure 44 is a schematic flowchart of the method for fabricating the transistor device. As shown in Figure 44, the method for fabricating the transistor device provided in the embodiments of this disclosure may include the following steps:

[0378] Step S1: Form the gate electrode of the transistor device on the substrate.

[0379] Step S2: Form the gate insulating layer and active layer of the transistor device on the gate electrode.

[0380] In an exemplary embodiment, the gate insulating layer includes: a first insulating layer and a second insulating layer stacked on a substrate, wherein one of the first insulating layer and the second insulating layer is provided with a via; the orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

[0381] In one exemplary embodiment, step S2 may include the following steps: forming a first insulating layer on a gate electrode; forming a primary semiconductor layer on the first insulating layer, the primary semiconductor layer including a first active layer and a third active layer; forming a second insulating layer on a substrate on which the primary semiconductor layer is formed, the second insulating layer having a via; forming a first electrode, a second electrode, and an active layer on a substrate on which the second insulating layer is formed, the active layer including a first active layer and a second active layer.

[0382] In another exemplary embodiment, step S2 may include the following steps: forming a first insulating layer on the gate electrode; forming a barrier layer on the first insulating layer; forming a second insulating layer on the barrier layer, wherein the second insulating layer is provided with a via, the via exposing the barrier layer; removing the barrier layer; forming a primary semiconductor layer on the second insulating layer, the primary semiconductor layer including a first active layer and a third active layer; forming a first electrode, a second electrode and an active layer on the primary semiconductor layer, the active layer including a first active layer and a second active layer.

[0383] In another exemplary embodiment, step S2 may include the following steps: forming a first insulating layer on the gate electrode, wherein the first insulating layer is provided with a via; forming a second insulating layer on the first insulating layer; forming a primary semiconductor layer on the second insulating layer, wherein the primary semiconductor layer includes a first active layer and a third active layer; forming a first electrode, a second electrode and an active layer on the primary semiconductor layer, wherein the active layer includes a first active layer and a second active layer.

[0384] Figure 45 is a schematic diagram of the planar structure of the display substrate. As shown in Figure 45, the display substrate includes: a display area AA and a non-display area BB. The display area AA is provided with sub-pixels P arranged in an array, multiple scan lines S and multiple data lines D.

[0385] In an exemplary embodiment, multiple scan lines can extend horizontally and be arranged sequentially vertically, and multiple data lines can extend vertically and be arranged sequentially horizontally. The intersecting scan lines and data lines define multiple regularly arranged sub-pixels.

[0386] In an exemplary embodiment, the display substrate may further include: a gate driving circuit that provides signals to multiple scan lines, and a source driving circuit that provides signals to multiple data lines.

[0387] In an exemplary embodiment, the display substrate may further include a timing controller connected to a gate driving circuit and a source driving circuit. The timing controller can provide grayscale values ​​and control signals of specifications suitable for the source driving circuit to the source driving circuit, and can provide clock signals, scan start signals, etc., of specifications suitable for the gate driving circuit to the gate driving circuit. The source driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data lines. For example, the source driving circuit can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data lines on a pixel-by-pixel basis. The gate driving circuit can generate scan signals to be provided to scan lines by receiving clock signals, scan start signals, etc., from the timing controller. For example, the gate driving circuit can sequentially provide scan signals with on-level pulses to the scan lines. For example, the gate driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal.

[0388] In an exemplary embodiment, the display substrate may include a plurality of pixel units arranged in a matrix. At least one of the plurality of pixel units includes a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. Each of the first, second, and third sub-pixels includes a transistor, a first electrode, and a second electrode. The transistors in the first, second, and third sub-pixels are respectively connected to a scan line and a data line. The transistors are configured to provide a data line signal to the first electrode under the control of the scan line signal.

[0389] In an exemplary embodiment, the first sub-pixel can be a red sub-pixel emitting red light, the second sub-pixel can be a blue sub-pixel emitting blue light, and the third sub-pixel can be a green sub-pixel emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0390] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement.

[0391] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0392] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal, or hexagonal, etc., and this disclosure does not limit it.

[0393] In an exemplary embodiment, the gate drive circuit includes a plurality of cascaded shift registers.

[0394] In an exemplary embodiment, at least one shift register may include: an input sub-circuit, an output sub-circuit, a blanking reset sub-circuit, a display reset sub-circuit, a pull-down control sub-circuit, and a noise reduction sub-circuit.

[0395] Figure 46 is an equivalent circuit diagram of at least one shift register. As shown in Figure 46, the input sub-circuit includes: a first transistor T1; the output sub-circuit includes: a third transistor T3 and a capacitor C; the display reset sub-circuit includes: a second transistor T2; the blanking reset sub-circuit includes: an eighteenth transistor T18 and a nineteenth transistor T19; the pull-down control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13; and the noise reduction sub-circuit includes: a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17.

[0396] As shown in Figure 46, the control electrode and first electrode of the first transistor T1 are electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the pull-up node PU; the control electrode of the second transistor T2 is electrically connected to the reset signal terminal RST, the first electrode of the second transistor T2 is electrically connected to the pull-up node PU, and the second electrode of the second transistor T2 is electrically connected to the third power supply terminal VGL; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the signal output terminal OUT; the control electrode and first electrode of the fourth transistor T4 are electrically connected to the first power supply terminal VDD1, and the second electrode of the fourth transistor T4 is electrically connected to the fifth transistor… The control electrode of transistor T5 is electrically connected to the first electrode of transistor T6; the first electrode of transistor T5 is electrically connected to the first power supply terminal VDD1, and the second electrode of transistor T5 is electrically connected to the first pull-down node PD1; the control electrode of transistor T6 is electrically connected to the pull-up node PU, and the second electrode of transistor T6 is electrically connected to the third power supply terminal VGL; the control electrode of transistor T7 is electrically connected to the pull-up node PU, the first electrode of transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of transistor T7 is electrically connected to the third power supply terminal VGL; the control electrode of transistor T8 is electrically connected to the signal input terminal IN, the first electrode of transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of transistor T8 is electrically connected to... The third power supply terminal VGL is electrically connected; the control electrode and first electrode of the ninth transistor T9 are electrically connected to the second power supply terminal VDD2, and the second electrode of the ninth transistor T9 is electrically connected to the control electrode of the tenth transistor T10 and the first electrode of the eleventh transistor T11, respectively; the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VDD2, and the second electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, and the second electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal VGL; the control electrode of the twelfth transistor T12 is electrically connected to the pull-up node PU, and the first electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2, and the twelfth transistor T12... The second terminal of the thirteenth transistor T13 is electrically connected to the third power supply terminal VGL; the control terminal of the thirteenth transistor T13 is electrically connected to the signal input terminal IN; the first terminal of the thirteenth transistor T13 is electrically connected to the second pull-down node PD2; and the second terminal of the thirteenth transistor T13 is electrically connected to the third power supply terminal VGL. The control terminal of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1; the first terminal of the fourteenth transistor T14 is electrically connected to the pull-up node PU; and the second terminal of the fourteenth transistor T14 is electrically connected to the third power supply terminal VGL. The control terminal of the fifteenth transistor T15 is electrically connected to the second pull-down node PD2; the first terminal of the fifteenth transistor T15 is electrically connected to the pull-up node PU; and the second terminal of the fifteenth transistor T15 is electrically connected to the third power supply terminal VGL.The control electrode of the sixteenth transistor T16 is electrically connected to the first pull-down node PD1, the first electrode of the sixteenth transistor T16 is electrically connected to the signal output terminal OUT, and the second electrode of the sixteenth transistor T16 is electrically connected to the third power supply terminal VGL; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the seventeenth transistor T17 is electrically connected to the signal output terminal OUT, and the second electrode of the sixteenth transistor T16 is electrically connected to the third power supply terminal VGL; the control electrode of the eighteenth transistor T18 is electrically connected to the blanking reset signal terminal TRST, the first electrode of the eighteenth transistor T18 is electrically connected to the pull-up node PU, and the second electrode of the eighteenth transistor T18 is electrically connected to the third power supply terminal VGL; the control electrode of the nineteenth transistor T19 is electrically connected to the blanking reset signal terminal TRST, the first electrode of the nineteenth transistor T19 is electrically connected to the signal output terminal OUT, and the second electrode of the nineteenth transistor T19 is electrically connected to the third power supply terminal VGL; the first plate C1 of capacitor C is electrically connected to the pull-up node PU, and the second plate C2 of capacitor C is electrically connected to the signal output terminal OUT.

[0397] In an exemplary embodiment, the first transistor T1 can be referred to as the input transistor. The third transistor T3 can be referred to as the output transistor.

[0398] In an exemplary embodiment, the signal output terminal of at least one shift register is electrically connected to the reset signal terminal of at least one shift register, and is also electrically connected to the signal input terminal of at least one shift register. Exemplarily, the cascaded signal output terminals of at least one shift register are electrically connected to the reset signal terminal of the preceding shift register and the signal input terminal of the following shift register, respectively.

[0399] In an exemplary embodiment, the operation of the display substrate includes a display phase and a power-off phase. During the power-off phase, the display substrate has an Xon function to promptly release the charge from the pixel units in the display substrate.

[0400] In an exemplary embodiment, the display phase includes multiple display frames, with a silencing period set between adjacent display frames.

[0401] In an exemplary embodiment, in at least one display frame, the signal received at the signal input terminal IN is a single pulse signal.

[0402] In an exemplary embodiment, in at least one display frame, the signal output terminal OUT of at least one level shift register is configured to provide an output cascade signal to the signal input terminal of at least one level shift register and the reset signal terminal of at least one level shift register, and to provide a drive signal to the scan signal line connected to the pixel driving circuit located in the display area.

[0403] In an exemplary embodiment, during the display phase, the signal at the third power supply terminal VGL is a low-level signal.

[0404] In an exemplary embodiment, during the power-off phase, the signal of the third power supply terminal VGL is a high-level signal to pull up the signal of the drive signal output terminal OUT of at least one shift register, thereby discharging the pixel unit. The signal of the third power supply terminal VGL is a low-level signal to pull down the signal of the pull-up node PU to prevent charge accumulation in the pull-up node PU of at least one shift register, so as to ensure that at least one shift register can work normally during the display phase.

[0405] In an exemplary embodiment, during the display phase, the signal at at least one of the first power supply terminal VDD1 and the second power supply terminal VDD2 is a periodic signal.

[0406] In an exemplary embodiment, during the display phase, the signals of the first power supply terminal VDD1 and the second power supply terminal VDD2 are at least partially inverted signals. When the signal of the first power supply terminal VDD1 is a high-level signal, the signal of the second power supply terminal VDD2 is a low-level signal, and when the signal of the second power supply terminal VDD2 is a high-level signal, the signal of the first power supply terminal VDD1 is a low-level signal.

[0407] In an exemplary embodiment, the display frame includes: a first display frame and a second display frame. In at least one first display frame, the signal of the first power terminal VDD1 is a high-level signal and the signal of the second power terminal VDD2 is a low-level signal. In at least one second display frame, the signal of the second power terminal VDD2 is a high-level signal and the signal of the first power terminal VDD1 is a low-level signal.

[0408] In an exemplary embodiment, the TRST signal at the blanking reset terminal is an active level signal during the blanking period and an inactive level signal during the display phase. An active level signal means that the signal terminal is electrically connected to the control electrode of the transistor, causing the transistor connected to the signal terminal to conduct; an inactive level signal means that the signal terminal is electrically connected to the control electrode of the transistor, causing the transistor connected to the signal terminal to disconnect.

[0409] In an exemplary embodiment, the reset signal terminal RST is an active level signal for a portion of at least one display frame.

[0410] In an exemplary embodiment, this disclosure reduces noise in the shift register by alternately changing the first power supply terminal VDD1 and the second power supply terminal VDD2 to high-level signals, which can reduce the stress on at least one transistor in the shift register and thus improve the lifespan of the shift register.

[0411] Figure 47 is a timing diagram of the shift register shown in Figure 46. Figure 47 is illustrated using the example of N-type transistors, from the first transistor T1 to the nineteenth transistor T19. The embodiments provided in this disclosure are further illustrated below through the operation of the shift register shown in Figure 46.

[0412] In the first display frame, the fourth transistor T4 and the fifth transistor T5 are turned on, while the ninth transistor T9, the tenth transistor T10, the fifteenth transistor T15, and the seventeenth transistor T17 are turned off.

[0413] In the first display frame, the operation of at least one shift register includes the following steps:

[0414] In the first stage, P1, the input stage, the signal at the input terminal IN is a high-level signal, while the clock signal terminal CLK and the reset signal terminal RST are low-level signals. The first transistor T1, the eighth transistor T8, and the thirteenth transistor T13 are turned on, and the second transistor T2 is turned off.

[0415] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written to the pull-up node PU. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the low-level signal of the clock signal terminal CLK is written to the signal output terminal OUT. The low-level signal of the third power supply terminal VGL is written to the first pull-down node PD1 and the second pull-down node PD2. The fourteenth transistor T14 and the sixteenth transistor T16 are turned off, and the signal of the pull-up node PU will not be pulled low.

[0416] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a low-level signal.

[0417] In the second stage, P2, the output stage, the clock signal CLK is high, while the signal input IN and reset signal RST are low. Transistors T1, T2, T8, and T13 are disconnected.

[0418] The first transistor T1 is off, so the low-level signal at the signal input terminal IN cannot be written to the pull-up node PU. The voltage value of the signal at the pull-up node PU increases under the bootstrap effect of the capacitor C. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are fully turned on. The high-level signal at the clock signal terminal CLK is written to the signal output terminal OUT. The low-level signal at the third power supply terminal VGL is written to the first pull-down node PD1 and the second pull-down node PD2. The fourteenth transistor T14 and the sixteenth transistor T16 are off, so the signal at the pull-up node PU will not be pulled low.

[0419] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a high-level signal.

[0420] In the third stage, the signals at P3, IN (signal input terminal), CLK (clock signal terminal), and RST (reset signal terminal) are low-level signals. Transistors T1, T2, T8, and T13 are disconnected.

[0421] The signal at the pull-up node PU is a high-level signal. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are continuously turned on. The low-level signal of the clock signal terminal CLK is written to the signal output terminal OUT. The low-level signal of the third power supply terminal VGL is written to the first pull-down node PD1 and the second pull-down node PD2. The fourteenth transistor T14 and the sixteenth transistor T16 are turned off, and the signal at the pull-up node PU will not be pulled low.

[0422] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signals of the signal output terminal OUT and the signal output terminal OUT are low-level signals.

[0423] In the fourth stage, P4, the reset stage, the clock signal terminal CLK and the reset signal terminal RST are high-level signals, while the signal input terminal IN is low-level. The second transistor T2 is turned on, while the first transistor T1, the eighth transistor T8, and the thirteenth transistor T13 are turned off.

[0424] The second transistor T2 is turned on, and the low-level signal of the third power supply terminal VGL is written to the pull-up node PU. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are turned off. The high-level signal of the first power supply terminal VDD1 is written to the first pull-down node PD1. The fourteenth transistor T14 and the sixteenth transistor T16 are turned on, and the low-level signal of the third power supply terminal VGL is written to the pull-up node PU and the signal output terminal OUT.

[0425] During this phase, the signal of the first pull-down node PD1 is a high-level signal, the signals of the pull-up node PU and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a low-level signal.

[0426] In the fifth stage, the signals at P5 and the clock signal terminal CLK are high, while the signals at the signal input terminal IN and the reset signal terminal RST are low. The first transistor T1, the second transistor T2, the eighth transistor T8, and the thirteenth transistor T13 are disconnected.

[0427] Under the influence of capacitor C, the signal at pull-up node PU remains low, and transistors T3, T6, T7, T11, and T12 are disconnected. The high-level signal at the first power supply terminal VDD1 is continuously written to the first pull-down node PD1, while transistors T14 and T16 remain continuously turned on. The low-level signal at the third power supply terminal VGL is written to pull-up node PU and signal output terminal OUT.

[0428] During this phase, the signal of the first pull-down node PD1 is a high-level signal, the signals of the pull-up node PU and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a low-level signal.

[0429] In the sixth stage, the signals at P6, IN (signal input terminal), CLK (clock signal terminal), and RST (reset signal terminal) are all low-level signals. Transistors T1, T2, T8, and T13 are disconnected.

[0430] Under the influence of capacitor C, the signal at pull-up node PU remains low, and transistors T3, T6, T7, T11, and T12 are disconnected. The high-level signal at the first power supply terminal VDD1 is continuously written to the first pull-down node PD1, while transistors T14 and T16 remain continuously turned on. The low-level signal at the third power supply terminal VGL is written to pull-up node PU and signal output terminal OUT.

[0431] During this phase, the signal of the first pull-down node PD1 is a high-level signal, the signals of the pull-up node PU and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a low-level signal.

[0432] The fifth stage (P5) and the sixth stage (P6) occur in a loop until the signal at the signal input terminal IN is a high-level signal.

[0433] In the second display frame, the ninth transistor T9 and the tenth transistor T10 are turned on, while the fourth transistor T4, the fifth transistor T5, the fourteenth transistor T14, and the seventeenth transistor T17 are turned off.

[0434] In the second display frame, the operation of at least one shift register includes the following steps:

[0435] In the first stage, P1, the input stage, the signal at the input terminal IN is a high-level signal, while the clock signal terminal CLK and the reset signal terminal RST are low-level signals. The first transistor T1, the eighth transistor T8, and the thirteenth transistor T13 are turned on, and the second transistor T2 is turned off.

[0436] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written to the pull-up node PU. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the low-level signal of the clock signal terminal CLK is written to the signal output terminal OUT. The low-level signal of the third power supply terminal VGL is written to the first pull-down node PD1 and the second pull-down node PD2. The fifteenth transistor T15 and the seventeenth transistor T17 are turned off, and the signal of the pull-up node PU will not be pulled low.

[0437] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a low-level signal.

[0438] In the second stage, P2, the output stage, the clock signal CLK is high, while the signal input IN and reset signal RST are low. Transistors T1, T2, T8, and T13 are disconnected.

[0439] The first transistor T1 is off, so the low-level signal at the signal input terminal IN cannot be written to the pull-up node PU. The voltage value of the signal at the pull-up node PU increases under the bootstrap effect of the capacitor C. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are fully turned on. The high-level signal at the clock signal terminal CLK is written to the signal output terminal OUT. The low-level signal at the third power supply terminal VGL is written to the first pull-down node PD1 and the second pull-down node PD2. The fifteenth transistor T15 and the seventeenth transistor T17 are off, so the signal at the pull-up node PU will not be pulled low.

[0440] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a high-level signal.

[0441] In the third stage, the signals at P3, IN (signal input terminal), CLK (clock signal terminal), and RST (reset signal terminal) are low-level signals. Transistors T1, T2, T8, and T13 are disconnected.

[0442] The signal at the pull-up node PU is a high-level signal. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are continuously turned on. The low-level signal of the clock signal terminal CLK is written to the signal output terminal OUT. The low-level signal of the third power supply terminal VGL is written to the first pull-down node PD1 and the second pull-down node PD2. The fifteenth transistor T15 and the seventeenth transistor T17 are turned off, and the signal at the pull-up node PU will not be pulled low.

[0443] During this phase, the signal of the pull-up node PU is a high-level signal, the signals of the first pull-down node PD1 and the second pull-down node PD2 are low-level signals, and the signal of the signal output terminal OUT is a low-level signal.

[0444] In the fourth stage, P4, the reset stage, the clock signal terminal CLK and the reset signal terminal RST are high-level signals, while the signal input terminal IN is low-level. The second transistor T2 is turned on, while the first transistor T1, the eighth transistor T8, and the thirteenth transistor T13 are turned off.

[0445] The second transistor T2 is turned on, and the low-level signal of the third power supply terminal VGL is written to the pull-up node PU. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are turned off. The high-level signal of the second power supply terminal VDD2 is written to the second pull-down node PD2, and the fifteenth transistor T15 and the seventeenth transistor T17 are turned on. The low-level signal of the third power supply terminal VGL is written to the pull-up node PU and the signal output terminal OUT.

[0446] During this phase, the signal of the second pull-down node PD2 is a high-level signal, the signals of the pull-up node PU and the first pull-down node PD1 are low-level signals, and the signal output terminal OUT is a low-level signal.

[0447] In the fifth stage, the signals at P5 and the clock signal terminal CLK are high, while the signals at the signal input terminal IN and the reset signal terminal RST are low. The first transistor T1, the second transistor T2, the eighth transistor T8, and the thirteenth transistor T13 are disconnected.

[0448] Under the influence of capacitor C, the signal at pull-up node PU remains low, and transistors T3, T6, T7, T11, and T12 are disconnected. The high-level signal at the second power supply terminal VDD2 is continuously written to the second pull-down node PD2, while transistors T15 and T17 remain on. The low-level signal at the third power supply terminal VGL is written to pull-up node PU and signal output terminal OUT.

[0449] During this phase, the signal of the second pull-down node PD2 is a high-level signal, the signals of the pull-up node PU and the first pull-down node PD1 are low-level signals, and the signal output terminal OUT is a low-level signal.

[0450] In the sixth stage, the signals at P6, IN (signal input terminal), CLK (clock signal terminal), and RST (reset signal terminal) are all low-level signals. Transistors T1, T2, T8, and T13 are disconnected.

[0451] Under the influence of capacitor C, the signal at pull-up node PU remains low, and transistors T3, T6, T7, T11, and T12 are disconnected. The high-level signal at the second power supply terminal VDD2 is continuously written to the second pull-down node PD2, while transistors T15 and T17 remain on. The low-level signal at the third power supply terminal VGL is written to pull-up node PU and signal output terminal OUT.

[0452] During this phase, the signal of the second pull-down node PD2 is a high-level signal, the signals of the pull-up node PU and the first pull-down node PD1 are low-level signals, and the signal output terminal OUT is a low-level signal.

[0453] The fifth stage (P5) and the sixth stage (P6) occur in a loop until the signal at the signal input terminal IN is a high-level signal.

[0454] Figure 48 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. The display substrate provided in Figure 48 includes a shift register as shown in Figure 46. The at least one shift register includes a plurality of transistors. The plurality of transistors includes a first transistor T1 to a nineteenth transistor T19. At least one of the plurality of transistors is a transistor device provided in any of the embodiments in Figures 22 to 40.

[0455] As shown in Figure 48, at least one transistor includes: an input transistor (first transistor T1), which is electrically connected to a signal input terminal and a pull-up node. At least one transistor also includes: an output transistor (third transistor T3), which is electrically connected to a pull-up node, a signal output terminal, and a clock signal terminal.

[0456] In an exemplary embodiment, FIG49 is a schematic diagram of a portion of the film layers in FIG48. As shown in FIG49, the display substrate includes: a substrate and a gate insulating layer disposed on the substrate. The gate insulating layer includes: a first insulating layer and a second insulating layer stacked on the substrate. One of the first insulating layer and the second insulating layer is provided with a first device via VV1. The orthographic projection of the active layer 1-2 of the input transistor (first transistor T1) onto the substrate at least partially overlaps with the orthographic projection of the first device via VV1 onto the substrate.

[0457] In an exemplary embodiment, as shown in FIG49, one of the first insulating layer and the second insulating layer is provided with a second device via VV2. The orthographic projection of the active layer 3-2 of the output transistor (third transistor T3) onto the substrate at least partially overlaps with the orthographic projection of the second device via VV2 onto the substrate.

[0458] In an exemplary embodiment, the first device via VV1 and the second device via VV2 may be disposed on the same insulating layer. Exemplarily, the first device via VV1 and the second device via VV2 may be disposed on the first insulating layer, or the first device via VV1 and the second device via VV2 may be disposed on the second insulating layer.

[0459] In an exemplary embodiment, the input transistor of at least one level shift register drives the signal of the pull-up node, and the output transistor drives the signal of the signal output terminal. Therefore, the display substrate has a large demand for increasing the turn-on current of the input transistor and the output transistor. By setting the input transistor and the output transistor to the transistor devices provided in the aforementioned embodiments, this disclosure can reduce the leakage current of the signal of the pull-up node and the signal output terminal, improve the driving capability of at least one level shift register, and thus improve the reliability of the gate drive circuit.

[0460] In an exemplary embodiment, the transistors of at least one shift register, excluding the input and output transistors, are not sensitive to the turn-on current of the transistor devices. Therefore, the active layers of the transistors of at least one shift register, excluding the input and output transistors, have overlapping gate insulating layers on the substrate, and no device vias need to be provided.

[0461] In an exemplary embodiment, as shown in Figures 48 and 49, at least one shift register further includes a capacitor C, which includes a first plate and a second plate. The orthographic projection of at least one of the substrates of the first and second plates of capacitor C onto the substrate at least partially overlaps with the orthographic projection of the second device via VV2 onto the substrate.

[0462] Since the total amount of charge stored in the capacitor is inversely proportional to the thickness of the insulating layer between the first plate and the second plate, the orthographic projection of at least one of the substrates of the first plate and the second plate of the capacitor C in this disclosure onto the substrate at least partially overlaps with the orthographic projection of the second device via VV2 onto the substrate, which can increase the total amount of charge stored in the capacitor and improve the reliability of the shift register.

[0463] In an exemplary embodiment, the display substrate includes a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes a first conductive layer, a semiconductor layer, and a second conductive layer sequentially stacked on the substrate.

[0464] In an exemplary embodiment, the first conductive layer includes: control electrodes of a plurality of transistors located in at least one level shift register.

[0465] In an exemplary embodiment, the semiconductor layer includes an active layer of a plurality of transistors located in at least one level shift register.

[0466] In an exemplary embodiment, the second conductive layer includes: a first electrode and a second electrode of a plurality of transistors located in at least one level shift register.

[0467] In an exemplary embodiment, as shown in FIG48, the display substrate further includes: a plurality of clock signal lines disposed on the substrate, a first power supply line VDDL1, a second power supply line VDDL2, a third power supply line VGLL, and a total reset signal line TRL. FIG48 is illustrated using an example of a plurality of clock signal lines including: a first clock signal line CLKL1, a second clock signal line CLKL2, a third clock signal line CLKL3, and a fourth clock signal line CLKL4.

[0468] In an exemplary embodiment, at least one of the first and second electrodes of at least one transistor (fourth transistor T4 and fifth transistor T5) in at least one level shift register is electrically connected to a first power supply terminal. At least one of the first and second electrodes of at least one transistor (ninth transistor T9 and tenth transistor T10) in at least one level shift register is electrically connected to a second power supply terminal. The second electrode of at least one transistor (sixth transistor T6, seventh transistor T7, eighth transistor T8, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, sixteenth transistor T16, seventeenth transistor T17, eighteenth transistor T18, and nineteenth transistor T19) in at least one level shift register is electrically connected to a third power supply terminal. The control electrode of at least one transistor (eighteenth transistor T18 and nineteenth transistor T19) in at least one level shift register is electrically connected to the total reset signal line TRL.

[0469] In an exemplary embodiment, at least one of the multiple clock signal lines, the first power line VDDL1, the second power line VDDL2, the third power line VGLL, and the total reset signal line TRL extends at least partially along the third direction D3 and is located in the first conductive layer.

[0470] In an exemplary embodiment, as shown in FIG48, the orthogonal projection of at least one of the multiple clock signal lines, the first power line VDDL1, the second power line VDDL2, and the third power line VGLL onto the substrate is located on the side of the orthogonal projection of the multiple transistors in at least one level shift register away from the display area.

[0471] In an exemplary embodiment, as shown in FIG48, the orthogonal projection of the total reset signal line TRL on the substrate lies between the orthogonal projections of the plurality of transistors on the substrate, and between the orthogonal projections of the output transistors and the input transistors on the substrate. Exemplarily, the orthogonal projection of the total reset signal line TRL on the substrate may lie between the orthogonal projections of at least one of the first transistors T1 to the seventeenth transistor T17 on the substrate and the orthogonal projection of the third transistor T3 on the substrate, and at least partially overlap with the orthogonal projections of at least one of the eighteenth transistor T18 and the nineteenth transistor T19 on the substrate.

[0472] In an exemplary embodiment, as shown in FIG48, the display substrate may further include: multiple cascaded signal lines OUTL, which may be electrically connected to the signal input terminal of at least one level shift register and to the reset signal terminal of at least one level shift register.

[0473] In an exemplary embodiment, as shown in FIG48, at least one of the multiple cascaded signal lines OUTL extends at least partially along the third direction D3 and is located in the first conductive layer.

[0474] In an exemplary embodiment, as shown in FIG48, the orthogonal projection of the plurality of cascaded signal lines OUTL on the substrate lies between the orthogonal projection of at least one of the first transistors T1 to the seventeenth transistor T17 on the substrate and the orthogonal projection of at least one of the eighteenth transistor T18 and the nineteenth transistor T19 on the substrate.

[0475] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0476] The following description uses the example of a second device via being disposed in the second insulating layer. The method for fabricating the display substrate shown in FIG48 further illustrates the display substrate provided in the embodiments of this disclosure.

[0477] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate, and patterning the first conductive thin film using a patterning process to form a first conductive layer pattern. As shown in FIG50, FIG50 is a schematic diagram after the formation of the first conductive layer pattern in FIG48. In an exemplary embodiment, the first conductive layer may be referred to as a gate metal (GATE) layer.

[0478] In an exemplary embodiment, as shown in FIG50, the first conductive layer pattern may include at least: multiple clock signal lines, a first power supply line VDDL1, a second power supply line VDDL2, a third power supply line VGLL, a total reset signal line TRL, and the control electrodes of multiple transistors in at least one shift register and the first plate C1 of a capacitor. The multiple clock signal lines include: a first clock signal line CLKL1, a second clock signal line CLKL2, a third clock signal line CLKL3, and a fourth clock signal line CLKL4. The control electrodes of the multiple transistors include: control electrodes 1-1 of the first transistor to 19-1 of the nineteenth transistor.

[0479] In an exemplary embodiment, as shown in FIG50, multiple clock signal lines, a first power line VDDL1, a second power line VDDL2, and a third power line VGLL are arranged sequentially along a fourth direction D4, and at least one of the multiple clock signal lines, the first power line VDDL1, the second power line VDDL2, and the third power line VGLL extends along a third direction D3.

[0480] In an exemplary embodiment, as shown in FIG50, multiple clock signal lines, a first power line VDDL1, a second power line VDDL2, and a third power line VGLL are located on the side of at least one of the control electrodes of the first transistor 1-1 to the nineteenth transistor 19-1 that is away from the display area.

[0481] In an exemplary embodiment, as shown in FIG50, at least one of the control electrodes of the first transistor 1-1 to the nineteenth transistor 19-1 extends at least partially along the third direction D3.

[0482] In an exemplary embodiment, as shown in FIG50, the first plate C1 of the capacitor is rectangular.

[0483] In an exemplary embodiment, as shown in FIG50, the control electrode 1-1 of the first transistor, the control electrode 8-1 of the eighth transistor, and the control electrode 13-1 of the thirteenth transistor are integrally formed. The control electrode 3-1 of the third transistor and the first plate C1 of the capacitor are integrally formed, and the first plate C1 of the capacitor is located on the side of the control electrode 3-1 of the third transistor away from the display area. The control electrodes 6-1 of the sixth transistor, 7-1 of the seventh transistor, 11-1 of the eleventh transistor, and 12-1 of the twelfth transistor are integrally formed. The control electrodes 14-1 of the fourteenth transistor and 16-1 of the sixteenth transistor are integrally formed. The control electrodes 15-1 of the fifteenth transistor and 17-1 of the seventeenth transistor are integrally formed. The control electrodes 2-1 of the second transistor, 4-1 of the fourth transistor, 5-1 of the fifth transistor, 9-1 of the ninth transistor, and 10-1 of the tenth transistor are individually provided.

[0484] In an exemplary embodiment, as shown in FIG50, the control electrode 18-1 of the eighteenth transistor and the control electrode 19-1 of the nineteenth transistor in at least one level shift register are integrated with the total reset signal line TRL.

[0485] (2) Forming a gate insulating layer pattern. In an exemplary embodiment, forming a gate insulating layer pattern may include: depositing a first insulating film and a second insulating film on the basis of the aforementioned pattern, and patterning the first insulating film and the second insulating film through a patterning process to form a gate insulating layer pattern covering the first conductive layer pattern. As shown in FIG51, FIG51 is a schematic diagram after the gate insulating layer pattern is formed in FIG48. The gate insulating layer includes: a first insulating layer and a second insulating layer.

[0486] In an exemplary embodiment, as shown in FIG23, the plurality of vias in the gate insulating layer pattern include: a first via V1 to a fifteenth via V15. The second insulating layer includes: a first device via VV1 and a second device via VV2.

[0487] In an exemplary embodiment, the orthogonal projection of the first device via VV1 onto the substrate is within the range of the orthogonal projection of the control electrode of the first transistor (which is also the control electrode of the eighth transistor and the control electrode of the thirteenth transistor) onto the substrate, and the first via V1 exposes the surface of the first insulating layer.

[0488] In an exemplary embodiment, the orthogonal projection of the second device via VV2 onto the substrate is within the range of the orthogonal projection of the control electrode of the third transistor (which is also the first plate of the capacitor) onto the substrate, and the second device via VV2 exposes the surface of the first insulating layer.

[0489] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the control electrode of the first transistor (which is also the control electrode of the eighth transistor and the control electrode of the thirteenth transistor) onto the substrate. The first via V1 exposes the surface of the control electrode of the first transistor (which is also the control electrode of the eighth transistor and the control electrode of the thirteenth transistor). The first via V1 is configured to allow the first electrode of the subsequently formed first transistor to be connected to the control electrode of the first transistor through the via.

[0490] In an exemplary embodiment, the orthogonal projection of the second via V2 onto the substrate is within the range of the orthogonal projection of the control electrode of the second transistor onto the substrate. The second via V2 exposes the surface of the control electrode of the second transistor. The second via V2 is configured to connect a subsequently formed connection electrode to the control electrode of the second transistor.

[0491] In an exemplary embodiment, the orthogonal projection of the third via V3 onto the substrate is within the range of the orthogonal projection of the control electrode of the third transistor (which is also the first plate of the capacitor) onto the substrate. The third via V3 exposes the surface of the control electrode of the third transistor (which is also the first plate of the capacitor). The third via V3 is configured to allow the second electrode of the subsequently formed first transistor (the first electrode of the second transistor, the first electrode of the fifteenth transistor, and the first electrode of the eighteenth transistor) to be connected to the control electrode of the third transistor (which is also the first plate of the capacitor) through the via.

[0492] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is within the range of the orthographic projection of the control electrode of the fourth transistor on the substrate. The fourth via V4 exposes the surface of the control electrode of the fourth transistor. The fourth via V4 is configured to allow the first electrode of the subsequently formed fourth transistor (which is also the first electrode of the fifth transistor) to be connected to the control electrode of the fourth transistor through the via.

[0493] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate is within the range of the orthogonal projection of the control electrode of the fifth transistor onto the substrate. The fifth via V5 exposes the surface of the control electrode of the fifth transistor. The fifth via V5 is configured to allow the second electrode of the subsequently formed fourth transistor (which is also the first electrode of the sixth transistor) to be connected to the control electrode of the fifth transistor through the via.

[0494] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the substrate lies within the range of the orthogonal projection of the control electrode of the sixth transistor (which is also the control electrode of the seventh transistor, the eleventh transistor, and the twelfth transistor) onto the substrate. The sixth via V6 exposes the surface of the control electrode of the sixth transistor (which is also the control electrode of the seventh transistor, the eleventh transistor, and the twelfth transistor). The sixth via V6 is configured to allow the second electrode of the subsequently formed first transistor (the first electrode of the second transistor, the first electrode of the fifteenth transistor, and the first electrode of the eighteenth transistor) to be connected to the control electrode of the sixth transistor (which is also the control electrode of the seventh transistor, the eleventh transistor, and the twelfth transistor) through the via.

[0495] In an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate is within the range of the orthogonal projection of the control electrode of the ninth transistor onto the substrate. The seventh via V7 exposes the surface of the control electrode of the ninth transistor. The seventh via V7 is configured to allow the first electrode of the subsequently formed ninth transistor (which is also the first electrode of the tenth transistor) to be connected to the control electrode of the ninth transistor through the via.

[0496] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the control electrode of the tenth transistor on the substrate. The eighth via V8 exposes the surface of the control electrode of the tenth transistor. The eighth via V8 is configured to allow the second electrode of the subsequently formed ninth transistor (which is also the first electrode of the eleventh transistor) to be connected to the control electrode of the tenth transistor through the via.

[0497] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the range of the orthogonal projection of the control electrode of the fourteenth transistor (which is also the control electrode of the sixteenth transistor) onto the substrate. The ninth via V9 exposes the surface of the control electrode of the fourteenth transistor (which is also the control electrode of the sixteenth transistor). The ninth via V9 is configured to allow the second electrode of the subsequently formed fifth transistor (which is also the first electrode of the seventh transistor and the first electrode of the eighth transistor) to be connected to the control electrode of the fourteenth transistor (which is also the control electrode of the sixteenth transistor) through the via.

[0498] In an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the substrate lies within the orthogonal projection of the control electrode of the fifteenth transistor (which is also the control electrode of the seventeenth transistor) onto the substrate. The tenth via V10 exposes the surface of the control electrode of the fifteenth transistor (which is also the control electrode of the seventeenth transistor). The tenth via V10 is configured to allow the second electrode of the subsequently formed tenth transistor (which is also the first electrode of the twelfth transistor and the first electrode of the thirteenth transistor) to be connected to the control electrode of the fifteenth transistor (which is also the control electrode of the seventeenth transistor) through the via.

[0499] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of at least one cascaded signal line onto the substrate. The eleventh via V11 exposes the surface of at least one cascaded signal line. The eleventh via V11 is configured to allow the first electrode of the subsequently formed first transistor, the second electrode of the third transistor (which is also the second plate of the capacitor, the first electrode of the sixteenth transistor, the first electrode of the seventeenth transistor, and the first electrode of the eighteenth transistor), and the connection electrode to be connected to at least one cascaded signal line through the via.

[0500] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the range of the orthographic projection of at least one clock signal line onto the substrate. The twelfth via V12 exposes the surface of at least one clock signal line. The twelfth via V12 is configured to allow the first electrode of a subsequently formed third transistor to be connected to at least one clock signal line through the via.

[0501] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the first power line on the substrate. The thirteenth via V13 exposes the surface of the first power line. The thirteenth via V13 is configured to allow the first terminal of the subsequently formed fourth transistor (which is also the first terminal of the fifth transistor) to be connected to the first power line through the via.

[0502] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the second power line on the substrate. The fourteenth via V14 exposes the surface of the second power line. The fourteenth via V14 is configured to allow the first terminal of the subsequently formed ninth transistor (which is also the first terminal of the tenth transistor) to be connected to the second power line through the via.

[0503] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the third power line on the substrate. The fifteenth via V15 exposes the surface of the third power line. The fifteenth via V15 is configured to allow the second terminal of the subsequently formed second transistor (which is also the second terminal of the sixth transistor, the second terminal of the seventh transistor, the second terminal of the eighth transistor, the second terminal of the eleventh transistor, the second terminal of the twelfth transistor, the second terminal of the thirteenth transistor, the second terminal of the fourteenth transistor, the second terminal of the fifteenth transistor, the second terminal of the sixteenth transistor, the second terminal of the seventeenth transistor, the second terminal of the eighteenth transistor, and the second terminal of the nineteenth transistor) to be connected to the third power line through the via.

[0504] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a semiconductor thin film on the basis of the aforementioned pattern, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern on the gate insulating layer. As shown in Figures 52 and 53, Figure 52 is a schematic diagram of the semiconductor layer pattern in Figure 48, and Figure 53 is a schematic diagram of the semiconductor layer pattern after it has been formed in Figure 48.

[0505] In an exemplary embodiment, as shown in Figures 52 and 53, the semiconductor layer pattern may include at least: active layers 1-2 of the first transistor to active layers 19-2 of the nineteenth transistor located in at least one level shift register.

[0506] In an exemplary embodiment, the active layers 1-2 of the first transistor to the active layer 19-2 of the nineteenth transistor are individually disposed. At least one of the active layers 1-2 of the first transistor to the active layer 19-2 of the nineteenth transistor extends at least partially along a third direction D3.

[0507] In an exemplary embodiment, the length of the active layer 3-2 of the third transistor along the fourth direction D4 is greater than the length of the active layer of at least one transistor other than the third transistor along the fourth direction D4.

[0508] In an exemplary embodiment, the length of the active layer 1-2 of the first transistor along the fourth direction D4 is greater than the length of the active layer of at least one transistor other than the first transistor and the third transistor along the fourth direction D4.

[0509] In an exemplary embodiment, the active layer 1-2 of the first transistor is disposed on the control electrode of the first transistor, the active layer 2-2 of the second transistor is disposed on the control electrode of the second transistor, the active layer 3-2 of the third transistor is disposed on the control electrode of the third transistor, the active layer 4-2 of the fourth transistor is disposed on the control electrode of the fourth transistor, the active layer 5-2 of the fifth transistor is disposed on the control electrode of the fifth transistor, the active layer 6-2 of the sixth transistor is disposed on the control electrode of the sixth transistor, the active layer 7-2 of the seventh transistor is disposed on the control electrode of the seventh transistor, the active layer 8-2 of the eighth transistor is disposed on the control electrode of the eighth transistor, the active layer 9-2 of the ninth transistor is disposed on the control electrode of the ninth transistor, and the active layer 10-2 of the tenth transistor is disposed on the control electrode of the tenth transistor. On the control electrode, the active layer 11-2 of the eleventh transistor is disposed on the control electrode of the eleventh transistor, the active layer 12-2 of the twelfth transistor is disposed on the control electrode of the twelfth transistor, the active layer 13-2 of the thirteenth transistor is disposed on the control electrode of the thirteenth transistor, the active layer 14-2 of the fourteenth transistor is disposed on the control electrode of the fourteenth transistor, the active layer 15-2 of the fifteenth transistor is disposed on the control electrode of the fifteenth transistor, the active layer 16-2 of the sixteenth transistor is disposed on the control electrode of the sixteenth transistor, the active layer 17-2 of the seventeenth transistor is disposed on the control electrode of the seventeenth transistor, the active layer 18-2 of the eighteenth transistor is disposed on the control electrode of the eighteenth transistor, and the control electrode 19-2 of the nineteenth transistor is disposed on the control electrode of the nineteenth transistor.

[0510] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the second conductive thin film using a patterning process to form a second conductive layer pattern disposed on the semiconductor layer pattern, as shown in Figures 54 and 55. Figure 54 is a schematic diagram of the second conductive layer pattern in Figure 48, and Figure 55 is a schematic diagram of the second conductive layer pattern after it has been formed in Figure 48. In an exemplary embodiment, the second conductive layer may be referred to as a source / drain metal (SD) layer.

[0511] In an exemplary embodiment, as shown in Figures 54 and 55, the second conductive layer pattern may include at least: the first pole 1-3 and the second pole 1-4 of the first transistor located in at least one level shift register to the first pole 19-3 and the second pole 19-4 of the nineteenth transistor, a second plate C2, and a connecting portion CL.

[0512] In an exemplary embodiment, the first electrode 13 of the first transistor is provided separately. The first electrode 13 of the first transistor is connected to the control electrode of the first transistor through a first via, and is connected to at least one cascaded signal line through an eleventh via.

[0513] In an exemplary embodiment, the second electrode 1-4 of the first transistor, the first electrode 2-3 of the second transistor, the first electrode 14-3 of the fourteenth transistor, the first electrode 15-2 of the fifteenth transistor, and the first electrode 18-3 of the eighteenth transistor are integrally formed. The second electrode 1-4 of the first transistor (which is also the first electrode 2-3 of the second transistor, the first electrode 14-3 of the fourteenth transistor, the first electrode 15-2 of the fifteenth transistor, and the first electrode 18-3 of the eighteenth transistor) is connected to the control electrode of the third transistor (which is also the first electrode plate of the capacitor) through a third via, and is connected to the control electrode of the sixth transistor (which is also the control electrode of the seventh transistor, the eleventh transistor, and the twelfth transistor) through a sixth via.

[0514] In an exemplary embodiment, the second electrode 2-4 of the second transistor is integrally structured with the second electrodes 6-4 of the sixth transistor, 7-4 of the seventh transistor, 8-4 of the eighth transistor, 11-4 of the eleventh transistor, 12-4 of the twelfth transistor, 13-4 of the thirteenth transistor, 14-4 of the fourteenth transistor, 15-4 of the fifteenth transistor, 16-4 of the sixteenth transistor, 17-4 of the seventeenth transistor, 18-4 of the eighteenth transistor, and 19-4 of the nineteenth transistor. The second terminal 2-4 of the second transistor (also the second terminal 6-4 of the sixth transistor, the second terminal 7-4 of the seventh transistor, the second terminal 8-4 of the eighth transistor, the second terminal 11-4 of the eleventh transistor, the second terminal 12-4 of the twelfth transistor, the second terminal 13-4 of the thirteenth transistor, the second terminal 14-4 of the fourteenth transistor, the second terminal 15-4 of the fifteenth transistor, the second terminal 16-4 of the sixteenth transistor, the second terminal 17-4 of the seventeenth transistor, the second terminal 18-4 of the eighteenth transistor, and the second terminal 19-4 of the nineteenth transistor) is connected to the third power line through the fifteenth via.

[0515] In an exemplary embodiment, the first electrode 3-3 of the third transistor is provided separately. The first electrode 3-3 of the third transistor is connected to at least one clock signal line through a twelfth via.

[0516] In an exemplary embodiment, the second terminal 3-4 of the third transistor, the second plate C2 of the capacitor, the first terminal 16-3 of the sixteenth transistor, the first terminal 17-3 of the seventeenth transistor, and the first terminal 18-3 of the eighteenth transistor are integrally formed. The second terminal 3-4 of the third transistor (which is also the second plate C2 of the capacitor, the first terminal 16-3 of the sixteenth transistor, the first terminal 17-3 of the seventeenth transistor, and the first terminal 18-3 of the eighteenth transistor) is electrically connected to at least one cascaded signal line through an eleventh via.

[0517] In an exemplary embodiment, the first electrode 4-3 of the fourth transistor and the first electrode 5-3 of the fifth transistor are integrated. The first electrode 4-3 of the fourth transistor (which is also the first electrode 5-3 of the fifth transistor) is connected to the control electrode of the fourth transistor through a fourth via and to the first power line through a thirteenth via.

[0518] In an exemplary embodiment, the second electrode 4-4 of the fourth transistor and the first electrode 6-3 of the sixth transistor are integrated. The second electrode 4-4 of the fourth transistor (which is also the first electrode 6-3 of the sixth transistor) is connected to the control electrode of the fifth transistor through a fifth via and to the first power line through a thirteenth via.

[0519] In an exemplary embodiment, the second electrode 5-4 of the fifth transistor, the first electrode 7-3 of the seventh transistor, and the first electrode 8-3 of the eighth transistor are integrally formed. The second electrode 5-4 of the fifth transistor (which is also the first electrode 7-3 of the seventh transistor and the first electrode 8-3 of the eighth transistor) is connected to the control electrode of the fourteenth transistor (which is also the control electrode of the sixteenth transistor) through a ninth via.

[0520] In an exemplary embodiment, the first electrode 9-3 of the ninth transistor and the first electrode 10-3 of the tenth transistor are integrated. The first electrode 9-3 of the ninth transistor (which is also the first electrode 10-3 of the tenth transistor) is connected to the control electrode of the ninth transistor through a seventh via and to the second power line through a fourteenth via.

[0521] In an exemplary embodiment, the second electrode 9-4 of the ninth transistor and the first electrode 11-3 of the eleventh transistor are integrated. The second electrode 9-4 of the ninth transistor (which is also the first electrode 11-3 of the eleventh transistor) is connected to the control electrode of the tenth transistor through an eighth via.

[0522] In an exemplary embodiment, the second terminal 10-4 of the tenth transistor, the first terminal 12-3 of the twelfth transistor, and the first terminal 13-3 of the thirteenth transistor are integrally formed. The second terminal 10-4 of the tenth transistor (which is also the first terminal 12-3 of the twelfth transistor and the first terminal 13-3 of the thirteenth transistor) is connected to the control terminal of the fifteenth transistor (which is also the control terminal of the seventeenth transistor) through a tenth via.

[0523] In an exemplary embodiment, the connection electrode CL is provided separately. The connection electrode CL is electrically connected to the control electrode of the second transistor through a second via, and the connection electrode CL is electrically connected to at least one cascaded signal line through an eleventh via.

[0524] At this point, the circuit structure layer on the substrate is complete. In a plane parallel to the display substrate, the circuit structure layer may include multiple shift registers. In a plane perpendicular to the display substrate, the circuit structure layer may be disposed on the substrate.

[0525] In an exemplary embodiment, Figures 50 to 55 illustrate an example where device vias are disposed in a second insulating layer, and the second insulating layer is formed before the semiconductor layer. Exemplarily, the device vias are disposed in the second insulating layer, which is also formed after the semiconductor layer. In this case, before forming the semiconductor layer, the process includes: forming a first insulating layer; after forming the semiconductor layer, the second insulating layer can be formed; the second insulating layer has device vias disposed therein; and the first and second insulating layers have first to fifteenth vias. Exemplarily, the device vias can also be disposed in the first insulating layer. In this case, before forming the semiconductor layer, the process includes: forming a first insulating layer; the first insulating layer has device vias disposed therein; forming a second insulating layer; and the first and second insulating layers have first to fifteenth vias. This will not be elaborated further in this disclosure.

[0526] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and metal sheets; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0527] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0528] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer or a polycrystalline silicon layer, or it can be a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0529] In an exemplary embodiment, the first conductive layer and the second conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo.

[0530] In an exemplary embodiment, the first insulating layer and the second insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers.

[0531] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0532] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0533] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A transistor device disposed on a substrate, the transistor device comprising: The device comprises a gate electrode, a gate insulating layer, and an active layer, wherein the gate electrode is located on the side of the gate insulating layer closer to the substrate, and the active layer is located on the side of the gate insulating layer away from the substrate. The gate insulating layer includes a first insulating layer and a second insulating layer stacked on the substrate, wherein one of the first insulating layer and the second insulating layer is provided with a via. The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

2. The transistor device according to claim 1, wherein, The orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the via on the substrate, or the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate.

3. The transistor device according to claim 2, further comprising: A first electrode and a second electrode are disposed on the side of the active layer away from the substrate; When the orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the via on the substrate, the minimum distance between the orthographic projection of at least one boundary of at least one of the first electrode and the second electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the active layer extending along the first direction on the substrate is greater than a first alignment deviation threshold.

4. The transistor device according to claim 3, wherein, At least a portion of the first electrode is U-shaped, the first electrode includes an opening facing the second electrode, and the first electrode partially surrounds the second electrode, the second electrode extending at least a portion along a first direction.

5. The transistor device according to claim 4, wherein, The orthographic projection of the first electrode on the substrate is within the range of the orthographic projection of the active layer on the substrate. The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate, and there is a non-overlapping region with the orthographic projection of the gate electrode on the substrate.

6. The transistor device according to claim 5, wherein, When the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a plurality of boundaries, the plurality of boundaries including: a first boundary, the first boundary extending along a second direction, the first direction intersecting the second direction; The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of at least one boundary of the via, excluding the first boundary, on the substrate; the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first boundary of the via on the substrate. The distance between the orthographic projection of at least one boundary of the first electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the via extending along the first direction (excluding the first boundary) on the substrate is greater than the second alignment deviation threshold.

7. The transistor device according to claim 6, wherein, The number of transistor devices is two, and the first transistor device and the second transistor device are arranged at least partially symmetrically with respect to a straight line extending along the second direction; The second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

8. The transistor device according to claim 4, wherein, When the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the first electrode includes: a first branch segment, a second branch segment, and a connecting segment. The first branch segment and the second branch segment are respectively connected to the connecting segment. The first branch segment and the second branch segment extend along a first direction, and the connecting segment extends along a second direction. At least one of the first branch segment and the second branch segment overlaps at least partially with the orthographic projection of the via on the substrate, and the orthographic projection of the connecting segment on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate.

9. The transistor device according to claim 8, wherein, The via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary, wherein the first boundary and the second boundary extend along a second direction and are disposed opposite to each other, and the third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other; The orthographic projection of the first branch segment on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary, the second boundary, and the third boundary on the substrate; the orthographic projection of the second branch segment on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary, the second boundary, and the fourth boundary on the substrate; and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary and the second boundary on the substrate.

10. The transistor device according to claim 9, wherein, The distance between the boundary of at least one of the first branch segment and the second branch segment away from the boundary of the connecting segment and the first boundary is the first distance, and the distance between the boundary of the second electrode near the boundary of the connecting segment and the second boundary is the second distance; The first distance is equal to the second distance, and at least one of the first distance and the second distance is greater than the third alignment deviation threshold; The distance between the orthographic projection of the first boundary on the substrate and the orthographic projection of the connecting segment on the substrate is greater than the distance between the orthographic projection of the second boundary on the substrate and the orthographic projection of the connecting segment on the substrate.

11. The transistor device according to claim 3, wherein, At least one of the first electrode and the second electrode extends along a first direction; The orthographic projection of at least one of the first electrode and the second electrode onto the substrate at least partially overlaps with the orthographic projection of the active layer onto the substrate, and there is a non-overlapping region with the orthographic projection of the gate electrode onto the substrate.

12. The transistor device according to claim 11, wherein, When the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a second direction and are disposed opposite to each other. The third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other. The length of at least one of the first boundary and the second boundary is less than the length of at least one of the third boundary and the fourth boundary. The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of at least one of the second boundary and the third boundary on the substrate, and there is no overlap with the orthographic projection of at least one of the first boundary and the fourth boundary on the substrate; the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of at least one of the first boundary and the fourth boundary on the substrate, and there is no overlap with the orthographic projection of at least one of the second boundary and the third boundary on the substrate.

13. The transistor device according to claim 11, wherein, When the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a second direction and are disposed opposite to each other. The third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other. The length of at least one of the first boundary and the second boundary is greater than or equal to the length of at least one of the third boundary and the fourth boundary. The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projections of at least one of the first boundary, the second boundary, and the third boundary on the substrate, and the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projections of at least one of the first boundary, the second boundary, and the fourth boundary on the substrate.

14. The transistor device of claim 11, wherein, When the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a second direction and are disposed opposite to each other. The third boundary and the fourth boundary extend along a first direction and are disposed opposite to each other. The length of at least one of the first boundary and the second boundary is greater than the length of at least one of the third boundary and the fourth boundary. The orthographic projection of at least one of the first and second electrodes on the substrate at least partially overlaps with the orthographic projection of at least one of the first and second boundaries on the substrate, and there is no overlap with the orthographic projection of at least one of the third and fourth boundaries on the substrate.

15. The transistor device according to claim 11, wherein, The via includes: multiple boundaries, including: a first boundary and a second boundary, wherein the first boundary and the second boundary extend along a second direction and are disposed opposite to each other; The orthographic projection of the first electrode on the substrate at least partially overlaps with the orthographic projection of the first boundary on the substrate, and there is no overlap with the orthographic projections of the other boundaries on the substrate except for the first boundary. The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the second boundary on the substrate, and there is no overlap with the orthographic projections of the other boundaries on the substrate except for the second boundary.

16. The transistor device according to any one of claims 13, 14 and 15, wherein, The distance between the orthographic projection of the target boundary of the first electrode on the substrate and the orthographic projection of the second boundary on the substrate is equal to the distance between the orthographic projection of the target boundary of the second electrode on the substrate and the orthographic projection of the first boundary on the substrate, and is greater than the third alignment deviation. At least one of the first electrode and the second electrode overlaps with the orthographic projection of the gate electrode on the substrate, and the boundary extending along the second direction is the target boundary. The distance between the orthographic projection of the target boundary of the first electrode on the substrate and the orthographic projection of the second boundary on the substrate is less than the distance between the orthographic projection of the target boundary of the first electrode on the substrate and the orthographic projection of the first boundary on the substrate. The distance between the orthographic projection of the target boundary of the second electrode on the substrate and the orthographic projection of the first boundary on the substrate is greater than the distance between the orthographic projection of the target boundary of the second electrode on the substrate and the orthographic projection of the first boundary on the substrate.

17. The transistor device according to claim 12 or 14, wherein, The minimum distance between the orthographic projection of the boundary of the first electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the via extending along the first direction on the substrate is equal to the minimum distance between the orthographic projection of the boundary of the second electrode extending along the first direction on the substrate and the orthographic projection of at least one boundary of the via extending along the first direction on the substrate, and is greater than the second alignment deviation threshold.

18. The transistor device according to claim 3, wherein, The second electrode extends along the first direction; The first electrode includes: a first connecting portion, a second connecting portion, a third connecting portion, and a fourth connecting portion; the first connecting portion and the fourth connecting portion extend along a second direction, and the third connecting portion extends along a first direction; the second connecting portion is connected to the first connecting portion and the third connecting portion respectively, and is disposed at an obtuse angle to the first connecting portion and the third connecting portion respectively; the first connecting portion, the second connecting portion, and the third connecting portion at least partially surround the second electrode; the fourth connecting portion is connected to the third connecting portion and is located on the side of the third connecting portion away from at least one of the first connecting portion and the second connecting portion. The orthographic projection of at least one of the second and third connecting portions on the substrate is within the range of the orthographic projection of the active layer on the substrate. The orthographic projections of the first connecting portion, the fourth connecting portion, and the second electrode on the substrate at least partially overlap with the orthographic projection of the active layer on the substrate, and there is a non-overlapping region with the orthographic projection of the gate electrode on the substrate.

19. The transistor device according to claim 18, wherein, When the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, the orthographic projections of the second connection portion and the third connection portion on the substrate are within the range of the orthographic projection of the via on the substrate. The via includes multiple boundaries, wherein the orthographic projection of at least one of the structures of the second electrode, the first connection portion, and the fourth connection portion onto the substrate at least partially overlaps with the orthographic projection of at least one of the multiple boundaries of the via onto the substrate.

20. The transistor device of claim 18, wherein, The via includes: a first boundary, a second boundary, a third boundary, a fourth boundary, a fifth boundary, a sixth boundary, and a seventh boundary; the first boundary, the fourth boundary, and the sixth boundary extend along a second direction, and the third boundary, the fifth boundary, and the seventh boundary extend along a first direction, and the first boundary to the seventh boundary are connected sequentially; The second boundary is set at an obtuse angle to the first boundary and the third boundary, the third boundary is set at a right angle to the fourth boundary, the fourth boundary is set at a right angle to the fifth boundary, the fifth boundary is set at a right angle to the sixth boundary, the sixth boundary is set at a right angle to the seventh boundary, the seventh boundary is set at a right angle to the first boundary, and the distance between the sixth boundary and the first boundary is less than the distance between the fourth boundary and the first boundary; The orthographic projection of the first boundary on the substrate is within the range of the orthographic projection of the first connecting portion on the substrate, the orthographic projection of the second boundary on the substrate is within the range of the orthographic projection of the second connecting portion on the substrate, the orthographic projection of the third connecting portion on the substrate at least partially overlaps with the orthographic projection of the third boundary on the substrate, and the length of the third connecting portion is less than the length of the third boundary, and the orthographic projection of the fourth connecting portion on the substrate does not overlap with the orthographic projection of at least one of the first boundary to the seventh boundary on the substrate. The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projections of the fourth boundary and the sixth boundary on the substrate, and covers the orthographic projection of the fifth boundary on the substrate; The second electrode is close to the third boundary, and the distance between the boundary extending along the first direction and the fifth boundary is greater than the second alignment deviation threshold. The distance between the second electrode near the first boundary and the boundary extending along the first direction and the seventh boundary is equal to the distance between the third connection near the fourth boundary and the boundary extending along the second direction and the fourth boundary, and is greater than the third alignment deviation threshold.

21. The transistor device according to claim 20, wherein, The number of transistor devices is two, and the target transistor device is at least partially symmetrical with respect to the straight line extending along the second direction with respect to the first direction. The second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

22. The transistor device according to claim 2, wherein, The active layer includes: a first active layer and a second active layer, wherein the second active layer is disposed on the side of the first active layer away from the substrate, and the second active layer includes: a first active structure and a second active structure; The orthographic projection of the second active layer on the substrate is within the range of the orthographic projection of the first active layer on the substrate, the orthographic projection of the first active structure on the substrate is within the range of the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second active structure on the substrate is within the range of the orthographic projection of the second electrode on the substrate. The thickness of the first active layer is greater than the thickness of the second active layer, and the conductivity of the second active layer is greater than that of the first active layer. At least one of the first electrode and the second electrode covers at least a portion of the sidewalls of the first active layer and the second active layer, as well as the surface of the second active layer away from the substrate; The orthographic projection of at least one of the first electrode and the second electrode onto the substrate at least partially overlaps with the orthographic projection of the insulating layer on the substrate having the via.

23. The transistor device according to claim 2, wherein, The maximum distance between the surface of the gate insulating layer away from the substrate and the surface of the gate electrode away from the substrate is in the range of 3800 angstroms to 4200 angstroms; The first insulating layer is made of one of silicon oxide and silicon nitride, and the second insulating layer is made of the other of silicon oxide and silicon nitride.

24. A display substrate, comprising: A display area and a non-display area disposed on at least one side of the display area, the non-display area being provided with a gate driving circuit, the gate driving circuit comprising: a plurality of cascaded shift registers, at least one of the shift registers comprising: a plurality of transistors, at least one of the plurality of transistors being a transistor device as described in any one of claims 1 to 23.

25. The display substrate according to claim 24, wherein, The display substrate includes: a substrate and a gate insulating layer disposed on the substrate. The gate insulating layer includes: a first insulating layer and a second insulating layer stacked on the substrate. One of the first insulating layer and the second insulating layer is provided with a first device via. At least one transistor includes: an input transistor, the input transistor being electrically connected to a signal input terminal and a pull-up node, respectively; The orthographic projection of the active layer of the input transistor onto the substrate at least partially overlaps with the orthographic projection of the first device via onto the substrate.

26. The display substrate according to claim 24, wherein, The display substrate includes: a substrate and a gate insulating layer disposed on the substrate. The gate insulating layer includes: a first insulating layer and a second insulating layer stacked on the substrate. One of the first insulating layer and the second insulating layer is provided with a second device via. At least one shift register includes an output transistor, which is electrically connected to a pull-up node, a signal output terminal, and a clock signal terminal, respectively. The orthographic projection of the active layer of the output transistor onto the substrate at least partially overlaps with the orthographic projection of the second device via onto the substrate.

27. The display substrate according to claim 26, wherein, At least one shift register also includes: a capacitor, which includes a first plate and a second plate; The orthographic projection of at least one of the first and second plates of the capacitor onto the substrate at least partially overlaps with the orthographic projection of the via of the second device onto the substrate.

28. The display substrate according to claim 24, wherein, The display substrate includes: a substrate and a circuit structure layer disposed on the substrate, the circuit structure layer including: a first conductive layer, a semiconductor layer and a second conductive layer sequentially stacked on the substrate; The first conductive layer includes: control electrodes of a plurality of transistors located in at least one level shift register; The semiconductor layer includes: an active layer of multiple transistors located in at least one level shift register; The second conductive layer includes: a first electrode and a second electrode of a plurality of transistors located in at least one level shift register.

29. The display substrate according to claim 28, further comprising: Multiple clock signal lines, a first power line, a second power line, a third power line, and a total reset signal line are disposed on a substrate; at least one of the multiple clock signal lines, the first power line, the second power line, the third power line, and the total reset signal line extends at least partially along a third direction and is located in the first conductive layer; At least one of the first and second electrodes of at least one transistor in at least one level shift register is electrically connected to a first power supply terminal; at least one of the first and second electrodes of at least one transistor in at least one level shift register is electrically connected to a second power supply terminal; the second electrode of at least one transistor in at least one level shift register is electrically connected to a third power supply terminal; and the control electrode of at least one transistor in at least one level shift register is electrically connected to the total reset signal line. The clock signal terminal in at least one level shift register is electrically connected to one of the multiple clock signal lines, the clock signal terminals in adjacent shift registers are connected to different clock signal lines, the first power supply terminal in at least one level shift register is electrically connected to the first power supply terminal, the second power supply terminal in at least one level shift register is electrically connected to the second power supply terminal, and the total reset signal terminal in at least one level shift register is electrically connected to the total reset signal line. Multiple transistors include: input transistors and output transistors; The orthographic projection of at least one of the multiple clock signal lines, the first power supply line, the second power supply line, and the third power supply line on the substrate is located on the side of the orthographic projection of multiple transistors on the substrate in at least one level shift register that is far from the display area. The orthographic projection of the total reset signal line on the substrate is located between the orthographic projections of multiple transistors on the substrate, and between the orthographic projections of the output transistor on the substrate and the orthographic projections of the input transistor on the substrate.

30. A method for fabricating a transistor device, configured to fabricate the transistor device as described in any one of claims 1 to 23, the method comprising: The gate electrode of a transistor device is formed on the substrate; A gate insulating layer and an active layer of a transistor device are formed on the gate electrode. The gate insulating layer includes a first insulating layer and a second insulating layer stacked on the substrate, wherein one of the first insulating layer and the second insulating layer is provided with a via. The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

31. The method according to claim 30, wherein, The formation of the gate insulating layer and active layer of the transistor device on the gate electrode includes: A first insulating layer is formed on the gate electrode; A primary semiconductor layer is formed on the first insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer; A second insulating layer is formed on a substrate on which the original semiconductor layer is formed, and the second insulating layer is provided with vias; A first electrode, a second electrode, and an active layer are formed on a substrate having a second insulating layer, wherein the active layer comprises a first active layer and a second active layer.

32. The method according to claim 30, wherein, The formation of the gate insulating layer and active layer of the transistor device on the gate electrode includes: A first insulating layer is formed on the gate electrode; A barrier layer is formed on the first insulating layer; A second insulating layer is formed on the barrier layer, and the second insulating layer is provided with a via, the via exposing the barrier layer; Remove the blocking layer; A primary semiconductor layer is formed on the second insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer; A first electrode, a second electrode, and an active layer are formed on the original semiconductor layer. The active layer includes a first active layer and a second active layer.

33. The method according to claim 30, wherein, The formation of the gate insulating layer and active layer of the transistor device on the gate electrode includes: A first insulating layer is formed on the gate electrode, and the first insulating layer has a via. A second insulating layer is formed from the first insulating layer; A primary semiconductor layer is formed on the second insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer; A first electrode, a second electrode, and an active layer are formed on the original semiconductor layer. The active layer includes a first active layer and a second active layer.

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